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authorMartin Roth <gaumless@gmail.com>2022-11-03 18:40:10 -0600
committerMartin L Roth <gaumless@gmail.com>2022-11-12 22:52:54 +0000
commit9a8667a841f14af61f50a3fba4e0734f24ff24b2 (patch)
treedf0f9ec0fbc42b8263284ed577c87b85cb483775 /src
parent898176a24c5bdde896a47bf60966d1476b4f913f (diff)
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device & commonlib: Update pci_scan_bus postcodes
The function pci_scan_bus had 3 post codes in it: 0x24 - beginning 0x25 - middle 0x55 - end I got rid of the middle postcode and used 0x25 for the code signifying the end of the function. I don't think all three are needed. 0x24 & 0x25 postcodes are currently also used in intel cache-as-ram code. Those postcodes should be adjusted to avoid conflicting. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I19c9d5e256505b64234919a99f73a71efbbfdae3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/commonlib/include/commonlib/console/post_codes.h14
-rw-r--r--src/device/pci_device.c6
2 files changed, 16 insertions, 4 deletions
diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h
index 8ab069bf1c1f..d838815fa214 100644
--- a/src/commonlib/include/commonlib/console/post_codes.h
+++ b/src/commonlib/include/commonlib/console/post_codes.h
@@ -66,6 +66,20 @@
#define POST_ENTRY_C_START 0x13
/**
+ * \brief Entry into pci_scan_bus
+ *
+ * Entered pci_scan_bus()
+ */
+#define POST_ENTER_PCI_SCAN_BUS 0x24
+
+/**
+ * \brief Entry into pci_scan_bus
+ *
+ * Entered pci_scan_bus()
+ */
+#define POST_EXIT_PCI_SCAN_BUS 0x25
+
+/**
* \brief Pre-memory init preparation start
*
* Post code emitted in romstage before making callbacks to allow SoC/mainboard
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 16c31ea221ac..865158644c77 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -1423,7 +1423,7 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn,
max_devfn=0xff;
}
- post_code(0x24);
+ post_code(POST_ENTER_PCI_SCAN_BUS);
if (pci_bus_only_one_child(bus))
max_devfn = MIN(max_devfn, 0x07);
@@ -1464,8 +1464,6 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn,
}
}
- post_code(0x25);
-
/*
* Warn if any leftover static devices are found.
* There's probably a problem in devicetree.cb.
@@ -1516,7 +1514,7 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn,
* side of any bridges that may be on this bus plus any devices.
* Return how far we've got finding sub-buses.
*/
- post_code(0x55);
+ post_code(POST_EXIT_PCI_SCAN_BUS);
}
typedef enum {