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| author | Subrata Banik <subratabanik@google.com> | 2022-10-12 14:24:41 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-27 00:33:42 +0000 |
| commit | a00db94270f87a82dbe8d83f05f53dbefd0e5a64 (patch) | |
| tree | 16cd54dade5aac9f925ed5eed2f30d22c8d5040e /src | |
| parent | bd12700be8c370b13264bb917a187a4700b30e5a (diff) | |
| download | coreboot-a00db94270f87a82dbe8d83f05f53dbefd0e5a64.tar.gz coreboot-a00db94270f87a82dbe8d83f05f53dbefd0e5a64.tar.bz2 coreboot-a00db94270f87a82dbe8d83f05f53dbefd0e5a64.zip | |
soc/intel/{adl, cmn}: Allow config to select the OCP workaround
This patch introduces a config option for SoC code to choose
the applicable SoC workaround.
For now, we have introduced `SOC_INTEL_UFS_OCP_TIMER_DISABLE`
to apply UFS OCP timeout disable workaround.
At present ADL SoC only selects so, and in future MTL and others
should check with Intel prior selecting this kconfig.
It's the placeholder to add more workaround in required going forward.
BUG=none
TEST=Able to build and boot Google/Brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68309
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 7 | ||||
| -rw-r--r-- | src/soc/intel/common/block/acpi/Kconfig | 7 | ||||
| -rw-r--r-- | src/soc/intel/common/block/acpi/acpi/ufs.asl | 4 |
3 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 92a8c06840cf..fe7b3a229b0a 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -425,6 +425,13 @@ config ACPI_ADL_IPU_ES_SUPPORT help Enables ACPI entry to provide silicon type information to IPU kernel driver. +config ALDERLAKE_ENABLE_SOC_WORKAROUND + bool + default y + select SOC_INTEL_UFS_OCP_TIMER_DISABLE + help + Selects the workarounds applicable for Alder Lake SoC. + choice prompt "Multiprocessor (MP) Initialization configuration to use" default USE_FSP_MP_INIT diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index e21584c07322..2b102bca426f 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -49,4 +49,11 @@ config SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID help Defines hybrid CPU specific ACPI helper functions. +config SOC_INTEL_UFS_OCP_TIMER_DISABLE + bool + help + OCP Timer need to be disabled in SCS UFS IOSF Bridge to + work around the Silicon Issue due to which LTR mechanism + doesn't work. + endif diff --git a/src/soc/intel/common/block/acpi/acpi/ufs.asl b/src/soc/intel/common/block/acpi/acpi/ufs.asl index 41c14d786377..f7cb9f336e64 100644 --- a/src/soc/intel/common/block/acpi/acpi/ufs.asl +++ b/src/soc/intel/common/block/acpi/acpi/ufs.asl @@ -67,8 +67,10 @@ Scope (\_SB.PCI0) /* Set BIT[1:0] = 00b - Power State D0 */ PSTA &= 0xFFFFFFFC +#if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE) /* Disable OCP Timer in SCS UFS IOSF Bridge */ OCPD () +#endif } Method (_PS3, 0, Serialized) @@ -79,7 +81,9 @@ Scope (\_SB.PCI0) Method (_INI) { +#if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE) OCPD () +#endif } } } |