diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-10 23:44:50 +0300 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-12 17:24:00 +0000 |
commit | a257efcfcc0c637b9e79fd0ddb958dae85f89a0b (patch) | |
tree | 69e5916045046f0ed627b9a170e0d7930ed9508a /src | |
parent | b7959b592191fab82824e1b7ed29aa7e2299ed33 (diff) | |
download | coreboot-a257efcfcc0c637b9e79fd0ddb958dae85f89a0b.tar.gz coreboot-a257efcfcc0c637b9e79fd0ddb958dae85f89a0b.tar.bz2 coreboot-a257efcfcc0c637b9e79fd0ddb958dae85f89a0b.zip |
AGESA boards: Clean up Ids.h and Filecode.h includes
Change-Id: I9cb63ff58900a39d7cd8e3da2b9a9a95c2a41a69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
78 files changed, 0 insertions, 128 deletions
diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index 4f66fad616c3..f14365ce6642 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -19,7 +19,6 @@ #include "amdlib.h" #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/pi/00660F01/chip.h> -#include "Ids.h" #include "FchPlatform.h" #include "cbfs.h" #include "imc.h" diff --git a/src/mainboard/amd/bettong/OemCustomize.c b/src/mainboard/amd/bettong/OemCustomize.c index 8d1ad4bdb528..f26bf474ddf4 100644 --- a/src/mainboard/amd/bettong/OemCustomize.c +++ b/src/mainboard/amd/bettong/OemCustomize.c @@ -17,7 +17,6 @@ #include <PlatformMemoryConfiguration.h> #include <boardid.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { /* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 3, ...) */ diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c index ceb295e5e410..71d3bd2dfc09 100644 --- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c +++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c @@ -18,7 +18,6 @@ #include "amdlib.h" #include <northbridge/amd/agesa/BiosCallOuts.h> #include <device/azalia.h> -#include "Ids.h" #include "FchPlatform.h" #include "cbfs.h" #include "imc.h" diff --git a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c index bffe88896a8b..278d4974d0d3 100644 --- a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c +++ b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c @@ -17,7 +17,6 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <PlatformMemoryConfiguration.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { /* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */ diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c index e4ec12e4e148..d7cffd153f6a 100644 --- a/src/mainboard/amd/dinar/BiosCallOuts.c +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -17,7 +17,6 @@ #include "amdlib.h" #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include "Ids.h" #include "SB700.h" #include "OEM.h" /* SMBUS0_BASE_ADDRESS */ #include <stdlib.h> diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c index e237ff0b790e..071b146e8283 100644 --- a/src/mainboard/amd/dinar/buildOpts.c +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -24,8 +24,6 @@ */ #include <stdlib.h> #include "AGESA.h" -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE //#define OPTION_HW_DQS_REC_EN_TRAINING TRUE /* AGESA will check the OEM configuration during preprocessing stage, * coreboot enable -Wundef option, so we should make sure we have all contanstand defined diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c index affda6fd76d1..d1d2b864f5f1 100644 --- a/src/mainboard/amd/dinar/gpio.c +++ b/src/mainboard/amd/dinar/gpio.c @@ -13,12 +13,10 @@ * GNU General Public License for more details. */ -#include "Filecode.h" #include "Hudson-2.h" #include "AmdSbLib.h" #include "gpio.h" -#define FILECODE UNASSIGNED_FILE_FILECODE #ifndef SB_GPIO_REG01 #define SB_GPIO_REG01 1 diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c index e570e1e43dbe..7171b4c6ac03 100644 --- a/src/mainboard/amd/inagua/OemCustomize.c +++ b/src/mainboard/amd/inagua/OemCustomize.c @@ -20,7 +20,6 @@ #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> -#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /*---------------------------------------------------------------------------------------*/ /** diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 1c5c424fddd6..cc7d1efe0590 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -26,8 +26,6 @@ */ #include <stdlib.h> -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c index 88e529999e77..4eda8d570d70 100644 --- a/src/mainboard/amd/lamar/BiosCallOuts.c +++ b/src/mainboard/amd/lamar/BiosCallOuts.c @@ -16,7 +16,6 @@ #include "AGESA.h" #include "amdlib.h" #include <northbridge/amd/agesa/BiosCallOuts.h> -#include "Ids.h" #include "FchPlatform.h" #include "cbfs.h" #include "imc.h" diff --git a/src/mainboard/amd/lamar/OemCustomize.c b/src/mainboard/amd/lamar/OemCustomize.c index e2c9a6993a66..32f8c23a8196 100644 --- a/src/mainboard/amd/lamar/OemCustomize.c +++ b/src/mainboard/amd/lamar/OemCustomize.c @@ -16,7 +16,6 @@ #include <northbridge/amd/pi/agesawrapper.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index ad81edf1526d..e56f552baaab 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -17,7 +17,6 @@ #include "amdlib.h" #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> -#include "Ids.h" #include "FchPlatform.h" #include "cbfs.h" #include "imc.h" diff --git a/src/mainboard/amd/olivehill/OemCustomize.c b/src/mainboard/amd/olivehill/OemCustomize.c index b0aa33ba28c1..d8171adb7b54 100644 --- a/src/mainboard/amd/olivehill/OemCustomize.c +++ b/src/mainboard/amd/olivehill/OemCustomize.c @@ -15,14 +15,11 @@ #include "AGESA.h" #include "amdlib.h" -#include "Ids.h" #include "heapManager.h" #include <PlatformMemoryConfiguration.h> -#include "Filecode.h" #include <northbridge/amd/agesa/state_machine.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { { diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 1d3fe778b06b..b4afa304700a 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -27,8 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE #define INSTALL_FT3_SOCKET_SUPPORT TRUE #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c index 49bc40224d6d..c6ed492adc69 100644 --- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c +++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c @@ -16,7 +16,6 @@ #include "AGESA.h" #include "amdlib.h" #include <northbridge/amd/agesa/BiosCallOuts.h> -#include "Ids.h" #include "FchPlatform.h" #include "cbfs.h" #include "imc.h" diff --git a/src/mainboard/amd/olivehillplus/OemCustomize.c b/src/mainboard/amd/olivehillplus/OemCustomize.c index ac60c420821d..0511653e1ac2 100644 --- a/src/mainboard/amd/olivehillplus/OemCustomize.c +++ b/src/mainboard/amd/olivehillplus/OemCustomize.c @@ -15,7 +15,6 @@ #include <northbridge/amd/pi/agesawrapper.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { /* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */ diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index dd7c6dd4b613..7a10ad98881d 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -17,7 +17,6 @@ #include "amdlib.h" #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> -#include "Ids.h" #include "FchPlatform.h" #include "cbfs.h" #include "imc.h" diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c index c16e6d96bbf4..494215f0fe10 100644 --- a/src/mainboard/amd/parmer/OemCustomize.c +++ b/src/mainboard/amd/parmer/OemCustomize.c @@ -15,14 +15,11 @@ #include "AGESA.h" #include "amdlib.h" -#include "Ids.h" #include "heapManager.h" #include <PlatformMemoryConfiguration.h> -#include "Filecode.h" #include <northbridge/amd/agesa/state_machine.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE /* * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 49a9feb7a9c3..795112ca9741 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -27,8 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c index c0dceff5af00..e048e6c92edd 100644 --- a/src/mainboard/amd/persimmon/OemCustomize.c +++ b/src/mainboard/amd/persimmon/OemCustomize.c @@ -20,7 +20,6 @@ #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> -#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /** * OemCustomizeInitEarly diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 670010d4c915..3fed0edeb757 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -26,8 +26,6 @@ */ #include <stdlib.h> -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c index a631eb076242..1f5297aedb62 100644 --- a/src/mainboard/amd/south_station/OemCustomize.c +++ b/src/mainboard/amd/south_station/OemCustomize.c @@ -20,7 +20,6 @@ #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> -#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /*---------------------------------------------------------------------------------------*/ /** diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 38a272d6d7e9..542d5b6f5b34 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -26,8 +26,6 @@ */ #include <stdlib.h> -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 3ab174c609c1..f161e3867a76 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -17,7 +17,6 @@ #include "amdlib.h" #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> -#include "Ids.h" #include "FchPlatform.h" #include "cbfs.h" #include "imc.h" diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c index 3f2563b60661..f91bf2ab00e1 100644 --- a/src/mainboard/amd/thatcher/OemCustomize.c +++ b/src/mainboard/amd/thatcher/OemCustomize.c @@ -15,14 +15,11 @@ #include "AGESA.h" #include "amdlib.h" -#include "Ids.h" #include "heapManager.h" #include <PlatformMemoryConfiguration.h> -#include "Filecode.h" #include <northbridge/amd/agesa/state_machine.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE /* * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 7bc5a7789cdd..2f0b7ca37f51 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -27,8 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index 38206ff4a24b..3e3d2520e2ed 100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -16,7 +16,6 @@ #include "AGESA.h" #include "amdlib.h" #include <northbridge/amd/agesa/BiosCallOuts.h> -#include "Ids.h" #include "Hudson-2.h" #include <stdlib.h> #include <southbridge/amd/cimx/sb700/gpio_oem.h> diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c index 8dc5affb6307..196e8bbaa432 100644 --- a/src/mainboard/amd/torpedo/OemCustomize.c +++ b/src/mainboard/amd/torpedo/OemCustomize.c @@ -21,7 +21,6 @@ #include <PlatformMemoryConfiguration.h> #include "amdlib.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c index 656102d0159e..07850d60df3f 100644 --- a/src/mainboard/amd/torpedo/buildOpts.c +++ b/src/mainboard/amd/torpedo/buildOpts.c @@ -27,8 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index 03ab409a6c97..5a77dc0de016 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -13,12 +13,10 @@ * GNU General Public License for more details. */ -#include "Filecode.h" #include "SbPlatform.h" #include "gpio.h" #include "vendorcode/amd/cimx/sb900/AmdSbLib.h" -#define FILECODE UNASSIGNED_FILE_FILECODE #ifndef SB_GPIO_REG01 #define SB_GPIO_REG01 1 diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c index 00db12c88e09..6f9b3b49f4f1 100644 --- a/src/mainboard/amd/union_station/OemCustomize.c +++ b/src/mainboard/amd/union_station/OemCustomize.c @@ -15,16 +15,13 @@ #include "AGESA.h" #include "amdlib.h" -#include "Ids.h" #include "heapManager.h" #include <PlatformMemoryConfiguration.h> #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" #include <string.h> #include <northbridge/amd/agesa/state_machine.h> -#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /*---------------------------------------------------------------------------------------*/ /** diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 38a272d6d7e9..542d5b6f5b34 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -26,8 +26,6 @@ */ #include <stdlib.h> -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ diff --git a/src/mainboard/asrock/e350m1/OemCustomize.c b/src/mainboard/asrock/e350m1/OemCustomize.c index 892e1c4f92f4..f48559ee88e0 100644 --- a/src/mainboard/asrock/e350m1/OemCustomize.c +++ b/src/mainboard/asrock/e350m1/OemCustomize.c @@ -15,16 +15,13 @@ #include "AGESA.h" #include "amdlib.h" -#include "Ids.h" #include "heapManager.h" #include <PlatformMemoryConfiguration.h> #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" #include <string.h> #include <northbridge/amd/agesa/state_machine.h> -#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /*---------------------------------------------------------------------------------------*/ /** diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index bdda82e1f485..e1058bea9863 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -27,8 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c index b2e6e42d9ec1..6f3b696a896b 100644 --- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c +++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c @@ -18,7 +18,6 @@ #include "amdlib.h" #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> -#include "Ids.h" #include "FchPlatform.h" #include "cbfs.h" #include <stdlib.h> diff --git a/src/mainboard/asrock/imb-a180/OemCustomize.c b/src/mainboard/asrock/imb-a180/OemCustomize.c index 7cb8d5656c54..0b09024384fe 100644 --- a/src/mainboard/asrock/imb-a180/OemCustomize.c +++ b/src/mainboard/asrock/imb-a180/OemCustomize.c @@ -15,14 +15,11 @@ #include "AGESA.h" #include "amdlib.h" -#include "Ids.h" #include "heapManager.h" #include <PlatformMemoryConfiguration.h> -#include "Filecode.h" #include <northbridge/amd/agesa/state_machine.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { { diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 07431e3c01de..a2b04cade566 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -27,8 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE #define INSTALL_FT3_SOCKET_SUPPORT TRUE #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c index 6f4aa8235379..316a110991af 100644 --- a/src/mainboard/asus/f2a85-m/OemCustomize.c +++ b/src/mainboard/asus/f2a85-m/OemCustomize.c @@ -21,7 +21,6 @@ #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE /* * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index ab9e1510e7ca..42e91dd5b458 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -41,7 +41,6 @@ #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index cb9f981c47d8..af618d44a611 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -17,7 +17,6 @@ #include "amdlib.h" #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> -#include "Ids.h" #include "FchPlatform.h" #include "cbfs.h" #include "imc.h" diff --git a/src/mainboard/bap/ode_e20XX/OemCustomize.c b/src/mainboard/bap/ode_e20XX/OemCustomize.c index 00d51b6b2750..8c59201c974a 100644 --- a/src/mainboard/bap/ode_e20XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e20XX/OemCustomize.c @@ -15,14 +15,11 @@ #include "AGESA.h" #include "amdlib.h" -#include "Ids.h" #include "heapManager.h" #include <PlatformMemoryConfiguration.h> -#include "Filecode.h" #include <northbridge/amd/agesa/state_machine.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { /* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device Number 2, Function 4) */ diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index b8f717f4b72e..44e4a750ec85 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -27,8 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE #define INSTALL_FT3_SOCKET_SUPPORT TRUE #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 10015123d4a9..64ee78575af8 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -16,7 +16,6 @@ #include "AGESA.h" #include "amdlib.h" #include <northbridge/amd/agesa/BiosCallOuts.h> -#include "Ids.h" #include "FchPlatform.h" #include "cbfs.h" #include "imc.h" diff --git a/src/mainboard/bap/ode_e21XX/OemCustomize.c b/src/mainboard/bap/ode_e21XX/OemCustomize.c index 3750ba430573..e97ad48db207 100644 --- a/src/mainboard/bap/ode_e21XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e21XX/OemCustomize.c @@ -15,7 +15,6 @@ #include <northbridge/amd/pi/agesawrapper.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { /* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device 2, Function 4) */ diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c index 3cdd7274e210..4c58d930c2f4 100644 --- a/src/mainboard/biostar/am1ml/BiosCallOuts.c +++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c @@ -19,7 +19,6 @@ #include "amdlib.h" #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> -#include "Ids.h" #include "FchPlatform.h" #include "cbfs.h" #include <stdlib.h> diff --git a/src/mainboard/biostar/am1ml/OemCustomize.c b/src/mainboard/biostar/am1ml/OemCustomize.c index 2fa9719368d0..42cf079087c6 100644 --- a/src/mainboard/biostar/am1ml/OemCustomize.c +++ b/src/mainboard/biostar/am1ml/OemCustomize.c @@ -15,14 +15,11 @@ #include "AGESA.h" #include "amdlib.h" -#include "Ids.h" #include "heapManager.h" #include <PlatformMemoryConfiguration.h> -#include "Filecode.h" #include <northbridge/amd/agesa/state_machine.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { { diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 404935b19f9d..334975727a9a 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -27,8 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE #define INSTALL_FT3_SOCKET_SUPPORT TRUE #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c index c0dceff5af00..e048e6c92edd 100644 --- a/src/mainboard/elmex/pcm205400/OemCustomize.c +++ b/src/mainboard/elmex/pcm205400/OemCustomize.c @@ -20,7 +20,6 @@ #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> -#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /** * OemCustomizeInitEarly diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index eb6cf33fa432..a90ee7990535 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -26,8 +26,6 @@ */ #include <stdlib.h> -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the cpu family. */ diff --git a/src/mainboard/gizmosphere/gizmo/OemCustomize.c b/src/mainboard/gizmosphere/gizmo/OemCustomize.c index 173f7f99918d..2d8a893a31c6 100644 --- a/src/mainboard/gizmosphere/gizmo/OemCustomize.c +++ b/src/mainboard/gizmosphere/gizmo/OemCustomize.c @@ -16,7 +16,6 @@ #include "AGESA.h" #include "amdlib.h" -#include "Ids.h" #include "heapManager.h" #include <PlatformMemoryConfiguration.h> #include "PlatformGnbPcieComplex.h" diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index d891875aa992..618679d63be3 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -28,8 +28,6 @@ #include <stdlib.h> -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ diff --git a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c index 4fb762374572..e6bc68e032be 100644 --- a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c @@ -17,7 +17,6 @@ #include "amdlib.h" #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> -#include "Ids.h" #include "FchPlatform.h" #include "cbfs.h" #include "imc.h" diff --git a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c index 2f25a89cc7d9..b5a8173209c5 100644 --- a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c +++ b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c @@ -15,14 +15,11 @@ #include "AGESA.h" #include "amdlib.h" -#include "Ids.h" #include "heapManager.h" #include <PlatformMemoryConfiguration.h> -#include "Filecode.h" #include <northbridge/amd/agesa/state_machine.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { { diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index b8f717f4b72e..44e4a750ec85 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -27,8 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE #define INSTALL_FT3_SOCKET_SUPPORT TRUE #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE diff --git a/src/mainboard/hp/abm/BiosCallOuts.c b/src/mainboard/hp/abm/BiosCallOuts.c index 785fb96ffdd1..8c08052ee463 100644 --- a/src/mainboard/hp/abm/BiosCallOuts.c +++ b/src/mainboard/hp/abm/BiosCallOuts.c @@ -18,7 +18,6 @@ #include "amdlib.h" #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> -#include "Ids.h" #include "FchPlatform.h" #include "cbfs.h" #include <stdlib.h> diff --git a/src/mainboard/hp/abm/OemCustomize.c b/src/mainboard/hp/abm/OemCustomize.c index 4eab307c98f2..63e69ccf7166 100644 --- a/src/mainboard/hp/abm/OemCustomize.c +++ b/src/mainboard/hp/abm/OemCustomize.c @@ -16,14 +16,11 @@ #include "AGESA.h" #include "amdlib.h" -#include "Ids.h" #include "heapManager.h" #include <PlatformMemoryConfiguration.h> -#include "Filecode.h" #include <northbridge/amd/agesa/state_machine.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { { diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 2f31c5e8040e..f217cfc00b47 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -32,8 +32,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE #define INSTALL_FT3_SOCKET_SUPPORT TRUE #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c index d5a0b51b8198..cb6e80fd4f48 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c @@ -21,7 +21,6 @@ #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE /* * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 709c81f00f41..1ab96bf65b54 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -43,7 +43,6 @@ #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c index cccb78c4db45..6b039f7e602f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c +++ b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c @@ -21,7 +21,6 @@ #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> -#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /** * OemCustomizeInitEarly diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 390d28ba79cd..8512afb43f89 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -41,7 +41,6 @@ #include <vendorcode/amd/agesa/f14/Proc/Mem/mm.h> #include <vendorcode/amd/agesa/f14/Proc/Mem/mn.h> -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c index d5a0b51b8198..cb6e80fd4f48 100644 --- a/src/mainboard/lenovo/g505s/OemCustomize.c +++ b/src/mainboard/lenovo/g505s/OemCustomize.c @@ -21,7 +21,6 @@ #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE /* * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 80b91ba4a856..e4365d94419e 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -43,7 +43,6 @@ #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE diff --git a/src/mainboard/lippert/frontrunner-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/OemCustomize.c index 80f568f437e9..aaaec7f62d22 100644 --- a/src/mainboard/lippert/frontrunner-af/OemCustomize.c +++ b/src/mainboard/lippert/frontrunner-af/OemCustomize.c @@ -15,16 +15,13 @@ #include "AGESA.h" #include "amdlib.h" -#include "Ids.h" #include "heapManager.h" #include <PlatformMemoryConfiguration.h> #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" #include <string.h> #include <northbridge/amd/agesa/state_machine.h> -#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /*---------------------------------------------------------------------------------------*/ /** diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index 30982b513418..3a3ab7482bbd 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -27,8 +27,6 @@ #include <stdlib.h> -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ diff --git a/src/mainboard/lippert/toucan-af/OemCustomize.c b/src/mainboard/lippert/toucan-af/OemCustomize.c index 0bb725e899eb..cf68ee40c9e0 100644 --- a/src/mainboard/lippert/toucan-af/OemCustomize.c +++ b/src/mainboard/lippert/toucan-af/OemCustomize.c @@ -15,16 +15,13 @@ #include "AGESA.h" #include "amdlib.h" -#include "Ids.h" #include "heapManager.h" #include <PlatformMemoryConfiguration.h> #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" #include <string.h> #include <northbridge/amd/agesa/state_machine.h> -#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /*---------------------------------------------------------------------------------------*/ /** diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index 30982b513418..3a3ab7482bbd 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -27,8 +27,6 @@ #include <stdlib.h> -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c index d527792621a4..a5e2a4c5b487 100644 --- a/src/mainboard/msi/ms7721/OemCustomize.c +++ b/src/mainboard/msi/ms7721/OemCustomize.c @@ -22,7 +22,6 @@ #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE /* * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index 5191574fef36..87fc20f9ee5a 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -41,7 +41,6 @@ #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index 798b38517ef6..36b4145945e7 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -26,8 +26,6 @@ */ #include <stdlib.h> -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the CPU family. */ diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 1dc0e1cbc3bb..dca6b442a5fa 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -17,8 +17,6 @@ #include "amdlib.h" #include <spd_bin.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include "Ids.h" -#include "OptionsIds.h" #include "FchPlatform.h" #include "cbfs.h" #include "gpio_ftns.h" diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index ea494a492e1f..3c28ac5011f1 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -15,7 +15,6 @@ #include <northbridge/amd/pi/agesawrapper.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { { diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index 9b742cb5ad4a..d8b98b54e1fb 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -17,7 +17,6 @@ #include "amdlib.h" #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include "Ids.h" #include <arch/io.h> #ifdef __PRE_RAM__ diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c index e93e83e91487..0b39b9cd0758 100644 --- a/src/mainboard/supermicro/h8qgi/buildOpts.c +++ b/src/mainboard/supermicro/h8qgi/buildOpts.c @@ -17,8 +17,6 @@ #include "AGESA.h" #include "AdvancedApi.h" -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* AGESA will check the OEM configuration during preprocessing stage, * coreboot enable -Wundef option, so we should make sure we have all contanstand defined diff --git a/src/mainboard/supermicro/h8scm/BiosCallOuts.c b/src/mainboard/supermicro/h8scm/BiosCallOuts.c index 30c1198c7a47..6fb9724e3a6d 100644 --- a/src/mainboard/supermicro/h8scm/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8scm/BiosCallOuts.c @@ -17,7 +17,6 @@ #include "amdlib.h" #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include "Ids.h" #include <stdlib.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = diff --git a/src/mainboard/supermicro/h8scm/buildOpts.c b/src/mainboard/supermicro/h8scm/buildOpts.c index ec2dca08c314..313aee36a9c7 100644 --- a/src/mainboard/supermicro/h8scm/buildOpts.c +++ b/src/mainboard/supermicro/h8scm/buildOpts.c @@ -17,8 +17,6 @@ #include "AGESA.h" #include "AdvancedApi.h" -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE //#define OPTION_HW_DQS_REC_EN_TRAINING TRUE /* AGESA will check the OEM configuration during preprocessing stage, * coreboot enable -Wundef option, so we should make sure we have all contanstand defined diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c index b7d263d44b1b..6cddad242cf4 100644 --- a/src/mainboard/tyan/s8226/BiosCallOuts.c +++ b/src/mainboard/tyan/s8226/BiosCallOuts.c @@ -17,7 +17,6 @@ #include "amdlib.h" #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include "Ids.h" #include <arch/io.h> #include <stdlib.h> diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c index 7c5ea5a34a57..7a3afa92629e 100644 --- a/src/mainboard/tyan/s8226/buildOpts.c +++ b/src/mainboard/tyan/s8226/buildOpts.c @@ -17,8 +17,6 @@ #include "AGESA.h" #include "AdvancedApi.h" -#include "Filecode.h" -#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* AGESA will check the OEM configuration during preprocessing stage, * coreboot enable -Wundef option, so we should make sure we have all contanstand defined |