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| author | Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> | 2023-07-24 03:06:50 +0000 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-07-28 14:22:55 +0000 |
| commit | aae52ef4b35a9dd2b27c2fe28083dee4e87e8d05 (patch) | |
| tree | 25834c96a1ca59240fdfb12de3ad840b15817037 /src | |
| parent | f4e3f15b44f0d0e117781d194f700cc19b3a88c7 (diff) | |
| download | coreboot-aae52ef4b35a9dd2b27c2fe28083dee4e87e8d05.tar.gz coreboot-aae52ef4b35a9dd2b27c2fe28083dee4e87e8d05.tar.bz2 coreboot-aae52ef4b35a9dd2b27c2fe28083dee4e87e8d05.zip | |
mb/google/nissa/var/gothrax: Tune SX9324 P-sensor configuration
Update SX9324 register settings based on tuning value from SEMTECH.
－ Enable GPP_B5/GPP_B6
－ Enable GPP_H19 open irq
－ Adjust register reg_afe_ctrl0/reg_afe_ctrl3/reg_afe_ctrl4
BUG=b:292016304
BRANCH=None
TEST=Check register settings and confirm P-sensor function can work.
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I6f15f7a7c428aee45d35830574ef84aefcae6401
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76711
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/gothrax/gpio.c | 7 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/gothrax/overridetree.cb | 8 |
2 files changed, 6 insertions, 9 deletions
diff --git a/src/mainboard/google/brya/variants/gothrax/gpio.c b/src/mainboard/google/brya/variants/gothrax/gpio.c index ab3b641f8c51..0bf1b52ddb49 100644 --- a/src/mainboard/google/brya/variants/gothrax/gpio.c +++ b/src/mainboard/google/brya/variants/gothrax/gpio.c @@ -21,11 +21,6 @@ static const struct pad_config override_gpio_table[] = { /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */ PAD_CFG_GPO(GPP_A22, 1, DEEP), - /* B5 : SOC_I2C_SUB_SDA */ - PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), - /* B6 : SOC_I2C_SUB_SCL */ - PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), - /* C1 : SMBDATA ==> TCHSCR_RST_L */ PAD_CFG_GPO(GPP_C1, 1, DEEP), @@ -36,6 +31,8 @@ static const struct pad_config override_gpio_table[] = { /* D16 : EN_PP1800_PP1200_WCAM_X */ PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), /* H22 : WCAM_MCLK_R */ PAD_NC(GPP_H22, NONE), }; diff --git a/src/mainboard/google/brya/variants/gothrax/overridetree.cb b/src/mainboard/google/brya/variants/gothrax/overridetree.cb index 0cc0954ae95a..2cb87a4e4b61 100644 --- a/src/mainboard/google/brya/variants/gothrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/gothrax/overridetree.cb @@ -227,14 +227,14 @@ chip soc/intel/alderlake register "desc" = ""SAR2 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" register "speed" = "I2C_SPEED_FAST" - register "uid" = "2" + register "uid" = "1" register "reg_gnrl_ctrl0" = "0x16" register "reg_gnrl_ctrl1" = "0x21" - register "reg_afe_ctrl0" = "0x00" + register "reg_afe_ctrl0" = "0x20" register "reg_afe_ctrl1" = "0x10" register "reg_afe_ctrl2" = "0x00" - register "reg_afe_ctrl3" = "0x00" - register "reg_afe_ctrl4" = "0x07" + register "reg_afe_ctrl3" = "0x01" + register "reg_afe_ctrl4" = "0x46" register "reg_afe_ctrl5" = "0x00" register "reg_afe_ctrl6" = "0x00" register "reg_afe_ctrl7" = "0x07" |