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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-01-02 14:04:02 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-24 13:54:21 +0000 |
| commit | ab0a77453c86fe01ef142fcf1df5e1c11a16daf2 (patch) | |
| tree | 14a701f834cf7e13da6444a50efae7dae5aefa63 /src | |
| parent | 267684f10e5b86bfa5ee8af25d8f61b2a5a27e5e (diff) | |
| download | coreboot-ab0a77453c86fe01ef142fcf1df5e1c11a16daf2.tar.gz coreboot-ab0a77453c86fe01ef142fcf1df5e1c11a16daf2.tar.bz2 coreboot-ab0a77453c86fe01ef142fcf1df5e1c11a16daf2.zip | |
cbmem_top: Fix comment and remove upper limit
There's no such limit on 64 Bit coreboot builds.
* Fix comment in cbmem.h
* Remove 4 GiB limit on Cavium SoCs
Tested on opencellular/elgon.
Still boots Linux as payload.
Change-Id: I8c9c6a5ff81bee48311e8bf8e383d1a032ea3a6d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/cbmem.h | 3 | ||||
| -rw-r--r-- | src/soc/cavium/cn81xx/cbmem.c | 4 |
2 files changed, 4 insertions, 3 deletions
diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 59f4e105e113..680284acf1c3 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -70,7 +70,8 @@ void cbmem_top_init(void); /* Return the top address for dynamic cbmem. The address returned needs to * be consistent across romstage and ramstage, and it is required to be - * below 4GiB. + * below 4GiB for 32bit coreboot builds. On 64bit coreboot builds there's no + * upper limit. * x86 boards or chipsets must return NULL before the cbmem backing store has * been initialized. */ void *cbmem_top(void); diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index 397fd263d712..bb6fa18f2017 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2014 Rockchip Inc. + * Copyright 2019 9Elements GmbH <patrick.rudolph@9elements.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +23,5 @@ void *cbmem_top(void) { /* Make sure not to overlap with reserved ATF scratchpad */ - return (void *)min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB, - 4ULL * GiB); + return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); } |