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authorPatrick Rudolph <siro@das-labor.org>2017-05-04 19:00:33 +0200
committerPatrick Rudolph <siro@das-labor.org>2017-05-21 16:38:34 +0200
commitac27d3688a862074631e3a1390caf85c068d55cb (patch)
tree904158a0566038c8d2c51972e2318370ef5617b2 /src
parent7565cf1a49bf9688e636e1ebc6a4cb8e1e567e1b (diff)
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mb/*/romstage: Don't lock ETR3 CF9GR in early romstage
Do not lock ETR3 CF9GR in early romstage. As of Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 this is done in bd82x6x's finalize handler. Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/gigabyte/ga-b75m-d3h/romstage.c2
-rw-r--r--src/mainboard/gigabyte/ga-b75m-d3v/romstage.c2
-rw-r--r--src/mainboard/lenovo/l520/romstage.c1
-rw-r--r--src/mainboard/lenovo/s230u/romstage.c2
-rw-r--r--src/mainboard/lenovo/t420/romstage.c2
-rw-r--r--src/mainboard/lenovo/t420s/romstage.c2
-rw-r--r--src/mainboard/lenovo/t430s/romstage.c2
-rw-r--r--src/mainboard/lenovo/t520/romstage.c3
-rw-r--r--src/mainboard/lenovo/t530/romstage.c3
-rw-r--r--src/mainboard/lenovo/x1_carbon_gen1/romstage.c3
-rw-r--r--src/mainboard/lenovo/x220/romstage.c3
-rw-r--r--src/mainboard/lenovo/x230/romstage.c3
12 files changed, 11 insertions, 17 deletions
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
index bb3b223c3b95..cbc55921a88f 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -153,7 +153,7 @@ void pch_enable_lpc(void)
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
/* Initialize SuperIO */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
index 4a02790c39db..22a10aef4d5e 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
@@ -85,7 +85,7 @@ void pch_enable_lpc(void)
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
/* Initialize SuperIO */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c
index 47b9fd6a2c2f..6c93eedd79a1 100644
--- a/src/mainboard/lenovo/l520/romstage.c
+++ b/src/mainboard/lenovo/l520/romstage.c
@@ -31,7 +31,6 @@ void pch_enable_lpc(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
}
void rcba_config(void)
diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c
index ad5f02187f17..610eb89e3075 100644
--- a/src/mainboard/lenovo/s230u/romstage.c
+++ b/src/mainboard/lenovo/s230u/romstage.c
@@ -43,7 +43,7 @@ void pch_enable_lpc(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), ETR3, 0x10000);
/* Memory map KB9012 EC registers */
pci_write_config32(
diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c
index d25ce4532876..766b019f5b92 100644
--- a/src/mainboard/lenovo/t420/romstage.c
+++ b/src/mainboard/lenovo/t420/romstage.c
@@ -33,7 +33,7 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void rcba_config(void)
diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c
index 27b45fd361dd..e32337aa12bf 100644
--- a/src/mainboard/lenovo/t420s/romstage.c
+++ b/src/mainboard/lenovo/t420s/romstage.c
@@ -36,7 +36,7 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void rcba_config(void)
diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c
index 92f9e6263fdf..a17ec52e43af 100644
--- a/src/mainboard/lenovo/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/romstage.c
@@ -36,7 +36,7 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void rcba_config(void)
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index 5ba487321c2b..fd17f21292b5 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -50,8 +50,7 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac,
- 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void rcba_config(void)
diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index 3d603c5d6d6b..050e8cf16a3e 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -37,8 +37,7 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac,
- 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void rcba_config(void)
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
index 3e11324f4c88..574d02b137fb 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
@@ -51,8 +51,7 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac,
- 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index 5a1c90af7771..15d2c845bbce 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -47,8 +47,7 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac,
- 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void rcba_config(void)
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 53ad9ac61a7d..e68843c10602 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -50,8 +50,7 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac,
- 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void rcba_config(void)