arch/x86: Use ENV_X86_64 instead of _x86_64_

Tested on Intel Sandybridge x86_64 and x86_32.

Change-Id: I152483d24af0512c0ee4fbbe8931b7312e487ac6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

23 files changed, 44 insertions, 44 deletions

diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index 31670c29b69c..6e730273f84f 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -15,7 +15,7 @@
 	#define _STACK_TOP _ecar_stack
 #endif
 
-#ifdef __x86_64__
+#if ENV_X86_64
 .code64
 #else
 .code32
@@ -26,7 +26,7 @@
 _start:
 
 	/* Migrate GDT to this text segment */
-#ifdef __x86_64__
+#if ENV_X86_64
 	call	gdt_init64
 #else
 	call	gdt_init
diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c
index 777a0b7d904a..31e7cee4dcef 100644
--- a/src/arch/x86/boot.c
+++ b/src/arch/x86/boot.c
@@ -21,14 +21,14 @@ int payload_arch_usable_ram_quirk(uint64_t start, uint64_t size)
 
 void arch_prog_run(struct prog *prog)
 {
-#if ENV_RAMSTAGE && defined(__x86_64__)
+#if ENV_RAMSTAGE && ENV_X86_64
 	const uint32_t arg = pointer_to_uint32_safe(prog_entry_arg(prog));
 	const uint32_t entry = pointer_to_uint32_safe(prog_entry(prog));
 
 	/* On x86 coreboot payloads expect to be called in protected mode */
 	protected_mode_jump(entry, arg);
 #else
-#ifdef __x86_64__
+#if ENV_X86_64
 	void (*doit)(void *arg);
 #else
 	/* Ensure the argument is pushed on the stack. */
diff --git a/src/arch/x86/c_exit.S b/src/arch/x86/c_exit.S
index e5b9bf8d74a6..bb1df28adf26 100644
--- a/src/arch/x86/c_exit.S
+++ b/src/arch/x86/c_exit.S
@@ -5,7 +5,7 @@
 #include <cpu/x86/cr.h>
 
 
-#ifdef __x86_64__
+#if ENV_X86_64
 
 	/*
 	 * Functions to handle mode switches from long mode to protected
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index b7ffddc385eb..3ef03b3346c3 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -24,7 +24,7 @@ thread_stacks:
 #endif
 
 	.section ".text._start", "ax", @progbits
-#ifdef __x86_64__
+#if ENV_X86_64
 	.code64
 #else
 	.code32
@@ -32,7 +32,7 @@ thread_stacks:
 	.globl _start
 _start:
 	cli
-#ifdef __x86_64__
+#if ENV_X86_64
 	movabs	$gdtaddr, %rax
 	lgdt	(%rax)
 #else
@@ -45,7 +45,7 @@ _start:
 	movl	%eax, %ss
 	movl	%eax, %fs
 	movl	%eax, %gs
-#ifdef __x86_64__
+#if ENV_X86_64
 	mov	$RAM_CODE_SEG64, %ecx
 	call	SetCodeSelector
 #endif
@@ -54,7 +54,7 @@ _start:
 
 	cld
 
-#ifdef	__x86_64__
+#if ENV_X86_64
 	mov	%rdi, %rax
 	movabs	%rax, _cbmem_top_ptr
 	movabs	$_stack, %rdi
@@ -117,7 +117,7 @@ _start:
 
 	.globl gdb_stub_breakpoint
 gdb_stub_breakpoint:
-#ifdef __x86_64__
+#if ENV_X86_64
 	pop	%rax	/* Return address */
 	pushfl
 	push	%cs
@@ -139,7 +139,7 @@ gdb_stub_breakpoint:
 
 gdtaddr:
 	.word	gdt_end - gdt - 1
-#ifdef __x86_64__
+#if ENV_X86_64
 	.quad	gdt
 #else
 	.long	gdt		/* we know the offset */
@@ -176,7 +176,7 @@ gdt:
 
 	/* selgdt 0x18, flat data segment */
 	.word	0xffff, 0x0000
-#ifdef __x86_64__
+#if ENV_X86_64
 	.byte	0x00, 0x92, 0xcf, 0x00
 #else
 	.byte	0x00, 0x93, 0xcf, 0x00
@@ -210,7 +210,7 @@ gdt:
 					* limit
 					*/
 
-#ifdef __x86_64__
+#if ENV_X86_64
 	/* selgdt 0x48, flat x64 code segment */
 	.word	0xffff, 0x0000
 	.byte	0x00, 0x9b, 0xaf, 0x00
@@ -218,7 +218,7 @@ gdt:
 gdt_end:
 
 	.section ".text._start", "ax", @progbits
-#ifdef __x86_64__
+#if ENV_X86_64
 SetCodeSelector:
 	# save rsp because iret will align it to a 16 byte boundary
 	mov	%rsp, %rdx
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index c929e5ea694c..f4cb83a4dd16 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -13,7 +13,7 @@
 #include <device/device.h>
 #include <smp/spinlock.h>
 
-#ifndef __x86_64__
+#if ENV_X86_32
 /* Standard macro to see if a specific flag is changeable */
 static inline int flag_is_changeable_p(uint32_t flag)
 {
@@ -136,7 +136,7 @@ static void identify_cpu(struct device *cpu)
 
 	vendor_name[0] = '\0'; /* Unset */
 
-#ifndef __x86_64__
+#if ENV_X86_32
 	/* Find the id and vendor_name */
 	if (!cpu_have_cpuid()) {
 		/* Its a 486 if we can modify the AC flag */
diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c
index 07de1553b89a..77d08c41962d 100644
--- a/src/arch/x86/cpu_common.c
+++ b/src/arch/x86/cpu_common.c
@@ -2,7 +2,7 @@
 
 #include <cpu/cpu.h>
 
-#ifndef __x86_64__
+#if ENV_X86_32
 /* Standard macro to see if a specific flag is changeable */
 static inline int flag_is_changeable_p(uint32_t flag)
 {
diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c
index aa94d3fe737c..624226e36e84 100644
--- a/src/arch/x86/exception.c
+++ b/src/arch/x86/exception.c
@@ -492,7 +492,7 @@ void x86_exception(struct eregs *info)
 	logical_processor = cpu_index();
 #endif
 	u8 *code;
-#ifdef __x86_64__
+#if ENV_X86_64
 #define MDUMP_SIZE 0x100
 	printk(BIOS_EMERG,
 		"CPU Index %d - APIC %d Unexpected Exception:\n"
diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S
index d1b1a537fef0..527a3cb13a54 100644
--- a/src/arch/x86/exit_car.S
+++ b/src/arch/x86/exit_car.S
@@ -11,7 +11,7 @@ post_car_stack_top:
 .long	0
 .long	0
 
-#if defined(__x86_64__)
+#if ENV_X86_64
 .code64
 .macro pop_eax_edx
 	pop	%rax
@@ -42,13 +42,13 @@ _start:
 	   is expected to be implemented in assembly. */
 
 	/* Migrate GDT to this text segment */
-#if defined(__x86_64__)
+#if ENV_X86_64
 	call	gdt_init64
 #else
 	call	gdt_init
 #endif
 
-#ifdef	__x86_64__
+#if ENV_X86_64
 	mov	%rdi, %rax
 	movabs %rax, _cbmem_top_ptr
 #else
@@ -61,7 +61,7 @@ _start:
 	cpuid
 	btl	$CPUID_FEATURE_CLFLUSH_BIT, %edx
 	jnc	skip_clflush
-#ifdef	__x86_64__
+#if ENV_X86_64
 	movabs	_cbmem_top_ptr, %rax
 	clflush	(%rax)
 #else
@@ -73,7 +73,7 @@ skip_clflush:
 	call	chipset_teardown_car
 
 	/* Enable caching if not already enabled. */
-#ifdef  __x86_64__
+#if ENV_X86_64
 	mov	%cr0, %rax
 	and     $(~(CR0_CD | CR0_NW)), %eax
 	mov	%rax, %cr0
@@ -115,7 +115,7 @@ skip_clflush:
 	/* Need to align stack to 16 bytes at the call instruction. Therefore
 	   account for the 1 push. */
 	andl	$0xfffffff0, %esp
-#if defined(__x86_64__)
+#if ENV_X86_64
 	mov	%rbp, %rdi
 #else
 	sub	$12, %esp
diff --git a/src/arch/x86/gdt_init.S b/src/arch/x86/gdt_init.S
index 30b39653c943..825c23ccbd56 100644
--- a/src/arch/x86/gdt_init.S
+++ b/src/arch/x86/gdt_init.S
@@ -18,7 +18,7 @@ gdtptr:
 	.word	gdt_end - gdt -1 /* compute the table limit */
 	.long	gdt		 /* we know the offset */
 
-#ifdef __x86_64__
+#if ENV_X86_64
 .code64
 .section .init._gdt64_, "ax", @progbits
 	.globl gdt_init64
diff --git a/src/arch/x86/idt.S b/src/arch/x86/idt.S
index 6807056fe317..d763b9e3fed5 100644
--- a/src/arch/x86/idt.S
+++ b/src/arch/x86/idt.S
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 	.section ".text._idt", "ax", @progbits
-#ifdef __x86_64__
+#if ENV_X86_64
 	.code64
 #else
 	.code32
@@ -109,7 +109,7 @@ vec19:
 
 .global int_hand
 int_hand:
-#ifdef __x86_64__
+#if ENV_X86_64
 	/* At this point, on x86-64, on the stack there is:
 	 *  0(%rsp) vector
 	 *  8(%rsp) error code
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 889628da27d1..3fd4c1b2eae0 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -235,7 +235,7 @@ static inline struct cpu_info *cpu_info(void)
 {
 	struct cpu_info *ci;
 	__asm__(
-#ifdef __x86_64__
+#if ENV_X86_64
 		"and %%rsp,%0; "
 		"or  %2, %0 "
 #else
diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h
index 5f8f9becd36f..7043cd1941d5 100644
--- a/src/arch/x86/include/arch/registers.h
+++ b/src/arch/x86/include/arch/registers.h
@@ -42,7 +42,7 @@
 		uint64_t r##A; \
 	} __packed
 
-#ifdef __ARCH_x86_64__
+#if ENV_X86_64
 struct eregs {
 	QUAD_DOWNTO8(a);
 	QUAD_DOWNTO8(c);
diff --git a/src/arch/x86/memcpy.c b/src/arch/x86/memcpy.c
index 1cfdf891755a..93002cdd2757 100644
--- a/src/arch/x86/memcpy.c
+++ b/src/arch/x86/memcpy.c
@@ -15,7 +15,7 @@ void *memcpy(void *dest, const void *src, size_t n)
 #endif
 
 	asm volatile(
-#ifdef __x86_64__
+#if ENV_X86_64
 		"rep ; movsd\n\t"
 		"mov %4,%%rcx\n\t"
 #else
diff --git a/src/arch/x86/wakeup.S b/src/arch/x86/wakeup.S
index ae2efe00edf3..dc9510bb9013 100644
--- a/src/arch/x86/wakeup.S
+++ b/src/arch/x86/wakeup.S
@@ -6,7 +6,7 @@
 /* CR0 bits */
 #define PE		(1 << 0)
 
-#ifdef __x86_64__
+#if ENV_X86_64
 	.code64
 #else
 	.code32
@@ -14,7 +14,7 @@
 
 	.globl __wakeup
 __wakeup:
-#ifdef __x86_64__
+#if ENV_X86_64
 	xor	%rax,%rax
 	mov	%ss, %ax
 	push	%rax
diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
index 07f848a0193a..f828d6f31ab0 100644
--- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S
+++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
@@ -83,7 +83,7 @@ pages_done:
 #include <cpu/x86/64bit/entry64.inc>
 
 	/* Restore the BIST result and timestamps. */
-#if defined(__x86_64__)
+#if ENV_X86_64
 	movd	%mm2, %rdi
 	shlq	$32, %rdi
 	movd	%mm1, %rsi
diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc
index 70255173f143..7da68b47f911 100644
--- a/src/cpu/x86/64bit/entry64.inc
+++ b/src/cpu/x86/64bit/entry64.inc
@@ -9,7 +9,7 @@
  * Clobbers: eax, ecx, edx
  */
 
-#if defined(__x86_64__)
+#if ENV_X86_64
 	.code32
 #if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0
 #error pagetables must be 4KiB aligned!
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 295f583b2708..e141ad8ec9b9 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -38,7 +38,7 @@ static int  lowmem_backup_size;
 static inline void setup_secondary_gdt(void)
 {
 	u16 *gdt_limit;
-#ifdef __x86_64__
+#if ENV_X86_64
 	u64 *gdt_base;
 #else
 	u32 *gdt_base;
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index d8156b88a80a..aa95461ae8f5 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -214,7 +214,7 @@ load_msr:
 	mov	%eax, %cr4
 #endif
 
-#ifdef __x86_64__
+#if ENV_X86_64
 	/* entry64.inc preserves ebx. */
 #include <cpu/x86/64bit/entry64.inc>
 
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 07be047a3654..44ee7cb327ca 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -185,7 +185,7 @@ apicid_end:
 	/* Align stack to 16 bytes. Another 32 bytes are pushed below. */
 	andl	$0xfffffff0, %esp
 
-#ifdef __x86_64__
+#if ENV_X86_64
 	mov	%ecx, %edi
 	/* Backup IA32_EFER. Preserves ebx. */
 	movl	$(IA32_EFER), %ecx
@@ -204,7 +204,7 @@ apicid_end:
 	 *   struct arg = { c_handler_params, cpu_num, smm_runtime, canary };
 	 *   c_handler(&arg)
 	 */
-#ifdef __x86_64__
+#if ENV_X86_64
 	push	%rbx /* uintptr_t *canary */
 	push	%rcx /* size_t cpu */
 
diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S
index 3750e5224a8d..b7805d06ab73 100644
--- a/src/cpu/x86/smm/smmhandler.S
+++ b/src/cpu/x86/smm/smmhandler.S
@@ -43,7 +43,7 @@
 
 #define SMM_HANDLER_OFFSET 0x0000
 
-#if defined(__x86_64__)
+#if ENV_X86_64
 .bss
 ia32efer_backup_eax:
 .long 0
@@ -166,7 +166,7 @@ untampered_lapic:
 	addl	$SMM_STACK_SIZE, %ebx
 	movl	%ebx, %esp
 
-#if defined(__x86_64__)
+#if ENV_X86_64
 	/* Backup IA32_EFER. Preserves ebx. */
 	movl	$(IA32_EFER), %ecx
 	rdmsr
@@ -180,7 +180,7 @@ untampered_lapic:
 	/* Call C handler */
 	call	smi_handler
 
-#if defined(__x86_64__)
+#if ENV_X86_64
 	/*
 	 * The only reason to go back to protected mode is that RSM doesn't restore
 	 * MSR registers and MSR IA32_EFER was modified by entering long mode.
diff --git a/src/include/assert.h b/src/include/assert.h
index 829e73207e55..93d6bfc41276 100644
--- a/src/include/assert.h
+++ b/src/include/assert.h
@@ -94,7 +94,7 @@ extern void _dead_code_assertion_failed(void) __attribute__((noreturn));
 	*(type *)(uintptr_t)0; \
 })
 
-#ifdef __x86_64__
+#if ENV_X86_64
 #define pointer_to_uint32_safe(x) ({ \
 	if ((uintptr_t)(x) > 0xffffffffUL) \
 		die("Cast from pointer to uint32_t overflows"); \
diff --git a/src/include/cpu/x86/cr.h b/src/include/cpu/x86/cr.h
index 3508505a7c0f..c70f35c10389 100644
--- a/src/include/cpu/x86/cr.h
+++ b/src/include/cpu/x86/cr.h
@@ -9,7 +9,7 @@
 
 #define COMPILER_BARRIER "memory"
 
-#ifdef __x86_64__
+#if ENV_X86_64
 #define CRx_TYPE uint64_t
 #define CRx_IN   "q"
 #define CRx_RET  "=q"
diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c
index d5b9b3445fcf..b4c707d3ecee 100644
--- a/src/soc/intel/denverton_ns/soc_util.c
+++ b/src/soc/intel/denverton_ns/soc_util.c
@@ -274,7 +274,7 @@ void *memcpy_s(void *dest, const void *src, size_t n)
 	unsigned long d0, d1, d2;
 
 	asm volatile(
-#ifdef __x86_64__
+#if ENV_X86_64
 		"rep ; movsd\n\t"
 		"mov %4,%%rcx\n\t"
 #else