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| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2020-06-26 19:15:43 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-29 16:03:24 +0000 |
| commit | af05c86dcb2db29584ab68e77aeecc4906f034b7 (patch) | |
| tree | 73fcd70b8d2430f68a4038cc66ce01053a11197f /src | |
| parent | 38569d061099d6453adc2dfc11eb6a26fb1985a3 (diff) | |
| download | coreboot-af05c86dcb2db29584ab68e77aeecc4906f034b7.tar.gz coreboot-af05c86dcb2db29584ab68e77aeecc4906f034b7.tar.bz2 coreboot-af05c86dcb2db29584ab68e77aeecc4906f034b7.zip | |
soc/amd/picasso/soc_util: add comment on the silicon and soc types
Change-Id: I71704ab292edf8bd343370e6b72c47a8f3aceffd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/picasso/soc_util.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c index 64a97a059e7d..12129206cfef 100644 --- a/src/soc/amd/picasso/soc_util.c +++ b/src/soc/amd/picasso/soc_util.c @@ -9,6 +9,14 @@ #include <soc/soc_util.h> #include <types.h> +/* + * The Zen/Zen+ based APUs can be RV (sometimes called RV1), PCO or RV2 silicon. RV2 has less + * PCIe, USB3 and DisplayPort connectivity than RV(1) or PCO. A Picasso SoC is always PCO + * silicon, a Dali SoC can either be RV2 or fused-down PCO silicon that has the same + * connectivity as the RV2 one and Pollock is always RV2 silicon. Picasso and Dali are in a FP5 + * package while Pollock is in the smaller FT5 package. + */ + #define SOCKET_TYPE_SHIFT 28 #define SOCKET_TYPSE_MASK (0xf << SOCKET_TYPE_SHIFT) |