vendor/mediatek: Add MT8195 dram initialization code

This is the DRAM initialization code from the reference
implementation released by Mediatek for MT8195.

The DRAM calibration code can be taken as a standalone
library, used by different boot loaders for initializing
DRAM and following a different coding style (coreboot was
using Linux Kernel coding style), so we have to put it
in vendor code folder.

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com>
Change-Id: Iada3ec5ae8a39a8e9253caba550c834d486dddcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

46 files changed, 96771 insertions, 0 deletions

diff --git a/src/vendorcode/mediatek/Makefile.inc b/src/vendorcode/mediatek/Makefile.inc
index 06561ef24a93..6befcdecef60 100644
--- a/src/vendorcode/mediatek/Makefile.inc
+++ b/src/vendorcode/mediatek/Makefile.inc
@@ -1 +1,2 @@
 subdirs-$(CONFIG_SOC_MEDIATEK_MT8192) += mt8192
+subdirs-$(CONFIG_SOC_MEDIATEK_MT8195) += mt8195
diff --git a/src/vendorcode/mediatek/mt8195/Makefile.inc b/src/vendorcode/mediatek/mt8195/Makefile.inc
new file mode 100644
index 000000000000..2dd5d098d642
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/Makefile.inc
@@ -0,0 +1,5 @@
+subdirs-y += dramc
+
+CPPFLAGS_common += -Isrc/soc/mediatek/mt8195/include
+CPPFLAGS_common += -Isrc/soc/mediatek/common/include
+CPPFLAGS_common += -Isrc/vendorcode/mediatek/mt8195/dramc/include -Isrc/vendorcode/mediatek/mt8195/include
diff --git a/src/vendorcode/mediatek/mt8195/dramc/ANA_init_config.c b/src/vendorcode/mediatek/mt8195/dramc/ANA_init_config.c
new file mode 100644
index 000000000000..8f3ab2c2800a
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/ANA_init_config.c
@@ -0,0 +1,1708 @@
+#include "dramc_dv_init.h"
+#include "dramc_common.h"
+#include "dramc_top.h"
+//==========================
+//PLL config
+//==========================
+static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate)
+{
+    U32 XTAL_FREQ = 26;
+    U8  PREDIV    = 1;  //0/1/2
+    U8  POSDIV    = 0;  //0/1/2
+    U8  FBKSEL    = 0;  //over 3800 1 otherwise 0
+    U32 PCW;
+    U8 DIV16_CK_SEL    = 0;
+
+#if EMI_LPBK_USE_DDR_800 // For Pe_trus DDR1600, sedalpbk DDR800 thru io
+    if(p->frequency==800)
+    {
+        POSDIV = 1;
+    }
+#endif
+
+#if (fcFOR_CHIP_ID == fc8195)
+    if(A_D->DQ_CA_OPEN == 1)
+    {
+        DIV16_CK_SEL = 0; // For open loop mode DDR400 = 1600/div4, confirm with WL Lee
+    }
+    else
+#endif
+    FBKSEL = (PLL_FREQ > 3800)?1:0;
+    PCW    = (PLL_FREQ/XTAL_FREQ) << (8+1-FBKSEL-PREDIV-POSDIV);
+
+
+    mcSHOW_DBG_MSG6((">>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL\n"));
+    mcSHOW_DBG_MSG6(("=================================== \n"));
+    mcSHOW_DBG_MSG6(("data_rate = %d,PCW = 0X%x\n",data_rate,PCW));
+    mcSHOW_DBG_MSG6(("=================================== \n"));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL1), P_Fld(0, PHYPLL1_RG_RPHYPLL_TST_EN) | P_Fld(0, PHYPLL1_RG_RPHYPLL_TSTOP_EN));
+    // @Darren, Mp settings sync @WL
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL0)     , P_Fld(0      , SHU_PHYPLL0_RG_RPHYPLL_RESERVED           ) \
+                                                                  | P_Fld(0      , SHU_PHYPLL0_RG_RPHYPLL_ICHP           ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL0)     , P_Fld(0      , SHU_CLRPLL0_RG_RCLRPLL_RESERVED           ) \
+                                                                  | P_Fld(0      , SHU_CLRPLL0_RG_RCLRPLL_ICHP           ));
+
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL2)     , P_Fld(PREDIV      , SHU_PHYPLL2_RG_RPHYPLL_PREDIV           ) \
+                                                                  | P_Fld(POSDIV      , SHU_PHYPLL2_RG_RPHYPLL_POSDIV           ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL2)     , P_Fld(PREDIV      , SHU_CLRPLL2_RG_RCLRPLL_PREDIV           ) \
+                                                                  | P_Fld(POSDIV      , SHU_CLRPLL2_RG_RCLRPLL_POSDIV           ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL1)     , P_Fld(PCW         , SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW          ) \
+                                                                  | P_Fld(1           , SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG      ) \
+                                                                  | P_Fld(0           , SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN       )); //for DV could set 1 to solve clock jitter issue.
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL1)     , P_Fld(PCW         , SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW          ) \
+                                                                  | P_Fld(1           , SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG      ) \
+                                                                  | P_Fld(0           , SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN       )); //for DV could set 1 to solve clock jitter issue.
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL1)        , P_Fld(1           , SHU_PLL1_RG_RPHYPLLGP_CK_SEL            ) \
+                                                                  | P_Fld(1           , SHU_PLL1_R_SHU_AUTO_PLL_MUX             ));  //notice here. TODO. should create another function to manage the SPM related
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL3)     , P_Fld(0           , SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN         ) \
+                                                                  | P_Fld(1           , SHU_PHYPLL3_RG_RPHYPLL_RST_DLY          ) \
+                                                                  | P_Fld(FBKSEL      , SHU_PHYPLL3_RG_RPHYPLL_FBKSEL           ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL3)     , P_Fld(0           , SHU_CLRPLL3_RG_RCLRPLL_LVROD_EN         ) \
+                                                                  | P_Fld(1           , SHU_CLRPLL3_RG_RCLRPLL_RST_DLY          ) \
+                                                                  | P_Fld(FBKSEL      , SHU_CLRPLL3_RG_RCLRPLL_FBKSEL           ));
+    //if(A_D->DQ_CA_OPEN == 1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_CLK_CTRL0), P_Fld( A_D->DQ_CA_OPEN   , SHU_MISC_CLK_CTRL0_M_CK_OPENLOOP_MODE_SEL   ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL3) , P_Fld( A_D->DQ_CA_OPEN          , SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN         ) \
+                                                                  | P_Fld( DIV16_CK_SEL          , SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL       )); //@Darren, DDR250 = 4G/div16, confirm with WL Lee
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL3) , P_Fld( A_D->DQ_CA_OPEN          , SHU_CLRPLL3_RG_RCLRPLL_MONCK_EN         ) \
+                                                                  | P_Fld( DIV16_CK_SEL          , SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL       )); //@Darren, DDR250 = 4G/div16, confirm with WL Lee
+    }
+//    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2)        , P_Fld(1           , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU    ));
+    mcSHOW_DBG_MSG6(("<<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL\n"));
+}
+
+
+static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T *a_cfg)
+{
+    U8 TX_ARDQ_SERMODE=0; //DQ_P2S_RATIO
+    U8 TX_ARCA_SERMODE=0; //CA_P2S_RATIO
+    U8 ARDLL_SERMODE_B=0;
+    U8 ARDLL_SERMODE_C=0;
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    mcSHOW_DBG_MSG6((">>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration\n"));
+    switch (tr->DQ_P2S_RATIO)
+    {
+        case 4 : { TX_ARDQ_SERMODE = 1; break; }
+        case 8 : { TX_ARDQ_SERMODE = 2; break; }
+        case 16: { TX_ARDQ_SERMODE = 3; break; }
+        default: mcSHOW_ERR_MSG(("ERROR: tr->DQ_P2S_RATIO= %2d, Not support!!",tr->DQ_P2S_RATIO));
+    }
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ14), P_Fld(  TX_ARDQ_SERMODE    , SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0        ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ14), P_Fld(  TX_ARDQ_SERMODE    , SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1        ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6) , P_Fld(  TX_ARDQ_SERMODE    , SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6) , P_Fld(  TX_ARDQ_SERMODE    , SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1));
+
+    //Justin confirm that DES_MODE -> Deserializer mode, while DQ_P2S_RATIO=16 setting 3 others 2. in fact ANA could support some other mode, Here is an propsal option
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11), P_Fld( (tr->DQ_P2S_RATIO == 16 ) ? 3 : 2 , SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11) , P_Fld( (tr->DQ_P2S_RATIO == 16 ) ? 3 : 2 , SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11) , P_Fld( (tr->DQ_P2S_RATIO == 16 ) ? 3 : 2 , SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1));
+
+    switch (tr->CA_P2S_RATIO)
+    {
+        case 2 : { TX_ARCA_SERMODE = (0 + tr->CA_FULL_RATE); break; }
+        case 4 : { TX_ARCA_SERMODE = (1 + tr->CA_FULL_RATE); break; }
+        case 8:  { TX_ARCA_SERMODE = (2 + tr->CA_FULL_RATE); break; }
+        default: mcSHOW_ERR_MSG(("ERROR: tr->CA_P2S_RATIO= %2d, Not support!!",tr->CA_P2S_RATIO));
+    }
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD14), P_Fld(TX_ARCA_SERMODE, SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6),  P_Fld(TX_ARCA_SERMODE, SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE));
+
+    switch (tr->DQ_AAMCK_DIV)
+    {
+        case 0 : { ARDLL_SERMODE_B = (isLP4_DSC)?2:0; break; } //for DSC semi-open B1 has to set 2 and B0 don't care
+        case 2 : { ARDLL_SERMODE_B = 1; break; }
+        case 4 : { ARDLL_SERMODE_B = 2; break; }
+        case 8:  { ARDLL_SERMODE_B = 3; break; }
+        default: mcSHOW_ERR_MSG(("WARN: tr->DQ_AAMCK_DIV= %2d, Because of DQ_SEMI_OPEN, It's don't care.",tr->DQ_AAMCK_DIV));
+    }
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1), P_Fld(ARDLL_SERMODE_B             , SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1), P_Fld(ARDLL_SERMODE_B             , SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1));//TODO:check
+
+    switch (tr->CA_ADMCK_DIV)
+    {
+        case 2 : { ARDLL_SERMODE_C = 1; break; }
+        case 4 : { ARDLL_SERMODE_C = 2; break; }
+        case 8:  { ARDLL_SERMODE_C = 3; break; }
+        default: mcSHOW_ERR_MSG(("ERROR: tr->CA_ADMCK_DIV= %2d, Not support!!",tr->CA_ADMCK_DIV));
+    }
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1),  P_Fld(ARDLL_SERMODE_C           , SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA));
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+
+    //DQ  SEMI-OPEN register control
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6)             , P_Fld(  tr->DQ_SEMI_OPEN , SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0         ) \
+                                                                         | P_Fld(  tr->DQ_CA_OPEN   , SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0          ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6)             , P_Fld(  tr->DQ_SEMI_OPEN , SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1         ) \
+                                                                         | P_Fld(  tr->DQ_CA_OPEN   , SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1          ));
+
+    //CA  SEMI-OPEN register control
+    if(tr->CA_SEMI_OPEN == 0)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6)        , P_Fld( 0         , SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA        ) \
+                                                                         | P_Fld( 0         , SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA  ) \
+                                                                         | P_Fld( 0         , SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA   ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3)   , P_Fld( !(tr->DQ_CA_OPEN)         , SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA      ) \
+                                                                         | P_Fld( !(tr->DQ_CA_OPEN)         , SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN        ) \
+                                                                         | P_Fld( !(tr->DQ_CA_OPEN)         , SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA    ));
+    }
+    else
+    {
+        // @Darren, for DDR800semi
+        DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD6        , P_Fld( 1         , SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA        ) \
+                                                                         | P_Fld( 1         , SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA  ) \
+                                                                         | P_Fld( 16        , SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA   ));
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_DLL_ARPI3   , P_Fld( 1         , SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA      ) \
+                                                                         | P_Fld( 1         , SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN        ));
+        if(!isLP4_DSC)
+        {
+            //CHA CA as master
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3), 1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA    );
+            //CHB CA as slave
+            vSetPHY2ChannelMapping(p, CHANNEL_B);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3), 0, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA    );
+            #if (CHANNEL_NUM>2)
+			    if (channel_num_auxadc > 2) {
+	            	vSetPHY2ChannelMapping(p, CHANNEL_C);
+		            //CHC CA as master
+        		    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3), 1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA    );
+            		//CHD CA as slave
+		            vSetPHY2ChannelMapping(p, CHANNEL_D);
+        		    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3), 0, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA    );
+			    	}
+            #endif
+        }
+        else
+        {
+            //CHA CA as master
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3), 1, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1        );
+            //CHB CA as slave
+            vSetPHY2ChannelMapping(p, CHANNEL_B);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3), 0, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1        );
+            #if (CHANNEL_NUM>2)
+			    if (channel_num_auxadc > 2) {
+		            vSetPHY2ChannelMapping(p, CHANNEL_C);
+        		    //CHC CA as master
+		            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3), 1, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1        );
+		            //CHD CA as slave
+		            vSetPHY2ChannelMapping(p, CHANNEL_D);
+		            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3), 0, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1        );
+			    	}
+            #endif
+        }
+
+        vSetPHY2ChannelMapping(p, CHANNEL_A);
+        DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+
+//--------TODO ---20190721 WAITING DPHY KaiHsin & Alucary confirm this RG setting.
+//        if(a_cfg->DLL_ASYNC_EN == 1)
+//        {
+//            //CA as all master
+//            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3)   , P_Fld(1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA    ));
+//        } else {
+//            DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+//            //CHA CA as master
+//            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3)   , P_Fld(1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA    ));
+//            //CHB CA as slave
+//            vSetPHY2ChannelMapping(p, CHANNEL_B);
+//            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3)   , P_Fld(0, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA    ));
+//            vSetPHY2ChannelMapping(p, CHANNEL_A);
+//            DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+//        }
+    }
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6)        , P_Fld( tr->DQ_CA_OPEN    , SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA        ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13)       , P_Fld( tr->CA_FULL_RATE  , SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA    ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1)        , P_Fld(   tr->PH8_DLY     , SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA   ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1)        , P_Fld( tr->CA_PREDIV_EN  , SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA));
+    if(tr->SEMI_OPEN_CA_PICK_MCK_RATIO == 4)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6)        , P_Fld( 0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA));
+    }
+    else if (tr->SEMI_OPEN_CA_PICK_MCK_RATIO == 8)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6)        , P_Fld( 1, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA));
+    } else {}
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1)        , P_Fld( tr->DQ_TRACK_CA_EN, SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0 ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1)        , P_Fld( tr->DQ_TRACK_CA_EN, SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1 ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2)   , P_Fld( 1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN     ));//TODO:check
+  mcSHOW_DBG_MSG6(("<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration\n"));
+}
+
+//==========================
+//DLL config
+//==========================
+static void ANA_DLL_non_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
+{
+  U8 u1PDZone = (p->frequency >= 2133) ? 0x2 : 0x3;
+
+  if(a_cfg->DLL_IDLE_MODE == 1)
+  {
+    if(a_cfg->DLL_ASYNC_EN == 1)
+    {
+      DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+      vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI5)     , P_Fld(0            , CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA       ) \
+                                                                     | P_Fld(u1PDZone            , CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA       ));
+      vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI5)     , P_Fld(1            , B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0       ) \
+                                                                     | P_Fld(u1PDZone            , B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0       ));
+      vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI5)     , P_Fld(1            , B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1       ) \
+                                                                     | P_Fld(u1PDZone            , B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1       ));
+      DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    } else {
+      DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI5)     , P_Fld(0            , CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA       ) \
+                                                                     | P_Fld(u1PDZone            , CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA       ));
+      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI5)     , P_Fld(1            , B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0       ) \
+                                                                     | P_Fld(u1PDZone            , B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0       ));
+      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI5)     , P_Fld(1            , B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1       ) \
+                                                                     | P_Fld(u1PDZone            , B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1       ));
+      vSetPHY2ChannelMapping(p, CHANNEL_B);
+
+      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI5)     , P_Fld(1            , CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA       ) \
+                                                                     | P_Fld(u1PDZone            , CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA       ));
+      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI5)     , P_Fld(1            , B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0       ) \
+                                                                     | P_Fld(u1PDZone            , B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0       ));
+      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI5)     , P_Fld(1            , B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1       ) \
+                                                                     | P_Fld(u1PDZone            , B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1       ));
+
+      #if (CHANNEL_NUM>2)
+          if (channel_num_auxadc > 2) {
+		      vSetPHY2ChannelMapping(p, CHANNEL_C);
+		      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI5)     , P_Fld(0            , CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA       )
+		                                                                     | P_Fld(u1PDZone            , CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA       ));
+		      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI5)     , P_Fld(1            , B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0       )
+        		                                                             | P_Fld(u1PDZone            , B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0       ));
+		      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI5)     , P_Fld(1            , B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1       )
+		                                                                     | P_Fld(u1PDZone            , B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1       ));
+		      vSetPHY2ChannelMapping(p, CHANNEL_D);
+
+		      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI5)     , P_Fld(1            , CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA       )
+                		                                                     | P_Fld(u1PDZone            , CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA       ));
+		      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI5)     , P_Fld(1            , B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0       )
+        		                                                             | P_Fld(u1PDZone            , B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0       ));
+		      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI5)     , P_Fld(1            , B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1       )
+        		                                                             | P_Fld(u1PDZone            , B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1       ));
+              }
+      #endif
+
+      vSetPHY2ChannelMapping(p, CHANNEL_A);
+
+      DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+  }
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI1)       , P_Fld(0           , CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN      ) \
+                                                                     | P_Fld(0           , CA_DLL_ARPI1_RG_ARPI_CMD_JUMP_EN         ) \
+                                                                     | P_Fld(0           , CA_DLL_ARPI1_RG_ARPI_CLK_JUMP_EN         ) \
+                                                                     | P_Fld(0           , CA_DLL_ARPI1_RG_ARPI_CS_JUMP_EN          ) \
+                                                                     | P_Fld(0           , CA_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_CA       ) \
+                                                                     | P_Fld(0           , CA_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_CA     ) \
+                                                                     | P_Fld(1           , CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA        ) \
+                                                                     | P_Fld(0           , CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI1)       , P_Fld(0           , B0_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B0   ) \
+                                                                     | P_Fld(0           , B0_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B0       ) \
+                                                                     | P_Fld(0           , B0_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B0      ) \
+                                                                     | P_Fld(0           , B0_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B0      ) \
+                                                                     | P_Fld(0           , B0_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B0       ) \
+                                                                     | P_Fld(0           , B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0     ) \
+                                                                     | P_Fld(0           , B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0        ) \
+                                                                     | P_Fld(0           , B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI1)       , P_Fld(0           , B1_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B1   ) \
+                                                                     | P_Fld(0           , B1_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B1       ) \
+                                                                     | P_Fld(0           , B1_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B1      ) \
+                                                                     | P_Fld(0           , B1_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B1      ) \
+                                                                     | P_Fld(0           , B1_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B1       ) \
+                                                                     | P_Fld(0           , B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1     ) \
+                                                                     | P_Fld(0           , B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1        ) \
+                                                                     | P_Fld(0           , B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT));
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI5)       , P_Fld(0           , CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA     ) \
+                                                                     | P_Fld(0           , CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA ) \
+                                                                     | P_Fld(0           , CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA         ) \
+                                                                     | P_Fld(0           , CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA         ));
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI5)       , P_Fld(0           , B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0     ) \
+                                                                     | P_Fld(0           , B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0 ) \
+                                                                     | P_Fld(0           , B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0         ) \
+                                                                     | P_Fld(0           , B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0         ));
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI5)       , P_Fld(0           , B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1     ) \
+                                                                     | P_Fld(0           , B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1 ) \
+                                                                     | P_Fld(0           , B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1         ) \
+                                                                     | P_Fld(0           , B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1         ));
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+}
+
+
+static void ANA_DLL_shuffle_Config(DRAMC_CTX_T *p, ANA_top_config_T *a_cfg)
+{
+    U8 u1Gain = 0;
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+    if(p->frequency<=1600)
+    {
+        u1Gain = 1;//checked by WL
+
+        mcSHOW_DBG_MSG6((">>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = %d\n",u1Gain));
+    }
+
+    mcSHOW_DBG_MSG6((">>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL\n"));
+
+    //B0
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL0)        , P_Fld(  7+u1Gain                       , SHU_B0_DLL0_RG_ARDLL_GAIN_B0         ) \
+                                                                     | P_Fld(  7                       , SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0      ) \
+                                                                     | P_Fld(  0                       , SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0    ) \
+                                                                     | P_Fld(  0                       , SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0   ) \
+                                                                     | P_Fld(  1                       , SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1)        , P_Fld(  1                       , SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0) \
+                                                                     | P_Fld(  1                       , SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0) \
+                                                                     | P_Fld(  0                       , SHU_B0_DLL1_RG_ARDLL_PGAIN_B0        ) \
+                                                                     | P_Fld(  1                       , SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0      ) \
+                                                                     | P_Fld(  1                       , SHU_B0_DLL1_RG_ARDLL_PHDIV_B0        ) \
+                                                                     | P_Fld(  1                       , SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0      ) \
+                                                                     | P_Fld(  1                       , SHU_B0_DLL1_RG_ARDLL_PS_EN_B0        ) \
+                                                                     | P_Fld(  0                       , SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0    ));
+if (isLP4_DSC)
+{
+    //B1
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL0)        , P_Fld(  7+u1Gain                       , SHU_CA_DLL0_RG_ARDLL_GAIN_CA         ) \
+                                                                     | P_Fld(  7                       , SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA      ) \
+                                                                     | P_Fld(  0                       , SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA    ) \
+                                                                     | P_Fld(  0                       , SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA   ) \
+                                                                     | P_Fld(  1                       , SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1)        , P_Fld(  1                       , SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) \
+                                                                     | P_Fld(  1                       , SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) \
+                                                                     | P_Fld(  0                       , SHU_CA_DLL1_RG_ARDLL_PGAIN_CA        ) \
+                                                                     | P_Fld(  1                       , SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA      ) \
+                                                                     | P_Fld(  1                       , SHU_CA_DLL1_RG_ARDLL_PHDIV_CA        ) \
+                                                                     | P_Fld(  1                       , SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA      ) \
+                                                                     | P_Fld(  1                       , SHU_CA_DLL1_RG_ARDLL_PS_EN_CA        ) \
+                                                                     | P_Fld(  0                       , SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA    ));
+
+
+    if(a_cfg->DLL_ASYNC_EN == 1)
+    {
+      DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+      vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL0)        , P_Fld( (a_cfg->ALL_SLAVE_EN == 0)?6:7, SHU_B1_DLL0_RG_ARDLL_GAIN_B1         ) \
+                                                                       | P_Fld( (a_cfg->ALL_SLAVE_EN == 0)?9:7, SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1      ) \
+                                                                       | P_Fld(!(a_cfg->ALL_SLAVE_EN)         , SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1    ) \
+                                                                       | P_Fld(  0                            , SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1   ) \
+                                                                       | P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1));
+      vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1)        , P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1) \
+                                                                       | P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1) \
+                                                                       | P_Fld(  0                            , SHU_B1_DLL1_RG_ARDLL_PGAIN_B1        ) \
+                                                                       | P_Fld(  1                            , SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1      ) \
+                                                                       | P_Fld(  1                            , SHU_B1_DLL1_RG_ARDLL_PHDIV_B1        ) \
+                                                                       | P_Fld(  1                            , SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1      ) \
+                                                                       | P_Fld(  1                            , SHU_B1_DLL1_RG_ARDLL_PS_EN_B1        ) \
+                                                                       | P_Fld(  !(a_cfg->ALL_SLAVE_EN)       , SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1    ));
+      DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    } else {
+      DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL0)        , P_Fld( (p->frequency>=2133)?(6+u1Gain):(7+u1Gain), SHU_B1_DLL0_RG_ARDLL_GAIN_B1         ) \
+                                                                       | P_Fld( (a_cfg->ALL_SLAVE_EN == 0)?9:7, SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1      ) \
+                                                                       | P_Fld(!(a_cfg->ALL_SLAVE_EN)         , SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1    ) \
+                                                                       | P_Fld(  0                            , SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1   ) \
+                                                                       | P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1));
+      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1)        , P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1) \
+                                                                       | P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1) \
+                                                                       | P_Fld(  0                            , SHU_B1_DLL1_RG_ARDLL_PGAIN_B1        ) \
+                                                                       | P_Fld(  1                            , SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1      ) \
+                                                                       | P_Fld(  1                            , SHU_B1_DLL1_RG_ARDLL_PHDIV_B1        ) \
+                                                                       | P_Fld(  1                            , SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1      ) \
+                                                                       | P_Fld(  1                            , SHU_B1_DLL1_RG_ARDLL_PS_EN_B1        ) \
+                                                                       | P_Fld(!(a_cfg->ALL_SLAVE_EN)         , SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1    ));
+
+      vSetPHY2ChannelMapping(p, CHANNEL_B);
+
+      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL0)        , P_Fld(  7+u1Gain                     , SHU_B1_DLL0_RG_ARDLL_GAIN_B1         ) \
+                                                                       | P_Fld(  7                     , SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1      ) \
+                                                                       | P_Fld(  0                     , SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1    ) \
+                                                                       | P_Fld(  0                     , SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1   ) \
+                                                                       | P_Fld(  1                     , SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1));
+      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1)        , P_Fld(  1                     , SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1) \
+                                                                       | P_Fld(  1                     , SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1) \
+                                                                       | P_Fld(  0                     , SHU_B1_DLL1_RG_ARDLL_PGAIN_B1        ) \
+                                                                       | P_Fld(  1                     , SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1      ) \
+                                                                       | P_Fld(  1                     , SHU_B1_DLL1_RG_ARDLL_PHDIV_B1        ) \
+                                                                       | P_Fld(  1                     , SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1      ) \
+                                                                       | P_Fld(  1                     , SHU_B1_DLL1_RG_ARDLL_PS_EN_B1        ) \
+                                                                       | P_Fld(  0                     , SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1    ));
+
+      #if (CHANNEL_NUM>2)
+          if (channel_num_auxadc > 2) {
+		      vSetPHY2ChannelMapping(p, CHANNEL_C);
+
+		      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL0)        , P_Fld( (p->frequency>=2133)?(6+u1Gain):(7+u1Gain), SHU_B1_DLL0_RG_ARDLL_GAIN_B1         )
+        		                                                               | P_Fld( (a_cfg->ALL_SLAVE_EN == 0)?9:7, SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1      )
+                		                                                       | P_Fld(!(a_cfg->ALL_SLAVE_EN)         , SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1    )
+                        		                                               | P_Fld(  0                            , SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1   )
+                                		                                       | P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1));
+		      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1)        , P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1)
+        		                                                               | P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1)
+                		                                                       | P_Fld(  0                            , SHU_B1_DLL1_RG_ARDLL_PGAIN_B1        )
+                        		                                               | P_Fld(  1                            , SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1      )
+                                		                                       | P_Fld(  1                            , SHU_B1_DLL1_RG_ARDLL_PHDIV_B1        )
+                                        		                               | P_Fld(  1                            , SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1      )
+                                                		                       | P_Fld(  1                            , SHU_B1_DLL1_RG_ARDLL_PS_EN_B1        )
+                                                        		               | P_Fld(!(a_cfg->ALL_SLAVE_EN)         , SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1    ));
+
+		      vSetPHY2ChannelMapping(p, CHANNEL_D);
+
+		      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL0)        , P_Fld(  7+u1Gain                     , SHU_B1_DLL0_RG_ARDLL_GAIN_B1         )
+        		                                                               | P_Fld(  7                     , SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1      )
+                		                                                       | P_Fld(  0                     , SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1    )
+                        		                                               | P_Fld(  0                     , SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1   )
+                                		                                       | P_Fld(  1                     , SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1));
+		      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1)        , P_Fld(  1                     , SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1)
+        		                                                               | P_Fld(  1                     , SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1)
+                		                                                       | P_Fld(  0                     , SHU_B1_DLL1_RG_ARDLL_PGAIN_B1        )
+                        		                                               | P_Fld(  1                     , SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1      )
+                                		                                       | P_Fld(  1                     , SHU_B1_DLL1_RG_ARDLL_PHDIV_B1        )
+                                        		                               | P_Fld(  1                     , SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1      )
+                                                		                       | P_Fld(  1                     , SHU_B1_DLL1_RG_ARDLL_PS_EN_B1        )
+                                                        		               | P_Fld(  0                     , SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1    ));
+          	}
+      #endif
+
+      vSetPHY2ChannelMapping(p, CHANNEL_A);
+
+      DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+}
+else
+{
+    //B1
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL0)        , P_Fld(  7+u1Gain                       , SHU_B1_DLL0_RG_ARDLL_GAIN_B1         ) \
+                                                                     | P_Fld(  7                       , SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1      ) \
+                                                                     | P_Fld(  0                       , SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1    ) \
+                                                                     | P_Fld(  0                       , SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1   ) \
+                                                                     | P_Fld(  1                       , SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1)        , P_Fld(  1                       , SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1) \
+                                                                     | P_Fld(  1                       , SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1) \
+                                                                     | P_Fld(  0                       , SHU_B1_DLL1_RG_ARDLL_PGAIN_B1        ) \
+                                                                     | P_Fld(  1                       , SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1      ) \
+                                                                     | P_Fld(  1                       , SHU_B1_DLL1_RG_ARDLL_PHDIV_B1        ) \
+                                                                     | P_Fld(  1                       , SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1      ) \
+                                                                     | P_Fld(  1                       , SHU_B1_DLL1_RG_ARDLL_PS_EN_B1        ) \
+                                                                     | P_Fld(  0                       , SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1    ));
+
+
+    if(a_cfg->DLL_ASYNC_EN == 1)
+    {
+      DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+      vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL0)        , P_Fld( (a_cfg->ALL_SLAVE_EN == 0)?6:7, SHU_CA_DLL0_RG_ARDLL_GAIN_CA         ) \
+                                                                       | P_Fld( (a_cfg->ALL_SLAVE_EN == 0)?9:7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA      ) \
+                                                                       | P_Fld(!(a_cfg->ALL_SLAVE_EN)         , SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA    ) \
+                                                                       | P_Fld(  0                            , SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA   ) \
+                                                                       | P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA));
+      vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1)        , P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) \
+                                                                       | P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) \
+                                                                       | P_Fld(  0                            , SHU_CA_DLL1_RG_ARDLL_PGAIN_CA        ) \
+                                                                       | P_Fld(  1                            , SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA      ) \
+                                                                       | P_Fld(  1                            , SHU_CA_DLL1_RG_ARDLL_PHDIV_CA        ) \
+                                                                       | P_Fld(  1                            , SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA      ) \
+                                                                       | P_Fld(  1                            , SHU_CA_DLL1_RG_ARDLL_PS_EN_CA        ) \
+                                                                       | P_Fld(  !(a_cfg->ALL_SLAVE_EN)       , SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA    ));
+      DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    } else {
+      DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL0)        , P_Fld( (p->frequency>=2133)?(6+u1Gain):(7+u1Gain), SHU_CA_DLL0_RG_ARDLL_GAIN_CA         ) \
+                                                                       | P_Fld( (a_cfg->ALL_SLAVE_EN == 0)?9:7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA      ) \
+                                                                       | P_Fld(!(a_cfg->ALL_SLAVE_EN)         , SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA    ) \
+                                                                       | P_Fld(  0                            , SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA   ) \
+                                                                       | P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA));
+      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1)        , P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) \
+                                                                       | P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) \
+                                                                       | P_Fld(  0                            , SHU_CA_DLL1_RG_ARDLL_PGAIN_CA        ) \
+                                                                       | P_Fld(  1                            , SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA      ) \
+                                                                       | P_Fld(  1                            , SHU_CA_DLL1_RG_ARDLL_PHDIV_CA        ) \
+                                                                       | P_Fld(  1                            , SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA      ) \
+                                                                       | P_Fld(  1                            , SHU_CA_DLL1_RG_ARDLL_PS_EN_CA        ) \
+                                                                       | P_Fld(!(a_cfg->ALL_SLAVE_EN)         , SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA    ));
+
+      vSetPHY2ChannelMapping(p, CHANNEL_B);
+
+      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL0)        , P_Fld(  7+u1Gain                     , SHU_CA_DLL0_RG_ARDLL_GAIN_CA         ) \
+                                                                       | P_Fld(  7                     , SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA      ) \
+                                                                       | P_Fld(  0                     , SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA    ) \
+                                                                       | P_Fld(  0                     , SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA   ) \
+                                                                       | P_Fld(  1                     , SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA));
+      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1)        , P_Fld(  1                     , SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) \
+                                                                       | P_Fld(  1                     , SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) \
+                                                                       | P_Fld(  0                     , SHU_CA_DLL1_RG_ARDLL_PGAIN_CA        ) \
+                                                                       | P_Fld(  1                     , SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA      ) \
+                                                                       | P_Fld(  1                     , SHU_CA_DLL1_RG_ARDLL_PHDIV_CA        ) \
+                                                                       | P_Fld(  1                     , SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA      ) \
+                                                                       | P_Fld(  1                     , SHU_CA_DLL1_RG_ARDLL_PS_EN_CA        ) \
+                                                                       | P_Fld(  0                     , SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA    ));
+
+      #if (CHANNEL_NUM>2)
+          if (channel_num_auxadc > 2) {
+		      vSetPHY2ChannelMapping(p, CHANNEL_C);
+
+		      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL0)        , P_Fld( (p->frequency>=2133)?(6+u1Gain):(7+u1Gain), SHU_CA_DLL0_RG_ARDLL_GAIN_CA         )
+        		                                                               | P_Fld( (a_cfg->ALL_SLAVE_EN == 0)?9:7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA      )
+                		                                                       | P_Fld(!(a_cfg->ALL_SLAVE_EN)         , SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA    )
+                        		                                               | P_Fld(  0                            , SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA   )
+                                		                                       | P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA));
+		      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1)        , P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA)
+        		                                                               | P_Fld(  a_cfg->ALL_SLAVE_EN          , SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA)
+                		                                                       | P_Fld(  0                            , SHU_CA_DLL1_RG_ARDLL_PGAIN_CA        )
+                        		                                               | P_Fld(  1                            , SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA      )
+                                		                                       | P_Fld(  1                            , SHU_CA_DLL1_RG_ARDLL_PHDIV_CA        )
+                                        		                               | P_Fld(  1                            , SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA      )
+                                                		                       | P_Fld(  1                            , SHU_CA_DLL1_RG_ARDLL_PS_EN_CA        )
+                                                        		               | P_Fld(!(a_cfg->ALL_SLAVE_EN)         , SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA    ));
+
+		      vSetPHY2ChannelMapping(p, CHANNEL_D);
+
+		      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL0)        , P_Fld(  7+u1Gain                     , SHU_CA_DLL0_RG_ARDLL_GAIN_CA         )
+        		                                                               | P_Fld(  7                     , SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA      )
+                		                                                       | P_Fld(  0                     , SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA    )
+                        		                                               | P_Fld(  0                     , SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA   )
+                                		                                       | P_Fld(  1                     , SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA));
+		      vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1)        , P_Fld(  1                     , SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA)
+        		                                                               | P_Fld(  1                     , SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA)
+                		                                                       | P_Fld(  0                     , SHU_CA_DLL1_RG_ARDLL_PGAIN_CA        )
+                        		                                               | P_Fld(  1                     , SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA      )
+                                		                                       | P_Fld(  1                     , SHU_CA_DLL1_RG_ARDLL_PHDIV_CA        )
+                                        		                               | P_Fld(  1                     , SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA      )
+                                                		                       | P_Fld(  1                     , SHU_CA_DLL1_RG_ARDLL_PS_EN_CA        )
+                                                        		               | P_Fld(  0                     , SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA    ));
+          	}
+      #endif
+
+      vSetPHY2ChannelMapping(p, CHANNEL_A);
+
+      DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+}
+
+    mcSHOW_DBG_MSG6(("<<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL\n"));
+}
+
+static void ANA_ARPI_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,ANA_DVFS_CORE_T *tr)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+    //B0
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI3)   , P_Fld(  !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0  ) \
+                                                                     | P_Fld(  !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0      ) \
+                                                                     | P_Fld(  !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0     ) \
+                                                                     | P_Fld(  !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0     ) \
+                                                                     | P_Fld(  !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0      ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI3)   , P_Fld((!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN))) && (a_cfg->NEW_RANK_MODE), SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0    ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ2)         , P_Fld(  1          , SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU    ) \
+                                                                     | P_Fld(  1          , SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0   ) \
+                                                                     | P_Fld(  1          , SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0      ) \
+                                                                     | P_Fld(  1          , SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0     ) \
+                                                                     | P_Fld(  1          , SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0     ) \
+                                                                     | P_Fld(  1          , SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0      ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7)         , P_Fld(  0          , SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0    ) \
+                                                                     | P_Fld(  0          , SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0   ) \
+                                                                     | P_Fld(  0          , SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0   ));
+
+    //B1
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3)   , P_Fld(  !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1  ) \
+                                                                     | P_Fld(  !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1      ) \
+                                                                     | P_Fld(  !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1     ) \
+                                                                     | P_Fld(  !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1     ) \
+                                                                     | P_Fld(  !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1      ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3)   , P_Fld((!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN))) && (a_cfg->NEW_RANK_MODE), SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1    ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ2)         , P_Fld(  1          , SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU    ) \
+                                                                     | P_Fld(  1          , SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1   ) \
+                                                                     | P_Fld(  1          , SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1      ) \
+                                                                     | P_Fld(  1          , SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1     ) \
+                                                                     | P_Fld(  1          , SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1     ) \
+                                                                     | P_Fld(  !isLP4_DSC          , SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1      ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7)         , P_Fld(  0          , SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1    ) \
+                                                                     | P_Fld(  0          , SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1   ) \
+                                                                     | P_Fld(  0          , SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1   ));
+
+
+    //CA
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3)   , P_Fld(  isLP4_DSC&&(!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN))), SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN     ) \
+                                                                     | P_Fld(  (!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN))), SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN        ) \
+                                                                     | P_Fld(  (!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN))), SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN         ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3)   , P_Fld((!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN))) && (a_cfg->NEW_RANK_MODE), SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA    ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD2)        , P_Fld(  1          , SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU   ) \
+                                                                     | P_Fld(  1          , SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA  ) \
+                                                                     | P_Fld(  1          , SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA     ) \
+                                                                     | P_Fld(  1          , SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA    ) \
+                                                                     | P_Fld(  1          , SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA     ) \
+                                                                     | P_Fld(  isLP4_DSC          , SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA     ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD7)        , P_Fld(  0          , SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW      ) \
+                                                                     | P_Fld(  0          , SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW     ));
+}
+//==========================
+//ANA_TX_CONFIG
+//==========================
+static void ANA_TX_nonshuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6)       , P_Fld(0                            , CA_CMD6_RG_TX_ARCMD_DDR3_SEL         ) \
+                                                                | P_Fld(0                            , CA_CMD6_RG_TX_ARCMD_DDR4_SEL         ) \
+                                                                | P_Fld(1                            , CA_CMD6_RG_TX_ARCMD_LP4_SEL          ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)        , P_Fld(0                            , B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0        ) \
+                                                                | P_Fld(!(a_cfg->LP45_APHY_COMB_EN)  , B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0        ) \
+                                                                | P_Fld(a_cfg->LP45_APHY_COMB_EN     , B0_DQ6_RG_TX_ARDQ_LP4_SEL_B0         ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)        , P_Fld(0                            , B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1        ) \
+                                                                | P_Fld(!(a_cfg->LP45_APHY_COMB_EN)  , B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1        ) \
+                                                                | P_Fld(a_cfg->LP45_APHY_COMB_EN     , B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1         ));
+    mcSHOW_DBG_MSG6(("<<<<<< [CONFIGURE PHASE]: ANA_TX\n"));
+    //enable TX OE
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2)        , P_Fld(0                      , B0_DQ2_RG_TX_ARDQ_OE_DIS_B0          ) \
+                                                                | P_Fld(0                      , B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0       ) \
+                                                                | P_Fld(0                      , B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0        ) \
+                                                                | P_Fld(0                      , B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B0     )
+                                                                | P_Fld(0                      , B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0        ) \
+                                                                | P_Fld(0                      , B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0     ));
+    if(isLP4_DSC)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld(0, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA) \
+                                                       | P_Fld(0, CA_CMD2_RG_TX_ARCMD_ODTEN_DIS_CA) \
+                                                       | P_Fld(0, CA_CMD2_RG_TX_ARCLK_OE_DIS_CA) \
+                                                       | P_Fld(0, CA_CMD2_RG_TX_ARCLK_ODTEN_DIS_CA) \
+                                                       | P_Fld(0, CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA) \
+                                                       | P_Fld(1, CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA) \
+                                                       | P_Fld(0, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) \
+                                                       | P_Fld(0, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),  P_Fld(1, B1_DQ2_RG_TX_ARDQ_OE_DIS_B1) \
+                                                       | P_Fld(0, B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1) \
+                                                       | P_Fld(0, B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1) \
+                                                       | P_Fld(0, B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1) \
+                                                       | P_Fld(0, B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1        ) \
+                                                       | P_Fld(0, B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1     ) \
+                                                       | P_Fld(1, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1) \
+                                                       | P_Fld(1, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1)
+                                                       | P_Fld(0, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1) \
+                                                       | P_Fld(0xff, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_TX_CKE_CTRL), P_Fld(1, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_SEL_B1) \
+                                                       | P_Fld(1, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_EN_B1) \
+                                                       | P_Fld(1, B1_TX_CKE_CTRL_RG_TX_ARCS1_OE_TIE_EN_B1)) ;
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld(1, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA) \
+                                                       | P_Fld(0, CA_CMD2_RG_TX_ARCMD_ODTEN_DIS_CA) \
+                                                       | P_Fld(0, CA_CMD2_RG_TX_ARCLK_OE_DIS_CA) \
+                                                       | P_Fld(0, CA_CMD2_RG_TX_ARCLK_ODTEN_DIS_CA) \
+                                                       | P_Fld(1, CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA) \
+                                                       | P_Fld(1, CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA) \
+                                                       | P_Fld(0, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) \
+                                                       | P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),  P_Fld(0, B1_DQ2_RG_TX_ARDQ_OE_DIS_B1) \
+                                                       | P_Fld(0, B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1) \
+                                                       | P_Fld(0, B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1) \
+                                                       | P_Fld(0, B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1) \
+                                                       | P_Fld(0, B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1        ) \
+                                                       | P_Fld(0, B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1     ) \
+                                                       | P_Fld(0, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1) \
+                                                       | P_Fld(0, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1)
+                                                       | P_Fld(0, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1) \
+                                                       | P_Fld(0, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1));
+
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_TX_ARCS_CTRL),P_Fld(1, CA_TX_ARCS_CTRL_RG_TX_ARCS_OE_TIE_SEL_C0)) ;
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_TX_ARDQ_CTRL), P_Fld(1, CA_TX_ARDQ_CTRL_RG_TX_ARDQ6_OE_TIE_EN_C0) \
+                                                       | P_Fld(1, CA_TX_ARDQ_CTRL_RG_TX_ARDQ7_OE_TIE_EN_C0)) ; //Sync MP setting WL C0 DQ6 and DQ7 is no use
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_TX_CKE_CTRL), P_Fld(1, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_EN_B1) \
+                                                       | P_Fld(1, B1_TX_CKE_CTRL_RG_TX_ARCS1_OE_TIE_EN_B1)) ; //Sync MP setting WL EMCP: B1 CS1 and CKE is no use
+    }
+
+
+    //enable TX & reset
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD3)       , P_Fld(1                      , CA_CMD3_RG_TX_ARCMD_EN               ) \
+                                                                | P_Fld(1                      , CA_CMD3_RG_ARCMD_RESETB              ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3)        , P_Fld(1                      , B0_DQ3_RG_ARDQ_RESETB_B0             ) \
+                                                                | P_Fld(1                      , B0_DQ3_RG_TX_ARDQ_EN_B0              ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3)        , P_Fld(1                      , B1_DQ3_RG_ARDQ_RESETB_B1             ) \
+                                                                | P_Fld(1                      , B1_DQ3_RG_TX_ARDQ_EN_B1              ));
+}
+
+static void ANA_TX_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 group_id)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    //ODTEN & DQS control
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13)  , P_Fld(isLP4_DSC                      , SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA        ) \
+                                                                | P_Fld(isLP4_DSC                      , SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA         )
+                                                                | P_Fld(0           , SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_EN_CA           )
+                                                                | P_Fld(0           , SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_EN_CA         )
+                                                                | P_Fld(0           , SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_DATA_TIE_EN_CA  )
+                                                                | P_Fld(0           , SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA )
+                                                                | P_Fld((a_cfg->TX_ODT_DIS & isLP4_DSC)      , SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA              ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13)   , P_Fld(1                      , SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0         )
+                                                                | P_Fld(1                      , SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0         )
+                                                                | P_Fld(0           , SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0           )
+                                                                | P_Fld(0           , SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0          )
+                                                                | P_Fld(0           , SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0  )
+                                                                | P_Fld(0           , SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0 )
+                                                                | P_Fld(a_cfg->TX_ODT_DIS      , SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0              ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13)   , P_Fld(!isLP4_DSC                      , SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1         )
+                                                                | P_Fld(!isLP4_DSC                      , SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1         )
+                                                                | P_Fld(0           , SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1           )
+                                                                | P_Fld(0           , SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1          )
+                                                                | P_Fld(0           , SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1  )
+                                                                | P_Fld(0           , SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1 )
+                                                                | P_Fld((a_cfg->TX_ODT_DIS & !isLP4_DSC)     , SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1              ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD14)  , P_Fld(isLP4_DSC                      , SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA         ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ14)   , P_Fld(1                      , SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0          ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ14)   , P_Fld(!isLP4_DSC                      , SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1          ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13)   , P_Fld((LPDDR5_EN_S) ? 2 : 0  , SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0           ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13)   , P_Fld((LPDDR5_EN_S) ? 2 : 0  , SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1           ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ14)   , P_Fld(  0                    , SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0               ) \
+                                                                | P_Fld(  0                    , SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0              ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ14)   , P_Fld(  0                    , SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1               ) \
+                                                                | P_Fld(  0                    , SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1              ));
+
+    //B0
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13), P_Fld(a_cfg->NEW_RANK_MODE, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ2), P_Fld(a_cfg->NEW_RANK_MODE, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0) \
+                                                            | P_Fld(a_cfg->NEW_RANK_MODE, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0));
+    if(!isLP4_DSC)
+    {
+    //B1
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), P_Fld(a_cfg->NEW_RANK_MODE, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ2), P_Fld(a_cfg->NEW_RANK_MODE, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) \
+                                                            | P_Fld(a_cfg->NEW_RANK_MODE, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1));
+    //CA
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld(0, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD2), P_Fld(0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) \
+                                                             | P_Fld(0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA));
+    }
+    else
+    {
+    //B1
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ2), P_Fld(0, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) \
+                                                            | P_Fld(0, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1));
+    //CA
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld(a_cfg->NEW_RANK_MODE, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD2), P_Fld(a_cfg->NEW_RANK_MODE, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) \
+                                                             | P_Fld(a_cfg->NEW_RANK_MODE, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA));
+    }
+
+
+#if SA_CONFIG_EN
+    // enable after runtime configs
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13)   , P_Fld( 0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0              ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ2)   , P_Fld( 0  , SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0              ));
+    if(!isLP4_DSC)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13)   , P_Fld( 0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1              ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ2)   , P_Fld( 0  , SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1              ));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13)  , P_Fld( 0, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA             ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD2)   , P_Fld( 0  , SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA              ));
+    }
+#endif
+}
+
+static void ANA_RX_shuffle_config(DRAMC_CTX_T *p,U8 group_id)
+{
+
+    U8 RDQS_SE_EN        ;
+    U8 DQSIEN_MODE       ;
+    U8 NEW_RANK_MODE     ;
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+#if (ENABLE_LP4Y_DFS && LP4Y_BACKUP_SOLUTION)
+    RDQS_SE_EN        = DFS(group_id)->data_rate<=1600 ? 1 : 0;
+#else
+    RDQS_SE_EN        = 0; //TODO for LPDDR5
+#endif
+    DQSIEN_MODE       = DFS(group_id)->DQSIEN_MODE;
+    NEW_RANK_MODE     = A_T->NEW_RANK_MODE;
+
+    //B0
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10)   , P_Fld(  RDQS_SE_EN           , SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0                 ) \
+                                                                | P_Fld(DQSIEN_MODE            , SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0           ) \
+                                                                | P_Fld(1                      , SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0            ) \
+                                                                | P_Fld(NEW_RANK_MODE          , SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0       ) \
+                                                                | P_Fld(NEW_RANK_MODE          , SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11)   , P_Fld(NEW_RANK_MODE          , SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0        ) \
+                                                                | P_Fld(NEW_RANK_MODE          , SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0        ) );
+
+    if(isLP4_DSC){
+    //CA
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD10)   , P_Fld(  RDQS_SE_EN           , SHU_CA_CMD10_RG_RX_ARCLK_SE_EN_CA                 ) \
+                                                                | P_Fld(DQSIEN_MODE            , SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_MODE_CA           ) \
+                                                                | P_Fld(1                      , SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA            ) \
+                                                                | P_Fld(NEW_RANK_MODE          , SHU_CA_CMD10_RG_RX_ARCLK_RANK_SEL_LAT_EN_CA       ) \
+                                                                | P_Fld(NEW_RANK_MODE          , SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_RANK_SEL_LAT_EN_CA));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11)   , P_Fld(NEW_RANK_MODE          , SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA        ) \
+                                                                | P_Fld(NEW_RANK_MODE          , SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA        ));
+    }
+    else
+    {
+    //B1
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10)   , P_Fld(  RDQS_SE_EN           , SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1                 ) \
+                                                                | P_Fld(DQSIEN_MODE            , SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1           ) \
+                                                                | P_Fld(1                      , SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1            ) \
+                                                                | P_Fld(NEW_RANK_MODE          , SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1       ) \
+                                                                | P_Fld(NEW_RANK_MODE          , SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11)   , P_Fld(NEW_RANK_MODE          , SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1        ) \
+                                                                | P_Fld(NEW_RANK_MODE          , SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1        ));
+    }
+    #if SA_CONFIG_EN
+    // enable after runtime configs
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10)   , P_Fld( 0  , SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0              ));
+
+    if(isLP4_DSC){
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD10)   , P_Fld( 0  , SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA              ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10)    , P_Fld(1, SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1              )\
+                                                                | P_Fld(1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1            ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11)   , P_Fld(1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1              ));
+    }
+    else
+    {
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10)   , P_Fld( 0  , SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1              ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD10)    , P_Fld(1, SHU_CA_CMD10_RG_RX_ARCLK_RANK_SEL_LAT_EN_CA              )\
+                                                                | P_Fld(1, SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_RANK_SEL_LAT_EN_CA            ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11)   , P_Fld(1, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA              ));
+    }
+    #endif
+}
+
+
+static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    //B0
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5)        , P_Fld( 1                     , B0_DQ5_RG_RX_ARDQ_VREF_EN_B0                     ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)        , P_Fld( 0                     , B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0                    ) \
+                                                                | P_Fld( 1                     , B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0                    ) \
+                                                                | P_Fld( 0                     , B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0               ) \
+                                                                | P_Fld( 1                     , B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0                     ) \
+                                                                | P_Fld( 0                     , B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0               ) \
+                                                                | P_Fld( 1                     , B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0                 ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3)        , P_Fld( 1                     , B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0                 ) \
+                                                                | P_Fld( 1                     , B0_DQ3_RG_RX_ARDQ_SMT_EN_B0                      ));
+
+    //B1
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5)        , P_Fld( (!isLP4_DSC)                     , B1_DQ5_RG_RX_ARDQ_VREF_EN_B1                     ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)        , P_Fld( 0                     , B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1                    ) \
+                                                                | P_Fld( (!isLP4_DSC)                     , B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1                    ) \
+                                                                | P_Fld( 0                     , B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1               ) \
+                                                                | P_Fld( (!isLP4_DSC)                     , B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1                     ) \
+                                                                | P_Fld( 0                     , B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1               ) \
+                                                                | P_Fld( (!isLP4_DSC)                     , B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1                 ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3)        , P_Fld( (!isLP4_DSC)                     , B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1                 ) \
+                                                                | P_Fld( (!isLP4_DSC)                     , B1_DQ3_RG_RX_ARDQ_SMT_EN_B1                      ));
+
+    //CA
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD5), P_Fld(isLP4_DSC, CA_CMD5_RG_RX_ARCMD_VREF_EN));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6)       , P_Fld( 0                     , CA_CMD6_RG_RX_ARCMD_DDR3_SEL                     ) \
+                                                                | P_Fld( isLP4_DSC                     , CA_CMD6_RG_RX_ARCMD_DDR4_SEL                     ) \
+                                                                | P_Fld( 0                     , CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL                ) \
+                                                                | P_Fld( isLP4_DSC                     , CA_CMD6_RG_RX_ARCMD_BIAS_EN                     ) \
+                                                                | P_Fld( 0                     , CA_CMD6_RG_RX_ARCMD_OP_BIAS_SW_EN                ) \
+                                                                | P_Fld( isLP4_DSC                     , CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN                  ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD3), P_Fld(isLP4_DSC, CA_CMD3_RG_RX_ARCMD_STBENCMP_EN) \
+                                                         | P_Fld(isLP4_DSC, CA_CMD3_RG_RX_ARCMD_SMT_EN));
+
+    //RX reset
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9)       , P_Fld( 1                     , CA_CMD9_RG_RX_ARCMD_STBEN_RESETB                 ) \
+                                                                | P_Fld( 1                     , CA_CMD9_RG_RX_ARCLK_STBEN_RESETB                 ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9)        , P_Fld( 1                     , B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0                ) \
+                                                                | P_Fld( 1                     , B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0              ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9)        , P_Fld( 1                     , B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1                ) \
+                                                                | P_Fld( 1                     , B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1              ));
+
+    //Justin confirm that: All set 1  for improving internal timing option
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD8)       , P_Fld( 1                     , CA_CMD8_RG_RX_ARCLK_SER_RST_MODE                 ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ8)        , P_Fld( 1                     , B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0               ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ8)        , P_Fld( 1                     , B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1               ));
+
+}
+
+//============================================
+// RESET
+//============================================
+void RESETB_PULL_DN(DRAMC_CTX_T *p)
+{
+    mcSHOW_DBG_MSG6(("============ PULL DRAM RESETB DOWN ============\n"));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD11)      , P_Fld( 1                     , CA_CMD11_RG_RRESETB_DRVP         ) \
+                                                                | P_Fld( 1                     , CA_CMD11_RG_RRESETB_DRVN         ) \
+                                                                | P_Fld( 1                     , CA_CMD11_RG_TX_RRESETB_DDR3_SEL  ) \
+                                                                | P_Fld( 1                     , CA_CMD11_RG_TX_RRESETB_PULL_DN   ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1)    , P_Fld( 1                     , MISC_CTRL1_R_DMRRESETB_I_OPT     ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1)    , P_Fld( 1                     , MISC_CTRL1_R_DMDA_RRESETB_E      ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD11)      , P_Fld( 0                     , CA_CMD11_RG_TX_RRESETB_PULL_DN   ));
+    mcSHOW_DBG_MSG6(("========== PULL DRAM RESETB DOWN end =========\n"));
+}
+//============================================
+// SUSPEND_OFF_control
+//============================================
+static void SUSPEND_ON(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_LP_CTRL0)   , P_Fld( 0                     , B0_LP_CTRL0_RG_ARDMSUS_10_B0     ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_LP_CTRL0)   , P_Fld( 0                     , B1_LP_CTRL0_RG_ARDMSUS_10_B1     ));
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_LP_CTRL0)   , P_Fld( 0                     , CA_LP_CTRL0_RG_ARDMSUS_10_CA     ));
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+}
+//============================================
+// SPM_control
+//============================================
+static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_LP_CTRL), P_Fld( 1                  , MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL            ) \
+                                                              | P_Fld( 1                  , MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL         ) \
+                                                              | P_Fld( 1                  , MISC_LP_CTRL_RG_RRESETB_LP_SEL               ) \
+                                                              | P_Fld( 1                  , MISC_LP_CTRL_RG_RPHYPLL_RESETB_LP_SEL        ) \
+                                                              | P_Fld( 1                  , MISC_LP_CTRL_RG_RPHYPLL_EN_LP_SEL            ) \
+                                                              | P_Fld( 1                  , MISC_LP_CTRL_RG_RCLRPLL_EN_LP_SEL            ) \
+                                                              | P_Fld( 1                  , MISC_LP_CTRL_RG_RPHYPLL_ADA_MCK8X_EN_LP_SEL  ) \
+                                                              | P_Fld( 1                  , MISC_LP_CTRL_RG_RPHYPLL_AD_MCK8X_EN_LP_SEL   ) \
+                                                              | P_Fld( 1                  , MISC_LP_CTRL_RG_RPHYPLL_TOP_REV_0_LP_SEL     ) \
+                                                              | P_Fld( 1                  , MISC_LP_CTRL_RG_RPHYPLL_DDR400_EN_LP_SEL     ) \
+                                                              | P_Fld( 1                  , MISC_LP_CTRL_RG_AD_MCK8X_OP_LP_SEL     ) \
+                                                              | P_Fld( 1                  , MISC_LP_CTRL_RG_ADA_MCK8X_OP_LP_SEL     ) \
+                                                              | P_Fld( a_cfg->NEW_8X_MODE , MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL ) \
+                                                              | P_Fld( a_cfg->NEW_8X_MODE , MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL      ) \
+                                                              | P_Fld( a_cfg->NEW_8X_MODE , MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL       ) \
+                                                              | P_Fld( a_cfg->NEW_8X_MODE , MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL       ) \
+                                                              | P_Fld( a_cfg->NEW_8X_MODE , MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL) \
+                                                              | P_Fld( a_cfg->NEW_8X_MODE , MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL          ) \
+                                                              | P_Fld( a_cfg->NEW_8X_MODE , MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL      ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_LP_CTRL0) , P_Fld( 1                  , B0_LP_CTRL0_RG_ARDMSUS_10_B0_LP_SEL          ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_RG_ARDQ_RESETB_B0_LP_SEL         ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_RG_ARPI_RESETB_B0_LP_SEL         ) \
+                                                              | P_Fld( 0                  , B0_LP_CTRL0_RG_B0_MS_SLV_LP_SEL              ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_RG_ARDLL_PHDET_EN_B0_LP_SEL      ) \
+                                                              | P_Fld( 0                  , B0_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B0_LP_SEL     ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_DA_ARPI_CG_MCK_B0_LP_SEL         ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B0_LP_SEL  ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_DA_ARPI_CG_MCTL_B0_LP_SEL        ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_DA_ARPI_CG_FB_B0_LP_SEL          ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_DA_ARPI_CG_DQ_B0_LP_SEL          ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_DA_ARPI_CG_DQM_B0_LP_SEL         ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_DA_ARPI_CG_DQS_B0_LP_SEL         ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_DA_ARPI_CG_DQSIEN_B0_LP_SEL      ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_DA_ARPI_MPDIV_CG_B0_LP_SEL       ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B0_LP_SEL     ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_DA_ARPI_MIDPI_EN_B0_LP_SEL       ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B0_LP_SEL)
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_RG_MIDPI_CKDIV4_EN_B0_OP_LP_SEL     ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_RG_MIDPI_EN_B0_OP_LP_SEL     ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_RG_ARPI_DDR400_EN_B0_LP_SEL     ) \
+                                                              | P_Fld( 1                  , B0_LP_CTRL0_RG_B0_DLL_EN_OP_SEQ_LP_SEL     ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_LP_CTRL0) , P_Fld( 1                  , B1_LP_CTRL0_RG_ARDMSUS_10_B1_LP_SEL          ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_RG_ARDQ_RESETB_B1_LP_SEL         ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_RG_ARPI_RESETB_B1_LP_SEL         ) \
+                                                              | P_Fld( 0                  , B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL              ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_RG_ARDLL_PHDET_EN_B1_LP_SEL      ) \
+                                                              | P_Fld( 0                  , B1_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B1_LP_SEL     ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_DA_ARPI_CG_MCK_B1_LP_SEL         ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B1_LP_SEL  ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_DA_ARPI_CG_MCTL_B1_LP_SEL        ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_DA_ARPI_CG_FB_B1_LP_SEL          ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_DA_ARPI_CG_DQ_B1_LP_SEL          ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_DA_ARPI_CG_DQM_B1_LP_SEL         ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_DA_ARPI_CG_DQS_B1_LP_SEL         ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_DA_ARPI_CG_DQSIEN_B1_LP_SEL      ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_DA_ARPI_MPDIV_CG_B1_LP_SEL       ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B1_LP_SEL     ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_DA_ARPI_MIDPI_EN_B1_LP_SEL       ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B1_LP_SEL)
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_RG_MIDPI_CKDIV4_EN_B1_OP_LP_SEL       ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_RG_MIDPI_EN_B1_OP_LP_SEL       ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_RG_ARPI_DDR400_EN_B1_LP_SEL       ) \
+                                                              | P_Fld( 1                  , B1_LP_CTRL0_RG_B1_DLL_EN_OP_SEQ_LP_SEL       ));
+
+
+        DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_LP_CTRL0) , P_Fld( 1                  , CA_LP_CTRL0_RG_ARDMSUS_10_CA_LP_SEL          ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_RG_ARCMD_RESETB_LP_SEL           ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_RG_ARPI_RESETB_CA_LP_SEL         ) \
+                                                              | P_Fld( 0                  , CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL         ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_RG_ARDLL_PHDET_EN_CA_LP_SEL      ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_RG_TX_ARCS_PULL_UP_LP_SEL        ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_RG_TX_ARCS_PULL_DN_LP_SEL        ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_RG_TX_ARCA_PULL_UP_LP_SEL        ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_RG_TX_ARCA_PULL_DN_LP_SEL        ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_DA_ARPI_CG_MCK_CA_LP_SEL         ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_CA_LP_SEL  ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_DA_ARPI_CG_MCTL_CA_LP_SEL        ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_DA_ARPI_CG_FB_CA_LP_SEL          ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_DA_ARPI_CG_CS_LP_SEL             ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_DA_ARPI_CG_CLK_LP_SEL            ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_DA_ARPI_CG_CMD_LP_SEL            ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_DA_ARPI_CG_CLKIEN_LP_SEL         ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_DA_ARPI_MPDIV_CG_CA_LP_SEL       ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_RG_RX_ARCMD_VREF_EN_LP_SEL       ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_DA_ARPI_MIDPI_EN_CA_LP_SEL       ) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_CA_LP_SEL) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_RG_MIDPI_CKDIV4_EN_CA_OP_LP_SEL) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_RG_MIDPI_EN_CA_OP_LP_SEL) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_RG_ARPI_DDR400_EN_CA_LP_SEL) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_RG_CA_DLL_EN_OP_SEQ_LP_SEL) \
+                                                              | P_Fld( 1                  , CA_LP_CTRL0_RG_DA_PICG_CA_CTRL_LOW_BY_LPC) \
+                                                              | P_Fld( 0 , CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL       )); //use CA as DQ set 1
+        DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+
+    REG_TRANSFER_T MS_SLV_LP_SEL_Reg;//TODO:check
+    if (isLP4_DSC){
+        MS_SLV_LP_SEL_Reg.u4Addr = DDRPHY_REG_B1_LP_CTRL0;
+        MS_SLV_LP_SEL_Reg.u4Fld = B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL;
+    }
+    else{
+        MS_SLV_LP_SEL_Reg.u4Addr = DDRPHY_REG_CA_LP_CTRL0;
+        MS_SLV_LP_SEL_Reg.u4Fld = CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL;
+    }
+
+    if(a_cfg->DLL_ASYNC_EN == 1)
+    {
+            DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+            vIO32WriteFldMulti_All(DRAMC_REG_ADDR(MS_SLV_LP_SEL_Reg.u4Addr), P_Fld(1, MS_SLV_LP_SEL_Reg.u4Fld));
+            DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+    else
+    {
+        DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_SLV_LP_SEL_Reg.u4Addr), P_Fld(1, MS_SLV_LP_SEL_Reg.u4Fld       ));
+        vSetPHY2ChannelMapping(p, CHANNEL_B);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_SLV_LP_SEL_Reg.u4Addr), P_Fld(0                , MS_SLV_LP_SEL_Reg.u4Fld       ));
+        #if (CHANNEL_NUM>2)
+			if (channel_num_auxadc > 2) {
+		        vSetPHY2ChannelMapping(p, CHANNEL_C);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_SLV_LP_SEL_Reg.u4Addr), P_Fld(1, MS_SLV_LP_SEL_Reg.u4Fld       ));
+    		    vSetPHY2ChannelMapping(p, CHANNEL_D);
+		        vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_SLV_LP_SEL_Reg.u4Addr), P_Fld(0                , MS_SLV_LP_SEL_Reg.u4Fld       ));
+				}
+        #endif
+        vSetPHY2ChannelMapping(p, CHANNEL_A);
+        DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+
+    //FOR DDR400 OPEN-LOOP MODE
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL9), P_Fld( 1           , MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN      ) \
+                                                               | P_Fld( 1           , MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN   ) \
+                                                               | P_Fld( 1           , MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF      ) \
+                                                               | P_Fld( 0           , MISC_CG_CTRL9_RG_DDR400_MCK4X_I_FORCE_ON    ) \
+                                                               | P_Fld( 1           , MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF       ) \
+                                                               | P_Fld( 1           , MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN   ) \
+                                                               | P_Fld( 1           , MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF      ) \
+                                                               | P_Fld( 0           , MISC_CG_CTRL9_RG_DDR400_MCK4X_Q_FORCE_ON    ) \
+                                                               | P_Fld( 1           , MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF       ));
+#if 0 // @Darren-, new APHY remove 45/135 phases
+                                                               | P_Fld( 1           , MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN   ) \
+                                                               | P_Fld( 1           , MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF      ) \
+                                                               | P_Fld( 0           , MISC_CG_CTRL9_RG_DDR400_MCK4X_O_FORCE_ON    ) \
+                                                               | P_Fld( 1           , MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF       ));
+#endif
+}
+
+static void DIG_DCM_nonshuffle_config(DRAMC_CTX_T *p)
+{
+    //RX DCM
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_CG_CTRL), P_Fld(3      , MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY          ));
+}
+
+static void DIG_PHY_SHU_MISC_CG_CTRL(DRAMC_CTX_T *p)
+{
+     //bit 0       : DPHY_NAO_GLUE_B0.mck_dq_cg_ctrl
+     //bit 1       : DPHY_NAO_GLUE_B1.mck_dq_cg_ctrl
+     //bit 2       : DPHY_NAO_GLUE_CA.mck_ca_cg_ctrl
+     //bit 4       : DPHY_NAO_GLUE_B0.rx_mck_dq_cg_ctrl
+     //bit 5       : DPHY_NAO_GLUE_B1.rx_mck_dq_cg_ctrl
+     //bit 6       : DPHY_NAO_GLUE_CA.rx_mck_ca_cg_ctrl
+     //bit [9 : 8] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle
+     //bit [11:10] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_dq
+     //bit [13:12] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_tx_cmd
+     //bit [17:16] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_tx_b0
+     //bit [19:18] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_tx_b1
+     //bit [22:20] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_rx_cmd
+     //bit [26:24] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_rx_b0
+     //bit [30:28] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_rx_b1
+
+//     vIO32Write4B      (DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_CG_CTRL0), 0x333f3f00);
+//     //1. ignore NAO_GLUE cg ctrl,
+//     2.00:ddrphy_idle/_ca/b0/b1 01: ddrphy_idle_shuopt 10: ddrphy_idle_shuopt_pinmux
+     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_CG_CTRL0), 0x33400000);//rx_cmd_idle tie 1 others DCM control depend on CA B0 B1 independtly -- could save more power
+}
+
+static void ANA_IMP_configure(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMP_CTRL1)  , P_Fld( 0, MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL                     ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMP_CTRL1)  , P_Fld( !(LPDDR5_EN_S), MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL   ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMP_CTRL1)  , P_Fld( 0, MISC_IMP_CTRL1_RG_RIMP_BIAS_EN                      ) \
+                                                                  | P_Fld( 0, MISC_IMP_CTRL1_RG_RIMP_ODT_EN                       ) \
+                                                                  | P_Fld( 0, MISC_IMP_CTRL1_RG_RIMP_PRE_EN                       ) \
+                                                                  | P_Fld( 0, MISC_IMP_CTRL1_RG_RIMP_VREF_EN                      ));
+}
+
+
+static void ANA_CLOCK_SWITCH(DRAMC_CTX_T *p)
+{
+    //OPENLOOP MODE. w_chg_mem_mck1x
+    if(A_D->DQ_CA_OPEN)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  1                , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1));
+        mcDELAY_XNS(100);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  0                , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1));
+    }
+    //mem_sel     _____|------------------------------------
+    //w_chg_mem   ______________|------------|______________
+    //BLCK        __|---|___|---|____________|-|_|-|_|-|_|-
+    //            |<-    26M  ->|<-  MUTE  ->|<-   MCK4X  ->|
+    //before DLL enable switch feedback clock
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL)     , P_Fld(  1                         , MISC_CKMUX_SEL_R_PHYCTRLDCM          ) \
+                                                                     | P_Fld(  1                         , MISC_CKMUX_SEL_R_PHYCTRLMUX          ));
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  1                         , MISC_CG_CTRL0_CLK_MEM_SEL            ) \
+                                                                     | P_Fld(  1                         , MISC_CG_CTRL0_W_CHG_MEM              ));
+
+    mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  0                         , MISC_CG_CTRL0_W_CHG_MEM              ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  1                         , MISC_CG_CTRL0_RG_FREERUN_MCK_CG      ));
+
+    //after clock change, if OPEN LOOP MODE should change clock to 1x.  bit7 is RG_dvfs_clk_mem_mck1x_sel
+    if(A_D->DQ_CA_OPEN)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  1                , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT7));
+    }
+}
+
+static void ANA_Config_nonshuffle(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
+{
+    #if !SA_CONFIG_EN
+    RESETB_PULL_DN(p);
+    #endif
+    SUSPEND_ON(p);
+    SPM_control(p,a_cfg);
+    ANA_TX_nonshuffle_config(p,a_cfg);
+    ANA_RX_nonshuffle_config(p);
+    DIG_DCM_nonshuffle_config(p);
+    ANA_IMP_configure(p);
+    ANA_DLL_non_shuffle_config(p,a_cfg);
+}
+
+void ANA_Config_shuffle(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 group_id)
+{
+    ANA_PLL_shuffle_Config(p,A_D->PLL_FREQ,DFS(group_id)->data_rate);
+    ANA_ARPI_shuffle_config(p,a_cfg,A_D);
+    ANA_TX_shuffle_config(p,a_cfg,group_id);
+    ANA_RX_shuffle_config(p,group_id);
+    DIG_PHY_SHU_MISC_CG_CTRL(p);
+    ANA_CLK_DIV_config_setting(p,A_D,a_cfg);
+    ANA_DLL_shuffle_Config(p,a_cfg);
+//    ANA_sequence_shuffle_colletion(p,&ana_core_p);
+}
+
+static void ANA_PHY_Config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
+{
+    //RESET DPM
+    //vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_MD32_REG_SSPM_CFGREG_SW_RSTN), 32'h1000_0001 );
+
+//    SC_DPY_MODE_SW(PULL_UP);
+    ANA_Config_nonshuffle(p,a_cfg);
+    ANA_Config_shuffle(p,a_cfg,0);
+}
+
+
+static void ANA_PLL_sequence(DRAMC_CTX_T *p)
+{
+    mcSHOW_DBG_MSG6(("[ANA_INIT] PLL >>>>>>>> \n"));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2)    , P_Fld(1, PHYPLL2_RG_RPHYPLL_RESETB                ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL0)    , P_Fld(1, PHYPLL0_RG_RPHYPLL_EN                    ));
+    mcDELAY_XUS(20);
+    mcSHOW_DBG_MSG6(("[ANA_INIT] PLL <<<<<<<< \n"));
+}
+
+static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    mcSHOW_DBG_MSG6(("[ANA_INIT] MIDPI >>>>>>>> \n"));
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ1)   , 1, SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0   );
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1)   , 1, SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1   );
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1)  , 1, SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA   );
+
+    //ASVA 2-6
+    //step1: CG high. --disable 8 phase clk output
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2)   , P_Fld(  1         , SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0   ) \
+                                                                     | P_Fld(  1         , SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0      ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2)   , P_Fld(  1         , SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1   ) \
+                                                                     | P_Fld(  1         , SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1      ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2)   , P_Fld(  1         , SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA   ) \
+                                                                     | P_Fld(  1         , SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA      ));
+
+    //CG
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
+                | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
+                | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
+                | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0)
+                | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0)
+                | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0)
+                | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0)
+                | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0)
+                | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2), P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1)
+                | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1)
+                | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1)
+                | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1)
+                | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1)
+                | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1)
+                | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1)
+                | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1)
+                | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2), P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA)
+                | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA)
+                | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA)
+                | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA)
+                | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS)
+                | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK)
+                | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD)
+                | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN)
+                | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA));
+
+    //step2:PLLGP_CK_SEL -- Initial no need it
+    //step3: PLLCK_EN disable
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2)           , P_Fld(  0         , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU     ));  //refer to MISC_DVFSCTRL2
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2)            , P_Fld(  0         , PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN           ) \
+                                                                     | P_Fld(  0         , PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN          ));
+    //step4:MIDPI_EN
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ1)             , P_Fld((!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)))&&(!(tr->DQ_CKDIV4_EN)), SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0         ) \
+                                                                         | P_Fld((!(tr->DQ_SEMI_OPEN))&&(tr->DQ_CKDIV4_EN), SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0     ) \
+                                                                         | P_Fld(   tr->PH8_DLY     , SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0    ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_SHU_MIDPI_CTRL), P_Fld( (!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)))&&(!(tr->DQ_CKDIV4_EN)), B0_SHU_MIDPI_CTRL_MIDPI_ENABLE_B0) \
+                                                                     | P_Fld( (!(tr->DQ_SEMI_OPEN))&&(tr->DQ_CKDIV4_EN), B0_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B0));
+
+    if (!isLP4_DSC)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1)             , P_Fld((!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)))&&(!(tr->DQ_CKDIV4_EN)), SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1         ) \
+                                                                         | P_Fld((!(tr->DQ_SEMI_OPEN))&&(tr->DQ_CKDIV4_EN), SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1     )
+                                                                         | P_Fld(   tr->PH8_DLY     , SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1    ));
+
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_SHU_MIDPI_CTRL), P_Fld((!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)))&&(!(tr->DQ_CKDIV4_EN)), B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1) \
+                                                                         | P_Fld((!(tr->DQ_SEMI_OPEN))&&(tr->DQ_CKDIV4_EN), B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1));
+
+
+    }
+    else// for DSC semi-open CHA B1 and CHB B1 is different
+    {
+        DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1)             , P_Fld((!tr->DQ_CA_OPEN)&&(!(tr->CA_CKDIV4_EN)), SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1         ) \
+                                                                         | P_Fld((tr->CA_CKDIV4_EN), SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1     )
+                                                                         | P_Fld(   tr->PH8_DLY     , SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1    ));
+        //vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1)        , P_Fld(   tr->CA_PREDIV_EN , SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_SHU_MIDPI_CTRL), P_Fld((!tr->DQ_CA_OPEN)&&(!(tr->CA_CKDIV4_EN)), B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1) \
+                                                                         | P_Fld((tr->CA_CKDIV4_EN), B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1));
+
+        vSetPHY2ChannelMapping(p, CHANNEL_B);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1)             , P_Fld((!((tr->CA_SEMI_OPEN)||(tr->DQ_CA_OPEN)))&&(!(tr->CA_CKDIV4_EN)), SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1         ) \
+                                                                         | P_Fld((!(tr->CA_SEMI_OPEN))&&(tr->CA_CKDIV4_EN), SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1     )
+                                                                         | P_Fld(   tr->PH8_DLY     , SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1    ));
+        //vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1)        , P_Fld(   tr->CA_PREDIV_EN , SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_SHU_MIDPI_CTRL), P_Fld((!((tr->CA_SEMI_OPEN)||(tr->DQ_CA_OPEN)))&&(!(tr->CA_CKDIV4_EN)), B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1) \
+                                                                         | P_Fld((!(tr->CA_SEMI_OPEN))&&(tr->CA_CKDIV4_EN), B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1));
+#if (CHANNEL_NUM > 2)
+		if (channel_num_auxadc > 2) {
+	        vSetPHY2ChannelMapping(p, CHANNEL_C);
+    	    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1)       , P_Fld((!tr->DQ_CA_OPEN)&&(!(tr->CA_CKDIV4_EN)), SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1         ) \
+                                                                            | P_Fld((tr->CA_CKDIV4_EN), SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1     )
+        		                                                            | P_Fld(   tr->PH8_DLY     , SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1    ));
+	        //vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1)      , P_Fld(   tr->CA_PREDIV_EN , SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1));
+	        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_SHU_MIDPI_CTRL), P_Fld((!tr->DQ_CA_OPEN)&&(!(tr->CA_CKDIV4_EN)), B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1) \
+    	           	                                                        | P_Fld((tr->CA_CKDIV4_EN), B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1));
+        	vSetPHY2ChannelMapping(p, CHANNEL_D);
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1)       , P_Fld((!((tr->CA_SEMI_OPEN)||(tr->DQ_CA_OPEN)))&&(!(tr->CA_CKDIV4_EN)), SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1         ) \
+            	                                                            | P_Fld((!(tr->CA_SEMI_OPEN))&&(tr->CA_CKDIV4_EN), SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1     )
+                	                                                        | P_Fld(   tr->PH8_DLY     , SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1    ));
+	        //vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1)      , P_Fld(   tr->CA_PREDIV_EN , SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1));
+    	    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_SHU_MIDPI_CTRL), P_Fld((!((tr->CA_SEMI_OPEN)||(tr->DQ_CA_OPEN)))&&(!(tr->CA_CKDIV4_EN)), B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1) \
+        	                                                                | P_Fld((!(tr->CA_SEMI_OPEN))&&(tr->CA_CKDIV4_EN), B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1));
+			}
+#endif
+        vSetPHY2ChannelMapping(p, CHANNEL_A);
+        DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+
+    // for both EMCP and DSC semi-open CHA CA and CHB CA settings are needed
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1)        , P_Fld( (!(tr->DQ_CA_OPEN))&&(!(tr->CA_CKDIV4_EN)), SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA        ) \
+                                                                     | P_Fld(   tr->CA_CKDIV4_EN , SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA )
+                                                                     | P_Fld(   tr->PH8_DLY     , SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA    ));
+    //vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1)        , P_Fld(   tr->CA_PREDIV_EN , SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_SHU_MIDPI_CTRL)  , P_Fld( (!(tr->DQ_CA_OPEN))&&(!(tr->CA_CKDIV4_EN)), CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA      ) \
+                                                                     | P_Fld(   tr->CA_CKDIV4_EN , CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA ));
+    //step5:PI_RESETB
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0)       , P_Fld(  0         , CA_DLL_ARPI0_RG_ARPI_RESETB_CA           ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0)       , P_Fld(  0         , B0_DLL_ARPI0_RG_ARPI_RESETB_B0           ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0)       , P_Fld(  0         , B1_DLL_ARPI0_RG_ARPI_RESETB_B1           ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0)       , P_Fld(  1         , CA_DLL_ARPI0_RG_ARPI_RESETB_CA           ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0)       , P_Fld(  1         , B0_DLL_ARPI0_RG_ARPI_RESETB_B0           ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0)       , P_Fld(  1         , B1_DLL_ARPI0_RG_ARPI_RESETB_B1           ));
+    //step6: PLLCK_EN enable
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2)           , P_Fld(  1         , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU     ));  //refer to MISC_DVFSCTRL2
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2)            , P_Fld(  1         , PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN           ) \
+                                                                     | P_Fld(  1         , PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN          ));
+    //step7: release CG 8 Phase clk enable
+    //CG
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
+                | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
+                | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
+                | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0)
+                | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0)
+                | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0)
+                | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0)
+                | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0)
+                | P_Fld(tr->DQ_SEMI_OPEN, SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2), P_Fld(0x0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1)
+                | P_Fld(0x0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1)
+                | P_Fld(0x0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1)
+                | P_Fld(0x0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1)
+                | P_Fld(0x0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1)
+                | P_Fld(0x0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1)
+                | P_Fld(0x0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1)
+                | P_Fld(0x0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1)
+                | P_Fld(((tr->DQ_SEMI_OPEN)&&(!isLP4_DSC)), SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2), P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA)
+                | P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA)
+                | P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA)
+                | P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA)
+                | P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS)
+                | P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK)
+                | P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD)
+                | P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN)
+                | P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA));
+
+    mcSHOW_DBG_MSG6(("[ANA_INIT] MIDPI <<<<<<<< \n"));
+
+}
+
+static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T *a_cfg)
+{
+    U8 DLL_ASYNC_EN;
+    U8 ALL_SLAVE_EN;
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    REG_TRANSFER_T MS_DLL_PHDET_EN_Reg,  SLV_DLL_PHDET_EN_Reg;
+    if (isLP4_DSC){
+        MS_DLL_PHDET_EN_Reg.u4Addr = DDRPHY_REG_SHU_B1_DLL1;
+        MS_DLL_PHDET_EN_Reg.u4Fld = SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1;
+        SLV_DLL_PHDET_EN_Reg.u4Addr = DDRPHY_REG_SHU_CA_DLL1;
+        SLV_DLL_PHDET_EN_Reg.u4Fld = SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA;
+    }
+    else{
+        MS_DLL_PHDET_EN_Reg.u4Addr = DDRPHY_REG_SHU_CA_DLL1;
+        MS_DLL_PHDET_EN_Reg.u4Fld = SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA;
+        SLV_DLL_PHDET_EN_Reg.u4Addr = DDRPHY_REG_SHU_B1_DLL1;
+        SLV_DLL_PHDET_EN_Reg.u4Fld = SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1;
+    }
+
+    DLL_ASYNC_EN = a_cfg->DLL_ASYNC_EN;
+    ALL_SLAVE_EN = a_cfg->ALL_SLAVE_EN;
+
+    mcSHOW_DBG_MSG6(("[ANA_INIT] DLL >>>>>>>> \n"));
+    //step1: DLL_RESETB
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD8)            , P_Fld(  1         , CA_CMD8_RG_ARDLL_RESETB_CA ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ8)             , P_Fld(  1         , B0_DQ8_RG_ARDLL_RESETB_B0  ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ8)             , P_Fld(  1         , B1_DQ8_RG_ARDLL_RESETB_B1  ));
+    //step2: master DLL_EN
+    if(ALL_SLAVE_EN == 1)
+    {
+        if (tr->DQ_SEMI_OPEN)
+        {
+            DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+            vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1)        , P_Fld(  1                , SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA));
+            DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+            mcDELAY_XNS(300);
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1)        , P_Fld(  0                , SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1)        , P_Fld(  0                , SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1));
+            mcDELAY_XNS(400); //2nd DLL > 77TMCK
+        }
+        else
+        {
+            DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+            vIO32WriteFldMulti_All(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr)        , P_Fld(  1                , MS_DLL_PHDET_EN_Reg.u4Fld));
+            DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+            mcDELAY_XNS(300);
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1)        , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(SLV_DLL_PHDET_EN_Reg.u4Addr)        , P_Fld(!(tr->DQ_SEMI_OPEN), SLV_DLL_PHDET_EN_Reg.u4Fld));
+            mcDELAY_XNS(400); //2nd DLL > 77TMCK
+        }
+    }
+    else
+    {
+        if(DLL_ASYNC_EN == 1)
+        {
+            DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+            vIO32WriteFldMulti_All(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr)        , P_Fld(  1     , MS_DLL_PHDET_EN_Reg.u4Fld));
+            DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+            mcDELAY_XNS(300); //1st DLL  > 55 TMCK
+        }
+        else
+        {
+            DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr)        , P_Fld(  1     , MS_DLL_PHDET_EN_Reg.u4Fld));
+            mcDELAY_XNS(300); //1st DLL >55T MCK
+            vSetPHY2ChannelMapping(p, CHANNEL_B);
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr)        , P_Fld(  1     , MS_DLL_PHDET_EN_Reg.u4Fld));
+            #if (CHANNEL_NUM>2)
+			    if (channel_num_auxadc > 2) {
+		            vSetPHY2ChannelMapping(p, CHANNEL_C);
+        		    vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr)        , P_Fld(  1     , MS_DLL_PHDET_EN_Reg.u4Fld));
+		            mcDELAY_XNS(300); //1st DLL >55T MCK
+        		    vSetPHY2ChannelMapping(p, CHANNEL_D);
+		            vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr)        , P_Fld(  1     , MS_DLL_PHDET_EN_Reg.u4Fld));
+			    	}
+            #endif
+            mcDELAY_XNS(300); //1st DLL >55T MCK
+            vSetPHY2ChannelMapping(p, CHANNEL_A);
+            DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+        }
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1)        , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0       ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(SLV_DLL_PHDET_EN_Reg.u4Addr)        , P_Fld(!(tr->DQ_SEMI_OPEN), SLV_DLL_PHDET_EN_Reg.u4Fld       ));
+        mcDELAY_XNS(400); //2nd DLL > 77TMCK
+    mcSHOW_DBG_MSG6(("[ANA_INIT] DLL <<<<<<<< \n"));
+    }
+}
+
+
+//shuffle register for ANA initial flow control
+//It is not easy for initial sequence SA/DV coding --- same register for different group.  need two different method to manage it
+//1. for seqeunce
+//2. for another shuffle group need to DMA to SRAM
+void ANA_sequence_shuffle_colletion(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+    //PLL
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2)           , P_Fld(  1                 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU   ));  //refer to MISC_DVFSCTRL2
+
+    //MIDPI
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2)   , P_Fld(  tr->DQ_SEMI_OPEN  , SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0   ) \
+                                                                     | P_Fld(  0                 , SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0      ) \
+                                                                     | P_Fld(  tr->DQ_SEMI_OPEN   , SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0));
+    if (isLP4_DSC)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2)   , P_Fld(  tr->DQ_SEMI_OPEN   , SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA   ) \
+                                                                         | P_Fld(  0                 , SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA      ) \
+                                                                         | P_Fld(  tr->DQ_SEMI_OPEN    , SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA    ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2)   , P_Fld(  0  , SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1   ) \
+                                                                         | P_Fld(  0                 , SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1      ) \
+                                                                         | P_Fld(  tr->DQ_CA_OPEN  , SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2)   , P_Fld( tr->DQ_SEMI_OPEN   , SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1   ) \
+                                                                         | P_Fld(  0                 , SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1      ) \
+                                                                         | P_Fld(  tr->DQ_SEMI_OPEN   , SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2)   , P_Fld(  0                 , SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA   ) \
+                                                                         | P_Fld(  0                 , SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA      ) \
+                                                                         | P_Fld( tr->DQ_CA_OPEN     , SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA    ));
+    }
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1)        , P_Fld( !(tr->CA_CKDIV4_EN), SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA        ) \
+                                                                     | P_Fld(   tr->CA_CKDIV4_EN , SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1)        , P_Fld(   tr->CA_PREDIV_EN , SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_SHU_MIDPI_CTRL)  , P_Fld( !(tr->DQ_CKDIV4_EN), B0_SHU_MIDPI_CTRL_MIDPI_ENABLE_B0      ) \
+                                                                     | P_Fld( (!(tr->DQ_SEMI_OPEN))&&(tr->DQ_CKDIV4_EN), B0_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B0 ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_SHU_MIDPI_CTRL)  , P_Fld( !(tr->DQ_CKDIV4_EN), B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1      ) \
+                                                                     | P_Fld( (!(tr->DQ_SEMI_OPEN))&&(tr->DQ_CKDIV4_EN), B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1 ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_SHU_MIDPI_CTRL)  , P_Fld( !(tr->CA_CKDIV4_EN), CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA      ) \
+                                                                     | P_Fld(   tr->CA_CKDIV4_EN , CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA ));
+    //DLL
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1)        , P_Fld(  1                , SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA        ));
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1)        , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0        ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1)        , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1        ));
+}
+
+static void ANA_ClockOff_Sequence(DRAMC_CTX_T *p)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+    /* Dynamic CKE to let HW disable CLK_TXD, avoiding CLK parking state violation during CKE high
+     * Note: BROADCAST is ON here
+     */
+    CKEFixOnOff(p, TO_ALL_RANK, CKE_DYNAMIC, TO_ONE_CHANNEL);
+    mcDELAY_US(1);
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), P_Fld(0, MISC_CG_CTRL0_CLK_MEM_SEL)
+                                                                | P_Fld(1, MISC_CG_CTRL0_W_CHG_MEM));
+    mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), 0, MISC_CG_CTRL0_W_CHG_MEM);
+
+    // @Darren, Fix 26M clock issue after DDR400 open loop mode (fail case: 26M/4)
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  0                , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  1                , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1));
+    mcDELAY_XNS(100);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)      , P_Fld(  0                , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1));
+
+    //DLL Off
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1), 0, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0);
+    if (!isLP4_DSC)
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1), 0, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1);
+        DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+        vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1), 0, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA);
+        DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+    else
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1), 0, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA);
+        DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+        vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1), 0, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1);
+        DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+
+    //CG
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
+                | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
+                | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
+                | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0)
+                | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0)
+                | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0)
+                | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0)
+                | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0)
+                | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0));
+    if (!isLP4_DSC)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2), P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1)
+                    | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1)
+                    | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1)
+                    | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1)
+                    | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1)
+                    | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1)
+                    | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1)
+                    | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1)
+                    | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2), P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA)
+                    | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA)
+                    | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA)
+                    | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA)
+                    | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS)
+                    | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK)
+                    | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD)
+                    | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN)
+                    | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2), P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA)
+                    | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA)
+                    | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA)
+                    | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA)
+                    | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS)
+                    | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK)
+                    | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD)
+                    | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN)
+                    | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2), P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1)
+                    | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1)
+                    | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1)
+                    | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1)
+                    | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1)
+                    | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1)
+                    | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1)
+                    | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1)
+                    | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1));
+    }
+
+    //PLLCK
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2), 0, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU);  //refer to MISC_DVFSCTRL2
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2), P_Fld(0, PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN)
+                                                        | P_Fld(0, PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN));
+
+    //PLL
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL0), 0, PHYPLL0_RG_RPHYPLL_EN);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2), 0, PHYPLL2_RG_RPHYPLL_RESETB);
+}
+
+static void TransferToSPM_Sequence(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2), 0x1, PHYPLL2_RG_RPHYPLL_RESETB);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL0), 0x1, PHYPLL0_RG_RPHYPLL_EN);
+    mcDELAY_XUS(20);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RG_DFS_CTRL), 0x1, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_MD32_REG_LPIF_FSM_CFG_1),
+                /* TBA set control mux in DV initial */
+                P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) |                // 0: DPM, 1: SPM
+                P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND) |            // 0: DPM, 1: SPM
+                P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR) |        // 0: DPM, 1: SPM
+                P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND));    // 0: DPM, 1: SPM
+}
+
+static void ANA_init_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T *a_cfg)
+{
+    mcSHOW_DBG_MSG6(("[ANA_INIT] flow start \n"));
+    ANA_PLL_sequence(p);
+    ANA_MIDPI_sequence(p,tr);
+    ANA_CLOCK_SWITCH(p); //clock switch supply correct FB clk. have to do this before DLL
+    ANA_DLL_sequence(p,tr,a_cfg);
+    mcSHOW_DBG_MSG6(("[ANA_INIT] flow end \n"));
+}
+
+void ANA_init(DRAMC_CTX_T *p)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+#if (fcFOR_CHIP_ID == fc8195)
+    DRAM_PINMUX DRAM_Pinmux = p->DRAMPinmux; // 0: EMCP, 1: DSC, 2: MCP, 3:DSC_REV
+#endif
+
+    DRAMC_SUBSYS_PRE_CONFIG(p, &DV_p);
+
+    mcSHOW_DBG_MSG6(("[ANA_INIT] >>>>>>>>>>>>>> \n"));
+#if (fcFOR_CHIP_ID == fc8195)
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1)    , P_Fld(   DRAM_Pinmux             , MISC_CTRL1_R_DMPINMUX            ));
+#endif
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL)     , P_Fld( isLP4_DSC, MISC_CKMUX_SEL_R_DMMCTLPLL_CKSEL          ));
+
+    //Disable CMD
+    CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ONE_CHANNEL);
+#if REPLACE_DFS_RG_MODE
+    TransferToSPM_Sequence(p);
+#endif
+    ANA_ClockOff_Sequence(p);
+    ANA_PHY_Config(p,A_T);
+    ANA_init_sequence(p,A_D,A_T);
+    //Enable CMD
+    CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ONE_CHANNEL);
+    LP4_single_end_DRAMC_post_config(p, M_LP4->LP4Y_EN);
+    mcSHOW_DBG_MSG6(("[ANA_INIT] <<<<<<<<<<<<< \n"));
+}
+
+#if FOR_DV_SIMULATION_USED
+void DPI_ANA_init(void)
+{
+    mysetscope();
+    ANA_init(DramcConfig);
+}
+#endif
diff --git a/src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c b/src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c
new file mode 100644
index 000000000000..086d92942840
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c
@@ -0,0 +1,1060 @@
+#include "dramc_dv_init.h"
+#include "dramc_top.h"
+
+Gating_confg_T Gat_p;
+
+//============================================
+// digital PHY config
+//============================================
+static void DIG_PHY_config(DRAMC_CTX_T *p)
+{
+#if ENABLE_PINMUX_FOR_RANK_SWAP
+    U8 RK_SWAP_EN = 1;
+#else
+    U8 RK_SWAP_EN = 0;
+#endif
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    mcSHOW_DBG_MSG6(("[Flow] Enable top DCM control >>>>> \n"));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2)          , P_Fld(   3     , MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL      ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2)          , P_Fld(   0     , MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG        ) \
+                                                                         | P_Fld(   0x1f  , MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL        ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2)          , P_Fld(   1     , MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG        ) \
+                                                                         | P_Fld(   0x1f  , MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL        ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2)          , P_Fld(   0     , MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG        ) \
+                                                                         | P_Fld(   0x1f  , MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL        ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2)          , P_Fld(   0x17  , MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL        ) \
+                                                                         | P_Fld(   1     , MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG        ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0)             , P_Fld(   0     , MISC_CTRL0_R_STBENCMP_DIV4CK_EN         ) \
+                                                                         | P_Fld(   1     , MISC_CTRL0_R_DQS0IEN_DIV4_CK_CG_CTRL    ) \
+                                                                         | P_Fld(   1    , MISC_CTRL0_R_DQS1IEN_DIV4_CK_CG_CTRL    ) \
+                                                                         | P_Fld(   isLP4_DSC     , MISC_CTRL0_R_CLKIEN_DIV4_CK_CG_CTRL     ) \
+                                                                         | P_Fld(   1     , MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF      ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RXDVS2)            , P_Fld(   1     , MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG));
+
+    mcSHOW_DBG_MSG6(("[Flow] Enable top DCM control <<<<< \n"));
+
+    mcSHOW_DBG_MSG6(("Enable DLL master slave shuffle \n"));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFS_EMI_CLK)      , P_Fld(   1     , MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9)                 , P_Fld(   1     , B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0        ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9)                 , P_Fld(   (!isLP4_DSC)     , B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1        ));//TODO:check
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9)                 , P_Fld(   isLP4_DSC     , CA_CMD9_R_DMRXFIFO_STBENCMP_EN_CA        ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1)             , P_Fld(RK_SWAP_EN, MISC_CTRL1_R_RK_PINMUXSWAP_EN          ));
+
+    mcDELAY_US(1);
+
+    if(A_T->NEW_RANK_MODE==0)
+    {
+        //B0
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9)             , P_Fld(   4     , B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0          ) \
+                                                                         | P_Fld(   0     , B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0      ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ10)            , P_Fld(   0     , B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0          ));//TODO:check
+
+        if (isLP4_DSC)
+        {
+            //CA
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9)             , P_Fld(   4     , CA_CMD9_R_IN_GATE_EN_LOW_OPT_CA          ) \
+                                                                         | P_Fld(   0     , CA_CMD9_R_DMRXDVS_R_F_DLY_RK_OPT      ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD10)            , P_Fld(   0     , CA_CMD10_ARPI_CG_RK1_SRC_SEL_CA          ));//TODO:check
+        }
+        else
+        {
+            //B1
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9)             , P_Fld(   4     , B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1          ) \
+                                                                         | P_Fld(   0     , B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1      ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ10)            , P_Fld(   0     , B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1          ));
+        }
+    }
+    else
+    {
+        //B0
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9)             , P_Fld(   0     , B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0          ) \
+                                                                         | P_Fld(   1     , B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0      ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ10)            , P_Fld(   1     , B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0          ));
+
+        if (isLP4_DSC)
+        {
+            //CA
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9)             , P_Fld(   0     , CA_CMD9_R_IN_GATE_EN_LOW_OPT_CA          ) \
+                                                                         | P_Fld(   1     , CA_CMD9_R_DMRXDVS_R_F_DLY_RK_OPT      ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD10)            , P_Fld(   1     , CA_CMD10_ARPI_CG_RK1_SRC_SEL_CA          ));//TODO:check
+        }
+        else
+        {
+            //B1
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9)             , P_Fld(   0     , B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1          ) \
+                                                                         | P_Fld(   1     , B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1      ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ10)            , P_Fld(   1     , B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1          ));//TODO:check
+        }
+    }
+
+    if(A_T->NEW_8X_MODE==1)
+    {
+        DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+        vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL)       , P_Fld(   1     , MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE  ) \
+                                                                         | P_Fld(   3     , MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN        ));
+        DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+}
+
+
+
+static void GATING_MODE_CFG(Gating_confg_T *tr)
+{
+    tr->GAT_TRACK_EN         = ((A_D->DQ_SEMI_OPEN == 1)||(A_D->DQ_CA_OPEN==1))?0:1;
+    tr->RX_GATING_MODE       = 2; //fix 7UI mode under LPDDR4
+    tr->RX_GATING_TRACK_MODE = 2; //fix FIFO mode under LPDDR4
+    tr->PICG_EARLY_EN        = 1; //fix under LPDDR4, if LPDDR5 have to set 1
+    tr->SELPH_MODE           = 1; //random inside {0,1} //for improve APHY XRTR2R. NEW_APHY MODE with 1.
+    tr->VALID_LAT_VALUE      = 1; //random inside {0,1}
+
+    mcSHOW_DBG_MSG6(("============================================================== \n"));
+    mcSHOW_DBG_MSG6(("Gating Mode config\n"              ));
+    mcSHOW_DBG_MSG6(("============================================================== \n"));
+    mcSHOW_DBG_MSG6(("Config description: \n"));
+    mcSHOW_DBG_MSG6(("RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode\n"));
+    mcSHOW_DBG_MSG6(("RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode\n"));
+    mcSHOW_DBG_MSG6(("SELPH_MODE            0: By rank         1: By Phase \n"));
+    mcSHOW_DBG_MSG6(("============================================================== \n"));
+    mcSHOW_DBG_MSG6(("GAT_TRACK_EN                 = %2d\n",tr->GAT_TRACK_EN        ));
+    mcSHOW_DBG_MSG6(("RX_GATING_MODE               = %2d\n",tr->RX_GATING_MODE      ));
+    mcSHOW_DBG_MSG6(("RX_GATING_TRACK_MODE         = %2d\n",tr->RX_GATING_TRACK_MODE));
+    mcSHOW_DBG_MSG6(("SELPH_MODE                   = %2d\n",tr->SELPH_MODE          ));
+    mcSHOW_DBG_MSG6(("PICG_EARLY_EN                = %2d\n",tr->PICG_EARLY_EN       ));
+    mcSHOW_DBG_MSG6(("VALID_LAT_VALUE              = %2d\n",tr->VALID_LAT_VALUE     ));
+    mcSHOW_DBG_MSG6(("============================================================== \n"));
+}
+
+//======================================
+//gating widnow mode
+//======================================
+static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+    mcSHOW_DBG_MSG6(("Enter into Gating configuration >>>> \n"));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1)      , P_Fld(!gat_c->GAT_TRACK_EN, MISC_STBCAL1_STBCNT_SW_RST          ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2)      , P_Fld(gat_c->SELPH_MODE, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1)      , P_Fld(   1      , MISC_STBCAL1_STBCNT_SHU_RST_EN      ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1)      , P_Fld(   1      , MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD ));
+
+    if(gat_c->PICG_EARLY_EN == 1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)          , P_Fld(   1        , B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)          , P_Fld(   1        , B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2)    , P_Fld(   1        , MISC_STBCAL2_STB_PICG_EARLY_1T_EN ));
+    }
+
+    //================================
+    //gating Mode config
+    //================================
+    switch (gat_c->RX_GATING_MODE)
+    {
+        //Pulse Mode
+        case 0:
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9)          , P_Fld(  0    , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9)          , P_Fld(  0    , B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1 ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)          , P_Fld(  0    , B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)          , P_Fld(  0    , B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld(  0    , MISC_SHU_STBCAL_DQSIEN_BURST_MODE ));
+            break;
+        }
+        // Burst Mode (8UI)
+        case 1:
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9)          , P_Fld(  1    , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9)          , P_Fld(  1    , B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1 ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)          , P_Fld(  1    , B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)          , P_Fld(  1    , B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1));
+            break;
+        }
+        // Burst Mode (7UI)
+        case 2:
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9)          , P_Fld(  1    , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9)          , P_Fld(  1    , B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1 ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)          , P_Fld(  2    , B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)          , P_Fld(  2    , B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1)    , P_Fld(  1    , MISC_STBCAL1_DQSIEN_7UI_EN        ));
+            break;
+        }
+        // Oringinal Burst
+        case 3:
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9)          , P_Fld(  1    , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9)          , P_Fld(  1    , B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1 ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)          , P_Fld(  0    , B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)          , P_Fld(  0    , B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1));
+            break;
+        }
+        default:
+        {
+            mcSHOW_ERR_MSG(("ERROR: Gating Mode choose unexpected Mode!!!!\n"));
+            break;
+        }
+    }
+
+    //================================
+    //Gating tracking Mode config
+    //================================
+    switch (gat_c->RX_GATING_TRACK_MODE)
+    {
+        //Valid DLY Mode
+        case 0:
+        {
+            //TODO SHU1_DQSG if -like mode should set STB_UPDMASKCYC = 0 STB_UPDMASK_EN=0 others STB_UPDMASKCYC=9 STB_UPDMASK_EN=1
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL)  , P_Fld(   1     , MISC_STBCAL_STB_DQIEN_IG          ) \
+                                                                       | P_Fld(   1     , MISC_STBCAL_PICHGBLOCK_NORD       ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_REFUICHG              ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_PHYVALID_IG           ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_STBSTATE_OPT          ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_STBDLELAST_FILTER     ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_STBDLELAST_PULSE      ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_STBDLELAST_OPT        ) \
+                                                                       | P_Fld(   1     , MISC_STBCAL_PIMASK_RKCHG_OPT      ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld(   1     , MISC_STBCAL1_STBCAL_FILTER        ) \
+                                                                       | P_Fld(   1     , MISC_STBCAL1_STB_FLAGCLR_OPT      ) \
+                                                                       | P_Fld(   1     , MISC_STBCAL1_STB_SHIFT_DTCOUT_IG  ) \
+                                                                       | P_Fld(   1     , MISC_STBCAL1_STBCNT_MODESEL       ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0)   , P_Fld(   0     , MISC_CTRL0_R_DMDQSIEN_FIFO_EN     ) \
+                                                                       | P_Fld(   2     , MISC_CTRL0_R_DMVALID_DLY          ) \
+                                                                       | P_Fld(   1     , MISC_CTRL0_R_DMVALID_DLY_OPT      ) \
+                                                                       | P_Fld(   0     , MISC_CTRL0_R_DMSTBEN_SYNCOPT      ) \
+                                                                       | P_Fld(   0     , MISC_CTRL0_R_DMVALID_NARROW_IG    )); //TODO
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)       , P_Fld(   1     , B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9)       , P_Fld(   0     , B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0    ) \
+                                                                       | P_Fld(   0     , B0_DQ9_R_DMDQSIEN_VALID_LAT_B0    ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)       , P_Fld(   1     , B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9)       , P_Fld(   0     , B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1    ) \
+                                                                       | P_Fld(   0     , B1_DQ9_R_DMDQSIEN_VALID_LAT_B1    ));
+            if (isLP4_DSC)
+            {
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6)       , P_Fld(   1     , CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL));
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9)       , P_Fld(   0     , CA_CMD9_R_DMDQSIEN_RDSEL_LAT_CA    ) \
+                                                                           | P_Fld(   0     , CA_CMD9_R_DMDQSIEN_VALID_LAT_CA    ));
+            }
+            break;
+        }
+        //-like Mode
+        case 1:
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL)  , P_Fld(   0     , MISC_STBCAL_STB_DQIEN_IG          ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_PICHGBLOCK_NORD       ) \
+                                                                       | P_Fld(   1     , MISC_STBCAL_REFUICHG              ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_PHYVALID_IG           ) \
+                                                                       | P_Fld(   1     , MISC_STBCAL_STBSTATE_OPT          ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_STBDLELAST_FILTER     ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_STBDLELAST_PULSE      ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_STBDLELAST_OPT        ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_PIMASK_RKCHG_OPT      ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld(   0     , MISC_STBCAL1_STBCAL_FILTER        ) \
+                                                                       | P_Fld(   1     , MISC_STBCAL1_STB_FLAGCLR_OPT      ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL1_STB_SHIFT_DTCOUT_IG  ) \
+                                                                       | P_Fld(   1     , MISC_STBCAL1_STBCNT_MODESEL       ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0)   , P_Fld(   0     , MISC_CTRL0_R_DMDQSIEN_FIFO_EN     ) \
+                                                                       | P_Fld(   0     , MISC_CTRL0_R_DMVALID_DLY          ) \
+                                                                       | P_Fld(   0     , MISC_CTRL0_R_DMVALID_DLY_OPT      ) \
+                                                                       | P_Fld(   0     , MISC_CTRL0_R_DMSTBEN_SYNCOPT      ) \
+                                                                       | P_Fld(   1     , MISC_CTRL0_R_DMVALID_NARROW_IG    ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)       , P_Fld(   1     , B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9)       , P_Fld(   0     , B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0    ) \
+                                                                       | P_Fld(   0     , B0_DQ9_R_DMDQSIEN_VALID_LAT_B0    ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)       , P_Fld(   1     , B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9)       , P_Fld(   0     , B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1    ) \
+                                                                       | P_Fld(   0     , B1_DQ9_R_DMDQSIEN_VALID_LAT_B1    ));
+            if (isLP4_DSC)
+            {
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6)       , P_Fld(   1     , CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL));
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9)       , P_Fld(   0     , CA_CMD9_R_DMDQSIEN_RDSEL_LAT_CA    ) \
+                                                                           | P_Fld(   0     , CA_CMD9_R_DMDQSIEN_VALID_LAT_CA    ));
+            }
+            break;
+        }
+        //FIFO Mode
+        case 2:
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL)  , P_Fld(   1     , MISC_STBCAL_STB_DQIEN_IG          ) \
+                                                                       | P_Fld(   1     , MISC_STBCAL_PICHGBLOCK_NORD       ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_REFUICHG              ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_PHYVALID_IG           ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_STBSTATE_OPT          ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_STBDLELAST_FILTER     ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_STBDLELAST_PULSE      ) \
+                                                                       | P_Fld(   0     , MISC_STBCAL_STBDLELAST_OPT        ) \
+                                                                       | P_Fld(   1     , MISC_STBCAL_PIMASK_RKCHG_OPT      ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld(   1     , MISC_STBCAL1_STBCAL_FILTER        ) \
+                                                                       | P_Fld(   1     , MISC_STBCAL1_STB_FLAGCLR_OPT      ) \
+                                                                       | P_Fld(   1     , MISC_STBCAL1_STB_SHIFT_DTCOUT_IG  ) \
+                                                                       | P_Fld(   1     , MISC_STBCAL1_STBCNT_MODESEL       ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0)   , P_Fld(   1     , MISC_CTRL0_R_DMDQSIEN_FIFO_EN     ) \
+                                                                       | P_Fld(   0     , MISC_CTRL0_R_DMVALID_DLY          ) \
+                                                                       | P_Fld(   0     , MISC_CTRL0_R_DMVALID_DLY_OPT      ) \
+                                                                       | P_Fld(   0     , MISC_CTRL0_R_DMSTBEN_SYNCOPT      ) \
+                                                                       | P_Fld(   0     , MISC_CTRL0_R_DMVALID_NARROW_IG    )); // @Darren, func no use sync MP settings from HJ
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)       , P_Fld(   0     , B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9)       , P_Fld(   1+gat_c->VALID_LAT_VALUE     , B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0    ) \
+                                                                       | P_Fld(   0+gat_c->VALID_LAT_VALUE     , B0_DQ9_R_DMDQSIEN_VALID_LAT_B0    ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)       , P_Fld(   0     , B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9)       , P_Fld(   1+gat_c->VALID_LAT_VALUE     , B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1    ) \
+                                                                       | P_Fld(   0+gat_c->VALID_LAT_VALUE     , B1_DQ9_R_DMDQSIEN_VALID_LAT_B1    ));
+            if (isLP4_DSC)
+            {
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6)       , P_Fld(   0     , CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL));
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9)       , P_Fld(   1+gat_c->VALID_LAT_VALUE     , CA_CMD9_R_DMDQSIEN_RDSEL_LAT_CA    ) \
+                                                                           | P_Fld(   0+gat_c->VALID_LAT_VALUE     , CA_CMD9_R_DMDQSIEN_VALID_LAT_CA    ));
+            }
+            break;
+        }
+        default:
+        {
+            mcSHOW_ERR_MSG(("ERROR: Gating tracking Mode choose unexpected Mode!!!!"));
+            break;
+        }
+    }
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2)           , P_Fld(   1  , B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2)           , P_Fld(   1  , B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1));
+    if (isLP4_DSC)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY2), P_Fld(1, CA_PHY2_RG_RX_ARCLK_DQSIEN_UI_LEAD_LAG_EN_CA)) ;
+    }
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL)       , P_Fld(   1  , MISC_STBCAL_DQSIENMODE                      ) \
+                                                                    | P_Fld(   1  , MISC_STBCAL_SREF_DQSGUPD                    ) \
+                                                                    | P_Fld(   1  , MISC_STBCAL_DQSIENCG_CHG_EN                 ) \
+                                                                    | P_Fld(   1  , MISC_STBCAL_PICGEN                          ) \
+                                                                    | P_Fld(   0  , MISC_STBCAL_RKCHGMASKDIS                    ) \
+                                                                    | P_Fld(   0  , MISC_STBCAL_STBCAL2R                        ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1)        , P_Fld(   1  , MISC_CTRL1_R_DMDQSIENCG_EN                  ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2)      , P_Fld(   0  , MISC_STBCAL2_STB_GERRSTOP                   ) \
+                                                                    | P_Fld(   0  , MISC_STBCAL2_STB_GERR_RST                   ) \
+                                                                    | P_Fld(   1  , MISC_STBCAL2_STB_GERR_B01                   ) \
+                                                                    | P_Fld(   0  , MISC_STBCAL2_STB_GERR_B23                   ));
+    //PICG_MODE only support new mode  so here fix 1
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), P_Fld(1, MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT   ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), P_Fld(1, MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT   ));
+
+    if(A_T->NEW_RANK_MODE == 1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2)  , P_Fld(   1  , MISC_STBCAL2_STB_IG_XRANK_CG_RST            ) \
+                                                                    | P_Fld(   1  , MISC_STBCAL2_STB_RST_BY_RANK                ) \
+                                                                    | P_Fld(   1  , MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN        ));
+    }
+    mcSHOW_DBG_MSG6(("Exit from Gating configuration <<<< \n"));
+}
+
+static void RX_INTPUT_Config(DRAMC_CTX_T *p)
+{
+    U8    VALID_LAT    = 1;// TODO inside {0,1}
+    U8    RDSEL_LAT    = 2;// TODO alywas VALID_LAT+1;
+    U8    dq_min       = 0;
+    U8    dq_max       = 0xff;
+    U8    scale        = 3;
+    U8    threadhold   = 0;
+    U32   dqs_min      = 0;
+    U32   dqs_max      = 0x1ff;
+    U8    RX_force_upd = 0; //TODO
+    U8    F_LEADLAG    = 0; //TODO
+    U8    RG_MODE_EN   = 0; //TODO
+    U8    irank        = 0;
+    U8    backup_rank  = 0;
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    backup_rank = p->rank;
+
+    mcSHOW_DBG_MSG6(("[RX_INPUT] configuration >>>>> \n"));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS0)      , P_Fld(  1   , B0_RXDVS0_R_HWSAVE_MODE_ENA_B0                            ) \
+                                                                 | P_Fld(  0   , B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0                         ) \
+                                                                 | P_Fld(  1   , B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0                       ) \
+                                                                 | P_Fld(  1   , B0_RXDVS0_R_HWRESTORE_ENA_B0                              ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_RXDVS0)      , P_Fld(  1   , B1_RXDVS0_R_HWSAVE_MODE_ENA_B1                            ) \
+                                                                 | P_Fld(  0   , B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1                         ) \
+                                                                 | P_Fld(  1   , B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1                       ) \
+                                                                 | P_Fld(  1   , B1_RXDVS0_R_HWRESTORE_ENA_B1                              ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9   )      , P_Fld(  VALID_LAT   , B0_DQ9_R_DMRXDVS_VALID_LAT_B0                     ) \
+                                                                 | P_Fld(  RDSEL_LAT   , B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0                     ));
+    if (!isLP4_DSC)
+    {
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9   )      , P_Fld(  VALID_LAT   , B1_DQ9_R_DMRXDVS_VALID_LAT_B1                     ) \
+                                                                 | P_Fld(  RDSEL_LAT   , B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1                     ));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9   )      , P_Fld(  VALID_LAT   , CA_CMD9_R_DMRXDVS_VALID_LAT_CA                     ) \
+                                                                     | P_Fld(  RDSEL_LAT   , CA_CMD9_R_DMRXDVS_RDSEL_LAT_CA                     ));
+    }
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RXDVS2 )   , P_Fld(  1   , MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN                          ) \
+                                                                 | P_Fld(  0   , MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR                         ) \
+                                                                 | P_Fld(  0   , MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN                        ) \
+                                                                 | P_Fld(  1   , MISC_RXDVS2_R_DMRXDVS_DEPTH_HALF                          ));
+
+    for(irank = RANK_0; irank < p->support_rank_num; irank++)
+    {
+        vSetRank(p, irank);
+        //RK0--B0
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS3 )  , P_Fld(  dq_min   , RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0              ) \
+                                                                     | P_Fld(  dq_max   , RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0              ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS4 )  , P_Fld(  dqs_min  , RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0            ) \
+                                                                     | P_Fld(  dqs_max  , RK_B0_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B0            ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS2 )  , P_Fld(  scale    , RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0       ) \
+                                                                     | P_Fld(  scale    , RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0        ) \
+                                                                     | P_Fld(  0        , RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0  ) \
+                                                                     | P_Fld(  scale    , RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0       ) \
+                                                                     | P_Fld(  scale    , RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0        ) \
+                                                                     | P_Fld(  0        , RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0  ) \
+                                                                     | P_Fld(  1        , RK_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0              ) \
+                                                                     | P_Fld(  0        , RK_B0_RXDVS2_R_RK0_DVS_MODE_B0                   ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS1 )  , P_Fld(  threadhold  , RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG              ) \
+                                                                     | P_Fld(  threadhold  , RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD             ));
+
+
+        //RK0--B1
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS3 )  , P_Fld(  dq_min   , RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1              ) \
+                                                                     | P_Fld(  dq_max   , RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1              ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS4 )  , P_Fld(  dqs_min  , RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1            ) \
+                                                                     | P_Fld(  dqs_max  , RK_B1_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B1            ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS2 )  , P_Fld(  scale    , RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1       ) \
+                                                                     | P_Fld(  scale    , RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1        ) \
+                                                                     | P_Fld(  0        , RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1  ) \
+                                                                     | P_Fld(  scale    , RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1       ) \
+                                                                     | P_Fld(  scale    , RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1        ) \
+                                                                     | P_Fld(  0        , RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1  ) \
+                                                                     | P_Fld(  1        , RK_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1              ) \
+                                                                     | P_Fld(  0        , RK_B1_RXDVS2_R_RK0_DVS_MODE_B1                   ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS1 )  , P_Fld(  threadhold  , RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG              ) \
+                                                                     | P_Fld(  threadhold  , RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD             ));
+    }
+    vSetRank(p, backup_rank);
+
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL1 )     ,   0xffffffff  , MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL              );  //TODO
+
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS1  )  , P_Fld(  F_LEADLAG  , B0_RXDVS1_F_LEADLAG_TRACK_B0           ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_RXDVS1  )  , P_Fld(  F_LEADLAG  , B1_RXDVS1_F_LEADLAG_TRACK_B1           ));
+
+    if(RX_force_upd == 1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL )  , P_Fld(  1  , DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT              ) \
+                                                                   | P_Fld(  1  , DLLFRZ_CTRL_DLLFRZ_BLOCKLONG                  ) \
+                                                                   | P_Fld(  1  , DLLFRZ_CTRL_INPUTRXTRACK_BLOCK                ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS1  )  , P_Fld(  1  , B0_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B0           ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_RXDVS1  )  , P_Fld(  1  , B1_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B1           ));
+    }
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5  )    , P_Fld(  1  , B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1          ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5  )    , P_Fld(  1  , B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0          ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS0 )  , P_Fld(  1  , B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0        )\
+                                                              | P_Fld(  1  , B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0      )\
+                                                              | P_Fld(  1  , B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0   )\
+                                                              | P_Fld(  0  , B0_RXDVS0_R_RX_RANKINCTL_B0            )\
+                                                              | P_Fld(  1  , B0_RXDVS0_R_RX_RANKINSEL_B0            ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_RXDVS0 )  , P_Fld(  1  , B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1        )\
+                                                              | P_Fld(  1  , B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1      )\
+                                                              | P_Fld(  1  , B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1   )\
+                                                              | P_Fld(  0  , B1_RXDVS0_R_RX_RANKINCTL_B1            )\
+                                                              | P_Fld(  1  , B1_RXDVS0_R_RX_RANKINSEL_B1            ));
+
+    for(irank = RANK_0; irank < RANK_MAX; irank++)
+    {
+        vSetRank(p, irank);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS2 )  , P_Fld(  1  , RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0  ) \
+                                                                     | P_Fld(  1  , RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0  ) \
+                                                                     | P_Fld(  2  , RK_B0_RXDVS2_R_RK0_DVS_MODE_B0                   ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS2 )  , P_Fld(  1  , RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1  ) \
+                                                                     | P_Fld(  1  , RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1  ) \
+                                                                     | P_Fld(  2  , RK_B1_RXDVS2_R_RK0_DVS_MODE_B1                   ));
+    }
+    vSetRank(p, backup_rank);
+
+    //Enable RX input delay tracking..
+    //TODO notice here if SA should not enbale it before RX perbit calibration
+    if (RG_MODE_EN == 1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RG_DFS_CTRL)    , P_Fld(  1  , MISC_RG_DFS_CTRL_RG_DPY_RXDLY_TRACK_EN      ));
+    } else {
+//        `TBA_TOP.dvfs_spm_vif.sc_dphy_reserved[1:0] = 2'b11; //TODO
+    }
+
+    mcSHOW_DBG_MSG6(("[RX_INPUT] configuration <<<<< \n"));
+}
+
+static void DDRPHY_PICG_Config(DRAMC_CTX_T *p)
+{
+    U8 PICG_MODE  = 1; // only support new Mode under
+    U8 MISC_CG_EN = 1;
+    U8 MISC_CG_REVERSE_DEFAULT_ON = 0;  //for default CG enable.
+
+    mcSHOW_DBG_MSG6(("Enter into PICG configuration >>>> \n"));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4)        , P_Fld(   PICG_MODE  , MISC_CTRL4_R_OPT2_MPDIV_CG                  ) \
+                                                                    | P_Fld(   PICG_MODE  , MISC_CTRL4_R_OPT2_CG_MCK                    ) \
+                                                                    | P_Fld(   PICG_MODE  , MISC_CTRL4_R_OPT2_CG_DQM                    ) \
+                                                                    | P_Fld(   PICG_MODE  , MISC_CTRL4_R_OPT2_CG_DQS                    ) \
+                                                                    | P_Fld(   PICG_MODE  , MISC_CTRL4_R_OPT2_CG_DQ                     ) \
+                                                                    | P_Fld(   PICG_MODE  , MISC_CTRL4_R_OPT2_CG_DQSIEN                 ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL3)        , P_Fld(  !PICG_MODE  , MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT             ) \
+                                                                    | P_Fld(  !PICG_MODE  , MISC_CTRL3_ARPI_CG_MCK_DQ_OPT               ) \
+                                                                    | P_Fld(  !PICG_MODE  , MISC_CTRL3_ARPI_CG_DQS_OPT                  ) \
+                                                                    | P_Fld(  !PICG_MODE  , MISC_CTRL3_ARPI_CG_DQ_OPT                   ));
+
+    //Notice here: MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE = 1 will leading other_shuffle_group before register settle down latch ->error. can not set to 1
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)     , P_Fld(  !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE       ) \
+                                                                    | P_Fld(  !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE          ) \
+                                                                    | P_Fld(  !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE        ) \
+                                                                    | P_Fld(  !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE         ) \
+                                                                    | P_Fld(  !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE       ) \
+                                                                    | P_Fld(  !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE       ) \
+                                                                    | P_Fld(  !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE      ) \
+                                                                    | P_Fld(  !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE    ) \
+                                                                    | P_Fld(  !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE    ) \
+                                                                    | P_Fld(  !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE       ));
+
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2)     , P_Fld(  !MISC_CG_EN , MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE     ) \
+                                                                    | P_Fld(  !MISC_CG_EN , MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE       ) \
+                                                                    | P_Fld(  !MISC_CG_EN , MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE         ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL5)     , P_Fld(   MISC_CG_EN , MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN              ) \
+                                                                    | P_Fld(   MISC_CG_EN , MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN              ) \
+                                                                    | P_Fld(   MISC_CG_EN , MISC_CG_CTRL5_R_CA_DLY_DCM_EN               ) \
+                                                                    | P_Fld(   MISC_CG_EN , MISC_CG_CTRL5_R_DQ1_PI_DCM_EN               ) \
+                                                                    | P_Fld(   MISC_CG_EN , MISC_CG_CTRL5_R_DQ0_PI_DCM_EN               ) \
+                                                                    | P_Fld(   MISC_CG_EN , MISC_CG_CTRL5_R_CA_PI_DCM_EN                ));
+
+    //defualt DCM enable, if we wanner to test CG enable, modified default CG condition.
+    //disable DCM.--- I think just for debug
+    if(MISC_CG_REVERSE_DEFAULT_ON == 1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RX_CG_SET0)         , P_Fld(   1      , RX_CG_SET0_RDATCKAR                          ) \
+                                                                        | P_Fld(   1      , RX_CG_SET0_RDYCKAR                           ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SREF_DPD_CTRL)      , P_Fld(   1      , SREF_DPD_CTRL_CMDCKAR                        ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DCM_CTRL0)          , P_Fld(   1      , DCM_CTRL0_BCLKAR                             ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_CG_SET0)         , P_Fld(   1      , TX_CG_SET0_PSELAR                            ) \
+                                                                        | P_Fld(   1      , TX_CG_SET0_DWCLKRUN                          ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SCSMCTRL_CG)        , P_Fld(   1      , SCSMCTRL_CG_SCSM_CGAR                        ) \
+                                                                        | P_Fld(   1      , SCSMCTRL_CG_SCARB_SM_CGAR                    ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_TRACKING_SET0)   , P_Fld(   1      , TX_TRACKING_SET0_RDDQSOSC_CGAR               ) \
+                                                                        | P_Fld(   1      , TX_TRACKING_SET0_HMRRSEL_CGAR                ) \
+                                                                        | P_Fld(   1      , TX_TRACKING_SET0_TXUIPI_CAL_CGAR             ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ZQ_SET0)            , P_Fld(   1      , ZQ_SET0_ZQCS_MASK_SEL_CGAR                   ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ACTIMING_CTRL)      , P_Fld(   1      , ACTIMING_CTRL_CLKWITRFC                      ) \
+                                                                        | P_Fld(   1      , ACTIMING_CTRL_SEQCLKRUN3                     ) \
+                                                                        | P_Fld(   1      , ACTIMING_CTRL_SEQCLKRUN2                     ) \
+                                                                        | P_Fld(   1      , ACTIMING_CTRL_SEQCLKRUN                      ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CLKAR)              , P_Fld(   1      , CLKAR_REQQUECLKRUN                           ) \
+                                                                        | P_Fld(   1      , CLKAR_REQQUE_PACG_DIS                        ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)      , P_Fld(   1      , DRAMC_PD_CTRL_PHYGLUECLKRUN                  ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3)           , P_Fld(   1      , TEST2_A3_TESTCLKRUN                          ));
+        DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+        vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0)         , P_Fld(   1      , DVFS_CTRL0_DVFS_CG_OPT                       ));
+        DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1)    , P_Fld(   1      , MISC_DUTYSCAN1_EYESCAN_DQS_OPT               ));
+
+        //TODO -- for DPHY shuffle RG have to set to different Group into SRAM or not.--here just conf0 but not all frequency group
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ8)        , P_Fld(   1      , SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0      ) \
+                                                                        | P_Fld(   1      , SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0               ) \
+                                                                        | P_Fld(   1      , SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0             ) \
+                                                                        | P_Fld(   1      , SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0     ) \
+                                                                        | P_Fld(   1      , SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 ) \
+                                                                        | P_Fld(   1      , SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0                ) \
+                                                                        | P_Fld(   1      , SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0     ) \
+                                                                        | P_Fld(   1      , SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0     ) \
+                                                                        | P_Fld(   1      , SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0    ) \
+                                                                        | P_Fld(   1      , SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) \
+                                                                        | P_Fld(   1      , SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0            ) \
+                                                                        | P_Fld(   1      , SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0        ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ8)        , P_Fld(   1      , SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1      ) \
+                                                                        | P_Fld(   1      , SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1               ) \
+                                                                        | P_Fld(   1      , SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1             ) \
+                                                                        | P_Fld(   1      , SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1     ) \
+                                                                        | P_Fld(   1      , SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 ) \
+                                                                        | P_Fld(   1      , SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1                ) \
+                                                                        | P_Fld(   1      , SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1     ) \
+                                                                        | P_Fld(   1      , SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1     ) \
+                                                                        | P_Fld(   1      , SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1    ) \
+                                                                        | P_Fld(   1      , SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) \
+                                                                        | P_Fld(   1      , SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1            ) \
+                                                                        | P_Fld(   1      , SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1        ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD8)        , P_Fld(   1      , SHU_CA_CMD8_R_DMRANK_RXDLY_PIPE_CG_IG_CA      ) \
+                                                                        | P_Fld(   1      , SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA               ) \
+                                                                        | P_Fld(   1      , SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA             ) \
+                                                                        | P_Fld(   1      , SHU_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA     ) \
+                                                                        | P_Fld(   1      , SHU_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA ) \
+                                                                        | P_Fld(   1      , SHU_CA_CMD8_R_DMRXDLY_CG_IG_CA                ) \
+                                                                        | P_Fld(   1      , SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA     ) \
+                                                                        | P_Fld(   1      , SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA     ) \
+                                                                        | P_Fld(   1      , SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA    ) \
+                                                                        | P_Fld(   1      , SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA) \
+                                                                        | P_Fld(   1      , SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA            ) \
+                                                                        | P_Fld(   1      , SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA        ));
+
+    }
+
+    mcSHOW_DBG_MSG6(("Exit from PICG configuration <<<< \n"));
+}
+
+static void DRAMC_COMMON_Config(DRAMC_CTX_T *p)
+{
+    U8 RD2MRR_EXTEND_EN = 1; // for fix Samsung RD2MRR seamless error, If the samsung fix that bug, this could set 0
+    U8 EBG_EN = 0              ;
+    U8 TMRRI_MODE       = 1; // !!!Notice here: 0: Old Mode, 1: New Mode   --- FIX NEW MODE. Pertrus not support old mode anymore
+    U8 NOBLOCKALE_EN    = 1;
+    U8 RUNTIME_MRR      = 1;
+
+    //pre configuration calculate
+    if(TMRRI_MODE == 1)
+    {
+        NOBLOCKALE_EN = 1;
+        RUNTIME_MRR   = 1;
+    } else {
+        //TODO
+        mcSHOW_DBG_MSG6(("NONBLOCKALE RUNTIMEMRR could be random.--for MP should setting 1. just record it."));
+    }
+
+
+#if ENABLE_EARLY_BG_CMD==1
+    EBG_EN = 1;
+#endif
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DDRCOMMON0)         , P_Fld(   1             , DDRCOMMON0_BK8EN                 ) \
+                                                                    | P_Fld(   LPDDR5_EN_S   , DDRCOMMON0_LPDDR5EN              ) \
+                                                                    | P_Fld(   LPDDR4_EN_S   , DDRCOMMON0_LPDDR4EN              ) \
+                                                                    | P_Fld(   0             , DDRCOMMON0_TRCDEARLY             )); //if LPDDR5 set1 HEFF mode ACT -> R/W delay-1
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0)            , P_Fld(   0             , RX_SET0_DM4TO1MODE               ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0)           , P_Fld(   5             , REFCTRL0_REF_PREGATE_CNT             ) \
+                                                                    | P_Fld(   0             , REFCTRL0_DMPGVLD_IG                  ) \
+                                                                    | P_Fld(   3             , REFCTRL0_DISBYREFNUM                 ) \
+                                                                    | P_Fld(   0             , REFCTRL0_PBREF_DISBYRATE             ) \
+                                                                    | P_Fld(   1             , REFCTRL0_PBREF_DISBYREFNUM           ) \
+                                                                    | P_Fld(   1             , REFCTRL0_PBREF_BK_REFA_ENA           ) \
+                                                                    | P_Fld(   1             , REFCTRL0_PBREF_BK_REFA_NUM           ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1)           , P_Fld(   1             , REFCTRL1_PB2AB_OPT                   ) \
+                                                                    | P_Fld(   1             , REFCTRL1_REF_QUE_AUTOSAVE_EN         ) \
+                                                                    | P_Fld(   0             , REFCTRL1_REF_OVERHEAD_ALL_REFPB_ENA  ) \
+                                                                    | P_Fld(   1             , REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA ) \
+                                                                    | P_Fld(   0             , REFCTRL1_REF_OVERHEAD_ALL_REFAL_ENA  ) \
+                                                                    | P_Fld(   0             , REFCTRL1_REF_OVERHEAD_SLOW_REFAL_ENA ) \
+                                                                    | P_Fld(   0             , REFCTRL1_REF_OVERHEAD_RATE_REFPB_ENA ) \
+                                                                    | P_Fld(   0             , REFCTRL1_REF_OVERHEAD_RATE_REFAL_ENA ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL2)           , P_Fld(   0             , REFCTRL2_REF_OVERHEAD_RATE           ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL)        , P_Fld(   0             , DLLFRZ_CTRL_UPDBYWR              ) \
+                                                                    | P_Fld(   1             , DLLFRZ_CTRL_DLLFRZ               ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAMCTRL)           , P_Fld(   0             , DRAMCTRL_ADRDECEN                ) \
+                                                                    | P_Fld(   1             , DRAMCTRL_PREALL_OPTION           ) \
+                                                                    | P_Fld(   0             , DRAMCTRL_REQQUE_THD_EN           ) \
+                                                                    | P_Fld(   1             , DRAMCTRL_DYNMWREN                ) \
+                                                                    | P_Fld(   0             , DRAMCTRL_AG0MWR                  ) \
+                                                                    | P_Fld(   0             , DRAMCTRL_ADRBIT3DEC              ) \
+                                                                    | P_Fld(   0             , DRAMCTRL_CTOREQ_HPRI_OPT         ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ACTIMING_CTRL)      , P_Fld(   0             , ACTIMING_CTRL_CLKWITRFC          ) \
+                                                                    | P_Fld(   1             , ACTIMING_CTRL_SEQCLKRUN3         ) \
+                                                                    | P_Fld(   0             , ACTIMING_CTRL_FASTW2R            ) \
+                                                                    | P_Fld(   0             , ACTIMING_CTRL_REFBW_FREN         ) \
+                                                                    | P_Fld(   1             , ACTIMING_CTRL_TMRRICHKDIS        ) \
+                                                                    | P_Fld(   0             , ACTIMING_CTRL_REFNA_OPT          ) \
+                                                                    | P_Fld(!TMRRI_MODE      , ACTIMING_CTRL_MRRIOPT            ) \
+                                                                    | P_Fld(!TMRRI_MODE      , ACTIMING_CTRL_TMRRIBYRK_DIS      ) \
+                                                                    | P_Fld( TMRRI_MODE      , ACTIMING_CTRL_TMRRICHKDIS        ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ARBCTL)             , P_Fld(   0x80          , ARBCTL_MAXPENDCNT                ) \
+                                                                    | P_Fld(   0             , ARBCTL_WDATACNTDIS               ) );
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAM_CLK_CTRL)      , P_Fld(   1             , DRAM_CLK_CTRL_CLK_EN             ) );
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CLKAR)              , P_Fld(   1             , CLKAR_DCMREF_OPT                 ) );
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)      , P_Fld(   1             , DRAMC_PD_CTRL_COMBCLKCTRL        ) \
+                                                                    | P_Fld(   0             , DRAMC_PD_CTRL_MIOCKCTRLOFF       ) \
+                                                                    | P_Fld(   1             , DRAMC_PD_CTRL_PHYCLKDYNGEN       ) \
+                                                                    | P_Fld(   1             , DRAMC_PD_CTRL_DCMEN              ) \
+                                                                    | P_Fld(   1             , DRAMC_PD_CTRL_DCMEN2             ) \
+//                                                                    | P_Fld(   0x3           , DRAMC_PD_CTRL_APHYPI_CKCGH_CNT   )
+                                                                    | P_Fld(   0             , DRAMC_PD_CTRL_PG_DCM_OPT         ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RKCFG)              , P_Fld(   0             , RKCFG_CKE2RANK                   ) \
+                                                                    | P_Fld(   0             , RKCFG_MRS2RK                     ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)            , P_Fld(   1             , CKECTRL_CKE2RANK_OPT2            ) \
+                                                                    | P_Fld(   1             , CKECTRL_CKEON                    ) \
+                                                                    | P_Fld(   0             , CKECTRL_CKETIMER_SEL             ) \
+                                                                    | P_Fld(   1             , CKECTRL_CKE2RANK_OPT8            ) \
+                                                                    | P_Fld(!RUNTIME_MRR     , CKECTRL_RUNTIMEMRRMIODIS         ) \
+                                                                    | P_Fld(   1             , CKECTRL_FASTWAKE_SEL             ) \
+                                                                    | P_Fld(   1             , CKECTRL_CKEPBDIS                 ) \
+                                                                    | P_Fld( !TMRRI_MODE     , CKECTRL_RUNTIMEMRRCKEFIX         ) \
+                                                                    | P_Fld(   0             , CKECTRL_CKELCKFIX                ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SREF_DPD_CTRL)      , P_Fld(   1             , SREF_DPD_CTRL_SELFREF_AUTOSAVE_EN) \
+                                                                    | P_Fld(   0             , SREF_DPD_CTRL_GT_SYNC_MASK       ) \
+                                                                    | P_Fld(   0             , SREF_DPD_CTRL_DAT_SYNC_MASK      ) \
+                                                                    | P_Fld(   0             , SREF_DPD_CTRL_PHY_SYNC_MASK      ) \
+                                                                    | P_Fld(   1             , SREF_DPD_CTRL_LPSM_BYPASS_B      ) \
+                                                                    | P_Fld(   0             , SREF_DPD_CTRL_SREF_PRD_OPT       ) \
+                                                                    | P_Fld(   1             , SREF_DPD_CTRL_CLR_EN             ) \
+                                                                    | P_Fld(   0             , SREF_DPD_CTRL_SRFPD_DIS          ) \
+                                                                    | P_Fld(   8             , SREF_DPD_CTRL_SREFDLY            ) \
+                                                                    | P_Fld(   1             , SREF_DPD_CTRL_SREF_HW_EN         ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SCHEDULER_COM)      , P_Fld(   1             , SCHEDULER_COM_DISRDPHASE1        ) \
+                                                                    | P_Fld(   1             , SCHEDULER_COM_MWHPRIEN           ) \
+                                                                    | P_Fld(   0             , SCHEDULER_COM_RWHPRICTL          ) \
+                                                                    | P_Fld(   1             , SCHEDULER_COM_RWOFOEN            ) \
+                                                                    | P_Fld(   1             , SCHEDULER_COM_RWSPLIT            ));
+//                                                                    | P_Fld(   1             , SCHEDULER_COM_BGPIPEEN           )); //diff with IPMV2 compile error
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_PERFCTL0)           , P_Fld(   1             , PERFCTL0_EMILLATEN               ) \
+                                                                    | P_Fld(   1             , PERFCTL0_RWHPRIEN                ) \
+                                                                    | P_Fld( EBG_EN          , PERFCTL0_EBG_EN                  ) \
+                                                                    | P_Fld(   1             , PERFCTL0_RWLLATEN                ) \
+                                                                    | P_Fld(   1             , PERFCTL0_RWAGEEN                 ) \
+                                                                    | P_Fld(   1             , PERFCTL0_WFLUSHEN                ) \
+                                                                    | P_Fld(   0             , PERFCTL0_REORDEREN               ) \
+                                                                    | P_Fld(   0             , PERFCTL0_REORDER_MODE            ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_HW_MRR_FUN)         , P_Fld(RUNTIME_MRR      , HW_MRR_FUN_TMRR_ENA              ) \
+                                                                    | P_Fld(   0             , HW_MRR_FUN_TRPMRR_EN             ) \
+                                                                    | P_Fld(   0             , HW_MRR_FUN_TRCDMRR_EN            ) \
+                                                                    | P_Fld(   1             , HW_MRR_FUN_MRR_HW_HIPRI          ) \
+                                                                    | P_Fld(RD2MRR_EXTEND_EN , HW_MRR_FUN_TR2MRR_ENA            ) \
+                                                                    | P_Fld(RD2MRR_EXTEND_EN , HW_MRR_FUN_R2MRRHPRICTL          ) \
+                                                                    | P_Fld(RD2MRR_EXTEND_EN , HW_MRR_FUN_MANTMRR_EN            ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ZQ_SET0)            , P_Fld(   0x0A          , ZQ_SET0_ZQCSAD                   ) \
+                                                                    | P_Fld(   0x56          , ZQ_SET0_ZQCSOP                   ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION)         , P_Fld(   1             , MPC_OPTION_MPCRKEN               ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL)           , P_Fld(!RUNTIME_MRR     , MPC_CTRL_REFR_BLOCKEN            ) \
+                                                                    | P_Fld( NOBLOCKALE_EN   , MPC_CTRL_ZQ_BLOCKALE_OPT         ) \
+                                                                    | P_Fld( NOBLOCKALE_EN   , MPC_CTRL_MPC_BLOCKALE_OPT        ) \
+                                                                    | P_Fld( NOBLOCKALE_EN   , MPC_CTRL_MPC_BLOCKALE_OPT1       ) \
+                                                                    | P_Fld( NOBLOCKALE_EN   , MPC_CTRL_MPC_BLOCKALE_OPT2       ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_HMR4)               , P_Fld(   1             , HMR4_SPDR_MR4_OPT                ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1)        , P_Fld(   0x010000      , RK_TEST2_A1_TEST2_BASE           ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2)           , P_Fld(   0x000020      , TEST2_A2_TEST2_OFF               ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3)           , P_Fld(   1             , TEST2_A3_TESTAUDPAT              ) \
+                                                                    | P_Fld(   1             , TEST2_A3_TEST2WREN2_HW_EN        ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4)           , P_Fld(   0x11          , TEST2_A4_TESTAUDINIT             ) \
+                                                                    | P_Fld(   0x0d          , TEST2_A4_TESTAUDINC              ) \
+                                                                    | P_Fld(   0x04          , TEST2_A4_TESTAGENTRKSEL          ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CMD_DEC_CTRL0)      , P_Fld(   1             , CMD_DEC_CTRL0_RKMODE             ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MISCTL0)            , P_Fld(   0             , MISCTL0_PAGDIS                   ) \
+                                                                    | P_Fld(   0             , MISCTL0_PBC_ARB_E1T              ) \
+                                                                    | P_Fld(   1             , MISCTL0_REFA_ARB_EN2             ) \
+                                                                    | P_Fld(   1             , MISCTL0_PBC_ARB_EN               ) \
+                                                                    | P_Fld(   1             , MISCTL0_REFP_ARB_EN2             ) \
+                                                                    | P_Fld(   0             , MISCTL0_EMIPREEN                 ) \
+                                                                    | P_Fld(   1             , MISCTL0_PG_WAKEUP_OPT            ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SCSMCTRL)           , P_Fld(   1             , SCSMCTRL_SC_PG_MAN_DIS           ) \
+                                                                    | P_Fld( TMRRI_MODE      , SCSMCTRL_SC_PG_UPD_OPT           ));
+
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHUCTRL1)           , P_Fld(   0x1a          , SHUCTRL1_FC_PRDCNT               )); //TODO
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DVFS_TIMING_CTRL1)  , P_Fld(   1             , DVFS_TIMING_CTRL1_DMSHU_CNT      ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFPEND1)           , P_Fld(   0x5           , REFPEND1_MPENDREFCNT_TH0         ) \
+                                                                    | P_Fld(   0x5           , REFPEND1_MPENDREFCNT_TH1         ) \
+                                                                    | P_Fld(   0x5           , REFPEND1_MPENDREFCNT_TH2         ) \
+                                                                    | P_Fld(   0x5           , REFPEND1_MPENDREFCNT_TH3         ) \
+                                                                    | P_Fld(   0x5           , REFPEND1_MPENDREFCNT_TH4         ) \
+                                                                    | P_Fld(   0x3           , REFPEND1_MPENDREFCNT_TH5         ) \
+                                                                    | P_Fld(   0x3           , REFPEND1_MPENDREFCNT_TH6         ) \
+                                                                    | P_Fld(   0x3           , REFPEND1_MPENDREFCNT_TH7         ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1)     , P_Fld(   0x10          , CBT_WLEV_CTRL1_CATRAIN_INTV      ) \
+                                                                    | P_Fld(   0x3           , CBT_WLEV_CTRL1_CATRAINLAT        ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0)            , P_Fld(   1             , TX_SET0_DRSCLR_EN                ) \
+                                                                    | P_Fld( !TMRRI_MODE     , TX_SET0_RK_SCINPUT_OPT           ));
+
+    if(A_T->LP45_APHY_COMB_EN == 1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0)        , P_Fld(   1             , TX_SET0_OE_DOWNGRADE             ));
+    }
+    //@Jouling, UI reloade path is updated. (DQSOSCR_SREF_TXUI_RELOAD_OPT)
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR)            , P_Fld(   0             , DQSOSCR_SREF_TXUI_RELOAD_OPT     ) \
+                                                                    | P_Fld(   1             , DQSOSCR_SREF_TXPI_RELOAD_OPT     ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD)           , P_Fld(   1             , DUMMY_RD_DRS_SELFWAKE_DMYRD_DIS  ) \
+                                                                    | P_Fld(   2             , DUMMY_RD_RANK_NUM                ) \
+                                                                    | P_Fld(   1             , DUMMY_RD_DUMMY_RD_SW             ) \
+                                                                    | P_Fld(   1             , DUMMY_RD_DQSG_DMYRD_EN           ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD_INTV)      , P_Fld(   0             , DUMMY_RD_INTV_DUMMY_RD_CNT7      ) \
+                                                                    | P_Fld(   1             , DUMMY_RD_INTV_DUMMY_RD_CNT6      ) \
+                                                                    | P_Fld(   1             , DUMMY_RD_INTV_DUMMY_RD_CNT5      ) \
+                                                                    | P_Fld(   0             , DUMMY_RD_INTV_DUMMY_RD_CNT4      ) \
+                                                                    | P_Fld(   1             , DUMMY_RD_INTV_DUMMY_RD_CNT3      ) \
+                                                                    | P_Fld(   0             , DUMMY_RD_INTV_DUMMY_RD_CNT2      ) \
+                                                                    | P_Fld(   0             , DUMMY_RD_INTV_DUMMY_RD_CNT1      ) \
+                                                                    | P_Fld(   0             , DUMMY_RD_INTV_DUMMY_RD_CNT0      ));
+    //Byte Mode choose
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC)          , P_Fld( p->dram_cbt_mode[RANK_0] , RK_DQSOSC_RK0_BYTE_MODE          ));
+    vSetRank(p, RANK_1);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC)          , P_Fld( p->dram_cbt_mode[RANK_1] , RK_DQSOSC_RK0_BYTE_MODE          ));
+    vSetRank(p, RANK_0);
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_TRACKING_SET0)   , P_Fld(   0             , TX_TRACKING_SET0_TX_TRACKING_OPT ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_CG_SET0)         , P_Fld(   1             , TX_CG_SET0_SELPH_4LCG_DIS        ));
+
+    //DVFS support SRAM_EN only
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0), P_Fld(DV_p.SRAM_EN, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL1)        , P_Fld(   1             , SWCMD_CTRL1_WRFIFO_MODE2         ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DBG_CMDDEC_CMDSEL0) , P_Fld( M_LP4->EX_ROW_EN[0], DBG_CMDDEC_CMDSEL0_RANK0_10GBEN ) \
+                                                                    | P_Fld( M_LP4->EX_ROW_EN[1], DBG_CMDDEC_CMDSEL0_RANK1_10GBEN ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DBIWR_PROTECT)      , P_Fld(   1             , DBIWR_PROTECT_DBIWR_IMP_EN        ) \
+                                                                    | P_Fld(   0             , DBIWR_PROTECT_DBIWR_PINMUX_EN     ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0)            , P_Fld(   1             , RX_SET0_PRE_DLE_VLD_OPT           ) \
+                                                                    | P_Fld(   7             , RX_SET0_DATLAT_PDLE_TH            ));
+
+    //TODO SRAM DPM control
+    // @Darren, sync MP settings from Joe (APB will be available when SRAM DMA access)
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0)    , P_Fld(   1             , MISC_SRAM_DMA0_PENABLE_LAT_WR     ) \
+                                                                    | P_Fld(   1             , MISC_SRAM_DMA0_KEEP_APB_ARB_ENA   ) \
+                                                                    | P_Fld(   1             , MISC_SRAM_DMA0_KEEP_SRAM_ARB_ENA  ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_MD32_REG_SSPM_MCLK_DIV), P_Fld(   1             , SSPM_MCLK_DIV_MCLK_DCM_EN         ));
+
+    //Indivial random sync
+    vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL1),   0xFFFFFFFF);
+    vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL4),   0xFFFFFFFF);
+    vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL7),   0xFFFFFFFF);
+}
+
+#if 0
+void DVFS_config(DRAMC_CTX_T *p)
+{
+    U8 DVFS_NO_QUEUE_FLASH = 0;
+
+    //1. DVFS flow control
+
+     //2. Relationship among groups -- Save & Restore
+}
+#endif
+static void IO_Release(DRAMC_CTX_T *p)
+{
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1)        , P_Fld(   1             , MISC_CTRL1_R_DM_TX_ARCLK_OE      ) \
+                                                                    | P_Fld(   1             , MISC_CTRL1_R_DM_TX_ARCMD_OE      ));
+    if(LPDDR5_EN_S == 1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2)        , P_Fld(   1             , B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0  ) \
+                                                                    | P_Fld(   1             , B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0 ) \
+                                                                    | P_Fld(   1             , B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0 ) \
+                                                                    | P_Fld(   1             , B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0) );
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2)        , P_Fld(   1             , B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1  ) \
+                                                                    | P_Fld(   1             , B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1 ) \
+                                                                    | P_Fld(   1             , B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1 ) \
+                                                                    | P_Fld(   1             , B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1) );
+    }
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7)           , P_Fld(   0             , CA_CMD7_RG_TX_ARCLKB_PULL_DN     ) \
+                                                                    | P_Fld(   0             , CA_CMD7_RG_TX_ARCLKB_PULL_UP     ) \
+                                                                    | P_Fld(   0             , CA_CMD7_RG_TX_ARCLK_PULL_DN      ) \
+                                                                    | P_Fld(   0             , CA_CMD7_RG_TX_ARCLK_PULL_UP      ) \
+                                                                    | P_Fld(   0             , CA_CMD7_RG_TX_ARCS0_PULL_DN      ) \
+                                                                    | P_Fld(   0             , CA_CMD7_RG_TX_ARCS0_PULL_UP      ) \
+                                                                    | P_Fld(   0             , CA_CMD7_RG_TX_ARCMD_PULL_DN      ) \
+                                                                    | P_Fld(   0             , CA_CMD7_RG_TX_ARCMD_PULL_UP      ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7)            , P_Fld(   0             , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0  ) \
+                                                                    | P_Fld(   0             , B0_DQ7_RG_TX_ARDQS0B_PULL_UP_B0  ) \
+                                                                    | P_Fld(   0             , B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0   ) \
+                                                                    | P_Fld(   0             , B0_DQ7_RG_TX_ARDQS0_PULL_UP_B0   ) \
+                                                                    | P_Fld(   0             , B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0   ) \
+                                                                    | P_Fld(   0             , B0_DQ7_RG_TX_ARDQM0_PULL_UP_B0   ) \
+                                                                    | P_Fld(   0             , B0_DQ7_RG_TX_ARDQ_PULL_DN_B0     ) \
+                                                                    | P_Fld(   0             , B0_DQ7_RG_TX_ARDQ_PULL_UP_B0     ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7)            , P_Fld(   0             , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1  ) \
+                                                                    | P_Fld(   0             , B1_DQ7_RG_TX_ARDQS0B_PULL_UP_B1  ) \
+                                                                    | P_Fld(   0             , B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1   ) \
+                                                                    | P_Fld(   0             , B1_DQ7_RG_TX_ARDQS0_PULL_UP_B1   ) \
+                                                                    | P_Fld(   0             , B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1   ) \
+                                                                    | P_Fld(   0             , B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1   ) \
+                                                                    | P_Fld(   0             , B1_DQ7_RG_TX_ARDQ_PULL_DN_B1     ) \
+                                                                    | P_Fld(   0             , B1_DQ7_RG_TX_ARDQ_PULL_UP_B1     ));
+    //for dram spec CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA will help to fix CKE=0 before  for meet 10ns tINIT2
+    //Assert DRAM reset PIN
+    #if !SA_CONFIG_EN
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1)        , P_Fld(   1             , MISC_CTRL1_R_DMDA_RRESETB_I      ));
+    #endif
+}
+
+static void DVFS_PRE_config(DRAMC_CTX_T *p)
+{
+#if (fcFOR_CHIP_ID == fc8195)
+    U32 MCP_EN = 0; //remove for MCP timing issue
+#else
+    U32 MCP_EN = 1; //for MCP should adjust some setting between CHs (A-B/C-D)
+#endif
+    U32 REF_104M_EN = 1;
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    mcSHOW_DBG_MSG(("Enter into  DVFS_PRE_config >>>>> \n"));
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0)         , P_Fld(   1             , DVFS_CTRL0_VRCG_EN                               ) \
+                                                                    | P_Fld(   0             , DVFS_CTRL0_DVFS_SYNC_MASK                        ) \
+                                                                    | P_Fld(   1             , DVFS_CTRL0_MR13_SHU_EN                           ) \
+                                                                    | P_Fld(   1             , DVFS_CTRL0_HWSET_WLRL                            ) \
+                                                                    | P_Fld(   0             , DVFS_CTRL0_MRWWOPRA                              )); //Have to fix 0, 1 with bug (some bank without precharge)
+    //for DVFS sync
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RG_DFS_CTRL)  , P_Fld(   0             , MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL            ));//SPM mode TODO should random  0 for SPM mode default
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0  )  , P_Fld(   0             , MISC_SRAM_DMA0_DMA_TIMER_EN                      ));
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA1  )  , P_Fld(   0x1ffff         , MISC_SRAM_DMA1_SPM_RESTORE_STEP_EN               ));
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL7   )  , P_Fld(   1             , MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL               ));
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL    )  , P_Fld(   1             , MISC_DVFSCTL_R_DVFS_PICG_POSTPONE                ) \
+                                                                    | P_Fld(   1             , MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT         ));
+    //for channel balance
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2)     , P_Fld(   0             , MISC_DVFSCTL2_R_CDC_MUX_SEL_OPTION               ) \
+                                                                    | P_Fld(   0             , MISC_DVFSCTL2_R_DVFS_SYNC_MODULE_RST_SEL         ));
+    //Could be randomed
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0    )     , P_Fld(   0             , DVFS_CTRL0_DVFS_CKE_OPT                          ) \
+                                                                    | P_Fld(   1             , DVFS_CTRL0_SCARB_PRI_OPT                         ));
+    //here is a flow??--TODO
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3  )   , P_Fld(   1             , MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK    ) \
+                                                                    | P_Fld(   0             , MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_BCLK    ) \
+                                                                    | P_Fld(   0             , MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_MCLK    ) \
+                                                                    | P_Fld(   1             , MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK    ) \
+                                                                    | P_Fld(   3             , MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI           ) \
+                                                                    | P_Fld(   1             , MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE          ) \
+                                                                    | P_Fld(   7             , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK) \
+                                                                    | P_Fld(   1             , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_MCLK) \
+                                                                    | P_Fld(   0x3f          , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK) );
+
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CLK_CTRL  )   , P_Fld(   1             , MISC_CLK_CTRL_DVFS_CLK_MEM_SEL                   ) \
+                                                                    | P_Fld(   1             , MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN          ));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3  )   , P_Fld(   0x10          , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK));
+    //flow end??
+
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DVFS_TIMING_CTRL1)  , P_Fld(   1             , DVFS_TIMING_CTRL1_DMSHU_CNT                      )\
+                                                                    | P_Fld(   1             , DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT         ));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2   )  , P_Fld(   0             , MISC_DVFSCTL2_R_DVFS_DLL_CHA                     )\
+                                                                    | P_Fld(   1             , MISC_DVFSCTL2_RG_TOPCK_FMEM_CK_BLOCK_DURING_DFS                     )\
+                                                                    | P_Fld(   1             , MISC_DVFSCTL2_R_DVFS_PARK_N                      )\
+                                                                    | P_Fld(   1             , MISC_DVFSCTL2_R_DVFS_OPTION                      ));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL  )  , P_Fld( REF_104M_EN     , MISC_CKMUX_SEL_RG_52M_104M_SEL                   ));
+
+    //notice here:
+    //*SHU_PHDET_SPM_EN = 1 means during DFS period as master. 2 means slave.
+    U32 MS_DLL_PHDET_FLD,  SLV_DLL_PHDET_FLD;
+    if (!isLP4_DSC)
+    {
+        MS_DLL_PHDET_FLD = MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN;
+        SLV_DLL_PHDET_FLD = MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN;
+    }
+    else
+    {
+        MS_DLL_PHDET_FLD = MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN;
+        SLV_DLL_PHDET_FLD = MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN;
+    }
+
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_OPT    )  , P_Fld(   1             , MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN )\
+                                                                    | P_Fld(   2             , MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN             )\
+                                                                    | P_Fld(   1             , MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN )\
+                                                                    | P_Fld(   2             , SLV_DLL_PHDET_FLD             )\
+                                                                    | P_Fld(   1             , MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN   )\
+                                                                    | P_Fld(   1             , MS_DLL_PHDET_FLD               ));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL    )  , P_Fld((REF_104M_EN==1)?3:1, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW           ) \
+                                                                    | P_Fld((REF_104M_EN==1)?3:1, MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW          ) \
+                                                                    | P_Fld((REF_104M_EN==1)?3:1, MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW          ) );
+    if(A_T->DLL_ASYNC_EN == 0)
+    {
+        mcSHOW_DBG_MSG6(("Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. \n"));
+        //DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+        vSetPHY2ChannelMapping(p, CHANNEL_B);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2   )  , 0             , MISC_DVFSCTL2_R_DVFS_DLL_CHA                  );
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_OPT    )  , 2             , MS_DLL_PHDET_FLD            );
+        #if (CHANNEL_NUM > 2)
+			if (channel_num_auxadc > 2) {
+		        vSetPHY2ChannelMapping(p, CHANNEL_D);
+        		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2   )  , 0             , MISC_DVFSCTL2_R_DVFS_DLL_CHA                  );
+		        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_OPT    )  , 2             , MS_DLL_PHDET_FLD            );
+				}
+        #endif
+        vSetPHY2ChannelMapping(p, CHANNEL_A);
+        //DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+
+
+    if(MCP_EN == 1)
+    {
+        //DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+        vSetPHY2ChannelMapping(p, CHANNEL_B);
+        mcSHOW_DBG_MSG6(("MCP Enable leading 2ch's sync singles should adjust delay margin."));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL    )  , P_Fld((REF_104M_EN==1)?6:4, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW        ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3  )   , P_Fld(   9                , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK    ));
+        #if (CHANNEL_NUM > 2)
+		    if (channel_num_auxadc > 2) {
+		        vSetPHY2ChannelMapping(p, CHANNEL_D);
+		        mcSHOW_DBG_MSG6(("MCP Enable leading 2ch's sync singles should adjust delay margin."));
+		        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL    )  , P_Fld((REF_104M_EN==1)?6:4, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW        ));
+		        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3  )   , P_Fld(   9                , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK    ));
+		    	}
+        #endif
+        vSetPHY2ChannelMapping(p, CHANNEL_A);
+        //DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+
+
+    //DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL  )  , 1             , MISC_CKMUX_SEL_FMEM_CK_MUX );
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0)         , 0             , DVFS_CTRL0_R_DRAMC_CHA     );
+    vSetPHY2ChannelMapping(p, CHANNEL_B);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL  )  , 3             , MISC_CKMUX_SEL_FMEM_CK_MUX );
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0)         , 0             , DVFS_CTRL0_R_DRAMC_CHA     );
+    #if (CHANNEL_NUM>2)
+	    if (channel_num_auxadc > 2) {
+		    vSetPHY2ChannelMapping(p, CHANNEL_C);
+		    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL  )  , 1             , MISC_CKMUX_SEL_FMEM_CK_MUX );
+		    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0)         , 0             , DVFS_CTRL0_R_DRAMC_CHA     );
+		    vSetPHY2ChannelMapping(p, CHANNEL_D);
+		    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL  )  , 3             , MISC_CKMUX_SEL_FMEM_CK_MUX );
+		    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0)         , 0             , DVFS_CTRL0_R_DRAMC_CHA     );
+	    	}
+    #endif
+    vSetPHY2ChannelMapping(p, CHANNEL_A);
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    mcSHOW_DBG_MSG6(("Exit from  DVFS_PRE_config <<<<< \n"));
+}
+
+void DIG_STATIC_SETTING(DRAMC_CTX_T *p)
+{
+    DIG_PHY_config(p);
+    GATING_MODE_CFG(&Gat_p);
+    DPHY_GAT_TRACK_Config(p,&Gat_p);
+    DRAMC_COMMON_Config(p);
+    #if 1//!SA_CONFIG_EN
+    DVFS_PRE_config(p);//for DVFS initial config.-- bring-up no need this code. but DVFS will need this
+    #endif
+    DDRPHY_PICG_Config(p);
+    IO_Release(p);
+    RX_INTPUT_Config(p);//TODO dummy write trigger
+}
+
+#if FOR_DV_SIMULATION_USED
+void DPI_DIG_init(void)
+{
+    mysetscope();
+    DIG_STATIC_SETTING(DramcConfig);
+}
+#endif
diff --git a/src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c b/src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c
new file mode 100644
index 000000000000..e483dfdcf9b2
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c
@@ -0,0 +1,751 @@
+#include "dramc_dv_init.h"
+
+//====================================
+//TX CA delay configuration
+//------------------------------------
+//Notice:
+//TX config with shuffle register with all data_rate the same
+//if under real IC , need to banlance the PI/Dline calibrated result
+//====================================
+static void DIG_CONFIG_SHUF_ALG_TXCA(DRAMC_CTX_T *p, int ch_id, int group_id)
+{
+    mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id));
+
+    U8 backup_ch_id = p->channel;
+    u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
+    u8 TX_UI;
+
+    TX_UI = (DFS(group_id)->data_rate<=800) ? 1: 0 ; //TODO -- LPDDR5 need  confirm
+
+    vSetPHY2ChannelMapping(p, ch_id);
+
+    p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA1), P_Fld(  0  , SHU_SELPH_CA1_TXDLY_CS   )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA1_TXDLY_CKE  )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA1_TXDLY_ODT  )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA1_TXDLY_RESET)\
+                                                              | P_Fld(  0  , SHU_SELPH_CA1_TXDLY_WE   )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA1_TXDLY_CAS  )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA1_TXDLY_RAS  )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA1_TXDLY_CS1  ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA2), P_Fld(  0  , SHU_SELPH_CA2_TXDLY_BA0  )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA2_TXDLY_BA1  )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA2_TXDLY_BA2  )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA2_TXDLY_CKE1 ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3), P_Fld(  0  , SHU_SELPH_CA3_TXDLY_RA0  )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA3_TXDLY_RA1  )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA3_TXDLY_RA2  )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA3_TXDLY_RA3  )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA3_TXDLY_RA4  )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA3_TXDLY_RA5  )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA3_TXDLY_RA6  )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA3_TXDLY_RA7  ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA4), P_Fld(  0  , SHU_SELPH_CA4_TXDLY_RA8  )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA4_TXDLY_RA9  )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA4_TXDLY_RA10 )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA4_TXDLY_RA11 )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA4_TXDLY_RA12 )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA4_TXDLY_RA13 )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA4_TXDLY_RA14 )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA4_TXDLY_RA15 ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), P_Fld(  TX_UI  , SHU_SELPH_CA5_DLY_CS     )\
+                                                              | P_Fld(  1  , SHU_SELPH_CA5_DLY_CKE    )\
+                                                              | P_Fld(  0  , SHU_SELPH_CA5_DLY_ODT    )\
+                                                              | P_Fld(  1  , SHU_SELPH_CA5_DLY_RESET  )\
+                                                              | P_Fld(  1  , SHU_SELPH_CA5_DLY_WE     )\
+                                                              | P_Fld(  1  , SHU_SELPH_CA5_DLY_CAS    )\
+                                                              | P_Fld(  1  , SHU_SELPH_CA5_DLY_RAS    )\
+                                                              | P_Fld(  TX_UI  , SHU_SELPH_CA5_DLY_CS1    ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA6), P_Fld(  1  , SHU_SELPH_CA6_DLY_BA0    )\
+                                                              | P_Fld(  1  , SHU_SELPH_CA6_DLY_BA1    )\
+                                                              | P_Fld(  1  , SHU_SELPH_CA6_DLY_BA2    )\
+                                                              | P_Fld(  1  , SHU_SELPH_CA6_DLY_CKE1   ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7), P_Fld(  TX_UI  , SHU_SELPH_CA7_DLY_RA0    )\
+                                                              | P_Fld(  TX_UI  , SHU_SELPH_CA7_DLY_RA1    )\
+                                                              | P_Fld(  TX_UI  , SHU_SELPH_CA7_DLY_RA2    )\
+                                                              | P_Fld(  TX_UI  , SHU_SELPH_CA7_DLY_RA3    )\
+                                                              | P_Fld(  TX_UI  , SHU_SELPH_CA7_DLY_RA4    )\
+                                                              | P_Fld(  TX_UI  , SHU_SELPH_CA7_DLY_RA5    )\
+                                                              | P_Fld(  TX_UI  , SHU_SELPH_CA7_DLY_RA6    )\
+                                                              | P_Fld(  TX_UI  , SHU_SELPH_CA7_DLY_RA7    ));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA8), P_Fld(  TX_UI  , SHU_SELPH_CA8_DLY_RA8    )\
+                                                              | P_Fld(  TX_UI  , SHU_SELPH_CA8_DLY_RA9    )\
+                                                              | P_Fld(  TX_UI  , SHU_SELPH_CA8_DLY_RA10   )\
+                                                              | P_Fld(  TX_UI  , SHU_SELPH_CA8_DLY_RA11   )\
+                                                              | P_Fld(  TX_UI  , SHU_SELPH_CA8_DLY_RA12   )\
+                                                              | P_Fld(  TX_UI  , SHU_SELPH_CA8_DLY_RA13   )\
+                                                              | P_Fld(  TX_UI  , SHU_SELPH_CA8_DLY_RA14   )\
+                                                              | P_Fld(  TX_UI  , SHU_SELPH_CA8_DLY_RA15   ));
+
+    vSetPHY2ChannelMapping(p, backup_ch_id);
+    p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
+
+    mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id));
+}
+
+//====================================
+//Impdance configuration
+//------------------------------------
+//Notice:
+//ANA result depend on calibration
+//====================================
+static void DIG_CONFIG_SHUF_IMP(DRAMC_CTX_T *p, int ch_id, int group_id)
+{
+    mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id));
+    U8  IPM_ODT_EN;
+    U8  CHKCYCLE      = 7; //200ns algrith --TODO, @Darren, fix hw imp tracking
+    U8  TXDLY_CMD     = 8; //Need algrithm support .. RL . TODO
+    U8  backup_ch_id  = p->channel;
+    u8  backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
+    vSetPHY2ChannelMapping(p, ch_id);
+    p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
+
+    IPM_ODT_EN = (DFS(group_id)->data_rate>=2667) ? 1 : 0;
+    if (DFS(group_id)->data_rate>=4266)
+        TXDLY_CMD = 0xc;
+    else if (DFS(group_id)->data_rate>=3733)
+        TXDLY_CMD = 0xb;
+    else if (DFS(group_id)->data_rate>=3200)
+        TXDLY_CMD = 0xa;
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_DRVING2)           , P_Fld(!IPM_ODT_EN          , SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN            ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1)           , P_Fld(CHKCYCLE             , SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE              )\
+                                                                             | P_Fld(8                    , SHU_MISC_IMPCAL1_IMPCAL_CALICNT               )\
+                                                                             | P_Fld(4                    , SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE           )\
+                                                                             | P_Fld(0x40                    , SHU_MISC_IMPCAL1_IMPCALCNT                    ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12)               , P_Fld(IPM_ODT_EN?0x1b:0x0f , SHU_CA_CMD12_RG_RIMP_REV                      ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1), P_Fld(1                    , MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVP_UPD_DIS )\
+                                                                             | P_Fld(1                    , MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVN_UPD_DIS )\
+                                                                             | P_Fld(1                    , MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_ODTN_UPD_DIS ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_DRVING6)           , P_Fld(TXDLY_CMD            , SHU_MISC_DRVING6_IMP_TXDLY_CMD                ));
+
+    vSetPHY2ChannelMapping(p, backup_ch_id);
+    p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
+    mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id));
+}
+
+//====================================
+//RX input delay configuration by mode choose
+//------------------------------------
+//Notice:
+//
+//====================================
+static void DIG_CONFIG_SHUF_RXINPUT(DRAMC_CTX_T *p, int ch_id, int group_id)
+{
+    U8 PERBYTE_TRACK_EN = 1;//TODO
+    U8 DQM_TRACK_EN     = 0;//TODO --following RD DBI
+    U8 DQM_FLOW_DQ_SEL  = 3;//TODO
+    U8 RX_force_upd     = 0;//TODO
+
+    U8 backup_ch_id = p->channel;
+    u8  backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
+    vSetPHY2ChannelMapping(p, ch_id);
+    p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
+
+    mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id));
+    if(RX_force_upd == 1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ8), P_Fld(1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ8), P_Fld(1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1));
+    }
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7)  , P_Fld(PERBYTE_TRACK_EN  , SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) \
+                                                              | P_Fld(DQM_FLOW_DQ_SEL   , SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0   ) \
+                                                              | P_Fld(DQM_TRACK_EN      , SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0  ) \
+                                                              | P_Fld(DQM_TRACK_EN      , SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0      ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7)  , P_Fld(PERBYTE_TRACK_EN  , SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) \
+                                                              | P_Fld(DQM_FLOW_DQ_SEL   , SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1   ) \
+                                                              | P_Fld(DQM_TRACK_EN      , SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1  ) \
+                                                              | P_Fld(DQM_TRACK_EN      , SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1      ));
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11) , 1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11) , 1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD5) , 1, CA_CMD5_RG_RX_ARCLK_DVS_EN);
+
+    vSetPHY2ChannelMapping(p, backup_ch_id);
+    p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
+
+    mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id));
+}
+
+#if ENABLE_WDQS_MODE_2
+static void WDQSMode2TxDQOE_CNT(DRAMC_CTX_T *p, U8 *u1DQOE_CNT)
+{
+    switch (p->frequency)
+    {
+        case 1866:
+            *u1DQOE_CNT = 6;
+            break;
+        case 1600:
+        case 1200:
+        case 800:
+        case 600:
+            *u1DQOE_CNT = 5;
+            break;
+        case 933:
+            *u1DQOE_CNT = 4;
+            break;
+        case 400:
+            *u1DQOE_CNT = 9;
+            break;
+        default:
+            mcSHOW_ERR_MSG(("[WDQSMode2TxDQOE_CNT] frequency err!\n"));
+            #if __ETT__
+            while (1);
+            #endif
+    }
+}
+#endif
+
+//====================================
+// MISC shuffle register fit
+//------------------------------------
+//Notice:
+//   MISC shuffle reigster should be fixed
+//====================================
+static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
+{
+    U8 PICG_MODE     = 1;
+    U8 LP5_HEFF      = 0;//TODO
+    U8 LP5WRAPEN     = 1;//Could random 1bit
+    U8 DQSIEN_DQSSTB_MODE=0;
+    U8 irank         = 0;
+    U8 LP5_CASMODE   = 1; //TODO  Impact AC timing  1,2,3 three mode support  1:Low Power; 2:Low Freq; 3:High Eff;
+    U8 WCKDUAL       = 0;
+    U8 NEW_RANK_MODE = 1;
+    U8 DUALSCHEN     = 1;
+    U8 backup_rank   = 0;
+    U8 DQOE_OPT = 0, DQOE_CNT = 0;
+
+    #if ENABLE_WDQS_MODE_2
+    DQOE_OPT = 1;
+    WDQSMode2TxDQOE_CNT(p, &DQOE_CNT);
+    #endif
+
+    backup_rank = p->rank;
+
+    mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] MISC >>>>>, group_id=%2d \n", group_id));
+    if(LPDDR4_EN_S)
+    {
+        DUALSCHEN = (A_D->DQ_P2S_RATIO==4) ? 0 : 1;
+    }
+    else if (LPDDR5_EN_S)
+    {
+        DUALSCHEN = (A_D->CA_P2S_RATIO==2) ? 0 : 1;
+    }
+
+
+    switch(DFS(group_id)->DQSIEN_MODE)
+    {
+        case 1: {DQSIEN_DQSSTB_MODE = 1;break;}
+        case 2: {DQSIEN_DQSSTB_MODE = 2;break;}
+        case 3: {DQSIEN_DQSSTB_MODE = 3;break;}
+        case 6: {DQSIEN_DQSSTB_MODE = 2;break;}
+        case 7: {DQSIEN_DQSSTB_MODE = 3;break;}
+        default: mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] Unexpected DFS(group_id)->DQSIEN_MODE=%1d input, group_id=%2d, \n",DFS(group_id)->DQSIEN_MODE, group_id));
+    }
+
+    switch(LP5_CASMODE)
+    {
+        case 1: {WCKDUAL=0;LP5_HEFF=0;break;}
+        case 2: {WCKDUAL=1;LP5_HEFF=0;break;}
+        case 3: {WCKDUAL=0;LP5_HEFF=1;break;}
+        default: mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] Unexpected LP5_CASMODE(%d) input\n",LP5_CASMODE));
+    }
+
+
+    U8 backup_ch_id = p->channel;
+    u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
+
+    vSetPHY2ChannelMapping(p, ch_id);
+
+    p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0)       , P_Fld(  1                                    , SHU_COMMON0_BL4               ) \
+                                                                   | P_Fld( (A_D->DQ_P2S_RATIO==8)                , SHU_COMMON0_FREQDIV4          ) \
+                                                                   | P_Fld( (A_D->DQ_P2S_RATIO==4)                , SHU_COMMON0_FDIV2             ) \
+                                                                   | P_Fld( LPDDR4_EN_S                           , SHU_COMMON0_BC4OTF            ) \
+                                                                   | P_Fld( !(A_D->DQ_P2S_RATIO==4)               , SHU_COMMON0_DM64BITEN         ));//TODO
+    if(LPDDR5_EN_S == 1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0)     , P_Fld( (A_D->DQ_P2S_RATIO==16)             , SHU_COMMON0_FREQDIV8          ) \
+                                                                     | P_Fld( (DFS(group_id)->data_rate>=3733)    , SHU_COMMON0_LP5BGEN           ) \
+                                                                     | P_Fld( (DFS(group_id)->data_rate<=3200)    , SHU_COMMON0_LP5BGOTF          ) \
+                                                                     | P_Fld( LP5_HEFF                            , SHU_COMMON0_LP5WCKON          ) \
+                                                                     | P_Fld( (DFS(group_id)->data_rate>=4800)    , SHU_COMMON0_DLE256EN          ) \
+                                                                     | P_Fld( LP5WRAPEN                           , SHU_COMMON0_LP5WRAPEN         ) \
+                                                                     | P_Fld( LP5_HEFF                            , SHU_COMMON0_LP5HEFF_MODE      ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL)     , P_Fld( WCKDUAL                          , SHU_WCKCTRL_WCKDUAL           ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL_1)   , P_Fld( (A_D->CKR==2)                        , SHU_WCKCTRL_1_WCKSYNC_PRE_MODE));//TODO
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_LP5_CMD)     , P_Fld( (A_D->CA_P2S_RATIO==2)               , SHU_LP5_CMD_LP5_CMD1TO2EN     ));//TODO
+    }
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_ACTIMING_CONF), P_Fld(  1                                     , SHU_ACTIMING_CONF_TREFBWIG      ) \
+                                                                  | P_Fld(  54                                    , SHU_ACTIMING_CONF_SCINTV        ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_DCM_CTRL0)    , P_Fld(  1                                     , SHU_DCM_CTRL0_FASTWAKE2         ) \
+                                                                  | P_Fld(  1                                     , SHU_DCM_CTRL0_FASTWAKE          ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_CONF0)        , P_Fld(  1                                     , SHU_CONF0_ADVPREEN              ) \
+                                                                  | P_Fld(  63                                    , SHU_CONF0_DMPGTIM               ) \
+                                                                  | P_Fld(  0                                     , SHU_CONF0_REFTHD                ) \
+                                                                  | P_Fld(  1                                     , SHU_CONF0_PBREFEN               ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_MATYPE)       , P_Fld(  2                                     , SHU_MATYPE_MATYPE               ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCHEDULER)    , P_Fld(  DUALSCHEN                             , SHU_SCHEDULER_DUALSCHEN         ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0)          , P_Fld(   1                                    , TX_SET0_WPRE2T                  ));
+    //TODO SHU_TX_SET0_WPST1P5T OVER3200 DRAM spec need 1 but in TBA should random
+    //OE_EXT2UI strange rule.--TODO
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0)      , P_Fld(  (A_D->DQ_P2S_RATIO==4)                , SHU_TX_SET0_WDATRGO             ) \
+                                                                  | P_Fld(  (DFS(group_id)->data_rate>=3200)      , SHU_TX_SET0_WPST1P5T            ) \
+                                                                  | P_Fld(   DQOE_OPT                                    , SHU_TX_SET0_DQOE_OPT            ) \
+                                                                  | P_Fld(   DQOE_CNT                                    , SHU_TX_SET0_DQOE_CNT            ) \
+                                                                  | P_Fld(  LPDDR5_EN_S                           , SHU_TX_SET0_OE_EXT2UI           ) \
+                                                                  | P_Fld(  ((DFS(group_id)->data_rate==1600) && (A_D->DQ_P2S_RATIO==8))?5:2, SHU_TX_SET0_TXUPD_W2R_SEL        )); //TODO
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL1), P_Fld(  0x30                                  , MISC_SHU_STBCAL1_STB_PI_TRACKING_RATIO) \
+                                                                  | P_Fld(  1                                     , MISC_SHU_STBCAL1_STB_UPDMASK_EN ) \
+                                                                  | P_Fld(  9                                     , MISC_SHU_STBCAL1_STB_UPDMASKCYC ) \
+                                                                  | P_Fld(  (DFS(group_id)->data_rate > 1600)     , MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL)); //TODO
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld(  Gat_p.GAT_TRACK_EN                    , MISC_SHU_STBCAL_STBCALEN          ) \
+                                                                  | P_Fld(  Gat_p.GAT_TRACK_EN                    , MISC_SHU_STBCAL_STB_SELPHCALEN    ) \
+                                                                  | P_Fld(  DQSIEN_DQSSTB_MODE                    , MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE)); //TODO
+
+    //@Darren, NOTE: Fix gating error or fifo mismatch => DMSTBLAT date_rate=1866 >= 3 : 1
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld( (((Gat_p.GAT_TRACK_EN)&&(DFS(group_id)->data_rate>=1866))?(2+Gat_p.VALID_LAT_VALUE):(0+Gat_p.VALID_LAT_VALUE)) , MISC_SHU_STBCAL_DMSTBLAT    ) \
+                                                                  | P_Fld(   1                                    , MISC_SHU_STBCAL_PICGLAT         ) \
+                                                                  | P_Fld(   1                                    , MISC_SHU_STBCAL_DQSG_MODE       ) \
+                                                                  | P_Fld(   PICG_MODE                            , MISC_SHU_STBCAL_DQSIEN_PICG_MODE));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), P_Fld(   PICG_MODE                            , MISC_SHU_RANKCTL_RANK_RXDLY_OPT ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_MISC         ), P_Fld(   1                                    , SHU_MISC_REQQUE_MAXCNT          ));
+    for(irank = RANK_0; irank < p->support_rank_num; irank++)
+    {
+        vSetRank(p, irank);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL), P_Fld(  0                     , MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT) \
+                                                                                  | P_Fld(  (A_D->DQ_P2S_RATIO == 4)  , MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT));
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_CKE_CTRL)                 ,  0         , SHURK_CKE_CTRL_CKE_DBE_CNT                 );
+    }
+    vSetRank(p, backup_rank);
+
+    //RODT offset TODO
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB), P_Fld(  1                                   , MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN       ) \
+                                                                    | P_Fld(  0                                   , MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE         ) \
+                                                                    | P_Fld(  (NEW_RANK_MODE)?1:PICG_MODE         , MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE     ) \
+                                                                    | P_Fld(  1                                   , MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) \
+                                                                    | P_Fld(  ((A_D->DQ_P2S_RATIO == 4)?2:0)      , MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET     ) \
+                                                                    | P_Fld(  ((A_D->DQ_P2S_RATIO == 4)?1:4)      , MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET     ) \
+                                                                    | P_Fld(  ((A_D->DQ_P2S_RATIO == 16)?19:((A_D->DQ_P2S_RATIO == 8)?13:10))    , MISC_SHU_RODTENSTB_RODTENSTB_EXT            ));
+
+    //[SV] //SHL, fix RODT rd_period low 1T issue
+    // @Darren, confirm MP settings w/ Chau-Wei Wang (Jason)
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB1), P_Fld( ((DFS(group_id)->data_rate >=3200)?1:0)   , MISC_SHU_RODTENSTB1_RODTENCGEN_TAIL         ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB1), P_Fld( ((DFS(group_id)->data_rate >=3200)?2:1)   , MISC_SHU_RODTENSTB1_RODTENCGEN_HEAD         ));
+
+    switch (A_D->DQ_P2S_RATIO)
+    {
+        case  4:
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 1          , MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 0          , MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE  ) \
+                                                                                | P_Fld( 0          , MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE  ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT1        ), P_Fld( 1          , MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT          ) \
+                                                                                | P_Fld( 1          , MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT        ) \
+                                                                                | P_Fld( 0          , MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT        ));
+            break;
+        }
+        case  8:
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 2          , MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 1          , MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE  ) \
+                                                                                | P_Fld( 1          , MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE  ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT1        ), P_Fld( 0          , MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT          ) \
+                                                                                | P_Fld( 0          , MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT        ) \
+                                                                                | P_Fld( 0          , MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT        ));
+            break;
+        }
+        case  16:
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 3          , MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 2          , MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE  ) \
+                                                                                | P_Fld( 2          , MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE  ));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT1        ), P_Fld( 0          , MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT          ) \
+                                                                                | P_Fld( 0          , MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT        ) \
+                                                                                | P_Fld( 0          , MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT        ));
+            break;
+        }
+        default:mcSHOW_ERR_MSG(("ERROR:Unexcepted A_D.DQ_P2S_RATIO = %2d \n", A_D->DQ_P2S_RATIO));
+    }
+
+    vSetPHY2ChannelMapping(p, backup_ch_id);
+    p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
+
+    mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] MISC <<<<<<, group_id=%2d \n", group_id));
+}
+
+static void DIG_CONFIG_SHUF_DQSGRETRY(DRAMC_CTX_T *p, int ch_id, int group_id)
+{
+    U8 backup_ch_id = p->channel;
+    u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
+
+    vSetPHY2ChannelMapping(p, ch_id);
+    mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id=%2d \n", group_id));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_DQSG_RETRY1), P_Fld( 0                                , MISC_SHU_DQSG_RETRY1_RETRY_SW_RESET        ) \
+                                                                      | P_Fld( 0                                , MISC_SHU_DQSG_RETRY1_RETRY_SW_EN           ) \
+                                                                      | P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS    ) \
+                                                                      | P_Fld( 0                                , MISC_SHU_DQSG_RETRY1_RETRY_ONCE            ) \
+                                                                      | P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_3TIMES          ) \
+                                                                      | P_Fld( 0                                , MISC_SHU_DQSG_RETRY1_RETRY_1RANK           ) \
+                                                                      | P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_BY_RANK         ) \
+                                                                      | P_Fld( 0                                , MISC_SHU_DQSG_RETRY1_RETRY_DM4BYTE         ) \
+                                                                      | P_Fld( 0                                , MISC_SHU_DQSG_RETRY1_RETRY_DQSIENLAT       ) \
+                                                                      | P_Fld( 0                                , MISC_SHU_DQSG_RETRY1_RETRY_STBENCMP_ALLBYTE) \
+                                                                      | P_Fld( 0                                , MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN     ) \
+                                                                      | P_Fld( 0 /*@Darren, sync MP settings by YT (DFS(group_id)->data_rate>=3733)*/ , MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE    ) \
+                                                                      | P_Fld( 0                                , MISC_SHU_DQSG_RETRY1_RETRY_CMP_DATA        ) \
+                                                                      | P_Fld( 0                                , MISC_SHU_DQSG_RETRY1_RETRY_ALE_BLOCK_MASK  ) \
+                                                                      | P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE     ) \
+                                                                      | P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_USE_NON_EXTEND  ) \
+                                                                      | P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_USE_CG_GATING   ) \
+                                                                      | P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM       ) \
+                                                                      | P_Fld( 0                                , MISC_SHU_DQSG_RETRY1_RETRY_RANKSEL_FROM_PHY) \
+                                                                      | P_Fld( 0                                , MISC_SHU_DQSG_RETRY1_RETRY_PA_DISABLE      ) \
+                                                                      | P_Fld( 0                                , MISC_SHU_DQSG_RETRY1_RETRY_STBEN_RESET_MSK ) \
+                                                                      | P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE  ));
+
+    vSetPHY2ChannelMapping(p, backup_ch_id);
+    p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
+    mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id=%2d \n", group_id));
+}
+
+static void DIG_CONFIG_SHUF_DBI(DRAMC_CTX_T *p, int ch_id, int group_id)
+{
+    U8 RD_DBI_EN = 1;//TODO
+    U8 WR_DBI_EN = 1;//TODO
+
+    U8 backup_ch_id = p->channel;
+    u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
+
+    mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] DBI >>>>>>, group_id=%2d \n",  group_id));
+    if(LPDDR4_EN_S)
+    {
+        LP4_DRAM_CONFIG_T LP4_temp;
+        memset((void *)&LP4_temp, 0, sizeof(LP4_temp));
+
+        LP4_DRAM_config(DFS(group_id)->data_rate,&LP4_temp);
+        RD_DBI_EN = LP4_temp.DBI_RD;
+        WR_DBI_EN = LP4_temp.DBI_WR;
+    }
+#if __LP5_COMBO__
+    else
+    {//TODO LPDDR5 and other dram type not ready
+        LP5_DRAM_CONFIG_T LP5_temp;
+        memset((void *)&LP5_temp, 0, sizeof(LP5_temp));
+
+        LP5_DRAM_config(DFS(group_id),&LP5_temp);
+        RD_DBI_EN = LP5_temp.DBI_RD;
+        WR_DBI_EN = LP5_temp.DBI_WR;
+    }
+#endif
+
+    vSetPHY2ChannelMapping(p, ch_id);
+    p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7), P_Fld(RD_DBI_EN, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0    ) \
+                                                            | P_Fld(RD_DBI_EN, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7), P_Fld(RD_DBI_EN, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1    ) \
+                                                            | P_Fld(RD_DBI_EN, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), P_Fld(WR_DBI_EN, SHU_TX_SET0_DBIWR               ));
+
+    vSetPHY2ChannelMapping(p, backup_ch_id);
+    p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
+    mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] DBI <<<<<<, group_id=%2d \n",  group_id));
+}
+
+//TODO LPDDR5
+static void DIG_CONFIG_SHUF_DVFSWLRL(DRAMC_CTX_T *p, int ch_id, int group_id)
+{
+    U8 backup_ch_id = p->channel;
+    u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
+
+    U8  HWSET_MR13_OP_Value   =0;
+    U8  HWSET_VRCG_OP_Value   =0;
+    U8  HWSET_MR2_OP_Value    =0;
+
+    mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id=%2d \n",  group_id));
+    p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
+
+    if(LPDDR4_EN_S)
+    {
+        LP4_DRAM_CONFIG_T LP4_temp;
+        memset((void *)&LP4_temp, 0, sizeof(LP4_temp));
+
+        LP4_DRAM_config (DFS(group_id)->data_rate,&LP4_temp);
+
+        HWSET_MR13_OP_Value = ((LP4_temp.WORK_FSP & 1) << 7) | ((LP4_temp.WORK_FSP & 1) << 6) | (( 0 << 5) | 8); //DMI default enable
+        HWSET_VRCG_OP_Value = ((LP4_temp.WORK_FSP & 1) << 7) | ((LP4_temp.WORK_FSP & 1) << 6);
+        HWSET_MR2_OP_Value  = ((LP4_temp.MR_WL & 7) << 3) | (LP4_temp.MR_WL & 7);
+    } else {
+        mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] LPDDR5 have to use Run-time MRW to support DVFS! Do not Use HWSET_MR serial Registers."));
+    }
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), P_Fld(HWSET_MR13_OP_Value, SHU_HWSET_MR13_HWSET_MR13_OP ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), P_Fld(HWSET_VRCG_OP_Value, SHU_HWSET_VRCG_HWSET_VRCG_OP ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), P_Fld(0xb                , SHU_HWSET_VRCG_VRCGDIS_PRDCNT));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR2 ), P_Fld(HWSET_MR2_OP_Value , SHU_HWSET_MR2_HWSET_MR2_OP   ));
+    vSetPHY2ChannelMapping(p, backup_ch_id);
+    p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
+
+    mcSHOW_DBG_MSG6(("[test_sa.c]====>ch_id:%2d, group_id:%2d, DPI_TBA_DVFS_WLRL_setting Exit\n", ch_id, group_id));
+}
+
+#if __LP5_COMBO__
+void DIG_CONFG_SHU_LP5_WCK(DRAMC_CTX_T *p, int ch_id, int group_id)
+{
+    U8 backup_ch_id = p->channel;
+    u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
+
+    U8 BYTEMODE_EN=0;//TODO
+    U8 READ_DBI=0;
+    U8 DVFSC_DIS=0;
+    U8 WCK_offset_by_UI=0;
+    U8 tWCKENL_WR=0;
+    U8 tWCKPRE_WR_Static=0;
+    U8 tWCKENL_RD_DBION=0;
+    U8 tWCKENL_RD_DBIOFF=0;
+    U8 tWCKPRE_RD_Static=0;
+    U8 tWCKENL_FS=0;
+    U8 tWCKPRE_FS_Static=0;
+
+    U8 WCK_WR_MCK=0;
+    U8 WCK_RD_MCK=0;
+    U8 WCK_FS_MCK=0;
+    U8 WCK_WR_UI=0;
+    U8 WCK_RD_UI=0;
+    U8 WCK_FS_UI=0;
+
+    U8 irank = 0;
+    U8 ui_ratio = 2;
+    //write and FS
+    if(DFS(group_id)->CKR==2) {
+               if(((DFS(group_id)->data_rate)>  40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_WR =1;tWCKPRE_WR_Static =1;tWCKENL_FS =0;tWCKPRE_FS_Static =1;}
+          else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_WR =0;tWCKPRE_WR_Static =2;tWCKENL_FS =0;tWCKPRE_FS_Static =2;}
+          else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_WR =1;tWCKPRE_WR_Static =2;tWCKENL_FS =1;tWCKPRE_FS_Static =2;}
+          else if(((DFS(group_id)->data_rate)>1600) && (((DFS(group_id)->data_rate)<=2133))) {tWCKENL_WR =2;tWCKPRE_WR_Static =3;tWCKENL_FS =1;tWCKPRE_FS_Static =3;}
+          else if(((DFS(group_id)->data_rate)>2133) && (((DFS(group_id)->data_rate)<=2750))) {tWCKENL_WR =1;tWCKPRE_WR_Static =4;tWCKENL_FS =1;tWCKPRE_FS_Static =4;}
+          else if(((DFS(group_id)->data_rate)>2750) && (((DFS(group_id)->data_rate)<=3200))) {tWCKENL_WR =3;tWCKPRE_WR_Static =4;tWCKENL_FS =2;tWCKPRE_FS_Static =4;}
+      } else if (DFS(group_id)->CKR==4){
+               if(((DFS(group_id)->data_rate)>  40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_WR =0;tWCKPRE_WR_Static =1;tWCKENL_FS =0;tWCKPRE_FS_Static =1;}
+          else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_WR =0;tWCKPRE_WR_Static =1;tWCKENL_FS =0;tWCKPRE_FS_Static =1;}
+          else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_WR =1;tWCKPRE_WR_Static =1;tWCKENL_FS =1;tWCKPRE_FS_Static =1;}
+          else if(((DFS(group_id)->data_rate)>1600) && (((DFS(group_id)->data_rate)<=2133))) {tWCKENL_WR =1;tWCKPRE_WR_Static =2;tWCKENL_FS =1;tWCKPRE_FS_Static =2;}
+          else if(((DFS(group_id)->data_rate)>2133) && (((DFS(group_id)->data_rate)<=2750))) {tWCKENL_WR =1;tWCKPRE_WR_Static =2;tWCKENL_FS =1;tWCKPRE_FS_Static =2;}
+          else if(((DFS(group_id)->data_rate)>2750) && (((DFS(group_id)->data_rate)<=3200))) {tWCKENL_WR =2;tWCKPRE_WR_Static =2;tWCKENL_FS =1;tWCKPRE_FS_Static =2;}
+          else if(((DFS(group_id)->data_rate)>3200) && (((DFS(group_id)->data_rate)<=3733))) {tWCKENL_WR =2;tWCKPRE_WR_Static =3;tWCKENL_FS =1;tWCKPRE_FS_Static =3;}
+          else if(((DFS(group_id)->data_rate)>3733) && (((DFS(group_id)->data_rate)<=4267))) {tWCKENL_WR =2;tWCKPRE_WR_Static =3;tWCKENL_FS =1;tWCKPRE_FS_Static =3;}
+          else if(((DFS(group_id)->data_rate)>4267) && (((DFS(group_id)->data_rate)<=4800))) {tWCKENL_WR =3;tWCKPRE_WR_Static =3;tWCKENL_FS =2;tWCKPRE_FS_Static =3;}
+          else if(((DFS(group_id)->data_rate)>4800) && (((DFS(group_id)->data_rate)<=5500))) {tWCKENL_WR =3;tWCKPRE_WR_Static =4;tWCKENL_FS =2;tWCKPRE_FS_Static =4;}
+          else if(((DFS(group_id)->data_rate)>5500) && (((DFS(group_id)->data_rate)<=6000))) {tWCKENL_WR =4;tWCKPRE_WR_Static =4;tWCKENL_FS =2;tWCKPRE_FS_Static =4;}
+          else if(((DFS(group_id)->data_rate)>6000) && (((DFS(group_id)->data_rate)<=6400))) {tWCKENL_WR =4;tWCKPRE_WR_Static =4;tWCKENL_FS =2;tWCKPRE_FS_Static =4;}
+      } else {
+          mcSHOW_ERR_MSG(("[DIG_CONFG_SHU_LP5_WCK] ERROR: Unexpected CKR!!! "));
+      }
+
+    //read
+    if(DVFSC_DIS == 1)
+    {
+        if(DFS(group_id)->CKR==2) {
+                 if(((DFS(group_id)->data_rate)>  40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
+            else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =2;}
+            else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_RD_DBIOFF =1;tWCKENL_RD_DBION =BYTEMODE_EN?3:1;tWCKPRE_RD_Static =2;}
+            else if(((DFS(group_id)->data_rate)>1600) && (((DFS(group_id)->data_rate)<=2133))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?4:2;tWCKENL_RD_DBION =4;tWCKPRE_RD_Static =3;}
+            else if(((DFS(group_id)->data_rate)>2133) && (((DFS(group_id)->data_rate)<=2750))) {tWCKENL_RD_DBIOFF =3;tWCKENL_RD_DBION =BYTEMODE_EN?5:3;tWCKPRE_RD_Static =4;}
+            else if(((DFS(group_id)->data_rate)>2750) && (((DFS(group_id)->data_rate)<=3200))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?7:5;tWCKENL_RD_DBION =7;tWCKPRE_RD_Static =4;}
+        } else if (DFS(group_id)->CKR==4){
+                 if(((DFS(group_id)->data_rate)>  40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
+            else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
+            else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_RD_DBIOFF =1;tWCKENL_RD_DBION =BYTEMODE_EN?2:1;tWCKPRE_RD_Static =1;}
+            else if(((DFS(group_id)->data_rate)>1600) && (((DFS(group_id)->data_rate)<=2133))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?2:1;tWCKENL_RD_DBION =2;tWCKPRE_RD_Static =2;}
+            else if(((DFS(group_id)->data_rate)>2133) && (((DFS(group_id)->data_rate)<=2750))) {tWCKENL_RD_DBIOFF =2;tWCKENL_RD_DBION =BYTEMODE_EN?3:2;tWCKPRE_RD_Static =2;}
+            else if(((DFS(group_id)->data_rate)>2750) && (((DFS(group_id)->data_rate)<=3200))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?4:3;tWCKENL_RD_DBION =4;tWCKPRE_RD_Static =2;}
+            else if(((DFS(group_id)->data_rate)>3200) && (((DFS(group_id)->data_rate)<=3733))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?4:3;tWCKENL_RD_DBION =BYTEMODE_EN?5:4;tWCKPRE_RD_Static =3;}
+            else if(((DFS(group_id)->data_rate)>3733) && (((DFS(group_id)->data_rate)<=4267))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?5:4;tWCKENL_RD_DBION =BYTEMODE_EN?6:5;tWCKPRE_RD_Static =3;}
+            else if(((DFS(group_id)->data_rate)>4267) && (((DFS(group_id)->data_rate)<=4800))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?6:5;tWCKENL_RD_DBION =BYTEMODE_EN?7:6;tWCKPRE_RD_Static =3;}
+            else if(((DFS(group_id)->data_rate)>4800) && (((DFS(group_id)->data_rate)<=5500))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?7:6;tWCKENL_RD_DBION =BYTEMODE_EN?8:7;tWCKPRE_RD_Static =4;}
+            else if(((DFS(group_id)->data_rate)>5500) && (((DFS(group_id)->data_rate)<=6000))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?7:6;tWCKENL_RD_DBION =BYTEMODE_EN?9:7;tWCKPRE_RD_Static =4;}
+            else if(((DFS(group_id)->data_rate)>6000) && (((DFS(group_id)->data_rate)<=6400))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?8:7;tWCKENL_RD_DBION =BYTEMODE_EN?10:8;tWCKPRE_RD_Static=4;}
+        } else {
+            mcSHOW_ERR_MSG(("[DIG_CONFG_SHU_LP5_WCK] ERROR: Unexpected CKR!!! "));
+        }
+
+    } else {
+        if(DFS(group_id)->CKR==2) {
+                 if(((DFS(group_id)->data_rate)>  40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
+            else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?2:0;tWCKENL_RD_DBION =2;tWCKPRE_RD_Static =2;}
+            else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_RD_DBIOFF =3;tWCKENL_RD_DBION =BYTEMODE_EN?5:3;tWCKPRE_RD_Static =2;}
+        } else if (DFS(group_id)->CKR==4){
+                 if(((DFS(group_id)->data_rate)>  40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
+            else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?1:0;tWCKENL_RD_DBION =1;tWCKPRE_RD_Static =1;}
+            else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_RD_DBIOFF =2;tWCKENL_RD_DBION =BYTEMODE_EN?3:2;tWCKPRE_RD_Static =1;}
+        } else {
+            mcSHOW_ERR_MSG(("[DIG_CONFG_SHU_LP5_WCK] ERROR: Unexpected CKR!!! "));
+        }
+    }
+    //=====================================
+    //Algrithm
+    //=====================================
+    WCK_offset_by_UI = (DFS(group_id)->DQ_P2S_RATIO==4) ?  0 :
+    	               (DFS(group_id)->DQ_P2S_RATIO==8) ? ((DFS(group_id)->CKR==4) ? 1 : -5) :
+    	               (DFS(group_id)->DQ_P2S_RATIO==16) ? -5 : 0;
+
+    WCK_WR_UI = ((tWCKENL_WR + tWCKPRE_WR_Static) * DFS(group_id)->CKR * ui_ratio) + WCK_offset_by_UI;
+    WCK_RD_UI = (((READ_DBI?tWCKENL_RD_DBION:tWCKENL_RD_DBIOFF) + tWCKPRE_RD_Static) * DFS(group_id)->CKR * ui_ratio) + WCK_offset_by_UI;
+    WCK_FS_UI = ((tWCKENL_FS + tWCKPRE_FS_Static) * DFS(group_id)->CKR * ui_ratio) + WCK_offset_by_UI;
+
+
+    //=====================================
+    //setting
+    //=====================================
+    p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
+
+    for(irank = RANK_0; irank < RANK_MAX; irank++)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_WR_MCK), P_Fld(WCK_WR_MCK, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) \
+                                                                     | P_Fld(WCK_WR_MCK, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_RD_MCK), P_Fld(WCK_RD_MCK, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) \
+                                                                     | P_Fld(WCK_RD_MCK, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_FS_MCK), P_Fld(WCK_FS_MCK, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) \
+                                                                     | P_Fld(WCK_FS_MCK, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_WR_UI) , P_Fld(WCK_WR_UI , SHURK_WCK_WR_UI_WCK_WR_B0_UI  ) \
+                                                                     | P_Fld(WCK_WR_UI , SHURK_WCK_WR_UI_WCK_WR_B1_UI  ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_RD_UI) , P_Fld(WCK_RD_UI , SHURK_WCK_RD_UI_WCK_RD_B0_UI  ) \
+                                                                     | P_Fld(WCK_RD_UI , SHURK_WCK_RD_UI_WCK_RD_B1_UI  ));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_FS_UI) , P_Fld(WCK_FS_UI , SHURK_WCK_FS_UI_WCK_FS_B0_UI  ) \
+                                                                     | P_Fld(WCK_FS_UI , SHURK_WCK_FS_UI_WCK_FS_B1_UI  ));
+    }
+    vSetPHY2ChannelMapping(p, backup_ch_id);
+    p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
+}
+#endif
+
+//=================================================
+//Jump ratio calculate and setting
+//------------------------------------------------
+//notice: 400 800 not support tracking TODO
+//  should confirm it with DQ_SEMI_OPEN =1 or not but not data_rate as condition
+//
+//================================================
+#if 0
+void TX_RX_jumpratio_calculate(DRAMC_CTX_T *p,int ch_id,int group_id)
+{
+    int tar;
+    int ratio = 32;
+    int result[DFS_GROUP_NUM];
+
+    U8 backup_ch_id = p->channel;
+    u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
+
+    vSetPHY2ChannelMapping(p, ch_id);
+    mcSHOW_DBG_MSG(("[TX_RX_jumpratio_calculate]>>>>>>>> group_id = %1d",group_id));
+    for(tar = 0; tar<DFS_GROUP_NUM;tar++)
+    {
+        if(((DFS(group_id)->data_rate == 800) || (DFS(group_id)->data_rate == 400)) || ((DFS(tar)->data_rate == 800) || (DFS(tar)->data_rate == 400))) //TODO wihtout tracking
+        {
+            result[tar] = 0;
+        }
+        else
+        {
+            result[tar] = (int)(((float)(DFS(tar)->data_rate) * (float)ratio) / (float)(DFS(group_id)->data_rate) + 0.5); //+0.5 for roundup
+        }
+        mcSHOW_DBG_MSG(("\n[TXRX_jumpratio]current_group data_rate=%1d,tar_data_rate=%1d,jumpratio=%1d;\n",DFS(group_id)->data_rate,DFS(tar)->data_rate,result[tar]));
+    }
+    //=============================
+    //setting
+    //=============================
+    p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_FREQ_RATIO_SET0), P_Fld(   result[0]  , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0) \
+                                                                    | P_Fld(   result[1]  , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) \
+                                                                    | P_Fld(   result[2]  , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) \
+                                                                    | P_Fld(   result[3]  , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_FREQ_RATIO_SET1), P_Fld(   result[4]  , SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4) \
+                                                                    | P_Fld(   result[5]  , SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5) \
+                                                                    | P_Fld(   result[6]  , SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6) \
+                                                                    | P_Fld(   result[7]  , SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_FREQ_RATIO_SET2), P_Fld(   result[8]  , SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8) \
+                                                                    | P_Fld(   result[9]  , SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9));
+    vSetPHY2ChannelMapping(p, backup_ch_id);
+    p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
+    mcSHOW_DBG_MSG(("[TX_RX_jumpratio_calculate]<<<<<<< group_id = %1d",group_id));
+}
+#endif
+
+static void DIG_CONFIG_DVFS_DEPENDENCE(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
+{
+    DIG_CONFIG_SHUF_DVFSWLRL(p,ch_id,group_id);
+    //TX_RX_jumpratio_calculate(p,ch_id,group_id);
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_DVFSDLL ) , P_Fld((LPDDR4_EN_S==1)?0x37:0x37   , MISC_SHU_DVFSDLL_R_DLL_IDLE        )\
+                                                                    | P_Fld((LPDDR4_EN_S==1)?0x4d:0x37   , MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE    )\
+                                                                    | P_Fld(   ana_top_p.ALL_SLAVE_EN    , MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL  )\
+                                                                    | P_Fld(             0               , MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL  ));
+}
+
+//====================================
+// Digital shuffle configuration entry
+//------------------------------------
+//Notice:
+//
+//====================================
+void DIG_CONFIG_SHUF(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
+{
+    DIG_CONFIG_SHUF_ALG_TXCA(p,ch_id,group_id);
+    DIG_CONFIG_SHUF_IMP(p,ch_id,group_id);
+    DIG_CONFIG_SHUF_RXINPUT(p,ch_id,group_id);
+    DIG_CONFIG_SHUF_MISC_FIX(p,ch_id,group_id);
+    DIG_CONFIG_SHUF_DQSGRETRY(p,ch_id,group_id);
+    DIG_CONFIG_SHUF_DBI(p,ch_id,group_id);
+    DIG_CONFIG_DVFS_DEPENDENCE(p,ch_id,group_id);
+}
+
+
+#if 0
+static void OTHER_GP_INIT(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
+{
+    U8 backup_ch_id = p->channel;
+    U8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
+
+    //notice here.  Replace the A_D A_T with new frequency auto-generation
+    ANA_TOP_FUNCTION_CFG(A_T,DFS(group_id)->data_rate);
+    ANA_CLK_DIV_config(A_D,DFS(group_id));
+
+    p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
+    ANA_sequence_shuffle_colletion(p,A_D);//these RG will be set during flow,but for DV another GP should be set directly
+    ANA_Config_shuffle(p,A_T,group_id);
+    DIG_CONFIG_SHUF(p,ch_id,group_id);
+    vSetPHY2ChannelMapping(p, backup_ch_id);
+    p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
+}
+#endif
+
+#if FOR_DV_SIMULATION_USED
+void DPI_OTHER_GP_INIT(U32 ch_id, U32 group_id)
+{
+    mysetscope();
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    OTHER_GP_INIT(DramcConfig,ch_id,group_id);
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    conf_to_sram_sudo(0,group_id,1);
+    conf_to_sram_sudo(1,group_id,1);
+    //DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    //vSetPHY2ChannelMapping(DramcConfig, CHANNEL_A);
+    //DRAMC_DMA_CONF_to_SRAM(DramcConfig,group_id,1);
+    //vSetPHY2ChannelMapping(DramcConfig, CHANNEL_B);
+    //DRAMC_DMA_CONF_to_SRAM(DramcConfig,group_id,1);
+    //vSetPHY2ChannelMapping(DramcConfig, CHANNEL_A);
+    //DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+}
+#endif
diff --git a/src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c b/src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c
new file mode 100644
index 000000000000..f1f2fc79fcc3
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c
@@ -0,0 +1,321 @@
+#include "dramc_dv_init.h"
+
+DRAM_TYPE_T MEM_TYPE = LPDDR4;
+LP4_DRAM_CONFIG_T LP4_INIT;
+LP5_DRAM_CONFIG_T LP5_INIT;
+ANA_top_config_T ana_top_p;
+ANA_DVFS_CORE_T ANA_option;
+DRAMC_DVFS_GROUP_CONFIG_T DFS_TOP[DFS_GROUP_NUM];
+DRAMC_SUBSYS_CONFIG_T DV_p;
+
+
+void ANA_TOP_FUNCTION_CFG(ANA_top_config_T *tr,U16 data_rate)
+{
+   // tr-> DLL_ASYNC_EN     = 0   ; //from DV random
+   // tr-> NEW_RANK_MODE    = 1   ; //from DV random
+   // tr-> DLL_IDLE_MODE    = 1   ; //from DV random
+   // tr-> LP45_APHY_COMB_EN= 1   ; //from DV define
+   // tr-> NEW_8X_MODE      = 1   ;
+
+
+    tr->ALL_SLAVE_EN     = (data_rate <= 1866)?1:0;
+
+    if(LPDDR5_EN_S == 1)
+    {
+        tr->TX_ODT_DIS = (data_rate <=3200) ? 1 : 0 ;
+    } else {
+        tr->TX_ODT_DIS = (data_rate <=2400) ? 1 : 0 ;
+    }
+
+    mcSHOW_DBG_MSG6(("=================================== \n"));
+    mcSHOW_DBG_MSG6(("ANA top config\n"              ));
+    mcSHOW_DBG_MSG6(("=================================== \n"));
+    mcSHOW_DBG_MSG6(("DLL_ASYNC_EN            = %2d\n",tr->DLL_ASYNC_EN     ));
+    mcSHOW_DBG_MSG6(("ALL_SLAVE_EN            = %2d\n",tr->ALL_SLAVE_EN     ));
+    mcSHOW_DBG_MSG6(("NEW_RANK_MODE           = %2d\n",tr->NEW_RANK_MODE    ));
+    mcSHOW_DBG_MSG6(("DLL_IDLE_MODE           = %2d\n",tr->DLL_IDLE_MODE    ));
+    mcSHOW_DBG_MSG6(("LP45_APHY_COMB_EN       = %2d\n",tr->LP45_APHY_COMB_EN));
+    mcSHOW_DBG_MSG6(("TX_ODT_DIS              = %2d\n",tr->TX_ODT_DIS       ));
+    mcSHOW_DBG_MSG6(("NEW_8X_MODE             = %2d\n",tr->NEW_8X_MODE      ));
+    mcSHOW_DBG_MSG6(("=================================== \n"));
+}
+
+
+void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs)
+{
+    U32  SEMI_OPEN_FMIN = 300;
+    U32  SEMI_OPEN_FMAX = 500; //lp4 600
+    U32  PI_FMIN        = 600;
+    U32  DQ_PICK;
+    U32  CA_PICK;    //U
+    U32  CA_MCKIO;   //S
+    U32  MCKIO_SEMI; //Q
+    U16  data_rate;
+
+    data_rate = dfs->data_rate;
+    tr->DQ_P2S_RATIO = dfs->DQ_P2S_RATIO;
+    tr->CKR = dfs->CKR;
+
+    //tr->CA_P2S_RATIO
+    tr->CA_P2S_RATIO = tr->DQ_P2S_RATIO/tr->CKR;
+
+    //tr->DQ_CA_OPEN
+    tr->DQ_CA_OPEN   = ( data_rate < (SEMI_OPEN_FMIN * 2) ) ? 1 : 0;
+    tr->DQ_SEMI_OPEN = ( data_rate/2 < PI_FMIN ) ? (1-tr->DQ_CA_OPEN) : ((data_rate <= SEMI_OPEN_FMAX*2) ? (1-tr->DQ_CA_OPEN) : 0);
+    tr->CA_SEMI_OPEN = (( data_rate/(tr->CKR*2) < PI_FMIN ) ? ((data_rate/(tr->CKR*2) > SEMI_OPEN_FMAX) ? 0 : (((tr->CA_P2S_RATIO>2)||(tr->DQ_SEMI_OPEN))*(1-tr->DQ_CA_OPEN))) : tr->DQ_SEMI_OPEN);
+    tr->CA_FULL_RATE = (tr->DQ_CA_OPEN == 1) ? ((tr->CKR>1)?1:0) : ((tr->DQ_SEMI_OPEN*tr->CA_SEMI_OPEN*(tr->CKR>>1)) + (( data_rate/(tr->CKR*2) < PI_FMIN) ? (1-tr->CA_SEMI_OPEN) : 0 ));
+    tr->DQ_CKDIV4_EN = ( tr->DQ_SEMI_OPEN == 1) ? DONT_CARE_VALUE : ((( (data_rate/2) < 1200 ) ? 1 : 0 ) * (1-tr->DQ_CA_OPEN)) ;
+
+    CA_MCKIO     = (data_rate/(tr->CKR*2))*(1+tr->CA_FULL_RATE);
+    DQ_PICK      = (tr->DQ_SEMI_OPEN == 1) ? 0 : (data_rate/2) ;
+    CA_PICK      = (tr->CA_SEMI_OPEN == 1) ? CA_MCKIO*2 : ((CA_MCKIO>=PI_FMIN) ? CA_MCKIO : (( CA_MCKIO >= (PI_FMIN/2) ) ? CA_MCKIO*2 : CA_MCKIO *4 ));
+
+    tr->CA_CKDIV4_EN = ((CA_PICK < 1200 ) ? 1 : 0 ) * ( 1- tr->DQ_CA_OPEN) ;
+
+    tr->CA_PREDIV_EN = (data_rate >= 4800) ? 1 : 0 ;
+
+#if SA_CONFIG_EN
+    if(LPDDR4_EN_S)
+    {
+        // @Darren, for LP4 8PH Delay
+        if (data_rate <= 1866)
+            tr->PH8_DLY = 0;
+        else if (data_rate <= 2400)
+            tr->PH8_DLY = 0x12;
+        else if (data_rate <= 3200)
+            tr->PH8_DLY = 0xd;
+        else if (data_rate <= 4266)
+            tr->PH8_DLY = 0x8;
+        else
+            tr->PH8_DLY = 0x7;
+    }
+    else
+#endif
+    {
+        tr->PH8_DLY = ((tr->DQ_CA_OPEN == 0) && (tr->DQ_SEMI_OPEN == 0) && (tr->DQ_CKDIV4_EN  == 0)) ? ( (1000000>>4)/data_rate -4) : DONT_CARE_VALUE;
+    }
+
+    MCKIO_SEMI = (tr->DQ_SEMI_OPEN * tr->CA_SEMI_OPEN * (data_rate/2)) + (1-tr->DQ_SEMI_OPEN) * tr->CA_SEMI_OPEN * CA_MCKIO;
+
+    tr->SEMI_OPEN_CA_PICK_MCK_RATIO = ( MCKIO_SEMI == 0) ? DONT_CARE_VALUE : (CA_PICK*tr->DQ_P2S_RATIO)/data_rate ; //need to be improved
+
+    tr->DQ_AAMCK_DIV = (tr->DQ_SEMI_OPEN == 0) ? ((tr->DQ_P2S_RATIO/2)*(1-tr->DQ_SEMI_OPEN)) : DONT_CARE_VALUE;
+    tr->CA_AAMCK_DIV = (tr->CA_SEMI_OPEN == 0) ? ((tr->DQ_P2S_RATIO/(2*tr->CKR))*(1+tr->CA_FULL_RATE)) : DONT_CARE_VALUE;
+    tr->CA_ADMCK_DIV = CA_PICK/(data_rate/tr->DQ_P2S_RATIO); //need to be improved
+    //tr->DQ_TRACK_CA_EN = ((data_rate/2) >= 2133) ? 1 : 0 ; //for Alucary confirm that 'interface timing' sign NOT OK.
+    tr->DQ_TRACK_CA_EN = 0 ;
+    tr->PLL_FREQ = ((DQ_PICK*2*(tr->DQ_CKDIV4_EN+1)) > (CA_PICK*2*(tr->CA_CKDIV4_EN+1))) ? (DQ_PICK*2*(tr->DQ_CKDIV4_EN+1)) : (CA_PICK*2*(tr->CA_CKDIV4_EN+1));
+#if SA_CONFIG_EN
+    //de-sense
+    if(data_rate==2400)
+        tr->PLL_FREQ = 2366;   //DDR2366
+    else if(data_rate==1200)
+        tr->PLL_FREQ = 2288;   //DDR1144
+    else if(data_rate==3200 || data_rate==1600)
+        tr->PLL_FREQ = 3068;   //DDR3068 DDR1534
+    else if(data_rate==800)
+        tr->PLL_FREQ = 3016;   //DDR754
+    else if(data_rate==400)
+        tr->PLL_FREQ = 1600;   //DDR400 1600/div4
+#endif
+    tr->DQ_UI_PI_RATIO = 32; //TODO:notice here. infact if DQ_SEMI_OPEM == 1 UI_PI_RATIO will only 4 lower 2bit wihtout use
+    tr->CA_UI_PI_RATIO = (tr->CA_SEMI_OPEN == 0) ? ((tr->CA_FULL_RATE == 1)? 64 : DONT_CARE_VALUE) : 32;
+
+    mcSHOW_DBG_MSG6(("=================================== \n"));
+    mcSHOW_DBG_MSG6(("data_rate                  = %4d\n"    ,data_rate                      ));
+    mcSHOW_DBG_MSG6(("CKR                        = %1d\n"    ,tr->CKR                        ));
+    mcSHOW_DBG_MSG6(("DQ_P2S_RATIO               = %1d\n"    ,tr->DQ_P2S_RATIO               ));
+    mcSHOW_DBG_MSG6(("=================================== \n"));
+    mcSHOW_DBG_MSG6(("CA_P2S_RATIO               = %1d\n"    ,tr->CA_P2S_RATIO               ));
+    mcSHOW_DBG_MSG6(("DQ_CA_OPEN                 = %1d\n"    ,tr->DQ_CA_OPEN                 ));
+    mcSHOW_DBG_MSG6(("DQ_SEMI_OPEN               = %1d\n"    ,tr->DQ_SEMI_OPEN               ));
+    mcSHOW_DBG_MSG6(("CA_SEMI_OPEN               = %1d\n"    ,tr->CA_SEMI_OPEN               ));
+    mcSHOW_DBG_MSG6(("CA_FULL_RATE               = %1d\n"    ,tr->CA_FULL_RATE               ));
+    mcSHOW_DBG_MSG6(("DQ_CKDIV4_EN               = %1d\n"    ,tr->DQ_CKDIV4_EN               ));
+    mcSHOW_DBG_MSG6(("CA_CKDIV4_EN               = %1d\n"    ,tr->CA_CKDIV4_EN               ));
+    mcSHOW_DBG_MSG6(("CA_PREDIV_EN               = %1d\n"    ,tr->CA_PREDIV_EN               ));
+    mcSHOW_DBG_MSG6(("PH8_DLY                    = %1d\n"    ,tr->PH8_DLY                    ));
+    mcSHOW_DBG_MSG6(("SEMI_OPEN_CA_PICK_MCK_RATIO= %1d\n"    ,tr->SEMI_OPEN_CA_PICK_MCK_RATIO));
+    mcSHOW_DBG_MSG6(("DQ_AAMCK_DIV               = %1d\n"    ,tr->DQ_AAMCK_DIV               ));
+    mcSHOW_DBG_MSG6(("CA_AAMCK_DIV               = %1d\n"    ,tr->CA_AAMCK_DIV               ));
+    mcSHOW_DBG_MSG6(("CA_ADMCK_DIV               = %1d\n"    ,tr->CA_ADMCK_DIV               ));
+    mcSHOW_DBG_MSG6(("DQ_TRACK_CA_EN             = %1d\n"    ,tr->DQ_TRACK_CA_EN             ));
+    mcSHOW_DBG_MSG6(("CA_PICK                    = %2d\n"    ,CA_PICK                        ));
+    mcSHOW_DBG_MSG6(("CA_MCKIO                   = %1d\n"    ,CA_MCKIO                       ));
+    mcSHOW_DBG_MSG6(("MCKIO_SEMI                 = %1d\n"    ,MCKIO_SEMI                     ));
+    mcSHOW_DBG_MSG6(("PLL_FREQ                   = %1d\n"    ,tr->PLL_FREQ                   ));
+    mcSHOW_DBG_MSG6(("DQ_UI_PI_RATIO             = %1d\n"    ,tr->DQ_UI_PI_RATIO             ));
+    mcSHOW_DBG_MSG6(("CA_UI_PI_RATIO             = %1d\n"    ,tr->CA_UI_PI_RATIO             ));
+    mcSHOW_DBG_MSG6(("=================================== \n"));
+}
+
+void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr)
+{
+   U8 gp_id;
+   tr->SRAM_EN               = 1;
+   tr->MD32_EN               = 1;
+   tr->a_cfg                 = &ana_top_p;
+   tr->a_opt                 = &ANA_option;
+   tr->lp4_init              = &LP4_INIT;
+   tr->lp5_init              = &LP5_INIT;
+
+   for(gp_id = 0; gp_id < DFS_GROUP_NUM; gp_id++)
+   {
+       tr->DFS_GP[gp_id]  = &DFS_TOP[gp_id];
+   }
+
+   if(LPDDR4_EN_S)
+   {
+        (tr->DFS_GP[0])->data_rate = 4266; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
+        (tr->DFS_GP[1])->data_rate = 3200; (tr->DFS_GP[1])->DQ_P2S_RATIO = 8;
+        (tr->DFS_GP[2])->data_rate = 2400; (tr->DFS_GP[2])->DQ_P2S_RATIO = 8;
+        (tr->DFS_GP[3])->data_rate = 1866; (tr->DFS_GP[3])->DQ_P2S_RATIO = 8;
+        (tr->DFS_GP[4])->data_rate = 1600; (tr->DFS_GP[4])->DQ_P2S_RATIO = 4;
+        (tr->DFS_GP[5])->data_rate = 1200; (tr->DFS_GP[5])->DQ_P2S_RATIO = 4;
+        (tr->DFS_GP[6])->data_rate = 800 ; (tr->DFS_GP[6])->DQ_P2S_RATIO = 4;
+        (tr->DFS_GP[7])->data_rate = 400 ; (tr->DFS_GP[7])->DQ_P2S_RATIO = 4;
+        (tr->DFS_GP[8])->data_rate = 4266; (tr->DFS_GP[8])->DQ_P2S_RATIO = 4;
+        (tr->DFS_GP[9])->data_rate = 1600; (tr->DFS_GP[9])->DQ_P2S_RATIO = 4;
+
+       for(gp_id = 0; gp_id < DFS_GROUP_NUM; gp_id++)
+       {
+           (tr->DFS_GP[gp_id])->CKR = 1;
+           (tr->DFS_GP[gp_id])->DQSIEN_MODE = 1;
+       }
+#if 0//DV_CONFIG_EN==1
+       tr->lp4_init->LP4Y_EN         = DUT_p.LP4Y_EN       ;
+       tr->lp4_init->WR_PST          = DUT_p.LP4_WR_PST    ;
+       tr->lp4_init->OTF             = DUT_p.LP4_OTF       ;
+       tr->a_cfg->NEW_8X_MODE        = DUT_p.NEW_8X_MODE   ;
+       tr->a_cfg->LP45_APHY_COMB_EN  = 1                   ;
+       tr->a_cfg->DLL_IDLE_MODE      = DUT_p.DLL_IDLE_MODE ;
+       tr->a_cfg->NEW_RANK_MODE      = DUT_p.NEW_RANK_MODE ;
+       tr->a_cfg->DLL_ASYNC_EN       = DUT_p.DLL_ASYNC_EN  ;
+       tr->MD32_EN                   = DUT_p.MD32_EN       ;
+       tr->SRAM_EN                   = DUT_p.SRAM_EN       ;
+       tr->GP_NUM                    = DUT_p.GP_NUM        ;
+
+
+       for(gp_id = 0; gp_id < DV_p.GP_NUM; gp_id++)
+       {
+           tr->DFS_GP[gp_id]->data_rate    = DUT_shu_p[gp_id].data_rate   ;
+           tr->DFS_GP[gp_id]->DQSIEN_MODE  = DUT_shu_p[gp_id].DQSIEN_MODE ;
+           tr->DFS_GP[gp_id]->DQ_P2S_RATIO = DUT_shu_p[gp_id].DQ_P2S_RATIO;
+           tr->DFS_GP[gp_id]->CKR          = DUT_shu_p[gp_id].CKR         ;
+       }
+#endif
+        #if SA_CONFIG_EN
+        tr->lp4_init->EX_ROW_EN[0]    = p->u110GBEn[RANK_0] ;
+        tr->lp4_init->EX_ROW_EN[1]    = p->u110GBEn[RANK_1] ;
+        tr->lp4_init->BYTE_MODE[0]    = 0                   ;
+        tr->lp4_init->BYTE_MODE[1]    = 0                   ;
+        tr->lp4_init->LP4Y_EN         = 0;//DUT_p.LP4Y_EN       ;
+        tr->lp4_init->WR_PST          = 1;//DUT_p.LP4_WR_PST    ;
+        tr->lp4_init->OTF             = 1;//DUT_p.LP4_OTF       ;
+        tr->a_cfg->NEW_8X_MODE        = 1;//DUT_p.NEW_8X_MODE   ;
+        tr->a_cfg->LP45_APHY_COMB_EN  = 1                   ;
+        tr->a_cfg->DLL_IDLE_MODE      = 1;//DUT_p.DLL_IDLE_MODE ;
+        tr->a_cfg->NEW_RANK_MODE      = 1;//DUT_p.NEW_RANK_MODE ;
+        tr->a_cfg->DLL_ASYNC_EN       = 0;//DUT_p.DLL_ASYNC_EN  ;
+        tr->MD32_EN                   = 0;//DUT_p.MD32_EN       ;
+        tr->SRAM_EN                   = 1;//DUT_p.SRAM_EN       ;
+        tr->GP_NUM                    = 10;//DUT_p.GP_NUM        ;
+
+        if(p->freq_sel==LP4_DDR4266)
+        {
+            (tr->DFS_GP[0])->data_rate = 4266; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
+        }
+        else if(p->freq_sel==LP4_DDR3733)
+        {
+            (tr->DFS_GP[0])->data_rate = 3733; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
+        }
+        else if(p->freq_sel==LP4_DDR3200)
+        {
+            (tr->DFS_GP[0])->data_rate = 3200; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
+        }
+        else if(p->freq_sel==LP4_DDR2400)
+        {
+            (tr->DFS_GP[0])->data_rate = 2400; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
+        }
+        else if(p->freq_sel==LP4_DDR1866)
+        {
+            (tr->DFS_GP[0])->data_rate = 1866; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
+        }
+        else if(p->freq_sel==LP4_DDR1600)
+        {
+            (tr->DFS_GP[0])->data_rate = 1600; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
+        }
+        else if(p->freq_sel==LP4_DDR1200)
+        {
+            (tr->DFS_GP[0])->data_rate = 1200; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
+        }
+        else if(p->freq_sel==LP4_DDR800)
+        {
+            (tr->DFS_GP[0])->data_rate = 800; (tr->DFS_GP[0])->DQ_P2S_RATIO = 4;
+        }
+        else if(p->freq_sel==LP4_DDR400)
+        {
+            (tr->DFS_GP[0])->data_rate = 400; (tr->DFS_GP[0])->DQ_P2S_RATIO = 4;
+        }
+        #endif
+
+//==============================================
+//Oterwise, SA should rebuild Top configuration.
+//==============================================
+
+       LP4_DRAM_config(tr->DFS_GP[0]->data_rate,tr->lp4_init);
+   }
+
+   //TODO for LPDDR5
+   //data_rate        DQ_P2S_RATIO
+   //[4800:6400]      16
+   //[1600:4800)      8
+   //[400 :1600]      4
+   //=========================
+   //data_rate        CKR
+   //[3733:6400]      4
+   //[400 :3733)      2
+
+#if __LP5_COMBO__
+    else if (MEM_TYPE == LPDDR5)
+    {
+        #if SA_CONFIG_EN
+            if(p->freq_sel==LP5_DDR4266)
+            {
+                (tr->DFS_GP[0])->data_rate = 4266; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 2;
+            }
+            else if(p->freq_sel==LP5_DDR5500)
+            {
+                (tr->DFS_GP[0])->data_rate = 5500; (tr->DFS_GP[0])->DQ_P2S_RATIO = 16 ; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 2;
+            }
+            else
+            {
+                (tr->DFS_GP[0])->data_rate = 3200; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[0]->CKR = 2;tr->DFS_GP[0]->DQSIEN_MODE = 1;
+            }
+        #else
+        (tr->DFS_GP[0])->data_rate = 6400; (tr->DFS_GP[0])->DQ_P2S_RATIO = 16; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 1;
+        #endif
+        (tr->DFS_GP[1])->data_rate = 3200; (tr->DFS_GP[1])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[1]->CKR = 2;tr->DFS_GP[1]->DQSIEN_MODE = 1;
+        (tr->DFS_GP[2])->data_rate = 1600; (tr->DFS_GP[2])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[2]->CKR = 2;tr->DFS_GP[2]->DQSIEN_MODE = 1;
+        (tr->DFS_GP[3])->data_rate = 4266; (tr->DFS_GP[3])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[3]->CKR = 4;tr->DFS_GP[3]->DQSIEN_MODE = 1;
+        (tr->DFS_GP[4])->data_rate = 3733; (tr->DFS_GP[4])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[4]->CKR = 4;tr->DFS_GP[4]->DQSIEN_MODE = 1;
+        (tr->DFS_GP[5])->data_rate = 1600; (tr->DFS_GP[5])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[5]->CKR = 2;tr->DFS_GP[5]->DQSIEN_MODE = 1;
+        (tr->DFS_GP[6])->data_rate = 1200; (tr->DFS_GP[6])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[6]->CKR = 2;tr->DFS_GP[6]->DQSIEN_MODE = 1;
+        (tr->DFS_GP[7])->data_rate = 800 ; (tr->DFS_GP[7])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[7]->CKR = 2;tr->DFS_GP[7]->DQSIEN_MODE = 1;
+        (tr->DFS_GP[8])->data_rate = 400 ; (tr->DFS_GP[8])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[8]->CKR = 2;tr->DFS_GP[8]->DQSIEN_MODE = 1;
+        (tr->DFS_GP[9])->data_rate = 5500; (tr->DFS_GP[9])->DQ_P2S_RATIO = 16; tr->DFS_GP[9]->CKR = 4;tr->DFS_GP[9]->DQSIEN_MODE = 1;
+        LP5_DRAM_config(tr->DFS_GP[0],tr->lp5_init);
+    }
+#endif
+    ANA_TOP_FUNCTION_CFG(tr->a_cfg,tr->DFS_GP[0]->data_rate);
+    ANA_CLK_DIV_config(tr->a_opt,tr->DFS_GP[0]);
+    mcSHOW_DBG_MSG6(("=================================== \n"));
+    mcSHOW_DBG_MSG6(("memory_type:%s         \n",LPDDR5_EN_S?"LPDDR5":"LPDDR4"     ));
+    mcSHOW_DBG_MSG6(("GP_NUM     : %1d       \n",tr->GP_NUM      ));
+    mcSHOW_DBG_MSG6(("SRAM_EN    : %1d       \n",tr->SRAM_EN     ));
+    mcSHOW_DBG_MSG6(("MD32_EN    : %1d       \n",tr->MD32_EN     ));
+    mcSHOW_DBG_MSG6(("=================================== \n"));
+    #if DUMP_ALLSUH_RG
+    mcSHOW_DBG_MSG(("[DUMPLOG] %d DQ_MCK_UI_RATIO=%d, DQ_UI_PI_RATIO=%d, CA_UI_PI_RATIO=%d\n", p->frequency * 2, vGet_Div_Mode(p) == DIV8_MODE ? 8 : 4, tr->a_opt->DQ_UI_PI_RATIO, tr->a_opt->CA_UI_PI_RATIO));
+    #endif
+}
diff --git a/src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c b/src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c
new file mode 100644
index 000000000000..81ce6f6163b1
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c
@@ -0,0 +1,414 @@
+#include "dramc_dv_init.h"
+
+//DRAM LP4 initial configuration
+void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr)
+{
+    tr->BYTE_MODE[0] = 0;//TODO
+    tr->BYTE_MODE[1] = 0;//TODO
+#if 0 // @Darren, remove it
+    #if SA_CONFIG_EN
+        tr->EX_ROW_EN[0] = 0;//TODO
+        tr->EX_ROW_EN[1] = 0;//TODO
+    #else
+        tr->EX_ROW_EN[0] = 1;//TODO
+        tr->EX_ROW_EN[1] = 0;//TODO
+    #endif
+#endif
+    tr->MR_WL     = LP4_DRAM_INIT_RLWL_MRfield_config(data_rate);
+    tr->MR_RL     = tr->MR_WL;
+    tr->BL        = 2;
+    tr->RPST      = 0;
+    tr->RD_PRE    = 0;
+    tr->WR_PRE    = 1;
+    tr->WR_PST    = (data_rate>=2667)?1:0; //TODO
+#if SA_CONFIG_EN
+        tr->DBI_WR    = 0;
+        tr->DBI_RD    = 0;
+#else
+        tr->DBI_WR    = (data_rate>=2667)?1:0;
+        tr->DBI_RD    = (data_rate>=2667)?1:0;
+#endif
+    //	tr->DMI       = 1;
+    tr->OTF       = 1;
+#if (ENABLE_LP4Y_DFS && LP4Y_BACKUP_SOLUTION)
+        tr->LP4Y_EN   = (data_rate>=1866)?0:1; //TODO, @Darren for LP4Y
+#else
+        tr->LP4Y_EN   = 0;
+#endif
+    tr->WORK_FSP  = (data_rate>=2667)?1:0;
+
+    mcSHOW_DBG_MSG2(("=================================== \n"));
+    mcSHOW_DBG_MSG2(("LPDDR4 DRAM CONFIGURATION\n"     ));
+    mcSHOW_DBG_MSG2(("=================================== \n"));
+//    mcSHOW_DBG_MSG(("BYTE_MODE    = B%1b\n",tr->BYTE_MODE));
+    mcSHOW_DBG_MSG2(("EX_ROW_EN[0]    = 0x%1x\n",tr->EX_ROW_EN[0]));
+    mcSHOW_DBG_MSG2(("EX_ROW_EN[1]    = 0x%1x\n",tr->EX_ROW_EN[1]));
+    mcSHOW_DBG_MSG2(("LP4Y_EN      = 0x%1x\n",tr->LP4Y_EN  ));
+    mcSHOW_DBG_MSG2(("WORK_FSP     = 0x%1x\n",tr->WORK_FSP ));
+    mcSHOW_DBG_MSG2(("WL           = 0x%1x\n",tr->MR_WL    ));
+    mcSHOW_DBG_MSG2(("RL           = 0x%1x\n",tr->MR_RL    ));
+    mcSHOW_DBG_MSG2(("BL           = 0x%1x\n",tr->BL       ));
+    mcSHOW_DBG_MSG2(("RPST         = 0x%1x\n",tr->RPST     ));
+    mcSHOW_DBG_MSG2(("RD_PRE       = 0x%1x\n",tr->RD_PRE   ));
+    mcSHOW_DBG_MSG2(("WR_PRE       = 0x%1x\n",tr->WR_PRE   ));
+    mcSHOW_DBG_MSG2(("WR_PST       = 0x%1x\n",tr->WR_PST   ));
+    mcSHOW_DBG_MSG2(("DBI_WR       = 0x%1x\n",tr->DBI_WR   ));
+    mcSHOW_DBG_MSG2(("DBI_RD       = 0x%1x\n",tr->DBI_RD   ));
+//  mcSHOW_DBG_MSG(("DMI          = 0x%1x\n",tr->DMI      ));
+    mcSHOW_DBG_MSG2(("OTF          = 0x%1x\n",tr->OTF      ));
+    mcSHOW_DBG_MSG2(("=================================== \n"));
+}
+//LP4 dram initial ModeRegister setting
+U8 LP4_DRAM_INIT_RLWL_MRfield_config(U32 data_rate)
+{
+    U8 MR2_RLWL;
+
+    if      ((data_rate<=4266) && (data_rate > 3733)) {MR2_RLWL = 7 ;}
+    else if ((data_rate<=3733) && (data_rate > 3200)) {MR2_RLWL = 6 ;}
+    else if ((data_rate<=3200) && (data_rate > 2667)) {MR2_RLWL = 5 ;}
+    else if ((data_rate<=2667) && (data_rate > 2400)) {MR2_RLWL = 4 ;}
+    else if ((data_rate<=2400) && (data_rate > 1866)) {MR2_RLWL = 4 ;}
+    else if ((data_rate<=1866) && (data_rate > 1600)) {MR2_RLWL = 3 ;}
+    else if ((data_rate<=1600) && (data_rate > 1200)) {MR2_RLWL = 2 ;}
+    else if ((data_rate<=1200) && (data_rate > 800 )) {MR2_RLWL = 2 ;}
+    else if ((data_rate<=800 ) && (data_rate > 400 )) {MR2_RLWL = 1 ;}
+    else if (data_rate<=400 )                         {MR2_RLWL = 0 ;}
+    else {mcSHOW_ERR_MSG(("ERROR: Unexpected data_rate:%4d under LPDDR4 \n",data_rate));return -1;}
+
+    mcSHOW_DBG_MSG(("[ModeRegister RLWL Config] data_rate:%4d-MR2_RLWL:%1x\n",data_rate,MR2_RLWL));
+
+    return MR2_RLWL;
+}
+
+U32 Get_RL_by_MR_LP4(U8 BYTE_MODE_EN,U8 DBI_EN, U8 MR_RL_field_value)
+{
+    U32 RL=0;
+
+    switch(MR_RL_field_value)
+    {
+        case 0: {RL = 6; break;}
+        case 1: {RL = ((DBI_EN == 1) ? 12 : 10); break;}
+        case 2: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 18 : 16 ) : ((DBI_EN == 1) ? 16 : 14); break;}
+        case 3: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 24 : 22 ) : ((DBI_EN == 1) ? 22 : 20); break;}
+        case 4: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 30 : 28 ) : ((DBI_EN == 1) ? 28 : 24); break;}
+        case 5: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 36 : 32 ) : ((DBI_EN == 1) ? 32 : 28); break;}
+        case 6: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 40 : 36 ) : ((DBI_EN == 1) ? 36 : 32); break;}
+        case 7: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 44 : 40 ) : ((DBI_EN == 1) ? 40 : 36); break;}
+        default:{mcSHOW_ERR_MSG(("ERROR: Unexpected MR_RL_field_value:%1x under LPDDR4 \n",MR_RL_field_value));}
+    }
+
+    mcSHOW_DBG_MSG(("[ReadLatency GET] BYTE_MODE_EN:%1d-DBI_EN:%1d-MR_RL_field_value:%1x-RL:%2d\n",BYTE_MODE_EN,DBI_EN,MR_RL_field_value,RL));
+
+    return RL;
+}
+
+U32 Get_WL_by_MR_LP4(U8 Version, U8 MR_WL_field_value)
+{
+    U32 WL=0;
+
+    switch(MR_WL_field_value)
+    {
+        case 0: {WL = 4; break;}
+        case 1: {WL = ((Version == 0) ? 6  : 8  ); break;}
+        case 2: {WL = ((Version == 0) ? 8  : 12 ); break;}
+        case 3: {WL = ((Version == 0) ? 10 : 18 ); break;}
+        case 4: {WL = ((Version == 0) ? 12 : 22 ); break;}
+        case 5: {WL = ((Version == 0) ? 14 : 26 ); break;}
+        case 6: {WL = ((Version == 0) ? 16 : 30 ); break;}
+        case 7: {WL = ((Version == 0) ? 18 : 34 ); break;}
+        default:{mcSHOW_ERR_MSG(("ERROR: Unexpected MR_WL_field_value:%1x under LPDDR4 \n",MR_WL_field_value));}
+    }
+
+    mcSHOW_DBG_MSG(("[WriteLatency GET] Version:%1d-MR_RL_field_value:%1x-WL:%2d\n",Version,MR_WL_field_value,WL));
+
+    return WL;
+}
+
+#if __LP5_COMBO__
+U32 Get_RL_LP5_DVFSC_DIS( U8 MR_RL_field_value, U8 DBI_EN, U8 BYTE_MODE_EN,U8 CKR)
+{
+    U32 RL=0;
+
+    if(CKR == 2)
+    {
+        switch(MR_RL_field_value)
+        {
+            case 0 : {RL = 6; break;}
+            case 1 : {RL = 8; break;}
+            case 2 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 12 : 10 ) : 10); break;}
+            case 3 : {RL = ((BYTE_MODE_EN == 1) ? ( 14 ) : ((DBI_EN == 1) ? 14 : 12 )); break;}
+            case 4 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 18 : 16 ) : ( 16 )); break;}
+            case 5 : {RL = ((BYTE_MODE_EN == 1) ? ( 20 ) : ((DBI_EN == 1) ? 20 : 18 )); break;}
+            default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected MR_RL_field_value:%d -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
+        }
+    }
+    else if (CKR == 4)
+    {
+        switch(MR_RL_field_value)
+        {
+            case 0 : {RL = 3; break;}
+            case 1 : {RL = 4; break;}
+            case 2 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 6  : 5  ) : ( 5 )); break;}
+            case 3 : {RL = ((BYTE_MODE_EN == 1) ? 7  : ((DBI_EN == 1) ? 7  : 6 )); break;}
+            case 4 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 9  : 8  ) : ( 8 )); break;}
+            case 5 : {RL = ((BYTE_MODE_EN == 1) ? 10 : ((DBI_EN == 1) ? 10 : 9 )); break;}
+            case 6 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 12 : 11 ) : ((DBI_EN == 1) ? 11 : 10)); break;}
+            case 7 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 14 : 13 ) : ((DBI_EN == 1) ? 13 : 12)); break;}
+            case 8 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 15 : 14 ) : ((DBI_EN == 1) ? 14 : 13)); break;}
+            case 9 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 17 : 16 ) : ((DBI_EN == 1) ? 16 : 15)); break;}
+            case 10: {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 19 : 17 ) : ((DBI_EN == 1) ? 17 : 16)); break;}
+            case 11: {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 20 : 18 ) : ((DBI_EN == 1) ? 18 : 17)); break;}
+            default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected MR_RL_field_value:%1x -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
+        }
+    }
+    else
+    {
+        mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected CKR:%1d under LPDDR5 \n",CKR));
+    }
+
+    mcSHOW_DBG_MSG(("[ReadLatency GET] DVFSC_DIS:BYTE_MODE_EN:%1d-DBI_EN:%1d-MR_RL_field_value:%1x-CKR:%2d-RL:%2d\n",BYTE_MODE_EN,DBI_EN,MR_RL_field_value,CKR,RL));
+
+    return RL;
+}
+
+U32 Get_RL_LP5_DVFSC_EN( U8 MR_RL_field_value, U8 DBI_EN, U8 BYTE_MODE_EN,U8 CKR)
+{
+    U32 RL=0;
+
+    if(CKR == 2)
+    {
+        switch(MR_RL_field_value)
+        {
+            case 0 : {RL = 6; break;}
+            case 1 : {RL = ((BYTE_MODE_EN == 1) ? 10 : ((DBI_EN == 1) ? 10 : 8  )); break;}
+            case 2 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 14 : 12 ) : 12); break;}
+            default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_EN: Unexpected MR_RL_field_value:%1d -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
+        }
+    }
+    else if (CKR == 4)
+    {
+        switch(MR_RL_field_value)
+        {
+            case 0 : {RL = 3; break;}
+            case 1 : {RL = ((BYTE_MODE_EN == 1) ? 5 : ((DBI_EN == 1) ? 4  : 5 )); break;}
+            case 2 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 7  : 6  ) : 6); break;}
+            default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_EN:Unexpected MR_RL_field_value:%1x -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
+        }
+    }
+    else
+    {
+        mcSHOW_ERR_MSG(("ERROR: DVFSC_EN:Unexpected CKR:%1d under LPDDR5 \n",CKR));
+    }
+
+    mcSHOW_DBG_MSG(("[ReadLatency GET] DVFSC_EN: BYTE_MODE_EN:%1d-DBI_EN:%1d-MR_RL_field_value:%1x-CKR:%2d-RL:%2d\n",BYTE_MODE_EN,DBI_EN,MR_RL_field_value,CKR,RL));
+
+    return RL;
+}
+
+
+
+//LPDDR5 write Latency Version B not implemented --TODO
+U32 Get_WL_LP5_DVFSC_DIS( U8 MR_RL_field_value,U8 BYTE_MODE_EN,U8 CKR)
+{
+    U32 WL=0;
+
+    if(CKR == 2)
+    {
+        switch(MR_RL_field_value)
+        {
+            case 0 : {WL = 4; break;}
+            case 1 : {WL = 4; break;}
+            case 2 : {WL = 6; break;}
+            case 3 : {WL = 8; break;}
+            case 4 : {WL = 8; break;}
+            case 5 : {WL = 10; break;}
+            default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected MR_RL_field_value:%1d -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
+        }
+    }
+    else if (CKR == 4)
+    {
+        switch(MR_RL_field_value)
+        {
+            case 0 : {WL = 2; break;}
+            case 1 : {WL = 2; break;}
+            case 2 : {WL = 3; break;}
+            case 3 : {WL = 4; break;}
+            case 4 : {WL = 4; break;}
+            case 5 : {WL = 5; break;}
+            case 6 : {WL = 6; break;}
+            case 7 : {WL = 6; break;}
+            case 8 : {WL = 7; break;}
+            case 9 : {WL = 8; break;}
+            case 10: {WL = 9; break;}
+            case 11: {WL = 9; break;}
+            default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected MR_RL_field_value:%1x -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
+        }
+    }
+    else
+    {
+        mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected CKR:%1d under LPDDR5 \n",CKR));
+    }
+
+    mcSHOW_DBG_MSG(("[WriteLatency GET] DVFSC_DIS:BYTE_MODE_EN:%1d-MR_RL_field_value:%1x-CKR:%2d-RL:%2d\n",BYTE_MODE_EN,MR_RL_field_value,CKR,WL));
+
+    return WL;
+}
+
+//LPDDR5 write Latency Version B not implemented --TODO
+U32 Get_WL_LP5_DVFSC_EN( U8 MR_RL_field_value, U8 BYTE_MODE_EN,U8 CKR)
+{
+    U32 WL=0;
+
+    if(CKR == 2)
+    {
+        switch(MR_RL_field_value)
+        {
+            case 0 : {WL = 4; break;}
+            case 1 : {WL = 4; break;}
+            case 2 : {WL = 6; break;}
+            default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_EN: Unexpected MR_RL_field_value:%1d -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
+        }
+    }
+    else if (CKR == 4)
+    {
+        switch(MR_RL_field_value)
+        {
+            case 0 : {WL = 2; break;}
+            case 1 : {WL = 2; break;}
+            case 2 : {WL = 3; break;}
+            default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_EN:Unexpected MR_RL_field_value:%1x -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
+        }
+    }
+    else
+    {
+        mcSHOW_ERR_MSG(("ERROR: DVFSC_EN:Unexpected CKR:%1d under LPDDR5 \n",CKR));
+    }
+
+    mcSHOW_DBG_MSG(("[WriteLatency GET] DVFSC_EN: BYTE_MODE_EN:%1d-MR_RL_field_value:%1x-CKR:%2d-RL:%2d\n",BYTE_MODE_EN,MR_RL_field_value,CKR,WL));
+
+    return WL;
+}
+
+//LP5 dram initial ModeRegister setting
+U8 LP5_DRAM_INIT_RLWL_MRfield_config(U32 data_rate)
+{
+    U8 MR2_RLWL=0;
+
+    if      ((data_rate<=6400) && (data_rate > 6000)) {MR2_RLWL = 11 ;}
+    else if ((data_rate<=6400) && (data_rate > 5500)) {MR2_RLWL = 10 ;}
+    else if ((data_rate<=5500) && (data_rate > 4800)) {MR2_RLWL = 9  ;}
+    else if ((data_rate<=4800) && (data_rate > 4266)) {MR2_RLWL = 8  ;}
+    else if ((data_rate<=4266) && (data_rate > 3733)) {MR2_RLWL = 7  ;}
+    else if ((data_rate<=3700) && (data_rate > 3200)) {MR2_RLWL = 6  ;}
+    else if ((data_rate<=3200) && (data_rate > 2400)) {MR2_RLWL = 5  ;}
+    else if ((data_rate<=2400) && (data_rate > 1866)) {MR2_RLWL = 4  ;}
+    else if ((data_rate<=1866) && (data_rate > 1600)) {MR2_RLWL = 3  ;}
+    else if ((data_rate<=1600) && (data_rate >= 800)) {MR2_RLWL = 2  ;}
+    else {mcSHOW_ERR_MSG(("ERROR: Unexpected data_rate:%4d under LPDDR5 \n",data_rate));return -1;}
+
+    mcSHOW_DBG_MSG(("[ModeRegister RLWL Config] data_rate:%4d-MR2_RLWL:%1x\n",data_rate,MR2_RLWL));
+
+    return MR2_RLWL;
+}
+
+void LP5_DRAM_config(DRAMC_DVFS_GROUP_CONFIG_T *dfs_tr, LP5_DRAM_CONFIG_T *tr)
+{
+    tr->BYTE_MODE[0] = 0 ;
+    tr->BYTE_MODE[1] = 0 ;
+    tr->EX_ROW_EN[0] = 0 ;
+    tr->EX_ROW_EN[1] = 0 ;
+    tr->MR_WL        = LP5_DRAM_INIT_RLWL_MRfield_config(dfs_tr->data_rate);
+    tr->MR_RL        = tr->MR_WL;
+    tr->BL           = 2;
+	tr->CK_Mode      = (dfs_tr->data_rate>=2133)?0:1;   //0:diff 1:SE
+    tr->RPST         = 0;
+    tr->RD_PRE       = 0;
+    tr->WR_PRE       = 1;
+    tr->WR_PST       = (dfs_tr->data_rate>=3200)?1:0 ;
+#if SA_CONFIG_EN
+        tr->DBI_WR       = 0;
+        #if LP5_DDR4266_RDBI_WORKAROUND
+    	tr->DBI_RD       = (dfs_tr->data_rate>=3733)?1:0 ;
+        #else
+        tr->DBI_RD       = 0;
+    #endif
+#else
+    tr->DBI_WR       = (dfs_tr->data_rate>=3733)?1:0 ;
+    tr->DBI_RD       = (dfs_tr->data_rate>=3733)?1:0 ;
+#endif
+    tr->DMI          = 1;
+    tr->OTF          = 1;
+    tr->WCK_PST      = (dfs_tr->data_rate>=3733)?1:0 ;
+    tr->RDQS_PST     = 0;
+    tr->CA_ODT       = 0;
+    tr->DQ_ODT       = (dfs_tr->data_rate>=3733)?3:0 ;
+    tr->CKR          = (dfs_tr->CKR==4)?0:1;
+    tr->WCK_ON       =  0; //TODO
+#if SA_CONFIG_EN
+        #if WCK_LEVELING_FM_WORKAROUND
+        tr->WCK_FM       = 0;
+        #else
+        tr->WCK_FM       = (dfs_tr->data_rate>=2133)?1:0;
+        #endif
+#else
+    tr->WCK_FM       = (dfs_tr->data_rate>=2133)?1:0;
+#endif
+    tr->WCK_ODT      = (dfs_tr->CKR==4)?3:0;
+    tr->DVFSQ        = (dfs_tr->data_rate>=3733)?0:1;
+    tr->DVFSC        = (dfs_tr->data_rate>=2133)?0:1;
+    tr->RDQSmode[0]  = EN_both;//TODO  --RK0 have to EN_t if SE enable
+    tr->RDQSmode[1]  = EN_both;//TODO  --RK1 have to EN_c if SE enable
+    tr->WCKmode[0]   = (dfs_tr->data_rate>=1600)?0:1;
+    tr->WCKmode[1]   = (dfs_tr->data_rate>=1600)?0:2;
+    tr->RECC         = 0;//TODO
+    tr->WECC         = 0;//TODO
+    tr->BankMode     = (dfs_tr->data_rate>=3733)?BG4BK4:BK16;
+    tr->WORK_FSP     = 0;//TODO
+
+    switch (dfs_tr->DQSIEN_MODE)
+    {
+        case 1: {tr->RDQS_PRE = 0;break;}
+        case 2: {tr->RDQS_PRE = 1;break;}
+        case 3: {tr->RDQS_PRE = 3;break;}
+        case 6: {tr->RDQS_PRE = 1;break;}
+        case 7: {tr->RDQS_PRE = 3;break;}
+        default : {mcSHOW_ERR_MSG(("ERROR: Unexpected DQSIEN_MODE :%d \n",dfs_tr->DQSIEN_MODE)); while(1);};
+    }
+
+    mcSHOW_DBG_MSG2(("=================================== \n"));
+    mcSHOW_DBG_MSG2(("LPDDR5 DRAM CONFIGURATION\n"     ));
+    mcSHOW_DBG_MSG2(("=================================== \n"));
+    mcSHOW_DBG_MSG2(("MR_WL         = 0x%1x\n",tr->MR_WL       ));
+    mcSHOW_DBG_MSG2(("MR_RL         = 0x%1x\n",tr->MR_RL       ));
+    mcSHOW_DBG_MSG2(("BL            = 0x%1x\n",tr->BL          ));
+    mcSHOW_DBG_MSG2(("CK_Mode       = 0x%1x\n",tr->CK_Mode     ));
+    mcSHOW_DBG_MSG2(("RPST          = 0x%1x\n",tr->RPST        ));
+    mcSHOW_DBG_MSG2(("RD_PRE        = 0x%1x\n",tr->RD_PRE      ));
+    mcSHOW_DBG_MSG2(("RDQS_PRE      = 0x%1x\n",tr->RDQS_PRE    ));
+    mcSHOW_DBG_MSG2(("WR_PRE        = 0x%1x\n",tr->WR_PRE      ));
+    mcSHOW_DBG_MSG2(("WR_PST        = 0x%1x\n",tr->WR_PST      ));
+    mcSHOW_DBG_MSG2(("DBI_WR        = 0x%1x\n",tr->DBI_WR      ));
+    mcSHOW_DBG_MSG2(("DBI_RD        = 0x%1x\n",tr->DBI_RD      ));
+    mcSHOW_DBG_MSG2(("DMI           = 0x%1x\n",tr->DMI         ));
+    mcSHOW_DBG_MSG2(("OTF           = 0x%1x\n",tr->OTF         ));
+    mcSHOW_DBG_MSG2(("WCK_PST       = 0x%1x\n",tr->WCK_PST     ));
+    mcSHOW_DBG_MSG2(("RDQS_PST      = 0x%1x\n",tr->RDQS_PST    ));
+    mcSHOW_DBG_MSG2(("CA_ODT        = 0x%1x\n",tr->CA_ODT      ));
+    mcSHOW_DBG_MSG2(("DQ_ODT        = 0x%1x\n",tr->DQ_ODT      ));
+    mcSHOW_DBG_MSG2(("CKR           = 0x%1x\n",tr->CKR         ));
+    mcSHOW_DBG_MSG2(("WCK_ON        = 0x%1x\n",tr->WCK_ON      ));
+    mcSHOW_DBG_MSG2(("WCK_FM        = 0x%1x\n",tr->WCK_FM      ));
+    mcSHOW_DBG_MSG2(("WCK_ODT       = 0x%1x\n",tr->WCK_ODT     ));
+    mcSHOW_DBG_MSG2(("DVFSQ         = 0x%1x\n",tr->DVFSQ       ));
+    mcSHOW_DBG_MSG2(("DVFSC         = 0x%1x\n",tr->DVFSC       ));
+    mcSHOW_DBG_MSG2(("RDQSmode[0]   = 0x%1x\n",tr->RDQSmode[0] ));
+    mcSHOW_DBG_MSG2(("RDQSmode[1]   = 0x%1x\n",tr->RDQSmode[1] ));
+    mcSHOW_DBG_MSG2(("WCKmode[0]    = 0x%1x\n",tr->WCKmode[0]  ));
+    mcSHOW_DBG_MSG2(("WCKmode[1]    = 0x%1x\n",tr->WCKmode[1]  ));
+    mcSHOW_DBG_MSG2(("RECC          = 0x%1x\n",tr->RECC        ));
+    mcSHOW_DBG_MSG2(("WECC          = 0x%1x\n",tr->WECC        ));
+    mcSHOW_DBG_MSG2(("BankMode      = 0x%1x\n",tr->BankMode    ));
+    mcSHOW_DBG_MSG2(("WORK_FSP      = 0x%1x\n",tr->WORK_FSP    ));
+    mcSHOW_DBG_MSG2(("=================================== \n"));
+}
+#endif
diff --git a/src/vendorcode/mediatek/mt8195/dramc/Hal_io.c b/src/vendorcode/mediatek/mt8195/dramc/Hal_io.c
new file mode 100644
index 000000000000..32b57a92a440
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/Hal_io.c
@@ -0,0 +1,619 @@
+/** @file hal_io.cpp
+ *  hal_io.cpp provides functions of register access
+ */
+
+#include "x_hal_io.h"
+#include "dramc_common.h"
+#include "dramc_int_global.h"
+
+#if __ETT__
+#include <barriers.h>
+#endif
+
+#ifdef DUMP_INIT_RG_LOG_TO_DE
+    U8  gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 0;
+#endif
+
+#if FOR_DV_SIMULATION_USED
+U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 u4reg_addr)
+{
+    U32 u4Offset = u4reg_addr & 0xffff;
+    U32 u4RegType = ((u4reg_addr - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0xf;
+    U32 u4BaseAddr = 0;
+
+    if (u4reg_addr < Channel_A_DRAMC_NAO_BASE_VIRTUAL ||
+        u4reg_addr >= MAX_BASE_VIRTUAL)
+    {
+        return u4reg_addr;
+    }
+
+    if (u4RegType >= 2 && u4RegType <= 3)// ChA/B Dramc AO Register
+    {
+        if (u4Offset < DRAMC_REG_AO_SHUFFLE0_BASE_ADDR || u4Offset > DRAMC_REG_AO_SHUFFLE0_END_ADDR)
+            eShu = 0;
+    }
+    else if (u4RegType >= 6 && u4RegType <= 7)// ChA/B Dramc AO Register
+    {
+        if (u4Offset < DDRPHY_AO_SHUFFLE0_BASE_ADDR || u4Offset > DDRPHY_AO_SHUFFLE0_END_ADDR)
+            eShu = 0;
+    }
+
+    if (eRank == RANK_1)
+    {
+        if (u4RegType >= 2 && u4RegType <= 3)// ChA/B Dramc AO Register
+        {
+            if (u4Offset >= DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR &&
+                u4Offset <= DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR)
+            { 
+                u4Offset += DRAMC_REG_AO_RANK_OFFSET;
+            }
+            else if (u4Offset >= DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR &&
+                     u4Offset <= DRAMC_REG_AO_RANK0_W_SHUFFLE0_END_ADDR)
+            {                
+                u4Offset += DRAMC_REG_AO_RANK_OFFSET;
+            }
+        }
+        else if (u4RegType >= 6 && u4RegType <= 7)// PhyA/B AO Register
+        {
+            // 0x60~0xE0
+            if (u4Offset >= DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR &&
+                u4Offset <= DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR)
+            {
+                u4Offset += DDRPHY_AO_RANK_OFFSET;
+            }
+            // 0x1E0~0x260
+            else if (u4Offset >= DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR &&
+                     u4Offset <= DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR)
+            {
+                u4Offset += DDRPHY_AO_RANK_OFFSET;
+            }
+            // 0x360~0x3E0
+            else if (u4Offset >= DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR &&
+                     u4Offset <= DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR)
+            {
+                u4Offset += DDRPHY_AO_RANK_OFFSET;
+            }
+            // 0x760~0x7E0
+            else if (u4Offset >= DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR &&
+                     u4Offset <= DDRPHY_AO_RANK0_B0_SHU0_END_ADDR)
+            {
+                u4Offset += DDRPHY_AO_RANK_OFFSET;
+            }
+            // 0x8E0~0x960
+            else if (u4Offset >= DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR &&
+                     u4Offset <= DDRPHY_AO_RANK0_B1_SHU0_END_ADDR)
+            {
+                u4Offset += DDRPHY_AO_RANK_OFFSET;
+            }
+            // 0xA60~0xAE0
+            else if (u4Offset >= DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR &&
+                     u4Offset <= DDRPHY_AO_RANK0_CA_SHU0_END_ADDR)
+            {
+                u4Offset += DDRPHY_AO_RANK_OFFSET;
+            }
+            // 0xBE0~0xC60
+            else if (u4Offset >= DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR &&
+                     u4Offset <= DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR)
+            {
+                u4Offset += DDRPHY_AO_RANK_OFFSET;
+            }             
+        }        
+        else if (u4RegType <= 1)// ChA/B Dramc NAO Register
+        {
+            if (u4Offset >= (DRAMC_REG_RK0_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS) &&
+                u4Offset < (DRAMC_REG_RK1_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS))
+            {
+                u4Offset += 0x100;
+            }
+            else if (u4Offset >= DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR &&
+                     u4Offset <= DRAMC_REG_NAO_RANK0_ROW_OFFSET_END_ADDR)
+            {        
+                u4Offset += DRAMC_REG_NAO_RANK_OFFSET;
+            }
+        }
+        else if (u4RegType >= 4 && u4RegType <= 5) // PhyA/B NAO Register
+        {
+            // PhyA/B NAO Register
+            if (u4Offset >= DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START &&
+                u4Offset < DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END)
+            {
+                u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET;
+            }
+            else if (u4Offset >= DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START &&
+                u4Offset < DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_END)
+            {
+                u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET;
+            }
+            else if (u4Offset >= DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START &&
+                u4Offset < DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_END)
+            {
+                u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET;
+            }
+            else if (u4Offset >= DDRPHY_NAO_RANK0_GATING_STATUS_START &&
+                u4Offset < DDRPHY_NAO_RANK0_GATING_STATUS_END)
+            {
+                u4Offset += DDRPHY_NAO_GATING_STATUS_RK_OFFSET;
+            }
+        }
+    }
+
+    switch (u4RegType)
+    {
+        case 0:
+             u4BaseAddr = Channel_A_DRAMC_NAO_BASE_ADDRESS;
+             break;
+         case 1:
+             u4BaseAddr = Channel_B_DRAMC_NAO_BASE_ADDRESS;
+             break;
+         case 2:
+             u4BaseAddr = Channel_A_DRAMC_AO_BASE_ADDRESS + (eShu * DRAMC_REG_AO_SHU_OFFSET);
+             break;
+         case 3:
+             u4BaseAddr = Channel_B_DRAMC_AO_BASE_ADDRESS + (eShu * DRAMC_REG_AO_SHU_OFFSET);
+             break;
+         case 4:
+               u4BaseAddr = Channel_A_DDRPHY_NAO_BASE_ADDRESS;
+               break;
+         case 5:
+               u4BaseAddr = Channel_B_DDRPHY_NAO_BASE_ADDRESS;
+               break;
+         case 6:
+               u4BaseAddr = Channel_A_DDRPHY_AO_BASE_ADDRESS + (eShu * DDRPHY_AO_SHU_OFFSET);
+               break;
+         case 7:
+               u4BaseAddr = Channel_B_DDRPHY_AO_BASE_ADDRESS + (eShu * DDRPHY_AO_SHU_OFFSET);
+               break;
+         case 8:
+               u4BaseAddr = Channel_A_DDRPHY_DPM_BASE_ADDRESS;
+               break;
+    }
+
+    return (u4BaseAddr + u4Offset);
+}
+#else
+static U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 u4reg_addr)
+{
+    U32 u4Offset = u4reg_addr & 0xffff;
+    U32 u4RegType = ((u4reg_addr - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0x1f;
+    U32 u4BaseAddr = 0;
+
+    if (u4reg_addr < Channel_A_DRAMC_NAO_BASE_VIRTUAL ||
+        u4reg_addr >= MAX_BASE_VIRTUAL)
+    {
+        return u4reg_addr;
+    }
+
+    if (u4RegType >= 4 && u4RegType <= 7)// ChA/B Dramc AO Register
+    {
+        if (u4Offset < DRAMC_REG_AO_SHUFFLE0_BASE_ADDR || u4Offset > DRAMC_REG_AO_SHUFFLE0_END_ADDR)
+            eShu = 0;
+    }
+    else if (u4RegType >= 12 && u4RegType <= 15)// ChA/B Phy AO Register
+    {
+        if (u4Offset < DDRPHY_AO_SHUFFLE0_BASE_ADDR || u4Offset > DDRPHY_AO_SHUFFLE0_END_ADDR)
+            eShu = 0;
+    }
+
+    if (eRank == RANK_1)
+    {
+        if (u4RegType >= 4 && u4RegType <= 7)// ChA/B Dramc AO Register
+        {
+            if (u4Offset >= DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR &&
+                u4Offset <= DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR)
+            { 
+                u4Offset += DRAMC_REG_AO_RANK_OFFSET;
+            }
+            else if (u4Offset >= DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR &&
+                     u4Offset <= DRAMC_REG_AO_RANK0_W_SHUFFLE0_END_ADDR)
+            {                
+                u4Offset += DRAMC_REG_AO_RANK_OFFSET;
+            }
+        }
+        else if (u4RegType >= 12 && u4RegType <= 15)// PhyA/B AO Register
+        {
+            // 0x60~0xE0
+            if (u4Offset >= DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR &&
+                u4Offset <= DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR)
+            {
+                u4Offset += DDRPHY_AO_RANK_OFFSET;
+            }
+            // 0x1E0~0x260
+            else if (u4Offset >= DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR &&
+                     u4Offset <= DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR)
+            {
+                u4Offset += DDRPHY_AO_RANK_OFFSET;
+            }
+            // 0x360~0x3E0
+            else if (u4Offset >= DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR &&
+                     u4Offset <= DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR)
+            {
+                u4Offset += DDRPHY_AO_RANK_OFFSET;
+            }
+            // 0x760~0x7E0
+            else if (u4Offset >= DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR &&
+                     u4Offset <= DDRPHY_AO_RANK0_B0_SHU0_END_ADDR)
+            {
+                u4Offset += DDRPHY_AO_RANK_OFFSET;
+            }
+            // 0x8E0~0x960
+            else if (u4Offset >= DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR &&
+                     u4Offset <= DDRPHY_AO_RANK0_B1_SHU0_END_ADDR)
+            {
+                u4Offset += DDRPHY_AO_RANK_OFFSET;
+            }
+            // 0xA60~0xAE0
+            else if (u4Offset >= DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR &&
+                     u4Offset <= DDRPHY_AO_RANK0_CA_SHU0_END_ADDR)
+            {
+                u4Offset += DDRPHY_AO_RANK_OFFSET;
+            }
+            // 0xBE0~0xC60
+            else if (u4Offset >= DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR &&
+                     u4Offset <= DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR)
+            {
+                u4Offset += DDRPHY_AO_RANK_OFFSET;
+            }             
+        }        
+        else if (u4RegType <= 3)// ChA/B Dramc NAO Register
+        {
+            if (u4Offset >= (DRAMC_REG_RK0_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS) &&
+                u4Offset < (DRAMC_REG_RK1_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS))
+            {
+                u4Offset += 0x100;
+            }
+        }
+        else if (u4RegType >= 8 && u4RegType <= 11) // PhyA/B NAO Register
+        {
+            // PhyA/B NAO Register
+            if (u4Offset >= DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START &&
+                u4Offset < DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END)
+            {
+                u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET;
+            }
+            else if (u4Offset >= DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START &&
+                u4Offset < DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_END)
+            {
+                u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET;
+            }
+            else if (u4Offset >= DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START &&
+                u4Offset < DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_END)
+            {
+                u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET;
+            }
+            else if (u4Offset >= DDRPHY_NAO_RANK0_GATING_STATUS_START &&
+                u4Offset < DDRPHY_NAO_RANK0_GATING_STATUS_END)
+            {
+                u4Offset += DDRPHY_NAO_GATING_STATUS_RK_OFFSET;
+            }
+        }
+    }
+
+    switch (u4RegType)
+    {
+         case 0:
+             u4BaseAddr = Channel_A_DRAMC_NAO_BASE_ADDRESS;
+             break;
+         case 1:
+             u4BaseAddr = Channel_B_DRAMC_NAO_BASE_ADDRESS;
+             break;
+         case 2:
+             u4BaseAddr = Channel_C_DRAMC_NAO_BASE_ADDRESS;
+             break;
+         case 3:
+             u4BaseAddr = Channel_D_DRAMC_NAO_BASE_ADDRESS;
+             break;
+         case 4:
+             u4BaseAddr = Channel_A_DRAMC_AO_BASE_ADDRESS + (eShu * DRAMC_REG_AO_SHU_OFFSET);
+             break;
+         case 5:
+             u4BaseAddr = Channel_B_DRAMC_AO_BASE_ADDRESS + (eShu * DRAMC_REG_AO_SHU_OFFSET);
+             break;
+         case 6:
+             u4BaseAddr = Channel_C_DRAMC_AO_BASE_ADDRESS + (eShu * DRAMC_REG_AO_SHU_OFFSET);
+             break;
+         case 7:
+             u4BaseAddr = Channel_D_DRAMC_AO_BASE_ADDRESS + (eShu * DRAMC_REG_AO_SHU_OFFSET);
+             break;
+         case 8:
+               u4BaseAddr = Channel_A_DDRPHY_NAO_BASE_ADDRESS;
+               break;
+         case 9:
+               u4BaseAddr = Channel_B_DDRPHY_NAO_BASE_ADDRESS;
+               break;
+         case 10:
+               u4BaseAddr = Channel_C_DDRPHY_NAO_BASE_ADDRESS;
+               break;
+         case 11:
+               u4BaseAddr = Channel_D_DDRPHY_NAO_BASE_ADDRESS;
+               break;
+         case 12:
+               u4BaseAddr = Channel_A_DDRPHY_AO_BASE_ADDRESS + (eShu * DDRPHY_AO_SHU_OFFSET);
+               break;
+         case 13:
+               u4BaseAddr = Channel_B_DDRPHY_AO_BASE_ADDRESS + (eShu * DDRPHY_AO_SHU_OFFSET);
+               break;
+         case 14:
+               u4BaseAddr = Channel_C_DDRPHY_AO_BASE_ADDRESS + (eShu * DDRPHY_AO_SHU_OFFSET);
+               break;
+         case 15:
+               u4BaseAddr = Channel_D_DDRPHY_AO_BASE_ADDRESS + (eShu * DDRPHY_AO_SHU_OFFSET);
+               break;
+         case 16:
+               u4BaseAddr = Channel_A_DDRPHY_DPM_BASE_ADDRESS;
+               break;
+         case 17:
+               u4BaseAddr = Channel_B_DDRPHY_DPM_BASE_ADDRESS;
+               break;
+    }
+
+    return (u4BaseAddr + u4Offset);
+}
+#endif
+//[FOR_CHROMEOS]
+//inline U32 _u4Dram_Register_Read(U32 u4reg_addr)
+inline U32 _u4Dram_Register_Read(U64 u4reg_addr)
+{
+    U32 u4reg_value;
+#if (!__ETT__) && (FOR_DV_SIMULATION_USED == 0)
+    dsb();
+#endif
+
+#if QT_GUI_Tool
+    ucDramRegRead_1(u4reg_addr, &u4reg_value);
+#elif (FOR_DV_SIMULATION_USED == 1)   //DV
+    u4reg_value = register_read_c(u4reg_addr);
+#else // real chip
+    u4reg_value = *((volatile unsigned int *)u4reg_addr);
+#endif
+
+    return u4reg_value;
+}
+
+//-------------------------------------------------------------------------
+/** ucDram_Register_Read
+ *  DRAM register read (32-bit).
+ *  @param  u4reg_addr    register address in 32-bit.
+ *  @param  pu4reg_value  Pointer of register read value.
+ *  @retval 0: OK, 1: FAIL
+ */
+//-------------------------------------------------------------------------
+// This function need to be porting by BU requirement
+U32 u4Dram_Register_Read(DRAMC_CTX_T *p, U32 u4reg_addr)
+{
+	U32 u4RegType = ((u4reg_addr - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0xf;
+
+#if (fcFOR_CHIP_ID == fc8195)
+	//ignore CH-B
+    if ((p->support_channel_num == CHANNEL_SINGLE) && (u4reg_addr >= Channel_A_DRAMC_NAO_BASE_VIRTUAL && u4reg_addr < MAX_BASE_VIRTUAL))
+	{
+		if(u4RegType%2!=0)
+        {
+			return 0;
+	}
+    }
+#endif
+
+    u4reg_addr = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, u4reg_addr);
+
+    return _u4Dram_Register_Read(u4reg_addr);
+}
+
+
+//-------------------------------------------------------------------------
+/** ucDram_Register_Write
+ *  DRAM register write (32-bit).
+ *  @param  u4reg_addr    register address in 32-bit.
+ *  @param  u4reg_value   register write value.
+ *  @retval 0: OK, 1: FAIL
+ */
+//-------------------------------------------------------------------------
+
+#if REG_ACCESS_NAO_DGB
+#if (fcFOR_CHIP_ID == fcCervino)
+U8 Check_RG_Not_AO(U32 u4reg_addr)
+{
+    U8 RegNotAO = 0;
+    if ((u4reg_addr >= DRAMC_AO_BASE_ADDRESS) && (u4reg_addr <= DRAMC_REG_SHU4_DQSG_RETRY))
+    {
+    }
+    else if ((u4reg_addr >= DRAMC_AO_BASE_ADDRESS + SHIFT_TO_CHB_ADDR) && (u4reg_addr <= DRAMC_REG_SHU4_DQSG_RETRY + SHIFT_TO_CHB_ADDR))
+    {
+    }
+    else if ((u4reg_addr >= DDRPHY_AO_BASE_ADDR) && (u4reg_addr <= DDRPHY_RFU_0X1FCC))
+    {
+    }
+    else if ((u4reg_addr >= DDRPHY_AO_BASE_ADDR + SHIFT_TO_CHB_ADDR) && (u4reg_addr <= DDRPHY_RFU_0X1FCC + SHIFT_TO_CHB_ADDR))
+    {
+    }
+    else
+    {
+        RegNotAO = 1;
+    }
+    return RegNotAO;
+}
+#endif
+#endif
+//[FOR_CHROMEOS]
+//inline void _ucDram_Register_Write(U32 u4reg_addr, U32 u4reg_value)
+inline void _ucDram_Register_Write(U64 u4reg_addr, U32 u4reg_value)
+{
+#if QT_GUI_Tool
+     ucDramRegWrite_1(u4reg_addr, u4reg_value);
+#elif (FOR_DV_SIMULATION_USED == 1) //DV
+    register_write_c(u4reg_addr, u4reg_value);
+#else // real chip
+    (*(volatile unsigned int *)u4reg_addr) = u4reg_value;//real chip
+    #if !defined(__DPM__)
+    dsb();
+    #endif
+#endif
+
+#ifdef DUMP_INIT_RG_LOG_TO_DE
+    if (gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag == 1)
+    {
+        mcSHOW_DUMP_INIT_RG_MSG(("*((UINT32P)(0x%x)) = 0x%x;\n",u4reg_addr,u4reg_value));
+        gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 0;
+        mcDELAY_MS(1); // to receive log for log 
+        gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 1;
+    }
+#endif 
+
+#if REG_ACCESS_PORTING_DGB
+    if (RegLogEnable)
+    {
+        mcSHOW_DBG_MSG(("\n[REG_ACCESS_PORTING_DBG]   ucDramC_Register_Write Reg(0x%X) = 0x%X\n", u4reg_addr, u4reg_value));
+    }
+#endif
+}
+
+//This function need to be porting by BU requirement
+void ucDram_Register_Write(DRAMC_CTX_T *p, U32 u4reg_addr, U32 u4reg_value)
+{
+	U32 u4RegType = ((u4reg_addr - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0xf;
+
+#if (fcFOR_CHIP_ID == fc8195)
+    //ignore CH-B
+    if ((p->support_channel_num == CHANNEL_SINGLE) && (u4reg_addr >= Channel_A_DRAMC_NAO_BASE_VIRTUAL && u4reg_addr < MAX_BASE_VIRTUAL))
+	{
+		if(u4RegType%2!=0)
+        {
+			return;
+	}
+    }
+#endif
+
+#if __ETT__
+    //CheckDramcWBR(u4reg_addr);
+#endif
+
+	//mcSHOW_DBG_MSG(("\n[REG_ACCESS_PORTING_DBG]   ucDramC_Register_Write Reg(0x%X) = 0x%X\n", u4reg_addr, u4reg_value));
+    u4reg_addr = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, u4reg_addr);
+
+	_ucDram_Register_Write(u4reg_addr, u4reg_value);
+}
+
+void vIO32Write4BMsk2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32)
+{
+    U32 u4Val;
+	U32 u4RegType = ((reg32 - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0xf;
+
+	//ignore CH-B
+    #if (fcFOR_CHIP_ID == fc8195)
+    if ((p->support_channel_num == CHANNEL_SINGLE) && (reg32 >= Channel_A_DRAMC_NAO_BASE_VIRTUAL && reg32 <= MAX_BASE_VIRTUAL))
+	{
+		if(u4RegType%2!=0)
+			return;
+	}
+    #endif
+
+    reg32 = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, reg32);
+
+    val32 &= msk32;
+
+    u4Val = _u4Dram_Register_Read(reg32);
+    u4Val = ((u4Val & ~msk32) | val32);
+    _ucDram_Register_Write(reg32, u4Val);
+}
+
+
+void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32)
+{
+    U8 ii, u1AllCount;
+    U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM));
+    U8 u1BCSupport = TRUE;
+
+    reg32 &= 0xffff;     // remove channel information
+
+    u1AllCount = p->support_channel_num; // for all dramC and PHY
+
+    if (u4RegType >= Channel_A_DDRPHY_DPM_BASE_VIRTUAL)//DPM
+    {
+        reg32 += Channel_A_DDRPHY_DPM_BASE_VIRTUAL;
+        if (u1AllCount > 1)
+            u1AllCount >>= 1;
+        u1BCSupport = FALSE;
+    }
+    else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL)// PHY AO
+    {
+        reg32 += Channel_A_DDRPHY_AO_BASE_VIRTUAL;
+    }
+    else if (u4RegType >= Channel_A_DDRPHY_NAO_BASE_VIRTUAL)// PHY NAO
+    {
+        reg32 += Channel_A_DDRPHY_NAO_BASE_VIRTUAL;
+    }
+    else if (u4RegType >= Channel_A_DRAMC_AO_BASE_VIRTUAL)// DramC AO
+    {
+        reg32 += Channel_A_DRAMC_AO_BASE_VIRTUAL;
+    }
+    else // DramC NAO
+    {
+        reg32 += Channel_A_DRAMC_NAO_BASE_VIRTUAL;
+    }
+
+#if __ETT__
+    if (u1BCSupport && GetDramcBroadcast()==DRAMC_BROADCAST_ON)
+    {
+        mcSHOW_ERR_MSG(("Error! virtual address 0x%x don't have to use write_all when Dramc WBR is on\n", reg32));
+        while (1);
+    }
+#endif
+
+
+    for (ii = 0; ii < u1AllCount; ii++)
+    {
+        vIO32Write4B(reg32 + ((U32)ii << POS_BANK_NUM), val32);
+    }
+}
+
+void vIO32Write4BMsk_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32)
+{
+    U32 u4Val, u4RegTmp;
+    U8 ii, u1AllCount;
+    U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM));
+    U8 u1BCSupport = TRUE;
+
+    reg32 &= 0xffff;     // remove channel information
+
+    u1AllCount = p->support_channel_num; // for all dramC and PHY
+
+    if (u4RegType >= Channel_A_DDRPHY_DPM_BASE_VIRTUAL)//DPM
+    {
+        reg32 += Channel_A_DDRPHY_DPM_BASE_VIRTUAL;
+        if (u1AllCount > 1)
+            u1AllCount >>= 1;
+        u1BCSupport = FALSE;
+    }
+    else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL)// PHY AO
+    {
+        reg32 += Channel_A_DDRPHY_AO_BASE_VIRTUAL;
+    }
+    else if (u4RegType >= Channel_A_DDRPHY_NAO_BASE_VIRTUAL)// PHY NAO
+    {
+        reg32 += Channel_A_DDRPHY_NAO_BASE_VIRTUAL;
+    }
+    else if (u4RegType >= Channel_A_DRAMC_AO_BASE_VIRTUAL)// DramC AO
+    {
+        reg32 += Channel_A_DRAMC_AO_BASE_VIRTUAL;
+    }
+    else // DramC NAO
+    {
+        reg32 += Channel_A_DRAMC_NAO_BASE_VIRTUAL;
+    }
+
+#if __ETT__
+    if (u1BCSupport && GetDramcBroadcast()==DRAMC_BROADCAST_ON)
+    {
+        mcSHOW_ERR_MSG(("Error! virtual address 0x%x don't have to use write_all when Dramc WBR is on\n", reg32));
+        while (1);
+    }
+#endif
+
+    for (ii = 0; ii < u1AllCount; ii++)
+    {
+        u4RegTmp = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, reg32 + ((U32)ii << POS_BANK_NUM));
+
+        u4Val = _u4Dram_Register_Read(u4RegTmp);
+        u4Val = ((u4Val & ~msk32) | val32);
+        _ucDram_Register_Write(u4RegTmp, u4Val);
+    }
+}
diff --git a/src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c b/src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c
new file mode 100644
index 000000000000..bc42923aa792
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c
@@ -0,0 +1,187 @@
+#include "dramc_dv_init.h"
+
+void CKE_FIX_ON(DRAMC_CTX_T *p, U8 EN, U8 rank)
+{
+  switch(rank)
+  {
+    case 0 : vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), P_Fld(EN, CKECTRL_CKEFIXON));  break;
+    case 1 : vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), P_Fld(EN, CKECTRL_CKE1FIXON)); break;
+    default: mcSHOW_ERR_MSG(("ERROR: CKE FIX ON error. Unexpected Rank  \n"));
+  }
+}
+//[SV] task LP4_MRS(bit [7:0] reg_addr, bit[7:0] reg_op, bit[1:0] rank);
+static void LP4_MRS(DRAMC_CTX_T *p, U16 reg_addr, U8 reg_op, U8 rank)
+{
+    U8 temp_MRS_RESPONSE  ;
+
+    mcSHOW_DBG_MSG6(("[LP4_DRAM_INIT_MRS] RK:%1d-MA:%2d-OP:0x%2x @Channle:%1d\n",rank,reg_addr,reg_op,vGetPHY2ChannelMapping(p)));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), P_Fld(rank , SWCMD_CTRL0_MRSRK       ) \
+                                                            | P_Fld(reg_addr, SWCMD_CTRL0_MRSMA    ) \
+                                                            | P_Fld(reg_op  , SWCMD_CTRL0_MRSOP    ));
+
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), P_Fld(1, SWCMD_EN_MRWEN));
+
+    temp_MRS_RESPONSE = 0 ;
+    do
+    {
+        temp_MRS_RESPONSE = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRW_RESPONSE) ;
+    } while ( temp_MRS_RESPONSE != 1 );
+    
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), P_Fld(0, SWCMD_EN_MRWEN));
+}
+
+
+static void LP4_FSP_WR_or_OP (DRAMC_CTX_T *p, U8 FSP_WR, U8 FSP_OP, U8 rank)
+{
+	U8 MR13 = 0;
+    MR13 = ((FSP_OP & 1) << 7) | ((FSP_WR & 1) << 6) /*| ((LP4_DMI & 1) << 5)*/ | (1 << 4)/*[RRO] for MR4 refresh rate*/;
+    LP4_MRS(p, 13, MR13, rank);
+}
+
+//==================================
+//uesage(constraint): DBI = 1 for FSPOP=1   if DBI=0 then FSP_OP =0
+//==================================
+static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 rank)
+{
+    U8 MR1;
+    U8 MR2;
+    U8 MR3;
+    U8 MR51;
+    U8 MR11;
+    U8 MR12;
+    U8 MR14;
+
+    //default value for LP4 DRAM CONFIG
+    U8 nWR    =5; 
+    U8 WR_LEV =0; 
+    U8 PDDS   =5; 
+    U8 PPRP   =0; 
+    U8 PU_CAL =0; 
+    U8 WLS    =0; 
+    
+    //Notice: DBI default = 0
+
+    //field & configuration adaption
+    MR1 = ((tr->RPST    & 1)<<7) | ((nWR         & 7)<<4) | ((tr->RD_PRE  & 1)<<3) | ((tr->WR_PRE & 1)<<2) | ((tr->BL & 3)<<0);
+    MR2 = ((WR_LEV      & 1)<<7) | ((WLS         & 1)<<6) | ((tr->MR_WL   & 7)<<3) | ((tr->MR_RL  & 7)<<0); 
+    MR3 = ((tr->DBI_WR  & 1)<<7) | ((tr->DBI_RD  & 1)<<6) | ((   PDDS     & 7)<<3) | ((PPRP       & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0);
+    MR51= ((tr->LP4Y_EN & 1)<<3) | ((tr->LP4Y_EN & 1)<<2) | ((tr->LP4Y_EN & 1)<<1);
+    if(tr->WORK_FSP == 0)
+    {
+        MR11 = 0x0;
+        MR14 = 0x5d;
+    }
+    else
+    {
+        MR11 = 0x04;
+        MR14 = 0x18;
+    }
+    MR12= 0x5d;
+    #if FSP1_CLKCA_TERM
+    if(p->dram_fsp == FSP_1)
+        MR12 = 0x20;
+    #endif
+    //temp workaround for global variable of MR
+    u1MR02Value[tr->WORK_FSP] = MR2;
+    u1MR03Value[tr->WORK_FSP] = MR3;
+    #if ENABLE_LP4_ZQ_CAL
+    DramcZQCalibration(p, rank); //ZQ calobration should be done before CBT calibration by switching to low frequency
+    #endif
+
+    mcSHOW_DBG_MSG6(("[LP4_DRAM_INIT] Channle:%1d-Rank:%1d >>>>>>\n",vGetPHY2ChannelMapping(p),rank));
+
+    //first FSP
+    if(tr->WORK_FSP == 0) {LP4_FSP_WR_or_OP(p, 0, 1, rank);}
+    else                  {LP4_FSP_WR_or_OP(p, 1, 0, rank);}
+
+    mcDELAY_XNS(15); //TCKFSPE
+
+    LP4_MRS(p,  1, MR1 , rank);
+    LP4_MRS(p,  2, MR2 , rank);
+    LP4_MRS(p,  3, MR3 , rank);
+    LP4_MRS(p,  11, MR11 , rank);
+    LP4_MRS(p,  12, MR12 , rank);
+    LP4_MRS(p,  14, MR14 , rank);
+    if(tr->LP4Y_EN == 1)  { LP4_MRS(p, 51, MR51, rank); }
+    
+    mcDELAY_XNS(15); //TCKFSPX
+
+    //2nd FSP
+    if(tr->WORK_FSP == 0) {LP4_FSP_WR_or_OP(p, 1, 0, rank);}
+    else                  {LP4_FSP_WR_or_OP(p, 0, 1, rank);}
+
+    mcDELAY_XNS(15); //TCKFSPE
+
+    LP4_MRS(p,  1, MR1 , rank);
+    LP4_MRS(p,  2, MR2 , rank);
+    //reverse the DBI 
+    MR3 = ((!tr->DBI_WR  & 1)<<7) | ((!tr->DBI_RD  & 1)<<6) | ((   PDDS     & 7)<<3) | ((PPRP       & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0);
+    LP4_MRS(p,  3, MR3 , rank);
+    LP4_MRS(p,  11, MR11 , rank);
+    LP4_MRS(p,  12, MR12 , rank);
+    LP4_MRS(p,  14, MR14 , rank);
+
+    LP4_FSP_WR_or_OP(p, tr->WORK_FSP, tr->WORK_FSP, rank);
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7)     , P_Fld( 1       , CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y       ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7)      , P_Fld( 1       , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y    ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7)      , P_Fld( 1       , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y    ));
+
+    mcSHOW_DBG_MSG6(("[LP4_DRAM_INIT] Channle:%1d-Rank:%1d <<<<<<\n",vGetPHY2ChannelMapping(p),rank));
+}
+
+void LP4_single_end_DRAMC_post_config(DRAMC_CTX_T *p, U8 LP4Y_EN)
+{
+    mcSHOW_DBG_MSG6(("============ LP4 DIFF to SE enter ============\n"));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld( LP4Y_EN , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA ) \
+                                                              | P_Fld( LP4Y_EN       , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA  ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13) , P_Fld( LP4Y_EN , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0  ) \
+                                                              | P_Fld( LP4Y_EN       , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0   ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13) , P_Fld( LP4Y_EN , SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1  ) \
+                                                              | P_Fld( LP4Y_EN       , SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1   ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD0) , P_Fld( 0 , SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK         ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ0)  , P_Fld( 0 , SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0         ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ0)  , P_Fld( 0 , SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1         ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD7) , P_Fld( 0 , SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK         )); //@Darren, debugging for DFS stress fail
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7)  , P_Fld( LP4Y_EN , SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0         ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7)  , P_Fld( LP4Y_EN , SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1         ));
+
+#if 1//ENABLE_LP4Y_DFS // @Darren, need confirm
+    // for strong pull low and normal mode
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7)     , P_Fld( 0 , CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y       ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7)      , P_Fld( 0 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y    ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7)      , P_Fld( 0 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y    ));
+#else
+    // for weak pull low mode only
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7)     , P_Fld( 1 , CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y       ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7)      , P_Fld( 1 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y    ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7)      , P_Fld( 1 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y    ));
+#endif
+    mcSHOW_DBG_MSG6(("============ LP4 DIFF to SE exit  ============\n"));
+}
+
+void LP4_DRAM_INIT(DRAMC_CTX_T *p)
+{
+    U8 RANK;
+
+
+#if SA_CONFIG_EN && DV_SIMULATION_DFS// @Darren, temp workaround
+    DramcPowerOnSequence(p);
+#endif
+
+
+    mcDELAY_XNS(200); //tINIT3 = 2ms  for DV fastup to 200ns
+
+    for(RANK=0;RANK<2;RANK++)
+    {
+        CKE_FIX_ON(p,1,RANK);
+        mcDELAY_XNS(400); //tINIT5  fastup to 400ns
+
+        //step4 moderegister setting
+        lp4_dram_init_single_rank(p,DV_p.lp4_init,RANK);
+        CKE_FIX_ON(p,0,RANK);
+    }
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), P_Fld(0, REFCTRL0_REFDIS)); //TODO enable refresh
+}
diff --git a/src/vendorcode/mediatek/mt8195/dramc/Makefile.inc b/src/vendorcode/mediatek/mt8195/dramc/Makefile.inc
new file mode 100644
index 000000000000..8d0361853160
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/Makefile.inc
@@ -0,0 +1,22 @@
+romstage-y += emi.c
+
+romstage-y += ANA_init_config.c
+romstage-y += DIG_NONSHUF_config.c
+romstage-y += DIG_SHUF_config.c
+romstage-y += dramc_actiming.c
+romstage-y += dramc_dv_freq_related.c
+romstage-y += dramc_dvfs.c
+romstage-y += dramc_lowpower.c
+romstage-y += DRAM_config_collctioin.c
+romstage-y += dramc_pi_basic_api.c
+romstage-y += dramc_pi_calibration_api.c
+romstage-y += dramc_pi_main.c
+romstage-y += DRAMC_SUBSYS_config.c
+romstage-y += dramc_top.c
+romstage-y += dramc_tracking.c
+romstage-y += dramc_utility.c
+romstage-y += Hal_io.c
+romstage-y += LP4_dram_init.c
+romstage-y += dramc_debug.c
+
+ramstage-y += emi.c
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c
new file mode 100644
index 000000000000..1d3361ca671b
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c
@@ -0,0 +1,4997 @@
+/*----------------------------------------------------------------------------*
+ * Copyright Statement:                                                       *
+ *                                                                            *
+ *   This software/firmware and related documentation ("MediaTek Software")   *
+ * are protected under international and related jurisdictions'copyright laws *
+ * as unpublished works. The information contained herein is confidential and *
+ * proprietary to MediaTek Inc. Without the prior written permission of       *
+ * MediaTek Inc., any reproduction, modification, use or disclosure of        *
+ * MediaTek Software, and information contained herein, in whole or in part,  *
+ * shall be strictly prohibited.                                              *
+ * MediaTek Inc. Copyright (C) 2010. All rights reserved.                     *
+ *                                                                            *
+ *   BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND     *
+ * AGREES TO THE FOLLOWING:                                                   *
+ *                                                                            *
+ *   1)Any and all intellectual property rights (including without            *
+ * limitation, patent, copyright, and trade secrets) in and to this           *
+ * Software/firmware and related documentation ("MediaTek Software") shall    *
+ * remain the exclusive property of MediaTek Inc. Any and all intellectual    *
+ * property rights (including without limitation, patent, copyright, and      *
+ * trade secrets) in and to any modifications and derivatives to MediaTek     *
+ * Software, whoever made, shall also remain the exclusive property of        *
+ * MediaTek Inc.  Nothing herein shall be construed as any transfer of any    *
+ * title to any intellectual property right in MediaTek Software to Receiver. *
+ *                                                                            *
+ *   2)This MediaTek Software Receiver received from MediaTek Inc. and/or its *
+ * representatives is provided to Receiver on an "AS IS" basis only.          *
+ * MediaTek Inc. expressly disclaims all warranties, expressed or implied,    *
+ * including but not limited to any implied warranties of merchantability,    *
+ * non-infringement and fitness for a particular purpose and any warranties   *
+ * arising out of course of performance, course of dealing or usage of trade. *
+ * MediaTek Inc. does not provide any warranty whatsoever with respect to the *
+ * software of any third party which may be used by, incorporated in, or      *
+ * supplied with the MediaTek Software, and Receiver agrees to look only to   *
+ * such third parties for any warranty claim relating thereto.  Receiver      *
+ * expressly acknowledges that it is Receiver's sole responsibility to obtain *
+ * from any third party all proper licenses contained in or delivered with    *
+ * MediaTek Software.  MediaTek is not responsible for any MediaTek Software  *
+ * releases made to Receiver's specifications or to conform to a particular   *
+ * standard or open forum.                                                    *
+ *                                                                            *
+ *   3)Receiver further acknowledge that Receiver may, either presently       *
+ * and/or in the future, instruct MediaTek Inc. to assist it in the           *
+ * development and the implementation, in accordance with Receiver's designs, *
+ * of certain softwares relating to Receiver's product(s) (the "Services").   *
+ * Except as may be otherwise agreed to in writing, no warranties of any      *
+ * kind, whether express or implied, are given by MediaTek Inc. with respect  *
+ * to the Services provided, and the Services are provided on an "AS IS"      *
+ * basis. Receiver further acknowledges that the Services may contain errors  *
+ * that testing is important and it is solely responsible for fully testing   *
+ * the Services and/or derivatives thereof before they are used, sublicensed  *
+ * or distributed. Should there be any third party action brought against     *
+ * MediaTek Inc. arising out of or relating to the Services, Receiver agree   *
+ * to fully indemnify and hold MediaTek Inc. harmless.  If the parties        *
+ * mutually agree to enter into or continue a business relationship or other  *
+ * arrangement, the terms and conditions set forth herein shall remain        *
+ * effective and, unless explicitly stated otherwise, shall prevail in the    *
+ * event of a conflict in the terms in any agreements entered into between    *
+ * the parties.                                                               *
+ *                                                                            *
+ *   4)Receiver's sole and exclusive remedy and MediaTek Inc.'s entire and    *
+ * cumulative liability with respect to MediaTek Software released hereunder  *
+ * will be, at MediaTek Inc.'s sole discretion, to replace or revise the      *
+ * MediaTek Software at issue.                                                *
+ *                                                                            *
+ *   5)The transaction contemplated hereunder shall be construed in           *
+ * accordance with the laws of Singapore, excluding its conflict of laws      *
+ * principles.  Any disputes, controversies or claims arising thereof and     *
+ * related thereto shall be settled via arbitration in Singapore, under the   *
+ * then current rules of the International Chamber of Commerce (ICC).  The    *
+ * arbitration shall be conducted in English. The awards of the arbitration   *
+ * shall be final and binding upon both parties and shall be entered and      *
+ * enforceable in any court of competent jurisdiction.                        *
+ *---------------------------------------------------------------------------*/
+
+//-----------------------------------------------------------------------------
+// Include files
+//-----------------------------------------------------------------------------
+#include "dramc_common.h"
+#include "x_hal_io.h"
+#include "dramc_actiming.h"
+#include "dramc_int_global.h"
+#include "dramc_dv_init.h"
+
+//-----------------------------------------------------------------------------
+// Global variables
+//-----------------------------------------------------------------------------
+U32 u4Datlat = 0;
+
+static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4];
+//static const ACTime_T_LP5 ACTimingTbl_LP5[AC_TIMING_NUMBER_LP5];
+//-------------------------------------------------------------------------
+/** u1GetACTimingIdx()
+ *  Retrieve internal ACTimingTbl's index according to dram type, freqGroup, Read DBI status
+ *  @param p                Pointer of context created by DramcCtxCreate.
+ *  @retval u1TimingIdx     Return ACTimingTbl entry's index
+ */
+//-------------------------------------------------------------------------
+static U8 u1GetACTimingIdx(DRAMC_CTX_T *p)
+{
+    U8 u1TimingIdx = 0xff, u1TmpIdx;
+    U8 u1TmpDramType = p->dram_type;
+
+#if (__LP5_COMBO__ == TRUE)
+    if (TRUE == is_lp5_family(p))
+    {
+        u1TmpDramType = TYPE_LPDDR5;
+    }
+    else
+#endif
+    {
+        // LP4/LP4P/LP4X use same table
+        if (u1TmpDramType == TYPE_LPDDR4X || u1TmpDramType == TYPE_LPDDR4P)
+            u1TmpDramType = TYPE_LPDDR4;
+    }
+
+#if (__LP5_COMBO__ == TRUE)
+    if (TRUE == is_lp5_family(p))
+    {
+        for (u1TmpIdx = 0; u1TmpIdx < AC_TIMING_NUMBER_LP5; u1TmpIdx++)
+        {
+            if ((ACTimingTbl_LP5[u1TmpIdx].dramType == u1TmpDramType) &&
+                /* p->frequency may not be in ACTimingTable, use p->freqGroup */
+                (ACTimingTbl_LP5[u1TmpIdx].freq == p->freqGroup) &&
+                (ACTimingTbl_LP5[u1TmpIdx].readDBI == p->DBI_R_onoff[p->dram_fsp]) &&
+                (ACTimingTbl_LP5[u1TmpIdx].DivMode == vGet_Div_Mode(p)) && // Darren for LP4 1:4 and 1:8 mode
+                (ACTimingTbl_LP5[u1TmpIdx].cbtMode == vGet_Dram_CBT_Mode(p)) //LP4 byte/mixed mode dram both use byte mode ACTiming
+               )
+            {
+                u1TimingIdx = u1TmpIdx;
+                //Also for Dump_REG
+                mcSHOW_DBG_MSG2(("match AC timing %d\n", u1TimingIdx));
+                break;
+            }
+        }
+    }
+    else
+#endif
+    {
+        for (u1TmpIdx = 0; u1TmpIdx < AC_TIMING_NUMBER_LP4; u1TmpIdx++)
+        {
+            if ((ACTimingTbl_LP4[u1TmpIdx].dramType == u1TmpDramType) &&
+                /* p->frequency may not be in ACTimingTable, use p->freqGroup */
+                (ACTimingTbl_LP4[u1TmpIdx].freq == p->freqGroup) &&
+                (ACTimingTbl_LP4[u1TmpIdx].readDBI == p->DBI_R_onoff[p->dram_fsp]) &&
+                (ACTimingTbl_LP4[u1TmpIdx].DivMode == vGet_Div_Mode(p)) && // Darren for LP4 1:4 and 1:8 mode
+                (ACTimingTbl_LP4[u1TmpIdx].cbtMode == vGet_Dram_CBT_Mode(p)) //LP4 byte/mixed mode dram both use byte mode ACTiming
+               )
+            {
+                u1TimingIdx = u1TmpIdx;
+                //mcDUMP_REG_MSG(("match AC timing %d\n", u1TimingIdx));
+                //Also for Dump_REG
+                mcSHOW_DBG_MSG2(("match AC timing %d\n", u1TimingIdx));
+                mcSHOW_DBG_MSG2(("dramType %d, freq %d, readDBI %d, DivMode %d, cbtMode %d\n", u1TmpDramType, p->freqGroup, p->DBI_R_onoff[p->dram_fsp], vGet_Div_Mode(p), vGet_Dram_CBT_Mode(p)));
+                break;
+            }
+        }
+    }
+
+    return u1TimingIdx;
+}
+
+static U8 u1GetDQSIEN_p2s_latency(U8 p2s_ratio)
+{
+    U8 ser_latency = 0;
+
+    switch(p2s_ratio)
+    {
+        case 16:
+            ser_latency = 18;
+            break;
+        case 8:
+            ser_latency = 8;
+            break;
+        case 4:
+            ser_latency = 4;
+            break;
+        case 2:
+            ser_latency = 2;
+            break;
+        default:
+            mcSHOW_ERR_MSG(("Error: %d is unexpected p2s ratio \n", p2s_ratio));
+    }
+
+    return ser_latency;
+}
+
+static U8 u1GetDQ_CA_p2s_latency(U8 p2s_ratio, U8 frate)
+{
+    U8 ser_latency = 0;
+
+    if(((p2s_ratio == 2) && (frate == 0)) || (frate > 1))
+    {
+        mcSHOW_ERR_MSG(("Error: when p2s ratio is 2, frate should be 1. But p2s ratio is %d, frate is %d\n", p2s_ratio, frate));
+    }
+
+    switch(p2s_ratio)
+    {
+        case 16:
+            ser_latency = 9;
+            break;
+        case 8:
+            ser_latency = 5;
+            break;
+        case 4:
+            ser_latency = 3;
+            break;
+        case 2:
+            ser_latency = 1;
+            break;
+        default:
+            mcSHOW_ERR_MSG(("Error: %d is unexpected p2s ratio \n", p2s_ratio));
+    }
+
+    return ser_latency;
+}
+
+static U32 A_div_B_Round(U32 A, U32 B)
+{
+    U32 result;
+
+    if (B == 0)
+    {
+        return 0xffff;
+    }
+
+    result = A/B;
+
+    if ((A - result*B) >= ((result + 1)*B - A))
+    {
+        return (result + 1);
+    }
+    else
+    {
+        return result;
+    }
+}
+
+static void DramcCalculate_Datlat_val(DRAMC_CTX_T *p)
+{
+    U32 u4TxPipeline = 0, u4RxPipeline = 0;
+    U32 u4Datlat_dsel = 0, u4Datlat_margin = 1, u4RDSEL_Offset = 2;
+    U32 u4DQ_P2S_Ratio = A_D->DQ_P2S_RATIO, u4CA_p2s_ratio = 0, u4CKR = A_D->CKR;
+    U32 u4CAdefault_delay = 1, u4CS2RL_start = 0, u4tRPRE_toggle = 0;
+    U32 u4DQSIEN_ser_latency = 0, u4CA_ser_latency = 0;
+    U32 u4DQ_ui_unit = 0, u4CA_ui_unit = 0, u4Dram_ui_ratio = 2, u4MCK_unit = 0;
+    U32 u4RL[2] = {0}, u4RLMax = 0, u4DQ_2_1stDVI4CK = 0, u4CA_MCKIO_ui_unit = 0;
+    U32 u4tDQSCK_Max = 0;
+    U32 u4RX_rdcmdout2rdcmdbus_by_ps = 0;
+
+    u4DQ_ui_unit =  (1000000 / (DDRPhyGetRealFreq(p) * 2));
+    u4CA_ui_unit = u4CKR * u4DQ_ui_unit;
+
+    if (u1IsLP4Family(p->dram_type))
+    {
+        u4CS2RL_start = 7;
+        u4tRPRE_toggle = 0;
+        u4tDQSCK_Max = 3500;  //ps
+        u4RL[0] = Get_RL_by_MR_LP4(p->dram_cbt_mode[RANK_0], 0, LP4_DRAM_INIT_RLWL_MRfield_config(p->frequency * 2));
+        u4RL[1] = Get_RL_by_MR_LP4(p->dram_cbt_mode[RANK_1], 0, LP4_DRAM_INIT_RLWL_MRfield_config(p->frequency * 2));
+        u4RLMax = (u4RL[0] > u4RL[1]) ? u4RL[0] : u4RL[1];
+    }
+    else
+    {
+        mcSHOW_ERR_MSG(("Error DramType[%d] !!!\n", p->dram_type));
+        #if __ETT__
+        while (1);
+        #endif
+    }
+
+    if (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_TX_PIPE_CTRL), SHU_MISC_TX_PIPE_CTRL_TX_PIPE_BYPASS_EN))
+    {
+        u4TxPipeline = 1;
+    }
+    else
+    {
+        u4TxPipeline = 0;
+    }
+
+    if (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL), SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN))
+    {
+        u4RxPipeline = 0;
+    }
+    else
+    {
+        u4RxPipeline = 1;
+    }
+
+    u4DQ_2_1stDVI4CK = 5 * u4DQ_ui_unit * u4Dram_ui_ratio;
+    u4RDSEL_Offset = 2 + 2 *(u4DQ_P2S_Ratio == 4);
+    u4MCK_unit = u4DQ_ui_unit * u4DQ_P2S_Ratio;
+    u4CA_p2s_ratio = u4DQ_P2S_Ratio / u4CKR;
+    u4DQSIEN_ser_latency = u1GetDQSIEN_p2s_latency(u4DQ_P2S_Ratio);
+    u4CA_ser_latency = u1GetDQ_CA_p2s_latency(u4CA_p2s_ratio, A_D->CA_FULL_RATE);
+    u4CA_MCKIO_ui_unit = u4DQ_ui_unit * u4CKR / (A_D->CA_FULL_RATE + 1);
+    u4RX_rdcmdout2rdcmdbus_by_ps = 3 * u4MCK_unit + u4CAdefault_delay * u4CA_ui_unit + u4CA_ser_latency * u4CA_MCKIO_ui_unit /*+ RX_C->ca_default_PI * RX_C->ca_MCKIO_ps / RX_C->ca_ui_pi_ratio*/ ; // 3 is 1.5T pipe to APHY + 0.5T wait posedge then start P2S + 1T read_cmd_out
+    u4Datlat_dsel = A_div_B_Round((u4RX_rdcmdout2rdcmdbus_by_ps + (u4CS2RL_start + u4RLMax * 2 )* u4CKR * u4DQ_ui_unit + u4tDQSCK_Max + u4DQ_2_1stDVI4CK), u4MCK_unit) - u4RDSEL_Offset - u4TxPipeline + u4Datlat_margin;
+    u4Datlat = u4Datlat_dsel + u4TxPipeline + u4RxPipeline - 1;
+
+    mcSHOW_DBG_MSG(("Calculate Datlat value is %d on freq %d\n", u4Datlat, p->frequency));
+}
+
+//-------------------------------------------------------------------------
+/** UpdateACTimingReg()
+ *  ACTiming related register field update
+ *  @param p                Pointer of context created by DramcCtxCreate.
+ *  @param  ACTbl           Pointer to correct ACTiming table struct
+ *  @retval status          (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL
+ */
+//-------------------------------------------------------------------------
+#if __LP5_COMBO__
+static DRAM_STATUS_T DdrUpdateACTimingReg_LP5(DRAMC_CTX_T *p, const ACTime_T_LP5 *ACTbl)
+{
+    ACTime_T_LP5 ACTblFinal;
+    U8 backup_rank = p->rank;
+    DRAM_ODT_MODE_T r2w_odt_onoff = p->odt_onoff; //Variable used in step 1 (decide to use odt on or off ACTiming)
+    // ACTiming regs that have ODT on/off values -> declare variables to save the wanted value
+    // -> Used to retrieve correct SHU_ACTIM2_TR2W value and write into final register field
+#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
+    U8 u1RANKINCTL = 0;
+#endif
+    U8 RODT_TRACKING_SAVEING_MCK = 0, u1ROOT = 0, u1TXRANKINCTL = 0, u1TXDLY = 0, u1DATLAT_DSEL = 0; //Used to store tmp ACTiming values
+
+#if SAMSUNG_LP4_NWR_WORKAROUND
+    U8 u1TWTR = 0, u1TWTR_05T = 0, u1TWTR_TMP = 0;
+#endif
+    // ACTiming regs that aren't currently in ACTime_T struct
+    U8 u1TREFBW = 0; //REFBW_FR (tREFBW) for LP3, REFBW_FR=0 & TREFBWIG=1 (by CF)
+    U8 u1TFAW_05T=0, u1TRRD_05T=0;
+    U16 u2XRTWTW = 0, u2XTRTRT = 0, u2XRTW2R = 0, u2XRTR2W = 0, u2TFAW = 0;
+    U16 u2TRTW=0, u2TRTW_05T=0, u2TMRR2W=0, u2TRRD=0;
+
+#if XRTRTR_NEW_CROSS_RK_MODE
+    U16 u2PHSINCTL = 0;
+#endif
+
+    U32 u4RankINCTL_ROOT;
+
+    if(ACTbl == NULL)
+        return DRAM_FAIL;
+    ACTblFinal = *ACTbl;
+
+    u4Datlat = ACTblFinal.datlat;
+
+    // ----Step 1: Perform ACTiming table adjustments according to different usage/scenarios--------------------------
+#if ENABLE_TX_WDQS
+    r2w_odt_onoff = ODT_ON;
+#else
+    r2w_odt_onoff = p->odt_onoff;
+#endif
+
+    // ACTimings that have different values for odt on/off, retrieve the correct one and store in local variable
+    if (r2w_odt_onoff == ODT_ON) //odt_on
+    {
+        u2TRTW = ACTblFinal.tr2w_odt_on;
+        u2TRTW_05T = ACTblFinal.tr2w_odt_on_05T;
+        u2XRTW2R = ACTblFinal.xrtw2r_odt_on_otf_off;
+        u2XRTR2W = ACTblFinal.xrtr2w_odt_on;
+    }
+    else //odt_off
+    {
+        u2TRTW = ACTblFinal.tr2w_odt_off;
+        u2TRTW_05T = ACTblFinal.tr2w_odt_off_05T;
+        u2XRTW2R = ACTblFinal.xrtw2r_odt_off_otf_off;
+        u2XRTR2W = ACTblFinal.xrtr2w_odt_off;
+    }
+
+    // Override the above tRTW & tRTW_05T selection for Hynix LPDDR4P dram (always use odt_on's value for tRTW)
+    if ((p->dram_type == TYPE_LPDDR4P) && (p->vendor_id == VENDOR_HYNIX)) //!SUPPORT_HYNIX_RX_DQS_WEAK_PULL (temp solution, need to discuss with SY)
+    {
+        u2TRTW = ACTblFinal.tr2w_odt_on;
+        u2TRTW_05T = ACTblFinal.tr2w_odt_on_05T;
+    }
+
+    if (r2w_odt_onoff == ODT_ON)
+    {
+        u2XTRTRT = ACTblFinal.xrtr2r_odt_on;
+        u2XRTWTW = ACTblFinal.xrtw2w_odt_on;
+    }
+    else
+    {
+        u2XTRTRT = ACTblFinal.xrtr2r_odt_off;
+        u2XRTWTW = ACTblFinal.xrtw2w_odt_off;
+    }
+
+#if ENABLE_RODT_TRACKING_SAVE_MCK
+    // for rodt tracking save 1 MCK and rodt tracking enable or not(RODTENSTB_TRACK_EN)
+    u1ODT_ON = p->odt_onoff;
+    u1RODT_TRACK = ENABLE_RODT_TRACKING;
+    u1ROEN = u1WDQS_ON | u1ODT_ON;
+    u1ModeSel = u1RODT_TRACK & u1ROEN;
+
+    // when WDQS on and RODT Track define open and un-term, RODT_TRACKING_SAVEING_MCK = 1 for the future setting
+    // Maybe "Save 1 MCK" will be set after Vins_on project, but Bian_co & Vins_on can not.(different with performance team)
+    //if (u1RODT_TRACK && (u1ROEN==1))
+    //    RODT_TRACKING_SAVEING_MCK = 1;
+#endif
+
+#if (ENABLE_RODT_TRACKING || defined(XRTR2W_PERFORM_ENHANCE_RODTEN))
+    /* yr: same code
+    // set to 0, let TRTW & XRTR2W setting values are the smae with DV-sim's value that DE provided
+    if (r2w_odt_onoff == ODT_ON) RODT_TRACKING_SAVEING_MCK = 0; //RODT_TRACKING eanble can save r2w 1 MCK
+    else RODT_TRACKING_SAVEING_MCK = 0;
+    */
+    RODT_TRACKING_SAVEING_MCK = 0;
+#endif
+
+    // Update values that are used by RODT_TRACKING_SAVEING_MCK
+    u2TRTW = u2TRTW - RODT_TRACKING_SAVEING_MCK;
+    u2XRTR2W = u2XRTR2W - RODT_TRACKING_SAVEING_MCK;
+
+#if SAMSUNG_LP4_NWR_WORKAROUND
+    // If nWR is fixed to 30 for all freqs, tWTR@800Mhz should add 2tCK gap, allowing sufficient Samsung DRAM internal IO precharge time
+    if ((p->vendor_id == VENDOR_SAMSUNG) && (p->frequency == 800)) //LP4X, Samsung, DDR1600
+    {
+        u1TWTR_TMP = (ACTblFinal.twtr * 4 - ACTblFinal.twtr_05T * 2) + 2; //Convert TWTR to tCK, and add 2tCK
+        if ((u1TWTR_TMP % 4) == 0) //TWTR can be transferred to TWTR directly
+        {
+            u1TWTR = u1TWTR_TMP >> 2;
+            u1TWTR_05T = 0;
+        }
+        else //Can't be transfered to TWTR directly
+        {
+            u1TWTR = (u1TWTR_TMP + 2) >> 2; //Add 2 tCK and set TWTR value (Then minus 2tCK using 05T)
+            u1TWTR_05T = 1;  //05T means minus 2tCK
+        }
+
+        ACTblFinal.twtr = u1TWTR;
+        ACTblFinal.twtr_05T = u1TWTR_05T;
+    }
+#endif
+
+    //DATLAT related
+    if (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL), SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN))
+        u1DATLAT_DSEL = u4Datlat;
+    else
+        u1DATLAT_DSEL = u4Datlat - 1;
+
+#if TX_OE_EXTEND
+    u2XRTWTW += 1;
+    u2XRTW2R += 1;
+#endif
+
+#if 0//(!CMD_CKE_WORKAROUND_FIX)
+    U8 u1Txp = 0, u1Txp0p5 = 0;
+
+    if (((p->frequency <= 1866) && (p->frequency >= 1600)) || ((vGet_Div_Mode(p) == DIV4_MODE) && (p->frequency == 400)))
+    {
+        u1Txp = 1;
+    }
+    else if ((p->frequency == 2133) || ((vGet_Div_Mode(p) == DIV4_MODE) && ((p->frequency <= 800) || (p->frequency >= 600))))
+    {
+        u1Txp = 2;
+    }
+
+    if ((p->frequency == 1866) || ((p->frequency <= 1333) && (p->frequency >= 1200)))
+    {
+        u1Txp0p5 = 1;
+    }
+
+    ACTblFinal.txp = u1Txp;
+    ACTblFinal.txp_05T = u1Txp0p5;
+    ACTblFinal.ckelckcnt = 4;
+    ACTblFinal.earlyckecnt = 0;
+    ACTblFinal.ckeprd -= 1;
+#endif
+
+    // ----Step 2: Perform register writes for entries in ACTblFinal struct & ACTiming excel file (all actiming adjustments should be done in Step 1)-------
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM1, P_Fld(ACTblFinal.tras, SHU_ACTIM1_TRAS)
+                                                | P_Fld(ACTblFinal.trp, SHU_ACTIM1_TRP)
+                                                | P_Fld(ACTblFinal.trpab, SHU_ACTIM1_TRPAB)
+                                                | P_Fld(ACTblFinal.tmrwckel, SHU_ACTIM1_TMRWCKEL)
+                                                | P_Fld(ACTblFinal.trc, SHU_ACTIM1_TRC));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM3, P_Fld(ACTblFinal.trfc, SHU_ACTIM3_TRFC)
+                                                | P_Fld(ACTblFinal.tr2mrr, SHU_ACTIM3_TR2MRR)
+                                                | P_Fld(ACTblFinal.trfcpb, SHU_ACTIM3_TRFCPB));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM2, P_Fld(ACTblFinal.txp, SHU_ACTIM2_TXP)
+                                                | P_Fld(ACTblFinal.tmrri, SHU_ACTIM2_TMRRI)
+                                                | P_Fld(ACTblFinal.tfaw, SHU_ACTIM2_TFAW)
+                                                | P_Fld(u2TRTW, SHU_ACTIM2_TR2W) // Value has odt_on/off difference, use local variable u1TRTW
+                                                | P_Fld(ACTblFinal.trtp, SHU_ACTIM2_TRTP));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM0, P_Fld(ACTblFinal.trcd, SHU_ACTIM0_TRCD)
+                                                | P_Fld(ACTblFinal.twr, SHU_ACTIM0_TWR)
+                                                | P_Fld(ACTblFinal.trrd, SHU_ACTIM0_TRRD));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM5, P_Fld(ACTblFinal.tpbr2pbr, SHU_ACTIM5_TPBR2PBR)
+                                                | P_Fld(ACTblFinal.twtpd, SHU_ACTIM5_TWTPD)
+                                                | P_Fld(ACTblFinal.tpbr2act, SHU_ACTIM5_TPBR2ACT));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM6, P_Fld(ACTblFinal.tr2mrw, SHU_ACTIM6_TR2MRW)
+                                                | P_Fld(ACTblFinal.tw2mrw, SHU_ACTIM6_TW2MRW)
+                                                | P_Fld(ACTblFinal.tmrd, SHU_ACTIM6_TMRD)
+                                                | P_Fld(ACTblFinal.zqlat2, SHU_ACTIM6_TZQLAT2)
+                                                | P_Fld(ACTblFinal.tmrw, SHU_ACTIM6_TMRW));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM4, P_Fld(ACTblFinal.tmrr2mrw, SHU_ACTIM4_TMRR2MRW)
+                                                | P_Fld(ACTblFinal.tmrr2w, SHU_ACTIM4_TMRR2W)
+                                                | P_Fld(ACTblFinal.tzqcs, SHU_ACTIM4_TZQCS)
+                                                | P_Fld(ACTblFinal.txrefcnt, SHU_ACTIM4_TXREFCNT));
+
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_CKECTRL, ACTblFinal.ckeprd, SHU_CKECTRL_TCKEPRD);
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(u2XRTWTW, SHU_ACTIM_XRT_XRTW2W)
+                                                | P_Fld(u2XRTW2R, SHU_ACTIM_XRT_XRTW2R)
+                                                | P_Fld(u2XRTR2W, SHU_ACTIM_XRT_XRTR2W)
+                                                | P_Fld(u2XTRTRT, SHU_ACTIM_XRT_XRTR2R));
+
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_VRCG, ACTblFinal.vrcgdis_prdcnt, SHU_HWSET_VRCG_VRCGDIS_PRDCNT);
+//    vIO32WriteFldMulti_All(DRAMC_REG_SHU_HWSET_VRCG, P_Fld(ACTblFinal.vrcgdis_prdcnt, SHU_HWSET_VRCG_VRCGDIS_PRDCNT)
+//                                                | P_Fld(ACTblFinal.hwset_vrcg_op, SHU_HWSET_VRCG_HWSET_VRCG_OP));
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_MR2, ACTblFinal.hwset_mr2_op, SHU_HWSET_MR2_HWSET_MR2_OP);
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_MR13, ACTblFinal.hwset_mr13_op, SHU_HWSET_MR13_HWSET_MR13_OP);
+
+    // AC timing 0.5T
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(ACTblFinal.twtr_05T, SHU_AC_TIME_05T_TWTR_M05T)
+                                                    | P_Fld(ACTblFinal.twtr_l_05T, SHU_AC_TIME_05T_BGTWTR_M05T)
+                                                    | P_Fld(u2TRTW_05T, SHU_AC_TIME_05T_TR2W_05T) // Value has odt_on/off difference, use local variable u1TRTW
+                                                    | P_Fld(ACTblFinal.twtpd_05T, SHU_AC_TIME_05T_TWTPD_M05T)
+                                                    | P_Fld(ACTblFinal.tfaw_05T, SHU_AC_TIME_05T_TFAW_05T)
+                                                    | P_Fld(ACTblFinal.trrd_05T, SHU_AC_TIME_05T_TRRD_05T)
+                                                    | P_Fld(ACTblFinal.twr_05T, SHU_AC_TIME_05T_TWR_M05T)
+                                                    | P_Fld(ACTblFinal.tras_05T, SHU_AC_TIME_05T_TRAS_05T)
+                                                    | P_Fld(ACTblFinal.trpab_05T, SHU_AC_TIME_05T_TRPAB_05T)
+                                                    | P_Fld(ACTblFinal.trp_05T, SHU_AC_TIME_05T_TRP_05T)
+                                                    | P_Fld(ACTblFinal.trcd_05T, SHU_AC_TIME_05T_TRCD_05T)
+                                                    | P_Fld(ACTblFinal.trtp_05T, SHU_AC_TIME_05T_TRTP_05T)
+                                                    | P_Fld(ACTblFinal.txp_05T, SHU_AC_TIME_05T_TXP_05T)
+                                                    | P_Fld(ACTblFinal.trfc_05T, SHU_AC_TIME_05T_TRFC_05T)
+                                                    | P_Fld(ACTblFinal.trfcpb_05T, SHU_AC_TIME_05T_TRFCPB_05T)
+                                                    | P_Fld(ACTblFinal.tpbr2pbr_05T, SHU_AC_TIME_05T_TPBR2PBR_05T)
+                                                    | P_Fld(ACTblFinal.tpbr2act_05T, SHU_AC_TIME_05T_TPBR2ACT_05T)
+                                                    | P_Fld(ACTblFinal.tr2mrw_05T, SHU_AC_TIME_05T_TR2MRW_05T)
+                                                    | P_Fld(ACTblFinal.tw2mrw_05T, SHU_AC_TIME_05T_TW2MRW_05T)
+                                                    | P_Fld(ACTblFinal.tmrr2mrw_05T, SHU_AC_TIME_05T_TMRR2MRW_05T)
+                                                    | P_Fld(ACTblFinal.tmrw_05T, SHU_AC_TIME_05T_TMRW_05T)
+                                                    | P_Fld(ACTblFinal.tmrd_05T, SHU_AC_TIME_05T_TMRD_05T)
+                                                    | P_Fld(ACTblFinal.tmrwckel_05T, SHU_AC_TIME_05T_TMRWCKEL_05T)
+                                                    | P_Fld(ACTblFinal.tmrri_05T, SHU_AC_TIME_05T_TMRRI_05T)
+                                                    | P_Fld(ACTblFinal.trc_05T, SHU_AC_TIME_05T_TRC_05T));
+
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM0, ACTblFinal.twtr_l, SHU_ACTIM0_TWTR_L);
+        vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM7, P_Fld(ACTblFinal.tcsh_cscal, SHU_ACTIM7_TCSH_CSCAL)
+                                                           | P_Fld(ACTblFinal.tcacsh, SHU_ACTIM7_TCACSH));
+    }
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM0, ACTblFinal.twtr, SHU_ACTIM0_TWTR);
+        vIO32WriteFldMulti_All(DRAMC_REG_SHU_CKECTRL, P_Fld(ACTblFinal.tpde, SHU_CKECTRL_TPDE)
+                                                        | P_Fld(ACTblFinal.tpdx, SHU_CKECTRL_TPDX)
+                                                        | P_Fld(ACTblFinal.tpde_05T, SHU_CKECTRL_TPDE_05T)
+                                                        | P_Fld(ACTblFinal.tpdx_05T, SHU_CKECTRL_TPDX_05T));
+        vIO32WriteFldMulti_All(DRAMC_REG_SHU_WCKCTRL, P_Fld(ACTblFinal.wckrdoff, SHU_WCKCTRL_WCKRDOFF)
+                                                        | P_Fld(ACTblFinal.wckrdoff_05T, SHU_WCKCTRL_WCKRDOFF_05T)
+                                                        | P_Fld(ACTblFinal.wckwroff, SHU_WCKCTRL_WCKWROFF)
+                                                        | P_Fld(ACTblFinal.wckwroff_05T, SHU_WCKCTRL_WCKWROFF_05T));
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM5, ACTblFinal.trtpd, SHU_ACTIM5_TR2PD);
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_TIME_05T, ACTblFinal.trtpd_05T, SHU_AC_TIME_05T_TR2PD_05T);
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_LP5_CMD, ACTblFinal.tcsh, SHU_LP5_CMD_TCSH);
+    }
+
+#if AC_TIMING_DERATE_ENABLE
+    if (u1IsLP4Family(p->dram_type))
+    {
+        vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING0, P_Fld(ACTblFinal.trcd_derate, SHU_AC_DERATING0_TRCD_DERATE)
+                                                        | P_Fld(ACTblFinal.trrd_derate, SHU_AC_DERATING0_TRRD_DERATE));
+        vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING1, P_Fld(ACTblFinal.trc_derate, SHU_AC_DERATING1_TRC_DERATE)
+                                                        | P_Fld(ACTblFinal.tras_derate, SHU_AC_DERATING1_TRAS_DERATE)
+                                                        | P_Fld(ACTblFinal.trp_derate, SHU_AC_DERATING1_TRP_DERATE)
+                                                        | P_Fld(ACTblFinal.trpab_derate, SHU_AC_DERATING1_TRPAB_DERATE));
+        vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING_05T, P_Fld(ACTblFinal.trrd_05T_derate, SHU_AC_DERATING_05T_TRRD_05T_DERATE)
+                                                        | P_Fld(ACTblFinal.tras_05T_derate, SHU_AC_DERATING_05T_TRAS_05T_DERATE)
+                                                        | P_Fld(ACTblFinal.trpab_05T_derate, SHU_AC_DERATING_05T_TRPAB_05T_DERATE)
+                                                        | P_Fld(ACTblFinal.trp_05T_derate, SHU_AC_DERATING_05T_TRP_05T_DERATE)
+                                                        | P_Fld(ACTblFinal.trcd_05T_derate, SHU_AC_DERATING_05T_TRCD_05T_DERATE)
+                                                        | P_Fld(ACTblFinal.trc_05T_derate, SHU_AC_DERATING_05T_TRC_05T_DERATE));
+        vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL3, 0xc0, REFCTRL3_REF_DERATING_EN);
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_DERATING0, 0x1, SHU_AC_DERATING0_ACDERATEEN); //enable derating for AC timing
+    }
+#endif
+
+    // DQSINCTL related
+    vSetRank(p, RANK_0);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL);// Rank 0 DQSINCTL
+    vSetRank(p, RANK_1);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL);// Rank 1 DQSINCTL
+    vSetRank(p, backup_rank);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_ODTCTRL, ACTblFinal.dqsinctl, MISC_SHU_ODTCTRL_RODT_LAT);
+
+    if (ACTblFinal.dqsinctl >= 2)
+    {
+        u4RankINCTL_ROOT = ACTblFinal.dqsinctl - 2;
+    }
+    else
+    {
+        mcSHOW_ERR_MSG(("u4RankINCTL_ROOT <2, Please check\n"));
+        u4RankINCTL_ROOT = 0;
+    }
+
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(ACTblFinal.dqsinctl, MISC_SHU_RANKCTL_RANKINCTL_PHY)
+                                                       | P_Fld(u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL_ROOT1)
+                                                       | P_Fld(u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL));
+
+#if XRTRTR_NEW_CROSS_RK_MODE
+    u2PHSINCTL = (ACTblFinal.dqsinctl == 0)? 0: (ACTblFinal.dqsinctl - 1);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, u2PHSINCTL, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL);
+#endif
+
+    // DATLAT related, tREFBW
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(u4Datlat, MISC_SHU_RDAT_DATLAT)
+                                            | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL)
+                                            | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
+
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIMING_CONF, u1TREFBW, SHU_ACTIMING_CONF_REFBW_FR);
+
+    // ----Step 3: Perform register writes/calculation for other regs (That aren't in ACTblFinal struct)------------------------------------------------
+#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
+    //Wei-Jen: Ininital setting values are the same, RANKINCTL_RXDLY = RANKINCTL = RANKINCTL_ROOT1
+    //XRTR2R setting will be updated in RxdqsGatingPostProcess
+    u1RANKINCTL = u4IO32ReadFldAlign(DDRPHY_REG_MISC_SHU_RANKCTL, MISC_SHU_RANKCTL_RANKINCTL);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RANKCTL, u1RANKINCTL, MISC_SHU_RANKCTL_RANKINCTL_RXDLY);
+#endif
+
+    //Update releated RG of XRTW2W
+    if (p->frequency <= 800)
+    {
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+        {
+            u1ROOT = 0; u1TXRANKINCTL = 1; u1TXDLY = 2;
+        }
+        else
+        {
+            u1ROOT = 0; u1TXRANKINCTL = 0; u1TXDLY = 1;
+        }
+    }
+    else
+    {
+        u1ROOT = (p->frequency == 1866)? 1: 0;
+        u1TXRANKINCTL = 1; u1TXDLY = 2;
+    }
+    #if TX_OE_EXTEND
+    if (p->frequency >= 1333)
+    {
+        u1TXRANKINCTL += 1;
+        u1TXDLY += 1;
+    }
+    #endif
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(u1ROOT, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)
+                                                | P_Fld(u1TXRANKINCTL, SHU_TX_RANKCTL_TXRANKINCTL)
+                                                | P_Fld(u1TXDLY, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY));
+
+    return DRAM_OK;
+}
+#endif
+
+#if ENABLE_WDQS_MODE_2
+static void WDQSMode2AcTimingEnlarge(DRAMC_CTX_T *p, U16 *u2_XRTW2W, U16 *u2_XRTR2W, U16 *u2_XRTW2R, U16 *u2_TRTW)
+{
+    U16 u2XRTW2W_enlarge = 0, u2XRTR2W_enlarge = 0;
+    U16 u2XRTW2R_enlarge = 0, u2TRTW_enlarge = 0;
+
+    switch (p->frequency)
+    {
+        case 1866:
+            u2XRTW2W_enlarge = 3;
+            break;
+        case 1600:
+            u2XRTW2W_enlarge = 2;
+            u2XRTR2W_enlarge = 1;
+            break;
+        case 1200:
+            u2XRTW2W_enlarge = 2;
+            if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+                u2XRTR2W_enlarge = 1;
+            break;
+        case 933:
+            u2XRTW2W_enlarge = 1;
+            if (vGet_Dram_CBT_Mode(p) == CBT_NORMAL_MODE)
+                u2XRTR2W_enlarge = 1;
+            break;
+        case 800:
+            u2XRTW2W_enlarge = 2;
+            u2TRTW_enlarge = 1;
+            if (vGet_Dram_CBT_Mode(p) == CBT_NORMAL_MODE)
+                u2XRTW2R_enlarge = 1;
+            break;
+        case 600:
+            u2XRTW2W_enlarge = 2;
+            u2TRTW_enlarge = 1;
+            if (vGet_Dram_CBT_Mode(p) == CBT_NORMAL_MODE)
+                u2XRTW2R_enlarge = 1;
+            break;
+        case 400:
+            u2XRTW2W_enlarge = 3;
+            u2TRTW_enlarge = 2;
+            u2XRTR2W_enlarge = 1;
+            break;
+        default:
+            mcSHOW_ERR_MSG(("[WDQSMode2AcTimingEnlarge] frequency err!\n"));
+            #if __ETT__
+            while (1);
+            #endif
+    }
+
+    *u2_XRTW2W += u2XRTW2W_enlarge;
+    *u2_XRTR2W += u2XRTR2W_enlarge;
+    *u2_XRTW2R += u2XRTW2R_enlarge;
+    *u2_TRTW += u2TRTW_enlarge;
+}
+#endif
+
+static DRAM_STATUS_T DdrUpdateACTimingReg_LP4(DRAMC_CTX_T *p, const ACTime_T_LP4 *ACTbl)
+{
+    ACTime_T_LP4 ACTblFinal;
+    U8 backup_rank = p->rank;
+    DRAM_ODT_MODE_T r2w_odt_onoff = p->odt_onoff; //Variable used in step 1 (decide to use odt on or off ACTiming)
+    // ACTiming regs that have ODT on/off values -> declare variables to save the wanted value
+    // -> Used to retrieve correct SHU_ACTIM2_TR2W value and write into final register field
+#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
+    U8 u1RANKINCTL = 0;
+#endif
+    U8 RODT_TRACKING_SAVEING_MCK = 0, u1ROOT = 0, u1TXRANKINCTL = 0, u1TXDLY = 0, u1DATLAT_DSEL = 0; //Used to store tmp ACTiming values
+
+#if SAMSUNG_LP4_NWR_WORKAROUND
+    U8 u1TWTR = 0, u1TWTR_05T = 0, u1TWTR_TMP = 0;
+    U8 u1MCKtoTck = 0, u105TtoTck = 0;
+#endif
+    // ACTiming regs that aren't currently in ACTime_T struct
+    U8 u1TREFBW = 0; //REFBW_FR (tREFBW) for LP3, REFBW_FR=0 & TREFBWIG=1 (by CF)
+    U8 u1TFAW_05T=0, u1TRRD_05T=0;
+    U16 u2XRTWTW = 0, u2XTRTRT = 0, u2XRTW2R = 0, u2XRTR2W = 0, u2TFAW = 0;
+    U16 u2TRTW=0, u2TRTW_05T=0, u2TMRR2W=0, u2TRRD=0;
+
+#if XRTRTR_NEW_CROSS_RK_MODE
+    U16 u2PHSINCTL = 0;
+#endif
+
+    U32 u4RankINCTL_ROOT;
+
+    if(ACTbl == NULL)
+        return DRAM_FAIL;
+    ACTblFinal = *ACTbl;
+
+#if ENABLE_DATLAT_BY_FORMULA
+    DramcCalculate_Datlat_val(p);
+#else
+    u4Datlat = ACTblFinal.datlat;
+#endif
+
+    // ----Step 1: Perform ACTiming table adjustments according to different usage/scenarios--------------------------
+#if ENABLE_TX_WDQS
+    r2w_odt_onoff = ODT_ON;
+#else
+    r2w_odt_onoff = p->odt_onoff;
+#endif
+    // ACTimings that have different values for odt on/off, retrieve the correct one and store in local variable
+    if (r2w_odt_onoff == ODT_ON) //odt_on
+    {
+        u2TRTW = ACTblFinal.trtw_odt_on;
+        u2TRTW_05T = ACTblFinal.trtw_odt_on_05T;
+        u2XRTW2R = ACTblFinal.xrtw2r_odt_on;
+        u2XRTR2W = ACTblFinal.xrtr2w_odt_on;
+    }
+    else //odt_off
+    {
+        u2TRTW = ACTblFinal.trtw_odt_off;
+        u2TRTW_05T = ACTblFinal.trtw_odt_off_05T;
+        u2XRTW2R = ACTblFinal.xrtw2r_odt_off;
+        u2XRTR2W = ACTblFinal.xrtr2w_odt_off;
+    }
+
+    // Override the above tRTW & tRTW_05T selection for Hynix LPDDR4P dram (always use odt_on's value for tRTW)
+    if ((p->dram_type == TYPE_LPDDR4P) && (p->vendor_id == VENDOR_HYNIX)) //!SUPPORT_HYNIX_RX_DQS_WEAK_PULL (temp solution, need to discuss with SY)
+    {
+        u2TRTW = ACTblFinal.trtw_odt_on;
+        u2TRTW_05T = ACTblFinal.trtw_odt_on_05T;
+    }
+
+    {
+        u2TFAW = ACTblFinal.tfaw_4266;
+        u1TFAW_05T = ACTblFinal.tfaw_4266_05T;
+        u2TRRD = ACTblFinal.trrd_4266;
+        u1TRRD_05T = ACTblFinal.trrd_4266_05T;
+    #if XRTRTR_NEW_CROSS_RK_MODE
+        u2XTRTRT = ACTblFinal.xrtr2r_new_mode;
+    #else
+        u2XTRTRT = ACTblFinal.xrtr2r_old_mode;
+    #endif
+
+    #if XRTWTW_NEW_CROSS_RK_MODE
+        u2XRTWTW = ACTblFinal.xrtw2w_new_mode;
+    #else
+        u2XRTWTW = ACTblFinal.xrtw2w_old_mode;
+    #endif
+
+    #if ENABLE_WDQS_MODE_2
+        WDQSMode2AcTimingEnlarge(p, &u2XRTWTW, &u2XRTR2W, &u2XRTW2R, &u2TRTW);
+    #endif
+
+        if (r2w_odt_onoff == ODT_ON)
+            u2TMRR2W = ACTblFinal.tmrr2w_odt_on;
+        else
+            u2TMRR2W = ACTblFinal.tmrr2w_odt_off;
+    }
+
+#if ENABLE_RODT_TRACKING_SAVE_MCK
+    // for rodt tracking save 1 MCK and rodt tracking enable or not(RODTENSTB_TRACK_EN)
+    u1ODT_ON = p->odt_onoff;
+    u1RODT_TRACK = ENABLE_RODT_TRACKING;
+    u1ROEN = u1WDQS_ON | u1ODT_ON;
+    u1ModeSel = u1RODT_TRACK & u1ROEN;
+
+    // when WDQS on and RODT Track define open and un-term, RODT_TRACKING_SAVEING_MCK = 1 for the future setting
+    // Maybe "Save 1 MCK" will be set after Vins_on project, but Bian_co & Vins_on can not.(different with performance team)
+    //if (u1RODT_TRACK && (u1ROEN==1))
+    //    RODT_TRACKING_SAVEING_MCK = 1;
+#endif
+
+#if (ENABLE_RODT_TRACKING || defined(XRTR2W_PERFORM_ENHANCE_RODTEN))
+    /* yr: same code
+    // set to 0, let TRTW & XRTR2W setting values are the smae with DV-sim's value that DE provided
+    if (r2w_odt_onoff == ODT_ON) RODT_TRACKING_SAVEING_MCK = 0; //RODT_TRACKING eanble can save r2w 1 MCK
+    else RODT_TRACKING_SAVEING_MCK = 0;
+    */
+    RODT_TRACKING_SAVEING_MCK = 0;
+#endif
+
+    // Update values that are used by RODT_TRACKING_SAVEING_MCK
+    u2TRTW = u2TRTW - RODT_TRACKING_SAVEING_MCK;
+    u2XRTR2W = u2XRTR2W - RODT_TRACKING_SAVEING_MCK;
+
+#if SAMSUNG_LP4_NWR_WORKAROUND
+    // If nWR is fixed to 30 for all freqs, tWTR@800Mhz should add 2tCK gap, allowing sufficient Samsung 1xnm DRAM internal IO precharge time
+    // Regarding the nWR setting recommandation, it is effective only for D1x LP4x, we changed logic from D1y (1ynm) to prevent that issue.
+    if ((p->vendor_id == VENDOR_SAMSUNG) && (p->frequency <= 800)) //LP4X, Samsung, DDR1600
+    {
+        if (vGet_Div_Mode(p) == DIV8_MODE)
+        {
+            u1MCKtoTck = 4;
+            u105TtoTck = 2;
+        }
+        else
+        {
+            u1MCKtoTck = 2;
+            u105TtoTck= 1;
+        }
+
+        u1TWTR_TMP = (ACTblFinal.twtr * u1MCKtoTck - ACTblFinal.twtr_05T * u105TtoTck) + 2; //Convert TWTR to tCK, and add 2tCK
+        if ((u1TWTR_TMP % u1MCKtoTck) == 0) //TWTR can be transferred to TWTR directly
+        {
+            u1TWTR = u1TWTR_TMP/u1MCKtoTck;
+            u1TWTR_05T = 0;
+        }
+        else //Can't be transfered to TWTR directly
+        {
+            u1TWTR = (u1TWTR_TMP + u105TtoTck)/u1MCKtoTck; //Add 2 tCK and set TWTR value (Then minus 2tCK using 05T)
+            u1TWTR_05T = 1;  //05T means minus 2tCK
+        }
+
+        ACTblFinal.twtr = u1TWTR;
+        ACTblFinal.twtr_05T = u1TWTR_05T;
+    }
+#endif
+
+    //DATLAT related
+    if (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL), SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN))
+        u1DATLAT_DSEL = u4Datlat; //ACTblFinal.datlat;
+    else
+        u1DATLAT_DSEL = u4Datlat - 1; //ACTblFinal.datlat - 1;
+
+#if TX_OE_EXTEND
+    u2XRTWTW += 1;
+    u2XRTW2R += 1;
+#endif
+
+#if 0//(!CMD_CKE_WORKAROUND_FIX)
+    U8 u1Txp = 0, u1Txp0p5 = 0;
+
+    if (((p->frequency <= 1866) && (p->frequency >= 1600)) || ((vGet_Div_Mode(p) == DIV4_MODE) && (p->frequency == 400)))
+    {
+        u1Txp = 1;
+    }
+    else if ((p->frequency == 2133) || ((vGet_Div_Mode(p) == DIV4_MODE) && ((p->frequency <= 800) || (p->frequency >= 600))))
+    {
+        u1Txp = 2;
+    }
+
+    if ((p->frequency == 1866) || ((p->frequency <= 1333) && (p->frequency >= 1200)))
+    {
+        u1Txp0p5 = 1;
+    }
+
+    ACTblFinal.txp = u1Txp;
+    ACTblFinal.txp_05T = u1Txp0p5;
+    ACTblFinal.ckelckcnt = 4;
+    ACTblFinal.earlyckecnt = 0;
+    ACTblFinal.ckeprd -= 1;
+#endif
+
+    // ----Step 2: Perform register writes for entries in ACTblFinal struct & ACTiming excel file (all actiming adjustments should be done in Step 1)-------
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM1, P_Fld(ACTblFinal.tras, SHU_ACTIM1_TRAS)
+                                                | P_Fld(ACTblFinal.trp, SHU_ACTIM1_TRP)
+                                                | P_Fld(ACTblFinal.trpab, SHU_ACTIM1_TRPAB)
+                                                | P_Fld(ACTblFinal.tmrwckel, SHU_ACTIM1_TMRWCKEL)
+                                                | P_Fld(ACTblFinal.trc, SHU_ACTIM1_TRC));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM3, P_Fld(ACTblFinal.trfc, SHU_ACTIM3_TRFC)
+                                                | P_Fld(ACTblFinal.tr2mrr, SHU_ACTIM3_TR2MRR)
+                                                | P_Fld(ACTblFinal.trfcpb, SHU_ACTIM3_TRFCPB));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM2, P_Fld(ACTblFinal.txp, SHU_ACTIM2_TXP)
+                                                | P_Fld(ACTblFinal.tmrri, SHU_ACTIM2_TMRRI)
+                                                | P_Fld(u2TFAW, SHU_ACTIM2_TFAW)
+                                                | P_Fld(u2TRTW, SHU_ACTIM2_TR2W) // Value has odt_on/off difference, use local variable u1TRTW
+                                                | P_Fld(ACTblFinal.trtp, SHU_ACTIM2_TRTP));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM0, P_Fld(ACTblFinal.trcd, SHU_ACTIM0_TRCD)
+                                                | P_Fld(ACTblFinal.twr, SHU_ACTIM0_TWR)
+                                                | P_Fld(u2TRRD, SHU_ACTIM0_TRRD));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM5, P_Fld(ACTblFinal.tpbr2pbr, SHU_ACTIM5_TPBR2PBR)
+                                                | P_Fld(ACTblFinal.twtpd, SHU_ACTIM5_TWTPD)
+                                                | P_Fld(ACTblFinal.tpbr2act, SHU_ACTIM5_TPBR2ACT));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM6, P_Fld(ACTblFinal.tr2mrw, SHU_ACTIM6_TR2MRW)
+                                                | P_Fld(ACTblFinal.tw2mrw, SHU_ACTIM6_TW2MRW)
+                                                | P_Fld(ACTblFinal.tmrd, SHU_ACTIM6_TMRD)
+                                                | P_Fld(ACTblFinal.zqlat2, SHU_ACTIM6_TZQLAT2)
+                                                | P_Fld(ACTblFinal.tmrw, SHU_ACTIM6_TMRW));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM4, P_Fld(ACTblFinal.tmrr2mrw, SHU_ACTIM4_TMRR2MRW)
+                                                | P_Fld(u2TMRR2W, SHU_ACTIM4_TMRR2W)
+                                                | P_Fld(ACTblFinal.tzqcs, SHU_ACTIM4_TZQCS)
+                                                | P_Fld(ACTblFinal.txrefcnt, SHU_ACTIM4_TXREFCNT));
+
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_CKECTRL, ACTblFinal.ckeprd, SHU_CKECTRL_TCKEPRD);
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(u2XRTWTW, SHU_ACTIM_XRT_XRTW2W)
+                                                | P_Fld(u2XRTW2R, SHU_ACTIM_XRT_XRTW2R)
+                                                | P_Fld(u2XRTR2W, SHU_ACTIM_XRT_XRTR2W)
+                                                | P_Fld(u2XTRTRT, SHU_ACTIM_XRT_XRTR2R));
+
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_VRCG, ACTblFinal.vrcgdis_prdcnt, SHU_HWSET_VRCG_VRCGDIS_PRDCNT);
+//    vIO32WriteFldMulti_All(DRAMC_REG_SHU_HWSET_VRCG, P_Fld(ACTblFinal.vrcgdis_prdcnt, SHU_HWSET_VRCG_VRCGDIS_PRDCNT)
+//                                                | P_Fld(ACTblFinal.hwset_vrcg_op, SHU_HWSET_VRCG_HWSET_VRCG_OP));
+    //tg removed. Only DramcModeRegInit_LP4() setting is preserved.
+    //vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_MR2, ACTblFinal.hwset_mr2_op, SHU_HWSET_MR2_HWSET_MR2_OP);
+    //vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_MR13, ACTblFinal.hwset_mr13_op, SHU_HWSET_MR13_HWSET_MR13_OP);
+
+    // AC timing 0.5T
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(ACTblFinal.twtr_05T, SHU_AC_TIME_05T_TWTR_M05T)
+                                                    | P_Fld(u2TRTW_05T, SHU_AC_TIME_05T_TR2W_05T) // Value has odt_on/off difference, use local variable u1TRTW
+                                                    | P_Fld(ACTblFinal.twtpd_05T, SHU_AC_TIME_05T_TWTPD_M05T)
+                                                    | P_Fld(u1TFAW_05T, SHU_AC_TIME_05T_TFAW_05T)
+                                                    | P_Fld(u1TRRD_05T, SHU_AC_TIME_05T_TRRD_05T)
+                                                    | P_Fld(ACTblFinal.twr_05T, SHU_AC_TIME_05T_TWR_M05T)
+                                                    | P_Fld(ACTblFinal.tras_05T, SHU_AC_TIME_05T_TRAS_05T)
+                                                    | P_Fld(ACTblFinal.trpab_05T, SHU_AC_TIME_05T_TRPAB_05T)
+                                                    | P_Fld(ACTblFinal.trp_05T, SHU_AC_TIME_05T_TRP_05T)
+                                                    | P_Fld(ACTblFinal.trcd_05T, SHU_AC_TIME_05T_TRCD_05T)
+                                                    | P_Fld(ACTblFinal.trtp_05T, SHU_AC_TIME_05T_TRTP_05T)
+                                                    | P_Fld(ACTblFinal.txp_05T, SHU_AC_TIME_05T_TXP_05T)
+                                                    | P_Fld(ACTblFinal.trfc_05T, SHU_AC_TIME_05T_TRFC_05T)
+                                                    | P_Fld(ACTblFinal.trfcpb_05T, SHU_AC_TIME_05T_TRFCPB_05T)
+                                                    | P_Fld(ACTblFinal.tpbr2pbr_05T, SHU_AC_TIME_05T_TPBR2PBR_05T)
+                                                    | P_Fld(ACTblFinal.tpbr2act_05T, SHU_AC_TIME_05T_TPBR2ACT_05T)
+                                                    | P_Fld(ACTblFinal.tr2mrw_05T, SHU_AC_TIME_05T_TR2MRW_05T)
+                                                    | P_Fld(ACTblFinal.tw2mrw_05T, SHU_AC_TIME_05T_TW2MRW_05T)
+                                                    | P_Fld(ACTblFinal.tmrr2mrw_05T, SHU_AC_TIME_05T_TMRR2MRW_05T)
+                                                    | P_Fld(ACTblFinal.tmrw_05T, SHU_AC_TIME_05T_TMRW_05T)
+                                                    | P_Fld(ACTblFinal.tmrd_05T, SHU_AC_TIME_05T_TMRD_05T)
+                                                    | P_Fld(ACTblFinal.tmrwckel_05T, SHU_AC_TIME_05T_TMRWCKEL_05T)
+                                                    | P_Fld(ACTblFinal.tmrri_05T, SHU_AC_TIME_05T_TMRRI_05T)
+                                                    | P_Fld(ACTblFinal.trc_05T, SHU_AC_TIME_05T_TRC_05T));
+
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM0, ACTblFinal.twtr, SHU_ACTIM0_TWTR);
+        vIO32WriteFldMulti_All(DRAMC_REG_SHU_CKECTRL, P_Fld(ACTblFinal.tpde, SHU_CKECTRL_TPDE)
+                                                        | P_Fld(ACTblFinal.tpdx, SHU_CKECTRL_TPDX)
+                                                        | P_Fld(ACTblFinal.tpde_05T, SHU_CKECTRL_TPDE_05T)
+                                                        | P_Fld(ACTblFinal.tpdx_05T, SHU_CKECTRL_TPDX_05T));
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM5, ACTblFinal.trtpd, SHU_ACTIM5_TR2PD);
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_TIME_05T, ACTblFinal.trtpd_05T, SHU_AC_TIME_05T_TR2PD_05T);
+    }
+
+#if AC_TIMING_DERATE_ENABLE
+    if (u1IsLP4Family(p->dram_type))
+    {
+        vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING0, P_Fld(ACTblFinal.trcd_derate, SHU_AC_DERATING0_TRCD_DERATE)
+                                                        | P_Fld(ACTblFinal.trrd_derate, SHU_AC_DERATING0_TRRD_DERATE));
+        vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING1, P_Fld(ACTblFinal.trc_derate, SHU_AC_DERATING1_TRC_DERATE)
+                                                        | P_Fld(ACTblFinal.tras_derate, SHU_AC_DERATING1_TRAS_DERATE)
+                                                        | P_Fld(ACTblFinal.trp_derate, SHU_AC_DERATING1_TRP_DERATE)
+                                                        | P_Fld(ACTblFinal.trpab_derate, SHU_AC_DERATING1_TRPAB_DERATE));
+        vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING_05T, P_Fld(ACTblFinal.trrd_derate_05T, SHU_AC_DERATING_05T_TRRD_05T_DERATE)
+                                                        | P_Fld(ACTblFinal.tras_derate_05T, SHU_AC_DERATING_05T_TRAS_05T_DERATE)
+                                                        | P_Fld(ACTblFinal.trpab_derate_05T, SHU_AC_DERATING_05T_TRPAB_05T_DERATE)
+                                                        | P_Fld(ACTblFinal.trp_derate_05T, SHU_AC_DERATING_05T_TRP_05T_DERATE)
+                                                        | P_Fld(ACTblFinal.trcd_derate_05T, SHU_AC_DERATING_05T_TRCD_05T_DERATE)
+                                                        | P_Fld(ACTblFinal.trc_derate_05T, SHU_AC_DERATING_05T_TRC_05T_DERATE));
+        vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL3, 0xc0, REFCTRL3_REF_DERATING_EN);
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_DERATING0, 0x1, SHU_AC_DERATING0_ACDERATEEN); //enable derating for AC timing
+    }
+#endif
+
+    // DQSINCTL related
+    vSetRank(p, RANK_0);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL);// Rank 0 DQSINCTL
+    vSetRank(p, RANK_1);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL);// Rank 1 DQSINCTL
+    vSetRank(p, backup_rank);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_ODTCTRL, ACTblFinal.dqsinctl, MISC_SHU_ODTCTRL_RODT_LAT);
+
+    if (ACTblFinal.dqsinctl >= 2)
+    {
+        u4RankINCTL_ROOT = ACTblFinal.dqsinctl - 2;
+    }
+    else
+    {
+        mcSHOW_ERR_MSG(("u4RankINCTL_ROOT <2, Please check\n"));
+        u4RankINCTL_ROOT = 0;
+    }
+
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(ACTblFinal.dqsinctl, MISC_SHU_RANKCTL_RANKINCTL_PHY)
+                                                       | P_Fld(u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL_ROOT1)
+                                                       | P_Fld(u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL));
+
+#if XRTRTR_NEW_CROSS_RK_MODE
+    u2PHSINCTL = (ACTblFinal.dqsinctl == 0)? 0: (ACTblFinal.dqsinctl - 1);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, u2PHSINCTL, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL);
+#endif
+
+    // DATLAT related, tREFBW
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(u4Datlat, MISC_SHU_RDAT_DATLAT)
+                                            | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL)
+                                            | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
+
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIMING_CONF, u1TREFBW, SHU_ACTIMING_CONF_REFBW_FR);
+
+    // ----Step 3: Perform register writes/calculation for other regs (That aren't in ACTblFinal struct)------------------------------------------------
+#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
+    //Wei-Jen: Ininital setting values are the same, RANKINCTL_RXDLY = RANKINCTL = RANKINCTL_ROOT1
+    //XRTR2R setting will be updated in RxdqsGatingPostProcess
+    u1RANKINCTL = u4IO32ReadFldAlign(DDRPHY_REG_MISC_SHU_RANKCTL, MISC_SHU_RANKCTL_RANKINCTL);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RANKCTL, u1RANKINCTL, MISC_SHU_RANKCTL_RANKINCTL_RXDLY);
+#endif
+
+    //Update releated RG of XRTW2W
+    if (p->frequency <= 800)
+    {
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+        {
+            u1ROOT = 0; u1TXRANKINCTL = 1; u1TXDLY = 2;
+        }
+        else
+        {
+            u1ROOT = 0; u1TXRANKINCTL = 0; u1TXDLY = 1;
+        }
+    }
+    else
+    {
+        u1ROOT = (p->frequency == 1866)? 1: 0;
+        u1TXRANKINCTL = 1; u1TXDLY = 2;
+    }
+    #if TX_OE_EXTEND
+    if (p->frequency >= 1333)
+    {
+        u1TXRANKINCTL += 1;
+        u1TXDLY += 1;
+    }
+    #endif
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(u1ROOT, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)
+                                                | P_Fld(u1TXRANKINCTL, SHU_TX_RANKCTL_TXRANKINCTL)
+                                                | P_Fld(u1TXDLY, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY));
+
+    return DRAM_OK;
+}
+
+
+DRAM_STATUS_T DdrUpdateACTiming(DRAMC_CTX_T *p)
+{
+    U8 u1TimingIdx = 0;
+
+    mcSHOW_DBG_MSG4(("[UpdateACTiming]\n"));
+
+    //Retrieve ACTimingTable's corresponding index
+    u1TimingIdx = u1GetACTimingIdx(p);
+
+
+    if (u1TimingIdx == 0xff)
+    {
+        #if 0
+        if (u1TmpDramType = TYPE_LPDDR4)
+            u1TimingIdx = 0;
+        else // LPDDR3
+            u1TimingIdx = 6;
+        mcSHOW_ERR_MSG(("Error, no match AC timing, use default timing %d\n", u1TimingIdx));
+        #else
+        mcSHOW_ERR_MSG(("Error, no match AC timing, not apply table\n"));
+        return DRAM_FAIL;
+        #endif
+    }
+
+    //Set ACTiming registers
+#if (__LP5_COMBO__ == TRUE)
+    if (TRUE == is_lp5_family(p))
+    {
+        DdrUpdateACTimingReg_LP5(p, &ACTimingTbl_LP5[u1TimingIdx]);
+    }
+    else
+#endif
+    {
+        DdrUpdateACTimingReg_LP4(p, &ACTimingTbl_LP4[u1TimingIdx]);
+    }
+
+    return DRAM_OK;
+}
+#if 0
+#if ((!SW_CHANGE_FOR_SIMULATION) && (!FOR_DV_SIMULATION_USED && SW_CHANGE_FOR_SIMULATION == 0) && (!__ETT__))
+DRAM_STATUS_T DdrUpdateACTiming_EMI(DRAMC_CTX_T *p, AC_TIMING_EXTERNAL_T *ACRegFromEmi)
+{
+    U8 u1TimingIdx = 0;
+    #if (__LP5_COMBO__ == TRUE)
+    ACTime_T_LP5 ACTime_LP5;
+    #endif
+    ACTime_T_LP4 ACTime_LP4;
+    mcSHOW_DBG_MSG3(("[DdrUpdateACTiming_EMI]\n"));
+
+   if (ACRegFromEmi == NULL)
+        return DRAM_FAIL;
+
+    //Retrieve ACTimingTable's corresponding index
+    u1TimingIdx = u1GetACTimingIdx(p);
+#if (__LP5_COMBO__ == TRUE)
+    if (TRUE == is_lp5_family(p))
+    {
+        ACTime_LP5 = ACTimingTbl_LP5[u1TimingIdx];
+    }
+#endif
+    ACTime_LP4 = ACTimingTbl_LP4[u1TimingIdx];
+
+    //Overwrite AC timing from emi settings
+    ACTime.dramType = p->dram_type;
+#if 1 // Will use MDL ac timing, Others from internal ac timing
+    ACTime.trp = ACRegFromEmi->AC_TIME_EMI_TRP;
+    ACTime.trpab = ACRegFromEmi->AC_TIME_EMI_TRPAB;
+    ACTime.trc = ACRegFromEmi->AC_TIME_EMI_TRC;
+    ACTime.trcd = ACRegFromEmi->AC_TIME_EMI_TRCD;
+
+    ACTime.trp_05T = ACRegFromEmi->AC_TIME_EMI_TRP_05T;
+    ACTime.trpab_05T = ACRegFromEmi->AC_TIME_EMI_TRPAB_05T;
+    ACTime.trc_05T = ACRegFromEmi->AC_TIME_EMI_TRC_05T;
+    ACTime.trcd_05T = ACRegFromEmi->AC_TIME_EMI_TRCD_05T;
+#else
+    ACTime.freq = ACRegFromEmi->AC_TIME_EMI_FREQUENCY;
+    ACTime.tras = ACRegFromEmi->AC_TIME_EMI_TRAS;
+    ACTime.trp = ACRegFromEmi->AC_TIME_EMI_TRP;
+
+    ACTime.trpab = ACRegFromEmi->AC_TIME_EMI_TRPAB;
+    ACTime.trc = ACRegFromEmi->AC_TIME_EMI_TRC;
+    ACTime.trfc = ACRegFromEmi->AC_TIME_EMI_TRFC;
+    ACTime.trfcpb = ACRegFromEmi->AC_TIME_EMI_TRFCPB;
+
+    ACTime.txp = ACRegFromEmi->AC_TIME_EMI_TXP;
+    ACTime.trtp = ACRegFromEmi->AC_TIME_EMI_TRTP;
+    ACTime.trcd = ACRegFromEmi->AC_TIME_EMI_TRCD;
+    ACTime.twr = ACRegFromEmi->AC_TIME_EMI_TWR;
+
+    ACTime.twtr = ACRegFromEmi->AC_TIME_EMI_TWTR;
+    ACTime.trrd = ACRegFromEmi->AC_TIME_EMI_TRRD;
+    ACTime.tfaw = ACRegFromEmi->AC_TIME_EMI_TFAW;
+    ACTime.trtw_ODT_off = ACRegFromEmi->AC_TIME_EMI_TRTW_ODT_OFF;
+    ACTime.trtw_ODT_on = ACRegFromEmi->AC_TIME_EMI_TRTW_ODT_ON;
+
+    ACTime.refcnt = ACRegFromEmi->AC_TIME_EMI_REFCNT; //(REFFRERUN = 0)
+    ACTime.refcnt_fr_clk = ACRegFromEmi->AC_TIME_EMI_REFCNT_FR_CLK; //(REFFRERUN = 1)
+    ACTime.txrefcnt = ACRegFromEmi->AC_TIME_EMI_TXREFCNT;
+    ACTime.tzqcs = ACRegFromEmi->AC_TIME_EMI_TZQCS;
+
+    ACTime.trtpd = ACRegFromEmi->AC_TIME_EMI_TRTPD;
+    ACTime.twtpd = ACRegFromEmi->AC_TIME_EMI_TWTPD;
+    ACTime.tmrr2w_ODT_off = ACRegFromEmi->AC_TIME_EMI_TMRR2W_ODT_OFF;
+    ACTime.tmrr2w_ODT_on = ACRegFromEmi->AC_TIME_EMI_TMRR2W_ODT_ON;
+
+    ACTime.tras_05T = ACRegFromEmi->AC_TIME_EMI_TRAS_05T;
+    ACTime.trp_05T = ACRegFromEmi->AC_TIME_EMI_TRP_05T;
+    ACTime.trpab_05T = ACRegFromEmi->AC_TIME_EMI_TRPAB_05T;
+    ACTime.trc_05T = ACRegFromEmi->AC_TIME_EMI_TRC_05T;
+    ACTime.trfc_05T = ACRegFromEmi->AC_TIME_EMI_TRFC_05T;
+    ACTime.trfcpb_05T = ACRegFromEmi->AC_TIME_EMI_TRFCPB_05T;
+    ACTime.txp_05T = ACRegFromEmi->AC_TIME_EMI_TXP_05T;
+    ACTime.trtp_05T = ACRegFromEmi->AC_TIME_EMI_TRTP_05T;
+    ACTime.trcd_05T = ACRegFromEmi->AC_TIME_EMI_TRCD_05T;
+    ACTime.twr_05T = ACRegFromEmi->AC_TIME_EMI_TWR_05T;
+    ACTime.twtr_05T = ACRegFromEmi->AC_TIME_EMI_TWTR_05T;
+    ACTime.trrd_05T = ACRegFromEmi->AC_TIME_EMI_TRRD_05T;
+    ACTime.tfaw_05T = ACRegFromEmi->AC_TIME_EMI_TFAW_05T;
+    ACTime.trtw_ODT_off_05T = ACRegFromEmi->AC_TIME_EMI_TRTW_ODT_OFF_05T;
+    ACTime.trtw_ODT_on_05T = ACRegFromEmi->AC_TIME_EMI_TRTW_ODT_ON_05T;
+    ACTime.trtpd_05T = ACRegFromEmi->AC_TIME_EMI_TRTPD_05T;
+    ACTime.twtpd_05T = ACRegFromEmi->AC_TIME_EMI_TWTPD_05T;
+#endif
+
+    //Set ACTiming registers
+    DdrUpdateACTimingReg(p, &ACTime);
+
+    return DRAM_OK;
+}
+#endif
+#endif
+///TODO: wait for porting +++
+#if __A60868_TO_BE_PORTING__
+
+U8 vDramcACTimingGetDatLat(DRAMC_CTX_T *p)
+{
+    U8 u1TimingIdx = u1GetACTimingIdx(p);
+#if (__LP5_COMBO__ == TRUE)
+    ACTime_T_LP5 ACTime = ACTimingTbl_LP5[u1TimingIdx];
+#else
+    ACTime_T_LP4 ACTime = ACTimingTbl_LP4[u1TimingIdx];
+#endif
+
+    return ACTime.datlat;
+}
+#endif // __A60868_TO_BE_PORTING__
+///TODO: wait for porting +++
+
+/* Optimize all-bank refresh parameters (by density) for LP4 */
+void vDramcACTimingOptimize(DRAMC_CTX_T *p)
+{
+    /* TRFC: tRFCab
+     *       Refresh Cycle Time (All Banks)
+     * TXREFCNT: tXSR max((tRFCab + 7.5ns), 2nCK)
+     *           Min self refresh time (Entry to Exit)
+     * u1ExecuteOptimize: Indicate if ACTimings are updated at the end of this function
+     */
+    U8 u1RFCabGrpIdx = 0, u1FreqGrpIdx = 0, u1ExecuteOptimize = ENABLE;
+    U8 u1TRFC=101, u1TRFC_05T=0, u1TRFCpb=44, u1TRFCpb_05T=0,u1TXREFCNT=118;
+    typedef struct
+    {   /* Bitfield sizes set to current project register field's size */
+        U8 u1TRFC      : 8;
+        U8 u1TRFRC_05T : 1;
+        U8 u1TRFCpb      : 8;
+        U8 u1TRFRCpb_05T : 1;
+        U16 u2TXREFCNT : 10;
+    } optimizeACTime;
+    /* JESD209-4B: tRFCab has 4 settings for 7 density settings (130, 180, 280, 380)
+     * tRFCAB_NUM: Used to indicate tRFCab group (since some densities share the same tRFCab)
+     */
+    enum tRFCABIdx{tRFCAB_130 = 0, tRFCAB_180, tRFCAB_280, tRFCAB_380, tRFCAB_NUM};
+    enum ACTimeIdx{GRP_DDR1200_ACTIM, GRP_DDR1600_ACTIM, GRP_DDR1866_ACTIM, GRP_DDR2400_ACTIM, GRP_DDR2667_ACTIM, GRP_DDR3200_ACTIM, GRP_DDR3733_ACTIM, GRP_DDR4266_ACTIM, GRP_ACTIM_NUM};
+    enum ACTimeIdxDiv4{
+#if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
+        GRP_DDR400_DIV4_ACTIM = 0,
+#endif
+        GRP_DDR800_DIV4_ACTIM, GRP_DDR1200_DIV4_ACTIM, GRP_DDR1600_DIV4_ACTIM, GRP_ACTIM_NUM_DIV4};
+    /* Values retrieved from 1. Alaska ACTiming excel file 2. JESD209-4B Refresh requirement table */
+
+    optimizeACTime *ptRFCab_Opt;
+
+    optimizeACTime tRFCab_Opt [GRP_ACTIM_NUM][tRFCAB_NUM] =
+    {
+        //For freqGroup DDR1200
+        {{.u1TRFC = 8, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 21}, //tRFCab = 130, tRFCpb = 60, @Robert Not enough to Optimize
+         {.u1TRFC = 15, .u1TRFRC_05T = 1, .u1TRFCpb = 2, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 29}, //tRFCab = 180, tRFCpb = 90
+         {.u1TRFC = 30, .u1TRFRC_05T = 1, .u1TRFCpb = 9, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 44}, //tRFCab = 280, tRFCpb = 140
+         {.u1TRFC = 45, .u1TRFRC_05T = 1, .u1TRFCpb = 17, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 59}},//tRFCab = 380, tRFCpb = 190
+        //For freqGroup DDR1600
+        {{.u1TRFC = 14, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 28}, //tRFCab = 130, tRFCpb = 60
+         {.u1TRFC = 24, .u1TRFRC_05T = 0, .u1TRFCpb = 6, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 38}, //tRFCab = 180, tRFCpb = 90
+         {.u1TRFC = 44, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 58}, //tRFCab = 280, tRFCpb = 140
+         {.u1TRFC = 64, .u1TRFRC_05T = 0, .u1TRFCpb = 26, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 78}},//tRFCab = 380, tRFCpb = 190
+        //For freqGroup DDR1866
+        {{.u1TRFC = 18, .u1TRFRC_05T = 1, .u1TRFCpb = 2, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 33}, //tRFCab = 130, tRFCpb = 60
+         {.u1TRFC = 30, .u1TRFRC_05T = 0, .u1TRFCpb = 9, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 44}, //tRFCab = 180, tRFCpb = 90
+         {.u1TRFC = 53, .u1TRFRC_05T = 1, .u1TRFCpb = 21, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 68}, //tRFCab = 280, tRFCpb = 140
+         {.u1TRFC = 77, .u1TRFRC_05T = 0, .u1TRFCpb = 32, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 91}},//tRFCab = 380, tRFCpb = 190
+        //For freqGroup DDR2400
+        {{.u1TRFC = 27, .u1TRFRC_05T = 1,  .u1TRFCpb = 6, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 42},   //tRFCab = 130, tRFCpb = 60
+         {.u1TRFC = 42, .u1TRFRC_05T = 1,  .u1TRFCpb = 15, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 57},   //tRFCab = 180, tRFCpb = 90
+         {.u1TRFC = 72, .u1TRFRC_05T = 1,  .u1TRFCpb = 30, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 87},   //tRFCab = 280, tRFCpb = 140
+         {.u1TRFC = 102, .u1TRFRC_05T = 1,  .u1TRFCpb = 45, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 117}},//tRFCab = 380, tRFCpb = 190
+        //For freqGroup DDR2667
+        {{.u1TRFC = 31, .u1TRFRC_05T = 1,  .u1TRFCpb = 8, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 46},    //tRFCab = 130, tRFCpb = 60
+         {.u1TRFC = 48, .u1TRFRC_05T = 1,  .u1TRFCpb = 18, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 63},    //tRFCab = 180, tRFCpb = 90
+         {.u1TRFC = 81, .u1TRFRC_05T = 1,  .u1TRFCpb = 35, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 96},   //tRFCab = 280, tRFCpb = 140
+         {.u1TRFC = 115, .u1TRFRC_05T = 0,  .u1TRFCpb = 51, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 130}}, //tRFCab = 380, tRFCpb = 190
+        //For freqGroup DDR3200
+       {{.u1TRFC = 40, .u1TRFRC_05T = 0,  .u1TRFCpb = 12, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 55},    //tRFCab = 130, tRFCpb = 60
+         {.u1TRFC = 60, .u1TRFRC_05T = 0,  .u1TRFCpb = 24, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 75},    //tRFCab = 180, tRFCpb = 90
+         {.u1TRFC = 100, .u1TRFRC_05T = 0, .u1TRFCpb = 44, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 115},   //tRFCab = 280, tRFCpb = 140
+         {.u1TRFC = 140, .u1TRFRC_05T = 0, .u1TRFCpb = 64, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 155}}, //tRFCab = 380, tRFCpb = 190
+        //For freqGroup DDR3733
+        {{.u1TRFC = 49, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 65},    //tRFCab = 130, tRFCpb = 60
+         {.u1TRFC = 72, .u1TRFRC_05T = 0, .u1TRFCpb = 30, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 88},    //tRFCab = 180, tRFCpb = 90
+         {.u1TRFC = 119, .u1TRFRC_05T = 0, .u1TRFCpb = 53, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 135},  //tRFCab = 280, tRFCpb = 140
+         {.u1TRFC = 165, .u1TRFRC_05T = 1, .u1TRFCpb = 77, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 181}}, //tRFCab = 380, tRFCpb = 190
+        //For freqGroup DDR4266
+        {{.u1TRFC = 57, .u1TRFRC_05T = 1, .u1TRFCpb = 20, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 74},    //tRFCab = 130, tRFCpb = 60
+         {.u1TRFC = 84, .u1TRFRC_05T = 0, .u1TRFCpb = 36, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 100},    //tRFCab = 180, tRFCpb = 90
+         {.u1TRFC = 137, .u1TRFRC_05T = 1, .u1TRFCpb = 63, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 154},  //tRFCab = 280, tRFCpb = 140
+         {.u1TRFC = 191, .u1TRFRC_05T = 0, .u1TRFCpb = 89, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 207}} //tRFCab = 380, tRFCpb = 190
+    };
+
+    optimizeACTime tRFCab_Opt_Div4 [GRP_ACTIM_NUM_DIV4][tRFCAB_NUM] =
+    {
+#if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
+        // @ tg add for DDR400
+        {{.u1TRFC = 1,  .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 14}, //tRFCab = 130, tRFCpb = 60
+         {.u1TRFC = 6,  .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 19}, //tRFCab = 180, tRFCpb = 90
+         {.u1TRFC = 16, .u1TRFRC_05T = 0, .u1TRFCpb = 2, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 29}, //tRFCab = 280, tRFCpb = 140
+         {.u1TRFC = 26, .u1TRFRC_05T = 0, .u1TRFCpb = 7, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 39}},//tRFCab = 380, tRFCpb = 190
+#endif
+        //NOTE: @Darren, For freqGroup DDR816
+        {{.u1TRFC = 14, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 28}, //tRFCab = 130, tRFCpb = 60
+         {.u1TRFC = 24, .u1TRFRC_05T = 0, .u1TRFCpb = 6, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 38}, //tRFCab = 180, tRFCpb = 90
+         {.u1TRFC = 44, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 58}, //tRFCab = 280, tRFCpb = 140
+         {.u1TRFC = 64, .u1TRFRC_05T = 0, .u1TRFCpb = 26, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 78}},//tRFCab = 380, tRFCpb = 190
+        //For freqGroup DDR1200
+        {{.u1TRFC = 28, .u1TRFRC_05T = 0,  .u1TRFCpb = 7, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 42},   //tRFCab = 130, tRFCpb = 60
+         {.u1TRFC = 43, .u1TRFRC_05T = 0,  .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 57},   //tRFCab = 180, tRFCpb = 90
+         {.u1TRFC = 73, .u1TRFRC_05T = 0,  .u1TRFCpb = 31, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 87},   //tRFCab = 280, tRFCpb = 140
+         {.u1TRFC = 103, .u1TRFRC_05T = 0,  .u1TRFCpb = 46, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 117}},//tRFCab = 380, tRFCpb = 190
+        //For freqGroup DDR1600
+       {{.u1TRFC = 40, .u1TRFRC_05T = 0,  .u1TRFCpb = 12, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 55},    //tRFCab = 130, tRFCpb = 60
+         {.u1TRFC = 60, .u1TRFRC_05T = 0,  .u1TRFCpb = 24, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 75},    //tRFCab = 180, tRFCpb = 90
+         {.u1TRFC = 100, .u1TRFRC_05T = 0, .u1TRFCpb = 44, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 115},   //tRFCab = 280, tRFCpb = 140
+         {.u1TRFC = 140, .u1TRFRC_05T = 0, .u1TRFCpb = 64, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 155}}, //tRFCab = 380, tRFCpb = 190
+    };
+
+
+    mcSHOW_DBG_MSG2(("[ACTimingOptimize]"));
+
+#if __ETT__
+    if (p->density==0xff)
+    {
+        mcSHOW_ERR_MSG(("Error : No call MR8 to get density!!\n"));
+        while(1);
+    }
+#endif
+    /* Set tRFCab group idx p->density = MR8 OP[5:2]*/
+    switch (p->density)
+    {
+        case 0x0:   //4Gb per die  (2Gb per channel),  tRFCab=130
+            u1RFCabGrpIdx = tRFCAB_130;
+            break;
+        case 0x1:   //6Gb per die  (3Gb per channel),  tRFCab=180
+        case 0x2:   //8Gb per die  (4Gb per channel),  tRFCab=180
+            u1RFCabGrpIdx = tRFCAB_180;
+            break;
+        case 0x3:   //12Gb per die (6Gb per channel),  tRFCab=280
+        case 0x4:   //16Gb per die (8Gb per channel),  tRFCab=280
+            u1RFCabGrpIdx = tRFCAB_280;
+            break;
+        case 0x5:   //24Gb per die (12Gb per channel), tRFCab=380
+        case 0x6:   //32Gb per die (16Gb per channel), tRFCab=380
+            u1RFCabGrpIdx = tRFCAB_380;
+            break;
+        default:
+            u1ExecuteOptimize = DISABLE;
+            mcSHOW_ERR_MSG(("MR8 density err!\n"));
+    }
+    /* Set freqGroup Idx */
+    switch (p->freqGroup)
+    {
+#if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
+        case 200:
+            if (vGet_Div_Mode(p) == DIV4_MODE)
+            {
+                u1FreqGrpIdx = GRP_DDR400_DIV4_ACTIM;
+            }
+            else
+            {
+                u1ExecuteOptimize = DISABLE;
+                mcSHOW_ERR_MSG(("freqGroup err!\n"));
+                #if __ETT__
+                while(1);
+                #endif
+            }
+            break;
+#endif
+        case 400:
+            if (vGet_Div_Mode(p) == DIV4_MODE)
+                u1FreqGrpIdx = GRP_DDR800_DIV4_ACTIM;
+            else
+            {
+                u1ExecuteOptimize = DISABLE;
+                mcSHOW_ERR_MSG(("freqGroup err!\n"));
+                #if __ETT__
+                while(1);
+                #endif
+            }
+            break;
+        case 600:
+            if (vGet_Div_Mode(p) == DIV4_MODE)
+                u1FreqGrpIdx = GRP_DDR1200_DIV4_ACTIM;
+            else
+                u1FreqGrpIdx = GRP_DDR1200_ACTIM;
+            break;
+        case 800:
+            if (vGet_Div_Mode(p) == DIV4_MODE)
+                u1FreqGrpIdx = GRP_DDR1600_DIV4_ACTIM;
+            else
+                u1FreqGrpIdx = GRP_DDR1600_ACTIM;
+            break;
+        case 933:
+            u1FreqGrpIdx = GRP_DDR1866_ACTIM;
+            break;
+        case 1200:
+            u1FreqGrpIdx = GRP_DDR2400_ACTIM;
+            break;
+        case 1333:
+            u1FreqGrpIdx = GRP_DDR2667_ACTIM;
+            break;
+        case 1600:
+            u1FreqGrpIdx = GRP_DDR3200_ACTIM;
+            break;
+        case 1866:
+            u1FreqGrpIdx = GRP_DDR3733_ACTIM;
+            break;
+        case 2133:
+            u1FreqGrpIdx = GRP_DDR4266_ACTIM;
+            break;
+        default:
+            u1ExecuteOptimize = DISABLE;
+            mcSHOW_ERR_MSG(("freqGroup err!\n"));
+            #if __ETT__
+            while(1);
+            #endif
+    }
+
+    if (vGet_Div_Mode(p) == DIV4_MODE && u1FreqGrpIdx >= GRP_ACTIM_NUM_DIV4)
+    {
+            u1ExecuteOptimize = DISABLE;
+            mcSHOW_ERR_MSG(("freqGroup err!\n"));
+            #if __ETT__
+            while(1);
+            #endif
+    }
+    if (vGet_Div_Mode(p) == DIV4_MODE && u1FreqGrpIdx < GRP_ACTIM_NUM_DIV4)
+        ptRFCab_Opt = &tRFCab_Opt_Div4[u1FreqGrpIdx][0];
+    else
+        ptRFCab_Opt = &tRFCab_Opt[u1FreqGrpIdx][0];
+
+    u1TRFC = ptRFCab_Opt[u1RFCabGrpIdx].u1TRFC;
+    u1TRFC_05T = ptRFCab_Opt[u1RFCabGrpIdx].u1TRFRC_05T;
+    u1TRFCpb = ptRFCab_Opt[u1RFCabGrpIdx].u1TRFCpb;
+    u1TRFCpb_05T = ptRFCab_Opt[u1RFCabGrpIdx].u1TRFRCpb_05T;
+    u1TXREFCNT = ptRFCab_Opt[u1RFCabGrpIdx].u2TXREFCNT;
+
+    /* Only execute ACTimingOptimize(write to regs) when corresponding values have been found */
+    if (u1ExecuteOptimize == ENABLE)
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM3, u1TRFC, SHU_ACTIM3_TRFC);
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_TIME_05T, u1TRFC_05T, SHU_AC_TIME_05T_TRFC_05T);
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM4, u1TXREFCNT, SHU_ACTIM4_TXREFCNT);
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM3, u1TRFCpb, SHU_ACTIM3_TRFCPB);
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_TIME_05T, u1TRFCpb_05T, SHU_AC_TIME_05T_TRFCPB_05T);
+
+        mcSHOW_DBG_MSG2(("Density (MR8 OP[5:2]) %u, TRFC %u, TRFC_05T %u, TXREFCNT %u, TRFCpb %u, TRFCpb_05T %u\n", p->density, u1TRFC, u1TRFC_05T, u1TXREFCNT, u1TRFCpb, u1TRFCpb_05T));
+    }
+
+    return;
+}
+
+/* ACTimingTbl: All freq's ACTiming from ACTiming excel file
+ * (Some fields don't exist for LP3 -> set to 0)
+ * Note: !!All ACTiming adjustments should not be set in-table should be moved into UpdateACTimingReg()!!
+ *       Or else preloader's highest freq ACTimings may be set to different values than expected.
+ */
+static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = {
+    //----------LPDDR4---------------------------
+#if SUPPORT_LP4_DDR4266_ACTIM
+    //LP4_DDR4266 ACTiming---------------------------------
+#if (ENABLE_READ_DBI == 1)
+//LPDDR4 4X_4266_Div 8_DBI1.csv Read 1
+{
+    .dramType = TYPE_LPDDR4, .freq = 2133, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1,
+    .readLat = 40,  .writeLat =  18,    .DivMode =  DIV8_MODE,
+
+    .tras = 14, .tras_05T = 0,
+    .trp = 8,   .trp_05T = 1,
+    .trpab = 10,    .trpab_05T = 0,
+    .trc = 23,  .trc_05T = 0,
+    .trfc = 137,    .trfc_05T = 1,
+    .trfcpb = 63,   .trfcpb_05T = 0,
+    .txp = 1,   .txp_05T = 0,
+    .trtp = 2,  .trtp_05T = 1,
+    .trcd = 10, .trcd_05T = 0,
+    .twr = 15,  .twr_05T = 0,
+    .twtr = 10, .twtr_05T = 1,
+    .tpbr2pbr = 41, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 18,   .tr2mrw_05T = 0,
+    .tw2mrw = 11,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 15, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 8,  .tmrd_05T = 0,
+    .tmrwckel = 9,  .tmrwckel_05T = 0,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 14,    .tmrri_05T = 0,
+    .trrd = 4,  .trrd_05T = 1,
+    .trrd_4266 = 3, .trrd_4266_05T = 0,
+    .tfaw = 13, .tfaw_05T = 1,
+    .tfaw_4266 = 8, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 7,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 9,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 154,
+    .tzqcs = 46,
+    .xrtw2w_new_mode = 5,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 1,
+    .xrtw2r_odt_off = 1,
+    .xrtr2w_odt_on = 8,
+    .xrtr2w_odt_off = 8,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 7,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 54,
+    .hwset_mr2_op = 63,
+    .hwset_mr13_op = 216,
+    .hwset_vrcg_op = 208,
+    .trcd_derate = 11,  .trcd_derate_05T = 0,
+    .trc_derate = 26,   .trc_derate_05T = 0,
+    .tras_derate = 15,  .tras_derate_05T = 0,
+    .trpab_derate = 11, .trpab_derate_05T = 0,
+    .trp_derate = 9,    .trp_derate_05T = 1,
+    .trrd_derate = 5,   .trrd_derate_05T = 1,
+    .trtpd = 15,    .trtpd_05T = 1,
+    .twtpd = 18,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 11,
+    .tmrr2w_odt_on = 13,
+    .ckeprd = 3,
+    .ckelckcnt = 3,
+    .zqlat2 = 16,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 7,   .datlat = 18
+},
+//LPDDR4 4X_4266_BT_Div 8_DBI1.csv Read 1
+{
+    .dramType = TYPE_LPDDR4, .freq = 2133, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1,
+    .readLat = 44,  .writeLat =  18,    .DivMode =  DIV8_MODE,
+
+    .tras = 14, .tras_05T = 0,
+    .trp = 8,   .trp_05T = 1,
+    .trpab = 10,    .trpab_05T = 0,
+    .trc = 23,  .trc_05T = 0,
+    .trfc = 137,    .trfc_05T = 1,
+    .trfcpb = 63,   .trfcpb_05T = 0,
+    .txp = 1,   .txp_05T = 0,
+    .trtp = 2,  .trtp_05T = 1,
+    .trcd = 10, .trcd_05T = 0,
+    .twr = 16,  .twr_05T = 0,
+    .twtr = 11, .twtr_05T = 1,
+    .tpbr2pbr = 41, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 19,   .tr2mrw_05T = 0,
+    .tw2mrw = 11,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 16, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 8,  .tmrd_05T = 0,
+    .tmrwckel = 9,  .tmrwckel_05T = 0,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 14,    .tmrri_05T = 0,
+    .trrd = 4,  .trrd_05T = 1,
+    .trrd_4266 = 3, .trrd_4266_05T = 0,
+    .tfaw = 13, .tfaw_05T = 1,
+    .tfaw_4266 = 8, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 8,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 10,  .trtw_odt_on_05T = 0,
+    .txrefcnt = 154,
+    .tzqcs = 46,
+    .xrtw2w_new_mode = 5,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 1,
+    .xrtw2r_odt_off = 1,
+    .xrtr2w_odt_on = 9,
+    .xrtr2w_odt_off = 9,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 7,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 54,
+    .hwset_mr2_op = 63,
+    .hwset_mr13_op = 216,
+    .hwset_vrcg_op = 208,
+    .trcd_derate = 11,  .trcd_derate_05T = 0,
+    .trc_derate = 26,   .trc_derate_05T = 0,
+    .tras_derate = 15,  .tras_derate_05T = 0,
+    .trpab_derate = 11, .trpab_derate_05T = 0,
+    .trp_derate = 9,    .trp_derate_05T = 1,
+    .trrd_derate = 5,   .trrd_derate_05T = 1,
+    .trtpd = 16,    .trtpd_05T = 1,
+    .twtpd = 19,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 12,
+    .tmrr2w_odt_on = 14,
+    .ckeprd = 3,
+    .ckelckcnt = 3,
+    .zqlat2 = 16,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 7,   .datlat = 18
+},
+#else  //ENABLE_READ_DBI == 0)
+//LPDDR4 4X_4266_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 2133, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    .readLat = 36,  .writeLat =  18,    .DivMode =  DIV8_MODE,
+
+    .tras = 14, .tras_05T = 0,
+    .trp = 8,   .trp_05T = 1,
+    .trpab = 10,    .trpab_05T = 0,
+    .trc = 23,  .trc_05T = 0,
+    .trfc = 137,    .trfc_05T = 1,
+    .trfcpb = 63,   .trfcpb_05T = 0,
+    .txp = 1,   .txp_05T = 0,
+    .trtp = 2,  .trtp_05T = 1,
+    .trcd = 10, .trcd_05T = 0,
+    .twr = 15,  .twr_05T = 0,
+    .twtr = 10, .twtr_05T = 1,
+    .tpbr2pbr = 41, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 17,   .tr2mrw_05T = 0,
+    .tw2mrw = 11,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 14, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 8,  .tmrd_05T = 0,
+    .tmrwckel = 9,  .tmrwckel_05T = 0,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 14,    .tmrri_05T = 0,
+    .trrd = 4,  .trrd_05T = 1,
+    .trrd_4266 = 3, .trrd_4266_05T = 0,
+    .tfaw = 13, .tfaw_05T = 1,
+    .tfaw_4266 = 8, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 6,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 8,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 154,
+    .tzqcs = 46,
+    .xrtw2w_new_mode = 5,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 1,
+    .xrtw2r_odt_off = 1,
+    .xrtr2w_odt_on = 7,
+    .xrtr2w_odt_off = 7,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 7,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 54,
+    .hwset_mr2_op = 63,
+    .hwset_mr13_op = 216,
+    .hwset_vrcg_op = 208,
+    .trcd_derate = 11,  .trcd_derate_05T = 0,
+    .trc_derate = 26,   .trc_derate_05T = 0,
+    .tras_derate = 15,  .tras_derate_05T = 0,
+    .trpab_derate = 11, .trpab_derate_05T = 0,
+    .trp_derate = 9,    .trp_derate_05T = 1,
+    .trrd_derate = 5,   .trrd_derate_05T = 1,
+    .trtpd = 14,    .trtpd_05T = 1,
+    .twtpd = 18,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 10,
+    .tmrr2w_odt_on = 12,
+    .ckeprd = 3,
+    .ckelckcnt = 3,
+    .zqlat2 = 16,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 7,   .datlat = 18
+},
+//LPDDR4 4X_4266_BT_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 2133, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    .readLat = 40,  .writeLat =  18,    .DivMode =  DIV8_MODE,
+
+    .tras = 14, .tras_05T = 0,
+    .trp = 8,   .trp_05T = 1,
+    .trpab = 10,    .trpab_05T = 0,
+    .trc = 23,  .trc_05T = 0,
+    .trfc = 137,    .trfc_05T = 1,
+    .trfcpb = 63,   .trfcpb_05T = 0,
+    .txp = 1,   .txp_05T = 0,
+    .trtp = 2,  .trtp_05T = 1,
+    .trcd = 10, .trcd_05T = 0,
+    .twr = 16,  .twr_05T = 0,
+    .twtr = 11, .twtr_05T = 1,
+    .tpbr2pbr = 41, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 18,   .tr2mrw_05T = 0,
+    .tw2mrw = 11,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 15, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 8,  .tmrd_05T = 0,
+    .tmrwckel = 9,  .tmrwckel_05T = 0,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 14,    .tmrri_05T = 0,
+    .trrd = 4,  .trrd_05T = 1,
+    .trrd_4266 = 3, .trrd_4266_05T = 0,
+    .tfaw = 13, .tfaw_05T = 1,
+    .tfaw_4266 = 8, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 7,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 9,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 154,
+    .tzqcs = 46,
+    .xrtw2w_new_mode = 5,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 1,
+    .xrtw2r_odt_off = 1,
+    .xrtr2w_odt_on = 8,
+    .xrtr2w_odt_off = 8,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 7,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 54,
+    .hwset_mr2_op = 63,
+    .hwset_mr13_op = 216,
+    .hwset_vrcg_op = 208,
+    .trcd_derate = 11,  .trcd_derate_05T = 0,
+    .trc_derate = 26,   .trc_derate_05T = 0,
+    .tras_derate = 15,  .tras_derate_05T = 0,
+    .trpab_derate = 11, .trpab_derate_05T = 0,
+    .trp_derate = 9,    .trp_derate_05T = 1,
+    .trrd_derate = 5,   .trrd_derate_05T = 1,
+    .trtpd = 15,    .trtpd_05T = 1,
+    .twtpd = 19,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 11,
+    .tmrr2w_odt_on = 13,
+    .ckeprd = 3,
+    .ckelckcnt = 3,
+    .zqlat2 = 16,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 7,   .datlat = 18
+},
+#endif
+#endif
+#if SUPPORT_LP4_DDR3733_ACTIM
+    //LP4_DDR3733 ACTiming---------------------------------
+#if (ENABLE_READ_DBI == 1)
+//LPDDR4 4X_3733_Div 8_DBI1.csv Read 1
+{
+    .dramType = TYPE_LPDDR4, .freq = 1866, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1,
+    .readLat = 36,  .writeLat =  16,    .DivMode =  DIV8_MODE,
+
+    .tras = 11, .tras_05T = 1,
+    .trp = 7,   .trp_05T = 0,
+    .trpab = 8, .trpab_05T = 1,
+    .trc = 19,  .trc_05T = 0,
+    .trfc = 119,    .trfc_05T = 0,
+    .trfcpb = 53,   .trfcpb_05T = 1,
+    .txp = 0,   .txp_05T = 1,
+    .trtp = 2,  .trtp_05T = 0,
+    .trcd = 8,  .trcd_05T = 1,
+    .twr = 13,  .twr_05T = 1,
+    .twtr = 8,  .twtr_05T = 0,
+    .tpbr2pbr = 35, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 16,   .tr2mrw_05T = 1,
+    .tw2mrw = 10,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 13, .tmrr2mrw_05T = 1,
+    .tmrw = 5,  .tmrw_05T = 1,
+    .tmrd = 7,  .tmrd_05T = 1,
+    .tmrwckel = 8,  .tmrwckel_05T = 1,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 12,    .tmrri_05T = 0,
+    .trrd = 4,  .trrd_05T = 0,
+    .trrd_4266 = 2, .trrd_4266_05T = 1,
+    .tfaw = 11, .tfaw_05T = 0,
+    .tfaw_4266 = 6, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 6,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 9,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 135,
+    .tzqcs = 40,
+    .xrtw2w_new_mode = 5,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 1,
+    .xrtw2r_odt_off = 1,
+    .xrtr2w_odt_on = 8,
+    .xrtr2w_odt_off = 8,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 7,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 47,
+    .hwset_mr2_op = 54,
+    .hwset_mr13_op = 216,
+    .hwset_vrcg_op = 208,
+    .trcd_derate = 9,   .trcd_derate_05T = 1,
+    .trc_derate = 21,   .trc_derate_05T = 1,
+    .tras_derate = 12,  .tras_derate_05T = 0,
+    .trpab_derate = 9,  .trpab_derate_05T = 1,
+    .trp_derate = 8,    .trp_derate_05T = 0,
+    .trrd_derate = 5,   .trrd_derate_05T = 0,
+    .trtpd = 14,    .trtpd_05T = 0,
+    .twtpd = 16,    .twtpd_05T = 1,
+    .tmrr2w_odt_off = 10,
+    .tmrr2w_odt_on = 12,
+    .ckeprd = 3,
+    .ckelckcnt = 3,
+    .zqlat2 = 14,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 6,   .datlat = 16
+},
+//LPDDR4 4X_3733_BT_Div 8_DBI1.csv Read 1
+{
+    .dramType = TYPE_LPDDR4, .freq = 1866, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1,
+    .readLat = 40,  .writeLat =  16,    .DivMode =  DIV8_MODE,
+
+    .tras = 11, .tras_05T = 1,
+    .trp = 7,   .trp_05T = 0,
+    .trpab = 8, .trpab_05T = 1,
+    .trc = 19,  .trc_05T = 0,
+    .trfc = 119,    .trfc_05T = 0,
+    .trfcpb = 53,   .trfcpb_05T = 1,
+    .txp = 0,   .txp_05T = 1,
+    .trtp = 2,  .trtp_05T = 0,
+    .trcd = 8,  .trcd_05T = 1,
+    .twr = 14,  .twr_05T = 1,
+    .twtr = 9,  .twtr_05T = 0,
+    .tpbr2pbr = 35, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 17,   .tr2mrw_05T = 1,
+    .tw2mrw = 10,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 14, .tmrr2mrw_05T = 1,
+    .tmrw = 5,  .tmrw_05T = 1,
+    .tmrd = 7,  .tmrd_05T = 1,
+    .tmrwckel = 8,  .tmrwckel_05T = 1,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 12,    .tmrri_05T = 0,
+    .trrd = 4,  .trrd_05T = 0,
+    .trrd_4266 = 2, .trrd_4266_05T = 1,
+    .tfaw = 11, .tfaw_05T = 0,
+    .tfaw_4266 = 6, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 7,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 10,  .trtw_odt_on_05T = 0,
+    .txrefcnt = 135,
+    .tzqcs = 40,
+    .xrtw2w_new_mode = 5,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 1,
+    .xrtw2r_odt_off = 1,
+    .xrtr2w_odt_on = 9,
+    .xrtr2w_odt_off = 9,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 7,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 47,
+    .hwset_mr2_op = 54,
+    .hwset_mr13_op = 216,
+    .hwset_vrcg_op = 208,
+    .trcd_derate = 9,   .trcd_derate_05T = 1,
+    .trc_derate = 21,   .trc_derate_05T = 1,
+    .tras_derate = 12,  .tras_derate_05T = 0,
+    .trpab_derate = 9,  .trpab_derate_05T = 1,
+    .trp_derate = 8,    .trp_derate_05T = 0,
+    .trrd_derate = 5,   .trrd_derate_05T = 0,
+    .trtpd = 15,    .trtpd_05T = 0,
+    .twtpd = 17,    .twtpd_05T = 1,
+    .tmrr2w_odt_off = 11,
+    .tmrr2w_odt_on = 13,
+    .ckeprd = 3,
+    .ckelckcnt = 3,
+    .zqlat2 = 14,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 6,   .datlat = 16
+},
+#else  //ENABLE_READ_DBI == 0)
+//LPDDR4 4X_3733_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 1866, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    .readLat = 32,  .writeLat =  16,    .DivMode =  DIV8_MODE,
+
+    .tras = 11, .tras_05T = 1,
+    .trp = 7,   .trp_05T = 0,
+    .trpab = 8, .trpab_05T = 1,
+    .trc = 19,  .trc_05T = 0,
+    .trfc = 119,    .trfc_05T = 0,
+    .trfcpb = 53,   .trfcpb_05T = 1,
+    .txp = 0,   .txp_05T = 1,
+    .trtp = 2,  .trtp_05T = 0,
+    .trcd = 8,  .trcd_05T = 1,
+    .twr = 13,  .twr_05T = 1,
+    .twtr = 8,  .twtr_05T = 0,
+    .tpbr2pbr = 35, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 15,   .tr2mrw_05T = 1,
+    .tw2mrw = 10,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 12, .tmrr2mrw_05T = 1,
+    .tmrw = 5,  .tmrw_05T = 1,
+    .tmrd = 7,  .tmrd_05T = 1,
+    .tmrwckel = 8,  .tmrwckel_05T = 1,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 12,    .tmrri_05T = 0,
+    .trrd = 4,  .trrd_05T = 0,
+    .trrd_4266 = 2, .trrd_4266_05T = 1,
+    .tfaw = 11, .tfaw_05T = 0,
+    .tfaw_4266 = 6, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 5,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 8,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 135,
+    .tzqcs = 40,
+    .xrtw2w_new_mode = 5,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 1,
+    .xrtw2r_odt_off = 1,
+    .xrtr2w_odt_on = 7,
+    .xrtr2w_odt_off = 7,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 7,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 47,
+    .hwset_mr2_op = 54,
+    .hwset_mr13_op = 216,
+    .hwset_vrcg_op = 208,
+    .trcd_derate = 9,   .trcd_derate_05T = 1,
+    .trc_derate = 21,   .trc_derate_05T = 1,
+    .tras_derate = 12,  .tras_derate_05T = 0,
+    .trpab_derate = 9,  .trpab_derate_05T = 1,
+    .trp_derate = 8,    .trp_derate_05T = 0,
+    .trrd_derate = 5,   .trrd_derate_05T = 0,
+    .trtpd = 13,    .trtpd_05T = 0,
+    .twtpd = 16,    .twtpd_05T = 1,
+    .tmrr2w_odt_off = 9,
+    .tmrr2w_odt_on = 11,
+    .ckeprd = 3,
+    .ckelckcnt = 3,
+    .zqlat2 = 14,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 6,   .datlat = 16
+},
+//LPDDR4 4X_3733_BT_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 1866, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    .readLat = 36,  .writeLat =  16,    .DivMode =  DIV8_MODE,
+
+    .tras = 11, .tras_05T = 1,
+    .trp = 7,   .trp_05T = 0,
+    .trpab = 8, .trpab_05T = 1,
+    .trc = 19,  .trc_05T = 0,
+    .trfc = 119,    .trfc_05T = 0,
+    .trfcpb = 53,   .trfcpb_05T = 1,
+    .txp = 0,   .txp_05T = 1,
+    .trtp = 2,  .trtp_05T = 0,
+    .trcd = 8,  .trcd_05T = 1,
+    .twr = 14,  .twr_05T = 1,
+    .twtr = 9,  .twtr_05T = 0,
+    .tpbr2pbr = 35, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 16,   .tr2mrw_05T = 1,
+    .tw2mrw = 10,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 13, .tmrr2mrw_05T = 1,
+    .tmrw = 5,  .tmrw_05T = 1,
+    .tmrd = 7,  .tmrd_05T = 1,
+    .tmrwckel = 8,  .tmrwckel_05T = 1,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 12,    .tmrri_05T = 0,
+    .trrd = 4,  .trrd_05T = 0,
+    .trrd_4266 = 2, .trrd_4266_05T = 1,
+    .tfaw = 11, .tfaw_05T = 0,
+    .tfaw_4266 = 6, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 6,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 9,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 135,
+    .tzqcs = 40,
+    .xrtw2w_new_mode = 5,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 1,
+    .xrtw2r_odt_off = 1,
+    .xrtr2w_odt_on = 8,
+    .xrtr2w_odt_off = 8,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 7,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 47,
+    .hwset_mr2_op = 54,
+    .hwset_mr13_op = 216,
+    .hwset_vrcg_op = 208,
+    .trcd_derate = 9,   .trcd_derate_05T = 1,
+    .trc_derate = 21,   .trc_derate_05T = 1,
+    .tras_derate = 12,  .tras_derate_05T = 0,
+    .trpab_derate = 9,  .trpab_derate_05T = 1,
+    .trp_derate = 8,    .trp_derate_05T = 0,
+    .trrd_derate = 5,   .trrd_derate_05T = 0,
+    .trtpd = 14,    .trtpd_05T = 0,
+    .twtpd = 17,    .twtpd_05T = 1,
+    .tmrr2w_odt_off = 10,
+    .tmrr2w_odt_on = 12,
+    .ckeprd = 3,
+    .ckelckcnt = 3,
+    .zqlat2 = 14,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 6,   .datlat = 16
+},
+#endif
+#endif
+#if SUPPORT_LP4_DDR3200_ACTIM
+    //LP4_DDR3200 ACTiming---------------------------------
+#if (ENABLE_READ_DBI == 1)
+//LPDDR4 4X_3200_Div 8_DBI1.csv Read 1
+{
+    .dramType = TYPE_LPDDR4, .freq = 1600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1,
+    .readLat = 32,  .writeLat =  14,    .DivMode =  DIV8_MODE,
+
+    .tras = 8,  .tras_05T = 1,
+    .trp = 6,   .trp_05T = 0,
+    .trpab = 7, .trpab_05T = 0,
+    .trc = 15,  .trc_05T = 0,
+    .trfc = 100,    .trfc_05T = 0,
+    .trfcpb = 44,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 1,  .trtp_05T = 1,
+    .trcd = 7,  .trcd_05T = 1,
+    .twr = 12,  .twr_05T = 1,
+    .twtr = 7,  .twtr_05T = 0,
+    .tpbr2pbr = 29, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 14,   .tr2mrw_05T = 1,
+    .tw2mrw = 9,    .tw2mrw_05T = 0,
+    .tmrr2mrw = 12, .tmrr2mrw_05T = 1,
+    .tmrw = 4,  .tmrw_05T = 1,
+    .tmrd = 6,  .tmrd_05T = 1,
+    .tmrwckel = 7,  .tmrwckel_05T = 1,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 10,    .tmrri_05T = 1,
+    .trrd = 3,  .trrd_05T = 0,
+    .trrd_4266 = 2, .trrd_4266_05T = 0,
+    .tfaw = 8,  .tfaw_05T = 0,
+    .tfaw_4266 = 4, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 5,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 7,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 115,
+    .tzqcs = 34,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 1,
+    .xrtw2r_odt_off = 1,
+    .xrtr2w_odt_on = 6,
+    .xrtr2w_odt_off = 6,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 7,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 40,
+    .hwset_mr2_op = 45,
+    .hwset_mr13_op = 216,
+    .hwset_vrcg_op = 208,
+    .trcd_derate = 8,   .trcd_derate_05T = 0,
+    .trc_derate = 17,   .trc_derate_05T = 0,
+    .tras_derate = 9,   .tras_derate_05T = 1,
+    .trpab_derate = 8,  .trpab_derate_05T = 0,
+    .trp_derate = 6,    .trp_derate_05T = 1,
+    .trrd_derate = 4,   .trrd_derate_05T = 0,
+    .trtpd = 13,    .trtpd_05T = 0,
+    .twtpd = 14,    .twtpd_05T = 1,
+    .tmrr2w_odt_off = 9,
+    .tmrr2w_odt_on = 11,
+    .ckeprd = 2,
+    .ckelckcnt = 2,
+    .zqlat2 = 12,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 5,   .datlat = 15
+},
+//LPDDR4 4X_3200_BT_Div 8_DBI1.csv Read 1
+{
+    .dramType = TYPE_LPDDR4, .freq = 1600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1,
+    .readLat = 36,  .writeLat =  14,    .DivMode =  DIV8_MODE,
+
+    .tras = 8,  .tras_05T = 1,
+    .trp = 6,   .trp_05T = 0,
+    .trpab = 7, .trpab_05T = 0,
+    .trc = 15,  .trc_05T = 0,
+    .trfc = 100,    .trfc_05T = 0,
+    .trfcpb = 44,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 1,  .trtp_05T = 1,
+    .trcd = 7,  .trcd_05T = 1,
+    .twr = 12,  .twr_05T = 1,
+    .twtr = 8,  .twtr_05T = 0,
+    .tpbr2pbr = 29, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 15,   .tr2mrw_05T = 1,
+    .tw2mrw = 9,    .tw2mrw_05T = 0,
+    .tmrr2mrw = 13, .tmrr2mrw_05T = 1,
+    .tmrw = 4,  .tmrw_05T = 1,
+    .tmrd = 6,  .tmrd_05T = 1,
+    .tmrwckel = 7,  .tmrwckel_05T = 1,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 10,    .tmrri_05T = 1,
+    .trrd = 3,  .trrd_05T = 0,
+    .trrd_4266 = 2, .trrd_4266_05T = 0,
+    .tfaw = 8,  .tfaw_05T = 0,
+    .tfaw_4266 = 4, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 6,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 8,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 115,
+    .tzqcs = 34,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 1,
+    .xrtw2r_odt_off = 1,
+    .xrtr2w_odt_on = 7,
+    .xrtr2w_odt_off = 7,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 7,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 40,
+    .hwset_mr2_op = 45,
+    .hwset_mr13_op = 216,
+    .hwset_vrcg_op = 208,
+    .trcd_derate = 8,   .trcd_derate_05T = 0,
+    .trc_derate = 17,   .trc_derate_05T = 0,
+    .tras_derate = 9,   .tras_derate_05T = 1,
+    .trpab_derate = 8,  .trpab_derate_05T = 0,
+    .trp_derate = 6,    .trp_derate_05T = 1,
+    .trrd_derate = 4,   .trrd_derate_05T = 0,
+    .trtpd = 14,    .trtpd_05T = 0,
+    .twtpd = 15,    .twtpd_05T = 1,
+    .tmrr2w_odt_off = 10,
+    .tmrr2w_odt_on = 12,
+    .ckeprd = 2,
+    .ckelckcnt = 2,
+    .zqlat2 = 12,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 5,   .datlat = 15
+},
+#else  //ENABLE_READ_DBI == 0)
+//LPDDR4 4X_3200_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 1600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    .readLat = 28,  .writeLat =  14,    .DivMode =  DIV8_MODE,
+
+    .tras = 8,  .tras_05T = 1,
+    .trp = 6,   .trp_05T = 0,
+    .trpab = 7, .trpab_05T = 0,
+    .trc = 15,  .trc_05T = 0,
+    .trfc = 100,    .trfc_05T = 0,
+    .trfcpb = 44,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 1,  .trtp_05T = 1,
+    .trcd = 7,  .trcd_05T = 1,
+    .twr = 12,  .twr_05T = 1,
+    .twtr = 7,  .twtr_05T = 0,
+    .tpbr2pbr = 29, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 13,   .tr2mrw_05T = 1,
+    .tw2mrw = 9,    .tw2mrw_05T = 0,
+    .tmrr2mrw = 11, .tmrr2mrw_05T = 1,
+    .tmrw = 4,  .tmrw_05T = 1,
+    .tmrd = 6,  .tmrd_05T = 1,
+    .tmrwckel = 7,  .tmrwckel_05T = 1,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 10,    .tmrri_05T = 1,
+    .trrd = 3,  .trrd_05T = 0,
+    .trrd_4266 = 2, .trrd_4266_05T = 0,
+    .tfaw = 8,  .tfaw_05T = 0,
+    .tfaw_4266 = 4, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 4,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 6,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 115,
+    .tzqcs = 34,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 1,
+    .xrtw2r_odt_off = 1,
+    .xrtr2w_odt_on = 5,
+    .xrtr2w_odt_off = 5,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 7,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 40,
+    .hwset_mr2_op = 45,
+    .hwset_mr13_op = 216,
+    .hwset_vrcg_op = 208,
+    .trcd_derate = 8,   .trcd_derate_05T = 0,
+    .trc_derate = 17,   .trc_derate_05T = 0,
+    .tras_derate = 9,   .tras_derate_05T = 1,
+    .trpab_derate = 8,  .trpab_derate_05T = 0,
+    .trp_derate = 6,    .trp_derate_05T = 1,
+    .trrd_derate = 4,   .trrd_derate_05T = 0,
+    .trtpd = 12,    .trtpd_05T = 0,
+    .twtpd = 14,    .twtpd_05T = 1,
+    .tmrr2w_odt_off = 8,
+    .tmrr2w_odt_on = 10,
+    .ckeprd = 2,
+    .ckelckcnt = 2,
+    .zqlat2 = 12,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 5,   .datlat = 15
+},
+//LPDDR4 4X_3200_BT_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 1600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    .readLat = 32,  .writeLat =  14,    .DivMode =  DIV8_MODE,
+
+    .tras = 8,  .tras_05T = 1,
+    .trp = 6,   .trp_05T = 0,
+    .trpab = 7, .trpab_05T = 0,
+    .trc = 15,  .trc_05T = 0,
+    .trfc = 100,    .trfc_05T = 0,
+    .trfcpb = 44,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 1,  .trtp_05T = 1,
+    .trcd = 7,  .trcd_05T = 1,
+    .twr = 12,  .twr_05T = 1,
+    .twtr = 8,  .twtr_05T = 0,
+    .tpbr2pbr = 29, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 14,   .tr2mrw_05T = 1,
+    .tw2mrw = 9,    .tw2mrw_05T = 0,
+    .tmrr2mrw = 12, .tmrr2mrw_05T = 1,
+    .tmrw = 4,  .tmrw_05T = 1,
+    .tmrd = 6,  .tmrd_05T = 1,
+    .tmrwckel = 7,  .tmrwckel_05T = 1,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 10,    .tmrri_05T = 1,
+    .trrd = 3,  .trrd_05T = 0,
+    .trrd_4266 = 2, .trrd_4266_05T = 0,
+    .tfaw = 8,  .tfaw_05T = 0,
+    .tfaw_4266 = 4, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 5,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 7,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 115,
+    .tzqcs = 34,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 1,
+    .xrtw2r_odt_off = 1,
+    .xrtr2w_odt_on = 6,
+    .xrtr2w_odt_off = 6,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 7,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 40,
+    .hwset_mr2_op = 45,
+    .hwset_mr13_op = 216,
+    .hwset_vrcg_op = 208,
+    .trcd_derate = 8,   .trcd_derate_05T = 0,
+    .trc_derate = 17,   .trc_derate_05T = 0,
+    .tras_derate = 9,   .tras_derate_05T = 1,
+    .trpab_derate = 8,  .trpab_derate_05T = 0,
+    .trp_derate = 6,    .trp_derate_05T = 1,
+    .trrd_derate = 4,   .trrd_derate_05T = 0,
+    .trtpd = 13,    .trtpd_05T = 0,
+    .twtpd = 15,    .twtpd_05T = 1,
+    .tmrr2w_odt_off = 9,
+    .tmrr2w_odt_on = 11,
+    .ckeprd = 2,
+    .ckelckcnt = 2,
+    .zqlat2 = 12,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 5,   .datlat = 15
+},
+#endif
+#endif
+#if SUPPORT_LP4_DDR2667_ACTIM
+    //LP4_DDR2667 ACTiming---------------------------------
+//LPDDR4 4X_2667_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 1333, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    .readLat = 24,  .writeLat =  12,    .DivMode =  DIV8_MODE,
+
+    .tras = 6,  .tras_05T = 0,
+    .trp = 5,   .trp_05T = 0,
+    .trpab = 6, .trpab_05T = 0,
+    .trc = 11,  .trc_05T = 1,
+    .trfc = 81, .trfc_05T = 1,
+    .trfcpb = 35,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 1,  .trtp_05T = 1,
+    .trcd = 6,  .trcd_05T = 1,
+    .twr = 10,  .twr_05T = 0,
+    .twtr = 6,  .twtr_05T = 0,
+    .tpbr2pbr = 23, .tpbr2pbr_05T = 1,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 12,   .tr2mrw_05T = 0,
+    .tw2mrw = 8,    .tw2mrw_05T = 0,
+    .tmrr2mrw = 10, .tmrr2mrw_05T = 0,
+    .tmrw = 4,  .tmrw_05T = 0,
+    .tmrd = 5,  .tmrd_05T = 1,
+    .tmrwckel = 6,  .tmrwckel_05T = 1,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 9, .tmrri_05T = 0,
+    .trrd = 2,  .trrd_05T = 1,
+    .trrd_4266 = 2, .trrd_4266_05T = 0,
+    .tfaw = 5,  .tfaw_05T = 1,
+    .tfaw_4266 = 2, .tfaw_4266_05T = 1,
+    .trtw_odt_off = 3,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 6,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 96,
+    .tzqcs = 29,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 1,
+    .xrtw2r_odt_off = 1,
+    .xrtr2w_odt_on = 5,
+    .xrtr2w_odt_off = 5,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 6,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 34,
+    .hwset_mr2_op = 36,
+    .hwset_mr13_op = 216,
+    .hwset_vrcg_op = 208,
+    .trcd_derate = 7,   .trcd_derate_05T = 0,
+    .trc_derate = 13,   .trc_derate_05T = 0,
+    .tras_derate = 6,   .tras_derate_05T = 1,
+    .trpab_derate = 6,  .trpab_derate_05T = 1,
+    .trp_derate = 5,    .trp_derate_05T = 1,
+    .trrd_derate = 3,   .trrd_derate_05T = 0,
+    .trtpd = 10,    .trtpd_05T = 1,
+    .twtpd = 13,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 6,
+    .tmrr2w_odt_on = 8,
+    .ckeprd = 2,
+    .ckelckcnt = 2,
+    .zqlat2 = 11,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = TBD,     .datlat = TBD
+},
+//LPDDR4 4X_2667_BT_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 1333, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    .readLat = 26,  .writeLat =  12,    .DivMode =  DIV8_MODE,
+
+    .tras = 6,  .tras_05T = 0,
+    .trp = 5,   .trp_05T = 0,
+    .trpab = 6, .trpab_05T = 0,
+    .trc = 11,  .trc_05T = 1,
+    .trfc = 81, .trfc_05T = 1,
+    .trfcpb = 35,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 1,  .trtp_05T = 1,
+    .trcd = 6,  .trcd_05T = 1,
+    .twr = 11,  .twr_05T = 1,
+    .twtr = 7,  .twtr_05T = 1,
+    .tpbr2pbr = 23, .tpbr2pbr_05T = 1,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 12,   .tr2mrw_05T = 1,
+    .tw2mrw = 8,    .tw2mrw_05T = 0,
+    .tmrr2mrw = 10, .tmrr2mrw_05T = 1,
+    .tmrw = 4,  .tmrw_05T = 0,
+    .tmrd = 5,  .tmrd_05T = 1,
+    .tmrwckel = 6,  .tmrwckel_05T = 1,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 9, .tmrri_05T = 0,
+    .trrd = 2,  .trrd_05T = 1,
+    .trrd_4266 = 2, .trrd_4266_05T = 0,
+    .tfaw = 5,  .tfaw_05T = 1,
+    .tfaw_4266 = 2, .tfaw_4266_05T = 1,
+    .trtw_odt_off = 4,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 6,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 96,
+    .tzqcs = 29,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 1,
+    .xrtw2r_odt_off = 1,
+    .xrtr2w_odt_on = 5,
+    .xrtr2w_odt_off = 5,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 6,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 34,
+    .hwset_mr2_op = 36,
+    .hwset_mr13_op = 216,
+    .hwset_vrcg_op = 208,
+    .trcd_derate = 7,   .trcd_derate_05T = 0,
+    .trc_derate = 13,   .trc_derate_05T = 0,
+    .tras_derate = 6,   .tras_derate_05T = 1,
+    .trpab_derate = 6,  .trpab_derate_05T = 1,
+    .trp_derate = 5,    .trp_derate_05T = 1,
+    .trrd_derate = 3,   .trrd_derate_05T = 0,
+    .trtpd = 11,    .trtpd_05T = 0,
+    .twtpd = 13,    .twtpd_05T = 1,
+    .tmrr2w_odt_off = 7,
+    .tmrr2w_odt_on = 9,
+    .ckeprd = 2,
+    .ckelckcnt = 2,
+    .zqlat2 = 11,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = TBD,     .datlat = TBD
+},
+#endif
+#if SUPPORT_LP4_DDR2400_ACTIM
+    //LP4_DDR2400 ACTiming---------------------------------
+//LPDDR4 4X_2400_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 1200, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    .readLat = 24,  .writeLat =  12,    .DivMode =  DIV8_MODE,
+
+    .tras = 4,  .tras_05T = 1,
+    .trp = 4,   .trp_05T = 0,
+    .trpab = 5, .trpab_05T = 0,
+    .trc = 9,   .trc_05T = 1,
+    .trfc = 72, .trfc_05T = 1,
+    .trfcpb = 30,   .trfcpb_05T = 1,
+    .txp = 0,   .txp_05T = 1,
+    .trtp = 1,  .trtp_05T = 0,
+    .trcd = 5,  .trcd_05T = 1,
+    .twr = 9,   .twr_05T = 1,
+    .twtr = 6,  .twtr_05T = 1,
+    .tpbr2pbr = 20, .tpbr2pbr_05T = 1,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 12,   .tr2mrw_05T = 0,
+    .tw2mrw = 8,    .tw2mrw_05T = 0,
+    .tmrr2mrw = 10, .tmrr2mrw_05T = 0,
+    .tmrw = 4,  .tmrw_05T = 0,
+    .tmrd = 5,  .tmrd_05T = 0,
+    .tmrwckel = 6,  .tmrwckel_05T = 0,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 8, .tmrri_05T = 0,
+    .trrd = 2,  .trrd_05T = 1,
+    .trrd_4266 = 1, .trrd_4266_05T = 1,
+    .tfaw = 4,  .tfaw_05T = 1,
+    .tfaw_4266 = 1, .tfaw_4266_05T = 1,
+    .trtw_odt_off = 3,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 6,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 87,
+    .tzqcs = 26,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 2,
+    .xrtw2r_odt_off = 2,
+    .xrtr2w_odt_on = 5,
+    .xrtr2w_odt_off = 5,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 6,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 31,
+    .hwset_mr2_op = 36,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 6,   .trcd_derate_05T = 0,
+    .trc_derate = 10,   .trc_derate_05T = 1,
+    .tras_derate = 5,   .tras_derate_05T = 0,
+    .trpab_derate = 5,  .trpab_derate_05T = 1,
+    .trp_derate = 4,    .trp_derate_05T = 1,
+    .trrd_derate = 3,   .trrd_derate_05T = 0,
+    .trtpd = 10,    .trtpd_05T = 1,
+    .twtpd = 12,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 6,
+    .tmrr2w_odt_on = 8,
+    .ckeprd = 2,
+    .ckelckcnt = 2,
+    .zqlat2 = 10,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 4,   .datlat = 13
+},
+//LPDDR4 4X_2400_BT_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 1200, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    .readLat = 26,  .writeLat =  12,    .DivMode =  DIV8_MODE,
+
+    .tras = 4,  .tras_05T = 1,
+    .trp = 4,   .trp_05T = 0,
+    .trpab = 5, .trpab_05T = 0,
+    .trc = 9,   .trc_05T = 1,
+    .trfc = 72, .trfc_05T = 1,
+    .trfcpb = 30,   .trfcpb_05T = 1,
+    .txp = 0,   .txp_05T = 1,
+    .trtp = 1,  .trtp_05T = 0,
+    .trcd = 5,  .trcd_05T = 1,
+    .twr = 10,  .twr_05T = 0,
+    .twtr = 6,  .twtr_05T = 0,
+    .tpbr2pbr = 20, .tpbr2pbr_05T = 1,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 12,   .tr2mrw_05T = 1,
+    .tw2mrw = 8,    .tw2mrw_05T = 0,
+    .tmrr2mrw = 10, .tmrr2mrw_05T = 1,
+    .tmrw = 4,  .tmrw_05T = 0,
+    .tmrd = 5,  .tmrd_05T = 0,
+    .tmrwckel = 6,  .tmrwckel_05T = 0,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 8, .tmrri_05T = 0,
+    .trrd = 2,  .trrd_05T = 1,
+    .trrd_4266 = 1, .trrd_4266_05T = 1,
+    .tfaw = 4,  .tfaw_05T = 1,
+    .tfaw_4266 = 1, .tfaw_4266_05T = 1,
+    .trtw_odt_off = 4,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 6,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 87,
+    .tzqcs = 26,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 1,
+    .xrtw2r_odt_off = 1,
+    .xrtr2w_odt_on = 5,
+    .xrtr2w_odt_off = 5,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 6,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 31,
+    .hwset_mr2_op = 36,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 6,   .trcd_derate_05T = 0,
+    .trc_derate = 10,   .trc_derate_05T = 1,
+    .tras_derate = 5,   .tras_derate_05T = 0,
+    .trpab_derate = 5,  .trpab_derate_05T = 1,
+    .trp_derate = 4,    .trp_derate_05T = 1,
+    .trrd_derate = 3,   .trrd_derate_05T = 0,
+    .trtpd = 11,    .trtpd_05T = 0,
+    .twtpd = 13,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 7,
+    .tmrr2w_odt_on = 9,
+    .ckeprd = 2,
+    .ckelckcnt = 2,
+    .zqlat2 = 10,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 4,   .datlat = 13
+},
+#endif
+#if SUPPORT_LP4_DDR1866_ACTIM
+    //LP4_DDR1866 ACTiming---------------------------------
+//LPDDR4 4X_1866_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 933, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    .readLat = 20,  .writeLat =  10,    .DivMode =  DIV8_MODE,
+
+    .tras = 1,  .tras_05T = 1,
+    .trp = 3,   .trp_05T = 0,
+    .trpab = 3, .trpab_05T = 1,
+    .trc = 5,   .trc_05T = 0,
+    .trfc = 53, .trfc_05T = 1,
+    .trfcpb = 21,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 0,  .trtp_05T = 1,
+    .trcd = 4,  .trcd_05T = 1,
+    .twr = 8,   .twr_05T = 1,
+    .twtr = 5,  .twtr_05T = 1,
+    .tpbr2pbr = 14, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 10,   .tr2mrw_05T = 0,
+    .tw2mrw = 7,    .tw2mrw_05T = 0,
+    .tmrr2mrw = 9,  .tmrr2mrw_05T = 0,
+    .tmrw = 3,  .tmrw_05T = 0,
+    .tmrd = 4,  .tmrd_05T = 0,
+    .tmrwckel = 5,  .tmrwckel_05T = 0,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 6, .tmrri_05T = 0,
+    .trrd = 1,  .trrd_05T = 1,
+    .trrd_4266 = 1, .trrd_4266_05T = 0,
+    .tfaw = 1,  .tfaw_05T = 1,
+    .tfaw_4266 = 0, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 3,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 5,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 68,
+    .tzqcs = 19,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 2,
+    .xrtw2r_odt_off = 2,
+    .xrtr2w_odt_on = 3,
+    .xrtr2w_odt_off = 3,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 6,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 24,
+    .hwset_mr2_op = 27,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 5,   .trcd_derate_05T = 0,
+    .trc_derate = 6,    .trc_derate_05T = 1,
+    .tras_derate = 2,   .tras_derate_05T = 0,
+    .trpab_derate = 4,  .trpab_derate_05T = 0,
+    .trp_derate = 3,    .trp_derate_05T = 1,
+    .trrd_derate = 2,   .trrd_derate_05T = 0,
+    .trtpd = 9, .trtpd_05T = 1,
+    .twtpd = 10,    .twtpd_05T = 1,
+    .tmrr2w_odt_off = 5,
+    .tmrr2w_odt_on = 7,
+    .ckeprd = 1,
+    .ckelckcnt = 2,
+    .zqlat2 = 7,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 3,   .datlat = 13
+},
+//LPDDR4 4X_1866_BT_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 933, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    .readLat = 22,  .writeLat =  10,    .DivMode =  DIV8_MODE,
+
+    .tras = 1,  .tras_05T = 1,
+    .trp = 3,   .trp_05T = 0,
+    .trpab = 3, .trpab_05T = 1,
+    .trc = 5,   .trc_05T = 0,
+    .trfc = 53, .trfc_05T = 1,
+    .trfcpb = 21,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 0,  .trtp_05T = 1,
+    .trcd = 4,  .trcd_05T = 1,
+    .twr = 8,   .twr_05T = 0,
+    .twtr = 5,  .twtr_05T = 0,
+    .tpbr2pbr = 14, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 10,   .tr2mrw_05T = 1,
+    .tw2mrw = 7,    .tw2mrw_05T = 0,
+    .tmrr2mrw = 9,  .tmrr2mrw_05T = 1,
+    .tmrw = 3,  .tmrw_05T = 0,
+    .tmrd = 4,  .tmrd_05T = 0,
+    .tmrwckel = 5,  .tmrwckel_05T = 0,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 6, .tmrri_05T = 0,
+    .trrd = 1,  .trrd_05T = 1,
+    .trrd_4266 = 1, .trrd_4266_05T = 0,
+    .tfaw = 1,  .tfaw_05T = 1,
+    .tfaw_4266 = 0, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 3,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 5,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 68,
+    .tzqcs = 19,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 2,
+    .xrtw2r_odt_off = 1,
+    .xrtr2w_odt_on = 4,
+    .xrtr2w_odt_off = 4,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 6,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 24,
+    .hwset_mr2_op = 27,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 5,   .trcd_derate_05T = 0,
+    .trc_derate = 6,    .trc_derate_05T = 1,
+    .tras_derate = 2,   .tras_derate_05T = 0,
+    .trpab_derate = 4,  .trpab_derate_05T = 0,
+    .trp_derate = 3,    .trp_derate_05T = 1,
+    .trrd_derate = 2,   .trrd_derate_05T = 0,
+    .trtpd = 10,    .trtpd_05T = 0,
+    .twtpd = 11,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 6,
+    .tmrr2w_odt_on = 8,
+    .ckeprd = 1,
+    .ckelckcnt = 2,
+    .zqlat2 = 7,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 3,   .datlat = 13
+},
+#endif
+#if SUPPORT_LP4_DDR1600_ACTIM
+    //LP4_DDR1600 ACTiming---------------------------------
+//LPDDR4 4X_1600_Div 4_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 800, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    .readLat = 14,  .writeLat =  8, .DivMode =  DIV4_MODE,
+
+    .tras = 9,  .tras_05T = 0,
+    .trp = 6,   .trp_05T = 0,
+    .trpab = 7, .trpab_05T = 0,
+    .trc = 15,  .trc_05T = 0,
+    .trfc = 100,    .trfc_05T = 0,
+    .trfcpb = 44,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 3,  .trtp_05T = 0,
+    .trcd = 8,  .trcd_05T = 0,
+    .twr = 15,  .twr_05T = 0,
+    .twtr = 10, .twtr_05T = 0,
+    .tpbr2pbr = 29, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 17,   .tr2mrw_05T = 0,
+    .tw2mrw = 13,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 14, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 7,  .tmrd_05T = 0,
+    .tmrwckel = 9,  .tmrwckel_05T = 0,
+    .tpde = 3,  .tpde_05T = 0,
+    .tpdx = 3,  .tpdx_05T = 0,
+    .tmrri = 11,    .tmrri_05T = 0,
+    .trrd = 3,  .trrd_05T = 0,
+    .trrd_4266 = 2, .trrd_4266_05T = 0,
+    .tfaw = 8,  .tfaw_05T = 0,
+    .tfaw_4266 = 4, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 7,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 11,  .trtw_odt_on_05T = 0,
+    .txrefcnt = 115,
+    .tzqcs = 34,
+    .xrtw2w_new_mode = 9,
+    .xrtw2w_old_mode = 10,
+    .xrtw2r_odt_on = 7,
+    .xrtw2r_odt_off = 6,
+    .xrtr2w_odt_on = 10,
+    .xrtr2w_odt_off = 10,
+    .xrtr2r_new_mode = 7,
+    .xrtr2r_old_mode = 9,
+    .tr2mrr = 8,
+    .vrcgdis_prdcnt = 40,
+    .hwset_mr2_op = 18,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 8,   .trcd_derate_05T = 0,
+    .trc_derate = 17,   .trc_derate_05T = 0,
+    .tras_derate = 10,  .tras_derate_05T = 0,
+    .trpab_derate = 8,  .trpab_derate_05T = 0,
+    .trp_derate = 6,    .trp_derate_05T = 0,
+    .trrd_derate = 4,   .trrd_derate_05T = 0,
+    .trtpd = 15,    .trtpd_05T = 0,
+    .twtpd = 19,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 10,
+    .tmrr2w_odt_on = 12,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .zqlat2 = 12,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 2,   .datlat = 10
+},
+//LPDDR4 4X_1600_BT_Div 4_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 800, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    .readLat = 16,  .writeLat =  8, .DivMode =  DIV4_MODE,
+
+    .tras = 9,  .tras_05T = 0,
+    .trp = 6,   .trp_05T = 0,
+    .trpab = 7, .trpab_05T = 0,
+    .trc = 15,  .trc_05T = 0,
+    .trfc = 100,    .trfc_05T = 0,
+    .trfcpb = 44,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 3,  .trtp_05T = 0,
+    .trcd = 8,  .trcd_05T = 0,
+    .twr = 16,  .twr_05T = 0,
+    .twtr = 11, .twtr_05T = 0,
+    .tpbr2pbr = 29, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 18,   .tr2mrw_05T = 0,
+    .tw2mrw = 13,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 15, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 7,  .tmrd_05T = 0,
+    .tmrwckel = 9,  .tmrwckel_05T = 0,
+    .tpde = 3,  .tpde_05T = 0,
+    .tpdx = 3,  .tpdx_05T = 0,
+    .tmrri = 11,    .tmrri_05T = 0,
+    .trrd = 3,  .trrd_05T = 0,
+    .trrd_4266 = 2, .trrd_4266_05T = 0,
+    .tfaw = 8,  .tfaw_05T = 0,
+    .tfaw_4266 = 4, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 8,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 12,  .trtw_odt_on_05T = 0,
+    .txrefcnt = 115,
+    .tzqcs = 34,
+    .xrtw2w_new_mode = 9,
+    .xrtw2w_old_mode = 10,
+    .xrtw2r_odt_on = 6,
+    .xrtw2r_odt_off = 5,
+    .xrtr2w_odt_on = 11,
+    .xrtr2w_odt_off = 11,
+    .xrtr2r_new_mode = 7,
+    .xrtr2r_old_mode = 10,
+    .tr2mrr = 8,
+    .vrcgdis_prdcnt = 40,
+    .hwset_mr2_op = 18,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 8,   .trcd_derate_05T = 0,
+    .trc_derate = 17,   .trc_derate_05T = 0,
+    .tras_derate = 10,  .tras_derate_05T = 0,
+    .trpab_derate = 8,  .trpab_derate_05T = 0,
+    .trp_derate = 6,    .trp_derate_05T = 0,
+    .trrd_derate = 4,   .trrd_derate_05T = 0,
+    .trtpd = 16,    .trtpd_05T = 0,
+    .twtpd = 19,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 11,
+    .tmrr2w_odt_on = 13,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .zqlat2 = 12,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 2,   .datlat = 10
+},
+//LPDDR4 4X_1600_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 800, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    .readLat = 14,  .writeLat =  8, .DivMode =  DIV8_MODE,
+
+    .tras = 0,  .tras_05T = 0,
+    .trp = 2,   .trp_05T = 1,
+    .trpab = 3, .trpab_05T = 0,
+    .trc = 3,   .trc_05T = 0,
+    .trfc = 44, .trfc_05T = 0,
+    .trfcpb = 16,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 0,  .trtp_05T = 1,
+    .trcd = 4,  .trcd_05T = 0,
+    .twr = 7,   .twr_05T = 1,
+    .twtr = 4,  .twtr_05T = 1,
+    .tpbr2pbr = 11, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 8,    .tr2mrw_05T = 1,
+    .tw2mrw = 6,    .tw2mrw_05T = 1,
+    .tmrr2mrw = 7,  .tmrr2mrw_05T = 0,
+    .tmrw = 3,  .tmrw_05T = 0,
+    .tmrd = 3,  .tmrd_05T = 1,
+    .tmrwckel = 4,  .tmrwckel_05T = 1,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 5, .tmrri_05T = 1,
+    .trrd = 1,  .trrd_05T = 0,
+    .trrd_4266 = 0, .trrd_4266_05T = 1,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tfaw_4266 = 0, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 1,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 4,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 58,
+    .tzqcs = 16,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 3,
+    .xrtw2r_odt_off = 3,
+    .xrtr2w_odt_on = 3,
+    .xrtr2w_odt_off = 3,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 6,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 20,
+    .hwset_mr2_op = 18,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 4,   .trcd_derate_05T = 0,
+    .trc_derate = 4,    .trc_derate_05T = 0,
+    .tras_derate = 0,   .tras_derate_05T = 1,
+    .trpab_derate = 3,  .trpab_derate_05T = 1,
+    .trp_derate = 2,    .trp_derate_05T = 1,
+    .trrd_derate = 1,   .trrd_derate_05T = 1,
+    .trtpd = 7, .trtpd_05T = 1,
+    .twtpd = 9, .twtpd_05T = 1,
+    .tmrr2w_odt_off = 3,
+    .tmrr2w_odt_on = 5,
+    .ckeprd = 1,
+    .ckelckcnt = 2,
+    .zqlat2 = 6,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 2,   .datlat = 10
+},
+//LPDDR4 4X_1600_BT_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 800, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    .readLat = 16,  .writeLat =  8, .DivMode =  DIV8_MODE,
+
+    .tras = 0,  .tras_05T = 0,
+    .trp = 2,   .trp_05T = 1,
+    .trpab = 3, .trpab_05T = 0,
+    .trc = 3,   .trc_05T = 0,
+    .trfc = 44, .trfc_05T = 0,
+    .trfcpb = 16,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 0,  .trtp_05T = 1,
+    .trcd = 4,  .trcd_05T = 0,
+    .twr = 7,   .twr_05T = 0,
+    .twtr = 4,  .twtr_05T = 0,
+    .tpbr2pbr = 11, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 9,    .tr2mrw_05T = 0,
+    .tw2mrw = 6,    .tw2mrw_05T = 1,
+    .tmrr2mrw = 7,  .tmrr2mrw_05T = 1,
+    .tmrw = 3,  .tmrw_05T = 0,
+    .tmrd = 3,  .tmrd_05T = 1,
+    .tmrwckel = 4,  .tmrwckel_05T = 1,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 5, .tmrri_05T = 1,
+    .trrd = 1,  .trrd_05T = 0,
+    .trrd_4266 = 0, .trrd_4266_05T = 1,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tfaw_4266 = 0, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 2,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 4,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 58,
+    .tzqcs = 16,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 3,
+    .xrtw2r_odt_off = 2,
+    .xrtr2w_odt_on = 3,
+    .xrtr2w_odt_off = 3,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 6,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 20,
+    .hwset_mr2_op = 18,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 4,   .trcd_derate_05T = 0,
+    .trc_derate = 4,    .trc_derate_05T = 0,
+    .tras_derate = 0,   .tras_derate_05T = 1,
+    .trpab_derate = 3,  .trpab_derate_05T = 1,
+    .trp_derate = 2,    .trp_derate_05T = 1,
+    .trrd_derate = 1,   .trrd_derate_05T = 1,
+    .trtpd = 8, .trtpd_05T = 0,
+    .twtpd = 9, .twtpd_05T = 1,
+    .tmrr2w_odt_off = 4,
+    .tmrr2w_odt_on = 6,
+    .ckeprd = 1,
+    .ckelckcnt = 2,
+    .zqlat2 = 6,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 2,   .datlat = 10
+},
+#endif
+#if SUPPORT_LP4_DDR1333_ACTIM
+    //LP4_DDR1333 ACTiming---------------------------------
+//LPDDR4 4X_1333_Div 4_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 666, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    .readLat = 14,  .writeLat =  8, .DivMode =  DIV4_MODE,
+
+    .tras = 6,  .tras_05T = 0,
+    .trp = 4,   .trp_05T = 0,
+    .trpab = 5, .trpab_05T = 0,
+    .trc = 11,  .trc_05T = 0,
+    .trfc = 82, .trfc_05T = 0,
+    .trfcpb = 35,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 3,  .trtp_05T = 0,
+    .trcd = 6,  .trcd_05T = 0,
+    .twr = 14,  .twr_05T = 0,
+    .twtr = 10, .twtr_05T = 0,
+    .tpbr2pbr = 23, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 17,   .tr2mrw_05T = 0,
+    .tw2mrw = 13,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 14, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 6,  .tmrd_05T = 0,
+    .tmrwckel = 8,  .tmrwckel_05T = 0,
+    .tpde = 3,  .tpde_05T = 0,
+    .tpdx = 3,  .tpdx_05T = 0,
+    .tmrri = 9, .tmrri_05T = 0,
+    .trrd = 3,  .trrd_05T = 0,
+    .trrd_4266 = 2, .trrd_4266_05T = 0,
+    .tfaw = 6,  .tfaw_05T = 0,
+    .tfaw_4266 = 2, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 7,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 11,  .trtw_odt_on_05T = 0,
+    .txrefcnt = 96,
+    .tzqcs = 28,
+    .xrtw2w_new_mode = 9,
+    .xrtw2w_old_mode = 10,
+    .xrtw2r_odt_on = 7,
+    .xrtw2r_odt_off = 6,
+    .xrtr2w_odt_on = 10,
+    .xrtr2w_odt_off = 10,
+    .xrtr2r_new_mode = 7,
+    .xrtr2r_old_mode = 9,
+    .tr2mrr = 8,
+    .vrcgdis_prdcnt = 34,
+    .hwset_mr2_op = 18,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 7,   .trcd_derate_05T = 0,
+    .trc_derate = 13,   .trc_derate_05T = 0,
+    .tras_derate = 7,   .tras_derate_05T = 0,
+    .trpab_derate = 6,  .trpab_derate_05T = 0,
+    .trp_derate = 5,    .trp_derate_05T = 0,
+    .trrd_derate = 3,   .trrd_derate_05T = 0,
+    .trtpd = 15,    .trtpd_05T = 0,
+    .twtpd = 17,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 10,
+    .tmrr2w_odt_on = 12,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .zqlat2 = 10,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = TBD,     .datlat = TBD
+},
+//LPDDR4 4X_1333_BT_Div 4_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 666, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    .readLat = 16,  .writeLat =  8, .DivMode =  DIV4_MODE,
+
+    .tras = 6,  .tras_05T = 0,
+    .trp = 4,   .trp_05T = 0,
+    .trpab = 5, .trpab_05T = 0,
+    .trc = 11,  .trc_05T = 0,
+    .trfc = 82, .trfc_05T = 0,
+    .trfcpb = 35,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 3,  .trtp_05T = 0,
+    .trcd = 6,  .trcd_05T = 0,
+    .twr = 15,  .twr_05T = 0,
+    .twtr = 10, .twtr_05T = 0,
+    .tpbr2pbr = 23, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 18,   .tr2mrw_05T = 0,
+    .tw2mrw = 13,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 15, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 6,  .tmrd_05T = 0,
+    .tmrwckel = 8,  .tmrwckel_05T = 0,
+    .tpde = 3,  .tpde_05T = 0,
+    .tpdx = 3,  .tpdx_05T = 0,
+    .tmrri = 9, .tmrri_05T = 0,
+    .trrd = 3,  .trrd_05T = 0,
+    .trrd_4266 = 2, .trrd_4266_05T = 0,
+    .tfaw = 6,  .tfaw_05T = 0,
+    .tfaw_4266 = 2, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 8,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 12,  .trtw_odt_on_05T = 0,
+    .txrefcnt = 96,
+    .tzqcs = 28,
+    .xrtw2w_new_mode = 9,
+    .xrtw2w_old_mode = 10,
+    .xrtw2r_odt_on = 6,
+    .xrtw2r_odt_off = 5,
+    .xrtr2w_odt_on = 11,
+    .xrtr2w_odt_off = 11,
+    .xrtr2r_new_mode = 7,
+    .xrtr2r_old_mode = 10,
+    .tr2mrr = 8,
+    .vrcgdis_prdcnt = 34,
+    .hwset_mr2_op = 18,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 7,   .trcd_derate_05T = 0,
+    .trc_derate = 13,   .trc_derate_05T = 0,
+    .tras_derate = 7,   .tras_derate_05T = 0,
+    .trpab_derate = 6,  .trpab_derate_05T = 0,
+    .trp_derate = 5,    .trp_derate_05T = 0,
+    .trrd_derate = 3,   .trrd_derate_05T = 0,
+    .trtpd = 16,    .trtpd_05T = 0,
+    .twtpd = 18,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 11,
+    .tmrr2w_odt_on = 13,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .zqlat2 = 10,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = TBD,     .datlat = TBD
+},
+//LPDDR4 4X_1333_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 666, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    .readLat = 14,  .writeLat =  8, .DivMode =  DIV8_MODE,
+
+    .tras = 0,  .tras_05T = 0,
+    .trp = 1,   .trp_05T = 1,
+    .trpab = 2, .trpab_05T = 0,
+    .trc = 1,   .trc_05T = 0,
+    .trfc = 35, .trfc_05T = 0,
+    .trfcpb = 11,   .trfcpb_05T = 1,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 0,  .trtp_05T = 1,
+    .trcd = 3,  .trcd_05T = 0,
+    .twr = 6,   .twr_05T = 0,
+    .twtr = 4,  .twtr_05T = 1,
+    .tpbr2pbr = 8,  .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 8,    .tr2mrw_05T = 1,
+    .tw2mrw = 6,    .tw2mrw_05T = 1,
+    .tmrr2mrw = 7,  .tmrr2mrw_05T = 0,
+    .tmrw = 3,  .tmrw_05T = 0,
+    .tmrd = 3,  .tmrd_05T = 0,
+    .tmrwckel = 4,  .tmrwckel_05T = 0,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 4, .tmrri_05T = 1,
+    .trrd = 1,  .trrd_05T = 0,
+    .trrd_4266 = 0, .trrd_4266_05T = 1,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tfaw_4266 = 0, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 1,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 4,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 48,
+    .tzqcs = 13,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 3,
+    .xrtw2r_odt_off = 3,
+    .xrtr2w_odt_on = 3,
+    .xrtr2w_odt_off = 3,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 6,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 17,
+    .hwset_mr2_op = 18,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 3,   .trcd_derate_05T = 1,
+    .trc_derate = 2,    .trc_derate_05T = 0,
+    .tras_derate = 0,   .tras_derate_05T = 0,
+    .trpab_derate = 2,  .trpab_derate_05T = 1,
+    .trp_derate = 2,    .trp_derate_05T = 0,
+    .trrd_derate = 1,   .trrd_derate_05T = 0,
+    .trtpd = 7, .trtpd_05T = 1,
+    .twtpd = 8, .twtpd_05T = 1,
+    .tmrr2w_odt_off = 3,
+    .tmrr2w_odt_on = 5,
+    .ckeprd = 1,
+    .ckelckcnt = 2,
+    .zqlat2 = 5,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = TBD,     .datlat = TBD
+},
+//LPDDR4 4X_1333_BT_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 666, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    .readLat = 16,  .writeLat =  8, .DivMode =  DIV8_MODE,
+
+    .tras = 0,  .tras_05T = 0,
+    .trp = 1,   .trp_05T = 1,
+    .trpab = 2, .trpab_05T = 0,
+    .trc = 1,   .trc_05T = 0,
+    .trfc = 35, .trfc_05T = 0,
+    .trfcpb = 11,   .trfcpb_05T = 1,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 0,  .trtp_05T = 1,
+    .trcd = 3,  .trcd_05T = 0,
+    .twr = 6,   .twr_05T = 1,
+    .twtr = 4,  .twtr_05T = 1,
+    .tpbr2pbr = 8,  .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 9,    .tr2mrw_05T = 0,
+    .tw2mrw = 6,    .tw2mrw_05T = 1,
+    .tmrr2mrw = 7,  .tmrr2mrw_05T = 1,
+    .tmrw = 3,  .tmrw_05T = 0,
+    .tmrd = 3,  .tmrd_05T = 0,
+    .tmrwckel = 4,  .tmrwckel_05T = 0,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 4, .tmrri_05T = 1,
+    .trrd = 1,  .trrd_05T = 0,
+    .trrd_4266 = 0, .trrd_4266_05T = 1,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tfaw_4266 = 0, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 2,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 5,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 48,
+    .tzqcs = 13,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 3,
+    .xrtw2r_odt_off = 2,
+    .xrtr2w_odt_on = 3,
+    .xrtr2w_odt_off = 3,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 6,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 17,
+    .hwset_mr2_op = 18,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 3,   .trcd_derate_05T = 1,
+    .trc_derate = 2,    .trc_derate_05T = 0,
+    .tras_derate = 0,   .tras_derate_05T = 0,
+    .trpab_derate = 2,  .trpab_derate_05T = 1,
+    .trp_derate = 2,    .trp_derate_05T = 0,
+    .trrd_derate = 1,   .trrd_derate_05T = 0,
+    .trtpd = 8, .trtpd_05T = 0,
+    .twtpd = 9, .twtpd_05T = 0,
+    .tmrr2w_odt_off = 4,
+    .tmrr2w_odt_on = 6,
+    .ckeprd = 1,
+    .ckelckcnt = 2,
+    .zqlat2 = 5,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = TBD,     .datlat = TBD
+},
+#endif
+#if SUPPORT_LP4_DDR1200_ACTIM
+    //LP4_DDR1200 ACTiming---------------------------------
+//LPDDR4 4X_1200_Div 4_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    .readLat = 14,  .writeLat =  8, .DivMode =  DIV4_MODE,
+
+    .tras = 5,  .tras_05T = 0,
+    .trp = 4,   .trp_05T = 0,
+    .trpab = 5, .trpab_05T = 0,
+    .trc = 10,  .trc_05T = 0,
+    .trfc = 73, .trfc_05T = 0,
+    .trfcpb = 31,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 3,  .trtp_05T = 0,
+    .trcd = 6,  .trcd_05T = 0,
+    .twr = 13,  .twr_05T = 0,
+    .twtr = 10, .twtr_05T = 0,
+    .tpbr2pbr = 21, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 17,   .tr2mrw_05T = 0,
+    .tw2mrw = 13,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 14, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 6,  .tmrd_05T = 0,
+    .tmrwckel = 8,  .tmrwckel_05T = 0,
+    .tpde = 3,  .tpde_05T = 0,
+    .tpdx = 3,  .tpdx_05T = 0,
+    .tmrri = 8, .tmrri_05T = 0,
+    .trrd = 3,  .trrd_05T = 0,
+    .trrd_4266 = 2, .trrd_4266_05T = 0,
+    .tfaw = 5,  .tfaw_05T = 0,
+    .tfaw_4266 = 2, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 7,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 11,  .trtw_odt_on_05T = 0,
+    .txrefcnt = 87,
+    .tzqcs = 26,
+    .xrtw2w_new_mode = 9,
+    .xrtw2w_old_mode = 10,
+    .xrtw2r_odt_on = 7,
+    .xrtw2r_odt_off = 6,
+    .xrtr2w_odt_on = 10,
+    .xrtr2w_odt_off = 10,
+    .xrtr2r_new_mode = 7,
+    .xrtr2r_old_mode = 9,
+    .tr2mrr = 8,
+    .vrcgdis_prdcnt = 31,
+    .hwset_mr2_op = 18,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 6,   .trcd_derate_05T = 0,
+    .trc_derate = 11,   .trc_derate_05T = 0,
+    .tras_derate = 6,   .tras_derate_05T = 0,
+    .trpab_derate = 5,  .trpab_derate_05T = 0,
+    .trp_derate = 4,    .trp_derate_05T = 0,
+    .trrd_derate = 3,   .trrd_derate_05T = 0,
+    .trtpd = 15,    .trtpd_05T = 0,
+    .twtpd = 17,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 10,
+    .tmrr2w_odt_on = 12,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .zqlat2 = 10,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 2,   .datlat = 9
+},
+//LPDDR4 4X_1200_BT_Div 4_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    .readLat = 16,  .writeLat =  8, .DivMode =  DIV4_MODE,
+
+    .tras = 5,  .tras_05T = 0,
+    .trp = 4,   .trp_05T = 0,
+    .trpab = 5, .trpab_05T = 0,
+    .trc = 10,  .trc_05T = 0,
+    .trfc = 73, .trfc_05T = 0,
+    .trfcpb = 31,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 3,  .trtp_05T = 0,
+    .trcd = 6,  .trcd_05T = 0,
+    .twr = 14,  .twr_05T = 0,
+    .twtr = 10, .twtr_05T = 0,
+    .tpbr2pbr = 21, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 18,   .tr2mrw_05T = 0,
+    .tw2mrw = 13,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 15, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 6,  .tmrd_05T = 0,
+    .tmrwckel = 8,  .tmrwckel_05T = 0,
+    .tpde = 3,  .tpde_05T = 0,
+    .tpdx = 3,  .tpdx_05T = 0,
+    .tmrri = 8, .tmrri_05T = 0,
+    .trrd = 3,  .trrd_05T = 0,
+    .trrd_4266 = 2, .trrd_4266_05T = 0,
+    .tfaw = 5,  .tfaw_05T = 0,
+    .tfaw_4266 = 2, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 8,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 12,  .trtw_odt_on_05T = 0,
+    .txrefcnt = 87,
+    .tzqcs = 26,
+    .xrtw2w_new_mode = 9,
+    .xrtw2w_old_mode = 10,
+    .xrtw2r_odt_on = 6,
+    .xrtw2r_odt_off = 5,
+    .xrtr2w_odt_on = 11,
+    .xrtr2w_odt_off = 11,
+    .xrtr2r_new_mode = 7,
+    .xrtr2r_old_mode = 10,
+    .tr2mrr = 8,
+    .vrcgdis_prdcnt = 31,
+    .hwset_mr2_op = 18,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 6,   .trcd_derate_05T = 0,
+    .trc_derate = 11,   .trc_derate_05T = 0,
+    .tras_derate = 6,   .tras_derate_05T = 0,
+    .trpab_derate = 5,  .trpab_derate_05T = 0,
+    .trp_derate = 4,    .trp_derate_05T = 0,
+    .trrd_derate = 3,   .trrd_derate_05T = 0,
+    .trtpd = 16,    .trtpd_05T = 0,
+    .twtpd = 18,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 11,
+    .tmrr2w_odt_on = 13,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .zqlat2 = 10,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 2,   .datlat = 9
+},
+//LPDDR4 4X_1200_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    .readLat = 14,  .writeLat =  8, .DivMode =  DIV8_MODE,
+
+    .tras = 0,  .tras_05T = 0,
+    .trp = 1,   .trp_05T = 1,
+    .trpab = 2, .trpab_05T = 0,
+    .trc = 0,   .trc_05T = 1,
+    .trfc = 30, .trfc_05T = 1,
+    .trfcpb = 9,    .trfcpb_05T = 1,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 0,  .trtp_05T = 1,
+    .trcd = 3,  .trcd_05T = 0,
+    .twr = 6,   .twr_05T = 1,
+    .twtr = 4,  .twtr_05T = 1,
+    .tpbr2pbr = 7,  .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 8,    .tr2mrw_05T = 1,
+    .tw2mrw = 6,    .tw2mrw_05T = 1,
+    .tmrr2mrw = 7,  .tmrr2mrw_05T = 0,
+    .tmrw = 3,  .tmrw_05T = 0,
+    .tmrd = 3,  .tmrd_05T = 0,
+    .tmrwckel = 4,  .tmrwckel_05T = 0,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 4, .tmrri_05T = 0,
+    .trrd = 1,  .trrd_05T = 0,
+    .trrd_4266 = 0, .trrd_4266_05T = 1,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tfaw_4266 = 0, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 1,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 4,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 44,
+    .tzqcs = 12,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 3,
+    .xrtw2r_odt_off = 3,
+    .xrtr2w_odt_on = 3,
+    .xrtr2w_odt_off = 3,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 6,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 16,
+    .hwset_mr2_op = 18,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 3,   .trcd_derate_05T = 0,
+    .trc_derate = 1,    .trc_derate_05T = 0,
+    .tras_derate = 0,   .tras_derate_05T = 0,
+    .trpab_derate = 2,  .trpab_derate_05T = 0,
+    .trp_derate = 1,    .trp_derate_05T = 1,
+    .trrd_derate = 1,   .trrd_derate_05T = 0,
+    .trtpd = 7, .trtpd_05T = 1,
+    .twtpd = 8, .twtpd_05T = 1,
+    .tmrr2w_odt_off = 3,
+    .tmrr2w_odt_on = 5,
+    .ckeprd = 1,
+    .ckelckcnt = 2,
+    .zqlat2 = 5,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 2,   .datlat = 9
+},
+//LPDDR4 4X_1200_BT_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    .readLat = 16,  .writeLat =  8, .DivMode =  DIV8_MODE,
+
+    .tras = 0,  .tras_05T = 0,
+    .trp = 1,   .trp_05T = 1,
+    .trpab = 2, .trpab_05T = 0,
+    .trc = 0,   .trc_05T = 1,
+    .trfc = 30, .trfc_05T = 1,
+    .trfcpb = 9,    .trfcpb_05T = 1,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 0,  .trtp_05T = 1,
+    .trcd = 3,  .trcd_05T = 0,
+    .twr = 6,   .twr_05T = 0,
+    .twtr = 4,  .twtr_05T = 1,
+    .tpbr2pbr = 7,  .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 9,    .tr2mrw_05T = 0,
+    .tw2mrw = 6,    .tw2mrw_05T = 1,
+    .tmrr2mrw = 7,  .tmrr2mrw_05T = 1,
+    .tmrw = 3,  .tmrw_05T = 0,
+    .tmrd = 3,  .tmrd_05T = 0,
+    .tmrwckel = 4,  .tmrwckel_05T = 0,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 4, .tmrri_05T = 0,
+    .trrd = 1,  .trrd_05T = 0,
+    .trrd_4266 = 0, .trrd_4266_05T = 1,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tfaw_4266 = 0, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 2,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 5,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 44,
+    .tzqcs = 12,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 3,
+    .xrtw2r_odt_off = 2,
+    .xrtr2w_odt_on = 3,
+    .xrtr2w_odt_off = 3,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 6,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 16,
+    .hwset_mr2_op = 18,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 3,   .trcd_derate_05T = 0,
+    .trc_derate = 1,    .trc_derate_05T = 0,
+    .tras_derate = 0,   .tras_derate_05T = 0,
+    .trpab_derate = 2,  .trpab_derate_05T = 0,
+    .trp_derate = 1,    .trp_derate_05T = 1,
+    .trrd_derate = 1,   .trrd_derate_05T = 0,
+    .trtpd = 8, .trtpd_05T = 0,
+    .twtpd = 9, .twtpd_05T = 0,
+    .tmrr2w_odt_off = 4,
+    .tmrr2w_odt_on = 6,
+    .ckeprd = 1,
+    .ckelckcnt = 2,
+    .zqlat2 = 5,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 2,   .datlat = 9
+},
+#endif
+#if SUPPORT_LP4_DDR800_ACTIM
+    //LP4_DDR800 ACTiming---------------------------------
+//LPDDR4 4X_800_Div 4_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 400, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    .readLat = 14,  .writeLat =  8, .DivMode =  DIV4_MODE,
+
+    .tras = 1,  .tras_05T = 0,
+    .trp = 2,   .trp_05T = 0,
+    .trpab = 3, .trpab_05T = 0,
+    .trc = 3,   .trc_05T = 0,
+    .trfc = 44, .trfc_05T = 0,
+    .trfcpb = 16,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 3,  .trtp_05T = 0,
+    .trcd = 4,  .trcd_05T = 0,
+    .twr = 12,  .twr_05T = 0,
+    .twtr = 10, .twtr_05T = 0,
+    .tpbr2pbr = 11, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 16,   .tr2mrw_05T = 0,
+    .tw2mrw = 13,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 14, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 6,  .tmrd_05T = 0,
+    .tmrwckel = 8,  .tmrwckel_05T = 0,
+    .tpde = 3,  .tpde_05T = 0,
+    .tpdx = 3,  .tpdx_05T = 0,
+    .tmrri = 7, .tmrri_05T = 0,
+    .trrd = 1,  .trrd_05T = 0,
+    .trrd_4266 = 1, .trrd_4266_05T = 0,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tfaw_4266 = 0, .tfaw_4266_05T = 0,
+    .trtw_odt_off =5,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 9,  .trtw_odt_on_05T = 0,
+    .txrefcnt = 58,
+    .tzqcs = 16,
+    .xrtw2w_new_mode = 9,
+    .xrtw2w_old_mode = 10,
+    .xrtw2r_odt_on = 7,
+    .xrtw2r_odt_off = 5,
+    .xrtr2w_odt_on = 9,
+    .xrtr2w_odt_off = 9,
+    .xrtr2r_new_mode = 6,
+    .xrtr2r_old_mode = 8,
+    .tr2mrr = 8,
+    .vrcgdis_prdcnt = 20,
+    .hwset_mr2_op = 9,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 4,   .trcd_derate_05T = 0,
+    .trc_derate = 4,    .trc_derate_05T = 0,
+    .tras_derate = 1,   .tras_derate_05T = 0,
+    .trpab_derate = 3,  .trpab_derate_05T = 0,
+    .trp_derate = 2,    .trp_derate_05T = 0,
+    .trrd_derate = 2,   .trrd_derate_05T = 0,
+    .trtpd = 15,    .trtpd_05T = 0,
+    .twtpd = 15,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 10,
+    .tmrr2w_odt_on = 12,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .zqlat2 = 6,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 4,   .datlat = 15
+},
+//LPDDR4 4X_800_BT_Div 4_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 400, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    .readLat = 16,  .writeLat =  8, .DivMode =  DIV4_MODE,
+
+    .tras = 1,  .tras_05T = 0,
+    .trp = 2,   .trp_05T = 0,
+    .trpab = 3, .trpab_05T = 0,
+    .trc = 3,   .trc_05T = 0,
+    .trfc = 44, .trfc_05T = 0,
+    .trfcpb = 16,   .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 3,  .trtp_05T = 0,
+    .trcd = 4,  .trcd_05T = 0,
+    .twr = 12,  .twr_05T = 0,
+    .twtr = 10, .twtr_05T = 0,
+    .tpbr2pbr = 11, .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 17,   .tr2mrw_05T = 0,
+    .tw2mrw = 13,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 15, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 6,  .tmrd_05T = 0,
+    .tmrwckel = 8,  .tmrwckel_05T = 0,
+    .tpde = 3,  .tpde_05T = 0,
+    .tpdx = 3,  .tpdx_05T = 0,
+    .tmrri = 7, .tmrri_05T = 0,
+    .trrd = 1,  .trrd_05T = 0,
+    .trrd_4266 = 1, .trrd_4266_05T = 0,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tfaw_4266 = 0, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 7,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 12,  .trtw_odt_on_05T = 0,
+    .txrefcnt = 58,
+    .tzqcs = 16,
+    .xrtw2w_new_mode = 9,
+    .xrtw2w_old_mode = 10,
+    .xrtw2r_odt_on = 6,
+    .xrtw2r_odt_off = 4,
+    .xrtr2w_odt_on = 10,
+    .xrtr2w_odt_off = 10,
+    .xrtr2r_new_mode = 6,
+    .xrtr2r_old_mode = 9,
+    .tr2mrr = 8,
+    .vrcgdis_prdcnt = 20,
+    .hwset_mr2_op = 9,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 4,   .trcd_derate_05T = 0,
+    .trc_derate = 4,    .trc_derate_05T = 0,
+    .tras_derate = 1,   .tras_derate_05T = 0,
+    .trpab_derate = 3,  .trpab_derate_05T = 0,
+    .trp_derate = 2,    .trp_derate_05T = 0,
+    .trrd_derate = 2,   .trrd_derate_05T = 0,
+    .trtpd = 16,    .trtpd_05T = 0,
+    .twtpd = 15,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 11,
+    .tmrr2w_odt_on = 13,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .zqlat2 = 6,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 4,   .datlat = 15
+},
+//LPDDR4 4X_800_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 400, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    .readLat = 14,  .writeLat =  8, .DivMode =  DIV8_MODE,
+
+    .tras = 0,  .tras_05T = 0,
+    .trp = 0,   .trp_05T = 1,
+    .trpab = 1, .trpab_05T = 0,
+    .trc = 0,   .trc_05T = 0,
+    .trfc = 16, .trfc_05T = 0,
+    .trfcpb = 2,    .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 0,  .trtp_05T = 1,
+    .trcd = 2,  .trcd_05T = 0,
+    .twr = 5,   .twr_05T = 0,
+    .twtr = 4,  .twtr_05T = 1,
+    .tpbr2pbr = 2,  .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 8,    .tr2mrw_05T = 0,
+    .tw2mrw = 6,    .tw2mrw_05T = 1,
+    .tmrr2mrw = 7,  .tmrr2mrw_05T = 0,
+    .tmrw = 3,  .tmrw_05T = 0,
+    .tmrd = 3,  .tmrd_05T = 0,
+    .tmrwckel = 4,  .tmrwckel_05T = 0,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 3, .tmrri_05T = 1,
+    .trrd = 0,  .trrd_05T = 0,
+    .trrd_4266 = 0, .trrd_4266_05T = 0,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tfaw_4266 = 0, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 1,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 4,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 29,
+    .tzqcs = 7,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 3,
+    .xrtw2r_odt_off = 2,
+    .xrtr2w_odt_on = 2,
+    .xrtr2w_odt_off = 2,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 6,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 10,
+    .hwset_mr2_op = 18,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 2,   .trcd_derate_05T = 0,
+    .trc_derate = 0,    .trc_derate_05T = 0,
+    .tras_derate = 0,   .tras_derate_05T = 0,
+    .trpab_derate = 1,  .trpab_derate_05T = 0,
+    .trp_derate = 0,    .trp_derate_05T = 1,
+    .trrd_derate = 0,   .trrd_derate_05T = 1,
+    .trtpd = 7, .trtpd_05T = 1,
+    .twtpd = 7, .twtpd_05T = 1,
+    .tmrr2w_odt_off = 3,
+    .tmrr2w_odt_on = 5,
+    .ckeprd = 1,
+    .ckelckcnt = 2,
+    .zqlat2 = 3,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 5,   .datlat = 15
+},
+//LPDDR4 4X_800_BT_Div 8_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 400, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    .readLat = 16,  .writeLat =  8, .DivMode =  DIV8_MODE,
+
+    .tras = 0,  .tras_05T = 0,
+    .trp = 0,   .trp_05T = 1,
+    .trpab = 1, .trpab_05T = 0,
+    .trc = 0,   .trc_05T = 0,
+    .trfc = 16, .trfc_05T = 0,
+    .trfcpb = 2,    .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 0,  .trtp_05T = 1,
+    .trcd = 2,  .trcd_05T = 0,
+    .twr = 5,   .twr_05T = 0,
+    .twtr = 4,  .twtr_05T = 1,
+    .tpbr2pbr = 2,  .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 8,    .tr2mrw_05T = 1,
+    .tw2mrw = 6,    .tw2mrw_05T = 1,
+    .tmrr2mrw = 7,  .tmrr2mrw_05T = 1,
+    .tmrw = 3,  .tmrw_05T = 0,
+    .tmrd = 3,  .tmrd_05T = 0,
+    .tmrwckel = 4,  .tmrwckel_05T = 0,
+    .tpde = 1,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 0,
+    .tmrri = 3, .tmrri_05T = 1,
+    .trrd = 0,  .trrd_05T = 0,
+    .trrd_4266 = 0, .trrd_4266_05T = 0,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tfaw_4266 = 0, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 2,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 4,   .trtw_odt_on_05T = 0,
+    .txrefcnt = 29,
+    .tzqcs = 7,
+    .xrtw2w_new_mode = 4,
+    .xrtw2w_old_mode = 6,
+    .xrtw2r_odt_on = 3,
+    .xrtw2r_odt_off = 2,
+    .xrtr2w_odt_on = 3,
+    .xrtr2w_odt_off = 3,
+    .xrtr2r_new_mode = 3,
+    .xrtr2r_old_mode = 6,
+    .tr2mrr = 4,
+    .vrcgdis_prdcnt = 10,
+    .hwset_mr2_op = 18,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 2,   .trcd_derate_05T = 0,
+    .trc_derate = 0,    .trc_derate_05T = 0,
+    .tras_derate = 0,   .tras_derate_05T = 0,
+    .trpab_derate = 1,  .trpab_derate_05T = 0,
+    .trp_derate = 0,    .trp_derate_05T = 1,
+    .trrd_derate = 0,   .trrd_derate_05T = 1,
+    .trtpd = 8, .trtpd_05T = 0,
+    .twtpd = 7, .twtpd_05T = 1,
+    .tmrr2w_odt_off = 4,
+    .tmrr2w_odt_on = 6,
+    .ckeprd = 1,
+    .ckelckcnt = 2,
+    .zqlat2 = 3,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 5,   .datlat = 15
+},
+#endif
+#if SUPPORT_LP4_DDR400_ACTIM
+    //LP4_DDR400 ACTiming---------------------------------
+//LPDDR4 4X_400_Div 4_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 200, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    .readLat = 14,  .writeLat =  8, .DivMode =  DIV4_MODE,
+
+    .tras = 0,  .tras_05T = 0,
+    .trp = 0,   .trp_05T = 0,
+    .trpab = 1, .trpab_05T = 0,
+    .trc = 0,   .trc_05T = 0,
+    .trfc = 16, .trfc_05T = 0,
+    .trfcpb = 2,    .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 3,  .trtp_05T = 0,
+    .trcd = 2,  .trcd_05T = 0,
+    .twr = 11,  .twr_05T = 0,
+    .twtr = 10, .twtr_05T = 0,
+    .tpbr2pbr = 2,  .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 16,   .tr2mrw_05T = 0,
+    .tw2mrw = 13,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 13, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 6,  .tmrd_05T = 0,
+    .tmrwckel = 8,  .tmrwckel_05T = 0,
+    .tpde = 3,  .tpde_05T = 0,
+    .tpdx = 3,  .tpdx_05T = 0,
+    .tmrri = 5, .tmrri_05T = 0,
+    .trrd = 1,  .trrd_05T = 0,
+    .trrd_4266 = 1, .trrd_4266_05T = 0,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tfaw_4266 = 0, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 6,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 10,  .trtw_odt_on_05T = 0,
+    .txrefcnt = 29,
+    .tzqcs = 7,
+    .xrtw2w_new_mode = 10,
+    .xrtw2w_old_mode = 10,
+    .xrtw2r_odt_on = 8,
+    .xrtw2r_odt_off = 8,
+    .xrtr2w_odt_on = 9,
+    .xrtr2w_odt_off = 9,
+    .xrtr2r_new_mode = 6,
+    .xrtr2r_old_mode = 8,
+    .tr2mrr = 8,
+    .vrcgdis_prdcnt = 10,
+    .hwset_mr2_op = 0,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 2,   .trcd_derate_05T = 0,
+    .trc_derate = 0,    .trc_derate_05T = 0,
+    .tras_derate = 0,   .tras_derate_05T = 0,
+    .trpab_derate = 1,  .trpab_derate_05T = 0,
+    .trp_derate = 0,    .trp_derate_05T = 0,
+    .trrd_derate = 1,   .trrd_derate_05T = 0,
+    .trtpd = 14,    .trtpd_05T = 0,
+    .twtpd = 14,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 9,
+    .tmrr2w_odt_on = 11,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .zqlat2 = 4,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 2,   .datlat = 15
+},
+//LPDDR4 4X_400_BT_Div 4_DBI0.csv Read 0
+{
+    .dramType = TYPE_LPDDR4, .freq = 200, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    .readLat = 16,  .writeLat =  8, .DivMode =  DIV4_MODE,
+
+    .tras = 0,  .tras_05T = 0,
+    .trp = 0,   .trp_05T = 0,
+    .trpab = 1, .trpab_05T = 0,
+    .trc = 0,   .trc_05T = 0,
+    .trfc = 16, .trfc_05T = 0,
+    .trfcpb = 2,    .trfcpb_05T = 0,
+    .txp = 0,   .txp_05T = 0,
+    .trtp = 3,  .trtp_05T = 0,
+    .trcd = 2,  .trcd_05T = 0,
+    .twr = 11,  .twr_05T = 0,
+    .twtr = 10, .twtr_05T = 0,
+    .tpbr2pbr = 2,  .tpbr2pbr_05T = 0,
+    .tpbr2act = 0,  .tpbr2act_05T = 0,
+    .tr2mrw = 17,   .tr2mrw_05T = 0,
+    .tw2mrw = 13,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 14, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 6,  .tmrd_05T = 0,
+    .tmrwckel = 8,  .tmrwckel_05T = 0,
+    .tpde = 3,  .tpde_05T = 0,
+    .tpdx = 3,  .tpdx_05T = 0,
+    .tmrri = 5, .tmrri_05T = 0,
+    .trrd = 1,  .trrd_05T = 0,
+    .trrd_4266 = 1, .trrd_4266_05T = 0,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tfaw_4266 = 0, .tfaw_4266_05T = 0,
+    .trtw_odt_off = 7,  .trtw_odt_off_05T = 0,
+    .trtw_odt_on = 11,  .trtw_odt_on_05T = 0,
+    .txrefcnt = 29,
+    .tzqcs = 7,
+    .xrtw2w_new_mode = 10,
+    .xrtw2w_old_mode = 10,
+    .xrtw2r_odt_on = 7,
+    .xrtw2r_odt_off = 7,
+    .xrtr2w_odt_on = 10,
+    .xrtr2w_odt_off = 10,
+    .xrtr2r_new_mode = 6,
+    .xrtr2r_old_mode = 9,
+    .tr2mrr = 8,
+    .vrcgdis_prdcnt = 10,
+    .hwset_mr2_op = 0,
+    .hwset_mr13_op = 24,
+    .hwset_vrcg_op = 16,
+    .trcd_derate = 2,   .trcd_derate_05T = 0,
+    .trc_derate = 0,    .trc_derate_05T = 0,
+    .tras_derate = 0,   .tras_derate_05T = 0,
+    .trpab_derate = 1,  .trpab_derate_05T = 0,
+    .trp_derate = 0,    .trp_derate_05T = 0,
+    .trrd_derate = 1,   .trrd_derate_05T = 0,
+    .trtpd = 15,    .trtpd_05T = 0,
+    .twtpd = 14,    .twtpd_05T = 0,
+    .tmrr2w_odt_off = 10,
+    .tmrr2w_odt_on = 12,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .zqlat2 = 4,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 2,   .datlat = 15
+},
+#endif
+};
+
+#if (__LP5_COMBO__)
+    static const ACTime_T_LP5 ACTimingTbl_LP5[AC_TIMING_NUMBER_LP5] = {
+    //----------LPDDR5---------------------------
+    #if SUPPORT_LP5_DDR6400_ACTIM
+    //LP5_DDR6400 ACTiming---------------------------------
+    #if (ENABLE_READ_DBI == 1)
+    //LPDDR5_6400_Div 16_DBI1.csv Read 1
+    {
+    .dramType = TYPE_LPDDR5, .freq = 3200, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1,
+
+    //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
+    .readLat = 20, .writeLat =  9, .DivMode = DIV16_MODE,
+
+    .tras = 8,  .tras_05T = 0,
+    .trp = 7,   .trp_05T = 1,
+    .trpab = 8, .trpab_05T = 1,
+    .trc = 16,  .trc_05T = 1,
+    .trfc = 100,    .trfc_05T = 0,
+    .trfcpb = 44,   .trfcpb_05T = 0,
+    .txp = 2,   .txp_05T = 1,
+    .trtp = 1,  .trtp_05T = 1,
+    .trcd = 7,  .trcd_05T = 1,
+    .twr = 19,  .twr_05T = 0,
+    .twtr = 6,  .twtr_05T = 0,
+    .twtr_l = 10,   .twtr_l_05T = 0,
+    .tpbr2pbr = 28, .tpbr2pbr_05T = 0,
+    .tpbr2act = 2,  .tpbr2act_05T = 0,
+    .tr2mrw = 15,   .tr2mrw_05T = 0,
+    .tw2mrw = 8,    .tw2mrw_05T = 1,
+    .tmrr2mrw = 13, .tmrr2mrw_05T = 0,
+    .tmrw = 4,  .tmrw_05T = 0,
+    .tmrd = 6,  .tmrd_05T = 1,
+    .tmrwckel = 8,  .tmrwckel_05T = 1,
+    .tpde = 2,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 1,
+    .tmrri = 12,    .tmrri_05T = 0,
+    .trrd = 2,  .trrd_05T = 0,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tr2w_odt_off = 5,  .tr2w_odt_off_05T = 1,
+    .tr2w_odt_on = 7,   .tr2w_odt_on_05T = 0,
+    .txrefcnt = 115,
+    .wckrdoff = 13, .wckrdoff_05T = 0,
+    .wckwroff = 7,  .wckwroff_05T = 1,
+    .tzqcs = 34,
+    .xrtw2w_odt_off = 2,
+    .xrtw2w_odt_on = 3,
+    .xrtw2r_odt_off_otf_off = 0,
+    .xrtw2r_odt_on_otf_off = 0,
+    .xrtw2r_odt_off_otf_on = 3,
+    .xrtw2r_odt_on_otf_on = 3,
+    .xrtr2w_odt_off = 8,
+    .xrtr2w_odt_on = 9,
+    .xrtr2r_odt_off = 6,
+    .xrtr2r_odt_on = 6,
+    .xrtw2w_odt_off_wck = 6,
+    .xrtw2w_odt_on_wck = 8,
+    .xrtw2r_odt_off_wck = 3,
+    .xrtw2r_odt_on_wck = 4,
+    .xrtr2w_odt_off_wck = 11,
+    .xrtr2w_odt_on_wck = 11,
+    .xrtr2r_wck = 8,
+    .tr2mrr = 4,
+    .hwset_mr2_op = 187,
+    .hwset_mr13_op = 74,
+    .hwset_vrcg_op = 176,
+    .vrcgdis_prdcnt = 40,
+    .lp5_cmd1to2en = 0,
+    .trtpd = 13,    .trtpd_05T = 1,
+    .twtpd = 21,    .twtpd_05T = 1,
+    .tmrr2w = 16,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .tcsh_cscal = 3,
+    .tcacsh = 2,
+    .tcsh = 5,
+    .trcd_derate = 8,   .trcd_derate_05T = 0,
+    .trc_derate = 17,   .trc_derate_05T = 0,
+    .tras_derate = 10,  .tras_derate_05T = 0,
+    .trpab_derate = 7,  .trpab_derate_05T = 1,
+    .trp_derate = 6,    .trp_derate_05T = 0,
+    .trrd_derate = 2,   .trrd_derate_05T = 0,
+    .zqlat2 = 12,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 7,  .datlat = 10
+    },
+    //LPDDR5_6400_BT_Div 16_DBI1.csv Read 1
+    {
+    .dramType = TYPE_LPDDR5, .freq = 3200, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1,
+    //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
+    .readLat = 18, .writeLat =  9, .DivMode = DIV16_MODE,
+
+    .tras = 8,  .tras_05T = 0,
+    .trp = 7,   .trp_05T = 1,
+    .trpab = 8, .trpab_05T = 1,
+    .trc = 16,  .trc_05T = 1,
+    .trfc = 100,    .trfc_05T = 0,
+    .trfcpb = 44,   .trfcpb_05T = 0,
+    .txp = 2,   .txp_05T = 1,
+    .trtp = 1,  .trtp_05T = 1,
+    .trcd = 7,  .trcd_05T = 1,
+    .twr = 18,  .twr_05T = 1,
+    .twtr = 5,  .twtr_05T = 0,
+    .twtr_l = 9,    .twtr_l_05T = 0,
+    .tpbr2pbr = 28, .tpbr2pbr_05T = 0,
+    .tpbr2act = 2,  .tpbr2act_05T = 0,
+    .tr2mrw = 14,   .tr2mrw_05T = 0,
+    .tw2mrw = 8,    .tw2mrw_05T = 1,
+    .tmrr2mrw = 12, .tmrr2mrw_05T = 0,
+    .tmrw = 4,  .tmrw_05T = 0,
+    .tmrd = 6,  .tmrd_05T = 1,
+    .tmrwckel = 8,  .tmrwckel_05T = 1,
+    .tpde = 2,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 1,
+    .tmrri = 12,    .tmrri_05T = 0,
+    .trrd = 2,  .trrd_05T = 0,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tr2w_odt_off = 4,  .tr2w_odt_off_05T = 1,
+    .tr2w_odt_on = 6,   .tr2w_odt_on_05T = 0,
+    .txrefcnt = 115,
+    .wckrdoff = 12, .wckrdoff_05T = 0,
+    .wckwroff = 7,  .wckwroff_05T = 1,
+    .tzqcs = 34,
+    .xrtw2w_odt_off = 2,
+    .xrtw2w_odt_on = 3,
+    .xrtw2r_odt_off_otf_off = 0,
+    .xrtw2r_odt_on_otf_off = 0,
+    .xrtw2r_odt_off_otf_on = 3,
+    .xrtw2r_odt_on_otf_on = 3,
+    .xrtr2w_odt_off = 7,
+    .xrtr2w_odt_on = 8,
+    .xrtr2r_odt_off = 6,
+    .xrtr2r_odt_on = 6,
+    .xrtw2w_odt_off_wck = 6,
+    .xrtw2w_odt_on_wck = 8,
+    .xrtw2r_odt_off_wck = 4,
+    .xrtw2r_odt_on_wck = 5,
+    .xrtr2w_odt_off_wck = 10,
+    .xrtr2w_odt_on_wck = 10,
+    .xrtr2r_wck = 8,
+    .tr2mrr = 3,
+    .hwset_mr2_op = 187,
+    .hwset_mr13_op = 74,
+    .hwset_vrcg_op = 176,
+    .vrcgdis_prdcnt = 40,
+    .lp5_cmd1to2en = 0,
+    .trtpd = 12,    .trtpd_05T = 1,
+    .twtpd = 21,    .twtpd_05T = 0,
+    .tmrr2w = 15,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .tcsh_cscal = 3,
+    .tcacsh = 2,
+    .tcsh = 5,
+    .trcd_derate = 8,   .trcd_derate_05T = 0,
+    .trc_derate = 17,   .trc_derate_05T = 0,
+    .tras_derate = 10,  .tras_derate_05T = 0,
+    .trpab_derate = 7,  .trpab_derate_05T = 1,
+    .trp_derate = 6,    .trp_derate_05T = 0,
+    .trrd_derate = 2,   .trrd_derate_05T = 0,
+    .zqlat2 = 12,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 7,  .datlat = 10
+    },
+    #else  //ENABLE_READ_DBI == 0)
+    //LPDDR5_6400_Div 16_DBI0.csv Read 0
+    {
+    .dramType = TYPE_LPDDR5, .freq = 3200, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
+    .readLat = 18, .writeLat =  9, .DivMode = DIV16_MODE,
+
+    .tras = 8,  .tras_05T = 0,
+    .trp = 7,   .trp_05T = 1,
+    .trpab = 8, .trpab_05T = 1,
+    .trc = 16,  .trc_05T = 1,
+    .trfc = 100,    .trfc_05T = 0,
+    .trfcpb = 44,   .trfcpb_05T = 0,
+    .txp = 2,   .txp_05T = 1,
+    .trtp = 1,  .trtp_05T = 1,
+    .trcd = 7,  .trcd_05T = 1,
+    .twr = 19,  .twr_05T = 0,
+    .twtr = 6,  .twtr_05T = 0,
+    .twtr_l = 10,   .twtr_l_05T = 0,
+    .tpbr2pbr = 28, .tpbr2pbr_05T = 0,
+    .tpbr2act = 2,  .tpbr2act_05T = 0,
+    .tr2mrw = 14,   .tr2mrw_05T = 0,
+    .tw2mrw = 8,    .tw2mrw_05T = 1,
+    .tmrr2mrw = 12, .tmrr2mrw_05T = 0,
+    .tmrw = 4,  .tmrw_05T = 0,
+    .tmrd = 6,  .tmrd_05T = 1,
+    .tmrwckel = 8,  .tmrwckel_05T = 1,
+    .tpde = 2,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 1,
+    .tmrri = 12,    .tmrri_05T = 0,
+    .trrd = 2,  .trrd_05T = 0,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tr2w_odt_off = 4,  .tr2w_odt_off_05T = 1,
+    .tr2w_odt_on = 6,   .tr2w_odt_on_05T = 0,
+    .txrefcnt = 115,
+    .wckrdoff = 12, .wckrdoff_05T = 0,
+    .wckwroff = 7,  .wckwroff_05T = 1,
+    .tzqcs = 34,
+    .xrtw2w_odt_off = 2,
+    .xrtw2w_odt_on = 3,
+    .xrtw2r_odt_off_otf_off = 0,
+    .xrtw2r_odt_on_otf_off = 0,
+    .xrtw2r_odt_off_otf_on = 3,
+    .xrtw2r_odt_on_otf_on = 3,
+    .xrtr2w_odt_off = 7,
+    .xrtr2w_odt_on = 8,
+    .xrtr2r_odt_off = 6,
+    .xrtr2r_odt_on = 6,
+    .xrtw2w_odt_off_wck = 6,
+    .xrtw2w_odt_on_wck = 8,
+    .xrtw2r_odt_off_wck = 4,
+    .xrtw2r_odt_on_wck = 5,
+    .xrtr2w_odt_off_wck = 10,
+    .xrtr2w_odt_on_wck = 10,
+    .xrtr2r_wck = 8,
+    .tr2mrr = 3,
+    .hwset_mr2_op = 187,
+    .hwset_mr13_op = 74,
+    .hwset_vrcg_op = 176,
+    .vrcgdis_prdcnt = 40,
+    .lp5_cmd1to2en = 0,
+    .trtpd = 12,    .trtpd_05T = 1,
+    .twtpd = 21,    .twtpd_05T = 1,
+    .tmrr2w = 15,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .tcsh_cscal = 3,
+    .tcacsh = 2,
+    .tcsh = 5,
+    .trcd_derate = 8,   .trcd_derate_05T = 0,
+    .trc_derate = 17,   .trc_derate_05T = 0,
+    .tras_derate = 10,  .tras_derate_05T = 0,
+    .trpab_derate = 7,  .trpab_derate_05T = 1,
+    .trp_derate = 6,    .trp_derate_05T = 0,
+    .trrd_derate = 2,   .trrd_derate_05T = 0,
+    .zqlat2 = 12,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 7,  .datlat = 10
+    },
+    //LPDDR5_6400_BT_Div 16_DBI0.csv Read 0
+    {
+    .dramType = TYPE_LPDDR5, .freq = 3200, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
+    .readLat = 17, .writeLat =  9, .DivMode = DIV16_MODE,
+
+    .tras = 8,  .tras_05T = 0,
+    .trp = 7,   .trp_05T = 1,
+    .trpab = 8, .trpab_05T = 1,
+    .trc = 16,  .trc_05T = 1,
+    .trfc = 100,    .trfc_05T = 0,
+    .trfcpb = 44,   .trfcpb_05T = 0,
+    .txp = 2,   .txp_05T = 1,
+    .trtp = 1,  .trtp_05T = 1,
+    .trcd = 7,  .trcd_05T = 1,
+    .twr = 18,  .twr_05T = 1,
+    .twtr = 5,  .twtr_05T = 0,
+    .twtr_l = 9,    .twtr_l_05T = 0,
+    .tpbr2pbr = 28, .tpbr2pbr_05T = 0,
+    .tpbr2act = 2,  .tpbr2act_05T = 0,
+    .tr2mrw = 13,   .tr2mrw_05T = 1,
+    .tw2mrw = 8,    .tw2mrw_05T = 1,
+    .tmrr2mrw = 11, .tmrr2mrw_05T = 1,
+    .tmrw = 4,  .tmrw_05T = 0,
+    .tmrd = 6,  .tmrd_05T = 1,
+    .tmrwckel = 8,  .tmrwckel_05T = 1,
+    .tpde = 2,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 1,
+    .tmrri = 12,    .tmrri_05T = 0,
+    .trrd = 2,  .trrd_05T = 0,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tr2w_odt_off = 4,  .tr2w_odt_off_05T = 0,
+    .tr2w_odt_on = 5,   .tr2w_odt_on_05T = 1,
+    .txrefcnt = 115,
+    .wckrdoff = 11, .wckrdoff_05T = 1,
+    .wckwroff = 7,  .wckwroff_05T = 1,
+    .tzqcs = 34,
+    .xrtw2w_odt_off = 2,
+    .xrtw2w_odt_on = 3,
+    .xrtw2r_odt_off_otf_off = 0,
+    .xrtw2r_odt_on_otf_off = 0,
+    .xrtw2r_odt_off_otf_on = 3,
+    .xrtw2r_odt_on_otf_on = 3,
+    .xrtr2w_odt_off = 7,
+    .xrtr2w_odt_on = 7,
+    .xrtr2r_odt_off = 6,
+    .xrtr2r_odt_on = 6,
+    .xrtw2w_odt_off_wck = 6,
+    .xrtw2w_odt_on_wck = 8,
+    .xrtw2r_odt_off_wck = 4,
+    .xrtw2r_odt_on_wck = 5,
+    .xrtr2w_odt_off_wck = 10,
+    .xrtr2w_odt_on_wck = 10,
+    .xrtr2r_wck = 8,
+    .tr2mrr = 2,
+    .hwset_mr2_op = 187,
+    .hwset_mr13_op = 74,
+    .hwset_vrcg_op = 176,
+    .vrcgdis_prdcnt = 40,
+    .lp5_cmd1to2en = 0,
+    .trtpd = 12,    .trtpd_05T = 0,
+    .twtpd = 21,    .twtpd_05T = 0,
+    .tmrr2w = 15,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .tcsh_cscal = 3,
+    .tcacsh = 2,
+    .tcsh = 5,
+    .trcd_derate = 8,   .trcd_derate_05T = 0,
+    .trc_derate = 17,   .trc_derate_05T = 0,
+    .tras_derate = 10,  .tras_derate_05T = 0,
+    .trpab_derate = 7,  .trpab_derate_05T = 1,
+    .trp_derate = 6,    .trp_derate_05T = 0,
+    .trrd_derate = 2,   .trrd_derate_05T = 0,
+    .zqlat2 = 12,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 7,  .datlat = 10
+    },
+    #endif
+    #endif
+    #if SUPPORT_LP5_DDR5500_ACTIM
+    //LP5_DDR5500 ACTiming---------------------------------
+    #if ((ENABLE_READ_DBI == 1) || (LP5_DDR4266_RDBI_WORKAROUND == 1))
+    //F5500_Div16_DB1_NT0_RG0_EC0.csv Read 1
+    {
+    .dramType = TYPE_LPDDR5, .freq = 2750, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1,
+
+    //BL (burst length) = 16, DRMC_Clock_Rate = 343.75
+    .readLat = 17, .writeLat =  8, .DivMode = DIV16_MODE,
+
+    .tras = 5,  .tras_05T = 1,
+    .trp = 6,   .trp_05T = 1,
+    .trpab = 7, .trpab_05T = 1,
+    .trc = 13,  .trc_05T = 0,
+    .trfc = 84, .trfc_05T = 1,
+    .trfcpb = 36,   .trfcpb_05T = 1,
+    .txp = 2,   .txp_05T = 0,
+    .trtp = 1,  .trtp_05T = 1,
+    .trcd = 6,  .trcd_05T = 1,
+    .twr = 16,  .twr_05T = 1,
+    .twtr = 5,  .twtr_05T = 0,
+    .twtr_l = 8,    .twtr_l_05T = 1,
+    .tpbr2pbr = 23, .tpbr2pbr_05T = 0,
+    .tpbr2act = 2,  .tpbr2act_05T = 0,
+    .tr2mrw = 13,   .tr2mrw_05T = 1,
+    .tw2mrw = 8,    .tw2mrw_05T = 0,
+    .tmrr2mrw = 11, .tmrr2mrw_05T = 1,
+    .tmrw = 3,  .tmrw_05T = 1,
+    .tmrd = 5,  .tmrd_05T = 1,
+    .tmrwckel = 7,  .tmrwckel_05T = 1,
+    .tpde = 2,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 1,
+    .tmrri = 10,    .tmrri_05T = 1,
+    .trrd = 2,  .trrd_05T = 0,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tr2w_odt_off = 4,  .tr2w_odt_off_05T = 1,
+    .tr2w_odt_on = 6,   .tr2w_odt_on_05T = 0,
+    .txrefcnt = 99,
+    .wckrdoff = 11, .wckrdoff_05T = 1,
+    .wckwroff = 7,  .wckwroff_05T = 0,
+    .tzqcs = 29,
+    .xrtw2w_odt_off = 2,
+    .xrtw2w_odt_on = 3,
+    .xrtw2r_odt_off_otf_off = 0,
+    .xrtw2r_odt_on_otf_off = 0,
+    .xrtw2r_odt_off_otf_on = 3,
+    .xrtw2r_odt_on_otf_on = 3,
+    .xrtr2w_odt_off = 7,
+    .xrtr2w_odt_on = 8,
+    .xrtr2r_odt_off = 6,
+    .xrtr2r_odt_on = 6,
+    .xrtw2w_odt_off_wck = 6,
+    .xrtw2w_odt_on_wck = 8,
+    .xrtw2r_odt_off_wck = 3,
+    .xrtw2r_odt_on_wck = 4,
+    .xrtr2w_odt_off_wck = 10,
+    .xrtr2w_odt_on_wck = 10,
+    .xrtr2r_wck = 8,
+    .tr2mrr = 2,
+    .hwset_mr2_op = 153,
+    .hwset_mr13_op = 74,
+    .hwset_vrcg_op = 144,
+    .vrcgdis_prdcnt = 35,
+    .lp5_cmd1to2en = 0,
+    .trtpd = 12,    .trtpd_05T = 0,
+    .twtpd = 19,    .twtpd_05T = 0,
+    .tmrr2w = 15,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .tcsh_cscal = 3,
+    .tcacsh = 2,
+    .tcsh = 5,
+    .trcd_derate = 7,   .trcd_derate_05T = 0,
+    .trc_derate = 13,   .trc_derate_05T = 1,
+    .tras_derate = 7,   .tras_derate_05T = 0,
+    .trpab_derate = 6,  .trpab_derate_05T = 0,
+    .trp_derate = 5,    .trp_derate_05T = 0,
+    .trrd_derate = 1,   .trrd_derate_05T = 1,
+    .zqlat2 = 11,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 6,  .datlat = 19
+    },
+    //LPDDR5_DDR5500_Div 16_RDBI_ON_CBT_NORMAL_MODE
+    {
+    .dramType = TYPE_LPDDR5, .freq = 2750, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1,
+    //BL (burst length) = 16, DRMC_Clock_Rate = 343.75
+    .readLat = 16, .writeLat =  8, .DivMode = DIV16_MODE,
+
+    .tras = 5,  .tras_05T = 1,
+    .trp = 6,   .trp_05T = 1,
+    .trpab = 7, .trpab_05T = 1,
+    .trc = 13,  .trc_05T = 0,
+    .trfc = 84, .trfc_05T = 1,
+    .trfcpb = 36,   .trfcpb_05T = 1,
+    .txp = 2,   .txp_05T = 0,
+    .trtp = 1,  .trtp_05T = 1,
+    .trcd = 6,  .trcd_05T = 1,
+    .twr = 16,  .twr_05T = 0,
+    .twtr = 4,  .twtr_05T = 1,
+    .twtr_l = 8,    .twtr_l_05T = 0,
+    .tpbr2pbr = 23, .tpbr2pbr_05T = 0,
+    .tpbr2act = 2,  .tpbr2act_05T = 0,
+    .tr2mrw = 13,   .tr2mrw_05T = 0,
+    .tw2mrw = 8,    .tw2mrw_05T = 0,
+    .tmrr2mrw = 11, .tmrr2mrw_05T = 0,
+    .tmrw = 3,  .tmrw_05T = 1,
+    .tmrd = 5,  .tmrd_05T = 1,
+    .tmrwckel = 7,  .tmrwckel_05T = 1,
+    .tpde = 2,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 1,
+    .tmrri = 10,    .tmrri_05T = 1,
+    .trrd = 2,  .trrd_05T = 0,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tr2w_odt_off = 4,  .tr2w_odt_off_05T = 0,
+    .tr2w_odt_on = 5,   .tr2w_odt_on_05T = 1,
+    .txrefcnt = 99,
+    .wckrdoff = 11, .wckrdoff_05T = 0,
+    .wckwroff = 7,  .wckwroff_05T = 0,
+    .tzqcs = 29,
+    .xrtw2w_odt_off = 2,
+    .xrtw2w_odt_on = 3,
+    .xrtw2r_odt_off_otf_off = 0,
+    .xrtw2r_odt_on_otf_off = 0,
+    .xrtw2r_odt_off_otf_on = 3,
+    .xrtw2r_odt_on_otf_on = 3,
+    .xrtr2w_odt_off = 7,
+    .xrtr2w_odt_on = 7,
+    .xrtr2r_odt_off = 6,
+    .xrtr2r_odt_on = 6,
+    .xrtw2w_odt_off_wck = 6,
+    .xrtw2w_odt_on_wck = 8,
+    .xrtw2r_odt_off_wck = 4,
+    .xrtw2r_odt_on_wck = 5,
+    .xrtr2w_odt_off_wck = 10,
+    .xrtr2w_odt_on_wck = 10,
+    .xrtr2r_wck = 8,
+    .tr2mrr = 2,
+    .hwset_mr2_op = 153,
+    .hwset_mr13_op = 74,
+    .hwset_vrcg_op = 144,
+    .vrcgdis_prdcnt = 35,
+    .lp5_cmd1to2en = 0,
+    .trtpd = 11,    .trtpd_05T = 1,
+    .twtpd = 18,    .twtpd_05T = 1,
+    .tmrr2w = 14,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .tcsh_cscal = 3,
+    .tcacsh = 2,
+    .tcsh = 5,
+    .trcd_derate = 7,   .trcd_derate_05T = 0,
+    .trc_derate = 13,   .trc_derate_05T = 1,
+    .tras_derate = 7,   .tras_derate_05T = 0,
+    .trpab_derate = 6,  .trpab_derate_05T = 0,
+    .trp_derate = 5,    .trp_derate_05T = 0,
+    .trrd_derate = 1,   .trrd_derate_05T = 1,
+    .zqlat2 = 11,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 6,  .datlat = 19
+    },
+    #else //ENABLE_READ_DBI == 0
+    //LPDDR5_DDR5500_Div 16_RDBI_OFF_CBT_BYTE_MODE1
+    {
+    .dramType = TYPE_LPDDR5, .freq = 2750, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    //BL (burst length) = 16, DRMC_Clock_Rate = 343.75
+    .readLat = 16, .writeLat =  8, .DivMode = DIV16_MODE,
+
+    .tras = 5,  .tras_05T = 1,
+    .trp = 6,   .trp_05T = 1,
+    .trpab = 7, .trpab_05T = 1,
+    .trc = 13,  .trc_05T = 0,
+    .trfc = 84, .trfc_05T = 1,
+    .trfcpb = 36,   .trfcpb_05T = 1,
+    .txp = 2,   .txp_05T = 0,
+    .trtp = 1,  .trtp_05T = 1,
+    .trcd = 6,  .trcd_05T = 1,
+    .twr = 16,  .twr_05T = 1,
+    .twtr = 5,  .twtr_05T = 0,
+    .twtr_l = 8,    .twtr_l_05T = 1,
+    .tpbr2pbr = 23, .tpbr2pbr_05T = 0,
+    .tpbr2act = 2,  .tpbr2act_05T = 0,
+    .tr2mrw = 13,   .tr2mrw_05T = 0,
+    .tw2mrw = 8,    .tw2mrw_05T = 0,
+    .tmrr2mrw = 11, .tmrr2mrw_05T = 0,
+    .tmrw = 3,  .tmrw_05T = 1,
+    .tmrd = 5,  .tmrd_05T = 1,
+    .tmrwckel = 7,  .tmrwckel_05T = 1,
+    .tpde = 2,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 1,
+    .tmrri = 10,    .tmrri_05T = 1,
+    .trrd = 2,  .trrd_05T = 0,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tr2w_odt_off = 4,  .tr2w_odt_off_05T = 0,
+    .tr2w_odt_on = 5,   .tr2w_odt_on_05T = 1,
+    .txrefcnt = 99,
+    .wckrdoff = 11, .wckrdoff_05T = 0,
+    .wckwroff = 7,  .wckwroff_05T = 0,
+    .tzqcs = 29,
+    .xrtw2w_odt_off = 2,
+    .xrtw2w_odt_on = 3,
+    .xrtw2r_odt_off_otf_off = 0,
+    .xrtw2r_odt_on_otf_off = 0,
+    .xrtw2r_odt_off_otf_on = 3,
+    .xrtw2r_odt_on_otf_on = 3,
+    .xrtr2w_odt_off = 7,
+    .xrtr2w_odt_on = 7,
+    .xrtr2r_odt_off = 6,
+    .xrtr2r_odt_on = 6,
+    .xrtw2w_odt_off_wck = 6,
+    .xrtw2w_odt_on_wck = 8,
+    .xrtw2r_odt_off_wck = 4,
+    .xrtw2r_odt_on_wck = 5,
+    .xrtr2w_odt_off_wck = 10,
+    .xrtr2w_odt_on_wck = 10,
+    .xrtr2r_wck = 8,
+    .tr2mrr = 2,
+    .hwset_mr2_op = 153,
+    .hwset_mr13_op = 74,
+    .hwset_vrcg_op = 144,
+    .vrcgdis_prdcnt = 35,
+    .lp5_cmd1to2en = 0,
+    .trtpd = 11,    .trtpd_05T = 1,
+    .twtpd = 19,    .twtpd_05T = 0,
+    .tmrr2w = 14,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .tcsh_cscal = 3,
+    .tcacsh = 2,
+    .tcsh = 5,
+    .trcd_derate = 7,   .trcd_derate_05T = 0,
+    .trc_derate = 13,   .trc_derate_05T = 1,
+    .tras_derate = 7,   .tras_derate_05T = 0,
+    .trpab_derate = 6,  .trpab_derate_05T = 0,
+    .trp_derate = 5,    .trp_derate_05T = 0,
+    .trrd_derate = 1,   .trrd_derate_05T = 1,
+    .zqlat2 = 11,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 6,  .datlat = 19
+    },
+    {
+    .dramType = TYPE_LPDDR5, .freq = 2750, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    //BL (burst length) = 16, DRMC_Clock_Rate = 343.75
+    .readLat = 15, .writeLat =  8, .DivMode = DIV16_MODE,
+
+    .tras = 5,  .tras_05T = 1,
+    .trp = 6,   .trp_05T = 1,
+    .trpab = 7, .trpab_05T = 1,
+    .trc = 13,  .trc_05T = 0,
+    .trfc = 84, .trfc_05T = 1,
+    .trfcpb = 36,   .trfcpb_05T = 1,
+    .txp = 2,   .txp_05T = 0,
+    .trtp = 1,  .trtp_05T = 1,
+    .trcd = 6,  .trcd_05T = 1,
+    .twr = 16,  .twr_05T = 0,
+    .twtr = 4,  .twtr_05T = 1,
+    .twtr_l = 8,    .twtr_l_05T = 0,
+    .tpbr2pbr = 23, .tpbr2pbr_05T = 0,
+    .tpbr2act = 2,  .tpbr2act_05T = 0,
+    .tr2mrw = 12,   .tr2mrw_05T = 1,
+    .tw2mrw = 8,    .tw2mrw_05T = 0,
+    .tmrr2mrw = 10, .tmrr2mrw_05T = 1,
+    .tmrw = 3,  .tmrw_05T = 1,
+    .tmrd = 5,  .tmrd_05T = 1,
+    .tmrwckel = 7,  .tmrwckel_05T = 1,
+    .tpde = 2,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 1,
+    .tmrri = 10,    .tmrri_05T = 1,
+    .trrd = 2,  .trrd_05T = 0,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tr2w_odt_off = 3,  .tr2w_odt_off_05T = 1,
+    .tr2w_odt_on = 5,   .tr2w_odt_on_05T = 0,
+    .txrefcnt = 99,
+    .wckrdoff = 10, .wckrdoff_05T = 1,
+    .wckwroff = 7,  .wckwroff_05T = 0,
+    .tzqcs = 29,
+    .xrtw2w_odt_off = 2,
+    .xrtw2w_odt_on = 3,
+    .xrtw2r_odt_off_otf_off = 0,
+    .xrtw2r_odt_on_otf_off = 1,
+    .xrtw2r_odt_off_otf_on = 3,
+    .xrtw2r_odt_on_otf_on = 3,
+    .xrtr2w_odt_off = 6,
+    .xrtr2w_odt_on = 7,
+    .xrtr2r_odt_off = 6,
+    .xrtr2r_odt_on = 6,
+    .xrtw2w_odt_off_wck = 6,
+    .xrtw2w_odt_on_wck = 8,
+    .xrtw2r_odt_off_wck = 4,
+    .xrtw2r_odt_on_wck = 5,
+    .xrtr2w_odt_off_wck = 9,
+    .xrtr2w_odt_on_wck = 9,
+    .xrtr2r_wck = 8,
+    .tr2mrr = 1,
+    .hwset_mr2_op = 153,
+    .hwset_mr13_op = 74,
+    .hwset_vrcg_op = 144,
+    .vrcgdis_prdcnt = 35,
+    .lp5_cmd1to2en = 0,
+    .trtpd = 11,    .trtpd_05T = 0,
+    .twtpd = 18,    .twtpd_05T = 1,
+    .tmrr2w = 14,
+    .ckeprd = 2,
+    .ckelckcnt = 3,
+    .tcsh_cscal = 3,
+    .tcacsh = 2,
+    .tcsh = 5,
+    .trcd_derate = 7,   .trcd_derate_05T = 0,
+    .trc_derate = 13,   .trc_derate_05T = 1,
+    .tras_derate = 7,   .tras_derate_05T = 0,
+    .trpab_derate = 6,  .trpab_derate_05T = 0,
+    .trp_derate = 5,    .trp_derate_05T = 0,
+    .trrd_derate = 1,   .trrd_derate_05T = 1,
+    .zqlat2 = 11,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 6,  .datlat = 19
+    },
+    #endif
+    #endif
+    #if SUPPORT_LP5_DDR4266_ACTIM
+    //LP5_DDR4266 ACTiming---------------------------------
+    #if ((ENABLE_READ_DBI == 1) || (LP5_DDR4266_RDBI_WORKAROUND == 1))
+    //LPDDR5_4266_Div 8_CKR4_DBI1.csv Read 1
+    {
+    .dramType = TYPE_LPDDR5, .freq = 2133, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1,
+
+    //BL (burst length) = 16, DRMC_Clock_Rate = 533.25
+    .readLat = 14, .writeLat =  6, .DivMode = DIV8_MODE,
+
+    .tras = 14, .tras_05T = 0,
+    .trp = 10,  .trp_05T = 0,
+    .trpab = 12,    .trpab_05T = 0,
+    .trc = 25,  .trc_05T = 0,
+    .trfc = 138,    .trfc_05T = 0,
+    .trfcpb = 63,   .trfcpb_05T = 0,
+    .txp = 5,   .txp_05T = 0,
+    .trtp = 4,  .trtp_05T = 0,
+    .trcd = 10, .trcd_05T = 0,
+    .twr = 27,  .twr_05T = 0,
+    .twtr = 10, .twtr_05T = 0,
+    .twtr_l = 16,   .twtr_l_05T = 0,
+    .tpbr2pbr = 40, .tpbr2pbr_05T = 0,
+    .tpbr2act = 3,  .tpbr2act_05T = 0,
+    .tr2mrw = 23,   .tr2mrw_05T = 0,
+    .tw2mrw = 14,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 21, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 9,  .tmrd_05T = 0,
+    .tmrwckel = 13, .tmrwckel_05T = 0,
+    .tpde = 5,  .tpde_05T = 0,
+    .tpdx = 3,  .tpdx_05T = 0,
+    .tmrri = 17,    .tmrri_05T = 0,
+    .trrd = 3,  .trrd_05T = 0,
+    .tfaw = 3,  .tfaw_05T = 0,
+    .tr2w_odt_off = 11, .tr2w_odt_off_05T = 0,
+    .tr2w_odt_on = 15,  .tr2w_odt_on_05T = 0,
+    .txrefcnt = 154,
+    .wckrdoff = 20, .wckrdoff_05T = 0,
+    .wckwroff = 12, .wckwroff_05T = 0,
+    .tzqcs = 46,
+    .xrtw2w_odt_off = 5,
+    .xrtw2w_odt_on = 7,
+    .xrtw2r_odt_off_otf_off = 0,
+    .xrtw2r_odt_on_otf_off = 0,
+    .xrtw2r_odt_off_otf_on = 3,
+    .xrtw2r_odt_on_otf_on = 3,
+    .xrtr2w_odt_off = 12,
+    .xrtr2w_odt_on = 14,
+    .xrtr2r_odt_off = 9,
+    .xrtr2r_odt_on = 9,
+    .xrtw2w_odt_off_wck = 10,
+    .xrtw2w_odt_on_wck = 12,
+    .xrtw2r_odt_off_wck = 6,
+    .xrtw2r_odt_on_wck = 7,
+    .xrtr2w_odt_off_wck = 18,
+    .xrtr2w_odt_on_wck = 18,
+    .xrtr2r_wck = 14,
+    .tr2mrr = 13,
+    .hwset_mr2_op = 119,
+    .hwset_mr13_op = 74,
+    .hwset_vrcg_op = 112,
+    .vrcgdis_prdcnt = 54,
+    .lp5_cmd1to2en = 1,
+    .trtpd = 19,    .trtpd_05T = 0,
+    .twtpd = 31,    .twtpd_05T = 0,
+    .tmrr2w = 23,
+    .ckeprd = 3,
+    .ckelckcnt = 5,
+    .tcsh_cscal = 5,
+    .tcacsh = 3,
+    .tcsh = 4,
+    .trcd_derate = 11,  .trcd_derate_05T = 0,
+    .trc_derate = 26,   .trc_derate_05T = 0,
+    .tras_derate = 17,  .tras_derate_05T = 0,
+    .trpab_derate = 10, .trpab_derate_05T = 0,
+    .trp_derate = 8,    .trp_derate_05T = 0,
+    .trrd_derate = 3,   .trrd_derate_05T = 0,
+    .zqlat2 = 16,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 10, .datlat = 19
+    },
+    //LPDDR5_4266_BT_Div 8_CKR4_DBI1.csv Read 1
+    {
+    .dramType = TYPE_LPDDR5, .freq = 2133, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1,
+    //BL (burst length) = 16, DRMC_Clock_Rate = 533.25
+    .readLat = 13, .writeLat =  6, .DivMode = DIV8_MODE,
+
+    .tras = 14, .tras_05T = 0,
+    .trp = 10,  .trp_05T = 0,
+    .trpab = 12,    .trpab_05T = 0,
+    .trc = 25,  .trc_05T = 0,
+    .trfc = 138,    .trfc_05T = 0,
+    .trfcpb = 63,   .trfcpb_05T = 0,
+    .txp = 5,   .txp_05T = 0,
+    .trtp = 4,  .trtp_05T = 0,
+    .trcd = 10, .trcd_05T = 0,
+    .twr = 26,  .twr_05T = 0,
+    .twtr = 9,  .twtr_05T = 0,
+    .twtr_l = 15,   .twtr_l_05T = 0,
+    .tpbr2pbr = 40, .tpbr2pbr_05T = 0,
+    .tpbr2act = 3,  .tpbr2act_05T = 0,
+    .tr2mrw = 22,   .tr2mrw_05T = 0,
+    .tw2mrw = 14,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 20, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 9,  .tmrd_05T = 0,
+    .tmrwckel = 13, .tmrwckel_05T = 0,
+    .tpde = 5,  .tpde_05T = 0,
+    .tpdx = 3,  .tpdx_05T = 0,
+    .tmrri = 17,    .tmrri_05T = 0,
+    .trrd = 3,  .trrd_05T = 0,
+    .tfaw = 3,  .tfaw_05T = 0,
+    .tr2w_odt_off = 10, .tr2w_odt_off_05T = 0,
+    .tr2w_odt_on = 14,  .tr2w_odt_on_05T = 0,
+    .txrefcnt = 154,
+    .wckrdoff = 19, .wckrdoff_05T = 0,
+    .wckwroff = 12, .wckwroff_05T = 0,
+    .tzqcs = 46,
+    .xrtw2w_odt_off = 5,
+    .xrtw2w_odt_on = 7,
+    .xrtw2r_odt_off_otf_off = 0,
+    .xrtw2r_odt_on_otf_off = 0,
+    .xrtw2r_odt_off_otf_on = 3,
+    .xrtw2r_odt_on_otf_on = 3,
+    .xrtr2w_odt_off = 11,
+    .xrtr2w_odt_on = 13,
+    .xrtr2r_odt_off = 9,
+    .xrtr2r_odt_on = 9,
+    .xrtw2w_odt_off_wck = 10,
+    .xrtw2w_odt_on_wck = 12,
+    .xrtw2r_odt_off_wck = 7,
+    .xrtw2r_odt_on_wck = 8,
+    .xrtr2w_odt_off_wck = 17,
+    .xrtr2w_odt_on_wck = 17,
+    .xrtr2r_wck = 14,
+    .tr2mrr = 12,
+    .hwset_mr2_op = 119,
+    .hwset_mr13_op = 74,
+    .hwset_vrcg_op = 112,
+    .vrcgdis_prdcnt = 54,
+    .lp5_cmd1to2en = 1,
+    .trtpd = 18,    .trtpd_05T = 0,
+    .twtpd = 30,    .twtpd_05T = 0,
+    .tmrr2w = 22,
+    .ckeprd = 3,
+    .ckelckcnt = 5,
+    .tcsh_cscal = 5,
+    .tcacsh = 3,
+    .tcsh = 4,
+    .trcd_derate = 11,  .trcd_derate_05T = 0,
+    .trc_derate = 26,   .trc_derate_05T = 0,
+    .tras_derate = 17,  .tras_derate_05T = 0,
+    .trpab_derate = 10, .trpab_derate_05T = 0,
+    .trp_derate = 8,    .trp_derate_05T = 0,
+    .trrd_derate = 3,   .trrd_derate_05T = 0,
+    .zqlat2 = 16,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 10, .datlat = 19
+    },
+    #else  //ENABLE_READ_DBI == 0)
+    //LPDDR5_4266_Div 8_CKR4_DBI0.csv Read 0
+    {
+    .dramType = TYPE_LPDDR5, .freq = 2133, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+    //BL (burst length) = 16, DRMC_Clock_Rate = 533.25
+    .readLat = 13, .writeLat =  6, .DivMode = DIV8_MODE,
+
+    .tras = 14, .tras_05T = 0,
+    .trp = 10,  .trp_05T = 0,
+    .trpab = 12,    .trpab_05T = 0,
+    .trc = 25,  .trc_05T = 0,
+    .trfc = 138,    .trfc_05T = 0,
+    .trfcpb = 63,   .trfcpb_05T = 0,
+    .txp = 5,   .txp_05T = 0,
+    .trtp = 4,  .trtp_05T = 0,
+    .trcd = 10, .trcd_05T = 0,
+    .twr = 27,  .twr_05T = 0,
+    .twtr = 10, .twtr_05T = 0,
+    .twtr_l = 16,   .twtr_l_05T = 0,
+    .tpbr2pbr = 40, .tpbr2pbr_05T = 0,
+    .tpbr2act = 3,  .tpbr2act_05T = 0,
+    .tr2mrw = 22,   .tr2mrw_05T = 0,
+    .tw2mrw = 14,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 20, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 9,  .tmrd_05T = 0,
+    .tmrwckel = 13, .tmrwckel_05T = 0,
+    .tpde = 5,  .tpde_05T = 0,
+    .tpdx = 3,  .tpdx_05T = 0,
+    .tmrri = 17,    .tmrri_05T = 0,
+    .trrd = 3,  .trrd_05T = 0,
+    .tfaw = 3,  .tfaw_05T = 0,
+    .tr2w_odt_off = 10, .tr2w_odt_off_05T = 0,
+    .tr2w_odt_on = 14,  .tr2w_odt_on_05T = 0,
+    .txrefcnt = 154,
+    .wckrdoff = 19, .wckrdoff_05T = 0,
+    .wckwroff = 12, .wckwroff_05T = 0,
+    .tzqcs = 46,
+    .xrtw2w_odt_off = 5,
+    .xrtw2w_odt_on = 7,
+    .xrtw2r_odt_off_otf_off = 0,
+    .xrtw2r_odt_on_otf_off = 0,
+    .xrtw2r_odt_off_otf_on = 3,
+    .xrtw2r_odt_on_otf_on = 3,
+    .xrtr2w_odt_off = 11,
+    .xrtr2w_odt_on = 13,
+    .xrtr2r_odt_off = 9,
+    .xrtr2r_odt_on = 9,
+    .xrtw2w_odt_off_wck = 10,
+    .xrtw2w_odt_on_wck = 12,
+    .xrtw2r_odt_off_wck = 7,
+    .xrtw2r_odt_on_wck = 8,
+    .xrtr2w_odt_off_wck = 17,
+    .xrtr2w_odt_on_wck = 17,
+    .xrtr2r_wck = 14,
+    .tr2mrr = 12,
+    .hwset_mr2_op = 119,
+    .hwset_mr13_op = 74,
+    .hwset_vrcg_op = 112,
+    .vrcgdis_prdcnt = 54,
+    .lp5_cmd1to2en = 1,
+    .trtpd = 18,    .trtpd_05T = 0,
+    .twtpd = 31,    .twtpd_05T = 0,
+    .tmrr2w = 22,
+    .ckeprd = 3,
+    .ckelckcnt = 5,
+    .tcsh_cscal = 5,
+    .tcacsh = 3,
+    .tcsh = 4,
+    .trcd_derate = 11,  .trcd_derate_05T = 0,
+    .trc_derate = 26,   .trc_derate_05T = 0,
+    .tras_derate = 17,  .tras_derate_05T = 0,
+    .trpab_derate = 10, .trpab_derate_05T = 0,
+    .trp_derate = 8,    .trp_derate_05T = 0,
+    .trrd_derate = 3,   .trrd_derate_05T = 0,
+    .zqlat2 = 16,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 10, .datlat = 19
+    },
+    //LPDDR5_4266_BT_Div 8_CKR4_DBI0.csv Read 0
+    {
+    .dramType = TYPE_LPDDR5, .freq = 2133, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    //BL (burst length) = 16, DRMC_Clock_Rate = 533.25
+    .readLat = 12, .writeLat =  6, .DivMode = DIV8_MODE,
+
+    .tras = 14, .tras_05T = 0,
+    .trp = 10,  .trp_05T = 0,
+    .trpab = 12,    .trpab_05T = 0,
+    .trc = 25,  .trc_05T = 0,
+    .trfc = 138,    .trfc_05T = 0,
+    .trfcpb = 63,   .trfcpb_05T = 0,
+    .txp = 5,   .txp_05T = 0,
+    .trtp = 4,  .trtp_05T = 0,
+    .trcd = 10, .trcd_05T = 0,
+    .twr = 26,  .twr_05T = 0,
+    .twtr = 9,  .twtr_05T = 0,
+    .twtr_l = 15,   .twtr_l_05T = 0,
+    .tpbr2pbr = 40, .tpbr2pbr_05T = 0,
+    .tpbr2act = 3,  .tpbr2act_05T = 0,
+    .tr2mrw = 21,   .tr2mrw_05T = 0,
+    .tw2mrw = 14,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 19, .tmrr2mrw_05T = 0,
+    .tmrw = 6,  .tmrw_05T = 0,
+    .tmrd = 9,  .tmrd_05T = 0,
+    .tmrwckel = 13, .tmrwckel_05T = 0,
+    .tpde = 5,  .tpde_05T = 0,
+    .tpdx = 3,  .tpdx_05T = 0,
+    .tmrri = 17,    .tmrri_05T = 0,
+    .trrd = 3,  .trrd_05T = 0,
+    .tfaw = 3,  .tfaw_05T = 0,
+    .tr2w_odt_off = 9,  .tr2w_odt_off_05T = 0,
+    .tr2w_odt_on = 13,  .tr2w_odt_on_05T = 0,
+    .txrefcnt = 154,
+    .wckrdoff = 18, .wckrdoff_05T = 0,
+    .wckwroff = 12, .wckwroff_05T = 0,
+    .tzqcs = 46,
+    .xrtw2w_odt_off = 5,
+    .xrtw2w_odt_on = 7,
+    .xrtw2r_odt_off_otf_off = 0,
+    .xrtw2r_odt_on_otf_off = 1,
+    .xrtw2r_odt_off_otf_on = 3,
+    .xrtw2r_odt_on_otf_on = 3,
+    .xrtr2w_odt_off = 10,
+    .xrtr2w_odt_on = 12,
+    .xrtr2r_odt_off = 9,
+    .xrtr2r_odt_on = 9,
+    .xrtw2w_odt_off_wck = 10,
+    .xrtw2w_odt_on_wck = 12,
+    .xrtw2r_odt_off_wck = 8,
+    .xrtw2r_odt_on_wck = 9,
+    .xrtr2w_odt_off_wck = 16,
+    .xrtr2w_odt_on_wck = 16,
+    .xrtr2r_wck = 14,
+    .tr2mrr = 11,
+    .hwset_mr2_op = 119,
+    .hwset_mr13_op = 74,
+    .hwset_vrcg_op = 112,
+    .vrcgdis_prdcnt = 54,
+    .lp5_cmd1to2en = 1,
+    .trtpd = 17,    .trtpd_05T = 0,
+    .twtpd = 30,    .twtpd_05T = 0,
+    .tmrr2w = 21,
+    .ckeprd = 3,
+    .ckelckcnt = 5,
+    .tcsh_cscal = 5,
+    .tcacsh = 3,
+    .tcsh = 4,
+    .trcd_derate = 11,  .trcd_derate_05T = 0,
+    .trc_derate = 26,   .trc_derate_05T = 0,
+    .tras_derate = 17,  .tras_derate_05T = 0,
+    .trpab_derate = 10, .trpab_derate_05T = 0,
+    .trp_derate = 8,    .trp_derate_05T = 0,
+    .trrd_derate = 3,   .trrd_derate_05T = 0,
+    .zqlat2 = 16,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 10, .datlat = 19
+    },
+    #endif
+    #endif
+    #if SUPPORT_LP5_DDR3200_ACTIM
+    //LP5_DDR3200 ACTiming---------------------------------
+    //LPDDR5_3200_Div 8_CKR2_DBI1.csv Read 0
+    {
+    .dramType = TYPE_LPDDR5, .freq = 1600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
+
+    //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
+    .readLat = 20, .writeLat =  10, .DivMode = DIV8_MODE,
+
+    .tras = 8,  .tras_05T = 0,
+    .trp = 7,   .trp_05T = 1,
+    .trpab = 8, .trpab_05T = 1,
+    .trc = 16,  .trc_05T = 1,
+    .trfc = 140,    .trfc_05T = 0,
+    .trfcpb = 64,   .trfcpb_05T = 0,
+    .txp = 2,   .txp_05T = 1,
+    .trtp = 2,  .trtp_05T = 0,
+    .trcd = 7,  .trcd_05T = 1,
+    .twr = 19,  .twr_05T = 0,
+    .twtr = 10, .twtr_05T = 0,
+    .twtr_l = 10,   .twtr_l_05T = 0,
+    .tpbr2pbr = 36, .tpbr2pbr_05T = 0,
+    .tpbr2act = 3,  .tpbr2act_05T = 0,
+    .tr2mrw = 15,   .tr2mrw_05T = 0,
+    .tw2mrw = 10,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 14, .tmrr2mrw_05T = 0,
+    .tmrw = 4,  .tmrw_05T = 0,
+    .tmrd = 6,  .tmrd_05T = 1,
+    .tmrwckel = 8,  .tmrwckel_05T = 1,
+    .tpde = 2,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 1,
+    .tmrri = 12,    .tmrri_05T = 0,
+    .trrd = 2,  .trrd_05T = 0,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tr2w_odt_off = 4,  .tr2w_odt_off_05T = 0,
+    .tr2w_odt_on = 6,   .tr2w_odt_on_05T = 0,
+    .txrefcnt = 115,
+    .wckrdoff = 13, .wckrdoff_05T = 0,
+    .wckwroff = 8,  .wckwroff_05T = 0,
+    .tzqcs = 34,
+    .xrtw2w_odt_off = 6,
+    .xrtw2w_odt_on = 9,
+    .xrtw2r_odt_off_otf_off = 3,
+    .xrtw2r_odt_on_otf_off = 3,
+    .xrtw2r_odt_off_otf_on = 3,
+    .xrtw2r_odt_on_otf_on = 3,
+    .xrtr2w_odt_off = 9,
+    .xrtr2w_odt_on = 10,
+    .xrtr2r_odt_off = 8,
+    .xrtr2r_odt_on = 8,
+    .xrtw2w_odt_off_wck = 7,
+    .xrtw2w_odt_on_wck = 9,
+    .xrtw2r_odt_off_wck = 5,
+    .xrtw2r_odt_on_wck = 6,
+    .xrtr2w_odt_off_wck = 12,
+    .xrtr2w_odt_on_wck = 12,
+    .xrtr2r_wck = 10,
+    .tr2mrr = 3,
+    .hwset_mr2_op = 45,
+    .hwset_mr13_op = 216,
+    .hwset_vrcg_op = 208,
+    .vrcgdis_prdcnt = 40,
+    .lp5_cmd1to2en = 0,
+    .trtpd = 13,    .trtpd_05T = 1,
+    .twtpd = 13,    .twtpd_05T = 0,
+    .tmrr2w = 16,
+    .ckeprd = 4,
+    .ckelckcnt = 3,
+    .tcsh_cscal = 3,
+    .tcacsh = 2,
+    .tcsh = 5,
+    .trcd_derate = 8,   .trcd_derate_05T = 0,
+    .trc_derate = 17,   .trc_derate_05T = 0,
+    .tras_derate = 10,  .tras_derate_05T = 0,
+    .trpab_derate = 7,  .trpab_derate_05T = 1,
+    .trp_derate = 6,    .trp_derate_05T = 0,
+    .trrd_derate = 2,   .trrd_derate_05T = 0,
+    .zqlat2 = 12,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 7,  .datlat = 15
+    },
+    //LPDDR5_3200_BT_Div 8_CKR2_DBI1.csv Read 0
+    {
+    .dramType = TYPE_LPDDR5, .freq = 1600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
+    //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
+    .readLat = 18, .writeLat =  10, .DivMode = DIV8_MODE,
+
+    .tras = 8,  .tras_05T = 0,
+    .trp = 7,   .trp_05T = 1,
+    .trpab = 8, .trpab_05T = 1,
+    .trc = 16,  .trc_05T = 1,
+    .trfc = 140,    .trfc_05T = 0,
+    .trfcpb = 64,   .trfcpb_05T = 0,
+    .txp = 2,   .txp_05T = 1,
+    .trtp = 2,  .trtp_05T = 0,
+    .trcd = 7,  .trcd_05T = 1,
+    .twr = 19,  .twr_05T = -2,
+    .twtr = 9,  .twtr_05T = 0,
+    .twtr_l = 9,    .twtr_l_05T = 0,
+    .tpbr2pbr = 36, .tpbr2pbr_05T = 0,
+    .tpbr2act = 3,  .tpbr2act_05T = 0,
+    .tr2mrw = 14,   .tr2mrw_05T = 0,
+    .tw2mrw = 10,   .tw2mrw_05T = 0,
+    .tmrr2mrw = 13, .tmrr2mrw_05T = 0,
+    .tmrw = 4,  .tmrw_05T = 0,
+    .tmrd = 6,  .tmrd_05T = 1,
+    .tmrwckel = 8,  .tmrwckel_05T = 1,
+    .tpde = 2,  .tpde_05T = 1,
+    .tpdx = 1,  .tpdx_05T = 1,
+    .tmrri = 12,    .tmrri_05T = 0,
+    .trrd = 2,  .trrd_05T = 0,
+    .tfaw = 0,  .tfaw_05T = 0,
+    .tr2w_odt_off = 3,  .tr2w_odt_off_05T = 0,
+    .tr2w_odt_on = 5,   .tr2w_odt_on_05T = 0,
+    .txrefcnt = 115,
+    .wckrdoff = 12, .wckrdoff_05T = 0,
+    .wckwroff = 8,  .wckwroff_05T = 0,
+    .tzqcs = 34,
+    .xrtw2w_odt_off = 6,
+    .xrtw2w_odt_on = 9,
+    .xrtw2r_odt_off_otf_off = 3,
+    .xrtw2r_odt_on_otf_off = 3,
+    .xrtw2r_odt_off_otf_on = 3,
+    .xrtw2r_odt_on_otf_on = 3,
+    .xrtr2w_odt_off = 8,
+    .xrtr2w_odt_on = 9,
+    .xrtr2r_odt_off = 8,
+    .xrtr2r_odt_on = 8,
+    .xrtw2w_odt_off_wck = 7,
+    .xrtw2w_odt_on_wck = 9,
+    .xrtw2r_odt_off_wck = 6,
+    .xrtw2r_odt_on_wck = 7,
+    .xrtr2w_odt_off_wck = 11,
+    .xrtr2w_odt_on_wck = 11,
+    .xrtr2r_wck = 10,
+    .tr2mrr = 2,
+    .hwset_mr2_op = 45,
+    .hwset_mr13_op = 216,
+    .hwset_vrcg_op = 208,
+    .vrcgdis_prdcnt = 40,
+    .lp5_cmd1to2en = 0,
+    .trtpd = 12,    .trtpd_05T = 1,
+    .twtpd = 12,    .twtpd_05T = 0,
+    .tmrr2w = 15,
+    .ckeprd = 4,
+    .ckelckcnt = 3,
+    .tcsh_cscal = 3,
+    .tcacsh = 2,
+    .tcsh = 5,
+    .trcd_derate = 8,   .trcd_derate_05T = 0,
+    .trc_derate = 17,   .trc_derate_05T = 0,
+    .tras_derate = 10,  .tras_derate_05T = 0,
+    .trpab_derate = 7,  .trpab_derate_05T = 1,
+    .trp_derate = 6,    .trp_derate_05T = 0,
+    .trrd_derate = 2,   .trrd_derate_05T = 0,
+    .zqlat2 = 12,
+
+    //DQSINCTL, DATLAT aren't in ACTiming excel file
+    .dqsinctl = 7,  .datlat = 15
+    },
+    #endif
+    };
+#endif
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_debug.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_debug.c
new file mode 100644
index 000000000000..5e89f70092e7
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_debug.c
@@ -0,0 +1,4809 @@
+/*----------------------------------------------------------------------------*
+ * Copyright Statement:                                                       *
+ *                                                                            *
+ *   This software/firmware and related documentation ("MediaTek Software")   *
+ * are protected under international and related jurisdictions'copyright laws *
+ * as unpublished works. The information contained herein is confidential and *
+ * proprietary to MediaTek Inc. Without the prior written permission of       *
+ * MediaTek Inc., any reproduction, modification, use or disclosure of        *
+ * MediaTek Software, and information contained herein, in whole or in part,  *
+ * shall be strictly prohibited.                                              *
+ * MediaTek Inc. Copyright (C) 2010. All rights reserved.                     *
+ *                                                                            *
+ *   BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND     *
+ * AGREES TO THE FOLLOWING:                                                   *
+ *                                                                            *
+ *   1)Any and all intellectual property rights (including without            *
+ * limitation, patent, copyright, and trade secrets) in and to this           *
+ * Software/firmware and related documentation ("MediaTek Software") shall    *
+ * remain the exclusive property of MediaTek Inc. Any and all intellectual    *
+ * property rights (including without limitation, patent, copyright, and      *
+ * trade secrets) in and to any modifications and derivatives to MediaTek     *
+ * Software, whoever made, shall also remain the exclusive property of        *
+ * MediaTek Inc.  Nothing herein shall be construed as any transfer of any    *
+ * title to any intellectual property right in MediaTek Software to Receiver. *
+ *                                                                            *
+ *   2)This MediaTek Software Receiver received from MediaTek Inc. and/or its *
+ * representatives is provided to Receiver on an "AS IS" basis only.          *
+ * MediaTek Inc. expressly disclaims all warranties, expressed or implied,    *
+ * including but not limited to any implied warranties of merchantability,    *
+ * non-infringement and fitness for a particular purpose and any warranties   *
+ * arising out of course of performance, course of dealing or usage of trade. *
+ * MediaTek Inc. does not provide any warranty whatsoever with respect to the *
+ * software of any third party which may be used by, incorporated in, or      *
+ * supplied with the MediaTek Software, and Receiver agrees to look only to   *
+ * such third parties for any warranty claim relating thereto.  Receiver      *
+ * expressly acknowledges that it is Receiver's sole responsibility to obtain *
+ * from any third party all proper licenses contained in or delivered with    *
+ * MediaTek Software.  MediaTek is not responsible for any MediaTek Software  *
+ * releases made to Receiver's specifications or to conform to a particular   *
+ * standard or open forum.                                                    *
+ *                                                                            *
+ *   3)Receiver further acknowledge that Receiver may, either presently       *
+ * and/or in the future, instruct MediaTek Inc. to assist it in the           *
+ * development and the implementation, in accordance with Receiver's designs, *
+ * of certain softwares relating to Receiver's product(s) (the "Services").   *
+ * Except as may be otherwise agreed to in writing, no warranties of any      *
+ * kind, whether express or implied, are given by MediaTek Inc. with respect  *
+ * to the Services provided, and the Services are provided on an "AS IS"      *
+ * basis. Receiver further acknowledges that the Services may contain errors  *
+ * that testing is important and it is solely responsible for fully testing   *
+ * the Services and/or derivatives thereof before they are used, sublicensed  *
+ * or distributed. Should there be any third party action brought against     *
+ * MediaTek Inc. arising out of or relating to the Services, Receiver agree   *
+ * to fully indemnify and hold MediaTek Inc. harmless.  If the parties        *
+ * mutually agree to enter into or continue a business relationship or other  *
+ * arrangement, the terms and conditions set forth herein shall remain        *
+ * effective and, unless explicitly stated otherwise, shall prevail in the    *
+ * event of a conflict in the terms in any agreements entered into between    *
+ * the parties.                                                               *
+ *                                                                            *
+ *   4)Receiver's sole and exclusive remedy and MediaTek Inc.'s entire and    *
+ * cumulative liability with respect to MediaTek Software released hereunder  *
+ * will be, at MediaTek Inc.'s sole discretion, to replace or revise the      *
+ * MediaTek Software at issue.                                                *
+ *                                                                            *
+ *   5)The transaction contemplated hereunder shall be construed in           *
+ * accordance with the laws of Singapore, excluding its conflict of laws      *
+ * principles.  Any disputes, controversies or claims arising thereof and     *
+ * related thereto shall be settled via arbitration in Singapore, under the   *
+ * then current rules of the International Chamber of Commerce (ICC).  The    *
+ * arbitration shall be conducted in English. The awards of the arbitration   *
+ * shall be final and binding upon both parties and shall be entered and      *
+ * enforceable in any court of competent jurisdiction.                        *
+ *---------------------------------------------------------------------------*/
+
+//-----------------------------------------------------------------------------
+// Include files
+//-----------------------------------------------------------------------------
+#include "dramc_common.h"
+#include "dramc_int_global.h"
+#include "x_hal_io.h"
+
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+#include "dramc_top.h"
+#ifndef MT6779_FPGA
+//#include <pmic.h>
+#endif
+#endif
+
+
+//-----------------------------------------------------------------------------
+// Global variables
+//-----------------------------------------------------------------------------
+
+#if ENABLE_EYESCAN_GRAPH || defined(FOR_HQA_REPORT_USED)
+EXTERN const U16 gRXVref_Voltage_Table_0P5V_T[EYESCAN_RX_VREF_RANGE_END];
+EXTERN const U16 gRXVref_Voltage_Table_0P5V_UT[EYESCAN_RX_VREF_RANGE_END];
+EXTERN const U16 gRXVref_Voltage_Table_0P3V_UT[EYESCAN_RX_VREF_RANGE_END];
+EXTERN const U16 gRXVref_Voltage_Table_0P6V_T[EYESCAN_RX_VREF_RANGE_END];
+EXTERN const U16 gRXVref_Voltage_Table_0P6V_UT[EYESCAN_RX_VREF_RANGE_END];
+EXTERN const U16 gVref_Voltage_Table_LP4X[VREF_RANGE_MAX][VREF_VOLTAGE_TABLE_NUM_LP4];
+EXTERN const U16 gVref_Voltage_Table_LP4[VREF_RANGE_MAX][VREF_VOLTAGE_TABLE_NUM_LP4];
+EXTERN const U16 gVref_Voltage_Table_LP5[VREF_VOLTAGE_TABLE_NUM_LP5];
+#endif
+
+#if __ETT__
+#define __NOBITS_SECTION__(x)
+#endif
+
+#if ENABLE_EYESCAN_GRAPH || defined(FOR_HQA_REPORT_USED)
+const U16 gRXVref_Voltage_Table_0P5V_T[EYESCAN_RX_VREF_RANGE_END] = {
+        3990,4140,4290,4440,4590,4740,4890,5030,5180,5330,
+        5480,5630,5770,5920,6070,6220,6480,6630,6780,6920,
+        7070,7220,7370,7520,7670,7820,7970,8110,8260,8410,
+        8560,8710,8950,9110,9250,9400,9550,9700,9850,10000,
+        10150,10300,10450,10590,10740,10890,11040,11190,11430,11590,
+        11740,11890,12040,12190,12340,12500,12650,12800,12950,13100,
+        13260,13410,13560,13710,13950,14110,14260,14410,14560,14710,
+        14860,15010,15170,15320,15470,15620,15770,15920,16080,16230,
+        16470,16620,16770,16920,17070,17220,17360,17510,17670,17820,
+        17960,18110,18260,18410,18560,18710,18950,19100,19250,19400,
+        19550,19700,19850,20000,20150,20300,20450,20600,20750,20900,
+        21040,21190,21430,21580,21730,21880,22030,22180,22330,22480,
+        22630,22780,22930,23080,23230,23380,23530,23680
+};
+const U16 gRXVref_Voltage_Table_0P5V_UT[EYESCAN_RX_VREF_RANGE_END] = {
+        7890,8190,8490,8780,9080,9380,9670,9970,10270,10560,
+        10860,11160,11450,11750,12050,12350,12830,13120,13420,13720,
+        14010,14310,14610,14900,15200,15500,15800,16090,16390,16680,
+        16980,17280,17760,18060,18350,18650,18940,19240,19540,19830,
+        20130,20430,20720,21020,21320,21610,21910,22210,22690,22990,
+        23290,23590,23900,24200,24500,24800,25100,25410,25710,26010,
+        26310,26610,26920,27220,27700,28000,28300,28610,28910,29210,
+        29510,29810,30110,30420,30720,31020,31320,31620,31920,32220,
+        32700,32990,33290,33590,33880,34180,34480,34770,35070,35370,
+        35670,35970,36260,36560,36860,37150,37630,37930,38220,38520,
+        38820,39110,39410,39710,40010,40300,40600,40900,41190,41490,
+        41790,42090,42560,42860,43150,43450,43750,44040,44340,44630,
+        44930,45230,45530,45820,46120,46420,46710,47010
+};
+const U16 gRXVref_Voltage_Table_0P3V_UT[EYESCAN_RX_VREF_RANGE_END] = {
+        4720,4900,5080,5250,5430,5600,5780,5950,6130,6310,
+        6480,6660,6840,7010,7190,7370,7650,7830,8010,8180,
+        8360,8540,8710,8890,9070,9240,9420,9590,9770,9950,
+        10120,10300,10580,10760,10940,11110,11290,11470,11640,11820,
+        12000,12170,12350,12530,12700,12880,13050,13230,13520,13700,
+        13880,14060,14240,14420,14600,14780,14960,15140,15320,15500,
+        15680,15860,16030,16220,16500,16680,16860,17040,17220,17400,
+        17580,17760,17940,18120,18300,18480,18660,18840,19010,19190,
+        19480,19660,19830,20010,20190,20360,20540,20720,20900,21070,
+        21250,21430,21600,21780,21960,22130,22420,22600,22780,22950,
+        23130,23310,23480,23660,23840,24010,24190,24370,24540,24720,
+        24900,25080,25360,25540,25710,25890,26070,26240,26420,26600,
+        26780,26950,27130,27310,27480,27660,27840,28020
+};
+const U16 gRXVref_Voltage_Table_0P6V_T[EYESCAN_RX_VREF_RANGE_END] = {
+        4790,4970,5150,5330,5500,5680,5860,6040,6220,6390,
+        6570,6750,6930,7110,7290,7470,7770,7950,8130,8310,
+        8490,8660,8840,9020,9200,9380,9560,9740,9920,10100,
+        10280,10460,10750,10930,11110,11280,11460,11640,11820,12000,
+        12180,12360,12540,12720,12900,13080,13250,13430,13720,13910,
+        14090,14270,14450,14640,14820,15000,15180,15370,15550,15730,
+        15910,16100,16280,16460,16750,16940,17120,17300,17480,17660,
+        17850,18030,18210,18390,18580,18760,18940,19120,19300,19490,
+        19780,19960,20140,20310,20490,20670,20850,21030,21210,21390,
+        21570,21750,21930,22110,22290,22470,22760,22940,23120,23300,
+        23480,23650,23830,24010,24190,24370,24550,24730,24910,25090,
+        25270,25450,25740,25920,26100,26280,26450,26630,26810,26990,
+        27170,27350,27530,27710,27890,28070,28250,28430
+};
+const U16 gRXVref_Voltage_Table_0P6V_UT[EYESCAN_RX_VREF_RANGE_END] = {
+        9470,9830,10190,10540,10900,11260,11610,11970,12330,12680,
+        13040,13400,13750,14110,14460,14820,15400,15760,16120,16470,
+        16830,17180,17540,17890,18250,18610,18970,19320,19680,20040,
+        20390,20750,21330,21680,22040,22400,22750,23110,23460,23820,
+        24180,24530,24890,25250,25600,25960,26310,26670,27250,27610,
+        27970,28330,28700,29060,29420,29780,30150,30520,30880,31240,
+        31600,31960,32330,32690,33270,33630,33990,34350,34710,35080,
+        35440,35800,36160,36530,36890,37250,37610,37970,38330,38700,
+        39270,39630,39980,40340,40690,41050,41410,41760,42120,42480,
+        42840,43190,43550,43900,44260,44620,45190,45550,45910,46260,
+        46620,46970,47330,47680,48040,48400,48760,49110,49470,49820,
+        50180,50540,51120,51480,51830,52190,52540,52890,53250,53600,
+        53960,54320,54670,55030,55380,55740,56090,56450
+};
+const U16 gRXVref_Voltage_Table_LP4[EYESCAN_RX_VREF_RANGE_END+1]={
+#if __Petrus_TO_BE_PORTING__
+        (364+821)/2,
+        (1202+1621)/2,
+        (2039+2420)/2,
+        (2875+3219)/2,
+        (3711+4018)/2,
+        (4548+4817)/2,
+        (5384+5615)/2,
+        (6221+6414)/2,
+        (7057+7213)/2,
+        (7893+8012)/2,
+        (8727+8811)/2,
+        (9554+9618)/2,
+        (10380+10430)/2,
+        (11200+11250)/2,
+        (12010+12080)/2,
+        (12810+12910)/2,
+        (13120+13540)/2,
+        (13830+14210)/2,
+        (14530+14870)/2,
+        (15240+15540)/2,
+        (15950+16210)/2,
+        (16650+16880)/2,
+        (17360+17550)/2,
+        (18070+18220)/2,
+        (18770+18890)/2,
+        (19470+19560)/2,
+        (20160+20240)/2,
+        (20850+20930)/2,
+        (21520+21610)/2,
+        (22190+22310)/2,
+        (22860+23010)/2,
+        (23540+23720)/2,
+        (23330+23770)/2,
+        (24040+24430)/2,
+        (24740+25090)/2,
+        (25450+25740)/2,
+        (26150+26400)/2,
+        (26860+27060)/2,
+        (27560+27730)/2,
+        (28240+28400)/2,
+        (28920+29070)/2,
+        (29580+29730)/2,
+        (30230+30410)/2,
+        (30890+31100)/2,
+        (31540+31790)/2,
+        (32190+32490)/2,
+        (32840+33200)/2,
+        (33500+33900)/2,
+        (33540+34030)/2,
+        (34250+34660)/2,
+        (34950+35300)/2,
+        (35650+35950)/2,
+        (36360+36600)/2,
+        (37060+37250)/2,
+        (37760+37900)/2,
+        (38420+38560)/2,
+        (39050+39230)/2,
+        (39680+39900)/2,
+        (40310+40590)/2,
+        (40940+41280)/2,
+        (41570+41990)/2,
+        (42190+42690)/2,
+        (42820+43400)/2,
+        (43450+44100)/2,
+#endif
+};
+
+const U16 gVref_Voltage_Table_LP4X[VREF_RANGE_MAX][VREF_VOLTAGE_TABLE_NUM_LP4] = {
+    {1500, 1560, 1620, 1680, 1740, 1800, 1860, 1920, 1980, 2040, 2100, 2160, 2220, 2280, 2340, 2400, 2460, 2510, 2570, 2630, 2690, 2750, 2810, 2870, 2930, 2990, 3050, 3110, 3170, 3230, 3290, 3350, 3410, 3470, 3530, 3590, 3650, 3710, 3770, 3830, 3890, 3950, 4010, 4070, 4130, 4190, 4250, 4310, 4370, 4430, 4490},
+    {3290, 3350, 3410, 3470, 3530, 3590, 3650, 3710, 3770, 3830, 3890, 3950, 4010, 4070, 4130, 4190, 4250, 4310, 4370, 4430, 4490, 4550, 4610, 4670, 4730, 4790, 4850, 4910, 4970, 5030, 5090, 5150, 5210, 5270, 5330, 5390, 5450, 5510, 5570, 5630, 5690, 5750, 5810, 5870, 5930, 5990, 6050, 6110, 6170, 6230, 6290}
+};
+const U16 gVref_Voltage_Table_LP4[VREF_RANGE_MAX][VREF_VOLTAGE_TABLE_NUM_LP4] = {
+    {1000, 1040, 1080, 1120, 1160, 1200, 1240, 1280, 1320, 1360, 1400, 1440, 1480, 1520, 1560, 1600, 1640, 1680, 1720, 1760, 1800, 1840, 1880, 1920, 1960, 2000, 2040, 2080, 2120, 2160, 2200, 2240, 2280, 2320, 2360, 2400, 2440, 2480, 2520, 2560, 2600, 2640, 2680, 2720, 2760, 2800, 2840, 2880, 2920, 2960, 3000},
+    {2200, 2240, 2280, 2320, 2360, 2400, 2440, 2480, 2520, 2560, 2600, 2640, 2680, 2720, 2760, 2800, 2840, 2880, 2920, 2960, 3000, 3040, 3080, 3120, 3160, 3200, 3240, 3280, 3320, 3360, 3400, 3440, 3480, 3520, 3560, 3600, 3640, 3680, 3720, 3760, 3880, 3840, 3880, 3920, 3960, 4000, 4040, 4080, 4120, 4160, 4200}
+};
+const U16 gVref_Voltage_Table_LP5[VREF_VOLTAGE_TABLE_NUM_LP5] = {
+   1000,1050,1100,1150,1200,1250,1300,1350,1400,1450,
+   1500,1550,1600,1650,1700,1750,1800,1850,1900,1950,
+   2000,2050,2100,2150,2200,2250,2300,2350,2400,2450,
+   2500,2550,2600,2650,2700,2750,2800,2850,2900,2950,
+   3000,3050,3100,3150,3200,3250,3300,3350,3400,3450,
+   3500,3550,3600,3650,3700,3750,3800,3850,3900,3950,
+   4000,4050,4100,4150,4200,4250,4300,4350,4400,4450,
+   4500,4550,4600,4650,4700,4750,4800,4850,4900,4950,
+   5000,5050,5100,5150,5200,5250,5300,5350,5400,5450,
+   5500,5550,5600,5650,5700,5750,5800,5850,5900,5950,
+   6000,6050,6100,6150,6200,6250,6300,6350,6400,6450,
+   6500,6550,6600,6650,6700,6750,6800,6850,6900,6950,
+   7000,7050,7100,7150,7200,7250,7300,7350
+};
+#endif
+
+
+#if ENABLE_EYESCAN_GRAPH
+__NOBITS_SECTION__(.gEyeScan_Min) S16 gEyeScan_Min[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH][EYESCAN_BROKEN_NUM];
+__NOBITS_SECTION__(.gEyeScan_Max) S16 gEyeScan_Max[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH][EYESCAN_BROKEN_NUM];
+U16  gEyeScan_CaliDelay[DQS_BYTE_NUMBER];
+S16 gEyeScan_MinMax_store_delay[DQS_BYTE_NUMBER];
+__NOBITS_SECTION__(.gEyeScan_WinSize) U16 gEyeScan_WinSize[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH];
+S16  gEyeScan_DelayCellPI[DQ_DATA_WIDTH];
+U16  gEyeScan_ContinueVrefHeight[DQ_DATA_WIDTH];
+U16  gEyeScan_TotalPassCount[DQ_DATA_WIDTH];
+#endif
+
+const char* HQA_LOG_Parsing_Freq(void)
+{
+    if (gHQA_Test_Freq_Vcore_Level != 0)
+    {
+        return (gHQA_Test_Freq_Vcore_Level == 1? "_L" : "_H");
+    }
+
+    return " ";
+}
+void HQA_LOG_Print_Prefix_String(DRAMC_CTX_T *p)
+{
+    mcSHOW_DBG_MSG(("[HQALOG] %d%s ", p->frequency * 2, HQA_LOG_Parsing_Freq() ));
+}
+
+void HQA_LOG_Print_Freq_String(DRAMC_CTX_T *p)
+{
+#if VENDER_JV_LOG
+    mcSHOW_EYESCAN_MSG(("%d%s ", p->frequency * 2, HQA_LOG_Parsing_Freq() ));
+#else
+    mcSHOW_DBG_MSG(("%d%s ", p->frequency * 2, HQA_LOG_Parsing_Freq() ));
+#endif
+}
+
+#ifdef FOR_HQA_TEST_USED
+static void EYESCAN_LOG_Print_Prefix_String(void)
+{
+    mcSHOW_DBG_MSG(("[EYESCAN_LOG] "));
+}
+
+static const char* print_EYESCAN_LOG_type(U8 print_type)
+{
+    switch (print_type)
+    {
+        case EYESCAN_TYPE_CBT: return "CBT";
+        case EYESCAN_TYPE_RX: return "RX";
+        default:
+        case EYESCAN_TYPE_TX: return "TX";
+    }
+}
+
+
+
+void HQA_measure_message_reset_all_data(DRAMC_CTX_T *p)
+{
+    U32 uiCA, u1BitIdx, u1ByteIdx, u1RankIdx, u1ChannelIdx;
+
+    for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < CHANNEL_NUM; u1ChannelIdx++)
+    {
+        for (u1RankIdx = RANK_0; u1RankIdx < RANK_MAX; u1RankIdx++)
+        {
+            for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
+            {
+                gFinalRXPerbitWin[u1ChannelIdx][u1RankIdx][u1BitIdx] = 0;
+                gFinalTXPerbitWin[u1ChannelIdx][u1RankIdx][u1BitIdx] = 0;
+            }
+        }
+    }
+}
+
+void print_HQA_SLT_BIN_message(DRAMC_CTX_T *p)
+{
+    S8 u1ShuIdx;
+    S8 ucstatus;
+
+    if (gHQALog_flag == 1)
+    {
+        ucstatus = 0;
+        for (u1ShuIdx = DRAM_DFS_SRAM_MAX - 1; u1ShuIdx >= SRAM_SHU0; u1ShuIdx--)
+        {
+            if (gHQALog_SLT_BIN[u1ShuIdx] != 0)
+            {
+                mcSHOW_DBG_MSG(("SLT_BIN%d\n", gHQALog_SLT_BIN[u1ShuIdx]));
+                ucstatus = 1;
+            }
+        }
+
+        if (ucstatus==0)
+        {
+            mcSHOW_DBG_MSG(("SLT_BIN1\n"));
+        }
+    }
+}
+
+#if defined(FOR_HQA_REPORT_USED)
+void print_HQA_message_before_CalibrationAllChannel(DRAMC_CTX_T *p)
+{
+    HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DBI_W_ONOFF %d\n", p->DBI_W_onoff[p->dram_fsp]));
+}
+#endif
+
+#ifdef RELEASE
+#undef mcSHOW_DBG_MSG
+#define mcSHOW_DBG_MSG(_x_) opt_print _x_
+#endif
+void print_HQA_measure_message(DRAMC_CTX_T *p)
+{
+    U32 uiCA, u1BitIdx, u1ByteIdx, u1RankIdx, u1ChannelIdx;
+    U32 min_ca_value[CHANNEL_NUM][RANK_MAX], min_ca_bit[CHANNEL_NUM][RANK_MAX];
+    U32 min_rx_value[CHANNEL_NUM][RANK_MAX], min_tx_value[CHANNEL_NUM][RANK_MAX];
+    U32 min_RX_DQ_bit[CHANNEL_NUM][RANK_MAX], min_TX_DQ_bit[CHANNEL_NUM][RANK_MAX];
+    U8 SRAMIdx, local_channel_num = CHANNEL_NUM, shuffle_index;
+    U8 print_imp_option[2] = {FALSE, FALSE};
+    int i;
+    U32 read_voltage_value;
+
+    mcSHOW_DBG_MSG(("\n\n\n[HQA] information for measurement, "));
+    mcSHOW_DBG_MSG(("\tDram Data rate = ")); HQA_LOG_Print_Freq_String(p); mcSHOW_DBG_MSG(("\n"));
+    //mcDUMP_REG_MSG(("\n\n\n[HQA] information for measurement, "));
+    //mcDUMP_REG_MSG(("\tDram Data rate = "));
+    //mcDUMP_REG_MSG(("%d%s ", p->frequency * 2, HQA_LOG_Parsing_Freq() ));
+    //mcDUMP_REG_MSG(("\n"));
+    vPrintCalibrationBasicInfo(p);
+    HQA_LOG_Print_Prefix_String(p);
+    mcSHOW_DBG_MSG(("Frequency = %u\n", DDRPhyGetRealFreq(p)));
+
+
+    if (gHQALog_flag == 1)
+    {
+        HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("ETT_Commit_Version = %s\n", _COMMIT_VERSION_));
+        HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("ETT_Commit_Date = %s\n", _COMMIT_DATE_));
+        HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Frequency = %d\n", DDRPhyGetRealFreq(p)));
+        HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("fsp = %d\n", p->dram_fsp));
+        HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("odt_onoff = %d\n", p->odt_onoff));
+        HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("byte_mode = %d\n", p->dram_cbt_mode[p->rank]));
+        HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DivMode = %d\n", vGet_Div_Mode(p)));
+    }
+    SRAMIdx = vGet_Current_SRAMIdx(p);
+
+    if (u1IsLP4Family(p->dram_type))
+    {
+        local_channel_num = p->support_channel_num;
+    }
+
+    for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+    {
+        for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+        {
+            min_ca_value[u1ChannelIdx][u1RankIdx] = 0xffff;
+            min_rx_value[u1ChannelIdx][u1RankIdx] = 0xffff;
+            min_tx_value[u1ChannelIdx][u1RankIdx] = 0xffff;
+            min_RX_DQ_bit[u1ChannelIdx][u1RankIdx] = 0xffff;
+            min_TX_DQ_bit[u1ChannelIdx][u1RankIdx] = 0xffff;
+
+            for (uiCA = 0; uiCA < ((u1IsLP4Family(p->dram_type) == 1)? CATRAINING_NUM_LP4: CATRAINING_NUM_LP5); uiCA++)
+            {
+                if (gFinalCBTCA[u1ChannelIdx][u1RankIdx][uiCA] < min_ca_value[u1ChannelIdx][u1RankIdx])
+                {
+                    min_ca_value[u1ChannelIdx][u1RankIdx] = gFinalCBTCA[u1ChannelIdx][u1RankIdx][uiCA];
+                    min_ca_bit[u1ChannelIdx][u1RankIdx] = uiCA;
+                }
+            }
+
+            for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
+            {
+                if (gFinalRXPerbitWin[u1ChannelIdx][u1RankIdx][u1BitIdx] < min_rx_value[u1ChannelIdx][u1RankIdx])
+                {
+                    min_rx_value[u1ChannelIdx][u1RankIdx] = gFinalRXPerbitWin[u1ChannelIdx][u1RankIdx][u1BitIdx];
+                    min_RX_DQ_bit[u1ChannelIdx][u1RankIdx] = u1BitIdx;
+                }
+                if (gFinalTXPerbitWin[u1ChannelIdx][u1RankIdx][u1BitIdx] < min_tx_value[u1ChannelIdx][u1RankIdx])
+                {
+                    min_tx_value[u1ChannelIdx][u1RankIdx] = gFinalTXPerbitWin[u1ChannelIdx][u1RankIdx][u1BitIdx];
+                    min_TX_DQ_bit[u1ChannelIdx][u1RankIdx] = u1BitIdx;
+                }
+            }
+        }
+    }
+
+
+    if (p->support_rank_num == RANK_DUAL)
+    {
+        //Preloader LP3 RX/TX only K Rank0, so Rank1 use Rank0's value
+        if (!u1IsLP4Family(p->dram_type))
+        {
+#ifndef LP3_DUAL_RANK_RX_K
+            min_rx_value[0][1] = min_rx_value[0][0];
+            min_RX_DQ_bit[0][1] = min_RX_DQ_bit[0][0];
+#endif
+
+#ifndef LP3_DUAL_RANK_TX_K
+            min_tx_value[0][1] = min_tx_value[0][0];
+            gFinalTXPerbitWin_min_max[0][1] = gFinalTXPerbitWin_min_max[0][0];
+            min_TX_DQ_bit[0][1] = min_TX_DQ_bit[0][0];
+#endif
+
+            #if 0//(TX_PER_BIT_DELAY_CELL==0)
+            gFinalTXPerbitWin_min_margin[0][1] = gFinalTXPerbitWin_min_margin[0][0];
+            gFinalTXPerbitWin_min_margin_bit[0][1] = gFinalTXPerbitWin_min_margin_bit[0][0];
+            #endif
+        }
+    }
+
+
+#if defined(DRAM_HQA)
+        mcSHOW_DBG_MSG(("[Read Voltage]\n"));
+        read_voltage_value = vGetVoltage(p, 0);
+        HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vcore_HQA = %d\n", read_voltage_value));
+
+        if (u1IsLP4Family(p->dram_type)) {
+            /* LPDDR4 */
+            read_voltage_value = vGetVoltage(p, 1);
+            HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vdram_HQA = %d\n", read_voltage_value));
+            read_voltage_value = vGetVoltage(p, 2);
+            HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vddq_HQA = %d\n", read_voltage_value));
+            read_voltage_value = vGetVoltage(p, 3);
+            HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vdd1_HQA = %d\n", read_voltage_value)); /* confirm with pmic owner¡Athis vio18 is pmic 6359 's vm18, is different with vio18 of system */
+            read_voltage_value = vGetVoltage(p, 4);
+            HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vmddr_HQA = %d\n", read_voltage_value));
+        } else {
+            /* LPDDR3 */
+            read_voltage_value = vGetVoltage(p, 1);
+            HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vdram_HQA = %d\n", read_voltage_value));
+        }
+        mcSHOW_DBG_MSG(("\n"));
+#endif
+
+    /*
+        [Impedance Calibration]
+
+        freq_region=0
+        [HQALOG] Impedance freq_region=0 DRVP 11
+        [HQALOG] Impedance freq_region=0 DRVN 7
+
+        freq_region=1
+        [HQALOG] Impedance freq_region=1 DRVP 13
+        [HQALOG] Impedance freq_region=1 ODTN 15
+    */
+    if (p->dram_type == TYPE_LPDDR4)
+    {
+        print_imp_option[1] = TRUE;
+    }
+    else if (p->dram_type == TYPE_LPDDR4X)
+    {
+        print_imp_option[0] = TRUE;
+        print_imp_option[1] = TRUE;
+    }
+    else
+    {
+      //TYPE_LPDDR4P, TYPE_LPDDR3
+      print_imp_option[0] = TRUE;
+    }
+
+#ifdef FOR_HQA_REPORT_USED
+if (gHQALog_flag == 1)
+{
+    mcSHOW_DBG_MSG(("[Impedance Calibration]\n"));
+
+    HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT6, "Impedance freq_region=0 ", "DRVP", 0, gDramcImpedanceResult[0][DRVP], NULL);
+    HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT6, "Impedance freq_region=0 ", "DRVN", 0, gDramcImpedanceResult[0][DRVN], NULL);
+    HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT6, "Impedance freq_region=0 ", "ODTN", 0, gDramcImpedanceResult[0][ODTN], NULL);
+
+    HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT6, "Impedance freq_region=1 ", "DRVP", 0, gDramcImpedanceResult[1][DRVP], NULL);
+    HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT6, "Impedance freq_region=1 ", "DRVN", 0, gDramcImpedanceResult[1][DRVN], NULL);
+    HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT6, "Impedance freq_region=1 ", "ODTN", 0, gDramcImpedanceResult[1][ODTN], NULL);
+
+    mcSHOW_DBG_MSG(("\n"));
+}
+#endif
+
+
+
+
+
+    mcSHOW_DBG_MSG(("\n[Cmd Bus Training window]\n"));
+
+    if (u1IsLP4Family(p->dram_type))
+    {
+        //TO DO: jimmy
+    //mcSHOW_DBG_MSG(("VrefCA Range : %d\n", gCBT_VREF_RANGE_SEL));
+        /*
+         VrefCA
+             [HQALOG] 1600 VrefCA Channel0 Rank0 32
+             [HQALOG] 1600 VrefCA Channel0 Rank1 24
+             [HQALOG] 1600 VrefCA Channel1 Rank0 26
+             [HQALOG] 1600 VrefCA Channel1 Rank1 30
+         */
+        mcSHOW_DBG_MSG(("VrefCA\n"));
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+            for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+            {
+                HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("VrefCA Channel%d "
+                                "Rank%d %d\n",
+                            u1ChannelIdx,
+                                u1RankIdx,
+                                gFinalCBTVrefCA[u1ChannelIdx][u1RankIdx]));
+            }
+        }
+    }
+
+#if 0//(SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_CBT)
+    if (p->femmc_Ready == 1 )
+    {
+        mcSHOW_DBG_MSG(("\n[Cmd Bus Training window bypass calibration]\n"));
+    }
+    else
+#endif
+    {
+        /*
+         CA_Window
+             [HQALOG] 1600 CA_Window Channel0 Rank0 61(bit 2)
+             [HQALOG] 1600 CA_Window Channel0 Rank1 62(bit 1)
+             [HQALOG] 1600 CA_Window Channel1 Rank0 60(bit 5)
+             [HQALOG] 1600 CA_Window Channel1 Rank1 60(bit 5)
+         */
+        mcSHOW_DBG_MSG(("CA_Window\n"));
+#ifdef FOR_HQA_REPORT_USED
+if (gHQALog_flag == 1)
+{
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+            for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+            {
+                    HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "CA", "_Window", 0, min_ca_value[u1ChannelIdx][u1RankIdx], NULL);
+                    HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "CA", "_Window_bit", 0, min_ca_bit[u1ChannelIdx][u1RankIdx], NULL);
+            }
+        }
+        mcSHOW_DBG_MSG(("\n"));
+}
+else
+#endif
+{
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+            for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+            {
+                HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("CA_Window Channel%d "
+                                "Rank%d %d (bit %d)\n",
+                                u1ChannelIdx,
+                                u1RankIdx,
+                                min_ca_value[u1ChannelIdx][u1RankIdx], min_ca_bit[u1ChannelIdx][u1RankIdx]));
+            }
+        }
+}
+
+        /*
+         CA Min Window(%)
+             [HQALOG] 1600 CA_Window(%) Channel0 Rank0 96%(PASS)
+             [HQALOG] 1600 CA_Window(%) Channel0 Rank1 97%(PASS)
+             [HQALOG] 1600 CA_Window(%) Channel1 Rank0 94%(PASS)
+             [HQALOG] 1600 CA_Window(%) Channel1 Rank1 94%(PASS)
+         */
+        mcSHOW_DBG_MSG(("CA Min Window(%%)\n"));
+#ifdef FOR_HQA_REPORT_USED
+if (gHQALog_flag == 1)
+{
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+            for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+            {
+                HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "CA", "_Window(%)", 0, ((min_ca_value[u1ChannelIdx][u1RankIdx] * 100 + (u1IsLP4Family(p->dram_type) == 1? 63: 31)) / (u1IsLP4Family(p->dram_type) == 1? 64: 32)), NULL);
+                HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT4, "CA", "_Window_PF", 0, 0, ((((min_ca_value[u1ChannelIdx][u1RankIdx] * 100 + (u1IsLP4Family(p->dram_type)==1?63:31)) / (u1IsLP4Family(p->dram_type)==1?64:32)) >= 30) ? "PASS" : "FAIL"));
+            }
+        }
+        mcSHOW_DBG_MSG(("\n"));
+}
+else
+#endif
+{
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+            for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+            {
+                HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("CA_Window(%%) Channel%d "
+                                "Rank%d %d%% (%s)\n",
+                                u1ChannelIdx,
+                                u1RankIdx,
+                                        ((min_ca_value[u1ChannelIdx][u1RankIdx] * 100 + (u1IsLP4Family(p->dram_type) == 1? 63: 31)) / (u1IsLP4Family(p->dram_type) == 1? 64: 32)),
+                                    ((((min_ca_value[u1ChannelIdx][u1RankIdx] * 100 + (u1IsLP4Family(p->dram_type) == 1? 63: 31)) / (u1IsLP4Family(p->dram_type) == 1? 64: 32)) >= 30)? "PASS" : "FAIL")));
+            }
+        }
+}
+    }
+            mcSHOW_DBG_MSG(("\n"));
+
+
+
+
+    /*
+    [RX minimum per bit window]
+    Delay cell measurement (/100ps)
+    [HQALOG] 3200 delaycell 892
+    */
+    mcSHOW_DBG_MSG(("\n[RX minimum per bit window]\n"));
+    mcSHOW_DBG_MSG(("Delaycell measurement(/100ps)\n"));
+
+#if defined(FOR_HQA_REPORT_USED) && !defined(RELEASE) && (VENDER_JV_LOG == 0)
+    HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("delaycell %d\n",
+                    gHQALOG_RX_delay_cell_ps_075V));
+#endif
+#if defined(FOR_HQA_REPORT_USED)
+    if (gHQALog_flag == 1)
+    {
+        if ((gHQALOG_RX_delay_cell_ps_075V < 245) || (gHQALOG_RX_delay_cell_ps_075V > 300))
+        {
+            gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 2; //SLT_BIN2
+        }
+    }
+#endif
+    /*
+     VrefDQ
+         [HQALOG] 1600 VrefRX Channel0 24
+         [HQALOG] 1600 VrefRX Channel1 24
+     */
+
+    if (u1IsLP4Family(p->dram_type))
+    {
+            mcSHOW_DBG_MSG(("VrefRX\n"));
+            if (gRX_EYE_Scan_flag == 1)
+            {
+                for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+                {
+                    for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+                    {
+                        for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+                        {
+                            HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("VrefRX Channel%d Rank%d Byte%d %d\n",
+                                        u1ChannelIdx,
+                                        u1RankIdx,
+                                        u1ByteIdx,
+                                        gFinalRXVrefDQ[u1ChannelIdx][u1RankIdx][u1ByteIdx]));
+                        }
+                    }
+                }
+            }
+            else
+            {
+                for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+                {
+                    for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+                    {
+                        HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("VrefRX Channel%d Byte%d %d\n",
+                                    u1ChannelIdx,
+                                    u1ByteIdx,
+                                    gFinalRXVrefDQ[u1ChannelIdx][RANK_0][u1ByteIdx]));
+                    }
+                }
+            }
+        }
+
+#if 0//(SUPPORT_SAVE_TIME_FOR_CALIBRATION )
+    if (p->femmc_Ready == 1 && ( p->Bypass_RXWINDOW))
+    {
+        mcSHOW_DBG_MSG(("\n[RX minimum per bit window bypass calibration]\n"));
+    }
+    else
+#endif
+    {
+        /*
+         RX_Window
+             [HQALOG] 1600 RX_Window Channel0 Rank0 52(bit 2)
+             [HQALOG] 1600 RX_Window Channel0 Rank1 52(bit 2)
+             [HQALOG] 1600 RX_Window Channel1 Rank0 60(bit 12)
+             [HQALOG] 1600 RX_Window Channel1 Rank1 62(bit 9)
+         */
+        mcSHOW_DBG_MSG(("RX_Window\n"));
+#ifdef FOR_HQA_REPORT_USED
+if (gHQALog_flag == 1)
+{
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+            for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+            {
+                    HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "RX", "_Window", 0, min_rx_value[u1ChannelIdx][u1RankIdx], NULL);
+                    HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "RX", "_Window_bit", 0, min_RX_DQ_bit[u1ChannelIdx][u1RankIdx], NULL);
+            }
+        }
+}
+else
+#endif
+{
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+            for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+            {
+                HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("RX_Window Channel%d "
+                                "Rank%d %d (bit %d)\n",
+                            u1ChannelIdx,
+                                u1RankIdx,
+                                min_rx_value[u1ChannelIdx][u1RankIdx], min_RX_DQ_bit[u1ChannelIdx][u1RankIdx]));
+            }
+        }
+}
+
+        /*
+         RX Min Window(%)
+             [HQALOG] 1600 RX_Window(%) Channel0 Rank0 43316/100ps(70%)(PASS)
+             [HQALOG] 1600 RX_Window(%) Channel0 Rank1 43316/100ps(70%)(PASS)
+             [HQALOG] 1600 RX_Window(%) Channel1 Rank0 49980/100ps(80%)(PASS)
+             [HQALOG] 1600 RX_Window(%) Channel1 Rank1 51646/100ps(83%)(PASS)
+         */
+        mcSHOW_DBG_MSG(("RX Window(%%)\n"));
+#ifdef FOR_HQA_REPORT_USED
+if (gHQALog_flag == 1)
+{
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+            for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+            {
+                HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "RX", "_Window(%)", 0, ((min_rx_value[u1ChannelIdx][u1RankIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, NULL);
+                HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT4, "RX", "_Window_PF", 0, 0, (min_rx_value[u1ChannelIdx][u1RankIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) / 1000000 >= 40 ? "PASS" : "FAIL");
+
+                if ((((min_rx_value[u1ChannelIdx][u1RankIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000) < 55)
+                {
+                    gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 4; //SLT_BIN4
+                }
+            }
+        }
+}
+else
+{
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+            for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+            {
+                HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("RX_Window(%%) Channel%d "
+                                "Rank%d "
+                                "%d/100ps (%d%%) (%s)\n",
+                                u1ChannelIdx,
+                                u1RankIdx,
+                                min_rx_value[u1ChannelIdx][u1RankIdx] * gHQALOG_RX_delay_cell_ps_075V,
+                                ((min_rx_value[u1ChannelIdx][u1RankIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000,
+                                ((min_rx_value[u1ChannelIdx][u1RankIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000 >= 40? "PASS" : "FAIL"));
+            }
+        }
+}
+#endif
+        mcSHOW_DBG_MSG(("\n"));
+    }
+
+
+
+
+
+
+    /* [TX minimum per bit window]
+     VrefDQ Range : 1
+     VrefDQ
+         [HQALOG] 1600 VrefTX Channel0 Rank0 30
+         [HQALOG] 1600 VrefTX Channel0 Rank1 25
+         [HQALOG] 1600 VrefTX Channel1 Rank0 24
+         [HQALOG] 1600 VrefTX Channel1 Rank1 23
+     */
+    mcSHOW_DBG_MSG(("\n[TX minimum per bit window]\n"));
+    if (u1IsLP4Family(p->dram_type))
+    {
+        if (Get_Vref_Calibration_OnOff(p) == VREF_CALI_ON)
+        {
+            mcSHOW_DBG_MSG(("VrefDQ Range : %d\n", (u1MR14Value[p->channel][p->rank][p->dram_fsp] >> 6) & 1));
+            mcSHOW_DBG_MSG(("VrefDQ\n"));
+            for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+            {
+                for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+                {
+                    HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("VrefDQ Channel%d "
+                                    "Rank%d %d\n",
+                                    u1ChannelIdx,
+                                    u1RankIdx,
+                                    gFinalTXVrefDQ[u1ChannelIdx][u1RankIdx]));
+                }
+            }
+        }
+        else
+        {
+            mcSHOW_DBG_MSG(("TX DQ Vref Scan : Disable\n"));
+        }
+    }
+#if 0//(SUPPORT_SAVE_TIME_FOR_CALIBRATION )
+    if (p->femmc_Ready == 1 && (p->Bypass_TXWINDOW))
+    {
+        mcSHOW_DBG_MSG(("\n[TX minimum per bit window bypass calibration]\n"));
+    }
+    else
+#endif
+    {
+        /*
+         TX_Window
+             [HQALOG] 1600 TX_Window Channel0 Rank0 25(bit 2)
+             [HQALOG] 1600 TX_Window Channel0 Rank1 25(bit 2)
+             [HQALOG] 1600 TX_Window Channel1 Rank0 22(bit 9)
+             [HQALOG] 1600 TX_Window Channel1 Rank1 23(bit 9)
+         */
+        mcSHOW_DBG_MSG(("TX_Window\n"));
+#ifdef FOR_HQA_REPORT_USED
+if (gHQALog_flag == 1)
+{
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+            for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+            {
+                    HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "TX", "_Window", 0, gFinalTXPerbitWin_min_max[u1ChannelIdx][u1RankIdx], NULL);
+                    HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "TX", "_Window_bit", 0, min_TX_DQ_bit[u1ChannelIdx][u1RankIdx], NULL);
+            }
+        }
+}
+else
+#endif
+{
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+            for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+            {
+                HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("TX_Window Channel%d "
+                                "Rank%d %d (bit %d)\n",
+                                u1ChannelIdx,
+                                u1RankIdx,
+                                gFinalTXPerbitWin_min_max[u1ChannelIdx][u1RankIdx], min_TX_DQ_bit[u1ChannelIdx][u1RankIdx]));
+            }
+        }
+}
+#if 0//(TX_PER_BIT_DELAY_CELL==0)
+        mcSHOW_DBG_MSG(("min DQ margin\n"));
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+            for (u1RankIdx = RANK_0; u1RankIdx < 2; u1RankIdx++)
+            {
+                HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("min_DQ_margin Channel%d "
+                                "Rank%d %d (bit %d)\n",
+                                u1ChannelIdx,
+                                u1RankIdx,
+                                gFinalTXPerbitWin_min_margin[u1ChannelIdx][u1RankIdx], gFinalTXPerbitWin_min_margin_bit[u1ChannelIdx][u1RankIdx]));
+            }
+        }
+#endif
+
+
+        /*
+         TX Min Window(%)
+             [HQALOG] 1600 TX_Window(%) Channel0 Rank0 79%(PASS)
+             [HQALOG] 1600 TX_Window(%) Channel0 Rank1 79%(PASS)
+             [HQALOG] 1600 TX_Window(%) Channel1 Rank0 69%(PASS)
+             [HQALOG] 1600 TX_Window(%) Channel1 Rank1 72%(PASS)
+         */
+        mcSHOW_DBG_MSG(("TX Min Window(%%)\n"));
+#ifdef FOR_HQA_REPORT_USED
+if (gHQALog_flag == 1)
+{
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+            for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+            {
+                /*
+                                Item Data Rate Mode Status
+                                1 DDR1600 1:4 mode Done
+                                2 DDR1200 1:4 mode Done
+                                3 DDR800 1:4 mode 1UI=64PI special case
+                */
+                HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "TX", "_Window(%)", 0, (min_tx_value[u1ChannelIdx][u1RankIdx] * 100 + (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 63: 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 64: 32), NULL);
+                HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT4, "TX", "_Window_PF", 0, 0, (min_tx_value[u1ChannelIdx][u1RankIdx] * 100 + (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP ? 63 : 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP ? 64 : 32) >= 45 ? "PASS" : "FAIL");
+
+                if (((min_tx_value[u1ChannelIdx][u1RankIdx] * 100 + (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 63: 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 64: 32)) < 55)
+                {
+                    gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 4; //SLT_BIN4
+                }
+            }
+        }
+}
+else
+#endif
+{
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+            for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+            {
+                /*
+                                Item Data Rate Mode Status
+                                1 DDR1600 1:4 mode Done
+                                2 DDR1200 1:4 mode Done
+                                3 DDR800 1:4 mode 1UI=64PI special case
+                */
+
+                HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("TX_Window(%%) Channel%d "
+                                "Rank%d %d%% (%s)\n",
+                                u1ChannelIdx,
+                                u1RankIdx,
+                               (min_tx_value[u1ChannelIdx][u1RankIdx] * 100 + (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 63: 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 64: 32),
+                               (min_tx_value[u1ChannelIdx][u1RankIdx] * 100 + (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 63: 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 64: 32) >= 45? "PASS" : "FAIL"));
+            }
+        }
+}
+
+        mcSHOW_DBG_MSG(("\n"));
+    }
+
+
+
+        /*
+            [Duty Calibration]
+            CLK Duty Final Delay Cell
+            [HQALOG] DUTY CLK_Final_Delay Channel0 0
+            [HQALOG] DUTY CLK_Final_Delay Channel1 -2
+        */
+#if !defined(RELEASE) && (VENDER_JV_LOG == 0)
+    if (u1IsLP4Family(p->dram_type) && (Get_Duty_Calibration_Mode(p) != DUTY_DEFAULT))
+    {
+        mcSHOW_DBG_MSG(("[duty Calibration]\n"));
+        mcSHOW_DBG_MSG(("CLK Duty Final Delay Cell\n"));
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+                     HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY CLK_Final_Delay Channel%d %d\n", u1ChannelIdx, gFinalClkDuty[u1ChannelIdx]));
+        }
+
+        /*
+            CLK Duty MAX
+            [HQALOG] DUTY CLK_MAX Channel0 4765%(X100)
+            [HQALOG] DUTY CLK_MAX Channel1 5212%(X100)
+        */
+        mcSHOW_DBG_MSG(("CLK Duty MAX\n"));
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+#ifdef FOR_HQA_REPORT_USED
+                if (gHQALog_flag == 1)
+                {
+                    HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT3, "DUTY CLK_", "MAX", 0, gFinalClkDutyMinMax[u1ChannelIdx][1], NULL);
+                }
+                else
+#endif
+                {
+                    HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY CLK_MAX Channel%d %d%%(X100)\n", u1ChannelIdx, gFinalClkDutyMinMax[u1ChannelIdx][1]));
+                }
+        }
+
+        /*
+            CLK Duty MIN
+            [HQALOG] DUTY CLK_MIN Channel0 4565%(X100)
+            [HQALOG] DUTY CLK_MIN Channel1 5012%(X100)
+        */
+        mcSHOW_DBG_MSG(("CLK Duty MIN\n"));
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+#ifdef FOR_HQA_REPORT_USED
+            if (gHQALog_flag == 1)
+            {
+                HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT3, "DUTY CLK_", "MIN", 0, gFinalClkDutyMinMax[u1ChannelIdx][0], NULL);
+                HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT3, "DUTY CLK_", "MAX-MIN", 0, gFinalClkDutyMinMax[u1ChannelIdx][1] - gFinalClkDutyMinMax[u1ChannelIdx][0], NULL);
+
+                if ((gFinalClkDutyMinMax[u1ChannelIdx][1] - gFinalClkDutyMinMax[u1ChannelIdx][0]) > 750)
+                {
+                    gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 3; //SLT_BIN3
+                }
+            }
+            else
+#endif
+            {
+                HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY CLK_MIN Channel%d %d%%(X100)\n", u1ChannelIdx, gFinalClkDutyMinMax[u1ChannelIdx][0]));
+            }
+        }
+
+        mcSHOW_DBG_MSG(("\n"));
+    }
+
+
+
+
+    /*
+        DQS Duty Final Delay Cell
+        [HQALOG] DUTY DQS_Final_Delay Channel0 DQS0 0
+        [HQALOG] DUTY DQS_Final_Delay Channel0 DQS1 1
+        [HQALOG] DUTY DQS_Final_Delay Channel1 DQS0 -2
+        [HQALOG] DUTY DQS_Final_Delay Channel1 DQS1 -1
+    */
+    if (u1IsLP4Family(p->dram_type) && (Get_Duty_Calibration_Mode(p) != DUTY_DEFAULT))
+    {
+        mcSHOW_DBG_MSG(("DQS Duty Final Delay Cell\n"));
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+            HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY DQS_Final_Delay Channel%d DQS0 %d\n", u1ChannelIdx, gFinalDQSDuty[u1ChannelIdx][0]));
+            HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY DQS_Final_Delay Channel%d DQS1 %d\n", u1ChannelIdx, gFinalDQSDuty[u1ChannelIdx][1]));
+        }
+
+        /*
+            DQS Duty MAX
+            [HQALOG] DUTY DQS_MAX Channel0 DQS0 4765%(X100)
+            [HQALOG] DUTY DQS_MAX Channel0 DQS1 5212%(X100)
+            [HQALOG] DUTY DQS_MAX Channel1 DQS0 4765%(X100)
+            [HQALOG] DUTY DQS_MAX Channel1 DQS1 5212%(X100)
+        */
+        mcSHOW_DBG_MSG(("DQS Duty MAX\n"));
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+#ifdef FOR_HQA_REPORT_USED
+                if (gHQALog_flag == 1)
+                {
+                    HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT0, "", "DUTY DQS_MAX", 0, gFinalDQSDutyMinMax[u1ChannelIdx][0][1], NULL);
+                    HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT0, "", "DUTY DQS_MAX", 1, gFinalDQSDutyMinMax[u1ChannelIdx][1][1], NULL);
+                }
+                else
+#endif
+                {
+                    HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY DQS_MAX Channel%d DQS0 %d%%(X100)\n", u1ChannelIdx, gFinalDQSDutyMinMax[u1ChannelIdx][0][1]));
+                    HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY DQS_MAX Channel%d DQS1 %d%%(X100)\n", u1ChannelIdx, gFinalDQSDutyMinMax[u1ChannelIdx][1][1]));
+                }
+        }
+
+        /*
+            DQS Duty MIN
+            [HQALOG] DUTY DQS_MIN Channel0 DQS0 4765%(X100)
+            [HQALOG] DUTY DQS_MIN Channel0 DQS1 5212%(X100)
+            [HQALOG] DUTY DQS_MIN Channel1 DQS0 4765%(X100)
+            [HQALOG] DUTY DQS_MIN Channel1 DQS1 5212%(X100)
+        */
+        mcSHOW_DBG_MSG(("DQS Duty MIN\n"));
+        for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++)
+        {
+#ifdef FOR_HQA_REPORT_USED
+            if (gHQALog_flag == 1)
+            {
+                HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT0, "DUTY DQS_", "MIN", 0, gFinalDQSDutyMinMax[u1ChannelIdx][0][0], NULL);
+                HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT0, "DUTY DQS_", "MIN", 1, gFinalDQSDutyMinMax[u1ChannelIdx][1][0], NULL);
+                HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT0, "DUTY DQS_", "MAX-MIN", 0, gFinalDQSDutyMinMax[u1ChannelIdx][0][1] - gFinalDQSDutyMinMax[u1ChannelIdx][0][0], NULL);
+                HQA_Log_Message_for_Report(p, u1ChannelIdx, 0, HQA_REPORT_FORMAT0, "DUTY DQS_", "MAX-MIN", 1, gFinalDQSDutyMinMax[u1ChannelIdx][1][1] - gFinalDQSDutyMinMax[u1ChannelIdx][1][0], NULL);
+
+                if (((gFinalDQSDutyMinMax[u1ChannelIdx][0][1] - gFinalDQSDutyMinMax[u1ChannelIdx][0][0]) > 750) || ((gFinalDQSDutyMinMax[u1ChannelIdx][1][1] - gFinalDQSDutyMinMax[u1ChannelIdx][1][0]) > 750))
+                {
+                    gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 3; //SLT_BIN3
+                }
+            }
+            else
+#endif
+            {
+                HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY DQS_MIN Channel%d DQS0 %d%%(X100)\n", u1ChannelIdx, gFinalDQSDutyMinMax[u1ChannelIdx][0][0]));
+                HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY DQS_MIN Channel%d DQS1 %d%%(X100)\n", u1ChannelIdx, gFinalDQSDutyMinMax[u1ChannelIdx][1][0]));
+            }
+        }
+
+        mcSHOW_DBG_MSG(("\n"));
+    }
+#endif
+
+
+    #if defined(ENABLE_MIOCK_JMETER) && !defined(RELEASE)
+            mcSHOW_DBG_MSG(("\n[DramcMiockJmeter]\n"
+                    "\t\t1 delay cell\t\t%d/100 ps\n", p->u2DelayCellTimex100));
+    #endif
+
+    mcSHOW_DBG_MSG(("\n\n\n"));
+
+
+
+#if VENDER_JV_LOG
+    mcSHOW_JV_LOG_MSG(("\n\n\n[Summary] information for measurement\n"));
+    //mcSHOW_JV_LOG_MSG(("\tDram Data rate = ")); HQA_LOG_Print_Freq_String(p); mcSHOW_DBG_MSG(("\n"));
+    vPrintCalibrationBasicInfo_ForJV(p);
+
+    if (u1IsLP4Family(p->dram_type))
+     {
+         mcSHOW_JV_LOG_MSG(("[Cmd Bus Training window]\n"));
+         //TO DO:jimmy
+         //mcSHOW_JV_LOG_MSG(("VrefCA Range : %d\n", gCBT_VREF_RANGE_SEL));
+#if CHANNEL_NUM == 4
+        mcSHOW_JV_LOG_MSG(("CHA_VrefCA_Rank0   CHB_VrefCA_Rank0   CHC_VrefCA_Rank0    CHD_VrefCA_Rank0\n"));
+        mcSHOW_JV_LOG_MSG(("%d                 %d                 %d                  %d\n", gFinalCBTVrefCA[0][0], gFinalCBTVrefCA[1][0], gFinalCBTVrefCA[2][0], gFinalCBTVrefCA[3][0]));
+#else
+         mcSHOW_JV_LOG_MSG(("CHA_VrefCA_Rank0   CHB_VrefCA_Rank0\n"));
+         mcSHOW_JV_LOG_MSG(("%d                 %d\n", gFinalCBTVrefCA[0][0], gFinalCBTVrefCA[1][0]));
+#endif
+         mcSHOW_JV_LOG_MSG(("CHA_CA_window_Rank0   CHB_CA_winow_Rank0\n"));
+         mcSHOW_JV_LOG_MSG(("%d%%(bit %d)              %d%%(bit %d) \n\n", (min_ca_value[0][0] * 100 + 63) / 64, min_ca_bit[0][0],
+                                                                     (min_ca_value[1][0] * 100 + 63) / 64, min_ca_bit[1][0]));
+     }
+     else
+     {
+         mcSHOW_JV_LOG_MSG(("[CA Training window]\n"));
+         mcSHOW_JV_LOG_MSG(("CHA_CA_win_Rank0\n"));
+         mcSHOW_JV_LOG_MSG(("%d%%(bit %d)\n\n", (min_ca_value[0][0] * 100 + 63) / 64, min_ca_bit[0][0]));
+     }
+
+     mcSHOW_JV_LOG_MSG(("[RX minimum per bit window]\n"));
+     if (Get_Vref_Calibration_OnOff(p) == VREF_CALI_ON)
+     {
+#if CHANNEL_NUM == 4
+        mcSHOW_JV_LOG_MSG(("CHA_VrefDQ    CHB_VrefDQ      CHC_VrefDQ      CHD_VrefDQ\n"));
+        mcSHOW_JV_LOG_MSG(("B0 %d            %d              %d              %d \n", gFinalRXVrefDQ[CHANNEL_A][RANK_0][0], gFinalRXVrefDQ[CHANNEL_B][RANK_0][0], gFinalRXVrefDQ[CHANNEL_C][RANK_0][0], gFinalRXVrefDQ[CHANNEL_D][RANK_0][0]));
+        mcSHOW_JV_LOG_MSG(("B1 %d            %d              %d              %d \n", gFinalRXVrefDQ[CHANNEL_A][RANK_0][1], gFinalRXVrefDQ[CHANNEL_B][RANK_0][1], gFinalRXVrefDQ[CHANNEL_C][RANK_0][1], gFinalRXVrefDQ[CHANNEL_D][RANK_0][1]));
+#else
+         mcSHOW_JV_LOG_MSG(("CHA_VrefDQ   CHB_VrefDQ\n"));
+         mcSHOW_JV_LOG_MSG(("B0 %d           %d \n", gFinalRXVrefDQ[CHANNEL_A][RANK_0][0], gFinalRXVrefDQ[CHANNEL_B][RANK_0][0]));
+         mcSHOW_JV_LOG_MSG(("B1 %d           %d \n", gFinalRXVrefDQ[CHANNEL_A][RANK_0][1], gFinalRXVrefDQ[CHANNEL_B][RANK_0][1]));
+#endif
+     }
+     else
+     {
+         mcSHOW_JV_LOG_MSG(("RX DQ Vref Scan : Disable\n"));
+
+     }
+
+    if (u1IsLP4Family(p->dram_type))
+    {
+#if CHANNEL_NUM == 4
+    mcSHOW_JV_LOG_MSG(("CHA_Rank0           CHA_Rank1           CHB_Rank0           CHB_Rank1         CHC_Rank0       CHC_Rank1       CHD_Rank0       CHD_Rank1\n"));
+    mcSHOW_JV_LOG_MSG(("%d%%(bit %d)         %d%%(bit %d)         %d%%(bit %d)         %d%%(bit %d)         %d%%(bit %d)         %d%%(bit %d)         %d%%(bit %d)         %d%%(bit %d)\n\n",
+                                    ((min_rx_value[0][0] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[0][0],
+                                    ((min_rx_value[0][1] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[0][1],
+                                    ((min_rx_value[1][0] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[1][0],
+                                    ((min_rx_value[1][1] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[1][1],
+                                    ((min_rx_value[2][0] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[2][0],
+                                    ((min_rx_value[2][1] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[2][1],
+                                    ((min_rx_value[3][0] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[3][0],
+                                    ((min_rx_value[3][1] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[3][1]));
+#else
+     mcSHOW_JV_LOG_MSG(("CHA_Rank0           CHA_Rank1           CHB_Rank0           CHB_Rank1\n"));
+     mcSHOW_JV_LOG_MSG(("%d%%(bit %d)         %d%%(bit %d)         %d%%(bit %d)         %d%%(bit %d)\n\n",
+                                     ((min_rx_value[0][0] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[0][0],
+                                     ((min_rx_value[0][1] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[0][1],
+                                     ((min_rx_value[1][0] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[1][0],
+                                     ((min_rx_value[1][1] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[1][1]));
+#endif
+    }
+#if ENABLE_LP3_SW
+    else
+    {
+        mcSHOW_JV_LOG_MSG(("CHA_Rank0           CHA_Rank1\n"));
+        mcSHOW_JV_LOG_MSG(("%d%%(bit %d)         %d%%(bit %d)\n\n",
+                                        ((min_rx_value[0][0] * u2gdelay_cell_ps_all[SRAMIdx] * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[0][0],
+                                        ((min_rx_value[0][1] * u2gdelay_cell_ps_all[SRAMIdx] * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000, min_RX_DQ_bit[0][1]));
+    }
+#endif
+
+     mcSHOW_JV_LOG_MSG(("[TX minimum per bit window]\n"));
+     if (Get_Vref_Calibration_OnOff(p) == VREF_CALI_ON)
+     {
+         mcSHOW_JV_LOG_MSG(("VrefDQ Range : %d\n", (u1MR14Value[p->channel][p->rank][p->dram_fsp] >> 6) & 1));
+#if CHANNEL_NUM == 4
+        mcSHOW_JV_LOG_MSG(("CHA_VrefDQ_Rank0   CHA_VrefDQ_Rank1    CHB_VrefDQ_Rank0    CHB_VrefDQ_Rank1   CHC_VrefDQ_Rank0    CHC_VrefDQ_Rank1    CHD_VrefDQ_Rank0    CHD_VrefDQ_Rank1\n"));
+        mcSHOW_JV_LOG_MSG(("%d                 %d                  %d                  %d                 %d                  %d                  %d                  %d\n"
+ , gFinalTXVrefDQ[0][0], gFinalTXVrefDQ[0][1], gFinalTXVrefDQ[1][0], gFinalTXVrefDQ[1][1]
+ , gFinalTXVrefDQ[2][0], gFinalTXVrefDQ[2][1], gFinalTXVrefDQ[3][0], gFinalTXVrefDQ[3][1]
+                    ));
+#else
+         mcSHOW_JV_LOG_MSG(("CHA_VrefDQ_Rank0   CHA_VrefDQ_Rank1    CHB_VrefDQ_Rank0    CHB_VrefDQ_Rank1\n"));
+         mcSHOW_JV_LOG_MSG(("%d                  %d                   %d                   %d\n", gFinalTXVrefDQ[0][0], gFinalTXVrefDQ[0][1], gFinalTXVrefDQ[1][0], gFinalTXVrefDQ[1][1]));
+#endif
+     }
+     else
+     {
+         mcSHOW_JV_LOG_MSG(("TX DQ Vref Scan : Disable\n"));
+     }
+
+    if (u1IsLP4Family(p->dram_type))
+    {
+#if CHANNEL_NUM == 4
+    mcSHOW_JV_LOG_MSG(("CHA_Rank0         CHA_Rank1           CHB_Rank0           CHB_Rank1       CHC_Rank0       CHC_Rank1       CHD_Rank0   CHD_Rank1\n"));
+    mcSHOW_JV_LOG_MSG(("%d%%               %d%%                 %d%%                 %d%%                 %d%%                 %d%%                 %d%%                 %d%%\n",
+                                        (min_tx_value[0][0] * 100 + 31) / 32,
+                                        (min_tx_value[0][1] * 100 + 31) / 32,
+                                        (min_tx_value[1][0] * 100 + 31) / 32,
+                                        (min_tx_value[1][1] * 100 + 31) / 32,
+                                        (min_tx_value[2][0] * 100 + 31) / 32,
+                                        (min_tx_value[2][1] * 100 + 31) / 32,
+                                        (min_tx_value[3][0] * 100 + 31) / 32,
+                                        (min_tx_value[3][1] * 100 + 31) / 32
+                                        ));
+#else
+     mcSHOW_JV_LOG_MSG(("CHA_Rank0           CHA_Rank1           CHB_Rank0           CHB_Rank1\n"));
+     mcSHOW_JV_LOG_MSG(("%d%%                %d%%                %d%%                %d%%\n",
+                                         (min_tx_value[0][0] * 100 + 31) / 32,
+                                         (min_tx_value[0][1] * 100 + 31) / 32,
+                                         (min_tx_value[1][0] * 100 + 31) / 32,
+                                         (min_tx_value[1][1] * 100 + 31) / 32));
+#endif
+    }
+    else
+    {
+     mcSHOW_JV_LOG_MSG(("CHA_Rank0           CHA_Rank1\n"));
+     mcSHOW_JV_LOG_MSG(("%d%%                %d%%\n",
+                                         (min_tx_value[0][0] * 100 + 31) / 32,
+                                         (min_tx_value[0][1] * 100 + 31) / 32));
+    }
+#endif
+
+
+    // reset all data
+    HQA_measure_message_reset_all_data(p);
+}
+#ifdef RELEASE
+#undef mcSHOW_DBG_MSG
+#define mcSHOW_DBG_MSG(_x_)
+#endif
+#endif
+
+
+#ifdef FOR_HQA_REPORT_USED
+static void print_EyeScanVcent_for_HQA_report_used(DRAMC_CTX_T *p, U8 print_type, U8 u1ChannelIdx, U8 u1RankIdx, U8 u1ByteIdx, U8 *EyeScanVcent, U8 EyeScanVcentUpperBound, U8 EyeScanVcentUpperBound_bit, U8 EyeScanVcentLowerBound, U8 EyeScanVcentLowerBound_bit)
+{
+    U8 uiCA, u1BitIdx;
+    U16 *pVref_Voltage_Table[VREF_VOLTAGE_TABLE_NUM_LP5] = {0};
+    U8  VrefRange;
+    U32 vddq = 0;
+    U8 local_channel_num = 2;
+    U8 SRAMIdx;
+    U8 u1CBTEyeScanEnable, u1RXEyeScanEnable, u1TXEyeScanEnable;
+    U16 Final_Vref_Vcent, VdlVWHigh_Upper_Vcent, VdlVWHigh_Lower_Vcent;
+    U32 Vcent_UpperBound_Window_percent = 0, Vcent_LowerBound_Window_percent = 0;
+    U32 Perbit_Window_percent, Perbit_BestWindow_percent, Perbit_Window_Upperbond_percent, Perbit_Window_Lowerbond_percent, Perbit_Eye_Height, Perbit_Eye_Area;
+    U8 u1BitIndex_Begin = 0, u1BitIndex_End = p->data_width;
+
+    if (gHQALog_flag == 0)
+    {
+    mcSHOW_DBG_MSG(("\n"));
+        return;
+    }
+
+    if (u1IsLP4Family(p->dram_type))
+    {
+        local_channel_num = p->support_channel_num;
+    }
+    else
+    {
+        //LP3
+        local_channel_num = 1;
+    }
+
+    u1CBTEyeScanEnable = GetEyeScanEnable(p, EYESCAN_TYPE_CBT);
+    u1RXEyeScanEnable = GetEyeScanEnable(p, EYESCAN_TYPE_RX);
+    u1TXEyeScanEnable = GetEyeScanEnable(p, EYESCAN_TYPE_TX);
+
+    SRAMIdx = vGet_Current_SRAMIdx(p);
+
+    if (print_type == EYESCAN_TYPE_RX)
+    {
+        if (p->odt_onoff==TRUE) //tern
+        {
+            if (p->dram_type==TYPE_LPDDR5)
+                pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_T;
+            else
+                pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P6V_T;
+        }
+        else //un-tern
+        {
+            if (p->dram_type==TYPE_LPDDR5)
+                pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_UT;
+            else
+                pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P6V_UT;
+        }
+
+        u1BitIndex_Begin = u1ByteIdx * DQS_BIT_NUMBER;
+        u1BitIndex_End = u1ByteIdx * DQS_BIT_NUMBER + DQS_BIT_NUMBER;
+    }
+    else
+    {
+        if (u1CBTEyeScanEnable || u1TXEyeScanEnable)
+        {
+            vddq = vGetVoltage(p, 2) / 1000; //mv
+
+            if (p->dram_type == TYPE_LPDDR4)
+            {
+                pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gVref_Voltage_Table_LP4[VREF_RANGE_0];
+                pVref_Voltage_Table[VREF_RANGE_1] = (U16 *)gVref_Voltage_Table_LP4[VREF_RANGE_1];
+            }
+            if (p->dram_type == TYPE_LPDDR4X)
+            {
+                pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gVref_Voltage_Table_LP4X[VREF_RANGE_0];
+                pVref_Voltage_Table[VREF_RANGE_1] = (U16 *)gVref_Voltage_Table_LP4X[VREF_RANGE_1];
+            }
+        }
+    }
+
+    if (print_type == EYESCAN_TYPE_CBT)
+    {
+        if (u1CBTEyeScanEnable)
+        {
+            VrefRange = (u1MR12Value[p->channel][p->rank][p->dram_fsp] >> 6) & 1;
+
+            Vcent_UpperBound_Window_percent = (EyeScanVcentUpperBound * 100 + (u1IsLP4Family(p->dram_type) == 1? 63: 31)) / (u1IsLP4Family(p->dram_type) == 1? 64: 32);
+            Vcent_LowerBound_Window_percent = (EyeScanVcentLowerBound * 100 + (u1IsLP4Family(p->dram_type) == 1? 63: 31)) / (u1IsLP4Family(p->dram_type) == 1? 64: 32);
+        }
+    }
+
+    if (print_type == EYESCAN_TYPE_RX)
+    {
+        if (u1RXEyeScanEnable)
+        {
+            Final_Vref_Vcent = pVref_Voltage_Table[0][EyeScanVcent[1]];
+            VdlVWHigh_Upper_Vcent = pVref_Voltage_Table[0][EyeScanVcent[3]];
+            VdlVWHigh_Lower_Vcent = pVref_Voltage_Table[0][EyeScanVcent[5]];
+
+            Vcent_UpperBound_Window_percent = ((EyeScanVcentUpperBound * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000;
+            Vcent_LowerBound_Window_percent = ((EyeScanVcentLowerBound * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000;
+        }
+    }
+
+    if (print_type == EYESCAN_TYPE_TX)
+    {
+        if (u1TXEyeScanEnable)
+        {
+            VrefRange = (u1MR14Value[p->channel][p->rank][p->dram_fsp] >> 6) & 1;
+
+            Final_Vref_Vcent = pVref_Voltage_Table[EyeScanVcent[0]][EyeScanVcent[1]] * vddq / 100;
+            VdlVWHigh_Upper_Vcent = pVref_Voltage_Table[EyeScanVcent[2]][EyeScanVcent[3]] * vddq / 100;
+            VdlVWHigh_Lower_Vcent = pVref_Voltage_Table[EyeScanVcent[4]][EyeScanVcent[5]] * vddq / 100;
+
+            Vcent_UpperBound_Window_percent = (EyeScanVcentUpperBound * 100 + (u1IsLP4Div4DDR800(p) == TRUE? 63: 31)) / (u1IsLP4Div4DDR800(p) == TRUE? 64: 32);
+            Vcent_LowerBound_Window_percent = (EyeScanVcentLowerBound * 100 + (u1IsLP4Div4DDR800(p) == TRUE? 63: 31)) / (u1IsLP4Div4DDR800(p) == TRUE? 64: 32);
+        }
+   }
+
+    mcSHOW_DBG_MSG(("\n\n\n[HQA] information for measurement, "));
+    mcSHOW_DBG_MSG(("\tDram Data rate = ")); HQA_LOG_Print_Freq_String(p); mcSHOW_DBG_MSG(("\n"));
+
+#if ENABLE_EYESCAN_GRAPH
+    mcSHOW_DBG_MSG(("%s Eye Scan Vcent Voltage\n", print_EYESCAN_LOG_type(print_type)));
+    if (print_type == EYESCAN_TYPE_RX)
+    {
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2_1, print_EYESCAN_LOG_type(print_type), "_Final_Vref Vcent", u1ByteIdx, pVref_Voltage_Table[0][EyeScanVcent[1]], NULL);
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2_1, print_EYESCAN_LOG_type(print_type), "_VdlVWHigh_Upper Vcent", u1ByteIdx, pVref_Voltage_Table[0][EyeScanVcent[3]], NULL);
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2_1, print_EYESCAN_LOG_type(print_type), "_VdlVWHigh_Lower Vcent", u1ByteIdx, pVref_Voltage_Table[0][EyeScanVcent[5]], NULL);
+    }
+    else
+    {
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_Final_Vref Vcent", 0, pVref_Voltage_Table[EyeScanVcent[0]][EyeScanVcent[1]] * vddq / 100, NULL);
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_VdlVWHigh_Upper Vcent", 0, pVref_Voltage_Table[EyeScanVcent[2]][EyeScanVcent[3]] * vddq / 100, NULL);
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_VdlVWHigh_Lower Vcent", 0, pVref_Voltage_Table[EyeScanVcent[4]][EyeScanVcent[5]] * vddq / 100, NULL);
+    }
+
+    mcSHOW_DBG_MSG(("\n"));
+#endif
+
+    mcSHOW_DBG_MSG(("%s Eye Scan Vcent_UpperBound window\n", print_EYESCAN_LOG_type(print_type)));
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_Vcent_UpperBound_Window", 0, EyeScanVcentUpperBound, NULL);
+    mcSHOW_DBG_MSG(("%s Eye Scan Vcent_UpperBound_Window worse bit\n", print_EYESCAN_LOG_type(print_type)));
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_Vcent_UpperBound_Window_bit", 0, EyeScanVcentUpperBound_bit, NULL);
+    mcSHOW_DBG_MSG(("%s Eye Scan Vcent_UpperBound Min Window(%%)\n", print_EYESCAN_LOG_type(print_type)));
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_Vcent_UpperBound_Window(%)", 0, Vcent_UpperBound_Window_percent, NULL);
+
+    mcSHOW_DBG_MSG(("\n"));
+
+    mcSHOW_DBG_MSG(("%s Eye Scan Vcent_LowerBound window\n", print_EYESCAN_LOG_type(print_type)));
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_Vcent_LowerBound_Window", 0, EyeScanVcentLowerBound, NULL);
+    mcSHOW_DBG_MSG(("%s Eye Scan Vcent_LowerBound_Window worse bit\n", print_EYESCAN_LOG_type(print_type)));
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_Vcent_LowerBound_Window_bit", 0, EyeScanVcentLowerBound_bit, NULL);
+    mcSHOW_DBG_MSG(("%s Eye Scan Vcent_UpperBound Min Window(%%)\n", print_EYESCAN_LOG_type(print_type)));
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, print_EYESCAN_LOG_type(print_type), "_Vcent_LowerBound_Window(%)", 0, Vcent_LowerBound_Window_percent, NULL);
+
+#if defined(FOR_HQA_REPORT_USED)
+    if (gHQALog_flag == 1)
+    {
+        if ((Vcent_UpperBound_Window_percent < 30) || (Vcent_LowerBound_Window_percent < 30))
+        {
+            gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 4; //SLT_BIN4
+        }
+    }
+#endif
+
+    if (print_type == EYESCAN_TYPE_RX || print_type == EYESCAN_TYPE_TX)
+    {
+        mcSHOW_DBG_MSG(("\n"));
+        mcSHOW_DBG_MSG(("%s Eye Scan per_bit window(%%)\n", print_EYESCAN_LOG_type(print_type)));
+        for (u1BitIdx = u1BitIndex_Begin; u1BitIdx < u1BitIndex_End; u1BitIdx++)
+        {
+#if ENABLE_EYESCAN_GRAPH
+            if (print_type == EYESCAN_TYPE_RX)
+            {
+                Perbit_Window_percent = ((gEyeScan_WinSize[EyeScanVcent[1] / EYESCAN_GRAPH_RX_VREF_STEP][u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000;
+                Perbit_BestWindow_percent = ((gEyeScan_WinSize[EyeScanVcent[10 + u1BitIdx] / EYESCAN_GRAPH_RX_VREF_STEP][u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000;
+                Perbit_Window_Upperbond_percent = ((gEyeScan_WinSize[EyeScanVcent[3] / EYESCAN_GRAPH_RX_VREF_STEP][u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000;
+                Perbit_Window_Lowerbond_percent = ((gEyeScan_WinSize[EyeScanVcent[5] / EYESCAN_GRAPH_RX_VREF_STEP][u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000;
+
+                Perbit_Eye_Height = (pVref_Voltage_Table[VREF_RANGE_0][((gEyeScan_ContinueVrefHeight[u1BitIdx] >> 8) & 0xff)] - pVref_Voltage_Table[VREF_RANGE_0][(gEyeScan_ContinueVrefHeight[u1BitIdx] & 0xff)]) / 100; //RX vref height last - first
+                Perbit_Eye_Area = gEyeScan_TotalPassCount[u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V * (((pVref_Voltage_Table[VREF_RANGE_0][((gEyeScan_ContinueVrefHeight[u1BitIdx] >> 8) & 0xff)] - pVref_Voltage_Table[VREF_RANGE_0][(gEyeScan_ContinueVrefHeight[u1BitIdx] & 0xff)])) / ((((gEyeScan_ContinueVrefHeight[u1BitIdx] >> 8) & 0xff) - (gEyeScan_ContinueVrefHeight[u1BitIdx] & 0xff)) * 10)) / 1000; //total count*jitter metter delay cell*(1/freq*10^6 ps)*(1330mv)
+            }
+            else //if (print_type==2)
+            {
+                Perbit_Window_percent = ((gEyeScan_WinSize[(EyeScanVcent[0] * 30 + EyeScanVcent[1]) / EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx]) * 100 + 31) / 32;
+                Perbit_BestWindow_percent = ((gEyeScan_WinSize[(EyeScanVcent[10 + u1BitIdx * 2] * 30 + EyeScanVcent[10 + u1BitIdx * 2 + 1]) / EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx]) * 100 + 31) / 32;
+                Perbit_Window_Upperbond_percent = ((gEyeScan_WinSize[(EyeScanVcent[2] * 30 + EyeScanVcent[3]) / EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx]) * 100 + 31) / 32;
+                Perbit_Window_Lowerbond_percent = ((gEyeScan_WinSize[(EyeScanVcent[4] * 30 + EyeScanVcent[5]) / EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx]) * 100 + 31) / 32;
+                Perbit_Eye_Height = (gEyeScan_ContinueVrefHeight[u1BitIdx] - 1) * 6 * vddq / 1000;
+                Perbit_Eye_Area = (gEyeScan_TotalPassCount[u1BitIdx] * 10 * 3 * vddq / (32 * DDRPhyGetRealFreq(p)))*100; //total count*1/32UI*(1/freq*10^6 ps)*(0.6%vddq)
+            }
+
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_1, print_EYESCAN_LOG_type(print_type), "_Perbit_Window(%)", u1BitIdx, Perbit_Window_percent, NULL);
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_1, print_EYESCAN_LOG_type(print_type), "_Perbit_BestWindow(%)", u1BitIdx, Perbit_BestWindow_percent, NULL);
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_1, print_EYESCAN_LOG_type(print_type), "_Perbit_Window_Upperbond(%)", u1BitIdx, Perbit_Window_Upperbond_percent, NULL);
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_1, print_EYESCAN_LOG_type(print_type), "_Perbit_Window_Lowerbond(%) ", u1BitIdx, Perbit_Window_Lowerbond_percent, NULL);
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_1, print_EYESCAN_LOG_type(print_type), "_Perbit_Eye_Height", u1BitIdx, Perbit_Eye_Height, NULL);
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_1, print_EYESCAN_LOG_type(print_type), "_Perbit_Eye_Area", u1BitIdx, Perbit_Eye_Area, NULL);
+#endif
+        }
+    }
+}
+
+void HQA_Log_Message_for_Report(DRAMC_CTX_T *p, U8 u1ChannelIdx, U8 u1RankIdx, U32 who_am_I, U8 *main_str, U8 *main_str2, U8 byte_bit_idx, S32 value1, U8 *ans_str)
+{
+    // HQA_REPORT_FORMAT0 : [HQALOG] 3200 Gating_Center_2T Channel0 Rank0 Byte0 3
+    // HQA_REPORT_FORMAT0_1:[HQALOG] 3200 Gating_Center_2T Channel0 Rank0 Bit0 3
+    // HQA_REPORT_FORMAT0_2:[HQALOG] 3200 Gating_Center_2T Channel0 Rank0 CA0 3
+    // HQA_REPORT_FORMAT1 : [HQALOG] 3200 WriteLeveling_DQS0 Channel0 Rank0 35
+    // HQA_REPORT_FORMAT2 : [HQALOG] 3200 TX_Final_Vref Vcent Channel0 Rank0 16860
+    // HQA_REPORT_FORMAT2_1:[HQALOG] 3200 RX_Final_Vref Vcent Channel0 Rank0 B0 16860
+    // HQA_REPORT_FORMAT3 : [HQALOG] 3200 DUTY CLK_MAX Channel0 5171
+    // HQA_REPORT_FORMAT4 : [HQALOG] 3200 TX_Vcent_LowerBound_Window_PF Channel0 Rank0 PASS
+    // HQA_REPORT_FORMAT5 : [HQALOG] 3200 AAAAAAAAAAAA BBBBB
+    // HQA_REPORT_FORMAT6 : [HQALOG] 3200 AAAAAAAAAAAA 0
+
+    if (gHQALog_flag == 1)
+    {
+        HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("%s%s", main_str, main_str2));
+        switch (who_am_I)
+        {
+            case HQA_REPORT_FORMAT1:
+                 mcSHOW_DBG_MSG(("%d", byte_bit_idx));
+                break;
+        }
+
+        if (who_am_I == HQA_REPORT_FORMAT3)
+        {
+            mcSHOW_DBG_MSG((" Channel%d ", u1ChannelIdx));
+        }
+        else if (who_am_I != HQA_REPORT_FORMAT5 && who_am_I != HQA_REPORT_FORMAT6)
+        {
+            mcSHOW_DBG_MSG((" Channel%d Rank%d ", u1ChannelIdx, u1RankIdx));
+        }
+
+        switch (who_am_I)
+        {
+            case HQA_REPORT_FORMAT2_1:
+            case HQA_REPORT_FORMAT0:
+                mcSHOW_DBG_MSG(("Byte%d %d\n", byte_bit_idx, value1));
+                break;
+            case HQA_REPORT_FORMAT0_1:
+                mcSHOW_DBG_MSG(("Bit%x %d\n", byte_bit_idx, value1));
+                break;
+            case HQA_REPORT_FORMAT0_2:
+                mcSHOW_DBG_MSG(("CA%x %d\n", byte_bit_idx, value1));
+                break;
+            case HQA_REPORT_FORMAT1:
+            case HQA_REPORT_FORMAT2:
+            case HQA_REPORT_FORMAT3:
+            case HQA_REPORT_FORMAT6:
+                mcSHOW_DBG_MSG(("%d\n", value1));
+                break;
+            case HQA_REPORT_FORMAT4:
+            case HQA_REPORT_FORMAT5:
+                mcSHOW_DBG_MSG((" %s\n", ans_str));
+                break;
+        }
+    }
+}
+
+#endif
+
+
+#ifdef RELEASE
+#undef mcSHOW_DBG_MSG
+#define mcSHOW_DBG_MSG(_x_) opt_print _x_
+#endif
+
+
+#if ENABLE_EYESCAN_GRAPH
+#define EyeScan_Pic_draw_line_Mirror 1
+#define EysScan_Pic_draw_1UI_line 1
+static void EyeScan_Pic_draw_line(DRAMC_CTX_T *p, U8 draw_type, U8 u1VrefRange, U8 u1VrefIdx, U8 u1BitIdx, S16 u2DQDelayBegin, S16 u2DQDelayEnd, U8 u1FinalVrefRange, U16 Final_Vref_val, U8 VdlVWHigh_Upper_Vcent_Range, U32 VdlVWHigh_Upper_Vcent, U8 VdlVWHigh_Lower_Vcent_Range, U32 VdlVWHigh_Lower_Vcent, U16 FinalDQCaliDelay, S16 EyeScan_DelayCellPI_value, U16 delay_cell_ps, U16 Max_EyeScan_Min_val)
+{
+    int i;
+    int local_VrefIdx, local_Upper_Vcent, local_Lower_Vcent, local_Final_VrefIdx;
+    S8 EyeScan_Index = 0;
+    S16 EyeScan_Min_val, EyeScan_Max_val, Final_EyeScan_Min_val = EYESCAN_DATA_INVALID, Final_EyeScan_Max_val = EYESCAN_DATA_INVALID, Final_EyeScan_winsize = 1;
+    U16 *pVref_Voltage_Table[VREF_VOLTAGE_TABLE_NUM_LP5];
+    U16 PI_of_1_UI;
+    U16 u2DQDelayStep=1, u2VrefStep=1;
+    U16 pass_region_h_value=3;
+
+    if (draw_type == EYESCAN_TYPE_RX)
+    {
+        u2DQDelayStep=4;
+        u2VrefStep=EYESCAN_GRAPH_RX_VREF_STEP;
+        if (p->odt_onoff==TRUE) //tern
+        {
+            if (p->dram_type==TYPE_LPDDR5)
+                pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_T;
+            else
+                pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P6V_T;
+        }
+        else //un-tern
+        {
+            if (p->dram_type==TYPE_LPDDR5)
+                pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_UT;
+            else
+                pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P6V_UT;
+        }
+
+        if (p->u2DelayCellTimex100 != 0)
+        {
+            PI_of_1_UI = (50000000 / (DDRPhyGetRealFreq(p)* p->u2DelayCellTimex100));
+
+            FinalDQCaliDelay = (U16)EyeScan_DelayCellPI_value;
+            EyeScan_DelayCellPI_value = 0;
+
+            //pass region = 20%UI, = +-10$UI, 1UI=1/freq*10^6, 10%UI=((1/freq*10^6)/10)/delay cell
+            pass_region_h_value = PI_of_1_UI/10;
+
+            delay_cell_ps = p->u2DelayCellTimex100;
+        }
+        else
+        {
+            PI_of_1_UI = 0;
+            //mcSHOW_ERR_MSG(("DelayCell is 0\n"));
+        }
+    }
+    else
+    {
+        u2VrefStep = EYESCAN_GRAPH_CATX_VREF_STEP;
+
+        //pass region = 20%UI, = +- 10%UI, 1UI=32PI, 10%UI=3PI
+        pass_region_h_value = 3;
+
+        if (p->dram_type == TYPE_LPDDR4)
+        {
+            pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gVref_Voltage_Table_LP4[VREF_RANGE_0];
+            pVref_Voltage_Table[VREF_RANGE_1] = (U16 *)gVref_Voltage_Table_LP4[VREF_RANGE_1];
+        }
+        else if (p->dram_type == TYPE_LPDDR4X)
+        {
+            pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gVref_Voltage_Table_LP4X[VREF_RANGE_0];
+            pVref_Voltage_Table[VREF_RANGE_1] = (U16 *)gVref_Voltage_Table_LP4X[VREF_RANGE_1];
+        }
+        else if (p->dram_type == TYPE_LPDDR5)
+        {
+            pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gVref_Voltage_Table_LP5;
+        }
+
+        PI_of_1_UI = 32;
+    }
+
+    if (u1VrefRange == 1 && u1VrefIdx <= 20)
+    {
+        u1VrefRange = 0;
+        u1VrefIdx += 30;
+    }
+    if (u1FinalVrefRange == 1 && Final_Vref_val <= 20)
+    {
+        u1FinalVrefRange = 0;
+        Final_Vref_val += 30;
+    }
+    if (u1VrefRange != u1FinalVrefRange)
+    {
+        Final_Vref_val = 0xff;
+    }
+
+    local_Upper_Vcent = VdlVWHigh_Upper_Vcent_Range * VREF_VOLTAGE_TABLE_NUM_LP4+ VdlVWHigh_Upper_Vcent;
+    local_Lower_Vcent = VdlVWHigh_Lower_Vcent_Range * VREF_VOLTAGE_TABLE_NUM_LP4+ VdlVWHigh_Lower_Vcent;
+    local_VrefIdx = u1VrefRange * VREF_VOLTAGE_TABLE_NUM_LP4+ u1VrefIdx;
+    local_Final_VrefIdx = u1FinalVrefRange * VREF_VOLTAGE_TABLE_NUM_LP4+ Final_Vref_val;
+
+    if (VdlVWHigh_Upper_Vcent_Range == VREF_RANGE_1 && VdlVWHigh_Upper_Vcent <= 20) local_Upper_Vcent = VdlVWHigh_Upper_Vcent_Range * VREF_VOLTAGE_TABLE_NUM_LP4+ VdlVWHigh_Upper_Vcent - 20;
+    if (VdlVWHigh_Lower_Vcent_Range == VREF_RANGE_1 && VdlVWHigh_Lower_Vcent <= 20) local_Lower_Vcent = VdlVWHigh_Lower_Vcent_Range * VREF_VOLTAGE_TABLE_NUM_LP4+ VdlVWHigh_Lower_Vcent - 20;
+
+    mcSHOW_EYESCAN_MSG(("Vref-"));
+
+    if (draw_type == EYESCAN_TYPE_RX && pVref_Voltage_Table[u1VrefRange][u1VrefIdx] <10000)
+    {
+        mcSHOW_EYESCAN_MSG((" "));
+    }
+
+    mcSHOW_EYESCAN_MSG(("%d.%d%d", pVref_Voltage_Table[u1VrefRange][u1VrefIdx] / 100, ((pVref_Voltage_Table[u1VrefRange][u1VrefIdx] % 100) / 10), pVref_Voltage_Table[u1VrefRange][u1VrefIdx] % 10));
+    if (draw_type == EYESCAN_TYPE_RX)
+    {
+        mcSHOW_EYESCAN_MSG(("m|"));
+    }
+    else
+    {
+        mcSHOW_EYESCAN_MSG(("%%|"));
+    }
+
+
+
+
+
+#if VENDER_JV_LOG || defined(RELEASE)
+#if EyeScan_Pic_draw_line_Mirror
+    EyeScan_DelayCellPI_value = 0 - EyeScan_DelayCellPI_value;
+#endif
+#endif
+
+#if EyeScan_Pic_draw_line_Mirror
+    EyeScan_Index = EYESCAN_BROKEN_NUM - 1;
+    EyeScan_Min_val = gEyeScan_Min[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
+    EyeScan_Max_val = gEyeScan_Max[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
+
+    while (EyeScan_Min_val == EYESCAN_DATA_INVALID && EyeScan_Index > 0)
+    {
+        EyeScan_Index--;
+        EyeScan_Min_val = gEyeScan_Min[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
+        EyeScan_Max_val = gEyeScan_Max[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
+    }
+#else
+    EyeScan_Index = 0;
+    EyeScan_Min_val = gEyeScan_Min[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
+    EyeScan_Max_val = gEyeScan_Max[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
+#endif
+
+    if (draw_type == EYESCAN_TYPE_TX)
+    {
+        EyeScan_Min_val += gEyeScan_MinMax_store_delay[u1BitIdx / 8];
+        EyeScan_Max_val += gEyeScan_MinMax_store_delay[u1BitIdx / 8];
+    }
+
+    if ((EyeScan_Max_val - EyeScan_Min_val + 1) > Final_EyeScan_winsize)
+    {
+#if EyeScan_Pic_draw_line_Mirror
+        Final_EyeScan_Max_val = EyeScan_Max_val;
+        Final_EyeScan_Min_val = EyeScan_Min_val;
+#else
+        Final_EyeScan_Max_val = EyeScan_Max_val;
+        Final_EyeScan_Min_val = EyeScan_Min_val;
+#endif
+        Final_EyeScan_winsize = (EyeScan_Max_val - EyeScan_Min_val + 1);
+    }
+
+#if VENDER_JV_LOG || defined(RELEASE)
+#if EyeScan_Pic_draw_line_Mirror
+    for (i = (Max_EyeScan_Min_val + PI_of_1_UI + EyeScan_DelayCellPI_value) * delay_cell_ps / 100; i > (Max_EyeScan_Min_val - PI_of_1_UI + EyeScan_DelayCellPI_value) * delay_cell_ps / 100; i -= 10)
+#else
+    for (i = (Max_EyeScan_Min_val - PI_of_1_UI + EyeScan_DelayCellPI_value) * delay_cell_ps / 100; i < (Max_EyeScan_Min_val + PI_of_1_UI + EyeScan_DelayCellPI_value) * delay_cell_ps / 100; i += 10)
+#endif
+#else
+#if EyeScan_Pic_draw_line_Mirror
+    for (i = u2DQDelayEnd; i >= u2DQDelayBegin; i-=u2DQDelayStep)
+#else
+    for (i = u2DQDelayBegin; i <= u2DQDelayEnd; i+=u2DQDelayStep)
+#endif
+#endif
+    {
+
+#if VENDER_JV_LOG || defined(RELEASE)
+#if EyeScan_Pic_draw_line_Mirror
+        if (i <= ((EyeScan_Min_val + EyeScan_DelayCellPI_value) * delay_cell_ps / 100) && EyeScan_Index != 0)
+        {
+            EyeScan_Index--;
+            EyeScan_Min_val = gEyeScan_Min[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
+            EyeScan_Max_val = gEyeScan_Max[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
+
+            if (draw_type == EYESCAN_TYPE_TX)
+            {
+                EyeScan_Min_val += gEyeScan_MinMax_store_delay[u1BitIdx / 8];
+                EyeScan_Max_val += gEyeScan_MinMax_store_delay[u1BitIdx / 8];
+            }
+
+            if ((EyeScan_Max_val - EyeScan_Min_val + 1) > Final_EyeScan_winsize)
+            {
+                Final_EyeScan_Max_val = EyeScan_Max_val;
+                Final_EyeScan_Min_val = EyeScan_Min_val;
+                Final_EyeScan_winsize = (EyeScan_Max_val - EyeScan_Min_val + 1);
+            }
+
+        }
+#endif
+#else
+#if EyeScan_Pic_draw_line_Mirror
+        if (i == (EyeScan_Min_val) && EyeScan_Index != 0)
+        {
+            EyeScan_Index--;
+            EyeScan_Min_val = gEyeScan_Min[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
+            EyeScan_Max_val = gEyeScan_Max[(u1VrefIdx + u1VrefRange * 30) / u2VrefStep][u1BitIdx][EyeScan_Index];
+
+            if (draw_type == EYESCAN_TYPE_TX)
+            {
+                EyeScan_Min_val += gEyeScan_MinMax_store_delay[u1BitIdx / 8];
+                EyeScan_Max_val += gEyeScan_MinMax_store_delay[u1BitIdx / 8];
+            }
+
+            if ((EyeScan_Max_val - EyeScan_Min_val + 1) > Final_EyeScan_winsize)
+            {
+                Final_EyeScan_Max_val = EyeScan_Max_val;
+                Final_EyeScan_Min_val = EyeScan_Min_val;
+                Final_EyeScan_winsize = (EyeScan_Max_val - EyeScan_Min_val + 1);
+            }
+
+        }
+#endif
+#endif
+
+#if VENDER_JV_LOG || defined(RELEASE)
+        if (i >= ((EyeScan_Min_val + EyeScan_DelayCellPI_value) * delay_cell_ps / 100) && i <= ((EyeScan_Max_val + EyeScan_DelayCellPI_value) * delay_cell_ps / 100))
+#else
+        if (i >= (EyeScan_Min_val) && i <= (EyeScan_Max_val))
+#endif
+        {
+#if !VENDER_JV_LOG && !defined(RELEASE)
+            if ((i>=(FinalDQCaliDelay+EyeScan_DelayCellPI_value-(u2DQDelayStep/2)))&&(i<=(FinalDQCaliDelay+EyeScan_DelayCellPI_value+(u2DQDelayStep/2)))) //Final DQ delay
+            {
+                if (gEye_Scan_color_flag)
+                {
+                    mcSHOW_EYESCAN_MSG(("\033[0;105mH\033[m"));
+                }
+                else
+                {
+                    mcSHOW_EYESCAN_MSG(("H"));
+                }
+            }
+            else
+            if ((local_VrefIdx >= local_Final_VrefIdx-(u2VrefStep/2))&&(local_VrefIdx <= local_Final_VrefIdx+(u2VrefStep/2))) //Final Vref
+            {
+                if (gEye_Scan_color_flag)
+                {
+                    mcSHOW_EYESCAN_MSG(("\033[0;105mV\033[m"));
+                }
+                else
+                {
+                    mcSHOW_EYESCAN_MSG(("V"));
+                }
+            }
+            else //spec in margin
+            if (local_VrefIdx <= local_Upper_Vcent && local_VrefIdx >= local_Lower_Vcent && i >= (FinalDQCaliDelay + EyeScan_DelayCellPI_value - pass_region_h_value) && i <= (FinalDQCaliDelay + EyeScan_DelayCellPI_value + pass_region_h_value))
+            {
+                if (gEye_Scan_color_flag)
+                {
+                    mcSHOW_EYESCAN_MSG(("\033[0;103mQ\033[m"));
+                }
+                else
+                {
+                    mcSHOW_EYESCAN_MSG(("Q"));
+                }
+            }
+            else //pass margin
+#endif
+            {
+#if VENDER_JV_LOG || defined(RELEASE)
+                if (gEye_Scan_color_flag)
+                {
+                    mcSHOW_EYESCAN_MSG(("\033[0;102mO\033[m"));
+                }
+                else
+                {
+                    mcSHOW_EYESCAN_MSG(("O"));
+                }
+#else
+                if (gEye_Scan_color_flag)
+                {
+                    mcSHOW_EYESCAN_MSG(("\033[0;102mO\033[m"));
+                }
+                else
+                {
+                    mcSHOW_EYESCAN_MSG(("O"));
+                }
+#endif
+            }
+        }
+        else
+        {
+#if !VENDER_JV_LOG && !defined(RELEASE)
+#if EysScan_Pic_draw_1UI_line
+            if (i == (int)(Max_EyeScan_Min_val) || i == (int)(Max_EyeScan_Min_val + PI_of_1_UI))
+            {
+                if (gEye_Scan_color_flag)
+                {
+                    if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1 && p->dram_fsp == FSP_0 && draw_type==0 && u1VrefIdx < EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF)
+                    {
+                        mcSHOW_EYESCAN_MSG(("\033[0;107m \033[m"));
+                    }
+                    else
+                    {
+                        mcSHOW_EYESCAN_MSG(("\033[0;107m.\033[m"));
+                    }
+                }
+                else
+                {
+                    if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1 && p->dram_fsp == FSP_0 && draw_type==0 && u1VrefIdx < EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF)
+                    {
+                        mcSHOW_EYESCAN_MSG((" "));
+                    }
+                    else
+                    {
+                        mcSHOW_EYESCAN_MSG(("."));
+                    }
+                }
+            }
+            else
+#endif
+#endif
+            {
+                //not valid
+#if VENDER_JV_LOG || defined(RELEASE)
+                if (gEye_Scan_color_flag)
+                {
+                    if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1 && p->dram_fsp == FSP_0 && draw_type==0 && u1VrefIdx < EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF)
+                    {
+                        mcSHOW_EYESCAN_MSG(("\033[0;100m \033[m"));
+                    }
+                    else
+                    {
+                        mcSHOW_EYESCAN_MSG(("\033[0;100m.\033[m"));
+                    }
+                }
+                else
+                {
+                    if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1 && p->dram_fsp == FSP_0 && draw_type==0 && u1VrefIdx < EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF)
+                    {
+                        mcSHOW_EYESCAN_MSG((" "));
+                    }
+                    else
+                    {
+                        mcSHOW_EYESCAN_MSG(("."));
+                    }
+                }
+#else
+                if (gEye_Scan_color_flag)
+                {
+                    if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1 && p->dram_fsp == FSP_0 && draw_type==0 && u1VrefIdx < EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF)
+                    {
+                        mcSHOW_EYESCAN_MSG(("\033[0;100m \033[m"));
+                    }
+                    else
+                    {
+                        mcSHOW_EYESCAN_MSG(("\033[0;100m.\033[m"));
+                    }
+                }
+                else
+                {
+                    if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1 && p->dram_fsp == FSP_0 && draw_type==0 && u1VrefIdx < EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF)
+                    {
+                        mcSHOW_EYESCAN_MSG((" "));
+                    }
+                    else
+                    {
+                        mcSHOW_EYESCAN_MSG(("."));
+                    }
+                }
+#endif
+
+            }
+        }
+    }
+
+
+#if EyeScan_Pic_draw_line_Mirror
+    if (Final_EyeScan_Min_val != EYESCAN_DATA_INVALID && Final_EyeScan_Max_val != EYESCAN_DATA_INVALID)
+    {
+#if !VENDER_JV_LOG && !defined(RELEASE)
+        if (Final_EyeScan_Max_val > (FinalDQCaliDelay + EyeScan_DelayCellPI_value) && (FinalDQCaliDelay + EyeScan_DelayCellPI_value) > Final_EyeScan_Min_val)
+        {
+            mcSHOW_EYESCAN_MSG((" -%d ", (Final_EyeScan_Max_val - (FinalDQCaliDelay + EyeScan_DelayCellPI_value))));
+            mcSHOW_EYESCAN_MSG(("%d ", ((FinalDQCaliDelay + EyeScan_DelayCellPI_value) - Final_EyeScan_Min_val)));
+        }
+        else if (Final_EyeScan_Max_val > (FinalDQCaliDelay + EyeScan_DelayCellPI_value) && Final_EyeScan_Min_val > (FinalDQCaliDelay + EyeScan_DelayCellPI_value))
+        {
+            mcSHOW_EYESCAN_MSG((" -%d ", (Final_EyeScan_Max_val - Final_EyeScan_Min_val)));
+            mcSHOW_EYESCAN_MSG((" --- "));
+        }
+        else if ((FinalDQCaliDelay + EyeScan_DelayCellPI_value) > Final_EyeScan_Max_val && (FinalDQCaliDelay + EyeScan_DelayCellPI_value) > Final_EyeScan_Min_val)
+        {
+            mcSHOW_EYESCAN_MSG((" --- "));
+            mcSHOW_EYESCAN_MSG(("%d ", (Final_EyeScan_Max_val - Final_EyeScan_Min_val)));
+        }
+        else
+        {
+            mcSHOW_EYESCAN_MSG((" --- "));
+            mcSHOW_EYESCAN_MSG((" --- "));
+        }
+#endif
+        //window
+#if VENDER_JV_LOG || defined(RELEASE)
+        mcSHOW_EYESCAN_MSG(("%dps", Final_EyeScan_winsize * delay_cell_ps / 100));
+#else
+        mcSHOW_EYESCAN_MSG(("%d", Final_EyeScan_winsize));
+#endif
+    }
+#else
+    if (Final_EyeScan_Max_val != Final_EyeScan_Min_val && Final_EyeScan_Max_val != EYESCAN_DATA_INVALID)
+    {
+#if !VENDER_JV_LOG && !defined(RELEASE)
+        if (Final_EyeScan_Max_val > (FinalDQCaliDelay + EyeScan_DelayCellPI_value) && (FinalDQCaliDelay + EyeScan_DelayCellPI_value) > Final_EyeScan_Min_val)
+        {
+            mcSHOW_EYESCAN_MSG((" -%d ", ((FinalDQCaliDelay + EyeScan_DelayCellPI_value) - Final_EyeScan_Min_val)));
+            mcSHOW_EYESCAN_MSG(("%d ", (Final_EyeScan_Max_val - (FinalDQCaliDelay + EyeScan_DelayCellPI_value))));
+        }
+        else if (Final_EyeScan_Max_val > (FinalDQCaliDelay + EyeScan_DelayCellPI_value) && Final_EyeScan_Min_val > (FinalDQCaliDelay + EyeScan_DelayCellPI_value))
+        {
+            mcSHOW_EYESCAN_MSG((" --- "));
+            mcSHOW_EYESCAN_MSG(("%d ", (Final_EyeScan_Max_val - Final_EyeScan_Min_val)));
+        }
+        else if ((FinalDQCaliDelay + EyeScan_DelayCellPI_value) > Final_EyeScan_Max_val && (FinalDQCaliDelay + EyeScan_DelayCellPI_value) > Final_EyeScan_Min_val)
+        {
+            mcSHOW_EYESCAN_MSG((" -%d ", (Final_EyeScan_Max_val - Final_EyeScan_Min_val)));
+            mcSHOW_EYESCAN_MSG((" --- "));
+        }
+        else
+        {
+            mcSHOW_EYESCAN_MSG((" --- "));
+            mcSHOW_EYESCAN_MSG((" --- "));
+        }
+#endif
+        //window
+#if VENDER_JV_LOG || defined(RELEASE)
+        mcSHOW_EYESCAN_MSG(("%dps", Final_EyeScan_winsize * delay_cell_ps / 100));
+#else
+        mcSHOW_EYESCAN_MSG(("%d", Final_EyeScan_winsize));
+#endif
+    }
+#endif
+
+    mcSHOW_EYESCAN_MSG(("\n"));
+
+
+}
+
+void print_EYESCAN_LOG_message(DRAMC_CTX_T *p, U8 print_type)
+{
+    U32 u1ChannelIdx = p->channel, u1RankIdx = p->rank;
+    S8 u1VrefIdx;
+    U8 u1VrefRange;
+    U8 u1BitIdx, u1CA;
+    U32 VdlVWTotal, VdlVWLow, VdlVWHigh, Vcent_DQ;
+    U32 VdlVWHigh_Upper_Vcent = VREF_VOLTAGE_TABLE_NUM_LP4- 1, VdlVWHigh_Lower_Vcent = 0, VdlVWBest_Vcent = 0;
+    U32 VdlVWHigh_Upper_Vcent_Range = 1, VdlVWHigh_Lower_Vcent_Range = 0, VdlVWBest_Vcent_Range = 1; ;
+    U8 Upper_Vcent_pass_flag = 0, Lower_Vcent_pass_flag = 0;
+    S32 i, vrefrange_i;
+    U8 local_channel_num = 2;
+    U8 SRAMIdx;
+    U8 TXVrefRange = 0, CBTVrefRange = 0;
+    U16 finalVref = 0, finalVrefRange = 0;
+    S32 scan_vref_number = 0;
+    U32 vddq;
+    U8 Min_Value_1UI_Line;
+    S8 EyeScan_Index;
+    U8 cal_length = 0;
+    U16 *pVref_Voltage_Table[VREF_VOLTAGE_TABLE_NUM_LP5];
+    S16 EyeScan_DelayCellPI_value;
+    U8 EyeScanVcent[10 + DQ_DATA_WIDTH * 2], max_winsize;
+    U8 minEyeScanVcentUpperBound = 0xff, minEyeScanVcentUpperBound_bit = 0;
+    U8 minEyeScanVcentLowerBound = 0xff, minEyeScanVcentLowerBound_bit = 0;
+    U16 one_pi_ps = 100000000 / (DDRPhyGetRealFreq(p)* 2 * 32);
+    U8 u1CBTEyeScanEnable, u1RXEyeScanEnable, u1TXEyeScanEnable;
+
+    U32 u2DQDelayEnd=0, u2TX_DQ_PreCal_LP4_Samll;
+    S32 u2DQDelayBegin=0;
+
+    U8 u1ByteIdx, u1ByteIdx_Begin = 0, u1ByteIdx_End = 0;
+
+    U16 u2VrefStep=1;
+
+    local_channel_num = p->support_channel_num;
+
+     if (print_type == EYESCAN_TYPE_RX)
+    {
+        u2VrefStep = EYESCAN_GRAPH_RX_VREF_STEP;
+
+        if (p->odt_onoff==TRUE) //tern
+        {
+            if (p->dram_type==TYPE_LPDDR5)
+                pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_T;
+            else
+                pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P6V_T;
+        }
+    else //un-tern
+    {
+         if (p->dram_type==TYPE_LPDDR5)
+                pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_UT;
+            else
+                pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P6V_UT;
+    }
+    }
+    else
+    {
+        u2VrefStep = EYESCAN_GRAPH_CATX_VREF_STEP;
+
+        if (p->dram_type == TYPE_LPDDR4)
+        {
+            pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gVref_Voltage_Table_LP4[VREF_RANGE_0];
+            pVref_Voltage_Table[VREF_RANGE_1] = (U16 *)gVref_Voltage_Table_LP4[VREF_RANGE_1];
+        }
+        if (p->dram_type == TYPE_LPDDR4X)
+        {
+            pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gVref_Voltage_Table_LP4X[VREF_RANGE_0];
+            pVref_Voltage_Table[VREF_RANGE_1] = (U16 *)gVref_Voltage_Table_LP4X[VREF_RANGE_1];
+        }
+        if (p->dram_type == TYPE_LPDDR5)
+        {
+            pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gVref_Voltage_Table_LP5;
+        }
+    }
+
+    u1CBTEyeScanEnable = GetEyeScanEnable(p, EYESCAN_TYPE_CBT);
+    u1RXEyeScanEnable =  GetEyeScanEnable(p, EYESCAN_TYPE_RX);
+    u1TXEyeScanEnable =  GetEyeScanEnable(p, EYESCAN_TYPE_TX);
+
+#if 0 //fra test
+    u1CBTEyeScanEnable = u1CBTEyeScanEnable & (p->channel == 0 && p->rank == 0);
+#endif
+
+/**************************************************************************************
+    CBT/RX/TX EYESCAN log
+***************************************************************************************/
+    if (print_type == EYESCAN_TYPE_CBT)
+    {
+        if (p->frequency <= 934) VdlVWTotal = 17500; //VcIVW 175mv
+        else if (p->frequency <= 1600) VdlVWTotal = 15500; //VcIVW 155mv
+        else VdlVWTotal = 14500; //VcIVW 145mv
+    }
+    else
+    {
+#if 0
+        if (p->frequency <= 1600) VdlVWTotal = 10000; //14000; //140mv
+        else VdlVWTotal = 10000; //12000; //120mv
+#else
+        VdlVWTotal = 10000;
+#endif
+    }
+
+    if (p->dram_type!=TYPE_LPDDR5)//LP5 no range
+    {
+        CBTVrefRange = (u1MR12Value[p->channel][p->rank][p->dram_fsp] >> 6) & 1;
+        TXVrefRange = (u1MR14Value[p->channel][p->rank][p->dram_fsp] >> 6) & 1;
+    }
+
+    if (print_type == EYESCAN_TYPE_RX)
+    {
+        u1ByteIdx_Begin = 0;
+        u1ByteIdx_End = 1;
+    }
+
+for (u1ByteIdx = u1ByteIdx_Begin; u1ByteIdx <= u1ByteIdx_End; u1ByteIdx++)
+{
+
+#if 1 //#if !VENDER_JV_LOG && !defined(RELEASE)
+    if ((print_type == EYESCAN_TYPE_CBT && u1CBTEyeScanEnable) || (print_type == EYESCAN_TYPE_RX && u1RXEyeScanEnable) || (print_type == EYESCAN_TYPE_TX && u1TXEyeScanEnable))
+    {
+        vddq = vGetVoltage(p, 2) / 1000; //mv
+        EYESCAN_LOG_Print_Prefix_String(); mcSHOW_DBG_MSG(("VDDQ=%dmV\n", vddq));
+
+        if (print_type == EYESCAN_TYPE_CBT)
+        {
+            if (p->dram_type==TYPE_LPDDR5)
+            {
+                finalVref = u1MR12Value[u1ChannelIdx][u1RankIdx][p->dram_fsp];
+            }
+            else
+            {
+                finalVrefRange = u1MR12Value[u1ChannelIdx][u1RankIdx][p->dram_fsp]>>6;
+                finalVref = u1MR12Value[u1ChannelIdx][u1RankIdx][p->dram_fsp]&0x3f;
+            }
+            cal_length = CATRAINING_NUM_LP4;
+        }
+        else if (print_type == EYESCAN_TYPE_RX)
+        {
+            finalVrefRange = 0;
+            finalVref = gFinalRXVrefDQ[u1ChannelIdx][u1RankIdx][u1ByteIdx];
+
+            cal_length = DQS_BIT_NUMBER; //p->data_width;
+        }
+        else//if (print_type==2)
+        {
+            if (p->dram_type==TYPE_LPDDR5)
+            {
+                finalVref = u1MR14Value[u1ChannelIdx][u1RankIdx][p->dram_fsp];
+            }
+            else
+            {
+                finalVrefRange = u1MR14Value[u1ChannelIdx][u1RankIdx][p->dram_fsp]>>6;
+                finalVref = u1MR14Value[u1ChannelIdx][u1RankIdx][p->dram_fsp]&0x3f;
+            }
+
+            cal_length = p->data_width;
+        }
+
+
+        EYESCAN_LOG_Print_Prefix_String(); mcSHOW_DBG_MSG(("%s Window\n", print_EYESCAN_LOG_type(print_type)));
+
+        EYESCAN_LOG_Print_Prefix_String(); mcSHOW_DBG_MSG(("%s Channel%d ", print_EYESCAN_LOG_type(print_type), u1ChannelIdx));
+        if (print_type == EYESCAN_TYPE_RX)
+        {
+            mcSHOW_DBG_MSG(("Final_Vref Byte%d Vcent %d(%dmV(X100))\n",
+                                                    u1ByteIdx,
+                                                    finalVref,
+                                                    pVref_Voltage_Table[finalVrefRange][finalVref]));
+
+            Vcent_DQ = pVref_Voltage_Table[finalVrefRange][finalVref];
+        }
+        else
+        {
+            mcSHOW_DBG_MSG(("Range %d Final_Vref Vcent=%d(%dmV(X100))\n",
+                                                finalVrefRange,
+                                                finalVref,
+                                                pVref_Voltage_Table[finalVrefRange][finalVref] * vddq / 100));
+
+            Vcent_DQ = pVref_Voltage_Table[finalVrefRange][finalVref] * vddq / 100;
+        }
+
+
+        //find VdlVWHigh first
+        if (print_type == EYESCAN_TYPE_RX)
+        {
+            VdlVWHigh_Upper_Vcent_Range = 0;
+            VdlVWHigh_Upper_Vcent = RX_VREF_RANGE_END-1;
+            vrefrange_i = 0;
+            scan_vref_number = RX_VREF_RANGE_END;
+        }
+        else
+        {
+            if (p->dram_type==TYPE_LPDDR5)
+            {
+                VdlVWHigh_Upper_Vcent_Range = 0;
+                VdlVWHigh_Upper_Vcent = VREF_VOLTAGE_TABLE_NUM_LP5-1;
+                vrefrange_i = 0;
+                scan_vref_number = VREF_VOLTAGE_TABLE_NUM_LP5;
+            }
+            else
+            {
+                VdlVWHigh_Upper_Vcent_Range = 1;
+                VdlVWHigh_Upper_Vcent = VREF_VOLTAGE_TABLE_NUM_LP4-1;
+                vrefrange_i = finalVrefRange;
+                scan_vref_number = VREF_VOLTAGE_TABLE_NUM_LP4;
+            }
+        }
+        for (i = finalVref; i < scan_vref_number; i += u2VrefStep)
+        {
+            if (print_type == EYESCAN_TYPE_RX||(print_type != EYESCAN_TYPE_RX&&p->dram_type==TYPE_LPDDR5))
+            {
+                if (pVref_Voltage_Table[vrefrange_i][i] - Vcent_DQ >= VdlVWTotal / 2)
+                {
+                    /* find VdlVWHigh upper bound */
+                    VdlVWHigh_Upper_Vcent = i;
+                    break;
+                }
+            }
+            else
+            {
+                if (((pVref_Voltage_Table[vrefrange_i][i] * vddq / 100 - Vcent_DQ)) >= VdlVWTotal / 2)
+                {
+                    /* find VdlVWHigh upper bound */
+                    VdlVWHigh_Upper_Vcent = i;
+                    VdlVWHigh_Upper_Vcent_Range = vrefrange_i;
+                    break;
+                }
+                if (i == (VREF_VOLTAGE_TABLE_NUM_LP4- 1) && vrefrange_i == 0)
+                {
+                    vrefrange_i = 1;
+                    i = 20;
+                }
+            }
+        }
+
+        EYESCAN_LOG_Print_Prefix_String(); mcSHOW_DBG_MSG(("%s VdlVWHigh_Upper ", print_EYESCAN_LOG_type(print_type)));
+        if (print_type != EYESCAN_TYPE_RX)
+        {
+            mcSHOW_DBG_MSG(("Range=%d ", VdlVWHigh_Upper_Vcent_Range));
+            mcSHOW_DBG_MSG(("Vcent=%d(%dmV(X100))\n",
+                VdlVWHigh_Upper_Vcent,
+                pVref_Voltage_Table[VdlVWHigh_Upper_Vcent_Range][VdlVWHigh_Upper_Vcent] * vddq / 100));
+        }
+        else
+        {
+            mcSHOW_DBG_MSG(("Byte%d ", u1ByteIdx));
+            mcSHOW_DBG_MSG(("Vcent=%d(%dmV(X100))\n",
+                VdlVWHigh_Upper_Vcent,
+                pVref_Voltage_Table[VdlVWHigh_Upper_Vcent_Range][VdlVWHigh_Upper_Vcent]));
+        }
+
+
+        //find VldVWLow first
+        VdlVWHigh_Lower_Vcent_Range = 0;
+        VdlVWHigh_Lower_Vcent = 0;
+        vrefrange_i = finalVrefRange;
+        for (i = (finalVref); i >= 0; i -= u2VrefStep)
+        {
+            if (print_type == EYESCAN_TYPE_RX||(print_type != EYESCAN_TYPE_RX&&p->dram_type==TYPE_LPDDR5))
+            {
+                if (Vcent_DQ - pVref_Voltage_Table[vrefrange_i][i] >= VdlVWTotal / 2)
+                {
+                    /* find VdlVWHigh lower bound */
+                    VdlVWHigh_Lower_Vcent = i;
+                    break;
+                }
+            }
+            else
+            {
+                if (((Vcent_DQ - pVref_Voltage_Table[vrefrange_i][i] * vddq / 100)) >= VdlVWTotal / 2)
+                {
+                    /* find VdlVWHigh lower bound */
+                    VdlVWHigh_Lower_Vcent = i;
+                    VdlVWHigh_Lower_Vcent_Range = vrefrange_i;
+                    break;
+                }
+                if (i <= 21 && vrefrange_i == 1)
+                {
+                    vrefrange_i = 0;
+                    i = VREF_VOLTAGE_TABLE_NUM_LP4- (21 - i);
+                }
+            }
+        }
+
+        EYESCAN_LOG_Print_Prefix_String(); mcSHOW_DBG_MSG(("%s VdlVWHigh_Lower ", print_EYESCAN_LOG_type(print_type)));
+        if (print_type != EYESCAN_TYPE_RX)
+        {
+            mcSHOW_DBG_MSG(("Range=%d ", VdlVWHigh_Lower_Vcent_Range));
+            mcSHOW_DBG_MSG(("Vcent=%d(%dmV(X100))\n",
+                VdlVWHigh_Lower_Vcent,
+                pVref_Voltage_Table[VdlVWHigh_Lower_Vcent_Range][VdlVWHigh_Lower_Vcent] * vddq / 100));
+        }
+        else
+        {
+            mcSHOW_DBG_MSG(("Byte%d ", u1ByteIdx));
+            mcSHOW_DBG_MSG(("Vcent=%d(%dmV(X100))\n",
+                VdlVWHigh_Lower_Vcent,
+                pVref_Voltage_Table[VdlVWHigh_Lower_Vcent_Range][VdlVWHigh_Lower_Vcent]));
+        }
+
+
+#ifdef FOR_HQA_TEST_USED
+            EyeScanVcent[0] = finalVrefRange;
+            EyeScanVcent[1] = finalVref;
+            EyeScanVcent[2] = VdlVWHigh_Upper_Vcent_Range;
+            EyeScanVcent[3] = VdlVWHigh_Upper_Vcent;
+            EyeScanVcent[4] = VdlVWHigh_Lower_Vcent_Range;
+            EyeScanVcent[5] = VdlVWHigh_Lower_Vcent;
+#endif
+
+        SRAMIdx = vGet_Current_SRAMIdx(p);
+
+#ifdef FOR_HQA_REPORT_USED
+        if (print_type == EYESCAN_TYPE_RX)
+        {
+            EYESCAN_LOG_Print_Prefix_String(); mcSHOW_DBG_MSG(("delay cell %d/100ps\n", gHQALOG_RX_delay_cell_ps_075V));
+        }
+#endif
+
+//            EYESCAN_LOG_Print_Prefix_String(); mcSHOW_DBG_MSG(("delay cell %d/100ps\n", u2gdelay_cell_ps_all[SRAMIdx][u1ChannelIdx]));
+
+        for (u1BitIdx = u1ByteIdx * DQS_BIT_NUMBER; u1BitIdx < (u1ByteIdx * DQS_BIT_NUMBER + cal_length); u1BitIdx++)
+        {
+            if (print_type != EYESCAN_TYPE_RX)
+            {
+                // compare Upper/Lower Vcent pass criterion is pass or fail?
+                for (u1VrefIdx = finalVref + finalVrefRange * 30; u1VrefIdx <= (S8)(VdlVWHigh_Upper_Vcent + VdlVWHigh_Upper_Vcent_Range * 30); u1VrefIdx += u2VrefStep)
+                {
+                    Upper_Vcent_pass_flag = 0;
+                    for (EyeScan_Index = 0; EyeScan_Index < EYESCAN_BROKEN_NUM; EyeScan_Index++)
+                    {
+                        if (gEyeScan_Min[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] != EYESCAN_DATA_INVALID && gEyeScan_Max[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] != EYESCAN_DATA_INVALID)
+                        if ((print_type == EYESCAN_TYPE_CBT && ((((gEyeScan_CaliDelay[0] + gEyeScan_DelayCellPI[u1BitIdx]) - gEyeScan_Min[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index]) >= 3) && ((gEyeScan_Max[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] - (gEyeScan_CaliDelay[0] + gEyeScan_DelayCellPI[u1BitIdx])) >= 3))) ||
+                            (print_type == EYESCAN_TYPE_TX && ((((gEyeScan_CaliDelay[u1BitIdx / 8] + gEyeScan_DelayCellPI[u1BitIdx]) - (gEyeScan_Min[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] + gEyeScan_MinMax_store_delay[u1BitIdx / 8])) >= 3) && (((gEyeScan_Max[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] + gEyeScan_MinMax_store_delay[u1BitIdx / 8]) - (gEyeScan_CaliDelay[u1BitIdx / 8] + gEyeScan_DelayCellPI[u1BitIdx])) >= 3 ))))
+                        {
+                            Upper_Vcent_pass_flag = 1;
+                        }
+                    }
+                    if (Upper_Vcent_pass_flag == 0) break; // fail!!
+                }
+                for (u1VrefIdx = VdlVWHigh_Lower_Vcent + VdlVWHigh_Lower_Vcent_Range * 30; u1VrefIdx <= (S8)(finalVref + finalVrefRange * 30); u1VrefIdx += u2VrefStep)
+                {
+                    Lower_Vcent_pass_flag = 0;
+                    for (EyeScan_Index = 0; EyeScan_Index < EYESCAN_BROKEN_NUM; EyeScan_Index++)
+                    {
+                        if (gEyeScan_Min[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] != EYESCAN_DATA_INVALID && gEyeScan_Max[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] != EYESCAN_DATA_INVALID)
+                        if ((print_type == EYESCAN_TYPE_CBT && ((((gEyeScan_CaliDelay[0] + gEyeScan_DelayCellPI[u1BitIdx]) - gEyeScan_Min[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index]) >= 3) && ((gEyeScan_Max[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] - (gEyeScan_CaliDelay[0] + gEyeScan_DelayCellPI[u1BitIdx])) >= 3))) ||
+                             (print_type == EYESCAN_TYPE_TX && ((((gEyeScan_CaliDelay[u1BitIdx / 8] + gEyeScan_DelayCellPI[u1BitIdx]) - (gEyeScan_Min[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] + gEyeScan_MinMax_store_delay[u1BitIdx / 8])) >= 3) && (((gEyeScan_Max[u1VrefIdx / u2VrefStep][u1BitIdx][EyeScan_Index] + gEyeScan_MinMax_store_delay[u1BitIdx / 8]) - (gEyeScan_CaliDelay[u1BitIdx / 8] + gEyeScan_DelayCellPI[u1BitIdx])) >= 3 ))))
+                        {
+                            Lower_Vcent_pass_flag = 1;
+                        }
+                    }
+                    if (Lower_Vcent_pass_flag == 0) break; //fail!!
+                }
+            }
+
+#ifdef FOR_HQA_TEST_USED
+            //find VdlVWBest Vref Range and Vref
+            VdlVWBest_Vcent_Range = 1;
+            VdlVWBest_Vcent = VREF_VOLTAGE_TABLE_NUM_LP4- 1;
+            if (print_type == EYESCAN_TYPE_RX||(print_type != EYESCAN_TYPE_RX&&p->dram_type==TYPE_LPDDR5)) vrefrange_i = 0;
+            else vrefrange_i = 1;
+            max_winsize = 0;
+            for (i = ((scan_vref_number-1) - ((scan_vref_number-1)%u2VrefStep)); i >= 0; i -= u2VrefStep)
+            {
+                if (gEyeScan_WinSize[(i + vrefrange_i * 30) / u2VrefStep][u1BitIdx] > max_winsize)
+                {
+                    max_winsize = gEyeScan_WinSize[(i + vrefrange_i * 30) / u2VrefStep][u1BitIdx];
+                    VdlVWBest_Vcent_Range = vrefrange_i;
+                    VdlVWBest_Vcent = i;
+                }
+                if (print_type != EYESCAN_TYPE_RX && i == 21 && vrefrange_i == 1)
+                {
+                    vrefrange_i = 0;
+                    i = VREF_VOLTAGE_TABLE_NUM_LP4;
+                }
+            }
+
+            if (print_type == EYESCAN_TYPE_RX)
+            {
+                EyeScanVcent[10 + u1BitIdx] = VdlVWBest_Vcent;
+            }
+            else
+            {
+                EyeScanVcent[10 + u1BitIdx * 2] = VdlVWBest_Vcent_Range;
+                EyeScanVcent[10 + u1BitIdx * 2 + 1] = VdlVWBest_Vcent;
+            }
+#endif
+
+            if (print_type == EYESCAN_TYPE_RX)
+            {
+#ifdef FOR_HQA_REPORT_USED
+                EYESCAN_LOG_Print_Prefix_String(); HQA_LOG_Print_Freq_String(p); mcSHOW_DBG_MSG(("Channel%d Rank%d Bit%d(DRAM DQ%d)\tHigher VdlTW=%d/100ps\tLower VdlTW=%d/100ps\n",
+                    u1ChannelIdx,
+                    u1RankIdx,
+                    u1BitIdx,
+                    uiLPDDR4_O1_Mapping_POP[p->channel][u1BitIdx],
+                    gEyeScan_WinSize[VdlVWHigh_Upper_Vcent / u2VrefStep][u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V,
+                    gEyeScan_WinSize[VdlVWHigh_Lower_Vcent / u2VrefStep][u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V
+                    ));
+#endif
+            }
+            else
+            {
+                EYESCAN_LOG_Print_Prefix_String(); HQA_LOG_Print_Freq_String(p); mcSHOW_DBG_MSG(("Channel%d Rank%d %s%d",
+                    u1ChannelIdx,
+                    u1RankIdx,
+                    print_type == EYESCAN_TYPE_CBT? "CA" : "Bit",
+                    u1BitIdx
+                    ));
+                    if (print_type == EYESCAN_TYPE_TX)
+                    {
+                        mcSHOW_DBG_MSG(("(DRAM DQ%d)", uiLPDDR4_O1_Mapping_POP[p->channel][u1BitIdx]));
+                    }
+                mcSHOW_DBG_MSG(("\tHigher VdlTW=%dPI(%d/100ps)(%s)\tLower VdlTW=%dpi(%d/100ps)(%s)\n",
+                    gEyeScan_WinSize[(VdlVWHigh_Upper_Vcent + VdlVWHigh_Upper_Vcent_Range * 30) / u2VrefStep][u1BitIdx],
+                    gEyeScan_WinSize[(VdlVWHigh_Upper_Vcent + VdlVWHigh_Upper_Vcent_Range * 30) / u2VrefStep][u1BitIdx] * one_pi_ps,
+                    Upper_Vcent_pass_flag == 1? "PASS" : "WARNING",
+                    gEyeScan_WinSize[(VdlVWHigh_Lower_Vcent + VdlVWHigh_Lower_Vcent_Range * 30) / u2VrefStep][u1BitIdx],
+                    gEyeScan_WinSize[(VdlVWHigh_Lower_Vcent + VdlVWHigh_Lower_Vcent_Range * 30) / u2VrefStep][u1BitIdx] * one_pi_ps,
+                    Lower_Vcent_pass_flag == 1? "PASS" : "WARNING"
+                    ));
+            }
+
+            if (gEyeScan_WinSize[(VdlVWHigh_Upper_Vcent + VdlVWHigh_Upper_Vcent_Range * 30) / u2VrefStep][u1BitIdx] < minEyeScanVcentUpperBound)
+            {
+                minEyeScanVcentUpperBound = gEyeScan_WinSize[(VdlVWHigh_Upper_Vcent + VdlVWHigh_Upper_Vcent_Range * 30) / u2VrefStep][u1BitIdx];
+                minEyeScanVcentUpperBound_bit = u1BitIdx;
+            }
+            if (gEyeScan_WinSize[(VdlVWHigh_Lower_Vcent + VdlVWHigh_Lower_Vcent_Range * 30) / u2VrefStep][u1BitIdx] < minEyeScanVcentLowerBound)
+            {
+                minEyeScanVcentLowerBound = gEyeScan_WinSize[(VdlVWHigh_Lower_Vcent + VdlVWHigh_Lower_Vcent_Range * 30) / u2VrefStep][u1BitIdx];
+                minEyeScanVcentLowerBound_bit = u1BitIdx;
+            }
+        }
+#ifdef FOR_HQA_TEST_USED
+#ifdef FOR_HQA_REPORT_USED
+        print_EyeScanVcent_for_HQA_report_used(p, print_type, u1ChannelIdx, u1RankIdx, u1ByteIdx, EyeScanVcent, minEyeScanVcentUpperBound, minEyeScanVcentUpperBound_bit, minEyeScanVcentLowerBound, minEyeScanVcentLowerBound_bit);
+#endif
+#endif
+    }
+
+
+#endif
+
+
+    if ((print_type == EYESCAN_TYPE_CBT && u1CBTEyeScanEnable) || (print_type == EYESCAN_TYPE_RX && u1RXEyeScanEnable) || (print_type == EYESCAN_TYPE_TX && u1TXEyeScanEnable))
+    {   U8 space_num;
+
+        mcSHOW_DBG_MSG(("\n\n"));
+
+        if (print_type == EYESCAN_TYPE_CBT )
+        {
+            u2DQDelayBegin = 0;
+            u2DQDelayEnd = 64+20;
+
+            space_num = 8 + one_pi_ps * 32 / 1000;
+        }
+        else if (print_type == EYESCAN_TYPE_RX)
+        {
+            u2DQDelayBegin = gEyeScan_Min[(finalVref) / EYESCAN_GRAPH_RX_VREF_STEP][0][0]-32;
+            u2DQDelayEnd = gEyeScan_Max[(finalVref) / EYESCAN_GRAPH_RX_VREF_STEP][0][0]+32;
+
+            space_num = 8 + one_pi_ps * 32 / 1000;
+        }
+        else// if (print_type==2)
+        {
+            if (gEyeScan_CaliDelay[0] < gEyeScan_CaliDelay[1])
+                u2DQDelayBegin = gEyeScan_CaliDelay[0] - 24;
+            else
+                u2DQDelayBegin = gEyeScan_CaliDelay[1] - 24;
+
+            u2DQDelayEnd = u2DQDelayBegin + 64;
+
+            space_num = 15 + u2DQDelayEnd - u2DQDelayBegin + 2;
+        }
+
+        for (u1BitIdx = u1ByteIdx * DQS_BIT_NUMBER; u1BitIdx < (u1ByteIdx * DQS_BIT_NUMBER + cal_length); u1BitIdx++)
+        {
+            EyeScan_Index = 0;
+
+            if (print_type == EYESCAN_TYPE_RX)
+            {
+                Min_Value_1UI_Line = gEyeScan_DelayCellPI[u1BitIdx] - 16;
+
+                EYESCAN_LOG_Print_Prefix_String(); mcSHOW_EYESCAN_MSG(("RX EYESCAN Channel%d, Rank%d, DQ%d ===\n", p->channel, p->rank, u1BitIdx));
+            }
+            else
+            {
+#if EyeScan_Pic_draw_line_Mirror
+                EyeScan_DelayCellPI_value = 0 - gEyeScan_DelayCellPI[u1BitIdx];
+#else
+                EyeScan_DelayCellPI_value = gEyeScan_DelayCellPI[u1BitIdx];
+#endif
+                Min_Value_1UI_Line = gEyeScan_CaliDelay[u1BitIdx / 8] - 16 - EyeScan_DelayCellPI_value;
+
+                EYESCAN_LOG_Print_Prefix_String(); mcSHOW_EYESCAN_MSG(("%s EYESCAN Channel%d, Rank%d, Bit%d", print_type==EYESCAN_TYPE_CBT ? "CBT" : "TX DQ", p->channel, p->rank, u1BitIdx));
+                if (print_type == EYESCAN_TYPE_TX)
+                {
+                    mcSHOW_EYESCAN_MSG(("(DRAM DQ%d)", uiLPDDR4_O1_Mapping_POP[p->channel][u1BitIdx]));
+                }
+                mcSHOW_EYESCAN_MSG((" ===\n"));
+            }
+
+
+#if VENDER_JV_LOG
+            for (i = 0; i < 8 + one_pi_ps * 32 / 1000; i++) mcSHOW_EYESCAN_MSG((" "));
+            mcSHOW_EYESCAN_MSG(("window\n"));
+#else
+            for (i = 0; i < space_num; i++) mcSHOW_EYESCAN_MSG((" "));
+            mcSHOW_EYESCAN_MSG(("first last window\n"));
+            mcSHOW_EYESCAN_MSG(("Vref Step: %d, Delay Step: %d\n",u2VrefStep, (print_type==EYESCAN_TYPE_RX)?4:1));
+
+#endif
+
+                if (print_type == EYESCAN_TYPE_RX||(print_type != EYESCAN_TYPE_RX&&p->dram_type==TYPE_LPDDR5)) u1VrefRange = VREF_RANGE_0;
+                else u1VrefRange = VREF_RANGE_1;
+
+                for (u1VrefIdx = ((scan_vref_number-1) - ((scan_vref_number-1)%u2VrefStep)); u1VrefIdx >= 0; u1VrefIdx -= u2VrefStep)
+                {
+                        EyeScan_Pic_draw_line(p, print_type, u1VrefRange, u1VrefIdx, u1BitIdx, u2DQDelayBegin, u2DQDelayEnd, finalVrefRange, finalVref, VdlVWHigh_Upper_Vcent_Range, VdlVWHigh_Upper_Vcent, VdlVWHigh_Lower_Vcent_Range, VdlVWHigh_Lower_Vcent, gEyeScan_CaliDelay[u1BitIdx / 8], gEyeScan_DelayCellPI[u1BitIdx], one_pi_ps, Min_Value_1UI_Line);
+
+                        if (print_type != EYESCAN_TYPE_RX && u1VrefRange == VREF_RANGE_1 && u1VrefIdx == 20)
+                        {
+                            u1VrefRange = VREF_RANGE_0;
+                            u1VrefIdx = VREF_VOLTAGE_TABLE_NUM_LP4-1;
+                        }
+                }
+
+            mcSHOW_EYESCAN_MSG(("\n\n"));
+
+        }
+    }
+}
+}
+
+
+#ifdef RELEASE
+#undef mcSHOW_DBG_MSG
+#define mcSHOW_DBG_MSG(_x_)
+#endif
+#endif
+
+#if PIN_CHECK_TOOL
+#define CA_THRESHOLD 20
+#define RX_THRESHOLD 150
+#define TX_THRESHOLD 20
+#define PERCENTAGE_THRESHOLD 50
+#define PRINT_WIN_SIZE 0
+DEBUG_PIN_INF_FOR_FLASHTOOL_T PINInfo_flashtool;
+static U8* print_Impedence_LOG_type(U8 print_type)
+{
+    switch (print_type)
+    {
+        case 0: return "DRVP";
+        case 1: return "DRVN";
+        case 2: return "ODTP";
+        case 3: return "ODTN";
+        default: return "ERROR";
+    }
+}
+void vPrintPinInfoResult(DRAMC_CTX_T *p)
+{
+    U8 u1CHIdx, u1RankIdx, u1CAIdx, u1ByteIdx, u1ByteIdx_DQ, u1BitIdx, u1BitIdx_DQ, u1FreqRegionIdx, u1ImpIdx;
+    U8 u1PinError=0;
+
+    mcSHOW_DBG_MSG3(("\n\n[Pin Info Summary] Freqency %d\n", p->frequency));
+
+    for (u1FreqRegionIdx=0;u1FreqRegionIdx<2/*IMP_VREF_MAX*/;u1FreqRegionIdx++)
+    {
+        for (u1ImpIdx=0;u1ImpIdx<IMP_DRV_MAX;u1ImpIdx++)
+        {
+            mcSHOW_DBG_MSG3(("IMP %s type:%s %s\n", u1FreqRegionIdx?"Region1":"Region0", print_Impedence_LOG_type(u1ImpIdx), ((PINInfo_flashtool.IMP_ERR_FLAG>>(u1FreqRegionIdx*4+u1ImpIdx)&0x1)?"ERROR":"PASS")));
+        }
+    }
+
+    //for(ucFreqIdx=SRAM_SHU0; ucFreqIdx<DRAM_DFS_SRAM_MAX; ucFreqIdx++)
+    {
+        //mcSHOW_DBG_MSG(("==Freqency = %d==\n", get_FreqTbl_by_SRAMIndex(p,ucFreqIdx)->frequency));
+        for(u1CHIdx=0; u1CHIdx<p->support_channel_num; u1CHIdx++)
+        {
+            for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++)
+            {
+                mcSHOW_DBG_MSG3(("CH %d, Rank %d\n", u1CHIdx, u1RankIdx));
+
+                //CA pin check
+                for (u1CAIdx =0; u1CAIdx <CATRAINING_NUM_LP4; u1CAIdx++)
+                {
+                    #if 1//Transfer to Percentage
+                    PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]= (PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]* 100 + 63) /64;
+                    if ((PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]==0)||(PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]<=PERCENTAGE_THRESHOLD))
+                    #else
+                    if ((PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]==0)||(PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]<=CA_THRESHOLD))
+                    #endif
+                    {
+                        PINInfo_flashtool.CA_ERR_FLAG[u1CHIdx][u1RankIdx] |= (1<<u1CAIdx);
+                        PINInfo_flashtool.TOTAL_ERR |= (0x1<<(u1CHIdx*4+u1RankIdx*2));
+                    }
+                    mcSHOW_DBG_MSG3(("CA %d: %s ", u1CAIdx, ((PINInfo_flashtool.CA_ERR_FLAG[u1CHIdx][u1RankIdx]>>u1CAIdx)&0x1)?"ERROR":"PASS"));
+                    #if PRINT_WIN_SIZE
+                    mcSHOW_DBG_MSG3(("(WIN_SIZE: %d %% )", (PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx])));
+                    #endif
+                    mcSHOW_DBG_MSG3(("\n"));
+
+                }
+
+                //DQ pin check
+                for (u1BitIdx =0; u1BitIdx <DQ_DATA_WIDTH; u1BitIdx++)
+                {
+                    u1ByteIdx = (u1BitIdx>=8?1:0);
+                    u1BitIdx_DQ = uiLPDDR4_O1_Mapping_POP[p->channel][u1BitIdx];
+                    u1ByteIdx_DQ = (u1BitIdx_DQ>=8?1:0);
+
+                //RX
+                #if 1//Transfer to Percentage
+                    PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx] = ((PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]* gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p)* 2)+ (1000000 - 1)) / 1000000;
+                    if (PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=PERCENTAGE_THRESHOLD)
+                #else
+                    if ((PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]==0)||(PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=RX_THRESHOLD)\
+                         ||(PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]==0)||(PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=TX_THRESHOLD))
+                #endif
+                    {
+                        PINInfo_flashtool.DQ_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] |= (1<<(u1BitIdx-(u1ByteIdx==1?8:0)));
+                        PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx_DQ] |= (1<<(u1BitIdx_DQ-(u1ByteIdx_DQ==1?8:0)));
+                        PINInfo_flashtool.TOTAL_ERR |= (0x1<<(u1CHIdx*4+u1RankIdx*2+1));
+                    }
+
+                //TX
+                #if 1//Transfer to Percentage
+                    PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx] = (PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]* 100+ (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 63: 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 64: 32);
+                    if (PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=PERCENTAGE_THRESHOLD)
+                #else
+                    if ((PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]==0)||(PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=RX_THRESHOLD)\
+                         ||(PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]==0)||(PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=TX_THRESHOLD))
+                #endif
+                    {
+                        PINInfo_flashtool.DQ_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] |= (1<<(u1BitIdx-(u1ByteIdx==1?8:0)));
+                        PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx_DQ] |= (1<<(u1BitIdx_DQ-(u1ByteIdx_DQ==1?8:0)));
+                        PINInfo_flashtool.TOTAL_ERR |= (0x1<<(u1CHIdx*4+u1RankIdx*2+1));
+                    }
+
+                    //mcSHOW_DBG_MSG(("bit %d(DRAM DQ %d): %s ", u1BitIdx, uiLPDDR4_O1_Mapping_POP[p->channel][u1BitIdx], ((PINInfo_flashtool.DQ_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]>>u1BitIdx)&0x1)?"ERROR":"PASS"));
+                    //mcSHOW_DBG_MSG(("(RX WIN SIZE: %d, TX WIN SIZE: %d)", PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx], PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]));
+                    //mcSHOW_DBG_MSG(("\n"));
+                }
+                for (u1BitIdx_DQ=0; u1BitIdx_DQ<DQ_DATA_WIDTH; u1BitIdx_DQ++)
+                {
+                    u1ByteIdx_DQ = (u1BitIdx_DQ>=8?1:0);
+                    mcSHOW_DBG_MSG3(("DRAM DQ %d: RX %s, TX %s ", u1BitIdx_DQ, (((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx_DQ]>>(u1BitIdx_DQ-(u1ByteIdx_DQ==1?8:0)))&0x1)?"ERROR":"PASS"),\
+                                                                                                                        (((PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx_DQ]>>(u1BitIdx_DQ-(u1ByteIdx_DQ==1?8:0)))&0x1)?"ERROR":"PASS")));
+                    #if PRINT_WIN_SIZE
+                    mcSHOW_DBG_MSG3(("(RX WIN SIZE: %d %%, TX WIN SIZE: %d %% )", PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][uiLPDDR4_O1_Mapping_POP[u1CHIdx][u1BitIdx_DQ]], PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][uiLPDDR4_O1_Mapping_POP[u1CHIdx][u1BitIdx_DQ]]));
+                    #endif
+                    mcSHOW_DBG_MSG3(("\n"));
+                }
+            }
+        }
+    }
+}
+
+void vGetErrorTypeResult(DRAMC_CTX_T *p)
+{
+    U8 u1CHIdx, u1CHIdx_EMI, u1RankIdx, u1CAIdx, u1ByteIdx, u1BitIdx, u1FreqRegionIdx, u1ImpIdx;
+
+    //pErrorTypeInfo = "ERROR TYPE TEST";
+    mcSHOW_DBG_MSG3(("\n[Get Pin Error Type Result]\n"));
+
+
+    if (PINInfo_flashtool.TOTAL_ERR==0 && PINInfo_flashtool.IMP_ERR_FLAG==0)//ALL PASS
+    {
+        mcSHOW_DBG_MSG3(("ALL PASS\n"));
+    }
+
+    //TYPE 1: Impedance calibration fail
+    if (PINInfo_flashtool.IMP_ERR_FLAG)
+    {
+        mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: Impedance calibration fail\n"));
+        mcSHOW_DBG_MSG3(("Suspect EXTR contact issue\n"));
+        mcSHOW_DBG_MSG3(("Suspect EXTR related resistor contact issue\n"));
+    }
+
+    //TYPE 2: ALL CH ALL Cal FAIL
+    if ((PINInfo_flashtool.TOTAL_ERR == 0xffff) && (PINInfo_flashtool.WL_ERR_FLAG== 0xff))
+    {
+        mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: ALL calibration fail\n"));
+        mcSHOW_DBG_MSG3(("Suspect RESET_N contact issue\n"));
+        mcSHOW_DBG_MSG3(("Suspect DRAM Power (VDD1/VDD2/VDDQ) contact issue\n"));
+    }
+    else
+    {
+        for (u1CHIdx = 0; u1CHIdx < p->support_channel_num; u1CHIdx++)
+        {
+            #if (CHANNEL_NUM > 2)
+		    if (channel_num_auxadc > 2) {
+            if(u1CHIdx == CHANNEL_B)
+                u1CHIdx_EMI = CHANNEL_C;
+            else if(u1CHIdx == CHANNEL_C)
+                u1CHIdx_EMI = CHANNEL_B;
+            else //CHANNEL_A,CHANNEL_D
+		    	}
+            #endif
+                u1CHIdx_EMI = u1CHIdx;
+
+            //TYPE 3: ONE CH ALL RK ALL Cal FAIL
+            if ((PINInfo_flashtool.TOTAL_ERR>>(u1CHIdx*4) & 0xf) == 0xf)
+            {
+                mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: CH%d all calibration fail\n",u1CHIdx));
+                mcSHOW_DBG_MSG3(("Suspect EMI%d_CK_T contact issue\n",u1CHIdx_EMI));
+                mcSHOW_DBG_MSG3(("Suspect EMI%d_CK_C contact issue\n",u1CHIdx_EMI));
+                for (u1CAIdx =0; u1CAIdx <CATRAINING_NUM_LP4; u1CAIdx++)
+                {
+                    mcSHOW_DBG_MSG(("Suspect EMI%d_CA%d contact issue\n",u1CHIdx_EMI,u1CAIdx));
+                }
+            }
+            else
+            {
+                for(u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+                {
+                    //TYPE 4: ONE CH ONE RK ALL Cal FAIL
+                    if ((((PINInfo_flashtool.TOTAL_ERR>>(u1CHIdx*4+u1RankIdx*2)) & 0x3)==0x3) && \
+                         (PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][BYTE_0] == 0xff) && \
+                         (PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][BYTE_1] == 0xff)&& \
+                         (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][BYTE_0] == 0xff) && \
+                         (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][BYTE_1] == 0xff))
+                    {
+                        mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: CH%d RK%d all calibration fail\n",u1CHIdx,u1RankIdx));
+                        mcSHOW_DBG_MSG3(("Suspect EMI%d_CKE_%d contact issue\n",u1CHIdx_EMI,u1RankIdx));
+                        mcSHOW_DBG_MSG3(("Suspect EMI%d_CS_%d contact issue\n",u1CHIdx_EMI,u1RankIdx));
+                    }
+                    else
+                    {
+                        for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+                        {
+                            //TYPE 5: ONE CH ONE RK ONE Byte FAIL
+                            if((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff) &&\
+                                      (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff))
+                            {
+                                mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: CH%d RK%d Byte%d WL/Read/Write calibration fail\n",u1CHIdx,u1RankIdx,u1ByteIdx));
+                                mcSHOW_DBG_MSG3(("Suspect EMI%d_DQS%d_T contact issue\n",u1CHIdx_EMI,u1ByteIdx));
+                                mcSHOW_DBG_MSG3(("Suspect EMI%d_DQS%d_C contact issue\n",u1CHIdx_EMI,u1ByteIdx));
+                            }
+                            //TYPE 6: ONE CH ONE RK ONE Bit FAIL
+                            else if (PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]&&\
+                                       PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx])
+                            {
+                                for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx++)
+                                {
+                                    if (((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]>>u1BitIdx)&0x1)&&\
+                                         ((PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]>>u1BitIdx)&0x1))
+                                    {
+                                            mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: CH%d RK%d DRAM DQ%d Read/Write fail\n",u1CHIdx,u1RankIdx,u1ByteIdx*8+u1BitIdx));
+                                            mcSHOW_DBG_MSG3(("Suspect EMI%d_DQ%d contact issue\n",u1CHIdx_EMI,u1ByteIdx*8+u1BitIdx));
+                                    }
+                                }
+                            }
+                            //TYPE 7: ONE CH ONE RK ONE Byte FAIL(only RX or TX) -->OTHERS
+                            else if((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff) ||\
+                                      (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff))
+                            {
+                                mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: CH%d RK%d Byte%d Suspect other special contact or calibration issue\n",u1CHIdx_EMI,u1RankIdx,u1ByteIdx));
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    }
+    mcSHOW_DBG_MSG3(("\n"));
+    return;
+}
+#endif
+
+
+#if GATING_ONLY_FOR_DEBUG
+void DramcGatingDebugRankSel(DRAMC_CTX_T *p, U8 u1Rank)
+{
+    if (p->support_rank_num == RANK_SINGLE)
+    {
+        u1Rank = 0;
+    }
+
+    vIO32WriteFldAlign_All(DDRPHY_MISC_CTRL1, u1Rank, MISC_CTRL1_R_DMSTBENCMP_RK_OPT);
+}
+
+void DramcGatingDebugInit(DRAMC_CTX_T *p)
+{
+    U32 backupReg0x64[CHANNEL_NUM], backupReg0xC8[CHANNEL_NUM], backupReg0xD0[CHANNEL_NUM];
+    U32 backupRegShu_SCINTV[DRAM_DFS_SRAM_MAX][CHANNEL_NUM];
+    U32 channel_idx, backup_channel, shu_index;
+
+    backup_channel = vGetPHY2ChannelMapping(p);
+
+    for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
+    {
+        vSetPHY2ChannelMapping(p, channel_idx);
+        backupReg0x64[channel_idx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL));
+        backupReg0xC8[channel_idx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR));
+        backupReg0xD0[channel_idx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD));
+        for (shu_index = SRAM_SHU0; shu_index < DRAM_DFS_SRAM_MAX; shu_index++)
+            backupRegShu_SCINTV[shu_index][channel_idx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCINTV) + SHU_GRP_DRAMC_OFFSET * shu_index);
+    }
+    vSetPHY2ChannelMapping(p, backup_channel);
+
+    //Disable MR4 MR18/MR19, TxHWTracking, Dummy RD before reset
+    vIO32WriteFldAlign_All(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_REFRDIS);    //MR4 Disable
+    vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS);  //MR18, MR19 Disable
+    for (shu_index = SRAM_SHU0; shu_index < DRAM_DFS_SRAM_MAX; shu_index++)
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_SCINTV + SHU_GRP_DRAMC_OFFSET * shu_index, 0x1, SHU_SCINTV_DQSOSCENDIS);
+    vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN)
+                                            | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN)
+                                            | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN)
+                                            | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG));
+    mcDELAY_US(4);
+
+    DramPhyReset(p);
+
+    //Restore backup regs
+    for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
+    {
+        vSetPHY2ChannelMapping(p, channel_idx);
+        vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL), backupReg0x64[channel_idx]);
+        vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), backupReg0xC8[channel_idx]);
+        vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), backupReg0xD0[channel_idx]);
+        for (shu_index = SRAM_SHU0; shu_index < DRAM_DFS_SRAM_MAX; shu_index++)
+            vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCINTV) + SHU_GRP_DRAMC_OFFSET * shu_index, backupRegShu_SCINTV[shu_index][channel_idx]);
+    }
+    vSetPHY2ChannelMapping(p, backup_channel);
+
+
+    //enable &reset DQS counter
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 1, SPCMD_DQSGCNTEN);
+    mcDELAY_US(4);//wait 1 auto refresh after DQS Counter enable
+
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 1, SPCMD_DQSGCNTRST);
+    mcDELAY_US(1);//delay 2T
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 0, SPCMD_DQSGCNTRST);
+    //mcSHOW_DBG_MSG(("DramcGatingDebugInit done\n" ));
+}
+
+void DramcGatingDebugExit(DRAMC_CTX_T *p)
+{
+    //enable &reset DQS counter
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 0, SPCMD_DQSGCNTEN);
+    vIO32WriteFldAlign_All(DDRPHY_MISC_CTRL1, 0, MISC_CTRL1_R_DMSTBENCMP_RK_OPT);
+}
+
+static void DramcGatingDebug(DRAMC_CTX_T *p, U8 u1Channel)
+{
+    U32 LP3_DataPerByte[DQS_BYTE_NUMBER];
+    U32 u4DebugCnt[DQS_BYTE_NUMBER];
+    U16 u2DebugCntPerByte;
+
+    U32 u4value, u4all_result_R, u4all_result_F, u4err_value;
+    U8 backup_channel;
+
+    backup_channel = p->channel;
+    vSetPHY2ChannelMapping(p, u1Channel);
+
+    mcDELAY_MS(10);
+
+    LP3_DataPerByte[0] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_MISC_STBERR_RK0_R), MISC_STBERR_RK0_R_STBERR_RK0_R));
+    LP3_DataPerByte[2] = (LP3_DataPerByte[0] >> 8) & 0xff;
+    LP3_DataPerByte[0] &= 0xff;
+
+    u4all_result_R = LP3_DataPerByte[0] | (LP3_DataPerByte[2] << 8);
+
+    // falling
+    LP3_DataPerByte[0] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_MISC_STBERR_RK0_F), MISC_STBERR_RK0_F_STBERR_RK0_F));
+    LP3_DataPerByte[2] = (LP3_DataPerByte[0] >> 8) & 0xff;
+    LP3_DataPerByte[0] &= 0xff;
+
+    u4all_result_F = LP3_DataPerByte[0] | (LP3_DataPerByte[2] << 8);
+
+     //read DQS counter
+    u4DebugCnt[0] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DQSGNWCNT0));
+    u4DebugCnt[1] = (u4DebugCnt[0] >> 16) & 0xffff;
+    u4DebugCnt[0] &= 0xffff;
+
+    u4DebugCnt[2] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DQSGNWCNT1));
+    u4DebugCnt[3] = (u4DebugCnt[2] >> 16) & 0xffff;
+    u4DebugCnt[2] &= 0xffff;
+
+    mcSHOW_DBG_MSG2(("\n[GatingDebug] CH %d, DQS count (B3->B0) 0x%H, 0x%H, 0x%H, 0x%H \nError flag Rank0 (B3->B0) %B %B  %B %B  %B %B  %B %B\n", \
+                                   u1Channel, u4DebugCnt[3], u4DebugCnt[2], u4DebugCnt[1], u4DebugCnt[0], \
+                                   (u4all_result_F >> 24) & 0xff, (u4all_result_R >> 24) & 0xff, \
+                                   (u4all_result_F >> 16) & 0xff, (u4all_result_R >> 16) & 0xff, \
+                                   (u4all_result_F >> 8) & 0xff, (u4all_result_R >> 8) & 0xff, \
+                                   (u4all_result_F) & 0xff, (u4all_result_R) & 0xff));
+
+    if (p->support_rank_num == RANK_DUAL)
+    {
+        LP3_DataPerByte[0] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_MISC_STBERR_RK1_R), MISC_STBERR_RK1_R_STBERR_RK1_R));//PHY_B
+        LP3_DataPerByte[2] = (LP3_DataPerByte[0] >> 8) & 0xff;
+        LP3_DataPerByte[0] &= 0xff;
+
+        u4all_result_R = LP3_DataPerByte[0] | (LP3_DataPerByte[2] << 8);
+
+        // falling
+        LP3_DataPerByte[0] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_MISC_STBERR_RK1_F), MISC_STBERR_RK1_F_STBERR_RK1_F));//PHY_B
+        LP3_DataPerByte[2] = (LP3_DataPerByte[0] >> 8) & 0xff;
+        LP3_DataPerByte[0] &= 0xff;
+
+        u4all_result_F = LP3_DataPerByte[0];
+
+        mcSHOW_DBG_MSG2(("Error flag Rank1 (B3->B0) %B %B  %B %B  %B %B  %B %B\n", \
+                                       (u4all_result_F >> 24) & 0xff, (u4all_result_R >> 24) & 0xff, \
+                                       (u4all_result_F >> 16) & 0xff, (u4all_result_R >> 16) & 0xff, \
+                                       (u4all_result_F >> 8) & 0xff, (u4all_result_R >> 8) & 0xff, \
+                                       (u4all_result_F) & 0xff, (u4all_result_R) & 0xff));
+    }
+    else
+    {
+        mcSHOW_DBG_MSG2(("\n"));
+    }
+
+    //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 1, SPCMD_DQSGCNTRST);
+    //mcDELAY_US(1);//delay 2T
+    //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 0, SPCMD_DQSGCNTRST);
+
+    vSetPHY2ChannelMapping(p, backup_channel);
+}
+#endif
+
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+#if (__ETT__ || CPU_RW_TEST_AFTER_K)
+void DramcDumpDebugInfo(DRAMC_CTX_T *p)
+{
+
+U8 u1RefreshRate; //mpdivInSel, cali_shu_sel, mpdiv_shu_sel
+DRAM_CHANNEL_T channelIdx;
+
+
+#ifdef TEMP_SENSOR_ENABLE
+    for (channelIdx = CHANNEL_A; channelIdx < (int)p->support_channel_num; channelIdx++)
+    {
+        u1RefreshRate = u1GetMR4RefreshRate(p, channelIdx);
+        mcSHOW_DBG_MSG2(("[CH%d] MRR(MR4) [10:8]=%x\n", channelIdx, u1RefreshRate));
+    }
+#endif
+
+#if ENABLE_REFRESH_RATE_DEBOUNCE
+    {
+        U8 pre_refresh_rate[4];
+        for (channelIdx = CHANNEL_A; channelIdx < (int)p->support_channel_num; channelIdx++)
+        {
+            vSetPHY2ChannelMapping(p, channelIdx);
+
+            pre_refresh_rate[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_IRQ_INFO1A), DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK0_FOR_INT_X0);
+            pre_refresh_rate[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_IRQ_INFO1A), DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK1_FOR_INT_X0);
+            pre_refresh_rate[2] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_IRQ_INFO1A), DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK0_B1_FOR_INT_X0);
+            pre_refresh_rate[3] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_IRQ_INFO1A), DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK1_B1_FOR_INT_X0);
+
+            mcSHOW_DBG_MSG2(("\t[CH%d] RK0 B0 Int Status=0x%x\n", channelIdx, pre_refresh_rate[0]));
+            mcSHOW_DBG_MSG2(("\t[CH%d] RK1 B0 Int Status=0x%x\n", channelIdx, pre_refresh_rate[1]));
+            mcSHOW_DBG_MSG2(("\t[CH%d] RK0 B1 Int Status=0x%x\n", channelIdx, pre_refresh_rate[2]));
+            mcSHOW_DBG_MSG2(("\t[CH%d] RK1 B1 Int Status=0x%x\n", channelIdx, pre_refresh_rate[3]));
+
+            mcSHOW_DBG_MSG2(("\t[CH%d] MISC_STATUSA_REFRESH_RATE=%d\n", channelIdx, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_REFRESH_RATE)));
+        }
+        vSetPHY2ChannelMapping(p, CHANNEL_A);
+    }
+#endif
+
+
+
+#if __A60868_TO_BE_PORTING__
+    U8 mpdivInSel, cali_shu_sel, mpdiv_shu_sel, u1RefreshRate;
+    DRAM_CHANNEL_T channelIdx;
+
+    mpdivInSel = u4IO32ReadFldAlign(DDRPHY_MISC_CTRL2, MISC_CTRL2_CLRPLL_SHU_GP);
+    cali_shu_sel = u4IO32ReadFldAlign(DRAMC_REG_SHUCTRL, SHUCTRL_R_OTHER_SHU_GP);
+    mpdiv_shu_sel = u4IO32ReadFldAlign(DRAMC_REG_SHUCTRL, SHUCTRL_R_MPDIV_SHU_GP);
+
+    // Read shuffle selection
+    mcSHOW_DBG_MSG2(("\n\n[DumpDebugInfo]\n"
+                    "\tmpdivInSel %d, cali_shu_sel %d, mpdiv_shu_sel %d\n",
+                         mpdivInSel, cali_shu_sel, mpdiv_shu_sel));
+
+    #if GATING_ONLY_FOR_DEBUG
+    // Read gating error flag
+    //DramcGatingDebugInit(p);
+    for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++)
+    {
+        DramcGatingDebug(p, channelIdx);
+    }
+    #endif
+
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+    // Read HW gating tracking
+#ifdef HW_GATING
+    for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++)
+        {
+        DramcPrintHWGatingStatus(p, channelIdx);
+        }
+#endif
+
+    DramcPrintRXFIFODebugStatus(p);
+
+#if (ENABLE_RX_TRACKING && RX_DLY_TRACK_ONLY_FOR_DEBUG && defined(DUMMY_READ_FOR_TRACKING))
+    DramcPrintRxDlyTrackDebugStatus(p);
+#endif
+
+#if ENABLE_RX_TRACKING
+    for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++)
+        {
+        DramcPrintRXDQDQSStatus(p, channelIdx);
+        }
+#endif
+
+#ifdef IMPEDANCE_TRACKING_ENABLE
+        if (u1IsLP4Family(p->dram_type))
+        {
+        for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++)
+        {
+            DramcPrintIMPTrackingStatus(p, channelIdx);
+        }
+
+        }
+#endif
+
+#ifdef TEMP_SENSOR_ENABLE
+    for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++)
+    {
+        u1RefreshRate = u1GetMR4RefreshRate(p, channelIdx);
+        mcSHOW_DBG_MSG2(("[CH%d] MRR(MR4) [10:8]=%x\n", channelIdx, u1RefreshRate));
+    }
+#endif
+#endif//(FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
+#endif
+}
+#endif
+#endif
+
+#if ((fcFOR_CHIP_ID == fcA60868) || (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0))
+#if __ETT__
+#if DUMP_ALLSUH_RG
+static void DramcRegDumpRange(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr)
+{
+    U32 ii;
+    for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4)
+    {
+        mcSHOW_DBG_MSG(("Reg(0x%xh) Address 0x%X = 0x%X\n", (ii & 0xfff) >> 2, ii, u4Dram_Register_Read(p, DRAMC_REG_ADDR(ii))));
+        mcDELAY_US(20000); //Large delay to prevent UART overflow
+    }
+}
+ #if 0//(fcFOR_CHIP_ID == fcLafite)
+#define DRAMC_NAO_DUMP_RANGE (DRAMC_REG_RK2_B23_STB_DBG_INFO_15 - DRAMC_NAO_BASE_ADDRESS)
+#define DDRPHY_NAO_DUMP_RANGE (DDRPHY_MISC_MBIST_STATUS2 - DDRPHY_NAO_BASE_ADDR)
+#define DRAMC_AO_NONSHU_DUMP_RANGE (DRAMC_REG_RK1_PRE_TDQSCK27 - DRAMC_AO_BASE_ADDRESS)
+#define DRAMC_AO_SHU_BASE (DRAMC_REG_SHU_ACTIM0 - DRAMC_AO_BASE_ADDRESS)
+#define DRAMC_AO_SHU_DUMP_RANGE (DRAMC_REG_SHURK1_DQS2DQ_CAL5 - DRAMC_REG_SHU_ACTIM0)
+#define DDRPHY_AO_NONSHU_DUMP_RANGE (DDRPHY_RFU_0XB2C - DDRPHY_AO_BASE_ADDR)
+#define DDRPHY_AO_SHU_BASE (DDRPHY_SHU_B0_DQ0 - DDRPHY_AO_BASE_ADDR)
+#define DDRPHY_AO_SHU_DUMP_RANGE (DDRPHY_SHU_R2_CA_CMD9 - DDRPHY_SHU_B0_DQ0)
+#endif
+void DumpAoNonShuNoRkReg(DRAMC_CTX_T *p)
+{
+    mcSHOW_DBG_MSG(("\n\tCHA_DRAMC_AO_NONSHU_NORK_BASE\n"));
+    DramcRegDumpRange(p, DRAMC_REG_DDRCOMMON0, DRAMC_REG_SA_RESERVE);
+    DramcRegDumpRange(p, DRAMC_REG_NONSHU_RSV, DRAMC_REG_SCRAMBLE_CFGF);
+    DramcRegDumpRange(p, DRAMC_REG_WDT_DBG_SIGNAL, DRAMC_REG_SELFREF_HWSAVE_FLAG);
+    DramcRegDumpRange(p, DRAMC_REG_DRAMC_IRQ_STATUS1, DRAMC_REG_DRAMC_IRQ_INFO5);
+    mcSHOW_DBG_MSG(("\n\tCHA_PHY_AO_NONSHU_NORK_BASE\n"));
+    DramcRegDumpRange(p, DDRPHY_REG_PHYPLL0, DDRPHY_REG_CLRPLL0);
+    DramcRegDumpRange(p, DDRPHY_REG_B0_LP_CTRL0, DDRPHY_REG_B0_PHY4);
+    DramcRegDumpRange(p, DDRPHY_REG_B1_LP_CTRL0, DDRPHY_REG_B1_TX_CKE_CTRL);
+    DramcRegDumpRange(p, DDRPHY_REG_CA_LP_CTRL0, DDRPHY_REG_CA_TX_ARDQ_CTRL);
+    DramcRegDumpRange(p, DDRPHY_REG_MISC_STBCAL, DDRPHY_REG_MISC_BIST_LPBK_CTRL0);
+    mcSHOW_DBG_MSG(("\n\tDDRPHY_MD32_BASE_ADDRESS\n"));
+    DramcRegDumpRange(p, DDRPHY_MD32_REG_SSPM_CFGREG_SW_RSTN, DDRPHY_MD32_REG_SSPM_CFGREG_TBUFH);
+    DramcRegDumpRange(p, DDRPHY_MD32_REG_SSPM_TIMER0_CON, DDRPHY_MD32_REG_SSPM_OS_TIMER_IRQ_ACK);
+    DramcRegDumpRange(p, DDRPHY_MD32_REG_SSPM_INTC_IRQ_RAW_STA0, DDRPHY_MD32_REG_SSPM_INTC_UART_RX_IRQ);
+    DramcRegDumpRange(p, DDRPHY_MD32_REG_SSPM_MCLK_DIV, DDRPHY_MD32_REG_SSPM_UART_CTRL);
+    DramcRegDumpRange(p, DDRPHY_MD32_REG_SSPM_DMA_GLBSTA, DDRPHY_MD32_REG_SSPM_DMA4_LIMITER);
+    DramcRegDumpRange(p, DDRPHY_MD32_REG_SSPM_UART_RBR_THR_DLL_ADDR, DDRPHY_MD32_REG_SSPM_UART_SPM_SEL);
+    DramcRegDumpRange(p, DDRPHY_MD32_REG_SSPM_TWAM_CTRL, DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT15);
+    DramcRegDumpRange(p, DDRPHY_MD32_REG_LPIF_FSM_CFG, DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_3);
+    return;
+}
+void DumpAoNonShuRkReg(DRAMC_CTX_T *p)
+{
+    mcSHOW_DBG_MSG(("\n\tCHA_DRAMC_AO_NONSHU_RK_BASE\n"));
+    DramcRegDumpRange(p, DRAMC_REG_RK_TEST2_A1, DRAMC_REG_RK_DQSOSC);
+    mcSHOW_DBG_MSG(("\n\tCHA_PHY_AO_NONSHU_RK_BASE\n"));
+    DramcRegDumpRange(p, DDRPHY_REG_RK_B0_RXDVS0, DDRPHY_REG_RK_B0_RXDVS4);
+    DramcRegDumpRange(p, DDRPHY_REG_RK_B1_RXDVS0, DDRPHY_REG_RK_B1_RXDVS4);
+    DramcRegDumpRange(p, DDRPHY_REG_RK_CA_RXDVS0, DDRPHY_REG_RK_CA_RXDVS4);
+    return;
+}
+void DumpAoShuNoRkReg(DRAMC_CTX_T *p)
+{
+    mcSHOW_DBG_MSG(("\n\tCHA_DRAMC_AO_SHU_NORK_BASE\n"));
+    DramcRegDumpRange(p, DRAMC_REG_SHU_MATYPE, DRAMC_REG_SHU_ACTIM7);
+    mcSHOW_DBG_MSG(("\n\tCHA_PHY_AO_SHU_NORK_BASE\n"));
+    DramcRegDumpRange(p, DDRPHY_REG_SHU_PHYPLL0, DDRPHY_REG_SHU_PLL2);
+    DramcRegDumpRange(p, DDRPHY_REG_SHU_B0_DQ0, DDRPHY_REG_SHU_B0_DQSIEN_CFG);
+    DramcRegDumpRange(p, DDRPHY_REG_SHU_B1_DQ0, DDRPHY_REG_SHU_B1_CKE_DLY_CTRL);
+    DramcRegDumpRange(p, DDRPHY_REG_SHU_CA_CMD0, DDRPHY_REG_SHU_CA_DQ_DLY);
+    DramcRegDumpRange(p, DDRPHY_REG_MISC_SHU_DRVING7, DDRPHY_REG_MISC_SHU_CG_CTRL0);
+    DramcRegDumpRange(p, DDRPHY_REG_MISC_STBERR_ALL, DDRPHY_REG_MISC_DBG_DB_MESSAGE7);
+    return;
+}
+void DumpAoShuRkReg(DRAMC_CTX_T *p)
+{
+    mcSHOW_DBG_MSG(("\n\tCHA_DRAMC_AO_SHU_RK_BASE\n"));
+    DramcRegDumpRange(p, DRAMC_REG_SHURK_SELPH_DQ0, DRAMC_REG_SHURK_CKE_CTRL);
+    mcSHOW_DBG_MSG(("\n\tCHA_PHY_AO_SHU_RK_BASE\n"));
+    DramcRegDumpRange(p, DDRPHY_REG_SHU_R0_B0_TXDLY0, DDRPHY_REG_SHU_RK_B0_BIST_CTRL);
+    DramcRegDumpRange(p, DDRPHY_REG_SHU_R0_B1_TXDLY0, DDRPHY_REG_SHU_RK_B1_CKE_DLY);
+    DramcRegDumpRange(p, DDRPHY_REG_SHU_R0_CA_TXDLY0, DDRPHY_REG_SHU_RK_CA_DQ_DLY);
+    DramcRegDumpRange(p, DDRPHY_REG_MISC_SHU_RK_DQSCTL, DDRPHY_REG_MISC_SHU_RK_DQSCAL);
+    return;
+}
+void DumpNaoReg(DRAMC_CTX_T *p)
+{
+    mcSHOW_DBG_MSG(("\n\n\tCHA_DRAMC_NAO_BASE\n"));
+    DramcRegDumpRange(p, DRAMC_REG_TESTMODE, DRAMC_REG_CBT_WLEV_ATK_RESULT13);
+    DramcRegDumpRange(p, DRAMC_REG_HWMRR_PUSH2POP_CNT, DRAMC_REG_SREF_DLY_CNT);
+    DramcRegDumpRange(p, DRAMC_REG_TX_ATK_SET0, DRAMC_REG_TX_ATK_DBG_BIT_STATUS4);
+    DramcRegDumpRange(p, DRAMC_REG_LP5_PDX_PDE_MON, DRAMC_REG_LAT_COUNTER_BLOCK_ALE);
+    DramcRegDumpRange(p, DRAMC_REG_DRAMC_LOOP_BAK_ADR, DRAMC_REG_DRAMC_LOOP_BAK_WDAT7);
+    DramcRegDumpRange(p, DRAMC_REG_RK0_DQSOSC_STATUS, DRAMC_REG_RK0_DUMMY_RD_DATA7);
+    DramcRegDumpRange(p, DRAMC_REG_RK0_PI_DQ_CAL, DRAMC_REG_RK0_PI_DQM_CAL);
+    DramcRegDumpRange(p, DRAMC_REG_RK1_DQSOSC_STATUS, DRAMC_REG_RK1_DUMMY_RD_DATA7);
+    DramcRegDumpRange(p, DRAMC_REG_RK1_PI_DQ_CAL, DRAMC_REG_RK1_PI_DQM_CAL);
+    DramcRegDumpRange(p, DRAMC_REG_MR_BACKUP_00_RK0_FSP0, DRAMC_REG_MR_BACKUP_03_RK0_FSP2);
+    DramcRegDumpRange(p, DRAMC_REG_MR_BACKUP_00_RK1_FSP0, DRAMC_REG_MR_BACKUP_03_RK1_FSP2);
+    mcSHOW_DBG_MSG(("\n\tCHA_PHY_NAO_BASE\n"));
+    DramcRegDumpRange(p, DDRPHY_REG_MISC_STA_EXTLB0, DDRPHY_REG_MISC_RDSEL_TRACK_DBG);
+    DramcRegDumpRange(p, DDRPHY_REG_MISC_DQ_RXDLY_TRRO0, DDRPHY_REG_MISC_DQ_RXDLY_TRRO31);
+    DramcRegDumpRange(p, DDRPHY_REG_MISC_CA_RXDLY_TRRO20, DDRPHY_REG_MISC_STA_TOGLB1);
+    DramcRegDumpRange(p, DDRPHY_REG_MISC_STA_EXTLB_DBG0, DDRPHY_REG_MISC_STA_EXTLB5);
+    DramcRegDumpRange(p, DDRPHY_REG_DEBUG_APHY_RX_CTL, DDRPHY_REG_DEBUG_RODT_CTL);
+    DramcRegDumpRange(p, DDRPHY_REG_CAL_DQSG_CNT_B0, DDRPHY_REG_RX_AUTOK_STATUS20);
+    DramcRegDumpRange(p, DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0, DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS5);
+    DramcRegDumpRange(p, DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_STATUS0, DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE11);
+    DramcRegDumpRange(p, DDRPHY_REG_MISC_DMA_SRAM_MBIST, DDRPHY_REG_MISC_STA_EXTLB9);
+    return;
+}
+void DumpAllRkRG(DRAMC_CTX_T *p, U8 u1ShuType)
+{
+    U8 u1RankIdx, u1rk_backup=u1GetRank(p);
+    if (u1ShuType == NONSHUFFLE_RG||u1ShuType == BOTH_SHU_NONSHU_RG)
+    {
+        mcSHOW_DBG_MSG(("\n[DUMPLOG] Channel=%d, Rank=NON, SHU=NON, FREQ=NON, AORG, start \n", vGetPHY2ChannelMapping(p)));
+        DumpAoNonShuNoRkReg(p);
+        mcSHOW_DBG_MSG(("\n[DUMPLOG] Channel=%d, Rank=NON, SHU=NON, FREQ=NON, AORG, end \n", vGetPHY2ChannelMapping(p)));
+    }
+    if (u1ShuType == SHUFFLE_RG||u1ShuType == BOTH_SHU_NONSHU_RG)
+    {
+        mcSHOW_DBG_MSG(("\n[DUMPLOG] Channel=%d, Rank=NON, SHU=SRAM%d, FREQ=%d, AORG, start \n", vGetPHY2ChannelMapping(p), vGet_Current_SRAMIdx(p), GetFreqBySel(p, vGet_PLL_FreqSel(p))));
+        DumpAoShuNoRkReg(p);
+        mcSHOW_DBG_MSG(("\n[DUMPLOG] Channel=%d, Rank=NON, SHU=SRAM%d, FREQ=%d, AORG, end \n", vGetPHY2ChannelMapping(p), vGet_Current_SRAMIdx(p), GetFreqBySel(p, vGet_PLL_FreqSel(p))));
+    }
+    for (u1RankIdx=RANK_0; u1RankIdx<p->support_rank_num; u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+        if (u1ShuType == NONSHUFFLE_RG||u1ShuType == BOTH_SHU_NONSHU_RG)
+        {
+            mcSHOW_DBG_MSG(("\n[DUMPLOG] Channel=%d, Rank=%d, SHU=NON, FREQ=NON, AORG, start \n", vGetPHY2ChannelMapping(p), u1GetRank(p)));
+            DumpAoNonShuRkReg(p);
+            mcSHOW_DBG_MSG(("\n[DUMPLOG] Channel=%d, Rank=%d, SHU=NON, FREQ=NON, AORG, end \n", vGetPHY2ChannelMapping(p), u1GetRank(p)));
+        }
+        if (u1ShuType == SHUFFLE_RG||u1ShuType == BOTH_SHU_NONSHU_RG)
+        {
+            mcSHOW_DBG_MSG(("\n[DUMPLOG] Channel=%d, Rank=%d, SHU=SRAM%d, FREQ=%d, AORG, start \n", vGetPHY2ChannelMapping(p), u1GetRank(p), vGet_Current_SRAMIdx(p), GetFreqBySel(p, vGet_PLL_FreqSel(p))));
+            DumpAoShuRkReg(p);
+            mcSHOW_DBG_MSG(("\n[DUMPLOG] Channel=%d, Rank=%d, SHU=SRAM%d, FREQ=%d, AORG, end \n", vGetPHY2ChannelMapping(p), u1GetRank(p), vGet_Current_SRAMIdx(p), GetFreqBySel(p, vGet_PLL_FreqSel(p))));
+        }
+    }
+    vSetRank(p, u1rk_backup);
+}
+void DumpAllChAllShuAllRkRG(DRAMC_CTX_T *p)
+{
+    U8 u1ChannelIdx, u1Ch_backup=vGetPHY2ChannelMapping(p);
+    U8 u1ShuffleIdx, u1Shu_backup=p->ShuRGAccessIdx;
+    for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<p->support_channel_num; u1ChannelIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1ChannelIdx);
+        DumpAllRkRG(p,NONSHUFFLE_RG);
+        for(u1ShuffleIdx=DRAM_DFS_REG_SHU0; u1ShuffleIdx<DRAM_DFS_REG_MAX; u1ShuffleIdx++)
+        {
+            p->ShuRGAccessIdx = u1ShuffleIdx;
+            DumpAllRkRG(p,SHUFFLE_RG);
+        }
+    }
+    p->ShuRGAccessIdx=u1Shu_backup;
+    vSetPHY2ChannelMapping(p, u1Ch_backup);
+}
+static void DumpShuRG(DRAMC_CTX_T *p)
+{
+    DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable = p->pDFSTable; // from dramc conf shu0
+    U8 u1ShuffleIdx;
+    U32 u4DramcShuOffset = 0;
+    U32 u4DDRPhyShuOffset = 0;
+    U32 u4RegBackupAddress[] =
+    {
+        (DDRPHY_REG_MISC_SRAM_DMA0),
+        (DDRPHY_REG_MISC_SRAM_DMA1),
+        #if (CHANNEL_NUM>1)
+        (DDRPHY_REG_MISC_SRAM_DMA0+SHIFT_TO_CHB_ADDR),
+        (DDRPHY_REG_MISC_SRAM_DMA1+SHIFT_TO_CHB_ADDR),
+        #endif
+        #if (CHANNEL_NUM>2)
+        (DDRPHY_REG_MISC_SRAM_DMA0+SHIFT_TO_CHC_ADDR),
+        (DDRPHY_REG_MISC_SRAM_DMA1+SHIFT_TO_CHC_ADDR),
+        (DDRPHY_REG_MISC_SRAM_DMA0+SHIFT_TO_CHD_ADDR),
+        (DDRPHY_REG_MISC_SRAM_DMA1+SHIFT_TO_CHD_ADDR),
+        #endif
+    };
+    DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);//before setting
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS);
+    DumpAllRkRG(p,NONSHUFFLE_RG);
+    for (u1ShuffleIdx = 0; u1ShuffleIdx <= DRAM_DFS_SRAM_MAX; u1ShuffleIdx++) //fill SHU1 of conf while (u1ShuffleIdx==DRAM_DFS_SRAM_MAX)
+    {
+        if (u1ShuffleIdx == DRAM_DFS_SRAM_MAX)
+        {
+            vSetDFSTable(p, pFreqTable);//Restore DFS table
+            u4DramcShuOffset = 0;
+            u4DDRPhyShuOffset = 0;
+            DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+        }
+        else
+        {
+            vSetDFSTable(p, get_FreqTbl_by_SRAMIndex(p, u1ShuffleIdx));//Update DFS table
+            vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);//before setting
+            vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, u1ShuffleIdx, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL);
+            vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL);//Trigger DEBUG MODE
+            p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1;
+            DumpAllRkRG(p,SHUFFLE_RG);
+            p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
+        }
+     }
+}
+void DumpAllChAllShuRG(DRAMC_CTX_T *p)
+{
+    U8 u1ChannelIdx, u1Channel_backup;
+    u1Channel_backup = p->channel;
+    for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<p->support_channel_num; u1ChannelIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1ChannelIdx);
+        mcSHOW_DBG_MSG(("\n[DUMPLOG]AllChannelAllShu-start Channel=%d\n", p->channel));
+        DumpShuRG(p);
+    }
+    vSetPHY2ChannelMapping(p, u1Channel_backup);
+}
+#endif
+#if ETT_NO_DRAM
+static void NoDramDramcRegDumpRange(U32 u4StartAddr, U32 u4EndAddr)
+{
+    U32 ii;
+    for (ii = u4StartAddr; ii < u4EndAddr; ii += 4)
+    {
+        mcSHOW_DBG_MSG(("*(volatile unsigned int *)0x%X = 0x%X;\n", ii, (*(volatile unsigned int *)(ii))));
+    }
+}
+DRAM_STATUS_T NoDramDramcRegDump(DRAMC_CTX_T *p)
+{
+    mcSHOW_DBG_MSG(("\n\n\tCHA_DRAMC_AO_BASE\n"));
+    NoDramDramcRegDumpRange(Channel_A_DRAMC_AO_BASE_ADDRESS, Channel_A_DRAMC_AO_BASE_ADDRESS + 0x1E58);
+    mcSHOW_DBG_MSG(("\n\tCHB_DRAMC_AO_BASE\n"));
+    NoDramDramcRegDumpRange(Channel_B_DRAMC_AO_BASE_ADDRESS, Channel_B_DRAMC_AO_BASE_ADDRESS + 0x1E58);
+    mcSHOW_DBG_MSG(("\n\tPHY_A_BASE\n"));
+    NoDramDramcRegDumpRange(Channel_A_DDRPHY_BASE_ADDRESS, Channel_A_DDRPHY_BASE_ADDRESS + 0x1FC8);
+    mcSHOW_DBG_MSG(("\n\tPHY_B_BASE\n"));
+    NoDramDramcRegDumpRange(Channel_B_PHY_BASE_ADDRESS, Channel_B_PHY_BASE_ADDRESS + 0x1FC8);
+    return DRAM_OK;
+}
+DRAM_STATUS_T NoDramRegFill(void)
+{
+}
+#endif
+#endif
+#endif
+#if DRAMC_MODEREG_CHECK
+#if defined(RELEASE) && defined(DEVIATION)
+#undef mcSHOW_JV_LOG_MSG
+#define mcSHOW_JV_LOG_MSG(_x_)    opt_print _x_
+#endif
+void DramcModeReg_Check(DRAMC_CTX_T *p)
+{
+    U8 backup_channel, backup_rank;
+    U8 u1ChannelIdx, u1RankIdx;
+    U8 u1MRFsp; //operating_fsp = p->dram_fsp
+    U8 ii, u1MR[] = {5, 12, 14, 4, 18, 19}; //MR5, MR12, MR14, MR18, MR19
+    U16 u2MRValue = 0, u2Value = 0;
+    U8 u1match = 0;
+    U8 backup_u1MR13Value[RANK_MAX] = {0};
+#if MRW_CHECK_ONLY || MRW_BACKUP
+    U8 FSPWR_FlagBak[RANK_MAX];
+#endif
+
+    mcSHOW_DBG_MSG2(("\n\n[DramcModeReg_Check] Freq_%d, FSP_%d\n", p->frequency, p->dram_fsp));
+
+    backup_channel = vGetPHY2ChannelMapping(p);
+    backup_rank = u1GetRank(p);
+
+    #if MRW_CHECK_ONLY || MRW_BACKUP
+    for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++)
+    {
+        FSPWR_FlagBak[u1RankIdx] = gFSPWR_Flag[u1RankIdx];
+    }
+    #endif
+
+    if (u1IsLP4Family(p->dram_type))
+    {
+        #if VENDER_JV_LOG && defined(DEVIATION)
+        mcSHOW_JV_LOG_MSG(("\n\n[DramcModeReg_Check] Freq_%d, FSP_%d\n",p->frequency,p->dram_fsp));
+        #else
+        mcSHOW_DBG_MSG2(("\n\n[DramcModeReg_Check] Freq_%d, FSP_%d\n",p->frequency,p->dram_fsp));
+        #endif
+
+        #if MRW_CHECK_ONLY
+        mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+        #endif
+
+        for (u1MRFsp = FSP_0; u1MRFsp < p->support_fsp_num; u1MRFsp++)
+        {
+            for (u1ChannelIdx = 0; u1ChannelIdx < (p->support_channel_num); u1ChannelIdx++)
+            {
+                vSetPHY2ChannelMapping(p, u1ChannelIdx);
+
+                for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++)
+                {
+                #if MRW_CHECK_ONLY || MRW_BACKUP
+                    if (u1MRFsp == FSP_0)
+                    {
+                        gFSPWR_Flag[u1RankIdx] = FSPWR_FlagBak[u1RankIdx];
+                    }
+                    else
+                    {
+                        gFSPWR_Flag[u1RankIdx] = u1MRFsp - 1;
+                    }
+                #endif
+
+                    backup_u1MR13Value[u1RankIdx] = u1MR13Value[u1RankIdx];
+                #if VENDER_JV_LOG && defined(DEVIATION)
+                    mcSHOW_JV_LOG_MSG(("FSP_%d, CH_%d, RK%d\n",u1MRFsp,u1ChannelIdx,u1RankIdx));
+                #else
+                    mcSHOW_DBG_MSG2(("FSP_%d, CH_%d, RK%d\n",u1MRFsp,u1ChannelIdx,u1RankIdx));
+                #endif
+
+                    if (u1MRFsp == FSP_1)
+                        u1MR13Value[u1RankIdx] |= 0x40;   //Read/Write FSP
+                    else
+                        u1MR13Value[u1RankIdx] &= (~0x40);   //Read/Write FSP
+
+                    DramcModeRegWriteByRank(p, u1RankIdx, 13, u1MR13Value[u1RankIdx]);
+
+                    for (ii = 0; ii < sizeof(u1MR); ii++)
+                    {
+                        DramcModeRegReadByRank(p, u1RankIdx, u1MR[ii], &u2Value);
+                        u2Value &= 0xFF;
+
+                        if ((u1MR[ii] == 12) || (u1MR[ii] == 14)) //need to compare final setting with global variants
+                        {
+                            if (u1MR[ii] == 12)
+                            {
+                                u2MRValue = u1MR12Value[u1ChannelIdx][u1RankIdx][u1MRFsp];
+                            }
+                            else if (u1MR[ii] == 14)
+                            {
+                                u2MRValue = u1MR14Value[u1ChannelIdx][u1RankIdx][u1MRFsp];
+                            }
+                            u1match = (u2Value == u2MRValue)? 1: 0;
+
+    #ifdef FOR_HQA_REPORT_USED
+                            if (gHQALog_flag == 1)
+                            {
+                                HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT1, "DramcModeReg_Read_FSP_", u1MRFsp==0?"0_MR":"1_MR", u1MR[ii], u2Value, NULL);
+                            }
+                            else
+    #endif
+                            {
+                                mcSHOW_DBG_MSG2(("\t\tMR%d = 0x%x (global = 0x%x)\t%smatch\n",u1MR[ii],u2Value,u2MRValue, (u1match==1)?"":"mis"));
+                                #if VENDER_JV_LOG && defined(DEVIATION)
+                                mcSHOW_JV_LOG_MSG(("[Vref Range = %d, Vref Value = %d]\n",(u2Value>>6)&1, u2Value&0x3f));
+                                #else
+                                mcSHOW_DBG_MSG2(("[Vref Range = %d, Vref Value = %d]\n",(u2Value>>6)&1, u2Value&0x3f));
+                                #endif
+
+                            }
+                        }
+                        else
+                        {
+    #ifdef FOR_HQA_REPORT_USED
+                            if (gHQALog_flag == 1)
+                            {
+                                HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT1, "DramcModeReg_Read_FSP_", u1MRFsp==0?"0_MR":"1_MR", u1MR[ii], u2Value, NULL);
+                            }
+                            else
+    #endif
+                            {
+                                const char *str_vender = "";
+                                if (u1MR[ii] == 5)
+                                {
+                                    //Vendor ID 1: Samsung, 6: Hynix
+                                    str_vender = (u2Value == 1)? "Samsung":(u2Value==0xff)?"Micron":(u2Value==0x5)?"Nanya":(u2Value==0x6)?"Hynix":"mismatch";
+                                }
+                                mcSHOW_DBG_MSG2(("\t\tMR%d = 0x%x %s\n", u1MR[ii], u2Value, str_vender));
+                            }
+                        }
+
+                    }
+
+                    // resotre MR13 settings
+                    u1MR13Value[u1RankIdx] = backup_u1MR13Value[u1RankIdx];
+                }
+            }
+        }
+
+    #if MRW_CHECK_ONLY || MRW_BACKUP
+        for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++)
+        {
+            FSPWR_FlagBak[u1RankIdx] = gFSPWR_Flag[u1RankIdx];
+        }
+    #endif
+
+        for (u1ChannelIdx = 0; u1ChannelIdx < (p->support_channel_num); u1ChannelIdx++)
+        {
+            vSetPHY2ChannelMapping(p, u1ChannelIdx);
+            for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++)
+            {
+            #if MRW_CHECK_ONLY || MRW_BACKUP
+                gFSPWR_Flag[u1RankIdx] = FSPWR_FlagBak[u1RankIdx];
+            #endif
+
+                DramcModeRegWriteByRank(p, u1RankIdx, 13, backup_u1MR13Value[u1RankIdx]);
+            }
+        }
+    }
+
+    vSetPHY2ChannelMapping(p, backup_channel);
+    vSetRank(p, backup_rank);
+    return;
+}
+#if defined(RELEASE) && defined(DEVIATION)
+#undef mcSHOW_JV_LOG_MSG
+#define mcSHOW_JV_LOG_MSG(_x_)
+#endif
+#endif
+
+#if MRW_CHECK_ONLY
+void vPrintFinalModeRegisterSetting(DRAMC_CTX_T * p)
+{
+    U8 u1CHIdx, u1RankIdx, u1FSPIdx, u1MRIdx;
+    U16 u2MRValue;
+    U8 u1Backup_Channel, u1Backup_Rank, u1Backup_Fsp;
+
+    mcSHOW_MRW_MSG(("\n\n\n==vPrintFinalModeRegisterSetting====\n"));
+
+    u1Backup_Channel = vGetPHY2ChannelMapping(p);
+    u1Backup_Rank = u1GetRank (p);
+
+    for (u1CHIdx = 0; u1CHIdx < p->support_channel_num; u1CHIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1CHIdx);
+        for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+        {
+            vSetRank(p, u1RankIdx);
+            u1Backup_Fsp = gFSPWR_Flag[p->rank];
+            for (u1FSPIdx = 0; u1FSPIdx < p->support_fsp_num; u1FSPIdx++)
+            {
+                gFSPWR_Flag[p->rank]=u1FSPIdx;
+                mcSHOW_MRW_MSG(("==[MR Dump] CH%d Rank%d Fsp%d ==\n", p->channel, p->rank, gFSPWR_Flag[p->rank]));
+                for (u1MRIdx = 0; u1MRIdx < MR_NUM; u1MRIdx++)
+                {
+                    u2MRValue = u2MRRecord[u1CHIdx][u1RankIdx][u1FSPIdx][u1MRIdx];
+                    if (u2MRValue != 0xffff) //value changed
+                    {
+                        mcSHOW_MRW_MSG(("[MR Dump] CH%d Rank%d Fsp%d MR%d =0x%x\n", p->channel, p->rank, gFSPWR_Flag[p->rank], u1MRIdx, u2MRValue));
+                        #if MRW_BACKUP
+                        //MR13(LP4) work around, two RG is not synchronized
+                        #if (__LP5_COMBO__ == TRUE)
+                        if (is_lp5_family(p))
+                        {
+                            if (u1MRIdx==16)
+                                gFSPWR_Flag[p->rank]=u1Backup_Fsp;
+                        }
+                        else
+                        #endif
+                        {
+                             if (u1MRIdx==13)
+                                gFSPWR_Flag[p->rank]=u1Backup_Fsp;
+                        }
+
+                        DramcMRWriteBackup(p, u1MRIdx, u1RankIdx);
+
+                        #if (__LP5_COMBO__ == TRUE)
+                        if (is_lp5_family(p))
+                        {
+                            if (u1MRIdx==16)
+                                gFSPWR_Flag[p->rank]=u1FSPIdx;
+                        }
+                        else
+                        #endif
+                        {
+                             if (u1MRIdx==13)
+                                gFSPWR_Flag[p->rank]=u1FSPIdx;
+                        }
+                        #endif
+                    }
+                }
+                mcSHOW_MRW_MSG(("\n"));
+            }
+            gFSPWR_Flag[p->rank] = u1Backup_Fsp;
+        }
+    }
+    vSetRank(p, u1Backup_Rank);
+    vSetPHY2ChannelMapping(p, u1Backup_Channel);
+}
+#endif
+
+#if defined(TEST_MODE_MRS) || SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER
+const U8 PME_Key[4][6] =
+{
+    { 2, 5, 5, 2, 4, 8},
+    { 2, 5, 5, 2, 4, 8},
+    { 2, 5, 5, 2, 4, 8},
+    { 10, 13, 13, 10, 12, 13}
+};
+
+
+static U32 u4TestModeV0[2] = {};
+static U32 u4TestModeV1[2] = {};
+static U32 u4TestModeV2[2] = {};
+static U32 u4TestModeV3[2] = {};
+static U32 u4TestModeV4[2] = {};
+static U32 u4TestModeV5[2] = {};
+static U32 u4TestModeV6[2] = {};
+
+static void BackupRGBeforeTestMode(DRAMC_CTX_T *p)
+{
+    DRAM_CHANNEL_T eOriChannel = p->channel;
+    int i = 0;
+     p->channel = CHANNEL_A;
+    for (i = 0; i < 2; i++)
+    {
+        if (i == 0)
+        {
+            mcSHOW_DBG_MSG(("***CHA\n"));
+        }
+        else
+        {
+            mcSHOW_DBG_MSG(("***CHB\n"));
+        }
+
+        u4TestModeV0[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0));//MRS_MRSRK
+        mcSHOW_DBG_MSG5(("DRAMC_REG_MRS[0x%x]\n", u4TestModeV0[i]));
+        u4TestModeV1[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL));
+        mcSHOW_DBG_MSG5(("DRAMC_REG_DRAMC_PD_CTRL[0x%x]\n", u4TestModeV1[i]));
+        u4TestModeV2[i] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL));//STBCAL_DQSIENCG_NORMAL_EN
+        mcSHOW_DBG_MSG5(("DRAMC_REG_STBCAL[0x%x]\n", u4TestModeV2[i]));
+        u4TestModeV3[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0));//Auto refresh
+        mcSHOW_DBG_MSG5(("DRAMC_REG_REFCTRL0[0x%x]\n", u4TestModeV3[i]));
+        u4TestModeV4[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_HMR4));//HW MR4
+        mcSHOW_DBG_MSG5(("DRAMC_REG_SPCMDCTRL[0x%x]\n", u4TestModeV4[i]));
+        u4TestModeV5[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL));
+        mcSHOW_DBG_MSG5(("DRAMC_REG_CKECTRL[0x%x]\n", u4TestModeV5[i]));
+        u4TestModeV6[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE));
+        mcSHOW_DBG_MSG5(("DRAMC_REG_SLP4_TESTMODE[0x%x]\n", u4TestModeV6[i]));
+        p->channel = CHANNEL_B;
+    }
+    p->channel = eOriChannel;
+    return;
+
+}
+
+static void RestoreRGBeforeTestMode(DRAMC_CTX_T *p)
+{
+    DRAM_CHANNEL_T eOriChannel = p->channel;
+    int i = 0;
+    p->channel = CHANNEL_A;
+    for (i = 0; i < 2; i++)
+    {
+        vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u4TestModeV0[i]);
+        vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4TestModeV1[i]);
+        vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), u4TestModeV2[i]);
+        vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), u4TestModeV3[i]);
+        vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_HMR4), u4TestModeV4[i]);
+        vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4TestModeV5[i]);
+        vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), u4TestModeV6[i]);
+
+        p->channel = CHANNEL_B;
+    }
+    p->channel = eOriChannel;
+    return;
+}
+
+void ProgramModeEnter(DRAMC_CTX_T *p)
+{
+    DRAM_CHANNEL_T eOriChannel = p->channel;
+    U8 i = 0;
+    U8 j = 0;
+    U8 k = 0;
+    U8 u1Rank = 0;
+
+    BackupRGBeforeTestMode(p);
+    p->channel = CHANNEL_A;
+    mcSHOW_DBG_MSG3(("ProgramModeEnter [Begin]\n"));
+
+    for (i = 0; i < 4; i++)
+    {
+        for (j = 0; j < 6; j++)
+        {
+             mcSHOW_DBG_MSG3(("Key[%d] CA[%d] => [%d]\n", i, j, PME_Key[i][j]));
+        }
+        mcSHOW_DBG_MSG3(("\n"));
+    }
+
+    for (i = 0; i < p->support_channel_num; i++)
+    {
+        if (i == 0)
+        {
+            mcSHOW_DBG_MSG3(("***CHA\n"));
+        }
+        else
+        {
+            mcSHOW_DBG_MSG3(("***CHB\n"));
+        }
+        for (j = 0; j < p->support_rank_num; j++)
+        {
+            if (j == 0)
+            {
+                u1Rank = 0;
+                mcSHOW_DBG_MSG3(("***R0\n"));
+            }
+            else
+            {
+                u1Rank = 1;
+                mcSHOW_DBG_MSG3(("***R1\n"));
+            }
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Rank, SWCMD_CTRL0_MRSRK);
+
+            //Disable dramc and DDRPHY clock gated, let clock freerun
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_DCMEN);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_PHYCLKDYNGEN);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0, MISC_STBCAL_DQSIENCG_NORMAL_EN);
+
+            //Disable MR4, refresh
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 1, REFCTRL0_REFDIS);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_REFRDIS);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), 1, CKECTRL_CKEFIXON);
+
+            for (k = 0; k < 4; k++)
+            {
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PME_Key[k][0], SLP4_TESTMODE_CA0_TEST);
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PME_Key[k][1], SLP4_TESTMODE_CA1_TEST);
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PME_Key[k][2], SLP4_TESTMODE_CA2_TEST);
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PME_Key[k][3], SLP4_TESTMODE_CA3_TEST);
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PME_Key[k][4], SLP4_TESTMODE_CA4_TEST);
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PME_Key[k][5], SLP4_TESTMODE_CA5_TEST);
+
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_STESTEN);
+                while (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_STEST_RESPONSE))
+                {
+                    mcSHOW_DBG_MSG3(("status[%d]: %d\n", k, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_STEST_RESPONSE)));
+                    break;
+                }
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_STESTEN);
+            }
+        }
+        p->channel = CHANNEL_B;
+    }
+    mcSHOW_DBG_MSG3(("ProgramModeEnter [Stop]\n"));
+    p->channel = eOriChannel;
+    RestoreRGBeforeTestMode(p);
+    return;
+}
+
+void ProgramCodeInput(DRAMC_CTX_T *p, U16 u2A_value, U16 u2B_value, U16 u2C_value)
+{
+    DRAM_CHANNEL_T eOriChannel = p->channel;
+    U8 i = 0;
+    U8 j = 0;
+    U8 k = 0;
+    int keyNumber = 0;
+    U16 u2Value = 0;
+    U8 u1Rank = 0;
+
+    BackupRGBeforeTestMode(p);
+    p->channel = CHANNEL_A;
+    //CA0, CA1, CA2, CA3, CA4, CA5
+    U8 PCI_Key[5][6] =
+    {
+        { 0, 0, 0, 0, 0, 0},
+        { 0, 0, 0, 0, 0, 0},
+        { 0, 0, 0, 0, 0, 0},
+        { 2, 5, 1, 2, 0, 0},
+        { 2, 5, 1, 2, 0, 0}
+    };
+
+    mcSHOW_DBG_MSG3(("ProgramCodeInput [Begin]\n"));
+
+    for (keyNumber = 0; keyNumber < 3; keyNumber++)
+    {
+        if (keyNumber == 0)
+            u2Value = u2A_value;
+        else if (keyNumber == 1)
+            u2Value = u2B_value;
+        else
+            u2Value = u2C_value;
+
+        PCI_Key[keyNumber][0] = (u2Value == 0)? (10): (2);
+        PCI_Key[keyNumber][1] = (u2Value == 1)? (13): (5);
+        PCI_Key[keyNumber][2] = (u2Value == 10)? (5): ((u2Value == 2)? (9): (1));
+        PCI_Key[keyNumber][3] = (u2Value == 9)? (6): ((u2Value == 3)? (10): (2));
+        PCI_Key[keyNumber][4] = (u2Value == 8)? (4): ((u2Value == 4)? (8): (0));
+        PCI_Key[keyNumber][5] = (u2Value == 7)? (1): ((u2Value == 6)? (4): ((u2Value == 5)? (8): (0)));
+    }
+
+    for (i = 0; i < 5; i++)
+    {
+        for (j = 0; j < 6; j++)
+        {
+             mcSHOW_DBG_MSG3(("Key[%d] CA[%d] => [%d]\n", i, j, PCI_Key[i][j]));
+        }
+        mcSHOW_DBG_MSG3(("\n"));
+    }
+
+    for (i = 0; i < p->support_channel_num; i++)
+    {
+        if (i == 0)
+        {
+            mcSHOW_DBG_MSG3(("***CHA\n"));
+        }
+        else
+        {
+            mcSHOW_DBG_MSG3(("***CHB\n"));
+        }
+        for (j = 0; j < p->support_rank_num; j++)
+        {
+            if (j == 0)
+            {
+                u1Rank = 0;
+                mcSHOW_DBG_MSG3(("***R0\n"));
+            }
+            else
+            {
+                u1Rank = 1;
+                mcSHOW_DBG_MSG3(("***R1\n"));
+            }
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Rank, SWCMD_CTRL0_MRSRK);
+
+            //Disable dramc and DDRPHY clock gated, let clock freerun
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_DCMEN);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_PHYCLKDYNGEN);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0, MISC_STBCAL_DQSIENCG_NORMAL_EN);
+
+            //Disable MR4, refresh
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 1, REFCTRL0_REFDIS);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_REFRDIS);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), 1, CKECTRL_CKEFIXON);
+
+            for (k = 0; k < 5; k++)
+            {
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PCI_Key[k][0], SLP4_TESTMODE_CA0_TEST);
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PCI_Key[k][1], SLP4_TESTMODE_CA1_TEST);
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PCI_Key[k][2], SLP4_TESTMODE_CA2_TEST);
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PCI_Key[k][3], SLP4_TESTMODE_CA3_TEST);
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PCI_Key[k][4], SLP4_TESTMODE_CA4_TEST);
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SLP4_TESTMODE), PCI_Key[k][5], SLP4_TESTMODE_CA5_TEST);
+
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_STESTEN);
+                while (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_STEST_RESPONSE))
+                {
+                    mcSHOW_DBG_MSG3(("status[%d]: %d\n", k, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_STEST_RESPONSE)));
+                    break;
+                }
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_STESTEN);
+            }
+        }
+        p->channel = CHANNEL_B;
+    }
+    mcSHOW_DBG_MSG3(("ProgramCodeInput [Stop]\n"));
+    p->channel = eOriChannel;
+    RestoreRGBeforeTestMode(p);
+    return;
+}
+
+void vApplyProgramSequence(DRAMC_CTX_T *p)
+{
+    #if SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER == 1
+    //Buffer sensitivity decrease1
+    //test 2. TMRS enter -> 000 -> 390 -> 120 -> 8A7
+    ProgramModeEnter(p);
+    ProgramCodeInput(p, 0, 0, 0);
+    ProgramCodeInput(p, 3, 9, 0);
+    ProgramCodeInput(p, 1, 2, 0);
+    ProgramCodeInput(p, 8, 0xa, 7);
+    ProgramCodeInput(p, 2, 5, 8);
+    mcSHOW_DBG_MSG3(("Buffer sensitivity decrease1: TMRS enter -> 000 -> 390 -> 120 -> 8A7 -> 258\n"));
+
+    #elif SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER == 2
+    //Buffer sensitivity decrease2
+    //test 3. TMRS enter -> 000 -> 390 -> 120 -> 803
+    ProgramModeEnter(p);
+    ProgramCodeInput(p, 0, 0, 0);
+    ProgramCodeInput(p, 3, 9, 0);
+    ProgramCodeInput(p, 1, 2, 0);
+    ProgramCodeInput(p, 8, 0, 3);
+    ProgramCodeInput(p, 2, 5, 8);
+    mcSHOW_DBG_MSG3(("Buffer sensitivity decrease1: TMRS enter -> 000 -> 390 -> 120 -> 803 -> 258\n"));
+
+    #elif SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER == 3
+    //2014 + 2863
+    //test 4.TMRS enter -> 000 -> 390 -> 120 -> 014 -> 863
+    ProgramModeEnter(p);
+    ProgramCodeInput(p, 0, 0, 0);
+    ProgramCodeInput(p, 3, 9, 0);
+    ProgramCodeInput(p, 1, 2, 0);
+    ProgramCodeInput(p, 0, 1, 4);
+    ProgramCodeInput(p, 8, 6, 3);
+    ProgramCodeInput(p, 2, 5, 8);
+    mcSHOW_DBG_MSG3(("2014 + 2863: test 4.TMRS enter -> 000 -> 390 -> 120 -> 014 -> 863 -> 258\n"));
+
+    #elif SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER == 4
+    //252A
+    //test 5. TMRS enter -> 000 -> 390 -> 120 -> 52A
+    ProgramModeEnter(p);
+    ProgramCodeInput(p, 0, 0, 0);
+    ProgramCodeInput(p, 3, 9, 0);
+    ProgramCodeInput(p, 1, 2, 0);
+    ProgramCodeInput(p, 5, 2, 0xa);
+    ProgramCodeInput(p, 2, 5, 8);
+    mcSHOW_DBG_MSG3(("252A: test 5. TMRS enter -> 000 -> 390 -> 120 -> 52A -> 258\n"));
+
+    #elif SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER == 5
+    mcSHOW_DBG_MSG3(("Trigger Samsung Test mode after 5 sec\n"));
+    mcDELAY_MS(5000);
+    while(1)
+    {
+        ProgramModeEnter(p);
+    }
+
+    #else
+    //test 1. TMRS enter -> 000 -> 390 -> 021
+    ProgramModeEnter(p);
+    ProgramCodeInput(p, 0, 0, 0);
+    ProgramCodeInput(p, 3, 9, 0);
+    ProgramCodeInput(p, 0, 2, 1);
+    ProgramCodeInput(p, 2, 5, 8);
+    mcSHOW_DBG_MSG3(("Buffer sensitivity decrease1: TMRS enter -> 000 -> 390 -> 021\n"));
+    #endif
+}
+#endif
+
+#if 0
+void Hynix_Test_Mode(DRAMC_CTX_T *p)
+{
+#if MRW_CHECK_ONLY
+    mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+#endif
+
+    DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xb8);
+    DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xe8);
+    DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0x98);
+    DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xbf);
+    DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xef);
+    DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0x9f);
+    DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xb9);
+    DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xe9);
+    DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0x99);
+    DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xd8);
+    DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0x88);
+    DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xa3);
+    DramcModeRegWriteByRank(p, u1GetRank(p), 9, 0xe0);
+}
+#endif
+
+#if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION
+void DramcRunTimeShmooRG_BackupRestore(DRAMC_CTX_T *p)
+{
+    U8 channel_idx, channel_backup;
+    U32 ii, u4RgBackupNum, *u4RG_Backup = 0;
+
+    channel_backup = vGetPHY2ChannelMapping(p);
+
+    for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
+    {
+        vSetPHY2ChannelMapping(p, channel_idx);
+
+        U32 u4RegBackupAddress[] =
+        {
+            // Rx shmoo backup RG
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ5)),  //RX Vref
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ5)),  //RX Vref
+            //RK0
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0)),  //RX DQ Delay
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY1)),  //RX DQ Delay
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY2)),  //RX DQ Delay
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY3)),  //RX DQ Delay
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4)),  //RX DQM Delay
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5)),  //RX DQS Delay
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0)),  //RX DQ Delay
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY1)),  //RX DQ Delay
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY2)),  //RX DQ Delay
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY3)),  //RX DQ Delay
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4)),  //RX DQM Delay
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5)),  //RX DQS Delay
+            //RK1
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY1+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY2+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY3+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY1+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY2+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY3+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5+DDRPHY_AO_RANK_OFFSET)),
+
+
+            // Tx shmoo backup RG
+            //RK0
+            (DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI)),  //TX tracking DQ PI Delay
+            (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0)),  //TX DQ MCK Delay
+            (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1)),  //TX DQM MCK Delay
+            (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2)),  //TX DQ UI Delay
+            (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3)),  //TX DQM UI Delay
+            (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL1)),  //TX Tracking Source DQ
+            (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL2)),  //TX Tracking Target DQ
+            (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL5)),  //TX Tracking Target DQM
+
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0)),  //TX DQ per bit delay cell bit0~3
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1)),  //TX DQ per bit delay cell bit4~7
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0)),  //TX DQ per bit delay cell bit8~11
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1)),  //TX DQ per bit delay cell bit12~15
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3)),  //TX DQM WCK WCK_B delay cell
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3)),  //TX DQM WCK WCK_B delay cell
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)),  //TX DQ WCK PI Delay (TX Calibration)
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)),  //TX DQ WCK PI Delay (TX Calibration)
+            //(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0)),  //CA CLK Delay
+
+            //RK1
+            (DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI+DRAMC_REG_AO_RANK_OFFSET )),
+            (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0+DRAMC_REG_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1+DRAMC_REG_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2+DRAMC_REG_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3+DRAMC_REG_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL1+DRAMC_REG_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL2+DRAMC_REG_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL5+DRAMC_REG_AO_RANK_OFFSET)),
+
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0+DDRPHY_AO_RANK_OFFSET)),
+            (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0+DDRPHY_AO_RANK_OFFSET)),
+            //(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0+DDRPHY_AO_RANK_OFFSET)),
+        };
+        u4RgBackupNum = sizeof(u4RegBackupAddress) >> 2;
+        u4RG_Backup = (U32*)(p->pSavetimeData->u4RG_Backup[channel_idx]);
+
+        for (ii = 0; ii < u4RgBackupNum; ii++)
+        {
+            if (ii >= RUNTIME_SHMOO_RG_BACKUP_NUM)
+            {
+                mcSHOW_DBG_MSG(("\nRuntime Shmoo Backup/Restore buffer(%d) empty!!\n", RUNTIME_SHMOO_RG_BACKUP_NUM));
+                while (1);
+            }
+            if (u1IsLP4Family(p->dram_type) && (p->femmc_Ready == 0))
+            {
+                *(U32*)(u4RG_Backup + ii) = u4IO32Read4B(u4RegBackupAddress[ii]);
+                mcSHOW_DBG_MSG(("=== run time shmoo backup : *(U32*)(0x%x) = 0x%x\n", u4RegBackupAddress[ii], *(U32*)(u4RG_Backup + ii)));
+            }
+            else
+            {
+                vIO32Write4B(u4RegBackupAddress[ii], *(U32*)(u4RG_Backup + ii));
+                mcSHOW_DBG_MSG(("=== run time shmoo restore: *(U32*)(0x%x) = 0x%x\n", u4RegBackupAddress[ii], *(U32*)(u4RG_Backup + ii)));
+            }
+        }
+    }
+    vSetPHY2ChannelMapping(p, channel_backup);
+
+    //DramcRegDump(p);//for run time Tx eye scan RG check
+}
+#endif
+
+#if VERIFY_CKE_PWR_DOWN_FLOW
+void CKEFixOnOff_dbg(DRAMC_CTX_T *p, U8 u1RankIdx, CKE_FIX_OPTION option, CHANNEL_RANK_SEL_T WriteChannelNUM)
+{
+    U8 u1CKEOn, u1CKEOff, u1setChannel, u1BackupChannel;
+
+    if (option == CKE_DYNAMIC) //if CKE is dynamic, set both CKE fix On and Off as 0
+    {                          //After CKE FIX on/off, CKE should be returned to dynamic (control by HW)
+        u1CKEOn = u1CKEOff = 0;
+    }
+    else //if CKE fix on is set as 1, CKE fix off should also be set as 0; vice versa
+    {
+        u1CKEOn = option;
+        u1CKEOff = (1 - option);
+    }
+
+    if (WriteChannelNUM == TO_ALL_CHANNEL) //write register to all channel
+    {
+        if((u1RankIdx == RANK_0)||(u1RankIdx == TO_ALL_RANK))
+        {
+            vIO32WriteFldMulti_All(DRAMC_REG_DCM_CTRL0, P_Fld(u1CKEOff, DCM_CTRL0_DBG_CKEFIXOFF)
+                                                    | P_Fld(u1CKEOn, DCM_CTRL0_DBG_CKEFIXON));
+        }
+
+        if(u1RankIdx == RANK_1||((u1RankIdx == TO_ALL_RANK) && (p->support_rank_num == RANK_DUAL)))
+        {
+            vIO32WriteFldMulti_All(DRAMC_REG_DCM_CTRL0, P_Fld(u1CKEOff, DCM_CTRL0_DBG_CKE1FIXOFF)
+                                                    | P_Fld(u1CKEOn, DCM_CTRL0_DBG_CKE1FIXON));
+        }
+    }
+    else
+    {
+        if((u1RankIdx == RANK_0) || (u1RankIdx == TO_ALL_RANK))
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DCM_CTRL0), P_Fld(u1CKEOff, DCM_CTRL0_DBG_CKEFIXOFF)
+                                                                | P_Fld(u1CKEOn, DCM_CTRL0_DBG_CKEFIXON));
+        }
+
+        if((u1RankIdx == RANK_1) ||((u1RankIdx == TO_ALL_RANK) && (p->support_rank_num == RANK_DUAL)))
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DCM_CTRL0), P_Fld(u1CKEOff, DCM_CTRL0_DBG_CKE1FIXOFF)
+                                                                | P_Fld(u1CKEOn, DCM_CTRL0_DBG_CKE1FIXON));
+        }
+    }
+}
+
+void DramcModeRegWrite_DcmOff(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Value)
+{
+    U32 u4register_dcm;
+    mcSHOW_DBG_MSG3(("### Write_lewis ###\n"));
+
+    u4register_dcm = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL));
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_MIOCKCTRLOFF);/* MIOCKCTRLOFF = 1 */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_DCMEN2);/* DCMEN2 = 0 */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_PHYCLKDYNGEN);/* PHYCLKDYNGEN = 0 */
+
+    DramcModeRegWrite_111(p, u1MRIdx, u1Value);
+
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4register_dcm); //restore DCM setting
+}
+#endif
+
+
+#if 0
+void Get_TA2_ST(DRAMC_CTX_T *p)
+{
+    U32 u4Value = 0;
+
+    u4Value = u4IO32Read4B(DRAMC_REG_TESTRPT);
+    mcSHOW_DBG_MSG(("DRAMC_REG_TESTRPT: 0x%x \n", u4Value));
+}
+
+void Get_TA2_ErrCnt(DRAMC_CTX_T *p)
+{
+    U32 u4Value = 0xffffffff;
+    DRAM_CHANNEL_T channelIdx;
+    DRAM_CHANNEL_T bkchannel = p->channel;
+
+    for(channelIdx=CHANNEL_A; channelIdx<(p->support_channel_num); channelIdx++)
+    {
+        vSetPHY2ChannelMapping(p, channelIdx);
+        mcSHOW_DBG_MSG(("CH[%d]\n", channelIdx));
+
+        u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_FLAG0));
+        mcSHOW_DBG_MSG(("flag 148:0x%x ", u4Value));
+
+        u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_FLAG1));
+        mcSHOW_DBG_MSG(("flag 14C:0x%x\n", u4Value));
+
+        {
+            //Choose which Byte of TA2 error count
+            //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), iByte, TEST2_A3_ERRFLAG_BYTE_SEL);
+
+            //Byte by TEST2_A3_ERRFLAG_BYTE_SEL
+            u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT1));
+            mcSHOW_DBG_MSG(("150:0x%x ", u4Value));
+
+            u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT2));
+            mcSHOW_DBG_MSG(("154:0x%x ", u4Value));
+
+            u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT3));
+            mcSHOW_DBG_MSG(("158:0x%x ", u4Value));
+
+            u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT4));
+            mcSHOW_DBG_MSG(("15C:0x%x ", u4Value));
+
+            u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT5));
+            mcSHOW_DBG_MSG(("160:0x%x ", u4Value));
+
+            u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT6));
+            mcSHOW_DBG_MSG(("164:0x%x ", u4Value));
+
+            u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT7));
+            mcSHOW_DBG_MSG(("168:0x%x ", u4Value));
+
+            u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT8));
+            mcSHOW_DBG_MSG(("16C:0x%x\n", u4Value));
+        }
+    }
+    vSetPHY2ChannelMapping(p, bkchannel);
+}
+
+void Modify_TX_Delay_Cell(DRAMC_CTX_T *p, int i)
+{
+    U16 u2DelayCellOfst[16] = {0};
+    U32 u4value = (i<8) ? 0 : 1;
+
+    if(i<16)
+    {
+        u2DelayCellOfst[i] = 0xffff;
+    }
+    else
+    {
+        mcSHOW_DBG_MSG(("!Error input, hang....\n"));
+        while(1);
+    }
+
+    //Choose which Byte of TA2 error count
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), u4value, TEST2_A3_ERRFLAG_BYTE_SEL);//Should set before TA2 trigger
+    mcSHOW_DBG_MSG(("********** Modify_TX_Delay_Cell %d **********\n", i));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0),
+               P_Fld(u2DelayCellOfst[3], SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)
+             | P_Fld(u2DelayCellOfst[2], SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0)
+             | P_Fld(u2DelayCellOfst[1], SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0)
+             | P_Fld(u2DelayCellOfst[0], SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0));
+     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1),
+               P_Fld(u2DelayCellOfst[7], SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)
+             | P_Fld(u2DelayCellOfst[6], SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0)
+             | P_Fld(u2DelayCellOfst[5], SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0)
+             | P_Fld(u2DelayCellOfst[4], SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0));
+     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0),
+               P_Fld(u2DelayCellOfst[11], SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)
+             | P_Fld(u2DelayCellOfst[10], SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1)
+             | P_Fld(u2DelayCellOfst[9], SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1)
+             | P_Fld(u2DelayCellOfst[8], SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1));
+     vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1),
+               P_Fld(u2DelayCellOfst[15], SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)
+             | P_Fld(u2DelayCellOfst[14], SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1)
+             | P_Fld(u2DelayCellOfst[13], SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1)
+             | P_Fld(u2DelayCellOfst[12], SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1));
+
+    //Read_TX_Delay_Cell(p);
+
+    return;
+}
+#endif
+
+#if 0//1. Test2agent R/F fail flag; Test agent compare error counter
+void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)
+{
+    int i=0;
+    U32 u4BackupDQSOSCENDIS = 0;
+    U8 u1ShuLevel = 0;
+    U8 channelIdx, channelBak;
+    U8 rankIdx, rankBak;
+    U32 u4RegBackupAddress[] =
+    {
+        (DRAMC_REG_HMR4),
+        (DRAMC_REG_DQSOSCR),
+        (DRAMC_REG_DUMMY_RD),
+#if CHANNEL_NUM > 1
+        (DRAMC_REG_HMR4+SHIFT_TO_CHB_ADDR),
+        (DRAMC_REG_DQSOSCR+SHIFT_TO_CHB_ADDR),
+        (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHB_ADDR),
+#endif
+#if CHANNEL_NUM > 2
+        (DRAMC_REG_HMR4+SHIFT_TO_CHC_ADDR),
+        (DRAMC_REG_DQSOSCR+SHIFT_TO_CHC_ADDR),
+        (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHC_ADDR),
+        (DRAMC_REG_HMR4+SHIFT_TO_CHD_ADDR),
+        (DRAMC_REG_DQSOSCR+SHIFT_TO_CHD_ADDR),
+        (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHD_ADDR),
+#endif
+    };
+
+#ifdef FAKE_ENGINE_STRESS
+    if(u1IsLP4Family(p->dram_type))
+    {
+        Fake_Engine_Presetting(p, 0);
+    }
+#endif
+
+    //DramcEngine2SetPat(p, TEST_XTALK_PATTERN, p->support_rank_num - 1, 0);//bug only one channel
+    TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_OFF);
+    do {
+        while(u1StopMiniStress){mcDELAY_MS(1000);}
+
+#ifdef TA2_STRESS
+        // HW mode: RKSEL=4, RWOFOEN = from 0 to 1
+        //@Darren, If single rank RWOFOEN = 1 (always) and enable tx tracking is available.
+
+        TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_HW);
+        TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W
+#endif
+
+#ifdef FAKE_ENGINE_STRESS
+        if(u1IsLP4Family(p->dram_type))
+        {
+            static U8 trans_type = W;
+            Do_Memory_Test_Fake_Engine_Presetting(p, (trans_type++) % 3);
+        }
+#endif
+        Get_TA2_ErrCnt(p);
+
+#ifdef TA2_STRESS
+        TA2_Test_Run_Time_HW_Status(p);//Check TA2 status
+#endif
+
+        //Error inject
+        vSetPHY2ChannelMapping(p, (i++) % p->support_channel_num);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \
+                                       P_Fld(7, SHURK_SELPH_DQ0_TXDLY_DQ0)) //MCK
+        //vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2),
+        //                         P_Fld(6, SHURK_SELPH_DQ2_DLY_DQ0)); //UI
+
+        //vSetRank(p, RANK_1);
+        //Modify_TX_Delay_Cell(p, (i++)%16); //Delay cell
+        //vSetRank(p, RANK_0);
+    } while(1);
+    return;
+}
+#endif
+
+#if 0 //2. TA2 R/W with identify RID/AID
+void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)
+{
+    U32 u4BackupDQSOSCENDIS = 0;
+    U8 u1ShuLevel = 0;
+    U8 channelIdx, channelBak;
+    U8 rankIdx, rankBak;
+    U32 u4RegBackupAddress[] =
+    {
+        (DRAMC_REG_HMR4),
+        (DRAMC_REG_DQSOSCR),
+        (DRAMC_REG_DUMMY_RD),
+#if CHANNEL_NUM > 1
+        (DRAMC_REG_HMR4+SHIFT_TO_CHB_ADDR),
+        (DRAMC_REG_DQSOSCR+SHIFT_TO_CHB_ADDR),
+        (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHB_ADDR),
+#endif
+#if CHANNEL_NUM > 2
+        (DRAMC_REG_HMR4+SHIFT_TO_CHC_ADDR),
+        (DRAMC_REG_DQSOSCR+SHIFT_TO_CHC_ADDR),
+        (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHC_ADDR),
+        (DRAMC_REG_HMR4+SHIFT_TO_CHD_ADDR),
+        (DRAMC_REG_DQSOSCR+SHIFT_TO_CHD_ADDR),
+        (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHD_ADDR),
+#endif
+    };
+
+#ifdef FAKE_ENGINE_STRESS
+    if(u1IsLP4Family(p->dram_type))
+    {
+        Fake_Engine_Presetting(p, 0);
+    }
+#endif
+
+    TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_OFF);//Use worst SI
+
+    do {
+        while(u1StopMiniStress){mcDELAY_MS(1000);}
+
+#ifdef TA2_STRESS
+        if (p->support_rank_num==RANK_DUAL)
+        {
+            DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
+
+            //Disable MR4 MR18/MR19, TxHWTracking, Dummy RD before reset
+            vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 0x1, HMR4_REFRDIS); //MR4 Disable
+            u1ShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_MISC_DVFSCTL, MISC_DVFSCTL_R_OTHER_SHU_GP);
+            u4BackupDQSOSCENDIS = u4IO32Read4B(DRAMC_REG_SHU_DQSOSC_SET0 + (SHU_GRP_DRAMC_OFFSET * u1ShuLevel));
+            vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS);  //MR18, MR19 Disable
+            vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0+(SHU_GRP_DRAMC_OFFSET*u1ShuLevel), 0x1, SHU_DQSOSC_SET0_DQSOSCENDIS);
+            vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN)
+                                                     | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN)
+                                                     | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN)
+                                                     | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG));
+            // XRT mode: RKSEL=3, RWOFOEN = from 1 to 0
+            //TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_ON);
+            TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_XRT); //enhance XRT R2R W2W test, TEST2_2_TEST2_OFF=0x400
+            TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W
+            TA2_Test_Run_Time_HW_Status(p);//Check TA2 status
+        }
+#endif
+
+#ifdef TA2_STRESS
+        // HW mode: RKSEL=4, RWOFOEN = from 0 to 1
+        //@Darren, If single rank RWOFOEN = 1 (always) and enable tx tracking is available.
+        //TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_ON);
+        TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_HW);
+        //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x10, TEST2_A2_TEST2_OFF);//TODO: Need to find out the reason
+
+
+        if (p->support_rank_num==RANK_DUAL)
+        {
+            //@Darren, Fixed TA2 overnight stress r/w fail (Don't enable tx tracking when RWOFOEN=0)
+            vIO32Write4B_All(DRAMC_REG_SHU_DQSOSC_SET0+(SHU_GRP_DRAMC_OFFSET*u1ShuLevel), u4BackupDQSOSCENDIS);
+            DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
+        }
+        TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W
+#endif
+
+#ifdef FAKE_ENGINE_STRESS
+        if(u1IsLP4Family(p->dram_type))
+        {
+            //static U8 trans_type = W;
+            //Do_Memory_Test_Fake_Engine_Presetting(p, (trans_type++) % 2);
+            static U8 trans_type = W;
+            Do_Memory_Test_Fake_Engine_Presetting(p, (trans_type++) % 3);
+            //Do_Memory_Test_Fake_Engine_Presetting(p, W);
+        }
+#endif
+
+#if (DRAMC_DFS_MODE != 3)
+        DFSTestProgram(p, 0); // Should open after DVFS is ready
+#else
+        GetPhyPllFrequency(p); // for DPM PST mode
+#endif
+
+#ifdef TA2_STRESS
+        TA2_Test_Run_Time_HW_Status(p);//Check TA2 status
+#endif
+
+#ifdef FAKE_ENGINE_STRESS
+        if(u1IsLP4Family(p->dram_type))
+        {
+            Disable_Fake_Engine();
+        }
+#endif
+
+#ifdef ENABLE_SW_RUN_TIME_ZQ_WA
+        DramcRunTimeSWZQ(p);
+#endif
+
+        static int cnt=0;
+        //if ((++cnt&0x7F)==0)
+        if (1)
+        {
+            MR_periodic_check(p);
+#ifdef COMPLEX_STRESS
+            int s4value, num;
+            U32 ii, addr[] = {
+                0x40024000,
+                0x56000000,
+                0x80000000,
+            };
+            num = sizeof(addr)>>2;
+            for(ii=0;ii<(U32)num;ii++)
+            {
+                s4value = dramc_complex_mem_test (addr[ii], 0x20000);
+                mcSHOW_DBG_MSG(("complex R/W mem 0x%x test %s: %d\n",addr[ii],s4value?"fail":"pass",-s4value));
+            }
+#endif
+        }
+
+
+#if ENABLE_SW_TX_TRACKING
+        channelBak = vGetPHY2ChannelMapping(p);
+        rankBak = u1GetRank(p);
+        for(channelIdx=CHANNEL_A; channelIdx<(p->support_channel_num); channelIdx++)
+        {
+            vSetPHY2ChannelMapping(p, channelIdx);
+            DramcSWTxTracking(p);
+        }
+        vSetRank(p, rankBak);
+        vSetPHY2ChannelMapping(p, channelBak);
+#endif
+        //DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
+    } while(1);
+    return;
+
+}
+#endif
+
+#if 0 //3. Loop mode (loop time 2^n/ never end/error break)
+void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)
+{
+    int i=0;
+
+#ifdef FAKE_ENGINE_STRESS
+    if(u1IsLP4Family(p->dram_type))
+    {
+        Fake_Engine_Presetting(p, 0);
+    }
+#endif
+
+    TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_OFF);
+    TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_HW);
+
+    vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, 1, TEST2_A0_TA2_LOOP_EN);
+    vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, 1, TEST2_A0_LOOP_NV_END);
+    vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, 1, TEST2_A0_ERR_BREAK_EN);
+    TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W
+    do {
+        while(u1StopMiniStress){mcDELAY_MS(1000);}
+
+#ifdef FAKE_ENGINE_STRESS
+        if(u1IsLP4Family(p->dram_type))
+        {
+            static U8 trans_type = W;
+            Do_Memory_Test_Fake_Engine_Presetting(p, (trans_type++) % 3);
+        }
+#endif
+        //Get_TA2_ErrCnt(p);
+        Get_TA2_ST(p);
+
+        //Error inject
+        if(i==20)
+        {
+            mcSHOW_DBG_MSG(("!!! Error Injection in CHA\n"));
+
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \
+                                       P_Fld(7, SHURK_SELPH_DQ0_TXDLY_DQ0)) //MCK
+        }
+        i++;
+    } while(1);
+    return;
+}
+#endif
+
+#if 0 //pst mode
+typedef enum
+{
+    SIDLE_SR_S1_S0 = 0,
+    SIDLE_SR_S1,
+} ETT_STRESS_LPS;
+void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)//Use the best effort of HW, since TA2 could compare data
+{
+    U32 u4BackupDQSOSCENDIS = 0;
+    U8 u1ShuLevel = 0;
+    bool bTa2_stress_enable = FALSE;
+    ETT_STRESS_LPS bLowPwrState = SIDLE_SR_S1_S0;
+    int iTestCnt = 0;
+
+    U32 u4RegBackupAddress[] =
+    {
+        (DRAMC_REG_HMR4),
+        (DRAMC_REG_DQSOSCR),
+        (DRAMC_REG_DUMMY_RD),
+#if CHANNEL_NUM > 1
+        (DRAMC_REG_HMR4+SHIFT_TO_CHB_ADDR),
+        (DRAMC_REG_DQSOSCR+SHIFT_TO_CHB_ADDR),
+        (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHB_ADDR),
+#endif
+#if CHANNEL_NUM > 2
+        (DRAMC_REG_HMR4+SHIFT_TO_CHC_ADDR),
+        (DRAMC_REG_DQSOSCR+SHIFT_TO_CHC_ADDR),
+        (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHC_ADDR),
+        (DRAMC_REG_HMR4+SHIFT_TO_CHD_ADDR),
+        (DRAMC_REG_DQSOSCR+SHIFT_TO_CHD_ADDR),
+        (DRAMC_REG_DUMMY_RD+SHIFT_TO_CHD_ADDR),
+#endif
+    };
+
+#ifdef FAKE_ENGINE_STRESS
+    if(u1IsLP4Family(p->dram_type))
+    {
+        Fake_Engine_Presetting(p, 0);
+    }
+#endif
+
+    do {
+        while(u1StopMiniStress){mcDELAY_MS(1000);}
+#if 1 //low power OK
+        if(iTestCnt % 10 == 0)
+        {
+            bLowPwrState = (bLowPwrState == SIDLE_SR_S1_S0) ? (SIDLE_SR_S1) : (SIDLE_SR_S1_S0);
+
+            mcSHOW_DBG_MSG(("*** Stop delay then start\n"));
+            Reg_Sync_Writel(0x10940020, 0x00000000);// GPR0  //S1, SR, idle
+            Reg_Sync_Writel(0x10A40020, 0x00000000);// GPR0
+
+            Reg_Sync_Writel(0x10940028, 0x00000003);// GPR2
+            Reg_Sync_Writel(0x10A40028, 0x00000003);// GPR2
+
+            Reg_Sync_Writel(0x109400A0, 1);//Tigger MSG BOX to stop low power flow
+            Reg_Sync_Writel(0x10A400A0, 1);//Tigger MSG BOX to stop low power flow
+
+            mcDELAY_MS(100);
+
+            if(bLowPwrState == SIDLE_SR_S1_S0)
+            {
+                mcSHOW_DBG_MSG(("*** SIDLE_SR_S1_S0\n"));
+
+                Reg_Sync_Writel(0x10940020, 0x00010203);// GPR0  //S0, S1, SR, idle
+                Reg_Sync_Writel(0x10A40020, 0x00010203);// GPR0
+
+                Reg_Sync_Writel(0x10940028, 0x80000004);// GPR2
+                Reg_Sync_Writel(0x10A40028, 0x80000004);// GPR2
+                bTa2_stress_enable = 0;
+            }
+            else
+            {
+                mcSHOW_DBG_MSG(("*** SIDLE_SR_S1 stop then start\n"));
+
+                Reg_Sync_Writel(0x10940020, 0x00010200);// GPR0  //S1, SR, idle
+                Reg_Sync_Writel(0x10A40020, 0x00010200);// GPR0
+
+                Reg_Sync_Writel(0x10940028, 0x80000003);// GPR2
+                Reg_Sync_Writel(0x10A40028, 0x80000003);// GPR2
+                bTa2_stress_enable = 1;
+            }
+            Reg_Sync_Writel(0x109400A0, 1);//Tigger MSG BOX
+            Reg_Sync_Writel(0x10A400A0, 1);//Tigger MSG BOX
+        }
+        iTestCnt++;
+#endif
+#if 0 //mix ==> bug
+        if(iTestCnt % 10 == 0)
+        {
+            bLowPwrState = (bLowPwrState == SIDLE_SR_S1_S0) ? (SIDLE_SR_S1) : (SIDLE_SR_S1_S0);
+
+            mcSHOW_DBG_MSG(("*** Stop delay then start\n"));
+            Reg_Sync_Writel(0x10940020, 0x00000000);// GPR0  //S1, SR, idle
+            Reg_Sync_Writel(0x10A40020, 0x00000000);// GPR0
+
+            Reg_Sync_Writel(0x10940028, 0x00000003);// GPR2
+            Reg_Sync_Writel(0x10A40028, 0x00000003);// GPR2
+
+            Reg_Sync_Writel(0x109400A0, 1);//Tigger MSG BOX to stop low power flow
+            Reg_Sync_Writel(0x10A400A0, 1);//Tigger MSG BOX to stop low power flow
+
+            if(bLowPwrState == SIDLE_SR_S1_S0)
+            {
+                mcSHOW_DBG_MSG(("*** SIDLE_SR_S1_S0\n"));
+
+                Reg_Sync_Writel(0x10940020, 0x00010300);// GPR0  //S0 -> S1 -> SR -> idle
+                Reg_Sync_Writel(0x10A40020, 0x00010300);// GPR0
+
+                Reg_Sync_Writel(0x10940024, 0x13121110);// GPR1  //->SHU0 -> SHU1 -> SHU2 -> SHU3
+                Reg_Sync_Writel(0x10A40024, 0x13121110);// GPR1
+
+                Reg_Sync_Writel(0x10940028, 0x80000008);// GPR2
+                Reg_Sync_Writel(0x10A40028, 0x80000008);// GPR2
+                bTa2_stress_enable = 0;
+            }
+            else
+            {
+                mcSHOW_DBG_MSG(("*** SIDLE_SR_S1\n"));
+
+                Reg_Sync_Writel(0x10940020, 0x00010200);// GPR0  //S1 -> SR -> idle
+                Reg_Sync_Writel(0x10A40020, 0x00010200);// GPR0
+
+                Reg_Sync_Writel(0x10940024, 0x13121110);// GPR1  //->SHU0 -> SHU1 -> SHU2 -> SHU3
+                Reg_Sync_Writel(0x10A40024, 0x13121110);// GPR1
+
+                Reg_Sync_Writel(0x10940028, 0x80000008);// GPR2
+                Reg_Sync_Writel(0x10A40028, 0x80000008);// GPR2
+                bTa2_stress_enable = 1;
+            }
+            Reg_Sync_Writel(0x109400A0, 1);//Tigger MSG BOX
+            Reg_Sync_Writel(0x10A400A0, 1);//Tigger MSG BOX
+        }
+        iTestCnt++;
+#endif
+
+
+#if 0 //DVFS
+        if(iTestCnt % 10 == 0)
+        {
+            bLowPwrState = (bLowPwrState == SIDLE_SR_S1_S0) ? (SIDLE_SR_S1) : (SIDLE_SR_S1_S0);
+            if(bLowPwrState == SIDLE_SR_S1_S0)
+            {
+                mcSHOW_DBG_MSG(("*** SIDLE_SR_S1_S0\n"));
+
+                Reg_Sync_Writel(0x10940020, 0x12111000);// GPR0  //all SHU
+                Reg_Sync_Writel(0x10A40020, 0x12111000);// GPR0
+
+                Reg_Sync_Writel(0x10940024, 0x16151413);// GPR1
+                Reg_Sync_Writel(0x10A40024, 0x16151413);// GPR1
+
+                Reg_Sync_Writel(0x10940028, 0x80000008);// GPR2
+                Reg_Sync_Writel(0x10A40028, 0x80000008);// GPR2
+                bTa2_stress_enable = 0;
+            }
+            else
+            {
+                mcSHOW_DBG_MSG(("*** SIDLE_SR_S1\n"));
+
+                Reg_Sync_Writel(0x10940020, 0x12111000);// GPR0  //all SHU
+                Reg_Sync_Writel(0x10A40020, 0x12111000);// GPR0
+
+                Reg_Sync_Writel(0x10940024, 0x16151413);// GPR1
+                Reg_Sync_Writel(0x10A40024, 0x16151413);// GPR1
+
+                Reg_Sync_Writel(0x10940028, 0x80000008);// GPR2
+                Reg_Sync_Writel(0x10A40028, 0x80000008);// GPR2
+                bTa2_stress_enable = 1;
+            }
+            Reg_Sync_Writel(0x109400A0, 1);//Tigger MSG BOX
+            Reg_Sync_Writel(0x10A400A0, 1);//Tigger MSG BOX
+        }
+        iTestCnt++;
+#endif
+
+
+
+#ifdef TA2_STRESS
+if(bTa2_stress_enable)
+{
+        if (p->support_rank_num==RANK_DUAL)
+        {
+            DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
+
+            //Disable MR4 MR18/MR19, TxHWTracking, Dummy RD before reset
+            vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 0x1, HMR4_REFRDIS); //MR4 Disable
+            u1ShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_MISC_DVFSCTL, MISC_DVFSCTL_R_OTHER_SHU_GP);
+            u4BackupDQSOSCENDIS = u4IO32Read4B(DRAMC_REG_SHU_DQSOSC_SET0 + (SHU_GRP_DRAMC_OFFSET * u1ShuLevel));
+            vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS);  //MR18, MR19 Disable
+            vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0+(SHU_GRP_DRAMC_OFFSET*u1ShuLevel), 0x1, SHU_DQSOSC_SET0_DQSOSCENDIS);
+            vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN)
+                                                     | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN)
+                                                     | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN)
+                                                     | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG));
+            // XRT mode: RKSEL=3, RWOFOEN = from 1 to 0
+            TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_ON);
+            TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_XRT); //enhance XRT R2R W2W test, TEST2_2_TEST2_OFF=0x400
+            TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W
+            TA2_Test_Run_Time_HW_Status(p);//Check TA2 status
+        }
+
+
+        // HW mode: RKSEL=4, RWOFOEN = from 0 to 1
+        //@Darren, If single rank RWOFOEN = 1 (always) and enable tx tracking is available.
+        TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_ON);
+        TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_HW);
+        //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x10, TEST2_A2_TEST2_OFF);//TODO: Need to find out the reason
+
+
+        if (p->support_rank_num==RANK_DUAL)
+        {
+            //@Darren, Fixed TA2 overnight stress r/w fail (Don't enable tx tracking when RWOFOEN=0)
+            vIO32Write4B_All(DRAMC_REG_SHU_DQSOSC_SET0+(SHU_GRP_DRAMC_OFFSET*u1ShuLevel), u4BackupDQSOSCENDIS);
+            DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
+        }
+        TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W
+}
+#endif
+
+#ifdef FAKE_ENGINE_STRESS
+        if(u1IsLP4Family(p->dram_type))
+        {
+            //static U8 trans_type = W;
+            //Do_Memory_Test_Fake_Engine_Presetting(p, (trans_type++) % 2);
+            static U8 trans_type = W;
+            Do_Memory_Test_Fake_Engine_Presetting(p, (trans_type++) % 3);
+            //Do_Memory_Test_Fake_Engine_Presetting(p, W);
+        }
+#endif
+
+
+#ifdef TA2_STRESS
+if(bTa2_stress_enable)
+{
+        TA2_Test_Run_Time_HW_Status(p);//Check TA2 status
+}
+#endif
+
+#ifdef FAKE_ENGINE_STRESS
+        if(u1IsLP4Family(p->dram_type))
+        {
+            Disable_Fake_Engine();
+        }
+#endif
+
+        static int cnt=0;
+        //if ((++cnt&0x7F)==0)
+        if (1)
+        {
+            MR_periodic_check(p);
+#ifdef COMPLEX_STRESS
+            int s4value, num;
+            U32 ii, addr[] = {
+                0x40024000,
+                0x56000000,
+                0x80000000,
+            };
+            num = sizeof(addr)>>2;
+            for(ii=0;ii<(U32)num;ii++)
+            {
+                s4value = dramc_complex_mem_test (addr[ii], 0x20000);
+                mcSHOW_DBG_MSG(("[%d]complex R/W mem 0x%x test %s: %d\n",iTestCnt, addr[ii],s4value?"fail":"pass",-s4value));
+            }
+#endif
+        }
+        //DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
+    } while(1);
+    return;
+}
+#endif
+
+//RX
+//if (u1UseTestEngine == PATTERN_TEST_ENGINE)
+//{
+//    U32 u4B0Tatal =0;
+//    U32 u4B1Tatal =0;
+//    mcSHOW_DBG_MSG(("RX window per bit CH[%d] Rank[%d] window size\n", p->channel, p->rank));
+//    for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
+//    {
+//        mcSHOW_DBG_MSG(("DQ[%d] size = %d\n", u1BitIdx, gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx]));
+//        if(u1BitIdx < 8)
+//        {
+//            u4B0Tatal += gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx];
+//        }
+//        else
+//        {
+//            u4B1Tatal += gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx];
+//        }
+//    }
+//    mcSHOW_DBG_MSG(("total rx window size B0: %d B1: %d\n", u4B0Tatal, u4B1Tatal));
+//}
+
+//TX
+//static void TxPrintWidnowInfo(DRAMC_CTX_T *p, PASS_WIN_DATA_T WinPerBitData[])
+//{
+//    U8 u1BitIdx;
+//    U32 u4B0Tatal=0;
+//    U32 u4B1Tatal=0;
+//    for (u1BitIdx = 0; u1BitIdx < 16; u1BitIdx++)
+//    {
+//        if(u1BitIdx < 8)
+//        {
+//            u4B0Tatal += WinPerBitData[u1BitIdx].win_size;
+//        }
+//        else
+//        {
+//            u4B1Tatal += WinPerBitData[u1BitIdx].win_size;
+//        }
+//
+//    }
+//    mcSHOW_DBG_MSG(("\ntotal tx window size B0: %d B1: %d\n", u4B0Tatal, u4B1Tatal));
+//}
+
+//#ifdef ETT_MINI_STRESS_TEST
+#if 0 //Only trigger W once, then R in the loop with TA2 HW mode
+//err |= aTA2_Test_Run_Time_HW_Status(p);/* Compare should use TE_OP_READ_CHECK */
+unsigned int DPMIsAlive(DRAMC_CTX_T *p);
+void Ett_Mini_Strss_Test_DPM(DRAMC_CTX_T *p, int iTestCnt, bool *bTa2_stress_enable);
+
+void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)//Use the best effort of HW, since TA2 could compare data
+{
+    static int sTestCnt = 0;
+    U8 channelIdx, channelBak;
+    U8 rankIdx, rankBak;
+    bool bTa2_stress_enable = TRUE;
+    int err = 0;
+
+#ifdef FAKE_ENGINE_STRESS
+    if(u1IsLP4Family(p->dram_type))
+    {
+        Fake_Engine_Presetting(p, 0);
+    }
+#endif
+
+    TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_OFF);//Assign TEST_WORST_SI_PATTERN
+    TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_HW);
+    TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W
+
+    do {
+        while(u1StopMiniStress){mcDELAY_MS(1000);}
+        mcSHOW_DBG_MSG(("Stress test.................\n"));
+
+#ifdef TA2_STRESS
+        if(bTa2_stress_enable)
+        {
+            if(sTestCnt)//after 2rd times
+            {
+                TA2_Test_Run_Time_HW_Read(p, ENABLE);//TA2 trigger R
+            }
+        }
+#endif
+
+#ifdef FAKE_ENGINE_STRESS
+        if(u1IsLP4Family(p->dram_type))
+        {
+            static U8 trans_type = W;
+            Do_Memory_Test_Fake_Engine_Presetting(p, (trans_type++) % 3);
+        }
+#endif
+
+        DFSTestProgram(p, 0); // Should open after DVFS is ready
+
+#ifdef TA2_STRESS
+        if(bTa2_stress_enable)
+        {
+            err |= TA2_Test_Run_Time_HW_Status(p);/* Compare should use TE_OP_READ_CHECK */
+        }
+#endif
+        sTestCnt ++;
+
+        if (1)
+        {
+            MR_periodic_check(p);
+#ifdef COMPLEX_STRESS
+            int s4value, num;
+            U32 ii, addr[] = {
+                0x40024000,
+                0x56000000,
+                0x80000000,
+            };
+            num = sizeof(addr)>>2;
+            for(ii=0;ii<(U32)num;ii++)
+            {
+                s4value = dramc_complex_mem_test (addr[ii], 0x20000);
+                mcSHOW_DBG_MSG(("complex R/W mem 0x%x test %s: %d\n",addr[ii],s4value?"fail":"pass",-s4value));
+
+                err |= s4value;
+            }
+#endif
+        }
+    } while(1);
+    return;
+}
+#endif
+
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_dv_freq_related.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_dv_freq_related.c
new file mode 100644
index 000000000000..ee5466aeb0ea
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_dv_freq_related.c
@@ -0,0 +1,24832 @@
+
+//#include "svdpi.h"
+//#include "vc_hdrs.h"
+#include "dramc_common.h"
+#include "dramc_int_global.h"
+#include "x_hal_io.h"
+//#include "./dramc_actiming.h"
+#include "dramc_dv_init.h"
+
+
+#if 0
+    #include "./drivers/DRAMC_SUBSYS_config.c"
+    #include "./drivers/ANA_init_config.c"
+    #include "./drivers/DIG_NONSHUF_config.c"
+    #include "./drivers/DRAM_config_collctioin.c"
+    #include "./drivers/LP4_dram_init.c"
+    #include "./drivers/LP5_dram_init.c"
+    #include "./drivers/DIG_SHUF_config.c"
+#endif
+
+#if 0
+void CInit_ConfigFromTBA(void)
+{
+    TbaConfig.dramc_dram_ratio  = 4;
+    TbaConfig.channel           = 0;
+    TbaConfig.dram_type         = 4;
+    TbaConfig.shu_type          = 0;
+    TbaConfig.dram_cbt_mode_RK0 = 1;
+    TbaConfig.dram_cbt_mode_RK1 = 1;
+    TbaConfig.DBI_R_onoff_FSP0  = 0;
+    TbaConfig.DBI_R_onoff_FSP1  = 0;
+    TbaConfig.frequency         = 1600;
+    TbaConfig.voltage_state     = 3;
+    mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: dramc_dram_ratio  = %1d\n", TbaConfig.dramc_dram_ratio));
+    mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: channel           = %1d\n", TbaConfig.channel));
+    mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: dram_type         = %1d\n", TbaConfig.dram_type));
+    mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: shu_type          = %1d\n", TbaConfig.shu_type));
+    mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: dram_cbt_mode_RK0 = %1d\n", TbaConfig.dram_cbt_mode_RK0));
+    mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: dram_cbt_mode_RK1 = %1d\n", TbaConfig.dram_cbt_mode_RK1));
+    mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: DBI_R_onoff_FSP0  = %1d\n", TbaConfig.DBI_R_onoff_FSP0));
+    mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: DBI_R_onoff_FSP1  = %1d\n", TbaConfig.DBI_R_onoff_FSP1));
+    mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: frequency         = %1d\n", TbaConfig.frequency));
+    mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: voltage_state     = %1d\n", TbaConfig.voltage_state));
+
+
+    TbaEnvConfig.TMRRI_way             = 1;
+    TbaEnvConfig.RUNTIMEMRR_way        = 1;
+    TbaEnvConfig.PICG_MODE             = 1;
+    TbaEnvConfig.LP_NEW8X_SEQ_MODE     = 0;
+    TbaEnvConfig.DDR400_OPEN_LOOP_MODE = 0;
+    TbaEnvConfig.RXTRACK_PBYTE_OPT     = 0;
+    TbaEnvConfig.RG_SPM_MODE           = 0;
+    TbaEnvConfig.TX_OE_EXT_OPT         = 0;
+    TbaEnvConfig.PLL_MODE_OPTION       = 1;
+    TbaEnvConfig.TREFBWIG_IGNORE       = 1;
+    TbaEnvConfig.SHUFFLE_LVL_MODE      = 1;
+    TbaEnvConfig.SELPH_MODE            = 1;
+    TbaEnvConfig.TRACK_UP_MODE         = 1;
+    TbaEnvConfig.VALID_LAT_VALUE       = 0;
+    TbaEnvConfig.NEW_RANK_MODE         = 1;
+    TbaEnvConfig.WPST1P5T_OPT          = 1;
+    TbaEnvConfig.TXP_WORKAROUND_OPT    = 0;
+    TbaEnvConfig.DLL_IDLE_MODE         = 1;
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: TMRRI_way             = %1d\n", TbaEnvConfig.TMRRI_way));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: RUNTIMEMRR_way        = %1d\n", TbaEnvConfig.RUNTIMEMRR_way));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: PICG_MODE             = %1d\n", TbaEnvConfig.PICG_MODE));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: LP_NEW8X_SEQ_MODE     = %1d\n", TbaEnvConfig.LP_NEW8X_SEQ_MODE));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: DDR400_OPEN_LOOP_MODE = %1d\n", TbaEnvConfig.DDR400_OPEN_LOOP_MODE));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: RXTRACK_PBYTE_OPT     = %1d\n", TbaEnvConfig.RXTRACK_PBYTE_OPT));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: RG_SPM_MODE           = %1d\n", TbaEnvConfig.RG_SPM_MODE));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: TX_OE_EXT_OPT         = %1d\n", TbaEnvConfig.TX_OE_EXT_OPT));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: PLL_MODE_OPTION       = %1d\n", TbaEnvConfig.PLL_MODE_OPTION));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: TREFBWIG_IGNORE       = %1d\n", TbaEnvConfig.TREFBWIG_IGNORE));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: SHUFFLE_LVL_MODE      = %1d\n", TbaEnvConfig.SHUFFLE_LVL_MODE));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: SELPH_MODE            = %1d\n", TbaEnvConfig.SELPH_MODE));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: TRACK_UP_MODE         = %1d\n", TbaEnvConfig.TRACK_UP_MODE));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: VALID_LAT_VALUE       = %1d\n", TbaEnvConfig.VALID_LAT_VALUE));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: NEW_RANK_MODE         = %1d\n", TbaEnvConfig.NEW_RANK_MODE));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: WPST1P5T_OPT          = %1d\n", TbaEnvConfig.WPST1P5T_OPT));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: TXP_WORKAROUND_OPT    = %1d\n", TbaEnvConfig.TXP_WORKAROUND_OPT));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: DLL_IDLE_MODE         = %1d\n", TbaEnvConfig.DLL_IDLE_MODE));
+
+    TBA_Build_Def.DQSG_TRACK_on = 1;
+    mcSHOW_DBG_MSG(("[TBA_build_def_T] Global: DQSG_TRACK_on = %1d\n", TBA_Build_Def.DQSG_TRACK_on));
+
+
+    TbaEnvDVFSCfg.group_num             = 2;
+    TbaEnvDVFSCfg.LP5BGOTF              = 0;
+    TbaEnvDVFSCfg.LP5BGEN               = 0;
+    TbaEnvDVFSCfg.CAS_MODE              = 3;
+    TbaEnvDVFSCfg.LP5_RDQS_SE_EN        = 0;
+    TbaEnvDVFSCfg.DQSIEN_MODE           = 1;
+    TbaEnvDVFSCfg.freq_group_map_0      = 2;
+    TbaEnvDVFSCfg.freq_group_map_1      = 6;
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: group_num        = %1d\n", TbaEnvDVFSCfg.group_num));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: LP5BGOTF         = %1d\n", TbaEnvDVFSCfg.LP5BGOTF));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: LP5BGEN          = %1d\n", TbaEnvDVFSCfg.LP5BGEN));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: CAS_MODE         = %1d\n", TbaEnvDVFSCfg.CAS_MODE));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: LP5_RDQS_SE_EN   = %1d\n", TbaEnvDVFSCfg.LP5_RDQS_SE_EN));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: DQSIEN_MODE      = %1d\n", TbaEnvDVFSCfg.DQSIEN_MODE));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: freq_group_map_0 = %1d\n", TbaEnvDVFSCfg.freq_group_map_0));
+    mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: freq_group_map_1 = %1d\n", TbaEnvDVFSCfg.freq_group_map_1));
+
+
+    TbaEnvHwFuncCfg.HW_MR4_OPTION_RANDOM             = 1;
+    TbaEnvHwFuncCfg.HW_DMYRD_OPTION_RANDOM           = 1;
+    TbaEnvHwFuncCfg.HW_DQSOSC_OPTION_RANDOM          = 1;
+    TbaEnvHwFuncCfg.HW_ZQ_OPTION_RANDOM              = 1;
+    TbaEnvHwFuncCfg.RX_INPUT_TRACK_OPTION_RANDOM     = 1;
+    TbaEnvHwFuncCfg.DQSG_RUNTIME_DEBUG_OPTION_RANDOM = 1;
+    TbaEnvHwFuncCfg.HW_MR4_EN                        = 1;
+    TbaEnvHwFuncCfg.HW_DMYRD_EN                      = 1;
+    TbaEnvHwFuncCfg.HW_DQSOSC_EN                     = 1;
+    TbaEnvHwFuncCfg.HW_ZQ_EN                         = 1;
+    TbaEnvHwFuncCfg.DQSG_RETRY_EN                    = 0;
+    TbaEnvHwFuncCfg.RX_INPUT_TRACK_EN                = 1;
+    TbaEnvHwFuncCfg.DQSG_RUNTIME_DEBUG_EN            = 1;
+    TbaEnvHwFuncCfg.RDSEL_TRACK_EN                   = 0;
+    TbaEnvHwFuncCfg.DQSG_TRACK_EN                    = 0;
+    mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_MR4_OPTION_RANDOM             = %1d\n", TbaEnvHwFuncCfg.HW_MR4_OPTION_RANDOM));
+    mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_DMYRD_OPTION_RANDOM           = %1d\n", TbaEnvHwFuncCfg.HW_DMYRD_OPTION_RANDOM));
+    mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_DQSOSC_OPTION_RANDOM          = %1d\n", TbaEnvHwFuncCfg.HW_DQSOSC_OPTION_RANDOM));
+    mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_ZQ_OPTION_RANDOM              = %1d\n", TbaEnvHwFuncCfg.HW_ZQ_OPTION_RANDOM));
+    mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: RX_INPUT_TRACK_OPTION_RANDOM     = %1d\n", TbaEnvHwFuncCfg.RX_INPUT_TRACK_OPTION_RANDOM));
+    mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: DQSG_RUNTIME_DEBUG_OPTION_RANDOM = %1d\n", TbaEnvHwFuncCfg.DQSG_RUNTIME_DEBUG_OPTION_RANDOM));
+    mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_MR4_EN                        = %1d\n", TbaEnvHwFuncCfg.HW_MR4_EN));
+    mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_DMYRD_EN                      = %1d\n", TbaEnvHwFuncCfg.HW_DMYRD_EN));
+    mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_DQSOSC_EN                     = %1d\n", TbaEnvHwFuncCfg.HW_DQSOSC_EN));
+    mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_ZQ_EN                         = %1d\n", TbaEnvHwFuncCfg.HW_ZQ_EN));
+    mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: DQSG_RETRY_EN                    = %1d\n", TbaEnvHwFuncCfg.DQSG_RETRY_EN));
+    mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: RX_INPUT_TRACK_EN                = %1d\n", TbaEnvHwFuncCfg.RX_INPUT_TRACK_EN));
+    mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: DQSG_RUNTIME_DEBUG_EN            = %1d\n", TbaEnvHwFuncCfg.DQSG_RUNTIME_DEBUG_EN));
+    mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: RDSEL_TRACK_EN                   = %1d\n", TbaEnvHwFuncCfg.RDSEL_TRACK_EN));
+    mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: DQSG_TRACK_EN                    = %1d\n", TbaEnvHwFuncCfg.DQSG_TRACK_EN));
+
+
+    TbaTestListDef.RandDefaultData_on      = 1;
+    TbaTestListDef.DQS2DQ_TRACK_on         = 1;
+    TbaTestListDef.LPDDR4_EN               = 1;
+    TbaTestListDef.ESL_LOG_GEN             = 1;
+    TbaTestListDef.LP4_X8_on               = 0;
+    TbaTestListDef.LP4_X8_mix_on           = 0; //Jeremy
+    TbaTestListDef.INCLUDE_LP45_COMBO_APHY = 1;
+    TbaTestListDef.LP45_COMBO_APHY_EN      = 1;
+    TbaTestListDef.LPDDR5_EN               = 0;
+    TbaTestListDef.LP3_4_PINMUX_EN         = 0;
+    mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: RandDefaultData_on      = %1d\n", TbaTestListDef.RandDefaultData_on));
+    mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: DQS2DQ_TRACK_on         = %1d\n", TbaTestListDef.DQS2DQ_TRACK_on));
+    mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: LPDDR4_EN               = %1d\n", TbaTestListDef.LPDDR4_EN));
+    mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: ESL_LOG_GEN             = %1d\n", TbaTestListDef.ESL_LOG_GEN));
+    mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: LP4_X8_on               = %1d\n", TbaTestListDef.LP4_X8_on));
+    mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: INCLUDE_LP45_COMBO_APHY = %1d\n", TbaTestListDef.INCLUDE_LP45_COMBO_APHY));
+    mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: LP45_COMBO_APHY_EN      = %1d\n", TbaTestListDef.LP45_COMBO_APHY_EN));
+    mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: LPDDR5_EN               = %1d\n", TbaTestListDef.LPDDR5_EN));
+    mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: LP3_4_PINMUX_EN         = %1d\n", TbaTestListDef.LP3_4_PINMUX_EN));
+
+
+
+    TbaDramcBenchConfig.rank_swap                = 0;
+    TbaDramcBenchConfig.new_uP_spm_mode          = 0;
+    TbaDramcBenchConfig.LP_MTCMOS_CONTROL_SEL    = 0;
+    // CHA, BYTE 0
+    TbaDramcBenchConfig.cha_pinmux_anti_order_0  = 0;
+    TbaDramcBenchConfig.cha_pinmux_anti_order_1  = 1;
+    TbaDramcBenchConfig.cha_pinmux_anti_order_2  = 2;
+    TbaDramcBenchConfig.cha_pinmux_anti_order_3  = 3;
+    TbaDramcBenchConfig.cha_pinmux_anti_order_4  = 4;
+    TbaDramcBenchConfig.cha_pinmux_anti_order_5  = 5;
+    TbaDramcBenchConfig.cha_pinmux_anti_order_6  = 6;
+    TbaDramcBenchConfig.cha_pinmux_anti_order_7  = 7;
+    // CHA, BYTE 1
+    TbaDramcBenchConfig.cha_pinmux_anti_order_8  = 8;
+    TbaDramcBenchConfig.cha_pinmux_anti_order_9  = 9;
+    TbaDramcBenchConfig.cha_pinmux_anti_order_10 = 10;
+    TbaDramcBenchConfig.cha_pinmux_anti_order_11 = 11;
+    TbaDramcBenchConfig.cha_pinmux_anti_order_12 = 12;
+    TbaDramcBenchConfig.cha_pinmux_anti_order_13 = 13;
+    TbaDramcBenchConfig.cha_pinmux_anti_order_14 = 14;
+    TbaDramcBenchConfig.cha_pinmux_anti_order_15 = 15;
+    // CHB, BYTE 0
+    TbaDramcBenchConfig.chb_pinmux_anti_order_0  = 0;
+    TbaDramcBenchConfig.chb_pinmux_anti_order_1  = 1;
+    TbaDramcBenchConfig.chb_pinmux_anti_order_2  = 2;
+    TbaDramcBenchConfig.chb_pinmux_anti_order_3  = 3;
+    TbaDramcBenchConfig.chb_pinmux_anti_order_4  = 4;
+    TbaDramcBenchConfig.chb_pinmux_anti_order_5  = 5;
+    TbaDramcBenchConfig.chb_pinmux_anti_order_6  = 6;
+    TbaDramcBenchConfig.chb_pinmux_anti_order_7  = 7;
+    // CHB, BYTE 1
+    TbaDramcBenchConfig.chb_pinmux_anti_order_8  = 8;
+    TbaDramcBenchConfig.chb_pinmux_anti_order_9  = 9;
+    TbaDramcBenchConfig.chb_pinmux_anti_order_10 = 10;
+    TbaDramcBenchConfig.chb_pinmux_anti_order_11 = 11;
+    TbaDramcBenchConfig.chb_pinmux_anti_order_12 = 12;
+    TbaDramcBenchConfig.chb_pinmux_anti_order_13 = 13;
+    TbaDramcBenchConfig.chb_pinmux_anti_order_14 = 14;
+    TbaDramcBenchConfig.chb_pinmux_anti_order_15 = 15;
+
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: rank_swap                = %1d\n", TbaDramcBenchConfig.rank_swap));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: new_uP_spm_mode          = %1d\n", TbaDramcBenchConfig.new_uP_spm_mode));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: LP_MTCMOS_CONTROL_SEL    = %1d\n", TbaDramcBenchConfig.LP_MTCMOS_CONTROL_SEL));
+    // CHA, BYTE 0
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_0  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_0));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_1  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_1));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_2  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_2));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_3  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_3));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_4  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_4));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_5  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_5));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_6  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_6));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_7  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_7));
+    // CHA BYTE 1
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_8  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_8));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_9  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_9));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_10 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_10));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_11 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_11));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_12 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_12));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_13 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_13));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_14 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_14));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_15 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_15));
+    // CHB, BYTE 0
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_0  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_0));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_1  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_1));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_2  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_2));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_3  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_3));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_4  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_4));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_5  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_5));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_6  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_6));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_7  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_7));
+    // CHB, BYTE 1
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_8  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_8));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_9  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_9));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_10 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_10));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_11 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_11));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_12 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_12));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_13 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_13));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_14 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_14));
+    mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_15 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_15));
+
+}
+#endif
+
+#if BYPASS_CALIBRATION
+#if (FOR_DV_SIMULATION_USED==0)
+void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p)
+{
+    U8 u1RankIdx=0;
+    U8 backup_rank=0;
+
+    backup_rank = p->rank;
+
+    ShiftDQUI_AllRK(p, -1, ALL_BYTES);
+    ShiftDQ_OENUI_AllRK(p, -1, ALL_BYTES);
+    ShiftDQSWCK_UI(p, -1, ALL_BYTES);
+
+    for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+        //CBT
+		DramcCmdUIDelaySetting(p, 0);
+
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0),
+    		P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) |
+    		P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK));
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), 0, SHU_R0_CA_CMD0_RG_ARPI_CS);
+
+        //WL
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), 0x20, SHU_R0_B0_DQ0_ARPI_PBYTE_B0);  //rank0, byte0, DQS delay
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), 0x20, SHU_R0_B1_DQ0_ARPI_PBYTE_B1);  //rank0, byte1, DQS delay
+
+        //Gating
+        if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE))
+        {
+            // normal mode
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+        		P_Fld(11,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+        		P_Fld(0,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) |
+        		P_Fld(15,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0));
+
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+        		P_Fld(11,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+        		P_Fld(0,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) |
+        		P_Fld(15,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1));
+
+            #if GATING_RODT_LATANCY_EN
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+        		P_Fld(0,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+        		P_Fld(0,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) |
+        		P_Fld(0,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0));
+
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+        		P_Fld(0,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+        		P_Fld(0,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) |
+        		P_Fld(0,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1));
+            #endif
+        }
+        else
+        {
+            //mix mode
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+        		P_Fld(15,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+        		P_Fld(1,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) |
+        		P_Fld(3,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0));
+
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+        		P_Fld(15,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+        		P_Fld(1,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) |
+        		P_Fld(3,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1));
+            
+            #if GATING_RODT_LATANCY_EN
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+        		P_Fld(4,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+        		P_Fld(0,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) |
+        		P_Fld(4,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0));
+
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+        		P_Fld(4,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+        		P_Fld(0,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) |
+        		P_Fld(4,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1));
+            #endif
+        }
+        
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY),
+        	8,
+        	SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY),
+        	8,
+        	SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+
+    	DramPhyReset(p);
+
+    	// set dqs delay, (dqm delay)
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5),
+                P_Fld((U32)0, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4),
+                P_Fld((U32)0x46, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5),
+                P_Fld((U32)0, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4),
+                P_Fld((U32)0x46, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1));
+
+        // set dq delay
+        U8 u1BitIdx;
+        for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2)
+        {
+             vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + u1BitIdx * 2),
+                                            P_Fld(((U32)0x46), SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+                                            P_Fld(((U32)0x46), SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+
+             vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + u1BitIdx * 2),
+                                            P_Fld((U32)0x46, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+                                            P_Fld((U32)0x46, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
+
+            //mcSHOW_DBG_MSG(("u1BitId %d  Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2,
+            //                FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly,  FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly));
+        }
+
+        {
+            U8 u1TXMCK[4] = {2,2,2,2};
+            U8 u1TXOENMCK[4] = {1,1,1,1};
+            U8 u1TXUI[4] = {1,1,1,1};
+            U8 u1TXOENUI[4] = {5,5,5,5};
+            U8 u1TXPI[4] = {30,30,30,30};
+
+            if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE))
+            {
+                u1TXPI[0] = u1TXPI[1]= u1TXPI[2] = u1TXPI[3] =41;
+            }
+            else
+            {
+                u1TXPI[0] = u1TXPI[1]= u1TXPI[2] = u1TXPI[3] =30;
+            }
+            
+            TXSetDelayReg_DQ(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, u1TXPI);
+            TXSetDelayReg_DQM(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, u1TXPI);
+
+            //Tx Perbits delay
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), 0);
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), 0);
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), 0);
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1), 0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), 0x0, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), 0x0, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1);
+
+
+            #if ENABLE_TX_TRACKING
+            TXUpdateTXTracking(p, TX_DQ_DQS_MOVE_DQ_ONLY, u1TXPI, u1TXPI);
+            #endif
+        }
+
+        dle_factor_handler(p, 9);
+    }
+
+    vSetRank(p, backup_rank);
+}
+
+void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p)
+{
+    U8 u1RankIdx=0;
+    // WL
+    U8 u1WLB0_Dly=0, u1WLB1_Dly=0;
+    // Gating
+    U8 u1GatingMCKB0_Dly=0, u1GatingMCKB1_Dly=0;
+    U8 u1GatingUIB0_Dly=0, u1GatingUIB1_Dly=0;
+    U8 u1GatingPIB0_Dly=0, u1GatingPIB1_Dly=0;
+    U8 u1B0RodtMCK=0, u1B1RodtMCK=0;
+    U8 u1B0RodtUI=0, u1B1RodtUI=0;
+    // Rx
+    U8 u1RxDQS0=0, u1RxDQS1=0;
+    U8 u1RxDQM0=0, u1RxDQM1=0;
+    U8 u1RxRK0B0DQ[8] = {153,147,155,133,149,147,147,143};
+    U8 u1RxRK0B1DQ[8] = {163,157,149,143,147,159,151,155};
+    U8 u1RxRK1B0DQ[8] = {151,147,149,131,151,147,143,139};
+    U8 u1RxRK1B1DQ[8] = {167,159,149,143,151,157,149,157};
+    U8 *pRxB0DQ, *pRxB1DQ;
+    U8 *pTxDQPi;
+    U8 backup_rank=0;
+
+    backup_rank = p->rank;
+
+    ShiftDQUI_AllRK(p, -1, ALL_BYTES);
+    ShiftDQ_OENUI_AllRK(p, -1, ALL_BYTES);
+    ShiftDQSWCK_UI(p, -1, ALL_BYTES);
+
+    for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+
+#if 0
+        //CBT
+        DramcCmdUIDelaySetting(p, 0);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0),
+                                P_Fld(32, SHU_R0_CA_CMD0_RG_ARPI_CMD) |
+                                P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK));
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), 0, SHU_R0_CA_CMD0_RG_ARPI_CS);
+#endif
+
+    #if 1
+        //WL
+        if (p->rank == RANK_0)
+        {
+            u1WLB0_Dly = 29;
+            u1WLB1_Dly = 28;
+        }
+        else
+        {
+            u1WLB0_Dly = 31;
+            u1WLB1_Dly = 24;
+        }
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), u1WLB0_Dly, SHU_R0_B0_DQ0_ARPI_PBYTE_B0);  //rank0, byte0, DQS delay
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), u1WLB1_Dly, SHU_R0_B1_DQ0_ARPI_PBYTE_B1);  //rank0, byte1, DQS delay
+
+        //Gating MCK/UI
+        if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE))
+        {
+            //if (p->rank == RANK_0)
+            {
+                u1GatingMCKB0_Dly=0; u1GatingMCKB1_Dly=0;
+                u1GatingUIB0_Dly=14; u1GatingUIB1_Dly=14;
+                u1GatingPIB0_Dly=8; u1GatingPIB1_Dly=10;
+                u1B0RodtMCK=0; u1B1RodtMCK=0;
+                u1B0RodtUI=3; u1B1RodtUI=3;
+            }
+            //else
+            {
+            //    u1GatingMCKB0_Dly=0; u1GatingMCKB1_Dly=0;
+            //    u1GatingUIB0_Dly=14; u1GatingUIB1_Dly=14;
+            //    u1GatingPIB0_Dly=4; u1GatingPIB1_Dly=10;
+            //    u1B0RodtMCK=0; u1B1RodtMCK=0;
+            //    u1B0RodtUI=3; u1B1RodtUI=3;
+            }
+            
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
+                P_Fld(u1GatingMCKB0_Dly,
+                SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+                P_Fld(u1GatingUIB0_Dly,
+                SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+                P_Fld(u1GatingMCKB0_Dly+1,
+                SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) |
+                P_Fld(u1GatingUIB0_Dly+4-16,
+                SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0));
+            
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
+                P_Fld(u1GatingMCKB1_Dly,
+                SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+                P_Fld(u1GatingUIB1_Dly,
+                SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+                P_Fld(u1GatingMCKB1_Dly+1,
+                SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) |
+                P_Fld(u1GatingUIB1_Dly+4-16,
+                SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1));
+        }
+        else
+        {
+            if (p->rank == RANK_0)
+            {
+                u1GatingMCKB0_Dly=1; u1GatingMCKB1_Dly=1;
+                u1GatingUIB0_Dly=6; u1GatingUIB1_Dly=6;
+                u1GatingPIB0_Dly=0; u1GatingPIB1_Dly=4;
+                u1B0RodtMCK=1; u1B1RodtMCK=1;
+                u1B0RodtUI=3; u1B1RodtUI=3;
+            }
+            else
+            {
+                u1GatingMCKB0_Dly=1; u1GatingMCKB1_Dly=1;
+                u1GatingUIB0_Dly=5; u1GatingUIB1_Dly=6;
+                u1GatingPIB0_Dly=28; u1GatingPIB1_Dly=0;
+                u1B0RodtMCK=1; u1B1RodtMCK=1;
+                u1B0RodtUI=2; u1B1RodtUI=3;
+            }
+            
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
+                P_Fld(u1GatingMCKB0_Dly,
+                SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+                P_Fld(u1GatingUIB0_Dly,
+                SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+                P_Fld(u1GatingMCKB0_Dly,
+                SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) |
+                P_Fld(u1GatingUIB0_Dly+4,
+                SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0));
+            
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
+                P_Fld(u1GatingMCKB1_Dly,
+                SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+                P_Fld(u1GatingUIB1_Dly,
+                SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+                P_Fld(u1GatingMCKB1_Dly,
+                SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) |
+                P_Fld(u1GatingUIB1_Dly+4,
+                SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1));
+        }
+
+#if GATING_RODT_LATANCY_EN
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY),
+                            P_Fld(u1B0RodtMCK,
+                            SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+                            P_Fld(u1B0RodtUI,
+                            SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+                            P_Fld(u1B0RodtMCK,
+                            SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) |
+                            P_Fld(u1B0RodtUI,
+                            SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0));
+
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY),
+                            P_Fld(u1B1RodtMCK,
+                            SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+                            P_Fld(u1B1RodtUI,
+                            SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+                            P_Fld(u1B1RodtMCK,
+                            SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) |
+                            P_Fld(u1B1RodtUI,
+                            SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1));
+#endif
+
+        //Gating PI
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY),
+                u1GatingPIB0_Dly,
+                SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY),
+                u1GatingPIB1_Dly,
+                SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); 
+
+        DramPhyReset(p);
+
+    #if RDSEL_TRACKING_EN
+        //Byte 0
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI),
+        (u1GatingMCKB0_Dly << 3) | (u1GatingUIB0_Dly),
+        SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0);//UI
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI), u1GatingPIB0_Dly,
+        SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0); //PI
+        //Byte 1
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI),
+        (u1GatingMCKB1_Dly << 3) | (u1GatingUIB1_Dly),
+        DDRPHY_REG_SHU_R0_B1_INI_UIPI);//UI
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI),
+        u1GatingPIB1_Dly, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1); //PI
+    #endif
+
+        if (p->rank == RANK_0)
+        {
+            u1RxDQS0=0; u1RxDQS1=0;
+            u1RxDQM0=146; u1RxDQM1=153;
+            pRxB0DQ = u1RxRK0B0DQ;
+            pRxB1DQ = u1RxRK0B1DQ;
+        }
+        else
+        {
+            u1RxDQS0=0; u1RxDQS1=0;
+            u1RxDQM0=144; u1RxDQM1=154;
+            pRxB0DQ = u1RxRK1B0DQ;
+            pRxB1DQ = u1RxRK1B1DQ;
+        }
+
+                // set Rx dqs delay, (dqm delay)
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5),
+                P_Fld((U32)u1RxDQS0, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4),
+                P_Fld((U32)u1RxDQM0, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+                P_Fld((U32)0, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5),
+                P_Fld((U32)u1RxDQS1, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4),
+                P_Fld((U32)u1RxDQM1, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+                P_Fld((U32)0, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+
+        // set Rx dq delay
+        U8 u1BitIdx;
+        for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2)
+        {
+              vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + u1BitIdx * 2),
+                                            P_Fld(((U32)pRxB0DQ[u1BitIdx]), SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+                                            P_Fld(((U32)pRxB0DQ[u1BitIdx+1]), SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+
+             vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + u1BitIdx * 2),
+                                            P_Fld((U32)pRxB1DQ[u1BitIdx], SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+                                            P_Fld((U32)pRxB1DQ[u1BitIdx+1], SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
+
+            //mcSHOW_DBG_MSG(("u1BitId %d  Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2,
+            //                FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly,  FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly));
+        }
+
+        {
+            U8 u1TXMCK[4] = {4,4,4,4};
+            U8 u1TXOENMCK[4] = {4,4,4,4};
+            U8 u1TXUI[4] = {6,6,6,6};
+            U8 u1TXOENUI[4] = {2,2,2,2};
+            U8 u1TXRK0PI[4] = {31,34,31,34};
+            U8 u1TXRK1PI[4] = {33,28,33,28};
+
+            if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE))
+            {
+                u1TXRK0PI[0] = u1TXRK0PI[1]= u1TXRK0PI[2] = u1TXRK0PI[3] =53;
+                u1TXRK1PI[0] = 45;
+                u1TXRK1PI[1]= u1TXRK1PI[2] = u1TXRK1PI[3] =53;
+            }
+
+            if (p->rank == RANK_0)
+                pTxDQPi = u1TXRK0PI;
+            else
+                pTxDQPi = u1TXRK1PI;
+            
+            TXSetDelayReg_DQ(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, pTxDQPi);
+            TXSetDelayReg_DQM(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, pTxDQPi);
+
+            //Tx Perbits delay
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), 0);
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), 0);
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), 0);
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1), 0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), 0x0, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), 0x0, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1);
+
+            #if ENABLE_TX_TRACKING
+            TXUpdateTXTracking(p, TX_DQ_DQS_MOVE_DQ_ONLY, pTxDQPi, pTxDQPi);
+            #endif
+        }
+
+    if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE))
+        dle_factor_handler(p, 16);
+    else
+        dle_factor_handler(p, 17);
+    #endif
+    }
+
+    vSetRank(p, backup_rank);
+}
+#else
+void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p)//simulation
+{
+    U8 u1RankIdx=0;
+    U8 backup_rank=0;
+
+    backup_rank = p->rank;
+
+    ShiftDQUI_AllRK(p, -1, ALL_BYTES);
+    ShiftDQ_OENUI_AllRK(p, -1, ALL_BYTES);
+    ShiftDQSWCK_UI(p, -1, ALL_BYTES);
+
+    for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+        //CBT
+		DramcCmdUIDelaySetting(p, 0);
+
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0),
+    		P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) |
+    		P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK));
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), 0, SHU_R0_CA_CMD0_RG_ARPI_CS);
+
+        //WL
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), 0x20, SHU_R0_B0_DQ0_ARPI_PBYTE_B0);  //rank0, byte0, DQS delay
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), 0x20, SHU_R0_B1_DQ0_ARPI_PBYTE_B1);  //rank0, byte1, DQS delay
+
+        //Gating
+        if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE))
+        {
+	    if(p->rank==RANK_0)
+	    {
+            // normal mode
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+        		P_Fld(9,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+        		P_Fld(0,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) |
+        		P_Fld(13,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0));
+
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+        		P_Fld(9,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+        		P_Fld(0,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) |
+        		P_Fld(13,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1));
+
+            #if GATING_RODT_LATANCY_EN
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+        		P_Fld(0,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+        		P_Fld(0,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) |
+        		P_Fld(0,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0));
+
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+        		P_Fld(0,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+        		P_Fld(0,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) |
+        		P_Fld(0,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1));
+            #endif
+	    }
+	    else
+	    {
+            // normal mode
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+        		P_Fld(12,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+        		P_Fld(1,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) |
+        		P_Fld(0,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0));
+
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+        		P_Fld(12,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+        		P_Fld(1,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) |
+        		P_Fld(0,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1));
+
+            #if GATING_RODT_LATANCY_EN
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+        		P_Fld(1,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+        		P_Fld(0,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) |
+        		P_Fld(1,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0));
+
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+        		P_Fld(1,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+        		P_Fld(0,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) |
+        		P_Fld(1,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1));
+            #endif
+	    }
+        }
+        else
+        {
+            //mix mode
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+        		P_Fld(15,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+        		P_Fld(1,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) |
+        		P_Fld(3,
+        		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0));
+
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+        		P_Fld(15,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+        		P_Fld(1,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) |
+        		P_Fld(3,
+        		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1));
+            
+            #if GATING_RODT_LATANCY_EN
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+        		P_Fld(4,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+        		P_Fld(0,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) |
+        		P_Fld(4,
+        		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0));
+
+        	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY),
+        		P_Fld(0,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+        		P_Fld(4,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+        		P_Fld(0,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) |
+        		P_Fld(4,
+        		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1));
+            #endif
+        }
+        
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY),
+        	16,
+        	SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY),
+        	16,
+        	SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+
+    	DramPhyReset(p);
+
+    	// set dqs delay, (dqm delay)
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5),
+                P_Fld((U32)0x45, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4),
+                P_Fld((U32)0x0, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5),
+                P_Fld((U32)0x45, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4),
+                P_Fld((U32)0x0, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1));
+
+        // set dq delay
+        U8 u1BitIdx;
+        for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2)
+        {
+             vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + u1BitIdx * 2),
+                                            P_Fld(((U32)0x0), SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+                                            P_Fld(((U32)0x0), SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+
+             vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + u1BitIdx * 2),
+                                            P_Fld((U32)0x0, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+                                            P_Fld((U32)0x0, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
+
+            //mcSHOW_DBG_MSG(("u1BitId %d  Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2,
+            //                FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly,  FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly));
+        }
+
+        {
+            U8 u1TXMCK[4] = {2,2,2,2};
+            U8 u1TXOENMCK[4] = {1,1,1,1};
+            U8 u1TXUI[4] = {1,1,1,1};
+            U8 u1TXOENUI[4] = {5,5,5,5};
+            U8 u1TXPI[4] = {30,30,30,30};
+
+            if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE))
+            {
+                u1TXPI[0] = u1TXPI[1]= u1TXPI[2] = u1TXPI[3] =30;
+            }
+            else
+            {
+                u1TXPI[0] = u1TXPI[1]= u1TXPI[2] = u1TXPI[3] =30;
+            }
+
+            if(p->rank==RANK_1)
+            {
+                u1TXPI[0] = u1TXPI[1]= u1TXPI[2] = u1TXPI[3] =50;
+            }
+            
+            TXSetDelayReg_DQ(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, u1TXPI);
+            TXSetDelayReg_DQM(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, u1TXPI);
+
+            //Tx Perbits delay
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), 0);
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), 0);
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), 0);
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1), 0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), 0x0, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), 0x0, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1);
+
+
+            #if ENABLE_TX_TRACKING
+            TXUpdateTXTracking(p, TX_DQ_DQS_MOVE_DQ_ONLY, u1TXPI, u1TXPI);
+            #endif
+        }
+
+        dle_factor_handler(p, 8);
+    }
+
+    vSetRank(p, backup_rank);
+}
+
+void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p)//simulation 
+{
+    U8 u1RankIdx=0;
+    // WL
+    U8 u1WLB0_Dly=0, u1WLB1_Dly=0;
+    // Gating
+    U8 u1GatingMCKB0_Dly=0, u1GatingMCKB1_Dly=0;
+    U8 u1GatingUIB0_Dly=0, u1GatingUIB1_Dly=0;
+    U8 u1GatingPIB0_Dly=0, u1GatingPIB1_Dly=0;
+    U8 u1B0RodtMCK=0, u1B1RodtMCK=0;
+    U8 u1B0RodtUI=0, u1B1RodtUI=0;
+    // Rx
+    U8 u1RxDQS0=0, u1RxDQS1=0;
+    U8 u1RxDQM0=0, u1RxDQM1=0;
+    U8 u1RxRK0B0DQ[8] = {70,70,70,70,70,70,70,70};
+    U8 u1RxRK0B1DQ[8] = {70,70,70,70,70,70,70,70};
+    U8 u1RxRK1B0DQ[8] = {70,70,70,70,70,70,70,70};
+    U8 u1RxRK1B1DQ[8] = {70,70,70,70,70,70,70,70};
+    U8 *pRxB0DQ, *pRxB1DQ;
+    U8 *pTxDQPi;
+    U8 backup_rank=0;
+
+    backup_rank = p->rank;
+
+    ShiftDQUI_AllRK(p, -1, ALL_BYTES);
+    ShiftDQ_OENUI_AllRK(p, -1, ALL_BYTES);
+    ShiftDQSWCK_UI(p, -1, ALL_BYTES);
+
+    for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+
+#if 1
+        //CBT
+        //DramcCmdUIDelaySetting(p, 0);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0),
+                                P_Fld(40, SHU_R0_CA_CMD0_RG_ARPI_CMD) |
+                                P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK));
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), 0, SHU_R0_CA_CMD0_RG_ARPI_CS);
+#endif
+
+    #if 1
+        //WL
+        if (p->rank == RANK_0)
+        {
+            u1WLB0_Dly = 34;
+            u1WLB1_Dly = 38;
+        }
+        else
+        {
+            u1WLB0_Dly = 37;
+            u1WLB1_Dly = 32;
+        }
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), u1WLB0_Dly, SHU_R0_B0_DQ0_ARPI_PBYTE_B0);  //rank0, byte0, DQS delay
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), u1WLB1_Dly, SHU_R0_B1_DQ0_ARPI_PBYTE_B1);  //rank0, byte1, DQS delay
+
+        //Gating MCK/UI
+        if (p->rank == RANK_0)
+        {
+            u1GatingMCKB0_Dly=0; u1GatingMCKB1_Dly=0;
+            u1GatingUIB0_Dly=9; u1GatingUIB1_Dly=9;
+            u1GatingPIB0_Dly=16; u1GatingPIB1_Dly=16;
+            u1B0RodtMCK=0; u1B1RodtMCK=0;
+            u1B0RodtUI=0; u1B1RodtUI=0;
+        }
+        else
+        {
+            u1GatingMCKB0_Dly=1; u1GatingMCKB1_Dly=1;
+            u1GatingUIB0_Dly=2; u1GatingUIB1_Dly=2;
+            u1GatingPIB0_Dly=0; u1GatingPIB1_Dly=0;
+            u1B0RodtMCK=1; u1B1RodtMCK=1;
+            u1B0RodtUI=3; u1B1RodtUI=3;
+        }
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
+            P_Fld(u1GatingMCKB0_Dly,
+            SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+            P_Fld(u1GatingUIB0_Dly,
+            SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+            P_Fld(((u1GatingMCKB0_Dly<<4)+u1GatingUIB0_Dly+4)>>4,
+            SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) |
+            P_Fld(((u1GatingMCKB0_Dly<<4)+u1GatingUIB0_Dly+4)%16,
+            SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0));
+        
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
+            P_Fld(u1GatingMCKB1_Dly,
+            SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+            P_Fld(u1GatingUIB1_Dly,
+            SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+            P_Fld(((u1GatingMCKB1_Dly<<4)+u1GatingUIB1_Dly+4)>>4,
+            SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) |
+            P_Fld(((u1GatingMCKB1_Dly<<4)+u1GatingUIB1_Dly+4)%16,
+            SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1));
+
+#if GATING_RODT_LATANCY_EN
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY),
+                            P_Fld(u1B0RodtMCK,
+                            SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+                            P_Fld(u1B0RodtUI,
+                            SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+                            P_Fld(u1B0RodtMCK,
+                            SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) |
+                            P_Fld(u1B0RodtUI,
+                            SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0));
+
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY),
+                            P_Fld(u1B1RodtMCK,
+                            SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+                            P_Fld(u1B1RodtUI,
+                            SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+                            P_Fld(u1B1RodtMCK,
+                            SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) |
+                            P_Fld(u1B1RodtUI,
+                            SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1));
+#endif
+
+        //Gating PI
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY),
+                u1GatingPIB0_Dly,
+                SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY),
+                u1GatingPIB1_Dly,
+                SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); 
+
+        DramPhyReset(p);
+
+
+        if (p->rank == RANK_0)
+        {
+            u1RxDQS0=0; u1RxDQS1=0;
+            u1RxDQM0=70; u1RxDQM1=70;
+            pRxB0DQ = u1RxRK0B0DQ;
+            pRxB1DQ = u1RxRK0B1DQ;
+        }
+        else
+        {
+            u1RxDQS0=0; u1RxDQS1=0;
+            u1RxDQM0=70; u1RxDQM1=70;
+            pRxB0DQ = u1RxRK1B0DQ;
+            pRxB1DQ = u1RxRK1B1DQ;
+        }
+
+                // set Rx dqs delay, (dqm delay)
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5),
+                P_Fld((U32)u1RxDQS0, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4),
+                P_Fld((U32)u1RxDQM0, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+                P_Fld((U32)0, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5),
+                P_Fld((U32)u1RxDQS1, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4),
+                P_Fld((U32)u1RxDQM1, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+                P_Fld((U32)0, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+
+        // set Rx dq delay
+        U8 u1BitIdx;
+        for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2)
+        {
+              vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + u1BitIdx * 2),
+                                            P_Fld(((U32)pRxB0DQ[u1BitIdx]), SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+                                            P_Fld(((U32)pRxB0DQ[u1BitIdx+1]), SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+
+             vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + u1BitIdx * 2),
+                                            P_Fld((U32)pRxB1DQ[u1BitIdx], SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+                                            P_Fld((U32)pRxB1DQ[u1BitIdx+1], SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
+
+            //mcSHOW_DBG_MSG(("u1BitId %d  Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2,
+            //                FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly,  FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly));
+        }
+
+        {
+            U8 u1TXMCK[4] = {4,4,4,4};
+            U8 u1TXOENMCK[4] = {4,4,4,4};
+            U8 u1TXUI[4] = {6,6,6,6 };
+            U8 u1TXOENUI[4] = {2,2,2,2};
+            U8 u1TXRK0PI[4] = {28,28,28,28};
+                        
+
+            U8 u1TXMCK_RK1[4] = {4,4,4,4};
+            U8 u1TXOENMCK_RK1[4] = {4,4,4,4};
+            U8 u1TXUI_RK1[4] = {7,7,7,7};
+            U8 u1TXOENUI_RK1[4] = {3,3,3,3};
+            U8 u1TXRK1PI[4] = {46,46,46,46};
+
+            if (p->rank == RANK_0)
+            {
+                pTxDQPi = u1TXRK0PI;
+                
+                TXSetDelayReg_DQ(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, pTxDQPi);
+                TXSetDelayReg_DQM(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, pTxDQPi);
+            }
+            else
+            {
+                pTxDQPi = u1TXRK1PI;
+                TXSetDelayReg_DQ(p, 1, u1TXMCK_RK1, u1TXOENMCK_RK1, u1TXUI_RK1, u1TXOENUI_RK1, pTxDQPi);
+                TXSetDelayReg_DQM(p, 1, u1TXMCK_RK1, u1TXOENMCK_RK1, u1TXUI_RK1, u1TXOENUI_RK1, pTxDQPi);
+            }
+            
+            //Tx Perbits delay
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), 0);
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), 0);
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), 0);
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1), 0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), 0x0, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), 0x0, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1);
+        }
+
+        dle_factor_handler(p, 14);
+    #endif
+    }
+
+    vSetRank(p, backup_rank);
+}
+
+#endif
+#endif
+
+void sv_algorithm_assistance_LP4_1600(DRAMC_CTX_T *p){
+//    Enter body
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter:
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                      
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_RDSEL_TRACK_0                         ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0                  -     @13206                                                     
+  DMDATLAT_i                                   uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h09 (Mirror: 5'h00)      
+  RDSEL_HWSAVE_MSK                             uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0)        
+  RDSEL_TRACK_EN                               uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0                       
+  SHU_GW_THRD_NEG                              uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfeb (Mirror: 12'h000) 
+  SHU_GW_THRD_POS                              uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h015 (Mirror: 12'h000)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x09, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) |
+        P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) |
+        P_Fld(0xfeb, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x015, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                      
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RDAT_0                                ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0                         -     @13076                                                     
+  DATLAT                                       uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[4:0]=5'h09 (Mirror: 5'h00)             
+  DATLAT_DSEL                                  uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[12:8]=5'h09 (Mirror: 5'h00)            
+  DATLAT_DSEL_PHY                              uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[20:16]=5'h09 (Mirror: 5'h00)           
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x09, MISC_SHU_RDAT_DATLAT) |
+        P_Fld(0x09, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x09, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
+#endif
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                      
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_PHY_RX_CTRL_0                         ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0                  -     @13012                                                     
+  RANK_RXDLY_UPDLAT_EN                         uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0)        
+  RANK_RXDLY_UPD_OFFSET                        uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0)       
+  RX_IN_GATE_EN_PRE_OFFSET                     uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0)      
+  RX_IN_GATE_EN_HEAD                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h0                     
+  RX_IN_GATE_EN_TAIL                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0)      
+  RX_IN_BUFF_EN_HEAD                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h0                     
+  RX_IN_BUFF_EN_TAIL                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0                     
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) |
+        P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) |
+        P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) |
+        P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                      
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RANKCTL_0                             ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0                      -     @13002                                                     
+  RANKINCTL_RXDLY                              uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[3:0]=4'h0                           
+  RANK_RXDLY_OPT                               uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[4:4]=1'h1                           
+  RANKSEL_SELPH_FRUN                           uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[15:15]=1'h1 (Mirror: 1'h0)          
+  RANKINCTL_STB                                uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[19:16]=4'h1 (Mirror: 4'h0)          
+  RANKINCTL                                    uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[23:20]=4'h0                         
+  RANKINCTL_ROOT1                              uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[27:24]=4'h0                         
+  RANKINCTL_PHY                                uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[31:28]=4'h3 (Mirror: 4'h0)          
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) |
+        P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x1, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) |
+        P_Fld(0x1, MISC_SHU_RANKCTL_RANKINCTL_STB));
+
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL) |
+        P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x3, MISC_SHU_RANKCTL_RANKINCTL_PHY));
+
+#endif
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                      
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RANK_SEL_LAT_0                        ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0                 -     @13229                                                     
+  RANK_SEL_LAT_B0                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0)       
+  RANK_SEL_LAT_B1                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0)       
+  RANK_SEL_LAT_CA                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0)      
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
+        P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
+
+#if !CODE_SIZE_REDUCE
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                      
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RK_DQSCTL_0_0                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0                  -     @12823                                                     
+  DQSINCTL                                     uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h2 (Mirror: 4'h0)        
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL);
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                      
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RK_DQSCTL_0_1                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1                  -     @12827                                                     
+  DQSINCTL                                     uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h2 (Mirror: 4'h0)        
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL);
+/*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                       
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0         -     @8022                                                       
+  DQSIEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h9 (Mirror: 4'h0)
+  DQSIEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hd (Mirror: 4'h0)
+  DQSIEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0             
+  DQSIEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0             
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x9, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+        P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+        P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+/*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                       
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_DQSIEN_PI_DLY_0_0                    ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0             -     @8036                                                       
+  DQSIEN_PI_B0                                 uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00)  
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0b, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1         -     @8029                                                         
+  DQSIEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0)  
+  DQSIEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0                 
+  DQSIEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0               
+  DQSIEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+        P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+        P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_DQSIEN_PI_DLY_0_1                    ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1             -     @8040                                                         
+  DQSIEN_PI_B0                                 uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00)    
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x11, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0         -     @9429                                                         
+  DQSIEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h9 (Mirror: 4'h0)  
+  DQSIEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hd (Mirror: 4'h0)  
+  DQSIEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0               
+  DQSIEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0               
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x9, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+        P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+        P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_DQSIEN_PI_DLY_0_0                    ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0             -     @9443                                                         
+  DQSIEN_PI_B1                                 uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00)    
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0b, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1         -     @9436                                                         
+  DQSIEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0)  
+  DQSIEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0                 
+  DQSIEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0               
+  DQSIEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+        P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+        P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_DQSIEN_PI_DLY_0_1                    ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1             -     @9447                                                         
+  DQSIEN_PI_B1                                 uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00)    
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x11, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_ODTCTRL_0                             ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0                      -     @13022                                                        
+  RODTEN                                       uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0)               
+  RODTENSTB_SELPH_CG_IG                        uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[1:1]=1'h0                              
+  RODT_LAT                                     uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[7:4]=4'h1 (Mirror: 4'h0)               
+  RODTEN_SELPH_FRUN                            uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[15:15]=1'h0                            
+  RODTDLY_LAT_OPT                              uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[25:24]=2'h0                            
+  FIXRODT                                      uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[27:27]=1'h0                            
+  RODTEN_OPT                                   uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[29:29]=1'h1                            
+  RODTE2                                       uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0)             
+  RODTE                                        uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0)             
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) |
+        P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) |
+        P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) |
+        P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) |
+        P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE));
+
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_ODTCTRL, 0x1, MISC_SHU_ODTCTRL_RODT_LAT);
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ7_0                            -     @8206                                                         
+  R_DMRANKRXDVS_B0                             uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[3:0]=4'h0                                    
+  R_DMDQMDBI_EYE_SHU_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[6:6]=1'h0                                    
+  R_DMDQMDBI_SHU_B0                            uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[7:7]=1'h0                                    
+  R_DMRXDVS_DQM_FLAGSEL_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[11:8]=4'h0                                   
+  R_DMRXDVS_PBYTE_FLAG_OPT_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[12:12]=1'h0                                  
+  R_DMRXDVS_PBYTE_DQM_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[13:13]=1'h0                                  
+  R_DMRXTRACK_DQM_EN_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[14:14]=1'h0                                  
+  R_DMRODTEN_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)                   
+  R_DMARPI_CG_FB2DLL_DCM_EN_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[16:16]=1'h0                                  
+  R_DMTX_ARPI_CG_DQ_NEW_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[17:17]=1'h0                                  
+  R_DMTX_ARPI_CG_DQS_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[18:18]=1'h0                                  
+  R_DMTX_ARPI_CG_DQM_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[19:19]=1'h0                                  
+  R_LP4Y_SDN_MODE_DQS0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[20:20]=1'h0                                  
+  R_DMRXRANK_DQ_EN_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)                   
+  R_DMRXRANK_DQ_LAT_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0)                   
+  R_DMRXRANK_DQS_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)                   
+  R_DMRXRANK_DQS_LAT_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[31:29]=3'h0                                  
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ7_0                            -     @9613                                                         
+  R_DMRANKRXDVS_B1                             uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[3:0]=4'h0                                    
+  R_DMDQMDBI_EYE_SHU_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[6:6]=1'h0                                    
+  R_DMDQMDBI_SHU_B1                            uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[7:7]=1'h0                                    
+  R_DMRXDVS_DQM_FLAGSEL_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[11:8]=4'h0                                   
+  R_DMRXDVS_PBYTE_FLAG_OPT_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[12:12]=1'h0                                  
+  R_DMRXDVS_PBYTE_DQM_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[13:13]=1'h0                                  
+  R_DMRXTRACK_DQM_EN_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[14:14]=1'h0                                  
+  R_DMRODTEN_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)                   
+  R_DMARPI_CG_FB2DLL_DCM_EN_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[16:16]=1'h0                                  
+  R_DMTX_ARPI_CG_DQ_NEW_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[17:17]=1'h0                                  
+  R_DMTX_ARPI_CG_DQS_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[18:18]=1'h0                                  
+  R_DMTX_ARPI_CG_DQM_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[19:19]=1'h0                                  
+  R_LP4Y_SDN_MODE_DQS1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[20:20]=1'h0                                  
+  R_DMRXRANK_DQ_EN_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)                   
+  R_DMRXRANK_DQ_LAT_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0)                   
+  R_DMRXRANK_DQS_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)                   
+  R_DMRXRANK_DQS_LAT_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[31:29]=3'h0                                  
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_RX_PIPE_CTRL_0                        ral_reg_DDRPHY_blk_SHU_MISC_RX_PIPE_CTRL_0                 -     @13176                                                        
+  RX_PIPE_BYPASS_EN                            uvm_reg_field                                              ...    RW SHU_MISC_RX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0)          
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x1, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0         -     @8044                                                         
+  RODTEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0)  
+  RODTEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0)  
+  RODTEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0               
+  RODTEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0               
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+        P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+        P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1         -     @8051                                                         
+  RODTEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0)  
+  RODTEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0)  
+  RODTEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0               
+  RODTEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0               
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+        P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+        P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0         -     @9451                                                         
+  RODTEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0)  
+  RODTEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0)  
+  RODTEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0               
+  RODTEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0               
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+        P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+        P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1         -     @9458                                                         
+  RODTEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0)  
+  RODTEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0)  
+  RODTEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0               
+  RODTEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0               
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+        P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+        P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RX_CG_SET0_0                               ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0                         -     @5628                                                         
+  DLE_LAST_EXTEND3                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[0:0]=1'h0                                
+  READ_START_EXTEND3                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[1:1]=1'h0                                
+  DLE_LAST_EXTEND2                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[2:2]=1'h0                                
+  READ_START_EXTEND2                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[3:3]=1'h0                                
+  DLE_LAST_EXTEND1                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0)                 
+  READ_START_EXTEND1                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0)                 
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) |
+        P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) |
+        P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
+        P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_RANK_SEL_STB_0                        ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0                 -     @13192                                                        
+  RANK_SEL_STB_EN                              uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0)          
+  RANK_SEL_STB_EN_B23                          uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0                         
+  RANK_SEL_STB_SERMODE                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0                         
+  RANK_SEL_STB_TRACK                           uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0)          
+  RANK_SEL_RXDLY_TRACK                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0                         
+  RANK_SEL_STB_PHASE_EN                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h0                         
+  RANK_SEL_PHSINCTL                            uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h1 (Mirror: 4'h0)         
+  RANK_SEL_STB_UI_PLUS                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0                       
+  RANK_SEL_STB_MCK_PLUS                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0                       
+  RANK_SEL_STB_UI_MINUS                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h0                       
+  RANK_SEL_STB_MCK_MINUS                       uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0                       
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) |
+        P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) |
+        P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) |
+        P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) |
+        P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) |
+        P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RK_DQSCAL_0_0                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0                  -     @12841                                                        
+  DQSIENLLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00)         
+  DQSIENLLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0)           
+  DQSIENHLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00)        
+  DQSIENHLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RK_DQSCAL_0_1                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1                  -     @12848                                                        
+  DQSIENLLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00)         
+  DQSIENLLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0)           
+  DQSIENHLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00)        
+  DQSIENHLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_INI_UIPI_0_0                         ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0                  -     @8000                                                         
+  CURR_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)         
+  CURR_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00)        
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+        P_Fld(0x09, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_INI_UIPI_0_0                         ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0                  -     @9407                                                         
+  CURR_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)         
+  CURR_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00)        
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+        P_Fld(0x09, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_INI_UIPI_0_1                         ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1                  -     @8005                                                         
+  CURR_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00)         
+  CURR_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00)        
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+        P_Fld(0x0c, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_INI_UIPI_0_1                         ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1                  -     @9412                                                         
+  CURR_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00)         
+  CURR_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00)        
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+        P_Fld(0x0c, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_NEXT_INI_UIPI_0_0                    ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0             -     @8010                                                         
+  NEXT_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)    
+  NEXT_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00)   
+  NEXT_INI_UI_P1_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h0d (Mirror: 8'h00)  
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+        P_Fld(0x09, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_NEXT_INI_UIPI_0_0                    ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0             -     @9417                                                         
+  NEXT_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)    
+  NEXT_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00)   
+  NEXT_INI_UI_P1_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h0d (Mirror: 8'h00)  
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+        P_Fld(0x09, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_NEXT_INI_UIPI_0_1                    ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1             -     @8016                                                         
+  NEXT_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00)    
+  NEXT_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00)   
+  NEXT_INI_UI_P1_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00)  
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+        P_Fld(0x0c, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x10, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_NEXT_INI_UIPI_0_1                    ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1             -     @9423                                                         
+  NEXT_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00)    
+  NEXT_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00)   
+  NEXT_INI_UI_P1_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00)  
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+        P_Fld(0x0c, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x10, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit:
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter:
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_CA_CMD0_0_0                             ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_0                      -     @10832                                                        
+  RG_RX_ARCLK_R_DLY_DUTY                       uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[2:0]=3'h0                              
+  RG_RX_ARCLK_F_DLY_DUTY                       uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[6:4]=3'h0                              
+  RG_ARPI_CS                                   uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[13:8]=6'h00                            
+  RG_ARPI_CMD                                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[21:16]=6'h20 (Mirror: 6'h00)           
+  RG_ARPI_CLK                                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[29:24]=6'h00                           
+  DA_ARPI_DDR400_0D5UI_RK0_CA                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[30:30]=1'h0                            
+  DA_RX_ARDQSIEN_0D5UI_RK0_CA                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[31:31]=1'h0                            
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
+        P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_DQ0_0_0                              ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0                       -     @7980                                                         
+  RG_RX_ARDQS0_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0                               
+  RG_RX_ARDQS0_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0                               
+  SW_ARPI_DQ_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[13:8]=6'h19 (Mirror: 6'h00)             
+  SW_ARPI_DQM_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[21:16]=6'h19 (Mirror: 6'h00)            
+  ARPI_PBYTE_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00                            
+  DA_ARPI_DDR400_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0                             
+  DA_RX_ARDQSIEN_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0                             
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x19, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+        P_Fld(0x19, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_DQ0_0_0                              ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0                       -     @9387                                                         
+  RG_RX_ARDQS1_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0                               
+  RG_RX_ARDQS1_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0                               
+  SW_ARPI_DQ_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[13:8]=6'h1f (Mirror: 6'h00)             
+  SW_ARPI_DQM_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[21:16]=6'h1f (Mirror: 6'h00)            
+  ARPI_PBYTE_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00                            
+  DA_ARPI_DDR400_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0                             
+  DA_RX_ARDQSIEN_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0                             
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+        P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_CA_CMD0_0_1                             ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_1                      -     @10842                                                        
+  RG_RX_ARCLK_R_DLY_DUTY                       uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[2:0]=3'h0                              
+  RG_RX_ARCLK_F_DLY_DUTY                       uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[6:4]=3'h0                              
+  RG_ARPI_CS                                   uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[13:8]=6'h00                            
+  RG_ARPI_CMD                                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[21:16]=6'h20 (Mirror: 6'h00)           
+  RG_ARPI_CLK                                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[29:24]=6'h00                           
+  DA_ARPI_DDR400_0D5UI_RK0_CA                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[30:30]=1'h0                            
+  DA_RX_ARDQSIEN_0D5UI_RK0_CA                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[31:31]=1'h0                            
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
+
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
+        P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_DQ0_0_1                              ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1                       -     @7990                                                         
+  RG_RX_ARDQS0_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0                               
+  RG_RX_ARDQS0_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0                               
+  SW_ARPI_DQ_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[13:8]=6'h13 (Mirror: 6'h00)             
+  SW_ARPI_DQM_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[21:16]=6'h13 (Mirror: 6'h00)            
+  ARPI_PBYTE_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00                            
+  DA_ARPI_DDR400_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0                             
+  DA_RX_ARDQSIEN_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0                             
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x13, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+        P_Fld(0x13, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_DQ0_0_1                              ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1                       -     @9397                                                         
+  RG_RX_ARDQS1_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0                               
+  RG_RX_ARDQS1_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0                               
+  SW_ARPI_DQ_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[13:8]=6'h12 (Mirror: 6'h00)             
+  SW_ARPI_DQM_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[21:16]=6'h12 (Mirror: 6'h00)            
+  ARPI_PBYTE_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00                            
+  DA_ARPI_DDR400_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0                             
+  DA_RX_ARDQSIEN_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0                             
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x12, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+        P_Fld(0x12, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_DCM_CTRL0_0                                ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0                          -     @5331                                                         
+  DDRPHY_CLK_EN_OPT                            uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0)                  
+  DPHY_CMD_CLKEN_EXTCNT                        uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[10:8]=3'h3                                
+  DDRPHY_CLK_DYN_GATING_SEL                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0)                
+  APHYPI_CKCGL_CNT                             uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[19:16]=4'h2                               
+  APHYPI_CKCGH_CNT                             uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[23:20]=4'h4                               
+  FASTWAKE2                                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[29:29]=1'h0                               
+  FASTWAKE                                     uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[31:31]=1'h1                               
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+        P_Fld(0x3, SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+        P_Fld(0x2, SHU_DCM_CTRL0_APHYPI_CKCGL_CNT) | P_Fld(0x4, SHU_DCM_CTRL0_APHYPI_CKCGH_CNT) |
+        P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_APHY_TX_PICG_CTRL_0                        ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0                  -     @5683                                                         
+  DDRPHY_CLK_EN_COMB_TX_PICG_CNT               uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h3 (Mirror: 4'h0)          
+  DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1             uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h1 (Mirror: 3'h0)          
+  DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0             uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h0                        
+  DPHY_TX_DCM_EXTCNT                           uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[15:12]=4'h2                       
+  DDRPHY_CLK_EN_COMB_TX_OPT                    uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0)        
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) |
+        P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) |
+        P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_APHY_TX_PICG_CTRL_0_0                    ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0              -     @5221                                                         
+  DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h1 (Mirror: 3'h0)      
+  DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h0                     
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x1, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+        P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_APHY_TX_PICG_CTRL_0_1                    ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1              -     @5226                                                         
+  DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h1 (Mirror: 3'h0)      
+  DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h1 (Mirror: 3'h0)      
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+        P_Fld(0x1, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_NEW_XRW2W_CTRL_0                           ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0                     -     @5677                                                         
+  TX_PI_UPDCTL_B0                              uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h0                          
+  TX_PI_UPDCTL_B1                              uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h0                          
+  TXPI_UPD_MODE                                uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1)           
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) |
+        P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SELPH_DQS0_0                               ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0                         -     @5576                                                         
+  TXDLY_DQS0                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[2:0]=3'h2 (Mirror: 3'h1)                 
+  TXDLY_DQS1                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[6:4]=3'h2 (Mirror: 3'h1)                 
+  TXDLY_DQS2                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[10:8]=3'h1                               
+  TXDLY_DQS3                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[14:12]=3'h1                              
+  TXDLY_OEN_DQS0                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[18:16]=3'h1                              
+  TXDLY_OEN_DQS1                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[22:20]=3'h1                              
+  TXDLY_OEN_DQS2                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[26:24]=3'h1                              
+  TXDLY_OEN_DQS3                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[30:28]=3'h1                              
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) |
+        P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) |
+        P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3));
+
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS0) |
+        P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) |
+        P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS1));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SELPH_DQS1_0                               ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0                         -     @5587                                                         
+  dly_DQS0                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[3:0]=4'h1                                
+  dly_DQS1                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[7:4]=4'h1                                
+  dly_DQS2                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[11:8]=4'h1                               
+  dly_DQS3                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[15:12]=4'h1                              
+  dly_oen_DQS0                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[19:16]=4'h6 (Mirror: 4'h1)               
+  dly_oen_DQS1                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[23:20]=4'h6 (Mirror: 4'h1)               
+  dly_oen_DQS2                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[27:24]=4'h1                              
+  dly_oen_DQS3                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[31:28]=4'h1                              
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) |
+        P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) |
+        P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3));
+
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS0) |
+        P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS0) |
+        P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ0_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0                      -     @5041                                                         
+  TXDLY_DQ0                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[2:0]=3'h2 (Mirror: 3'h1)              
+  TXDLY_DQ1                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[6:4]=3'h2 (Mirror: 3'h1)              
+  TXDLY_DQ2                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1                            
+  TXDLY_DQ3                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1                           
+  TXDLY_OEN_DQ0                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[18:16]=3'h1                           
+  TXDLY_OEN_DQ1                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[22:20]=3'h1                           
+  TXDLY_OEN_DQ2                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1                           
+  TXDLY_OEN_DQ3                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1                           
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+        P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ1_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0                      -     @5063                                                         
+  TXDLY_DQM0                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[2:0]=3'h2 (Mirror: 3'h1)              
+  TXDLY_DQM1                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[6:4]=3'h2 (Mirror: 3'h1)              
+  TXDLY_DQM2                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1                            
+  TXDLY_DQM3                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1                           
+  TXDLY_OEN_DQM0                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[18:16]=3'h1                           
+  TXDLY_OEN_DQM1                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[22:20]=3'h1                           
+  TXDLY_OEN_DQM2                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1                           
+  TXDLY_OEN_DQM3                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1                           
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+        P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ2_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0                      -     @5085                                                         
+  dly_DQ0                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[3:0]=4'h1                             
+  dly_DQ1                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[7:4]=4'h1                             
+  dly_DQ2                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1                            
+  dly_DQ3                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1                           
+  dly_oen_DQ0                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[19:16]=4'h6 (Mirror: 4'h1)            
+  dly_oen_DQ1                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[23:20]=4'h6 (Mirror: 4'h1)            
+  dly_oen_DQ2                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1                           
+  dly_oen_DQ3                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1                           
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+        P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ3_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0                      -     @5107                                                         
+  dly_DQM0                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[3:0]=4'h1                             
+  dly_DQM1                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[7:4]=4'h1                             
+  dly_DQM2                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1                            
+  dly_DQM3                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1                           
+  dly_oen_DQM0                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[19:16]=4'h6 (Mirror: 4'h1)            
+  dly_oen_DQM1                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[23:20]=4'h6 (Mirror: 4'h1)            
+  dly_oen_DQM2                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1                           
+  dly_oen_DQM3                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1                           
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+        P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ0_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1                      -     @5052                                                         
+  TXDLY_DQ0                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[2:0]=3'h2 (Mirror: 3'h1)              
+  TXDLY_DQ1                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[6:4]=3'h2 (Mirror: 3'h1)              
+  TXDLY_DQ2                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1                            
+  TXDLY_DQ3                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1                           
+  TXDLY_OEN_DQ0                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[18:16]=3'h1                           
+  TXDLY_OEN_DQ1                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[22:20]=3'h1                           
+  TXDLY_OEN_DQ2                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1                           
+  TXDLY_OEN_DQ3                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1                           
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+        P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ1_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1                      -     @5074                                                         
+  TXDLY_DQM0                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[2:0]=3'h2 (Mirror: 3'h1)              
+  TXDLY_DQM1                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[6:4]=3'h2 (Mirror: 3'h1)              
+  TXDLY_DQM2                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1                            
+  TXDLY_DQM3                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1                           
+  TXDLY_OEN_DQM0                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[18:16]=3'h1                           
+  TXDLY_OEN_DQM1                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[22:20]=3'h1                           
+  TXDLY_OEN_DQM2                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1                           
+  TXDLY_OEN_DQM3                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1                           
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+        P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ2_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1                      -     @5096                                                         
+  dly_DQ0                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[3:0]=4'h2 (Mirror: 4'h1)              
+  dly_DQ1                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[7:4]=4'h2 (Mirror: 4'h1)              
+  dly_DQ2                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1                            
+  dly_DQ3                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1                           
+  dly_oen_DQ0                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[19:16]=4'h7 (Mirror: 4'h1)            
+  dly_oen_DQ1                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[23:20]=4'h7 (Mirror: 4'h1)            
+  dly_oen_DQ2                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1                           
+  dly_oen_DQ3                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1                           
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ0) |
+        P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+        P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ3_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1                      -     @5118                                                         
+  dly_DQM0                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[3:0]=4'h2 (Mirror: 4'h1)              
+  dly_DQM1                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[7:4]=4'h2 (Mirror: 4'h1)              
+  dly_DQM2                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1                            
+  dly_DQM3                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1                           
+  dly_oen_DQM0                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[19:16]=4'h7 (Mirror: 4'h1)            
+  dly_oen_DQM1                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[23:20]=4'h7 (Mirror: 4'h1)            
+  dly_oen_DQM2                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1                           
+  dly_oen_DQM3                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1                           
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM0) |
+        P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+        P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL1_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0                    -     @5129                                                         
+  BOOT_ORIG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h019 (Mirror: 11'h000)     
+  BOOT_ORIG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h01f (Mirror: 11'h000)    
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x019, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+        P_Fld(0x01f, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL2_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0                    -     @5139                                                         
+  BOOT_TARG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h019 (Mirror: 11'h000)     
+  BOOT_TARG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h01f (Mirror: 11'h000)    
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x019, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+        P_Fld(0x01f, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL5_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0                    -     @5177                                                         
+  BOOT_TARG_UI_RK0_DQM0                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h019 (Mirror: 11'h000)     
+  BOOT_TARG_UI_RK0_DQM1                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h01f (Mirror: 11'h000)    
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x019, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+        P_Fld(0x01f, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL1_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1                    -     @5134                                                         
+  BOOT_ORIG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h013 (Mirror: 11'h000)     
+  BOOT_ORIG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h012 (Mirror: 11'h000)    
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x013, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+        P_Fld(0x012, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL2_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1                    -     @5144                                                         
+  BOOT_TARG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h013 (Mirror: 11'h000)     
+  BOOT_TARG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h012 (Mirror: 11'h000)    
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x013, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+        P_Fld(0x012, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL5_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1                    -     @5182                                                         
+  BOOT_TARG_UI_RK0_DQM0                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h013 (Mirror: 11'h000)     
+  BOOT_TARG_UI_RK0_DQM1                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h012 (Mirror: 11'h000)    
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x013, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+        P_Fld(0x012, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_PI_0_0                                   ral_reg_DRAMC_blk_SHURK_PI_0_0                             -     @5187                                                         
+  RK0_ARPI_DQ_B1                               uvm_reg_field                                              ...    RW SHURK_PI_0_0[5:0]=6'h1f (Mirror: 6'h00)                   
+  RK0_ARPI_DQ_B0                               uvm_reg_field                                              ...    RW SHURK_PI_0_0[13:8]=6'h19 (Mirror: 6'h00)                  
+  RK0_ARPI_DQM_B1                              uvm_reg_field                                              ...    RW SHURK_PI_0_0[21:16]=6'h1f (Mirror: 6'h00)                 
+  RK0_ARPI_DQM_B0                              uvm_reg_field                                              ...    RW SHURK_PI_0_0[29:24]=6'h19 (Mirror: 6'h00)                 
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQ_B1) |
+        P_Fld(0x19, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQM_B1) |
+        P_Fld(0x19, SHURK_PI_RK0_ARPI_DQM_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_PI_0_1                                   ral_reg_DRAMC_blk_SHURK_PI_0_1                             -     @5194                                                         
+  RK0_ARPI_DQ_B1                               uvm_reg_field                                              ...    RW SHURK_PI_0_1[5:0]=6'h12 (Mirror: 6'h00)                   
+  RK0_ARPI_DQ_B0                               uvm_reg_field                                              ...    RW SHURK_PI_0_1[13:8]=6'h13 (Mirror: 6'h00)                  
+  RK0_ARPI_DQM_B1                              uvm_reg_field                                              ...    RW SHURK_PI_0_1[21:16]=6'h12 (Mirror: 6'h00)                 
+  RK0_ARPI_DQM_B0                              uvm_reg_field                                              ...    RW SHURK_PI_0_1[29:24]=6'h13 (Mirror: 6'h00)                 
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x12, SHURK_PI_RK0_ARPI_DQ_B1) |
+        P_Fld(0x13, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x12, SHURK_PI_RK0_ARPI_DQM_B1) |
+        P_Fld(0x13, SHURK_PI_RK0_ARPI_DQM_B0));
+
+#if !CODE_SIZE_REDUCE
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_TXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0                    -     @7826
+  TX_ARDQ0_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h3c (Mirror: 8'h00)
+  TX_ARDQ1_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h3c (Mirror: 8'h00)
+  TX_ARDQ2_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h3c (Mirror: 8'h00)
+  TX_ARDQ3_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h3c (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+        P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+        P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_TXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0                    -     @7840                                                         
+  TX_ARDQ4_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h3c (Mirror: 8'h00)           
+  TX_ARDQ5_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h3c (Mirror: 8'h00)          
+  TX_ARDQ6_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h3c (Mirror: 8'h00)         
+  TX_ARDQ7_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h3c (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+        P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+        P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_TXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0                    -     @7868                                                         
+  TX_ARDQM0_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h3c (Mirror: 8'h00)           
+  TX_ARWCK_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00                         
+  TX_ARWCKB_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x3c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+        P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_TXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1                    -     @9240                                                         
+  TX_ARDQ0_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h08 (Mirror: 8'h00)           
+  TX_ARDQ1_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h08 (Mirror: 8'h00)          
+  TX_ARDQ2_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h08 (Mirror: 8'h00)         
+  TX_ARDQ3_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h08 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+        P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+        P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_TXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1                    -     @9254                                                         
+  TX_ARDQ4_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h08 (Mirror: 8'h00)           
+  TX_ARDQ5_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h08 (Mirror: 8'h00)          
+  TX_ARDQ6_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h08 (Mirror: 8'h00)         
+  TX_ARDQ7_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h08 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+        P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+        P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_TXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1                    -     @9281                                                         
+  TX_ARDQM0_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h08 (Mirror: 8'h00)           
+  TX_ARWCK_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00                         
+  TX_ARWCKB_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+        P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit:
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter:
+#endif
+
+# if !(CODE_SIZE_REDUCE && AC_TIMING_DERATE_ENABLE)
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_AC_DERATING0_0                             ral_reg_DRAMC_blk_SHU_AC_DERATING0_0                       -     @5538                                                         
+  ACDERATEEN                                   uvm_reg_field                                              ...    RW SHU_AC_DERATING0_0[0:0]=1'h0                              
+  TRRD_DERATE                                  uvm_reg_field                                              ...    RW SHU_AC_DERATING0_0[18:16]=3'h1 (Mirror: 3'h0)             
+  TRCD_DERATE                                  uvm_reg_field                                              ...    RW SHU_AC_DERATING0_0[27:24]=4'h4 (Mirror: 4'h0)             
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING0, P_Fld(0x0, SHU_AC_DERATING0_ACDERATEEN) |
+        P_Fld(0x1, SHU_AC_DERATING0_TRRD_DERATE) | P_Fld(0x4, SHU_AC_DERATING0_TRCD_DERATE));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_AC_DERATING1_0                             ral_reg_DRAMC_blk_SHU_AC_DERATING1_0                       -     @5544                                                         
+  TRPAB_DERATE                                 uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[3:0]=4'h3 (Mirror: 4'h0)               
+  TRP_DERATE                                   uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[11:8]=4'h2 (Mirror: 4'h0)              
+  TRAS_DERATE                                  uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[21:16]=6'h00                           
+  TRC_DERATE                                   uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[28:24]=5'h00                           
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING1, P_Fld(0x3, SHU_AC_DERATING1_TRPAB_DERATE) |
+        P_Fld(0x2, SHU_AC_DERATING1_TRP_DERATE) | P_Fld(0x00, SHU_AC_DERATING1_TRAS_DERATE) |
+        P_Fld(0x00, SHU_AC_DERATING1_TRC_DERATE));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_AC_DERATING_05T_0                          ral_reg_DRAMC_blk_SHU_AC_DERATING_05T_0                    -     @5551                                                         
+  TRC_05T_DERATE                               uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[0:0]=1'h0                           
+  TRCD_05T_DERATE                              uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[6:6]=1'h0                           
+  TRP_05T_DERATE                               uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[7:7]=1'h1 (Mirror: 1'h0)            
+  TRPAB_05T_DERATE                             uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[8:8]=1'h1 (Mirror: 1'h0)            
+  TRAS_05T_DERATE                              uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[9:9]=1'h1 (Mirror: 1'h0)            
+  TRRD_05T_DERATE                              uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[12:12]=1'h0                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING_05T, P_Fld(0x0, SHU_AC_DERATING_05T_TRC_05T_DERATE) |
+        P_Fld(0x0, SHU_AC_DERATING_05T_TRCD_05T_DERATE) | P_Fld(0x1, SHU_AC_DERATING_05T_TRP_05T_DERATE) |
+        P_Fld(0x1, SHU_AC_DERATING_05T_TRPAB_05T_DERATE) | P_Fld(0x1, SHU_AC_DERATING_05T_TRAS_05T_DERATE) |
+        P_Fld(0x0, SHU_AC_DERATING_05T_TRRD_05T_DERATE));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SREF_CTRL_0                                ral_reg_DRAMC_blk_SHU_SREF_CTRL_0                          -     @5322                                                         
+  CKEHCMD                                      uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[5:4]=2'h3                                 
+  SREF_CK_DLY                                  uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0)                
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) |
+        P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_HMR4_DVFS_CTRL0_0                          ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0                    -     @5341                                                         
+  FSPCHG_PRDCNT                                uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h32 (Mirror: 8'h00)         
+  REFRCNT                                      uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000                      
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x32, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+        P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_AC_TIME_05T_0                              ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0                        -     @5504                                                         
+  TRC_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[0:0]=1'h0                               
+  TRFCPB_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[1:1]=1'h0                               
+  TRFC_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[2:2]=1'h0                               
+  TPBR2PBR_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[3:3]=1'h0                               
+  TXP_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[4:4]=1'h0                               
+  TRTP_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[5:5]=1'h1 (Mirror: 1'h0)                
+  TRCD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[6:6]=1'h0                               
+  TRP_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[7:7]=1'h1 (Mirror: 1'h0)                
+  TRPAB_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[8:8]=1'h0                               
+  TRAS_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[9:9]=1'h0                               
+  TWR_M05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0)              
+  TRRD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[12:12]=1'h0                             
+  TFAW_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[13:13]=1'h0                             
+  TCKEPRD_05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[14:14]=1'h0                             
+  TR2PD_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[15:15]=1'h0                             
+  TWTPD_M05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[16:16]=1'h1 (Mirror: 1'h0)              
+  TMRRI_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[17:17]=1'h1 (Mirror: 1'h0)              
+  TMRWCKEL_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[18:18]=1'h0                             
+  BGTRRD_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[19:19]=1'h0                             
+  BGTCCD_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[20:20]=1'h0                             
+  BGTWTR_M05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[21:21]=1'h0                             
+  TR2W_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[22:22]=1'h0                             
+  TWTR_M05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[23:23]=1'h1 (Mirror: 1'h0)              
+  XRTR2W_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[24:24]=1'h0                             
+  TMRD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[25:25]=1'h1 (Mirror: 1'h0)              
+  TMRW_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[26:26]=1'h1 (Mirror: 1'h0)              
+  TMRR2MRW_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[27:27]=1'h1 (Mirror: 1'h0)              
+  TW2MRW_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[28:28]=1'h1 (Mirror: 1'h0)              
+  TR2MRW_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[29:29]=1'h0                             
+  TPBR2ACT_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[30:30]=1'h1 (Mirror: 1'h0)              
+  XRTW2R_M05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[31:31]=1'h0                             
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T,
+        P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTWTR_M05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T));
+
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TXP_05T) |
+        P_Fld(0x1, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRCD_05T) |
+        P_Fld(0x1, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTPD_M05T) |
+        P_Fld(0x1, SHU_AC_TIME_05T_TMRRI_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRWCKEL_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTR_M05T) |
+        P_Fld(0x1, SHU_AC_TIME_05T_TMRD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRW_05T) |
+        P_Fld(0x1, SHU_AC_TIME_05T_TMRR2MRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TW2MRW_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TPBR2ACT_05T));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM_XRT_0                                ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0                          -     @5497                                                         
+  XRTR2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[4:0]=5'h03 (Mirror: 5'h01)                
+  XRTR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[13:8]=6'h03 (Mirror: 6'h01)               
+  XRTW2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[19:16]=4'h3 (Mirror: 4'h1)                
+  XRTW2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[28:24]=5'h04 (Mirror: 5'h01)              
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x03, SHU_ACTIM_XRT_XRTR2R) |
+        P_Fld(0x03, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x3, SHU_ACTIM_XRT_XRTW2R) |
+        P_Fld(0x04, SHU_ACTIM_XRT_XRTW2W));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM0_0                                   ral_reg_DRAMC_blk_SHU_ACTIM0_0                             -     @5443                                                         
+  TWTR                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[5:0]=6'h04 (Mirror: 6'h01)                   
+  TWR                                          uvm_reg_field                                              ...    RW SHU_ACTIM0_0[15:8]=8'h07 (Mirror: 8'h06)                  
+  TRRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[18:16]=3'h1 (Mirror: 3'h0)                   
+  TRCD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[27:24]=4'h4 (Mirror: 4'h2)                   
+  CKELCKCNT                                    uvm_reg_field                                              ...    RW SHU_ACTIM0_0[31:28]=4'h2 (Mirror: 4'h0)                   
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x04, SHU_ACTIM0_TWTR) |
+        P_Fld(0x07, SHU_ACTIM0_TWR) | P_Fld(0x1, SHU_ACTIM0_TRRD) |
+        P_Fld(0x4, SHU_ACTIM0_TRCD) | P_Fld(0x2, SHU_ACTIM0_CKELCKCNT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM1_0                                   ral_reg_DRAMC_blk_SHU_ACTIM1_0                             -     @5451                                                         
+  TRPAB                                        uvm_reg_field                                              ...    RW SHU_ACTIM1_0[3:0]=4'h3 (Mirror: 4'ha)                     
+  TMRWCKEL                                     uvm_reg_field                                              ...    RW SHU_ACTIM1_0[7:4]=4'h4 (Mirror: 4'h8)                     
+  TRP                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[11:8]=4'h2                                   
+  TRAS                                         uvm_reg_field                                              ...    RW SHU_ACTIM1_0[21:16]=6'h00 (Mirror: 6'h04)                 
+  TRC                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[28:24]=5'h00 (Mirror: 5'h05)                 
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x3, SHU_ACTIM1_TRPAB) |
+        P_Fld(0x4, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x2, SHU_ACTIM1_TRP) |
+        P_Fld(0x00, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM2_0                                   ral_reg_DRAMC_blk_SHU_ACTIM2_0                             -     @5459                                                         
+  TXP                                          uvm_reg_field                                              ...    RW SHU_ACTIM2_0[3:0]=4'h0                                    
+  TMRRI                                        uvm_reg_field                                              ...    RW SHU_ACTIM2_0[8:4]=5'h05 (Mirror: 5'h0e)                   
+  TRTP                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[14:12]=3'h0                                  
+  TR2W                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[21:16]=6'h03 (Mirror: 6'h00)                 
+  TFAW                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[28:24]=5'h00 (Mirror: 5'h05)                 
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x0, SHU_ACTIM2_TXP) |
+        P_Fld(0x05, SHU_ACTIM2_TMRRI) | P_Fld(0x0, SHU_ACTIM2_TRTP) |
+        P_Fld(0x03, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM3_0                                   ral_reg_DRAMC_blk_SHU_ACTIM3_0                             -     @5467                                                         
+  TRFCPB                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[7:0]=8'h1a (Mirror: 8'h00)                   
+  MANTMRR                                      uvm_reg_field                                              ...    RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0)                    
+  TR2MRR                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0)                   
+  TRFC                                         uvm_reg_field                                              ...    RW SHU_ACTIM3_0[23:16]=8'h40 (Mirror: 8'h00)                 
+  TWTR_L                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[29:24]=6'h00                                 
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x1a, SHU_ACTIM3_TRFCPB) | 
+        P_Fld(0x4, SHU_ACTIM3_TR2MRR) | P_Fld(0x40, SHU_ACTIM3_TRFC));
+#endif
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x4, SHU_ACTIM3_MANTMRR) |
+        P_Fld(0x00, SHU_ACTIM3_TWTR_L));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM4_0                                   ral_reg_DRAMC_blk_SHU_ACTIM4_0                             -     @5475                                                         
+  TXREFCNT                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[9:0]=10'h04e (Mirror: 10'h028)               
+  TMRR2MRW                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[15:10]=6'h07 (Mirror: 6'h00)                 
+  TMRR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM4_0[21:16]=6'h05 (Mirror: 6'h00)                 
+  TZQCS                                        uvm_reg_field                                              ...    RW SHU_ACTIM4_0[31:24]=8'h10 (Mirror: 8'h00)                 
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x04e, SHU_ACTIM4_TXREFCNT) |
+        P_Fld(0x07, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x05, SHU_ACTIM4_TMRR2W) |
+        P_Fld(0x10, SHU_ACTIM4_TZQCS));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM5_0                                   ral_reg_DRAMC_blk_SHU_ACTIM5_0                             -     @5482                                                         
+  TR2PD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[6:0]=7'h08 (Mirror: 7'h00)                   
+  TWTPD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[14:8]=7'h09 (Mirror: 7'h00)                  
+  TPBR2PBR                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[23:16]=8'h0b (Mirror: 8'h00)                 
+  TPBR2ACT                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[29:28]=2'h0                                  
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x08, SHU_ACTIM5_TR2PD) |
+        P_Fld(0x09, SHU_ACTIM5_TWTPD) | P_Fld(0x0b, SHU_ACTIM5_TPBR2PBR) |
+        P_Fld(0x0, SHU_ACTIM5_TPBR2ACT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM6_0                                   ral_reg_DRAMC_blk_SHU_ACTIM6_0                             -     @5489                                                         
+  TZQLAT2                                      uvm_reg_field                                              ...    RW SHU_ACTIM6_0[4:0]=5'h06 (Mirror: 5'h1f)                   
+  TMRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[11:8]=4'h3 (Mirror: 4'h0)                    
+  TMRW                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[15:12]=4'h2 (Mirror: 4'h0)                   
+  TW2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[25:20]=6'h06 (Mirror: 6'h00)                 
+  TR2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[31:26]=6'h09 (Mirror: 6'h13)                 
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x06, SHU_ACTIM6_TZQLAT2) |
+        P_Fld(0x3, SHU_ACTIM6_TMRD) | P_Fld(0x2, SHU_ACTIM6_TMRW) |
+        P_Fld(0x06, SHU_ACTIM6_TW2MRW) | P_Fld(0x09, SHU_ACTIM6_TR2MRW));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_CKECTRL_0                                  ral_reg_DRAMC_blk_SHU_CKECTRL_0                            -     @5567                                                         
+  TPDE_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0)                    
+  TPDX_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[1:1]=1'h0                                   
+  TPDE                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[14:12]=3'h1                                 
+  TPDX                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[18:16]=3'h1                                 
+  TCKEPRD                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[22:20]=3'h1 (Mirror: 3'h2)                  
+  TCKESRX                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0)                  
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) |
+        P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) |
+        P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x1, SHU_CKECTRL_TCKEPRD));
+#endif
+
+vIO32WriteFldAlign(DRAMC_REG_SHU_CKECTRL, 0x3, SHU_CKECTRL_TCKESRX);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_0                                     ral_reg_DRAMC_blk_SHU_MISC_0                               -     @5671                                                         
+  REQQUE_MAXCNT                                uvm_reg_field                                              ...    RW SHU_MISC_0[3:0]=4'h2                                      
+  DCMDLYREF                                    uvm_reg_field                                              ...    RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4)                     
+  DAREFEN                                      uvm_reg_field                                              ...    RW SHU_MISC_0[30:30]=1'h0                                    
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x7, SHU_MISC_DCMDLYREF) |
+        P_Fld(0x0, SHU_MISC_DAREFEN));
+
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldAlign(DRAMC_REG_SHU_MISC, 0x2, SHU_MISC_REQQUE_MAXCNT);
+
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter.
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit.
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ8_0                            -     @8226                                                         
+  R_DMRXDVS_UPD_FORCE_CYC_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[14:0]=15'h0063 (Mirror: 15'h0000)            
+  R_DMRXDVS_UPD_FORCE_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[15:15]=1'h0                                  
+  R_DMRANK_RXDLY_PIPE_CG_IG_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[19:19]=1'h0                                  
+  R_RMRODTEN_CG_IG_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[20:20]=1'h0                                  
+  R_RMRX_TOPHY_CG_IG_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)                   
+  R_DMRXDVS_RDSEL_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[22:22]=1'h0                                  
+  R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0            uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[23:23]=1'h0                                  
+  R_DMRXDLY_CG_IG_B0                           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)                   
+  R_DMDQSIEN_FLAG_SYNC_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[26:26]=1'h0                                  
+  R_DMDQSIEN_FLAG_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[27:27]=1'h0                                  
+  R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0               uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[28:28]=1'h0                                  
+  R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[29:29]=1'h0                                  
+  R_DMRANK_PIPE_CG_IG_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[30:30]=1'h0                                  
+  R_DMRANK_CHG_PIPE_CG_IG_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[31:31]=1'h0                                  
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+        P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+#endif
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0063, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0));
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ8_0                            -     @9633                                                         
+  R_DMRXDVS_UPD_FORCE_CYC_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[14:0]=15'h0063 (Mirror: 15'h0000)            
+  R_DMRXDVS_UPD_FORCE_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[15:15]=1'h0                                  
+  R_DMRANK_RXDLY_PIPE_CG_IG_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[19:19]=1'h0                                  
+  R_RMRODTEN_CG_IG_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[20:20]=1'h0                                  
+  R_RMRX_TOPHY_CG_IG_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)                   
+  R_DMRXDVS_RDSEL_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[22:22]=1'h0                                  
+  R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1            uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[23:23]=1'h0                                  
+  R_DMRXDLY_CG_IG_B1                           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)                   
+  R_DMDQSIEN_FLAG_SYNC_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[26:26]=1'h0                                  
+  R_DMDQSIEN_FLAG_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[27:27]=1'h0                                  
+  R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1               uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[28:28]=1'h0                                  
+  R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[29:29]=1'h0                                  
+  R_DMRANK_PIPE_CG_IG_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[30:30]=1'h0                                  
+  R_DMRANK_CHG_PIPE_CG_IG_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[31:31]=1'h0                                  
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+        P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+#endif
+
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0063, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ5_0                            -     @8126                                                         
+  RG_RX_ARDQ_VREF_SEL_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[5:0]=6'h0e                                   
+  RG_RX_ARDQ_VREF_BYPASS_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[6:6]=1'h0                                    
+  RG_ARPI_FB_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[13:8]=6'h00                                  
+  RG_RX_ARDQS0_DQSIEN_DLY_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[18:16]=3'h0                                  
+  RG_RX_ARDQS_DQSIEN_RB_DLY_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[19:19]=1'h0                                  
+  RG_RX_ARDQS0_DVS_DLY_B0                      uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[23:20]=4'h5 (Mirror: 4'h0)                   
+  RG_RX_ARDQ_FIFO_DQSI_DLY_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[31:29]=3'h0                                  
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) |
+        P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) |
+        P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) |
+        P_Fld(0x5, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ5_0                            -     @9533                                                         
+  RG_RX_ARDQ_VREF_SEL_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[5:0]=6'h0e                                   
+  RG_RX_ARDQ_VREF_BYPASS_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[6:6]=1'h0                                    
+  RG_ARPI_FB_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[13:8]=6'h00                                  
+  RG_RX_ARDQS0_DQSIEN_DLY_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[18:16]=3'h0                                  
+  RG_RX_ARDQS_DQSIEN_RB_DLY_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[19:19]=1'h0                                  
+  RG_RX_ARDQS0_DVS_DLY_B1                      uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[23:20]=4'h5 (Mirror: 4'h0)                   
+  RG_RX_ARDQ_FIFO_DQSI_DLY_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[31:29]=3'h0                                  
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) |
+        P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) |
+        P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) |
+        P_Fld(0x5, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0                    -     @7888                                                         
+  RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h64 (Mirror: 8'h00)           
+  RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h64 (Mirror: 8'h00)          
+  RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h64 (Mirror: 8'h00)         
+  RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h64 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x64, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | 
+        P_Fld(0x64, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x64, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+        P_Fld(0x64, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+#endif
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0                    -     @7902                                                         
+  RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h64 (Mirror: 8'h00)           
+  RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h64 (Mirror: 8'h00)          
+  RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h64 (Mirror: 8'h00)         
+  RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h64 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x64, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+        P_Fld(0x64, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+        P_Fld(0x64, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0                    -     @7916                                                         
+  RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h64 (Mirror: 8'h00)           
+  RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h64 (Mirror: 8'h00)          
+  RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h64 (Mirror: 8'h00)         
+  RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h64 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x64, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+        P_Fld(0x64, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+        P_Fld(0x64, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0                    -     @7930                                                         
+  RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h64 (Mirror: 8'h00)           
+  RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h64 (Mirror: 8'h00)          
+  RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h64 (Mirror: 8'h00)         
+  RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h64 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x64, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+        P_Fld(0x64, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+        P_Fld(0x64, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0                    -     @7944                                                         
+  RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h64 (Mirror: 8'h00)           
+  RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h64 (Mirror: 8'h00)          
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x64, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+        P_Fld(0x64, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0                    -     @7954                                                         
+  RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h0da (Mirror: 9'h000)         
+  RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h0da (Mirror: 9'h000)       
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x0da, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+        P_Fld(0x0da, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1                    -     @7895                                                         
+  RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h63 (Mirror: 8'h00)           
+  RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h63 (Mirror: 8'h00)          
+  RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h63 (Mirror: 8'h00)         
+  RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h63 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | 
+        P_Fld(0x63, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+        P_Fld(0x63, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+#endif
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1                    -     @7909                                                         
+  RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h63 (Mirror: 8'h00)           
+  RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h63 (Mirror: 8'h00)          
+  RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h63 (Mirror: 8'h00)         
+  RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h63 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+        P_Fld(0x63, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+        P_Fld(0x63, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1                    -     @7923                                                         
+  RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h63 (Mirror: 8'h00)           
+  RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h63 (Mirror: 8'h00)          
+  RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h63 (Mirror: 8'h00)         
+  RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h63 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+        P_Fld(0x63, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+        P_Fld(0x63, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1                    -     @7937                                                         
+  RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h63 (Mirror: 8'h00)           
+  RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h63 (Mirror: 8'h00)          
+  RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h63 (Mirror: 8'h00)         
+  RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h63 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+        P_Fld(0x63, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+        P_Fld(0x63, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1                    -     @7949                                                         
+  RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h63 (Mirror: 8'h00)           
+  RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h63 (Mirror: 8'h00)          
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+        P_Fld(0x63, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1                    -     @7959                                                         
+  RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h0d9 (Mirror: 9'h000)         
+  RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h0d9 (Mirror: 9'h000)       
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0d9, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+        P_Fld(0x0d9, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0                    -     @9295                                                         
+  RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h64 (Mirror: 8'h00)           
+  RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h64 (Mirror: 8'h00)          
+  RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h64 (Mirror: 8'h00)         
+  RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h64 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x64, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+        P_Fld(0x64, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
+        P_Fld(0x64, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0                    -     @9309                                                         
+  RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h64 (Mirror: 8'h00)           
+  RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h64 (Mirror: 8'h00)          
+  RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h64 (Mirror: 8'h00)         
+  RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h64 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x64, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+        P_Fld(0x64, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+        P_Fld(0x64, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0                    -     @9323                                                         
+  RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h64 (Mirror: 8'h00)           
+  RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h64 (Mirror: 8'h00)          
+  RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h64 (Mirror: 8'h00)         
+  RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h64 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x64, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+        P_Fld(0x64, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+        P_Fld(0x64, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0                    -     @9337                                                         
+  RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h64 (Mirror: 8'h00)           
+  RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h64 (Mirror: 8'h00)          
+  RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h64 (Mirror: 8'h00)         
+  RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h64 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x64, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+        P_Fld(0x64, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+        P_Fld(0x64, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0                    -     @9351                                                         
+  RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h64 (Mirror: 8'h00)           
+  RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h64 (Mirror: 8'h00)          
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+#if !CODE_SIZE_REDUCE
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x64, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+        P_Fld(0x64, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0                    -     @9361                                                         
+  RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h0da (Mirror: 9'h000)         
+  RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h0da (Mirror: 9'h000)       
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x0da, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+        P_Fld(0x0da, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1                    -     @9302                                                         
+  RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h63 (Mirror: 8'h00)           
+  RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h63 (Mirror: 8'h00)          
+  RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h63 (Mirror: 8'h00)         
+  RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h63 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+        P_Fld(0x63, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
+        P_Fld(0x63, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1                    -     @9316                                                         
+  RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h63 (Mirror: 8'h00)           
+  RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h63 (Mirror: 8'h00)          
+  RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h63 (Mirror: 8'h00)         
+  RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h63 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+        P_Fld(0x63, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+        P_Fld(0x63, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1                    -     @9330                                                         
+  RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h63 (Mirror: 8'h00)           
+  RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h63 (Mirror: 8'h00)          
+  RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h63 (Mirror: 8'h00)         
+  RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h63 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+        P_Fld(0x63, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+        P_Fld(0x63, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1                    -     @9344                                                         
+  RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h63 (Mirror: 8'h00)           
+  RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h63 (Mirror: 8'h00)          
+  RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h63 (Mirror: 8'h00)         
+  RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h63 (Mirror: 8'h00)         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+        P_Fld(0x63, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+        P_Fld(0x63, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1                    -     @9356                                                         
+  RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h63 (Mirror: 8'h00)           
+  RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h63 (Mirror: 8'h00)          
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+        P_Fld(0x63, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1                    -     @9366                                                         
+  RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h0d9 (Mirror: 9'h000)         
+  RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h0d9 (Mirror: 9'h000)       
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0d9, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+        P_Fld(0x0d9, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B0_DQ9                                         ral_reg_DDRPHY_blk_B0_DQ9                                  -     @7782                                                         
+  RG_RX_ARDQ_STBEN_RESETB_B0                   uvm_reg_field                                              ...    RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0)                           
+  RG_RX_ARDQS0_STBEN_RESETB_B0                 uvm_reg_field                                              ...    RW B0_DQ9[4:4]=1'h0                                          
+  RG_RX_ARDQS0_DQSIENMODE_B0                   uvm_reg_field                                              ...    RW B0_DQ9[5:5]=1'h0                                          
+  R_DMRXDVS_R_F_DLY_RK_OPT_B0                  uvm_reg_field                                              ...    RW B0_DQ9[6:6]=1'h1                                          
+  R_DMRXFIFO_STBENCMP_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ9[7:7]=1'h0                                          
+  R_IN_GATE_EN_LOW_OPT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[15:8]=8'h00                                        
+  R_DMDQSIEN_VALID_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[18:16]=3'h0                                        
+  R_DMDQSIEN_RDSEL_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[22:20]=3'h0                                        
+  R_DMRXDVS_VALID_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[26:24]=3'h0                                        
+  R_DMRXDVS_RDSEL_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[30:28]=3'h0                                        
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
+        P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
+        P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
+        P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
+        P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
+        P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B1_DQ9                                         ral_reg_DDRPHY_blk_B1_DQ9                                  -     @9189                                                         
+  RG_RX_ARDQ_STBEN_RESETB_B1                   uvm_reg_field                                              ...    RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0)                           
+  RG_RX_ARDQS0_STBEN_RESETB_B1                 uvm_reg_field                                              ...    RW B1_DQ9[4:4]=1'h0                                          
+  RG_RX_ARDQS0_DQSIENMODE_B1                   uvm_reg_field                                              ...    RW B1_DQ9[5:5]=1'h0                                          
+  R_DMRXDVS_R_F_DLY_RK_OPT_B1                  uvm_reg_field                                              ...    RW B1_DQ9[6:6]=1'h1                                          
+  R_DMRXFIFO_STBENCMP_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ9[7:7]=1'h0                                          
+  R_IN_GATE_EN_LOW_OPT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[15:8]=8'h00                                        
+  R_DMDQSIEN_VALID_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[18:16]=3'h0                                        
+  R_DMDQSIEN_RDSEL_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[22:20]=3'h0                                        
+  R_DMRXDVS_VALID_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[26:24]=3'h0                                        
+  R_DMRXDVS_RDSEL_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[30:28]=3'h0                                        
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
+        P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
+        P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
+        P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
+        P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
+        P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B0_DQ4                                         ral_reg_DDRPHY_blk_B0_DQ4                                  -     @7711                                                         
+  RG_RX_ARDQS_EYE_R_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[6:0]=7'h6e (Mirror: 7'h00)                         
+  RG_RX_ARDQS_EYE_F_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[14:8]=7'h6e (Mirror: 7'h00)                        
+  RG_RX_ARDQ_EYE_R_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[21:16]=6'h24 (Mirror: 6'h00)                       
+  RG_RX_ARDQ_EYE_F_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[29:24]=6'h24 (Mirror: 6'h00)                       
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x6e, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) |
+        P_Fld(0x6e, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x24, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) |
+        P_Fld(0x24, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B1_DQ4                                         ral_reg_DDRPHY_blk_B1_DQ4                                  -     @9118                                                         
+  RG_RX_ARDQS_EYE_R_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[6:0]=7'h6e (Mirror: 7'h00)                         
+  RG_RX_ARDQS_EYE_F_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[14:8]=7'h6e (Mirror: 7'h00)                        
+  RG_RX_ARDQ_EYE_R_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[21:16]=6'h24 (Mirror: 6'h00)                       
+  RG_RX_ARDQ_EYE_F_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[29:24]=6'h24 (Mirror: 6'h00)                       
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x6e, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) |
+        P_Fld(0x6e, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x24, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) |
+        P_Fld(0x24, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B0_DQ5                                         ral_reg_DDRPHY_blk_B0_DQ5                                  -     @7718                                                         
+  RG_RX_ARDQ_EYE_VREF_SEL_B0                   uvm_reg_field                                              ...    RW B0_DQ5[13:8]=6'h0e                                        
+  RG_RX_ARDQ_VREF_EN_B0                        uvm_reg_field                                              ...    RW B0_DQ5[16:16]=1'h0                                        
+  RG_RX_ARDQ_EYE_VREF_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ5[17:17]=1'h0                                        
+  RG_RX_ARDQ_EYE_SEL_B0                        uvm_reg_field                                              ...    RW B0_DQ5[23:20]=4'h0                                        
+  RG_RX_ARDQ_EYE_EN_B0                         uvm_reg_field                                              ...    RW B0_DQ5[24:24]=1'h0                                        
+  RG_RX_ARDQ_EYE_STBEN_RESETB_B0               uvm_reg_field                                              ...    RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0)                         
+  RG_RX_ARDQS0_DVS_EN_B0                       uvm_reg_field                                              ...    RW B0_DQ5[31:31]=1'h0                                        
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x0e, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) |
+        P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) |
+        P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) |
+        P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value                                                         
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B1_DQ5                                         ral_reg_DDRPHY_blk_B1_DQ5                                  -     @9125                                                         
+  RG_RX_ARDQ_EYE_VREF_SEL_B1                   uvm_reg_field                                              ...    RW B1_DQ5[13:8]=6'h0e                                        
+  RG_RX_ARDQ_VREF_EN_B1                        uvm_reg_field                                              ...    RW B1_DQ5[16:16]=1'h0                                        
+  RG_RX_ARDQ_EYE_VREF_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ5[17:17]=1'h0                                        
+  RG_RX_ARDQ_EYE_SEL_B1                        uvm_reg_field                                              ...    RW B1_DQ5[23:20]=4'h0                                        
+  RG_RX_ARDQ_EYE_EN_B1                         uvm_reg_field                                              ...    RW B1_DQ5[24:24]=1'h0                                        
+  RG_RX_ARDQ_EYE_STBEN_RESETB_B1               uvm_reg_field                                              ...    RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0)                         
+  RG_RX_ARDQS0_DVS_EN_B1                       uvm_reg_field                                              ...    RW B1_DQ5[31:31]=1'h0                                        
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x0e, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) |
+        P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) |
+        P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) |
+        P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT
+//    Exit body
+}
+
+void sv_algorithm_assistance_LP4_400(DRAMC_CTX_T *p)
+{
+    //    Enter body
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter:
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_AC_DERATING0_0                             ral_reg_DRAMC_blk_SHU_AC_DERATING0_0                       -     @5271
+      ACDERATEEN                                   uvm_reg_field                                              ...    RW SHU_AC_DERATING0_0[0:0]=1'h0
+      TRRD_DERATE                                  uvm_reg_field                                              ...    RW SHU_AC_DERATING0_0[18:16]=3'h1 (Mirror: 3'h0)
+      TRCD_DERATE                                  uvm_reg_field                                              ...    RW SHU_AC_DERATING0_0[27:24]=4'h2 (Mirror: 4'h0)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !(CODE_SIZE_REDUCE && AC_TIMING_DERATE_ENABLE)
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING0, P_Fld(0x0, SHU_AC_DERATING0_ACDERATEEN) |
+            P_Fld(0x1, SHU_AC_DERATING0_TRRD_DERATE) | P_Fld(0x2, SHU_AC_DERATING0_TRCD_DERATE));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_AC_DERATING1_0                             ral_reg_DRAMC_blk_SHU_AC_DERATING1_0                       -     @5277
+      TRPAB_DERATE                                 uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[3:0]=4'h1 (Mirror: 4'h0)
+      TRP_DERATE                                   uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[11:8]=4'h0
+      TRAS_DERATE                                  uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[21:16]=6'h00
+      TRC_DERATE                                   uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[28:24]=5'h00
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING1, P_Fld(0x1, SHU_AC_DERATING1_TRPAB_DERATE) |
+            P_Fld(0x0, SHU_AC_DERATING1_TRP_DERATE) | P_Fld(0x00, SHU_AC_DERATING1_TRAS_DERATE) |
+            P_Fld(0x00, SHU_AC_DERATING1_TRC_DERATE));
+	#endif
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SREF_CTRL_0                                ral_reg_DRAMC_blk_SHU_SREF_CTRL_0                          -     @5055
+      CKEHCMD                                      uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[5:4]=2'h3
+      SREF_CK_DLY                                  uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) |
+            P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_HMR4_DVFS_CTRL0_0                          ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0                    -     @5074
+      FSPCHG_PRDCNT                                uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h1e (Mirror: 8'h00)
+      REFRCNT                                      uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x1e, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+            P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_AC_TIME_05T_0                              ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0                        -     @5237
+      TRC_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[0:0]=1'h0
+      TRFCPB_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[1:1]=1'h0
+      TRFC_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[2:2]=1'h0
+      TPBR2PBR_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[3:3]=1'h0
+      TXP_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[4:4]=1'h0
+      TRTP_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[5:5]=1'h0
+      TRCD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[6:6]=1'h0
+      TRP_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[7:7]=1'h0
+      TRPAB_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[8:8]=1'h0
+      TRAS_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[9:9]=1'h0
+      TWR_M05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[10:10]=1'h0
+      TRRD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[12:12]=1'h0
+      TFAW_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[13:13]=1'h0
+      TCKEPRD_05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[14:14]=1'h0
+      TR2PD_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[15:15]=1'h0
+      TWTPD_M05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[16:16]=1'h0
+      TMRRI_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[17:17]=1'h0
+      TMRWCKEL_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[18:18]=1'h0
+      BGTRRD_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[19:19]=1'h0
+      BGTCCD_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[20:20]=1'h0
+      BGTWTR_M05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[21:21]=1'h1 (Mirror: 1'h0)
+      TR2W_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[22:22]=1'h0
+      TWTR_M05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[23:23]=1'h0
+      XRTR2W_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[24:24]=1'h0
+      TMRD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[25:25]=1'h0
+      TMRW_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[26:26]=1'h0
+      TMRR2MRW_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[27:27]=1'h0
+      TW2MRW_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[28:28]=1'h0
+      TR2MRW_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[29:29]=1'h0
+      TPBR2ACT_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[30:30]=1'h0
+      XRTW2R_M05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[31:31]=1'h0
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T,
+            P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_BGTWTR_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TXP_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRCD_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TWR_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TWTPD_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TMRRI_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRWCKEL_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TWTR_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TMRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRW_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TMRR2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM_XRT_0                                ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0                          -     @5230
+      XRTR2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[4:0]=5'h05 (Mirror: 5'h01)
+      XRTR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[13:8]=6'h0a (Mirror: 6'h01)
+      XRTW2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[19:16]=4'h7 (Mirror: 4'h1)
+      XRTW2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[28:24]=5'h0a (Mirror: 5'h01)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x05, SHU_ACTIM_XRT_XRTR2R) |
+            P_Fld(0x0a, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x7, SHU_ACTIM_XRT_XRTW2R) |
+            P_Fld(0x0a, SHU_ACTIM_XRT_XRTW2W));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM0_0                                   ral_reg_DRAMC_blk_SHU_ACTIM0_0                             -     @5176
+      TWTR                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[5:0]=6'h0a (Mirror: 6'h01)
+      TWR                                          uvm_reg_field                                              ...    RW SHU_ACTIM0_0[15:8]=8'h0b (Mirror: 8'h06)
+      TRRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[18:16]=3'h1 (Mirror: 3'h0)
+      TRCD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[27:24]=4'h2
+      CKELCKCNT                                    uvm_reg_field                                              ...    RW SHU_ACTIM0_0[31:28]=4'h3 (Mirror: 4'h0)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x0a, SHU_ACTIM0_TWTR) |
+            P_Fld(0x0b, SHU_ACTIM0_TWR) | P_Fld(0x1, SHU_ACTIM0_TRRD) |
+            P_Fld(0x2, SHU_ACTIM0_TRCD));
+    #endif
+    vIO32WriteFldAlign(DRAMC_REG_SHU_ACTIM0, 0x3, SHU_ACTIM0_CKELCKCNT);
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM1_0                                   ral_reg_DRAMC_blk_SHU_ACTIM1_0                             -     @5184
+      TRPAB                                        uvm_reg_field                                              ...    RW SHU_ACTIM1_0[3:0]=4'h1 (Mirror: 4'ha)
+      TMRWCKEL                                     uvm_reg_field                                              ...    RW SHU_ACTIM1_0[7:4]=4'h7 (Mirror: 4'h8)
+      TRP                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[11:8]=4'h0 (Mirror: 4'h2)
+      TRAS                                         uvm_reg_field                                              ...    RW SHU_ACTIM1_0[21:16]=6'h00 (Mirror: 6'h04)
+      TRC                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[28:24]=5'h00 (Mirror: 5'h05)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x1, SHU_ACTIM1_TRPAB) |
+            P_Fld(0x7, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x0, SHU_ACTIM1_TRP) |
+            P_Fld(0x00, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM2_0                                   ral_reg_DRAMC_blk_SHU_ACTIM2_0                             -     @5192
+      TXP                                          uvm_reg_field                                              ...    RW SHU_ACTIM2_0[3:0]=4'h0
+      TMRRI                                        uvm_reg_field                                              ...    RW SHU_ACTIM2_0[8:4]=5'h05 (Mirror: 5'h0e)
+      TRTP                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[14:12]=3'h3 (Mirror: 3'h0)
+      TR2W                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[21:16]=6'h09 (Mirror: 6'h00)
+      TFAW                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[28:24]=5'h00 (Mirror: 5'h05)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x0, SHU_ACTIM2_TXP) |
+            P_Fld(0x05, SHU_ACTIM2_TMRRI) | P_Fld(0x3, SHU_ACTIM2_TRTP) |
+            P_Fld(0x09, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM3_0                                   ral_reg_DRAMC_blk_SHU_ACTIM3_0                             -     @5200
+      TRFCPB                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[7:0]=8'h07 (Mirror: 8'h00)
+      MANTMRR                                      uvm_reg_field                                              ...    RW SHU_ACTIM3_0[11:8]=4'h8 (Mirror: 4'h0)
+      TR2MRR                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[15:12]=4'h8 (Mirror: 4'h0)
+      TRFC                                         uvm_reg_field                                              ...    RW SHU_ACTIM3_0[23:16]=8'h1a (Mirror: 8'h00)
+      TWTR_L                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[29:24]=6'h05 (Mirror: 6'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x07, SHU_ACTIM3_TRFCPB) |
+            P_Fld(0x8, SHU_ACTIM3_TR2MRR) | P_Fld(0x1a, SHU_ACTIM3_TRFC));
+    #endif
+
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x8, SHU_ACTIM3_MANTMRR) |
+            P_Fld(0x05, SHU_ACTIM3_TWTR_L));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM4_0                                   ral_reg_DRAMC_blk_SHU_ACTIM4_0                             -     @5208
+      TXREFCNT                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[9:0]=10'h027 (Mirror: 10'h028)
+      TMRR2MRW                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[15:10]=6'h0e (Mirror: 6'h00)
+      TMRR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM4_0[21:16]=6'h0c (Mirror: 6'h00)
+      TZQCS                                        uvm_reg_field                                              ...    RW SHU_ACTIM4_0[31:24]=8'h07 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x027, SHU_ACTIM4_TXREFCNT) |
+            P_Fld(0x0e, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0c, SHU_ACTIM4_TMRR2W) |
+            P_Fld(0x07, SHU_ACTIM4_TZQCS));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM5_0                                   ral_reg_DRAMC_blk_SHU_ACTIM5_0                             -     @5215
+      TR2PD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[6:0]=7'h10 (Mirror: 7'h00)
+      TWTPD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[14:8]=7'h0f (Mirror: 7'h00)
+      TPBR2PBR                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[23:16]=8'h0b (Mirror: 8'h00)
+      TPBR2ACT                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[29:28]=2'h0
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x10, SHU_ACTIM5_TR2PD) |
+            P_Fld(0x0f, SHU_ACTIM5_TWTPD) | P_Fld(0x0b, SHU_ACTIM5_TPBR2PBR) |
+            P_Fld(0x0, SHU_ACTIM5_TPBR2ACT));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM6_0                                   ral_reg_DRAMC_blk_SHU_ACTIM6_0                             -     @5222
+      TZQLAT2                                      uvm_reg_field                                              ...    RW SHU_ACTIM6_0[4:0]=5'h04 (Mirror: 5'h1f)
+      TMRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[11:8]=4'h6 (Mirror: 4'h0)
+      TMRW                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0)
+      TW2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[25:20]=6'h0d (Mirror: 6'h00)
+      TR2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[31:26]=6'h11 (Mirror: 6'h13)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x04, SHU_ACTIM6_TZQLAT2) |
+            P_Fld(0x6, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) |
+            P_Fld(0x0d, SHU_ACTIM6_TW2MRW) | P_Fld(0x11, SHU_ACTIM6_TR2MRW));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_CKECTRL_0                                  ral_reg_DRAMC_blk_SHU_CKECTRL_0                            -     @5300
+      TPDE_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[0:0]=1'h0
+      TPDX_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[1:1]=1'h0
+      TPDE                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[14:12]=3'h3 (Mirror: 3'h1)
+      TPDX                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[18:16]=3'h3 (Mirror: 3'h1)
+      TCKEPRD                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[22:20]=3'h2
+      TCKESRX                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x0, SHU_CKECTRL_TPDE_05T) |
+            P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x3, SHU_CKECTRL_TPDE) |
+            P_Fld(0x3, SHU_CKECTRL_TPDX) | P_Fld(0x2, SHU_CKECTRL_TCKEPRD));
+    #endif
+    vIO32WriteFldAlign(DRAMC_REG_SHU_CKECTRL, 0x3, SHU_CKECTRL_TCKESRX);
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_0                                     ral_reg_DRAMC_blk_SHU_MISC_0                               -     @5404
+      REQQUE_MAXCNT                                uvm_reg_field                                              ...    RW SHU_MISC_0[3:0]=4'h2
+      DCMDLYREF                                    uvm_reg_field                                              ...    RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4)
+      DAREFEN                                      uvm_reg_field                                              ...    RW SHU_MISC_0[30:30]=1'h0
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_MISC,
+            P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldAlign(DRAMC_REG_SHU_MISC, 0x2, SHU_MISC_REQQUE_MAXCNT);
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter.
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit.
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ8_0                            -     @8224
+      R_DMRXDVS_UPD_FORCE_CYC_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[14:0]=15'h0018 (Mirror: 15'h0000)
+      R_DMRXDVS_UPD_FORCE_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[15:15]=1'h0
+      R_DMRANK_RXDLY_PIPE_CG_IG_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[19:19]=1'h0
+      R_RMRODTEN_CG_IG_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[20:20]=1'h0
+      R_RMRX_TOPHY_CG_IG_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)
+      R_DMRXDVS_RDSEL_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[22:22]=1'h0
+      R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0            uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[23:23]=1'h0
+      R_DMRXDLY_CG_IG_B0                           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)
+      R_DMDQSIEN_FLAG_SYNC_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[26:26]=1'h0
+      R_DMDQSIEN_FLAG_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[27:27]=1'h0
+      R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0               uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[28:28]=1'h0
+      R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[29:29]=1'h0
+      R_DMRANK_PIPE_CG_IG_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[30:30]=1'h0
+      R_DMRANK_CHG_PIPE_CG_IG_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[31:31]=1'h0
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+            P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+    #endif
+
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0018, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ8_0                            -     @9647
+      R_DMRXDVS_UPD_FORCE_CYC_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[14:0]=15'h0018 (Mirror: 15'h0000)
+      R_DMRXDVS_UPD_FORCE_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[15:15]=1'h0
+      R_DMRANK_RXDLY_PIPE_CG_IG_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[19:19]=1'h0
+      R_RMRODTEN_CG_IG_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[20:20]=1'h0
+      R_RMRX_TOPHY_CG_IG_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)
+      R_DMRXDVS_RDSEL_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[22:22]=1'h0
+      R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1            uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[23:23]=1'h0
+      R_DMRXDLY_CG_IG_B1                           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)
+      R_DMDQSIEN_FLAG_SYNC_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[26:26]=1'h0
+      R_DMDQSIEN_FLAG_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[27:27]=1'h0
+      R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1               uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[28:28]=1'h0
+      R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[29:29]=1'h0
+      R_DMRANK_PIPE_CG_IG_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[30:30]=1'h0
+      R_DMRANK_CHG_PIPE_CG_IG_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[31:31]=1'h0
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0018, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+            P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+    #endif
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ5_0                            -     @8124
+      RG_RX_ARDQ_VREF_SEL_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[5:0]=6'h0e
+      RG_RX_ARDQ_VREF_BYPASS_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[6:6]=1'h0
+      RG_ARPI_FB_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[13:8]=6'h00
+      RG_RX_ARDQS0_DQSIEN_DLY_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[18:16]=3'h0
+      RG_RX_ARDQS_DQSIEN_RB_DLY_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[19:19]=1'h0
+      RG_RX_ARDQS0_DVS_DLY_B0                      uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[23:20]=4'h7 (Mirror: 4'h0)
+      RG_RX_ARDQ_FIFO_DQSI_DLY_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[31:29]=3'h0
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) |
+            P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) |
+            P_Fld(0x7, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ5_0                            -     @9547
+      RG_RX_ARDQ_VREF_SEL_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[5:0]=6'h0e
+      RG_RX_ARDQ_VREF_BYPASS_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[6:6]=1'h0
+      RG_ARPI_FB_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[13:8]=6'h00
+      RG_RX_ARDQS0_DQSIEN_DLY_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[18:16]=3'h0
+      RG_RX_ARDQS_DQSIEN_RB_DLY_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[19:19]=1'h0
+      RG_RX_ARDQS0_DVS_DLY_B1                      uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[23:20]=4'h7 (Mirror: 4'h0)
+      RG_RX_ARDQ_FIFO_DQSI_DLY_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[31:29]=3'h0
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) |
+            P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) |
+            P_Fld(0x7, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0                    -     @7878
+      RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h68 (Mirror: 8'h00)
+      RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h68 (Mirror: 8'h00)
+      RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h68 (Mirror: 8'h00)
+      RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h68 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x68, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) |
+            P_Fld(0x68, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x68, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+            P_Fld(0x68, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+    #endif
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0                    -     @7892
+      RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h68 (Mirror: 8'h00)
+      RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h68 (Mirror: 8'h00)
+      RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h68 (Mirror: 8'h00)
+      RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h68 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x68, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+            P_Fld(0x68, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x68, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+            P_Fld(0x68, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0                    -     @7906
+      RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h68 (Mirror: 8'h00)
+      RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h68 (Mirror: 8'h00)
+      RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h68 (Mirror: 8'h00)
+      RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h68 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x68, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+            P_Fld(0x68, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x68, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+            P_Fld(0x68, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0                    -     @7920
+      RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h68 (Mirror: 8'h00)
+      RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h68 (Mirror: 8'h00)
+      RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h68 (Mirror: 8'h00)
+      RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h68 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x68, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+            P_Fld(0x68, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x68, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+            P_Fld(0x68, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0                    -     @7934
+      RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h68 (Mirror: 8'h00)
+      RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h68 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x68, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+            P_Fld(0x68, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+    #endif
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0                    -     @7944
+      RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h14a (Mirror: 9'h000)
+      RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h14a (Mirror: 9'h000)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x14a, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+            P_Fld(0x14a, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1                    -     @7885
+      RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'hc6 (Mirror: 8'h00)
+      RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'hc6 (Mirror: 8'h00)
+      RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'hc6 (Mirror: 8'h00)
+      RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'hc6 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc6, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) |
+            P_Fld(0xc6, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc6, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+            P_Fld(0xc6, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+    #endif
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1                    -     @7899
+      RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'hc6 (Mirror: 8'h00)
+      RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'hc6 (Mirror: 8'h00)
+      RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'hc6 (Mirror: 8'h00)
+      RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'hc6 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc6, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+            P_Fld(0xc6, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0xc6, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+            P_Fld(0xc6, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1                    -     @7913
+      RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'hc6 (Mirror: 8'h00)
+      RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'hc6 (Mirror: 8'h00)
+      RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'hc6 (Mirror: 8'h00)
+      RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'hc6 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc6, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+            P_Fld(0xc6, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0xc6, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+            P_Fld(0xc6, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1                    -     @7927
+      RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'hc6 (Mirror: 8'h00)
+      RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'hc6 (Mirror: 8'h00)
+      RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'hc6 (Mirror: 8'h00)
+      RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'hc6 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc6, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+            P_Fld(0xc6, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0xc6, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+            P_Fld(0xc6, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1                    -     @7939
+      RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'hc6 (Mirror: 8'h00)
+      RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'hc6 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc6, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+            P_Fld(0xc6, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+    #endif
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1                    -     @7949
+      RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h1a1 (Mirror: 9'h000)
+      RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h1a1 (Mirror: 9'h000)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1a1, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+            P_Fld(0x1a1, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0                    -     @9301
+      RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h06 (Mirror: 8'h00)
+      RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h06 (Mirror: 8'h00)
+      RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h06 (Mirror: 8'h00)
+      RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h06 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x06, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) |
+            P_Fld(0x06, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x06, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+            P_Fld(0x06, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
+    #endif
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0                    -     @9315
+      RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h06 (Mirror: 8'h00)
+      RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h06 (Mirror: 8'h00)
+      RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h06 (Mirror: 8'h00)
+      RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h06 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x06, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+            P_Fld(0x06, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x06, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+            P_Fld(0x06, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0                    -     @9329
+      RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h06 (Mirror: 8'h00)
+      RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h06 (Mirror: 8'h00)
+      RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h06 (Mirror: 8'h00)
+      RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h06 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x06, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+            P_Fld(0x06, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x06, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+            P_Fld(0x06, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0                    -     @9343
+      RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h06 (Mirror: 8'h00)
+      RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h06 (Mirror: 8'h00)
+      RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h06 (Mirror: 8'h00)
+      RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h06 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x06, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+            P_Fld(0x06, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x06, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+            P_Fld(0x06, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0                    -     @9357
+      RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h06 (Mirror: 8'h00)
+      RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h06 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x06, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+            P_Fld(0x06, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+    #endif
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0                    -     @9367
+      RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h0e5 (Mirror: 9'h000)
+      RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h0e5 (Mirror: 9'h000)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x0e5, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+            P_Fld(0x0e5, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1                    -     @9308
+      RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h65 (Mirror: 8'h00)
+      RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h65 (Mirror: 8'h00)
+      RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h65 (Mirror: 8'h00)
+      RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h65 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x65, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) |
+            P_Fld(0x65, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x65, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+            P_Fld(0x65, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
+    #endif
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1                    -     @9322
+      RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h65 (Mirror: 8'h00)
+      RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h65 (Mirror: 8'h00)
+      RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h65 (Mirror: 8'h00)
+      RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h65 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x65, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+            P_Fld(0x65, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x65, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+            P_Fld(0x65, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1                    -     @9336
+      RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h65 (Mirror: 8'h00)
+      RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h65 (Mirror: 8'h00)
+      RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h65 (Mirror: 8'h00)
+      RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h65 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x65, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+            P_Fld(0x65, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x65, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+            P_Fld(0x65, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1                    -     @9350
+      RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h65 (Mirror: 8'h00)
+      RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h65 (Mirror: 8'h00)
+      RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h65 (Mirror: 8'h00)
+      RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h65 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x65, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+            P_Fld(0x65, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x65, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+            P_Fld(0x65, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1                    -     @9362
+      RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h65 (Mirror: 8'h00)
+      RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h65 (Mirror: 8'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x65, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+            P_Fld(0x65, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+    #endif
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1                    -     @9372
+      RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h141 (Mirror: 9'h000)
+      RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h141 (Mirror: 9'h000)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x141, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+            P_Fld(0x141, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ9                                         ral_reg_DDRPHY_blk_B0_DQ9                                  -     @7772
+      RG_RX_ARDQ_STBEN_RESETB_B0                   uvm_reg_field                                              ...    RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0)
+      RG_RX_ARDQS0_STBEN_RESETB_B0                 uvm_reg_field                                              ...    RW B0_DQ9[4:4]=1'h0
+      RG_RX_ARDQS0_DQSIENMODE_B0                   uvm_reg_field                                              ...    RW B0_DQ9[5:5]=1'h0
+      R_DMRXDVS_R_F_DLY_RK_OPT_B0                  uvm_reg_field                                              ...    RW B0_DQ9[6:6]=1'h1
+      R_DMRXFIFO_STBENCMP_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ9[7:7]=1'h0
+      R_IN_GATE_EN_LOW_OPT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[15:8]=8'h00
+      R_DMDQSIEN_VALID_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[18:16]=3'h0
+      R_DMDQSIEN_RDSEL_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[22:20]=3'h0
+      R_DMRXDVS_VALID_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[26:24]=3'h0
+      R_DMRXDVS_RDSEL_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[30:28]=3'h0
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
+            P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
+            P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
+            P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
+            P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
+            P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ9                                         ral_reg_DDRPHY_blk_B1_DQ9                                  -     @9195
+      RG_RX_ARDQ_STBEN_RESETB_B1                   uvm_reg_field                                              ...    RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0)
+      RG_RX_ARDQS0_STBEN_RESETB_B1                 uvm_reg_field                                              ...    RW B1_DQ9[4:4]=1'h0
+      RG_RX_ARDQS0_DQSIENMODE_B1                   uvm_reg_field                                              ...    RW B1_DQ9[5:5]=1'h0
+      R_DMRXDVS_R_F_DLY_RK_OPT_B1                  uvm_reg_field                                              ...    RW B1_DQ9[6:6]=1'h1
+      R_DMRXFIFO_STBENCMP_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ9[7:7]=1'h0
+      R_IN_GATE_EN_LOW_OPT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[15:8]=8'h00
+      R_DMDQSIEN_VALID_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[18:16]=3'h0
+      R_DMDQSIEN_RDSEL_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[22:20]=3'h0
+      R_DMRXDVS_VALID_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[26:24]=3'h0
+      R_DMRXDVS_RDSEL_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[30:28]=3'h0
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
+            P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
+            P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
+            P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
+            P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
+            P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ4                                         ral_reg_DDRPHY_blk_B0_DQ4                                  -     @7701
+      RG_RX_ARDQS_EYE_R_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[6:0]=7'h76 (Mirror: 7'h00)
+      RG_RX_ARDQS_EYE_F_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[14:8]=7'h76 (Mirror: 7'h00)
+      RG_RX_ARDQ_EYE_R_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[21:16]=6'h28 (Mirror: 6'h00)
+      RG_RX_ARDQ_EYE_F_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[29:24]=6'h28 (Mirror: 6'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x76, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) |
+            P_Fld(0x76, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x28, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) |
+            P_Fld(0x28, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ4                                         ral_reg_DDRPHY_blk_B1_DQ4                                  -     @9124
+      RG_RX_ARDQS_EYE_R_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[6:0]=7'h14 (Mirror: 7'h00)
+      RG_RX_ARDQS_EYE_F_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[14:8]=7'h14 (Mirror: 7'h00)
+      RG_RX_ARDQ_EYE_R_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[21:16]=6'h06 (Mirror: 6'h00)
+      RG_RX_ARDQ_EYE_F_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[29:24]=6'h06 (Mirror: 6'h00)
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x14, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) |
+            P_Fld(0x14, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x06, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) |
+            P_Fld(0x06, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1));
+    /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ5                                         ral_reg_DDRPHY_blk_B0_DQ5                                  -     @7708
+      RG_RX_ARDQ_EYE_VREF_SEL_B0                   uvm_reg_field                                              ...    RW B0_DQ5[13:8]=6'h0e
+      RG_RX_ARDQ_VREF_EN_B0                        uvm_reg_field                                              ...    RW B0_DQ5[16:16]=1'h0
+      RG_RX_ARDQ_EYE_VREF_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ5[17:17]=1'h0
+      RG_RX_ARDQ_EYE_SEL_B0                        uvm_reg_field                                              ...    RW B0_DQ5[23:20]=4'h0
+      RG_RX_ARDQ_EYE_EN_B0                         uvm_reg_field                                              ...    RW B0_DQ5[24:24]=1'h0
+  RG_RX_ARDQ_EYE_STBEN_RESETB_B0               uvm_reg_field                                              ...    RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0)
+  RG_RX_ARDQS0_DVS_EN_B0                       uvm_reg_field                                              ...    RW B0_DQ5[31:31]=1'h0
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x0e, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) |
+        P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) |
+        P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) |
+        P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0));
+/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B1_DQ5                                         ral_reg_DDRPHY_blk_B1_DQ5                                  -     @9131
+  RG_RX_ARDQ_EYE_VREF_SEL_B1                   uvm_reg_field                                              ...    RW B1_DQ5[13:8]=6'h0e
+  RG_RX_ARDQ_VREF_EN_B1                        uvm_reg_field                                              ...    RW B1_DQ5[16:16]=1'h0
+  RG_RX_ARDQ_EYE_VREF_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ5[17:17]=1'h0
+  RG_RX_ARDQ_EYE_SEL_B1                        uvm_reg_field                                              ...    RW B1_DQ5[23:20]=4'h0
+  RG_RX_ARDQ_EYE_EN_B1                         uvm_reg_field                                              ...    RW B1_DQ5[24:24]=1'h0
+  RG_RX_ARDQ_EYE_STBEN_RESETB_B1               uvm_reg_field                                              ...    RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0)
+  RG_RX_ARDQS0_DVS_EN_B1                       uvm_reg_field                                              ...    RW B1_DQ5[31:31]=1'h0
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x0e, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) |
+        P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) |
+        P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) |
+        P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT
+//    Exit body
+}
+
+void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p)
+{
+    //    Enter body
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter:
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_RDSEL_TRACK_0                         ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0                  -     @13206                                                     
+      DMDATLAT_i                                   uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h0e (Mirror: 5'h00)      
+      RDSEL_HWSAVE_MSK                             uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0)        
+      RDSEL_TRACK_EN                               uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0                       
+      SHU_GW_THRD_NEG                              uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hff5 (Mirror: 12'h000) 
+      SHU_GW_THRD_POS                              uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h00b (Mirror: 12'h000)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x0e, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) |
+            P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) |
+            P_Fld(0xff5, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x00b, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RDAT_0                                ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0                         -     @13076                                                     
+      DATLAT                                       uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[4:0]=5'h0e (Mirror: 5'h00)             
+      DATLAT_DSEL                                  uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[12:8]=5'h0e (Mirror: 5'h00)            
+      DATLAT_DSEL_PHY                              uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[20:16]=5'h0e (Mirror: 5'h00)           
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x0e, MISC_SHU_RDAT_DATLAT) |
+            P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
+    #endif
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_PHY_RX_CTRL_0                         ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0                  -     @13012                                                     
+      RANK_RXDLY_UPDLAT_EN                         uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0)        
+      RANK_RXDLY_UPD_OFFSET                        uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0)       
+      RX_IN_GATE_EN_PRE_OFFSET                     uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h1 (Mirror: 2'h0)      
+      RX_IN_GATE_EN_HEAD                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h0                     
+      RX_IN_GATE_EN_TAIL                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0)      
+      RX_IN_BUFF_EN_HEAD                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h0                     
+      RX_IN_BUFF_EN_TAIL                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0                     
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) |
+            P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) |
+            P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) |
+            P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RANKCTL_0                             ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0                      -     @13002                                                     
+      RANKINCTL_RXDLY                              uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[3:0]=4'h3 (Mirror: 4'h0)            
+      RANK_RXDLY_OPT                               uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[4:4]=1'h1                           
+      RANKSEL_SELPH_FRUN                           uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[15:15]=1'h1 (Mirror: 1'h0)          
+      RANKINCTL_STB                                uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[19:16]=4'h4 (Mirror: 4'h0)          
+      RANKINCTL                                    uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[23:20]=4'h4 (Mirror: 4'h0)          
+      RANKINCTL_ROOT1                              uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[27:24]=4'h4 (Mirror: 4'h0)          
+      RANKINCTL_PHY                                uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[31:28]=4'h6 (Mirror: 4'h0)          
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x3, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) |
+            P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x1, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) |
+            P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_STB));
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL) |
+            P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_PHY));
+    #endif
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RANK_SEL_LAT_0                        ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0                 -     @13229                                                     
+      RANK_SEL_LAT_B0                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h4 (Mirror: 4'h0)       
+      RANK_SEL_LAT_B1                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h4 (Mirror: 4'h0)       
+      RANK_SEL_LAT_CA                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h4 (Mirror: 4'h0)      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
+            P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
+
+    #if !CODE_SIZE_REDUCE
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCTL_0_0                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0                  -     @12823                                                     
+      DQSINCTL                                     uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h6 (Mirror: 4'h0)        
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x6, MISC_SHU_RK_DQSCTL_DQSINCTL);
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCTL_0_1                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1                  -     @12827                                                     
+      DQSINCTL                                     uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h6 (Mirror: 4'h0)        
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x6, MISC_SHU_RK_DQSCTL_DQSINCTL);
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0         -     @8022                                                       
+      DQSIEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h6 (Mirror: 4'h0)
+      DQSIEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h8 (Mirror: 4'h0)
+      DQSIEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0             
+      DQSIEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0             
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x6, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+            P_Fld(0x8, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_PI_DLY_0_0                    ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0             -     @8036                                                       
+      DQSIEN_PI_B0                                 uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00)  
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0b, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1         -     @8029                                                       
+      DQSIEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h7 (Mirror: 4'h0)
+      DQSIEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h9 (Mirror: 4'h0)
+      DQSIEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0             
+      DQSIEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h0             
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+            P_Fld(0x9, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_PI_DLY_0_1                    ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1             -     @8040                                                       
+      DQSIEN_PI_B0                                 uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h1f (Mirror: 7'h00)  
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1f, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0         -     @9429                                                       
+      DQSIEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h6 (Mirror: 4'h0)
+      DQSIEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h8 (Mirror: 4'h0)
+      DQSIEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0             
+      DQSIEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0             
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x6, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+            P_Fld(0x8, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_PI_DLY_0_0                    ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0             -     @9443                                                       
+      DQSIEN_PI_B1                                 uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00)  
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0b, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1         -     @9436                                                       
+      DQSIEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h7 (Mirror: 4'h0)
+      DQSIEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h9 (Mirror: 4'h0)
+      DQSIEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0             
+      DQSIEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h0             
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+            P_Fld(0x9, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_PI_DLY_0_1                    ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1             -     @9447                                                       
+      DQSIEN_PI_B1                                 uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h1f (Mirror: 7'h00)  
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1f, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_ODTCTRL_0                             ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0                      -     @13022                                                      
+      RODTEN                                       uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0)             
+      RODTENSTB_SELPH_CG_IG                        uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[1:1]=1'h0                            
+      RODT_LAT                                     uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[7:4]=4'h4 (Mirror: 4'h0)             
+      RODTEN_SELPH_FRUN                            uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[15:15]=1'h0                          
+      RODTDLY_LAT_OPT                              uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[25:24]=2'h0                          
+      FIXRODT                                      uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[27:27]=1'h0                          
+      RODTEN_OPT                                   uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[29:29]=1'h1                          
+      RODTE2                                       uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0)           
+      RODTE                                        uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0)           
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) |
+            P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_ODTCTRL, 0x4, MISC_SHU_ODTCTRL_RODT_LAT);
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ7_0                            -     @8206                                                       
+      R_DMRANKRXDVS_B0                             uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[3:0]=4'h0                                  
+      R_DMDQMDBI_EYE_SHU_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[6:6]=1'h0                                  
+      R_DMDQMDBI_SHU_B0                            uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[7:7]=1'h0                                  
+      R_DMRXDVS_DQM_FLAGSEL_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[11:8]=4'h0                                 
+      R_DMRXDVS_PBYTE_FLAG_OPT_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[12:12]=1'h0                                
+      R_DMRXDVS_PBYTE_DQM_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[13:13]=1'h0                                
+      R_DMRXTRACK_DQM_EN_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[14:14]=1'h0                                
+      R_DMRODTEN_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)                 
+      R_DMARPI_CG_FB2DLL_DCM_EN_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[16:16]=1'h0                                
+      R_DMTX_ARPI_CG_DQ_NEW_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[17:17]=1'h0                                
+      R_DMTX_ARPI_CG_DQS_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[18:18]=1'h0                                
+      R_DMTX_ARPI_CG_DQM_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[19:19]=1'h0                                
+      R_LP4Y_SDN_MODE_DQS0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[20:20]=1'h0                                
+      R_DMRXRANK_DQ_EN_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)                 
+      R_DMRXRANK_DQ_LAT_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0)                 
+      R_DMRXRANK_DQS_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)                 
+      R_DMRXRANK_DQS_LAT_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[31:29]=3'h0                                
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ7_0                            -     @9613                                                       
+      R_DMRANKRXDVS_B1                             uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[3:0]=4'h0                                  
+      R_DMDQMDBI_EYE_SHU_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[6:6]=1'h0                                  
+      R_DMDQMDBI_SHU_B1                            uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[7:7]=1'h0                                  
+      R_DMRXDVS_DQM_FLAGSEL_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[11:8]=4'h0                                 
+      R_DMRXDVS_PBYTE_FLAG_OPT_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[12:12]=1'h0                                
+      R_DMRXDVS_PBYTE_DQM_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[13:13]=1'h0                                
+      R_DMRXTRACK_DQM_EN_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[14:14]=1'h0                                
+      R_DMRODTEN_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)                 
+      R_DMARPI_CG_FB2DLL_DCM_EN_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[16:16]=1'h0                                
+      R_DMTX_ARPI_CG_DQ_NEW_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[17:17]=1'h0                                
+      R_DMTX_ARPI_CG_DQS_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[18:18]=1'h0                                
+      R_DMTX_ARPI_CG_DQM_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[19:19]=1'h0                                
+      R_LP4Y_SDN_MODE_DQS1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[20:20]=1'h0                                
+      R_DMRXRANK_DQ_EN_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)                 
+      R_DMRXRANK_DQ_LAT_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0)                 
+      R_DMRXRANK_DQS_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)                 
+      R_DMRXRANK_DQS_LAT_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[31:29]=3'h0                                
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_RX_PIPE_CTRL_0                        ral_reg_DDRPHY_blk_SHU_MISC_RX_PIPE_CTRL_0                 -     @13176                                                      
+      RX_PIPE_BYPASS_EN                            uvm_reg_field                                              ...    RW SHU_MISC_RX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0)        
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x1, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN);
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0         -     @8044                                                       
+      RODTEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h1 (Mirror: 3'h0)
+      RODTEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h1 (Mirror: 3'h0)
+      RODTEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0             
+      RODTEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0             
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+            P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1         -     @8051                                                       
+      RODTEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h2 (Mirror: 3'h0)
+      RODTEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h2 (Mirror: 3'h0)
+      RODTEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0             
+      RODTEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0             
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+            P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0         -     @9451                                                       
+      RODTEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h1 (Mirror: 3'h0)
+      RODTEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h1 (Mirror: 3'h0)
+      RODTEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0             
+      RODTEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0             
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+            P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1         -     @9458                                                       
+      RODTEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h2 (Mirror: 3'h0)
+      RODTEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h2 (Mirror: 3'h0)
+      RODTEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0             
+      RODTEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0             
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+            P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RX_CG_SET0_0                               ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0                         -     @5628                                                       
+      DLE_LAST_EXTEND3                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[0:0]=1'h0                              
+      READ_START_EXTEND3                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[1:1]=1'h0                              
+      DLE_LAST_EXTEND2                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0)               
+      READ_START_EXTEND2                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0)               
+      DLE_LAST_EXTEND1                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0)               
+      READ_START_EXTEND1                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0)               
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) |
+            P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) |
+            P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
+            P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1));
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_RANK_SEL_STB_0                        ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0                 -     @13192                                                      
+      RANK_SEL_STB_EN                              uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0)        
+      RANK_SEL_STB_EN_B23                          uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0                       
+      RANK_SEL_STB_SERMODE                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0                       
+      RANK_SEL_STB_TRACK                           uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0)        
+      RANK_SEL_RXDLY_TRACK                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0                       
+      RANK_SEL_STB_PHASE_EN                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h0                       
+      RANK_SEL_PHSINCTL                            uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h5 (Mirror: 4'h0)       
+      RANK_SEL_STB_UI_PLUS                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0                     
+      RANK_SEL_STB_MCK_PLUS                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0                     
+      RANK_SEL_STB_UI_MINUS                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h0                     
+      RANK_SEL_STB_MCK_MINUS                       uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h1 (Mirror: 4'h0)      
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) |
+            P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) |
+            P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) |
+            P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x5, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) |
+            P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) |
+            P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCAL_0_0                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0                  -     @12841                                                      
+      DQSIENLLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00)       
+      DQSIENLLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0)         
+      DQSIENHLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00)      
+      DQSIENHLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCAL_0_1                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1                  -     @12848                                                      
+      DQSIENLLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00)       
+      DQSIENLLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0)         
+      DQSIENHLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00)      
+      DQSIENHLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_INI_UIPI_0_0                         ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0                  -     @8000                                                       
+      CURR_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)       
+      CURR_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h06 (Mirror: 8'h00)      
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+            P_Fld(0x06, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_INI_UIPI_0_0                         ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0                  -     @9407                                                       
+      CURR_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)       
+      CURR_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h06 (Mirror: 8'h00)      
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+            P_Fld(0x06, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_INI_UIPI_0_1                         ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1                  -     @8005                                                       
+      CURR_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h1f (Mirror: 7'h00)       
+      CURR_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h07 (Mirror: 8'h00)      
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1f, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+            P_Fld(0x07, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_INI_UIPI_0_1                         ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1                  -     @9412                                                       
+      CURR_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h1f (Mirror: 7'h00)       
+      CURR_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h07 (Mirror: 8'h00)      
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1f, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+            P_Fld(0x07, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_NEXT_INI_UIPI_0_0                    ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0             -     @8010                                                       
+      NEXT_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)  
+      NEXT_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h06 (Mirror: 8'h00) 
+      NEXT_INI_UI_P1_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h08 (Mirror: 8'h00)
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+            P_Fld(0x06, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x08, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_NEXT_INI_UIPI_0_0                    ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0             -     @9417                                                       
+      NEXT_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)  
+      NEXT_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h06 (Mirror: 8'h00) 
+      NEXT_INI_UI_P1_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h08 (Mirror: 8'h00)
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+            P_Fld(0x06, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x08, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_NEXT_INI_UIPI_0_1                    ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1             -     @8016                                                       
+      NEXT_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h1f (Mirror: 7'h00)  
+      NEXT_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h07 (Mirror: 8'h00) 
+      NEXT_INI_UI_P1_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h09 (Mirror: 8'h00)
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+            P_Fld(0x07, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x09, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_NEXT_INI_UIPI_0_1                    ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1             -     @9423                                                       
+      NEXT_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h1f (Mirror: 7'h00)  
+      NEXT_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h07 (Mirror: 8'h00) 
+      NEXT_INI_UI_P1_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h09 (Mirror: 8'h00)
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+            P_Fld(0x07, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x09, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit:
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter:
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_DQ0_0_0                              ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0                       -     @7980                                                       
+      RG_RX_ARDQS0_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0                             
+      RG_RX_ARDQS0_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0                             
+      SW_ARPI_DQ_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[13:8]=6'h18 (Mirror: 6'h00)           
+      SW_ARPI_DQM_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[21:16]=6'h18 (Mirror: 6'h00)          
+      ARPI_PBYTE_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00                          
+      DA_ARPI_DDR400_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0                           
+      DA_RX_ARDQSIEN_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0                           
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x18, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+            P_Fld(0x18, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0));
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_DQ0_0_0                              ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0                       -     @9387                                                       
+      RG_RX_ARDQS1_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0                             
+      RG_RX_ARDQS1_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0                             
+      SW_ARPI_DQ_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[13:8]=6'h18 (Mirror: 6'h00)           
+      SW_ARPI_DQM_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[21:16]=6'h18 (Mirror: 6'h00)          
+      ARPI_PBYTE_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00                          
+      DA_ARPI_DDR400_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0                           
+      DA_RX_ARDQSIEN_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0                           
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+            P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1));
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_DQ0_0_1                              ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1                       -     @7990                                                       
+      RG_RX_ARDQS0_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0                             
+      RG_RX_ARDQS0_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0                             
+      SW_ARPI_DQ_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[13:8]=6'h18 (Mirror: 6'h00)           
+      SW_ARPI_DQM_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[21:16]=6'h18 (Mirror: 6'h00)          
+      ARPI_PBYTE_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00                          
+      DA_ARPI_DDR400_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0                           
+      DA_RX_ARDQSIEN_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0                           
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x18, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+            P_Fld(0x18, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0));
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_DQ0_0_1                              ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1                       -     @9397                                                       
+      RG_RX_ARDQS1_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0                             
+      RG_RX_ARDQS1_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0                             
+      SW_ARPI_DQ_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[13:8]=6'h18 (Mirror: 6'h00)           
+      SW_ARPI_DQM_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[21:16]=6'h18 (Mirror: 6'h00)          
+      ARPI_PBYTE_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00                          
+      DA_ARPI_DDR400_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0                           
+      DA_RX_ARDQSIEN_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0                           
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+            P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1));
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_DCM_CTRL0_0                                ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0                          -     @5331                                                       
+      DDRPHY_CLK_EN_OPT                            uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0)                
+      DPHY_CMD_CLKEN_EXTCNT                        uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[10:8]=3'h3                              
+      DDRPHY_CLK_DYN_GATING_SEL                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[15:12]=4'h6 (Mirror: 4'h0)              
+      APHYPI_CKCGL_CNT                             uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[19:16]=4'h2                             
+      APHYPI_CKCGH_CNT                             uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[23:20]=4'h4                             
+      FASTWAKE2                                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[29:29]=1'h0                             
+      FASTWAKE                                     uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[31:31]=1'h1                             
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+            P_Fld(0x3, SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT) | P_Fld(0x6, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+            P_Fld(0x2, SHU_DCM_CTRL0_APHYPI_CKCGL_CNT) | P_Fld(0x5, SHU_DCM_CTRL0_APHYPI_CKCGH_CNT) |
+            P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_APHY_TX_PICG_CTRL_0                        ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0                  -     @5683                                                       
+      DDRPHY_CLK_EN_COMB_TX_PICG_CNT               uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h3 (Mirror: 4'h0)        
+      DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1             uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h0                       
+      DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0             uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h3 (Mirror: 3'h0)       
+      DPHY_TX_DCM_EXTCNT                           uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[15:12]=4'h2                     
+      DDRPHY_CLK_EN_COMB_TX_OPT                    uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0)      
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) |
+            P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) |
+            P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_APHY_TX_PICG_CTRL_0_0                    ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0              -     @5221                                                       
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h0                   
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h3 (Mirror: 3'h0)    
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+            P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_APHY_TX_PICG_CTRL_0_1                    ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1              -     @5226                                                       
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h0                   
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h3 (Mirror: 3'h0)    
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+            P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_NEW_XRW2W_CTRL_0                           ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0                     -     @5677                                                       
+      TX_PI_UPDCTL_B0                              uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h2 (Mirror: 3'h0)         
+      TX_PI_UPDCTL_B1                              uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h2 (Mirror: 3'h0)         
+      TXPI_UPD_MODE                                uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1)         
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) |
+            P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_DQS0_0                               ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0                         -     @5576                                                       
+      TXDLY_DQS0                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[2:0]=3'h4 (Mirror: 3'h1)               
+      TXDLY_DQS1                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[6:4]=3'h4 (Mirror: 3'h1)               
+      TXDLY_DQS2                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[10:8]=3'h1                             
+      TXDLY_DQS3                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[14:12]=3'h1                            
+      TXDLY_OEN_DQS0                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[18:16]=3'h3 (Mirror: 3'h1)             
+      TXDLY_OEN_DQS1                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[22:20]=3'h3 (Mirror: 3'h1)             
+      TXDLY_OEN_DQS2                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[26:24]=3'h1                            
+      TXDLY_OEN_DQS3                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[30:28]=3'h1                            
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) |
+            P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) |
+            P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ0_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0                      -     @5041                                                       
+      TXDLY_DQ0                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[2:0]=3'h4 (Mirror: 3'h1)            
+      TXDLY_DQ1                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[6:4]=3'h4 (Mirror: 3'h1)            
+      TXDLY_DQ2                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1                          
+      TXDLY_DQ3                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1                         
+      TXDLY_OEN_DQ0                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[18:16]=3'h3 (Mirror: 3'h1)          
+      TXDLY_OEN_DQ1                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[22:20]=3'h3 (Mirror: 3'h1)          
+      TXDLY_OEN_DQ2                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1                         
+      TXDLY_OEN_DQ3                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1                         
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+            P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+            P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ1_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0                      -     @5063                                                       
+      TXDLY_DQM0                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[2:0]=3'h4 (Mirror: 3'h1)            
+      TXDLY_DQM1                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[6:4]=3'h4 (Mirror: 3'h1)            
+      TXDLY_DQM2                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1                          
+      TXDLY_DQM3                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1                         
+      TXDLY_OEN_DQM0                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[18:16]=3'h3 (Mirror: 3'h1)          
+      TXDLY_OEN_DQM1                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[22:20]=3'h3 (Mirror: 3'h1)          
+      TXDLY_OEN_DQM2                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1                         
+      TXDLY_OEN_DQM3                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1                         
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+            P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+            P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ2_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0                      -     @5085                                                       
+      dly_DQ0                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[3:0]=4'h1                           
+      dly_DQ1                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[7:4]=4'h1                           
+      dly_DQ2                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1                          
+      dly_DQ3                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1                         
+      dly_oen_DQ0                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[19:16]=4'h2 (Mirror: 4'h1)          
+      dly_oen_DQ1                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[23:20]=4'h2 (Mirror: 4'h1)          
+      dly_oen_DQ2                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1                         
+      dly_oen_DQ3                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1                         
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+            P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ3_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0                      -     @5107                                                       
+      dly_DQM0                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[3:0]=4'h1                           
+      dly_DQM1                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[7:4]=4'h1                           
+      dly_DQM2                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1                          
+      dly_DQM3                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1                         
+      dly_oen_DQM0                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[19:16]=4'h2 (Mirror: 4'h1)          
+      dly_oen_DQM1                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[23:20]=4'h2 (Mirror: 4'h1)          
+      dly_oen_DQM2                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1                         
+      dly_oen_DQM3                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1                         
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+            P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ0_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1                      -     @5052                                                       
+      TXDLY_DQ0                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[2:0]=3'h4 (Mirror: 3'h1)            
+      TXDLY_DQ1                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[6:4]=3'h4 (Mirror: 3'h1)            
+      TXDLY_DQ2                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1                          
+      TXDLY_DQ3                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1                         
+      TXDLY_OEN_DQ0                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[18:16]=3'h3 (Mirror: 3'h1)          
+      TXDLY_OEN_DQ1                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[22:20]=3'h3 (Mirror: 3'h1)          
+      TXDLY_OEN_DQ2                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1                         
+      TXDLY_OEN_DQ3                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1                         
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+            P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+            P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ1_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1                      -     @5074                                                       
+      TXDLY_DQM0                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[2:0]=3'h4 (Mirror: 3'h1)            
+      TXDLY_DQM1                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[6:4]=3'h4 (Mirror: 3'h1)            
+      TXDLY_DQM2                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1                          
+      TXDLY_DQM3                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1                         
+      TXDLY_OEN_DQM0                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[18:16]=3'h3 (Mirror: 3'h1)          
+      TXDLY_OEN_DQM1                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[22:20]=3'h3 (Mirror: 3'h1)          
+      TXDLY_OEN_DQM2                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1                         
+      TXDLY_OEN_DQM3                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1                         
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+            P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+            P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ2_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1                      -     @5096                                                       
+      dly_DQ0                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[3:0]=4'h1                           
+      dly_DQ1                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[7:4]=4'h1                           
+      dly_DQ2                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1                          
+      dly_DQ3                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1                         
+      dly_oen_DQ0                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[19:16]=4'h2 (Mirror: 4'h1)          
+      dly_oen_DQ1                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[23:20]=4'h2 (Mirror: 4'h1)          
+      dly_oen_DQ2                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1                         
+      dly_oen_DQ3                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1                         
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+            P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ3_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1                      -     @5118                                                       
+      dly_DQM0                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[3:0]=4'h1                           
+      dly_DQM1                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[7:4]=4'h1                           
+      dly_DQM2                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1                          
+      dly_DQM3                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1                         
+      dly_oen_DQM0                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[19:16]=4'h2 (Mirror: 4'h1)          
+      dly_oen_DQM1                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[23:20]=4'h2 (Mirror: 4'h1)          
+      dly_oen_DQM2                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1                         
+      dly_oen_DQM3                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1                         
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+            P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL1_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0                    -     @5129                                                       
+      BOOT_ORIG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h018 (Mirror: 11'h000)   
+      BOOT_ORIG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h018 (Mirror: 11'h000)  
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+            P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL2_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0                    -     @5139                                                       
+      BOOT_TARG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h018 (Mirror: 11'h000)   
+      BOOT_TARG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h018 (Mirror: 11'h000)  
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+            P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL5_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0                    -     @5177                                                       
+      BOOT_TARG_UI_RK0_DQM0                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h018 (Mirror: 11'h000)   
+      BOOT_TARG_UI_RK0_DQM1                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h018 (Mirror: 11'h000)  
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+            P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL1_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1                    -     @5134                                                       
+      BOOT_ORIG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h018 (Mirror: 11'h000)   
+      BOOT_ORIG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h018 (Mirror: 11'h000)  
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+            P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL2_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1                    -     @5144                                                       
+      BOOT_TARG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h018 (Mirror: 11'h000)   
+      BOOT_TARG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h018 (Mirror: 11'h000)  
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+            P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL5_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1                    -     @5182                                                       
+      BOOT_TARG_UI_RK0_DQM0                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h018 (Mirror: 11'h000)   
+      BOOT_TARG_UI_RK0_DQM1                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h018 (Mirror: 11'h000)  
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+            P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_PI_0_0                                   ral_reg_DRAMC_blk_SHURK_PI_0_0                             -     @5187                                                       
+      RK0_ARPI_DQ_B1                               uvm_reg_field                                              ...    RW SHURK_PI_0_0[5:0]=6'h18 (Mirror: 6'h00)                 
+      RK0_ARPI_DQ_B0                               uvm_reg_field                                              ...    RW SHURK_PI_0_0[13:8]=6'h18 (Mirror: 6'h00)                
+      RK0_ARPI_DQM_B1                              uvm_reg_field                                              ...    RW SHURK_PI_0_0[21:16]=6'h18 (Mirror: 6'h00)               
+      RK0_ARPI_DQM_B0                              uvm_reg_field                                              ...    RW SHURK_PI_0_0[29:24]=6'h18 (Mirror: 6'h00)               
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B1) |
+            P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B1) |
+            P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_PI_0_1                                   ral_reg_DRAMC_blk_SHURK_PI_0_1                             -     @5194                                                       
+      RK0_ARPI_DQ_B1                               uvm_reg_field                                              ...    RW SHURK_PI_0_1[5:0]=6'h18 (Mirror: 6'h00)                 
+      RK0_ARPI_DQ_B0                               uvm_reg_field                                              ...    RW SHURK_PI_0_1[13:8]=6'h18 (Mirror: 6'h00)                
+      RK0_ARPI_DQM_B1                              uvm_reg_field                                              ...    RW SHURK_PI_0_1[21:16]=6'h18 (Mirror: 6'h00)               
+      RK0_ARPI_DQM_B0                              uvm_reg_field                                              ...    RW SHURK_PI_0_1[29:24]=6'h18 (Mirror: 6'h00)               
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B1) |
+            P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B1) |
+            P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B0));
+
+    #if !CODE_SIZE_REDUCE
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0                    -     @7826                                                       
+      TX_ARDQ0_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h30 (Mirror: 8'h00)         
+      TX_ARDQ1_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h30 (Mirror: 8'h00)        
+      TX_ARDQ2_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h30 (Mirror: 8'h00)       
+      TX_ARDQ3_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h30 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x30, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+            P_Fld(0x30, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x30, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+            P_Fld(0x30, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0                    -     @7840                                                       
+      TX_ARDQ4_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h30 (Mirror: 8'h00)         
+      TX_ARDQ5_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h30 (Mirror: 8'h00)        
+      TX_ARDQ6_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h30 (Mirror: 8'h00)       
+      TX_ARDQ7_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h30 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x30, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+            P_Fld(0x30, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x30, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+            P_Fld(0x30, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0                    -     @7868                                                       
+      TX_ARDQM0_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h30 (Mirror: 8'h00)         
+      TX_ARWCK_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00                       
+      TX_ARWCKB_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x30, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+            P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0                    -     @9233                                                       
+      TX_ARDQ0_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h0c (Mirror: 8'h00)         
+      TX_ARDQ1_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h0c (Mirror: 8'h00)        
+      TX_ARDQ2_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h0c (Mirror: 8'h00)       
+      TX_ARDQ3_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h0c (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x0c, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+            P_Fld(0x0c, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x0c, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+            P_Fld(0x0c, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0                    -     @9247                                                       
+      TX_ARDQ4_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h0c (Mirror: 8'h00)         
+      TX_ARDQ5_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h0c (Mirror: 8'h00)        
+      TX_ARDQ6_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h0c (Mirror: 8'h00)       
+      TX_ARDQ7_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h0c (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x0c, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+            P_Fld(0x0c, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x0c, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+            P_Fld(0x0c, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0                    -     @9275                                                       
+      TX_ARDQM0_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h0c (Mirror: 8'h00)         
+      TX_ARWCK_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00                       
+      TX_ARWCKB_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x0c, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+            P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1                    -     @7833                                                       
+      TX_ARDQ0_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h10 (Mirror: 8'h00)         
+      TX_ARDQ1_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h10 (Mirror: 8'h00)        
+      TX_ARDQ2_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h10 (Mirror: 8'h00)       
+      TX_ARDQ3_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h10 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+            P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+            P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1                    -     @7847                                                       
+      TX_ARDQ4_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h10 (Mirror: 8'h00)         
+      TX_ARDQ5_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h10 (Mirror: 8'h00)        
+      TX_ARDQ6_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h10 (Mirror: 8'h00)       
+      TX_ARDQ7_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h10 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+            P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+            P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1                    -     @7874                                                       
+      TX_ARDQM0_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h10 (Mirror: 8'h00)         
+      TX_ARWCK_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00                       
+      TX_ARWCKB_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x10, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+            P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1                    -     @9240                                                       
+      TX_ARDQ0_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h20 (Mirror: 8'h00)         
+      TX_ARDQ1_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h20 (Mirror: 8'h00)        
+      TX_ARDQ2_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h20 (Mirror: 8'h00)       
+      TX_ARDQ3_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h20 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+            P_Fld(0x20, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x20, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+            P_Fld(0x20, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1                    -     @9254                                                       
+      TX_ARDQ4_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h20 (Mirror: 8'h00)         
+      TX_ARDQ5_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h20 (Mirror: 8'h00)        
+      TX_ARDQ6_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h20 (Mirror: 8'h00)       
+      TX_ARDQ7_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h20 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+            P_Fld(0x20, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x20, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+            P_Fld(0x20, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1                    -     @9281                                                       
+      TX_ARDQM0_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h20 (Mirror: 8'h00)         
+      TX_ARWCK_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00                       
+      TX_ARWCKB_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+            P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_TX_RANKCTL_0                               ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0                         -     @5651                                                       
+      TXRANKINCTL_TXDLY                            uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[3:0]=4'h1 (Mirror: 4'h0)               
+      TXRANKINCTL                                  uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[7:4]=4'h1 (Mirror: 4'h0)               
+      TXRANKINCTL_ROOT                             uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[11:8]=4'h0                             
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) |
+            P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT));
+    #endif
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit:
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter:
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_AC_DERATING0_0                             ral_reg_DRAMC_blk_SHU_AC_DERATING0_0                       -     @5538                                                       
+      ACDERATEEN                                   uvm_reg_field                                              ...    RW SHU_AC_DERATING0_0[0:0]=1'h1 (Mirror: 1'h0)             
+      TRRD_DERATE                                  uvm_reg_field                                              ...    RW SHU_AC_DERATING0_0[18:16]=3'h2 (Mirror: 3'h0)           
+      TRCD_DERATE                                  uvm_reg_field                                              ...    RW SHU_AC_DERATING0_0[27:24]=4'h4 (Mirror: 4'h0)           
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !(CODE_SIZE_REDUCE && AC_TIMING_DERATE_ENABLE)
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING0, P_Fld(0x1, SHU_AC_DERATING0_ACDERATEEN) |
+            P_Fld(0x2, SHU_AC_DERATING0_TRRD_DERATE) | P_Fld(0x4, SHU_AC_DERATING0_TRCD_DERATE));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_AC_DERATING1_0                             ral_reg_DRAMC_blk_SHU_AC_DERATING1_0                       -     @5544                                                       
+      TRPAB_DERATE                                 uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[3:0]=4'h3 (Mirror: 4'h0)             
+      TRP_DERATE                                   uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[11:8]=4'h2 (Mirror: 4'h0)            
+      TRAS_DERATE                                  uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[21:16]=6'h01 (Mirror: 6'h00)         
+      TRC_DERATE                                   uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[28:24]=5'h00                         
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING1, P_Fld(0x3, SHU_AC_DERATING1_TRPAB_DERATE) |
+            P_Fld(0x2, SHU_AC_DERATING1_TRP_DERATE) | P_Fld(0x01, SHU_AC_DERATING1_TRAS_DERATE) |
+            P_Fld(0x00, SHU_AC_DERATING1_TRC_DERATE));
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SREF_CTRL_0                                ral_reg_DRAMC_blk_SHU_SREF_CTRL_0                          -     @5322                                                       
+      CKEHCMD                                      uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[5:4]=2'h3                               
+      SREF_CK_DLY                                  uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0)              
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) |
+            P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_HMR4_DVFS_CTRL0_0                          ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0                    -     @5341                                                       
+      FSPCHG_PRDCNT                                uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h32 (Mirror: 8'h00)       
+      REFRCNT                                      uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000                    
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x32, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+            P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM_XRT_0                                ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0                          -     @5497                                                       
+      XRTR2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[4:0]=5'h05 (Mirror: 5'h01)              
+      XRTR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[13:8]=6'h0a (Mirror: 6'h01)             
+      XRTW2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[19:16]=4'h6 (Mirror: 4'h1)              
+      XRTW2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[28:24]=5'h09 (Mirror: 5'h01)            
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x05, SHU_ACTIM_XRT_XRTR2R) |
+            P_Fld(0x0a, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x6, SHU_ACTIM_XRT_XRTW2R) |
+            P_Fld(0x09, SHU_ACTIM_XRT_XRTW2W));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM0_0                                   ral_reg_DRAMC_blk_SHU_ACTIM0_0                             -     @5443                                                       
+      TWTR                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[5:0]=6'h0a (Mirror: 6'h01)                 
+      TWR                                          uvm_reg_field                                              ...    RW SHU_ACTIM0_0[15:8]=8'h0c (Mirror: 8'h06)                
+      TRRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[18:16]=3'h1 (Mirror: 3'h0)                 
+      TRCD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[27:24]=4'h4 (Mirror: 4'h2)                 
+      CKELCKCNT                                    uvm_reg_field                                              ...    RW SHU_ACTIM0_0[31:28]=4'h3 (Mirror: 4'h0)                 
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x0a, SHU_ACTIM0_TWTR) |
+            P_Fld(0x0c, SHU_ACTIM0_TWR) | P_Fld(0x1, SHU_ACTIM0_TRRD) |
+            P_Fld(0x4, SHU_ACTIM0_TRCD) | P_Fld(0x3, SHU_ACTIM0_CKELCKCNT));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM1_0                                   ral_reg_DRAMC_blk_SHU_ACTIM1_0                             -     @5451                                                       
+      TRPAB                                        uvm_reg_field                                              ...    RW SHU_ACTIM1_0[3:0]=4'h3 (Mirror: 4'ha)                   
+      TMRWCKEL                                     uvm_reg_field                                              ...    RW SHU_ACTIM1_0[7:4]=4'h7 (Mirror: 4'h8)                   
+      TRP                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[11:8]=4'h2                                 
+      TRAS                                         uvm_reg_field                                              ...    RW SHU_ACTIM1_0[21:16]=6'h01 (Mirror: 6'h04)               
+      TRC                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[28:24]=5'h00 (Mirror: 5'h05)               
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x3, SHU_ACTIM1_TRPAB) |
+            P_Fld(0x7, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x2, SHU_ACTIM1_TRP) |
+            P_Fld(0x01, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM2_0                                   ral_reg_DRAMC_blk_SHU_ACTIM2_0                             -     @5459                                                       
+      TXP                                          uvm_reg_field                                              ...    RW SHU_ACTIM2_0[3:0]=4'h0                                  
+      TMRRI                                        uvm_reg_field                                              ...    RW SHU_ACTIM2_0[8:4]=5'h07 (Mirror: 5'h0e)                 
+      TRTP                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[14:12]=3'h3 (Mirror: 3'h0)                 
+      TR2W                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[21:16]=6'h0a (Mirror: 6'h00)               
+      TFAW                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[28:24]=5'h00 (Mirror: 5'h05)               
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x0, SHU_ACTIM2_TXP) |
+            P_Fld(0x07, SHU_ACTIM2_TMRRI) | P_Fld(0x3, SHU_ACTIM2_TRTP) |
+            P_Fld(0x0a, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM3_0                                   ral_reg_DRAMC_blk_SHU_ACTIM3_0                             -     @5467                                                       
+      TRFCPB                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[7:0]=8'h1a (Mirror: 8'h00)                 
+      MANTMRR                                      uvm_reg_field                                              ...    RW SHU_ACTIM3_0[11:8]=4'h8 (Mirror: 4'h0)                  
+      TR2MRR                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[15:12]=4'h8 (Mirror: 4'h0)                 
+      TRFC                                         uvm_reg_field                                              ...    RW SHU_ACTIM3_0[23:16]=8'h40 (Mirror: 8'h00)               
+      TWTR_L                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[29:24]=6'h25 (Mirror: 6'h00)               
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x1a, SHU_ACTIM3_TRFCPB) |
+            P_Fld(0x8, SHU_ACTIM3_TR2MRR) | P_Fld(0x40, SHU_ACTIM3_TRFC));
+    #endif
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x8, SHU_ACTIM3_MANTMRR) |
+            P_Fld(0x25, SHU_ACTIM3_TWTR_L));
+
+    #if !CODE_SIZE_REDUCE
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM4_0                                   ral_reg_DRAMC_blk_SHU_ACTIM4_0                             -     @5475                                                       
+      TXREFCNT                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[9:0]=10'h04e (Mirror: 10'h028)             
+      TMRR2MRW                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[15:10]=6'h0f (Mirror: 6'h00)               
+      TMRR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM4_0[21:16]=6'h0c (Mirror: 6'h00)               
+      TZQCS                                        uvm_reg_field                                              ...    RW SHU_ACTIM4_0[31:24]=8'h10 (Mirror: 8'h00)               
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x04e, SHU_ACTIM4_TXREFCNT) |
+            P_Fld(0x0f, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0c, SHU_ACTIM4_TMRR2W) |
+            P_Fld(0x10, SHU_ACTIM4_TZQCS));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM5_0                                   ral_reg_DRAMC_blk_SHU_ACTIM5_0                             -     @5482                                                       
+      TR2PD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[6:0]=7'h10 (Mirror: 7'h00)                 
+      TWTPD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[14:8]=7'h0f (Mirror: 7'h00)                
+      TPBR2PBR                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[23:16]=8'h15 (Mirror: 8'h00)               
+      TPBR2ACT                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[29:28]=2'h0                                
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x10, SHU_ACTIM5_TR2PD) |
+            P_Fld(0x0f, SHU_ACTIM5_TWTPD) | P_Fld(0x15, SHU_ACTIM5_TPBR2PBR) |
+            P_Fld(0x0, SHU_ACTIM5_TPBR2ACT));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM6_0                                   ral_reg_DRAMC_blk_SHU_ACTIM6_0                             -     @5489                                                       
+      TZQLAT2                                      uvm_reg_field                                              ...    RW SHU_ACTIM6_0[4:0]=5'h06 (Mirror: 5'h1f)                 
+      TMRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[11:8]=4'h6 (Mirror: 4'h0)                  
+      TMRW                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0)                 
+      TW2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[25:20]=6'h0d (Mirror: 6'h00)               
+      TR2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[31:26]=6'h11 (Mirror: 6'h13)               
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x06, SHU_ACTIM6_TZQLAT2) |
+            P_Fld(0x6, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) |
+            P_Fld(0x0d, SHU_ACTIM6_TW2MRW) | P_Fld(0x11, SHU_ACTIM6_TR2MRW));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_CKECTRL_0                                  ral_reg_DRAMC_blk_SHU_CKECTRL_0                            -     @5567                                                       
+      TPDE_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[0:0]=1'h0                                 
+      TPDX_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[1:1]=1'h0                                 
+      TPDE                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[14:12]=3'h3 (Mirror: 3'h1)                
+      TPDX                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[18:16]=3'h3 (Mirror: 3'h1)                
+      TCKEPRD                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[22:20]=3'h2                               
+      TCKESRX                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0)                
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x0, SHU_CKECTRL_TPDE_05T) |
+            P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x3, SHU_CKECTRL_TPDE) |
+            P_Fld(0x3, SHU_CKECTRL_TPDX) | P_Fld(0x2, SHU_CKECTRL_TCKEPRD));
+    #endif
+
+    vIO32WriteFldAlign(DRAMC_REG_SHU_CKECTRL, 0x3, SHU_CKECTRL_TCKESRX);
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_0                                     ral_reg_DRAMC_blk_SHU_MISC_0                               -     @5671                                                       
+      REQQUE_MAXCNT                                uvm_reg_field                                              ...    RW SHU_MISC_0[3:0]=4'h2                                    
+      DCMDLYREF                                    uvm_reg_field                                              ...    RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4)                   
+      DAREFEN                                      uvm_reg_field                                              ...    RW SHU_MISC_0[30:30]=1'h0                                  
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x7, SHU_MISC_DCMDLYREF) |
+    P_Fld(0x0, SHU_MISC_DAREFEN));
+
+	#if !CODE_SIZE_REDUCE
+    vIO32WriteFldAlign(DRAMC_REG_SHU_MISC, 0x2, SHU_MISC_REQQUE_MAXCNT);
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter.
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit.
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ8_0                            -     @8226                                                       
+      R_DMRXDVS_UPD_FORCE_CYC_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[14:0]=15'h0031 (Mirror: 15'h0000)          
+      R_DMRXDVS_UPD_FORCE_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[15:15]=1'h0                                
+      R_DMRANK_RXDLY_PIPE_CG_IG_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[19:19]=1'h0                                
+      R_RMRODTEN_CG_IG_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[20:20]=1'h0                                
+      R_RMRX_TOPHY_CG_IG_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)                 
+      R_DMRXDVS_RDSEL_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[22:22]=1'h0                                
+      R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0            uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[23:23]=1'h0                                
+      R_DMRXDLY_CG_IG_B0                           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)                 
+      R_DMDQSIEN_FLAG_SYNC_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[26:26]=1'h0                                
+      R_DMDQSIEN_FLAG_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[27:27]=1'h0                                
+      R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0               uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[28:28]=1'h0                                
+      R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[29:29]=1'h0                                
+      R_DMRANK_PIPE_CG_IG_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[30:30]=1'h0                                
+      R_DMRANK_CHG_PIPE_CG_IG_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[31:31]=1'h0                                
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+            P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+    #endif
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0031, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ8_0                            -     @9633                                                       
+      R_DMRXDVS_UPD_FORCE_CYC_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[14:0]=15'h0031 (Mirror: 15'h0000)          
+      R_DMRXDVS_UPD_FORCE_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[15:15]=1'h0                                
+      R_DMRANK_RXDLY_PIPE_CG_IG_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[19:19]=1'h0                                
+      R_RMRODTEN_CG_IG_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[20:20]=1'h0                                
+      R_RMRX_TOPHY_CG_IG_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)                 
+      R_DMRXDVS_RDSEL_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[22:22]=1'h0                                
+      R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1            uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[23:23]=1'h0                                
+      R_DMRXDLY_CG_IG_B1                           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)                 
+      R_DMDQSIEN_FLAG_SYNC_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[26:26]=1'h0                                
+      R_DMDQSIEN_FLAG_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[27:27]=1'h0                                
+      R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1               uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[28:28]=1'h0                                
+      R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[29:29]=1'h0                                
+      R_DMRANK_PIPE_CG_IG_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[30:30]=1'h0                                
+      R_DMRANK_CHG_PIPE_CG_IG_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[31:31]=1'h0                                
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0031, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1));
+
+	#if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+            P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ5_0                            -     @8126                                                       
+      RG_RX_ARDQ_VREF_SEL_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[5:0]=6'h0e                                 
+      RG_RX_ARDQ_VREF_BYPASS_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[6:6]=1'h0                                  
+      RG_ARPI_FB_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[13:8]=6'h00                                
+      RG_RX_ARDQS0_DQSIEN_DLY_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[18:16]=3'h0                                
+      RG_RX_ARDQS_DQSIEN_RB_DLY_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[19:19]=1'h0                                
+      RG_RX_ARDQS0_DVS_DLY_B0                      uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[23:20]=4'h7 (Mirror: 4'h0)                 
+      RG_RX_ARDQ_FIFO_DQSI_DLY_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[31:29]=3'h0                                
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) |
+            P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) |
+            P_Fld(0x7, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ5_0                            -     @9533                                                       
+      RG_RX_ARDQ_VREF_SEL_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[5:0]=6'h0e                                 
+      RG_RX_ARDQ_VREF_BYPASS_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[6:6]=1'h0                                  
+      RG_ARPI_FB_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[13:8]=6'h00                                
+      RG_RX_ARDQS0_DQSIEN_DLY_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[18:16]=3'h0                                
+      RG_RX_ARDQS_DQSIEN_RB_DLY_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[19:19]=1'h0                                
+      RG_RX_ARDQS0_DVS_DLY_B1                      uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[23:20]=4'h7 (Mirror: 4'h0)                 
+      RG_RX_ARDQ_FIFO_DQSI_DLY_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[31:29]=3'h0                                
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) |
+            P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) |
+            P_Fld(0x7, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0                    -     @7888                                                       
+      RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h75 (Mirror: 8'h00)         
+      RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h75 (Mirror: 8'h00)        
+      RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h75 (Mirror: 8'h00)       
+      RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h75 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0                    -     @7902                                                       
+      RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h75 (Mirror: 8'h00)         
+      RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h75 (Mirror: 8'h00)        
+      RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h75 (Mirror: 8'h00)       
+      RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h75 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0                    -     @7916                                                       
+      RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h75 (Mirror: 8'h00)         
+      RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h75 (Mirror: 8'h00)        
+      RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h75 (Mirror: 8'h00)       
+      RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h75 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0                    -     @7930                                                       
+      RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h75 (Mirror: 8'h00)         
+      RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h75 (Mirror: 8'h00)        
+      RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h75 (Mirror: 8'h00)       
+      RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h75 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0                    -     @7944                                                       
+      RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h75 (Mirror: 8'h00)         
+      RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h75 (Mirror: 8'h00)        
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x75, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0                    -     @7954                                                       
+      RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h17e (Mirror: 9'h000)       
+      RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h17e (Mirror: 9'h000)     
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x17e, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+            P_Fld(0x17e, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1                    -     @7895                                                       
+      RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h74 (Mirror: 8'h00)         
+      RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h74 (Mirror: 8'h00)        
+      RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h74 (Mirror: 8'h00)       
+      RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h74 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) |
+            P_Fld(0x74, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+            P_Fld(0x74, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1                    -     @7909                                                       
+      RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h74 (Mirror: 8'h00)         
+      RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h74 (Mirror: 8'h00)        
+      RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h74 (Mirror: 8'h00)       
+      RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h74 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+            P_Fld(0x74, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+            P_Fld(0x74, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1                    -     @7923                                                       
+      RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h74 (Mirror: 8'h00)         
+      RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h74 (Mirror: 8'h00)        
+      RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h74 (Mirror: 8'h00)       
+      RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h74 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+            P_Fld(0x74, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+            P_Fld(0x74, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1                    -     @7937                                                       
+      RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h74 (Mirror: 8'h00)         
+      RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h74 (Mirror: 8'h00)        
+      RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h74 (Mirror: 8'h00)       
+      RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h74 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+            P_Fld(0x74, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+            P_Fld(0x74, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1                    -     @7949                                                       
+      RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h74 (Mirror: 8'h00)         
+      RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h74 (Mirror: 8'h00)        
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+            P_Fld(0x74, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1                    -     @7959                                                       
+      RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h17d (Mirror: 9'h000)       
+      RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h17d (Mirror: 9'h000)     
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17d, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+            P_Fld(0x17d, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0                    -     @9295                                                       
+      RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h75 (Mirror: 8'h00)         
+      RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h75 (Mirror: 8'h00)        
+      RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h75 (Mirror: 8'h00)       
+      RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h75 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0                    -     @9309                                                       
+      RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h75 (Mirror: 8'h00)         
+      RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h75 (Mirror: 8'h00)        
+      RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h75 (Mirror: 8'h00)       
+      RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h75 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0                    -     @9323                                                       
+      RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h75 (Mirror: 8'h00)         
+      RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h75 (Mirror: 8'h00)        
+      RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h75 (Mirror: 8'h00)       
+      RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h75 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0                    -     @9337                                                       
+      RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h75 (Mirror: 8'h00)         
+      RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h75 (Mirror: 8'h00)        
+      RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h75 (Mirror: 8'h00)       
+      RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h75 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0                    -     @9351                                                       
+      RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h75 (Mirror: 8'h00)         
+      RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h75 (Mirror: 8'h00)        
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x75, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0                    -     @9361                                                       
+      RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h17e (Mirror: 9'h000)       
+      RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h17e (Mirror: 9'h000)     
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x17e, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+            P_Fld(0x17e, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1                    -     @9302                                                       
+      RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h74 (Mirror: 8'h00)         
+      RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h74 (Mirror: 8'h00)        
+      RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h74 (Mirror: 8'h00)       
+      RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h74 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) |
+            P_Fld(0x74, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+            P_Fld(0x74, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1                    -     @9316                                                       
+      RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h74 (Mirror: 8'h00)         
+      RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h74 (Mirror: 8'h00)        
+      RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h74 (Mirror: 8'h00)       
+      RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h74 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+            P_Fld(0x74, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+            P_Fld(0x74, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1                    -     @9330                                                       
+      RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h74 (Mirror: 8'h00)         
+      RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h74 (Mirror: 8'h00)        
+      RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h74 (Mirror: 8'h00)       
+      RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h74 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+            P_Fld(0x74, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+            P_Fld(0x74, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1                    -     @9344                                                       
+      RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h74 (Mirror: 8'h00)         
+      RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h74 (Mirror: 8'h00)        
+      RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h74 (Mirror: 8'h00)       
+      RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h74 (Mirror: 8'h00)       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+            P_Fld(0x74, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+            P_Fld(0x74, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1                    -     @9356                                                       
+      RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h74 (Mirror: 8'h00)         
+      RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h74 (Mirror: 8'h00)        
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+            P_Fld(0x74, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+    #endif
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1                    -     @9366                                                       
+      RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h17d (Mirror: 9'h000)       
+      RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h17d (Mirror: 9'h000)     
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17d, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+            P_Fld(0x17d, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ9                                         ral_reg_DDRPHY_blk_B0_DQ9                                  -     @7782                                                       
+      RG_RX_ARDQ_STBEN_RESETB_B0                   uvm_reg_field                                              ...    RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0)                         
+      RG_RX_ARDQS0_STBEN_RESETB_B0                 uvm_reg_field                                              ...    RW B0_DQ9[4:4]=1'h0                                        
+      RG_RX_ARDQS0_DQSIENMODE_B0                   uvm_reg_field                                              ...    RW B0_DQ9[5:5]=1'h0                                        
+      R_DMRXDVS_R_F_DLY_RK_OPT_B0                  uvm_reg_field                                              ...    RW B0_DQ9[6:6]=1'h1                                        
+      R_DMRXFIFO_STBENCMP_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ9[7:7]=1'h0                                        
+      R_IN_GATE_EN_LOW_OPT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[15:8]=8'h00                                      
+      R_DMDQSIEN_VALID_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[18:16]=3'h0                                      
+      R_DMDQSIEN_RDSEL_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[22:20]=3'h0                                      
+      R_DMRXDVS_VALID_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[26:24]=3'h0                                      
+      R_DMRXDVS_RDSEL_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[30:28]=3'h0                                      
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
+            P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
+            P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
+            P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
+            P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
+            P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ9                                         ral_reg_DDRPHY_blk_B1_DQ9                                  -     @9189                                                       
+      RG_RX_ARDQ_STBEN_RESETB_B1                   uvm_reg_field                                              ...    RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0)                         
+      RG_RX_ARDQS0_STBEN_RESETB_B1                 uvm_reg_field                                              ...    RW B1_DQ9[4:4]=1'h0                                        
+      RG_RX_ARDQS0_DQSIENMODE_B1                   uvm_reg_field                                              ...    RW B1_DQ9[5:5]=1'h0                                        
+      R_DMRXDVS_R_F_DLY_RK_OPT_B1                  uvm_reg_field                                              ...    RW B1_DQ9[6:6]=1'h1                                        
+      R_DMRXFIFO_STBENCMP_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ9[7:7]=1'h0                                        
+      R_IN_GATE_EN_LOW_OPT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[15:8]=8'h00                                      
+      R_DMDQSIEN_VALID_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[18:16]=3'h0                                      
+      R_DMDQSIEN_RDSEL_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[22:20]=3'h0                                      
+      R_DMRXDVS_VALID_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[26:24]=3'h0                                      
+      R_DMRXDVS_RDSEL_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[30:28]=3'h0                                      
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
+            P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
+            P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
+            P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
+            P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
+            P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ4                                         ral_reg_DDRPHY_blk_B0_DQ4                                  -     @7711                                                       
+      RG_RX_ARDQS_EYE_R_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[6:0]=7'h03 (Mirror: 7'h00)                       
+      RG_RX_ARDQS_EYE_F_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[14:8]=7'h03 (Mirror: 7'h00)                      
+      RG_RX_ARDQ_EYE_R_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[21:16]=6'h35 (Mirror: 6'h00)                     
+      RG_RX_ARDQ_EYE_F_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[29:24]=6'h35 (Mirror: 6'h00)                     
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x03, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) |
+            P_Fld(0x03, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x35, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) |
+            P_Fld(0x35, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ4                                         ral_reg_DDRPHY_blk_B1_DQ4                                  -     @9118                                                       
+      RG_RX_ARDQS_EYE_R_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[6:0]=7'h03 (Mirror: 7'h00)                       
+      RG_RX_ARDQS_EYE_F_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[14:8]=7'h03 (Mirror: 7'h00)                      
+      RG_RX_ARDQ_EYE_R_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[21:16]=6'h35 (Mirror: 6'h00)                     
+      RG_RX_ARDQ_EYE_F_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[29:24]=6'h35 (Mirror: 6'h00)                     
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x03, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) |
+            P_Fld(0x03, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x35, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) |
+            P_Fld(0x35, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ5                                         ral_reg_DDRPHY_blk_B0_DQ5                                  -     @7718                                                       
+      RG_RX_ARDQ_EYE_VREF_SEL_B0                   uvm_reg_field                                              ...    RW B0_DQ5[13:8]=6'h0e                                      
+      RG_RX_ARDQ_VREF_EN_B0                        uvm_reg_field                                              ...    RW B0_DQ5[16:16]=1'h0                                      
+      RG_RX_ARDQ_EYE_VREF_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ5[17:17]=1'h0                                      
+      RG_RX_ARDQ_EYE_SEL_B0                        uvm_reg_field                                              ...    RW B0_DQ5[23:20]=4'h0                                      
+      RG_RX_ARDQ_EYE_EN_B0                         uvm_reg_field                                              ...    RW B0_DQ5[24:24]=1'h0                                      
+      RG_RX_ARDQ_EYE_STBEN_RESETB_B0               uvm_reg_field                                              ...    RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0)                       
+      RG_RX_ARDQS0_DVS_EN_B0                       uvm_reg_field                                              ...    RW B0_DQ5[31:31]=1'h0                                      
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x0e, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) |
+            P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) |
+            P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) |
+            P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                       
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ5                                         ral_reg_DDRPHY_blk_B1_DQ5                                  -     @9125                                                       
+      RG_RX_ARDQ_EYE_VREF_SEL_B1                   uvm_reg_field                                              ...    RW B1_DQ5[13:8]=6'h0e                                      
+      RG_RX_ARDQ_VREF_EN_B1                        uvm_reg_field                                              ...    RW B1_DQ5[16:16]=1'h0                                      
+      RG_RX_ARDQ_EYE_VREF_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ5[17:17]=1'h0                                      
+      RG_RX_ARDQ_EYE_SEL_B1                        uvm_reg_field                                              ...    RW B1_DQ5[23:20]=4'h0                                      
+      RG_RX_ARDQ_EYE_EN_B1                         uvm_reg_field                                              ...    RW B1_DQ5[24:24]=1'h0                                      
+      RG_RX_ARDQ_EYE_STBEN_RESETB_B1               uvm_reg_field                                              ...    RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0)                       
+      RG_RX_ARDQS0_DVS_EN_B1                       uvm_reg_field                                              ...    RW B1_DQ5[31:31]=1'h0                                      
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x0e, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) |
+            P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) |
+            P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) |
+            P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT
+    //    Exit body
+}
+
+
+void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p)
+{
+    //    Enter body
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter:
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_RDSEL_TRACK_0                         ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0                  -     @13206                                                     
+      DMDATLAT_i                                   uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h0f (Mirror: 5'h00)      
+      RDSEL_HWSAVE_MSK                             uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0)        
+      RDSEL_TRACK_EN                               uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0                       
+      SHU_GW_THRD_NEG                              uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfd0 (Mirror: 12'h000) 
+      SHU_GW_THRD_POS                              uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h030 (Mirror: 12'h000)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x0f, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) |
+            P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) |
+            P_Fld(0xfd0, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x030, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RDAT_0                                ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0                         -     @13076                                                     
+      DATLAT                                       uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[4:0]=5'h0f (Mirror: 5'h00)             
+      DATLAT_DSEL                                  uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[12:8]=5'h0f (Mirror: 5'h00)            
+      DATLAT_DSEL_PHY                              uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[20:16]=5'h0f (Mirror: 5'h00)           
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x0f, MISC_SHU_RDAT_DATLAT) |
+            P_Fld(0x0f, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0f, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
+    #endif
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_PHY_RX_CTRL_0                         ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0                  -     @13012                                                     
+      RANK_RXDLY_UPDLAT_EN                         uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0)        
+      RANK_RXDLY_UPD_OFFSET                        uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0)       
+      RX_IN_GATE_EN_PRE_OFFSET                     uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0)      
+      RX_IN_GATE_EN_HEAD                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h1 (Mirror: 3'h0)      
+      RX_IN_GATE_EN_TAIL                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0)      
+      RX_IN_BUFF_EN_HEAD                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h2 (Mirror: 3'h0)      
+      RX_IN_BUFF_EN_TAIL                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0                     
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) |
+            P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) |
+            P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) |
+            P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RANKCTL_0                             ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0                      -     @13002                                                     
+      RANKINCTL_RXDLY                              uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[3:0]=4'h4 (Mirror: 4'h0)            
+      RANK_RXDLY_OPT                               uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[4:4]=1'h1                           
+      RANKSEL_SELPH_FRUN                           uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[15:15]=1'h1 (Mirror: 1'h0)          
+      RANKINCTL_STB                                uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[19:16]=4'h6 (Mirror: 4'h0)          
+      RANKINCTL                                    uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[23:20]=4'h5 (Mirror: 4'h0)          
+      RANKINCTL_ROOT1                              uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[27:24]=4'h5 (Mirror: 4'h0)          
+      RANKINCTL_PHY                                uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[31:28]=4'h8 (Mirror: 4'h0)          
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) |
+            P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x1, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) |
+            P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_STB));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL) |
+            P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x8, MISC_SHU_RANKCTL_RANKINCTL_PHY));
+    #endif
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RANK_SEL_LAT_0                        ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0                 -     @13229                                                     
+      RANK_SEL_LAT_B0                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0)       
+      RANK_SEL_LAT_B1                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0)       
+      RANK_SEL_LAT_CA                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0)      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
+            P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
+
+    #if !CODE_SIZE_REDUCE
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCTL_0_0                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0                  -     @12823                                                     
+      DQSINCTL                                     uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h7 (Mirror: 4'h0)        
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL);
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCTL_0_1                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1                  -     @12827                                                     
+      DQSINCTL                                     uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h7 (Mirror: 4'h0)        
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0         -     @8022                                                         
+      DQSIEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h0                 
+      DQSIEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h4 (Mirror: 4'h0)  
+      DQSIEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0)
+      DQSIEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+            P_Fld(0x4, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+            P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_PI_DLY_0_0                    ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0             -     @8036                                                         
+      DQSIEN_PI_B0                                 uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0f (Mirror: 7'h00)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0f, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1         -     @8029                                                         
+      DQSIEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h7 (Mirror: 4'h0)  
+      DQSIEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hb (Mirror: 4'h0)  
+      DQSIEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0)
+      DQSIEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+            P_Fld(0xb, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+            P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_PI_DLY_0_1                    ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1             -     @8040                                                         
+      DQSIEN_PI_B0                                 uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h1c (Mirror: 7'h00)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1c, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0         -     @9429                                                         
+      DQSIEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h0                 
+      DQSIEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h4 (Mirror: 4'h0)  
+      DQSIEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0)
+      DQSIEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+            P_Fld(0x4, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+            P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_PI_DLY_0_0                    ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0             -     @9443                                                         
+      DQSIEN_PI_B1                                 uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0f (Mirror: 7'h00)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0f, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1         -     @9436                                                         
+      DQSIEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h7 (Mirror: 4'h0)  
+      DQSIEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hb (Mirror: 4'h0)  
+      DQSIEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0)
+      DQSIEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+            P_Fld(0xb, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+            P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_PI_DLY_0_1                    ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1             -     @9447                                                         
+      DQSIEN_PI_B1                                 uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h1c (Mirror: 7'h00)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1c, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_ODTCTRL_0                             ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0                      -     @13022                                                        
+      RODTEN                                       uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0)               
+      RODTENSTB_SELPH_CG_IG                        uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[1:1]=1'h0                              
+      RODT_LAT                                     uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[7:4]=4'h7 (Mirror: 4'h0)               
+      RODTEN_SELPH_FRUN                            uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[15:15]=1'h0                            
+      RODTDLY_LAT_OPT                              uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[25:24]=2'h0                            
+      FIXRODT                                      uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[27:27]=1'h0                            
+      RODTEN_OPT                                   uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[29:29]=1'h1                            
+      RODTE2                                       uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0)             
+      RODTE                                        uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0)             
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) |
+            P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE));
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_ODTCTRL, 0x7, MISC_SHU_ODTCTRL_RODT_LAT);
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ7_0                            -     @8206                                                         
+      R_DMRANKRXDVS_B0                             uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[3:0]=4'h0                                    
+      R_DMDQMDBI_EYE_SHU_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[6:6]=1'h0                                    
+      R_DMDQMDBI_SHU_B0                            uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[7:7]=1'h0                                    
+      R_DMRXDVS_DQM_FLAGSEL_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[11:8]=4'h0                                   
+      R_DMRXDVS_PBYTE_FLAG_OPT_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[12:12]=1'h0                                  
+      R_DMRXDVS_PBYTE_DQM_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[13:13]=1'h0                                  
+      R_DMRXTRACK_DQM_EN_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[14:14]=1'h0                                  
+      R_DMRODTEN_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)                   
+      R_DMARPI_CG_FB2DLL_DCM_EN_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[16:16]=1'h0                                  
+      R_DMTX_ARPI_CG_DQ_NEW_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[17:17]=1'h0                                  
+      R_DMTX_ARPI_CG_DQS_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[18:18]=1'h0                                  
+      R_DMTX_ARPI_CG_DQM_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[19:19]=1'h0                                  
+      R_LP4Y_SDN_MODE_DQS0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[20:20]=1'h0                                  
+      R_DMRXRANK_DQ_EN_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)                   
+      R_DMRXRANK_DQ_LAT_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0)                   
+      R_DMRXRANK_DQS_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)                   
+      R_DMRXRANK_DQS_LAT_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[31:29]=3'h0                                  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ7_0                            -     @9613                                                         
+      R_DMRANKRXDVS_B1                             uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[3:0]=4'h0                                    
+      R_DMDQMDBI_EYE_SHU_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[6:6]=1'h0                                    
+      R_DMDQMDBI_SHU_B1                            uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[7:7]=1'h0                                    
+      R_DMRXDVS_DQM_FLAGSEL_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[11:8]=4'h0                                   
+      R_DMRXDVS_PBYTE_FLAG_OPT_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[12:12]=1'h0                                  
+      R_DMRXDVS_PBYTE_DQM_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[13:13]=1'h0                                  
+      R_DMRXTRACK_DQM_EN_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[14:14]=1'h0                                  
+      R_DMRODTEN_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)                   
+      R_DMARPI_CG_FB2DLL_DCM_EN_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[16:16]=1'h0                                  
+      R_DMTX_ARPI_CG_DQ_NEW_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[17:17]=1'h0                                  
+      R_DMTX_ARPI_CG_DQS_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[18:18]=1'h0                                  
+      R_DMTX_ARPI_CG_DQM_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[19:19]=1'h0                                  
+      R_LP4Y_SDN_MODE_DQS1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[20:20]=1'h0                                  
+      R_DMRXRANK_DQ_EN_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)                   
+      R_DMRXRANK_DQ_LAT_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0)                   
+      R_DMRXRANK_DQS_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)                   
+      R_DMRXRANK_DQS_LAT_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[31:29]=3'h0                                  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_RX_PIPE_CTRL_0                        ral_reg_DDRPHY_blk_SHU_MISC_RX_PIPE_CTRL_0                 -     @13176                                                        
+      RX_PIPE_BYPASS_EN                            uvm_reg_field                                              ...    RW SHU_MISC_RX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0)          
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x1, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0         -     @8044                                                         
+      RODTEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h3 (Mirror: 3'h0)  
+      RODTEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h3 (Mirror: 3'h0)  
+      RODTEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0               
+      RODTEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0               
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+            P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1         -     @8051                                                         
+      RODTEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h2 (Mirror: 3'h0)  
+      RODTEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h2 (Mirror: 3'h0)  
+      RODTEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0)
+      RODTEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0               
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+            P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0         -     @9451                                                         
+      RODTEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h3 (Mirror: 3'h0)  
+      RODTEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h3 (Mirror: 3'h0)  
+      RODTEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0               
+      RODTEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0               
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+            P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1         -     @9458                                                         
+      RODTEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h2 (Mirror: 3'h0)  
+      RODTEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h2 (Mirror: 3'h0)  
+      RODTEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0)
+      RODTEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0               
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+            P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RX_CG_SET0_0                               ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0                         -     @5628                                                         
+      DLE_LAST_EXTEND3                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[0:0]=1'h0                                
+      READ_START_EXTEND3                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[1:1]=1'h0                                
+      DLE_LAST_EXTEND2                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0)                 
+      READ_START_EXTEND2                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0)                 
+      DLE_LAST_EXTEND1                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0)                 
+      READ_START_EXTEND1                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0)                 
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) |
+            P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) |
+            P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
+            P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_RANK_SEL_STB_0                        ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0                 -     @13192                                                        
+      RANK_SEL_STB_EN                              uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0)          
+      RANK_SEL_STB_EN_B23                          uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0                         
+      RANK_SEL_STB_SERMODE                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0                         
+      RANK_SEL_STB_TRACK                           uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0)          
+      RANK_SEL_RXDLY_TRACK                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0                         
+      RANK_SEL_STB_PHASE_EN                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h0                         
+      RANK_SEL_PHSINCTL                            uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h6 (Mirror: 4'h0)         
+      RANK_SEL_STB_UI_PLUS                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0                       
+      RANK_SEL_STB_MCK_PLUS                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0                       
+      RANK_SEL_STB_UI_MINUS                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h2 (Mirror: 4'h0)        
+      RANK_SEL_STB_MCK_MINUS                       uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0                       
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) |
+            P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) |
+            P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) |
+            P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x6, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) |
+            P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) |
+            P_Fld(0x2, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCAL_0_0                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0                  -     @12841                                                        
+      DQSIENLLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00)         
+      DQSIENLLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0)           
+      DQSIENHLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00)        
+      DQSIENHLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCAL_0_1                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1                  -     @12848                                                        
+      DQSIENLLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00)         
+      DQSIENLLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0)           
+      DQSIENHLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00)        
+      DQSIENHLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_INI_UIPI_0_0                         ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0                  -     @8000                                                         
+      CURR_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00)         
+      CURR_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h10 (Mirror: 8'h00)        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0f, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+            P_Fld(0x10, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_INI_UIPI_0_0                         ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0                  -     @9407                                                         
+      CURR_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00)         
+      CURR_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h10 (Mirror: 8'h00)        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0f, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+            P_Fld(0x10, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_INI_UIPI_0_1                         ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1                  -     @8005                                                         
+      CURR_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h1c (Mirror: 7'h00)         
+      CURR_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h17 (Mirror: 8'h00)        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+            P_Fld(0x17, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_INI_UIPI_0_1                         ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1                  -     @9412                                                         
+      CURR_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h1c (Mirror: 7'h00)         
+      CURR_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h17 (Mirror: 8'h00)        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+            P_Fld(0x17, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_NEXT_INI_UIPI_0_0                    ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0             -     @8010                                                         
+      NEXT_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00)    
+      NEXT_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h10 (Mirror: 8'h00)   
+      NEXT_INI_UI_P1_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h14 (Mirror: 8'h00)  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+            P_Fld(0x10, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x14, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_NEXT_INI_UIPI_0_0                    ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0             -     @9417                                                         
+      NEXT_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00)    
+      NEXT_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h10 (Mirror: 8'h00)   
+      NEXT_INI_UI_P1_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h14 (Mirror: 8'h00)  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+            P_Fld(0x10, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x14, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_NEXT_INI_UIPI_0_1                    ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1             -     @8016                                                         
+      NEXT_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h1c (Mirror: 7'h00)    
+      NEXT_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h17 (Mirror: 8'h00)   
+      NEXT_INI_UI_P1_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h1b (Mirror: 8'h00)  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+            P_Fld(0x17, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x1b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_NEXT_INI_UIPI_0_1                    ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1             -     @9423                                                         
+      NEXT_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h1c (Mirror: 7'h00)    
+      NEXT_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h17 (Mirror: 8'h00)   
+      NEXT_INI_UI_P1_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h1b (Mirror: 8'h00)  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+            P_Fld(0x17, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x1b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit:
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter:
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_CA_CMD0_0_0                             ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_0                      -     @10832                                                        
+      RG_RX_ARCLK_R_DLY_DUTY                       uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[2:0]=3'h0                              
+      RG_RX_ARCLK_F_DLY_DUTY                       uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[6:4]=3'h0                              
+      RG_ARPI_CS                                   uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[13:8]=6'h00                            
+      RG_ARPI_CMD                                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[21:16]=6'h20 (Mirror: 6'h00)           
+      RG_ARPI_CLK                                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[29:24]=6'h00                           
+      DA_ARPI_DDR400_0D5UI_RK0_CA                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[30:30]=1'h0                            
+      DA_RX_ARDQSIEN_0D5UI_RK0_CA                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[31:31]=1'h0                            
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
+            P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_DQ0_0_0                              ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0                       -     @7980                                                         
+      RG_RX_ARDQS0_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0                               
+      RG_RX_ARDQS0_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0                               
+      SW_ARPI_DQ_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[13:8]=6'h11 (Mirror: 6'h00)             
+      SW_ARPI_DQM_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[21:16]=6'h11 (Mirror: 6'h00)            
+      ARPI_PBYTE_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00                            
+      DA_ARPI_DDR400_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0                             
+      DA_RX_ARDQSIEN_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0                             
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x11, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+            P_Fld(0x11, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_DQ0_0_0                              ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0                       -     @9387                                                         
+      RG_RX_ARDQS1_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0                               
+      RG_RX_ARDQS1_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0                               
+      SW_ARPI_DQ_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[13:8]=6'h12 (Mirror: 6'h00)             
+      SW_ARPI_DQM_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[21:16]=6'h12 (Mirror: 6'h00)            
+      ARPI_PBYTE_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00                            
+      DA_ARPI_DDR400_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0                             
+      DA_RX_ARDQSIEN_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0                             
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x12, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+            P_Fld(0x12, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_CA_CMD0_0_1                             ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_1                      -     @10842                                                        
+      RG_RX_ARCLK_R_DLY_DUTY                       uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[2:0]=3'h0                              
+      RG_RX_ARCLK_F_DLY_DUTY                       uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[6:4]=3'h0                              
+      RG_ARPI_CS                                   uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[13:8]=6'h00                            
+      RG_ARPI_CMD                                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[21:16]=6'h20 (Mirror: 6'h00)           
+      RG_ARPI_CLK                                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[29:24]=6'h00                           
+      DA_ARPI_DDR400_0D5UI_RK0_CA                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[30:30]=1'h0                            
+      DA_RX_ARDQSIEN_0D5UI_RK0_CA                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[31:31]=1'h0                            
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET),P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
+            P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_DQ0_0_1                              ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1                       -     @7990                                                         
+      RG_RX_ARDQS0_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0                               
+      RG_RX_ARDQS0_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0                               
+      SW_ARPI_DQ_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[13:8]=6'h16 (Mirror: 6'h00)             
+      SW_ARPI_DQM_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[21:16]=6'h16 (Mirror: 6'h00)            
+      ARPI_PBYTE_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00                            
+      DA_ARPI_DDR400_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0                             
+      DA_RX_ARDQSIEN_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0                             
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+            P_Fld(0x16, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_DQ0_0_1                              ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1                       -     @9397                                                         
+      RG_RX_ARDQS1_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0                               
+      RG_RX_ARDQS1_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0                               
+      SW_ARPI_DQ_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[13:8]=6'h21 (Mirror: 6'h00)             
+      SW_ARPI_DQM_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[21:16]=6'h21 (Mirror: 6'h00)            
+      ARPI_PBYTE_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00                            
+      DA_ARPI_DDR400_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0                             
+      DA_RX_ARDQSIEN_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0                             
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x21, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+            P_Fld(0x21, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_DCM_CTRL0_0                                ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0                          -     @5331                                                         
+      DDRPHY_CLK_EN_OPT                            uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0)                  
+      DPHY_CMD_CLKEN_EXTCNT                        uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[10:8]=3'h3                                
+      DDRPHY_CLK_DYN_GATING_SEL                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0)                
+      APHYPI_CKCGL_CNT                             uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[19:16]=4'h2                               
+      APHYPI_CKCGH_CNT                             uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[23:20]=4'h4                               
+      FASTWAKE2                                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[29:29]=1'h0                               
+      FASTWAKE                                     uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[31:31]=1'h1                               
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+            P_Fld(0x3, SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+            P_Fld(0x2, SHU_DCM_CTRL0_APHYPI_CKCGL_CNT) | P_Fld(0x4, SHU_DCM_CTRL0_APHYPI_CKCGH_CNT) |
+            P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_APHY_TX_PICG_CTRL_0                        ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0                  -     @5683                                                         
+      DDRPHY_CLK_EN_COMB_TX_PICG_CNT               uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h3 (Mirror: 4'h0)          
+      DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1             uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h3 (Mirror: 3'h0)          
+      DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0             uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h2 (Mirror: 3'h0)         
+      DPHY_TX_DCM_EXTCNT                           uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[15:12]=4'h2                       
+      DDRPHY_CLK_EN_COMB_TX_OPT                    uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0)        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) |
+            P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) |
+            P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_APHY_TX_PICG_CTRL_0_0                    ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0              -     @5221                                                         
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h3 (Mirror: 3'h0)      
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h3 (Mirror: 3'h0)      
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+            P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_APHY_TX_PICG_CTRL_0_1                    ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1              -     @5226                                                         
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h3 (Mirror: 3'h0)      
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h3 (Mirror: 3'h0)      
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+            P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_NEW_XRW2W_CTRL_0                           ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0                     -     @5677                                                         
+      TX_PI_UPDCTL_B0                              uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h3 (Mirror: 3'h0)           
+      TX_PI_UPDCTL_B1                              uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h3 (Mirror: 3'h0)           
+      TXPI_UPD_MODE                                uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1)           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) |
+            P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_DQS0_0                               ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0                         -     @5576                                                         
+      TXDLY_DQS0                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[2:0]=3'h4 (Mirror: 3'h1)                 
+      TXDLY_DQS1                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[6:4]=3'h4 (Mirror: 3'h1)                 
+      TXDLY_DQS2                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[10:8]=3'h1                               
+      TXDLY_DQS3                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[14:12]=3'h1                              
+      TXDLY_OEN_DQS0                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[18:16]=3'h3 (Mirror: 3'h1)               
+      TXDLY_OEN_DQS1                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[22:20]=3'h3 (Mirror: 3'h1)               
+      TXDLY_OEN_DQS2                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[26:24]=3'h1                              
+      TXDLY_OEN_DQS3                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[30:28]=3'h1                              
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) |
+            P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) |
+            P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS1));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_DQS1_0                               ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0                         -     @5587                                                         
+      dly_DQS0                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[3:0]=4'h1                                
+      dly_DQS1                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[7:4]=4'h1                                
+      dly_DQS2                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[11:8]=4'h1                               
+      dly_DQS3                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[15:12]=4'h1                              
+      dly_oen_DQS0                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[19:16]=4'h6 (Mirror: 4'h1)               
+      dly_oen_DQS1                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[23:20]=4'h6 (Mirror: 4'h1)               
+      dly_oen_DQS2                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[27:24]=4'h1                              
+      dly_oen_DQS3                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[31:28]=4'h1                              
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS0) |
+            P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS0) |
+            P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ0_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0                      -     @5041                                                         
+      TXDLY_DQ0                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[2:0]=3'h3 (Mirror: 3'h1)              
+      TXDLY_DQ1                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[6:4]=3'h3 (Mirror: 3'h1)              
+      TXDLY_DQ2                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1                            
+      TXDLY_DQ3                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1                           
+      TXDLY_OEN_DQ0                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[18:16]=3'h3 (Mirror: 3'h1)            
+      TXDLY_OEN_DQ1                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[22:20]=3'h3 (Mirror: 3'h1)            
+      TXDLY_OEN_DQ2                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1                           
+      TXDLY_OEN_DQ3                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+            P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+            P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ1_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0                      -     @5063                                                         
+      TXDLY_DQM0                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[2:0]=3'h3 (Mirror: 3'h1)              
+      TXDLY_DQM1                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[6:4]=3'h3 (Mirror: 3'h1)              
+      TXDLY_DQM2                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1                            
+      TXDLY_DQM3                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1                           
+      TXDLY_OEN_DQM0                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[18:16]=3'h3 (Mirror: 3'h1)            
+      TXDLY_OEN_DQM1                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[22:20]=3'h3 (Mirror: 3'h1)            
+      TXDLY_OEN_DQM2                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1                           
+      TXDLY_OEN_DQM3                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+            P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+            P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ2_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0                      -     @5085                                                         
+      dly_DQ0                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[3:0]=4'h2 (Mirror: 4'h1)              
+      dly_DQ1                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[7:4]=4'h2 (Mirror: 4'h1)              
+      dly_DQ2                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1                            
+      dly_DQ3                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1                           
+      dly_oen_DQ0                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[19:16]=4'h7 (Mirror: 4'h1)            
+      dly_oen_DQ1                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[23:20]=4'h7 (Mirror: 4'h1)            
+      dly_oen_DQ2                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1                           
+      dly_oen_DQ3                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ0) |
+            P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+            P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ3_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0                      -     @5107                                                         
+      dly_DQM0                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[3:0]=4'h2 (Mirror: 4'h1)              
+      dly_DQM1                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[7:4]=4'h2 (Mirror: 4'h1)              
+      dly_DQM2                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1                            
+      dly_DQM3                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1                           
+      dly_oen_DQM0                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[19:16]=4'h7 (Mirror: 4'h1)            
+      dly_oen_DQM1                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[23:20]=4'h7 (Mirror: 4'h1)            
+      dly_oen_DQM2                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1                           
+      dly_oen_DQM3                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM0) |
+            P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+            P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ0_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1                      -     @5052                                                         
+      TXDLY_DQ0                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[2:0]=3'h3 (Mirror: 3'h1)              
+      TXDLY_DQ1                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[6:4]=3'h3 (Mirror: 3'h1)              
+      TXDLY_DQ2                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1                            
+      TXDLY_DQ3                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1                           
+      TXDLY_OEN_DQ0                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[18:16]=3'h4 (Mirror: 3'h1)            
+      TXDLY_OEN_DQ1                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[22:20]=3'h4 (Mirror: 3'h1)            
+      TXDLY_OEN_DQ2                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1                           
+      TXDLY_OEN_DQ3                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+            P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+            P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ1_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1                      -     @5074                                                         
+      TXDLY_DQM0                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[2:0]=3'h3 (Mirror: 3'h1)              
+      TXDLY_DQM1                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[6:4]=3'h3 (Mirror: 3'h1)              
+      TXDLY_DQM2                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1                            
+      TXDLY_DQM3                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1                           
+      TXDLY_OEN_DQM0                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[18:16]=3'h4 (Mirror: 3'h1)            
+      TXDLY_OEN_DQM1                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[22:20]=3'h4 (Mirror: 3'h1)            
+      TXDLY_OEN_DQM2                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1                           
+      TXDLY_OEN_DQM3                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+            P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+            P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ2_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1                      -     @5096                                                         
+      dly_DQ0                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[3:0]=4'h3 (Mirror: 4'h1)              
+      dly_DQ1                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[7:4]=4'h3 (Mirror: 4'h1)              
+      dly_DQ2                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1                            
+      dly_DQ3                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1                           
+      dly_oen_DQ0                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[19:16]=4'h0 (Mirror: 4'h1)            
+      dly_oen_DQ1                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[23:20]=4'h0 (Mirror: 4'h1)            
+      dly_oen_DQ2                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1                           
+      dly_oen_DQ3                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_SELPH_DQ2_DLY_DQ0) |
+            P_Fld(0x3, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x0, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+            P_Fld(0x0, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ3_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1                      -     @5118                                                         
+      dly_DQM0                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[3:0]=4'h3 (Mirror: 4'h1)              
+      dly_DQM1                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[7:4]=4'h3 (Mirror: 4'h1)              
+      dly_DQM2                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1                            
+      dly_DQM3                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1                           
+      dly_oen_DQM0                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[19:16]=4'h0 (Mirror: 4'h1)            
+      dly_oen_DQM1                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[23:20]=4'h0 (Mirror: 4'h1)            
+      dly_oen_DQM2                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1                           
+      dly_oen_DQM3                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_SELPH_DQ3_DLY_DQM0) |
+            P_Fld(0x3, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x0, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+            P_Fld(0x0, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL1_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0                    -     @5129                                                         
+      BOOT_ORIG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h011 (Mirror: 11'h000)     
+      BOOT_ORIG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h012 (Mirror: 11'h000)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x011, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+            P_Fld(0x012, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL2_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0                    -     @5139                                                         
+      BOOT_TARG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h011 (Mirror: 11'h000)     
+      BOOT_TARG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h012 (Mirror: 11'h000)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x011, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+            P_Fld(0x012, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL5_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0                    -     @5177                                                         
+      BOOT_TARG_UI_RK0_DQM0                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h011 (Mirror: 11'h000)     
+      BOOT_TARG_UI_RK0_DQM1                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h012 (Mirror: 11'h000)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x011, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+            P_Fld(0x012, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL1_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1                    -     @5134                                                         
+      BOOT_ORIG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h016 (Mirror: 11'h000)     
+      BOOT_ORIG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h021 (Mirror: 11'h000)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x016, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+            P_Fld(0x021, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL2_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1                    -     @5144                                                         
+      BOOT_TARG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h016 (Mirror: 11'h000)     
+      BOOT_TARG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h021 (Mirror: 11'h000)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x016, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+            P_Fld(0x021, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL5_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1                    -     @5182                                                         
+      BOOT_TARG_UI_RK0_DQM0                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h016 (Mirror: 11'h000)     
+      BOOT_TARG_UI_RK0_DQM1                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h021 (Mirror: 11'h000)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x016, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+            P_Fld(0x021, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_PI_0_0                                   ral_reg_DRAMC_blk_SHURK_PI_0_0                             -     @5187                                                         
+      RK0_ARPI_DQ_B1                               uvm_reg_field                                              ...    RW SHURK_PI_0_0[5:0]=6'h12 (Mirror: 6'h00)                   
+      RK0_ARPI_DQ_B0                               uvm_reg_field                                              ...    RW SHURK_PI_0_0[13:8]=6'h11 (Mirror: 6'h00)                  
+      RK0_ARPI_DQM_B1                              uvm_reg_field                                              ...    RW SHURK_PI_0_0[21:16]=6'h12 (Mirror: 6'h00)                 
+      RK0_ARPI_DQM_B0                              uvm_reg_field                                              ...    RW SHURK_PI_0_0[29:24]=6'h11 (Mirror: 6'h00)                 
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x12, SHURK_PI_RK0_ARPI_DQ_B1) |
+            P_Fld(0x11, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x12, SHURK_PI_RK0_ARPI_DQM_B1) |
+            P_Fld(0x11, SHURK_PI_RK0_ARPI_DQM_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_PI_0_1                                   ral_reg_DRAMC_blk_SHURK_PI_0_1                             -     @5194                                                         
+      RK0_ARPI_DQ_B1                               uvm_reg_field                                              ...    RW SHURK_PI_0_1[5:0]=6'h21 (Mirror: 6'h00)                   
+      RK0_ARPI_DQ_B0                               uvm_reg_field                                              ...    RW SHURK_PI_0_1[13:8]=6'h16 (Mirror: 6'h00)                  
+      RK0_ARPI_DQM_B1                              uvm_reg_field                                              ...    RW SHURK_PI_0_1[21:16]=6'h21 (Mirror: 6'h00)                 
+      RK0_ARPI_DQM_B0                              uvm_reg_field                                              ...    RW SHURK_PI_0_1[29:24]=6'h16 (Mirror: 6'h00)                 
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x21, SHURK_PI_RK0_ARPI_DQ_B1) |
+            P_Fld(0x16, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x21, SHURK_PI_RK0_ARPI_DQM_B1) |
+            P_Fld(0x16, SHURK_PI_RK0_ARPI_DQM_B0));
+
+    #if !CODE_SIZE_REDUCE
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0                    -     @7826                                                         
+      TX_ARDQ0_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h08 (Mirror: 8'h00)           
+      TX_ARDQ1_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h08 (Mirror: 8'h00)          
+      TX_ARDQ2_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h08 (Mirror: 8'h00)         
+      TX_ARDQ3_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h08 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+            P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+            P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0                    -     @7840                                                         
+      TX_ARDQ4_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h08 (Mirror: 8'h00)           
+      TX_ARDQ5_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h08 (Mirror: 8'h00)          
+      TX_ARDQ6_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h08 (Mirror: 8'h00)         
+      TX_ARDQ7_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h08 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+            P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+            P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0                    -     @7868                                                         
+      TX_ARDQM0_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h08 (Mirror: 8'h00)           
+      TX_ARWCK_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00                         
+      TX_ARWCKB_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x08, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+            P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0                    -     @9233                                                         
+      TX_ARDQ0_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h04 (Mirror: 8'h00)           
+      TX_ARDQ1_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h04 (Mirror: 8'h00)          
+      TX_ARDQ2_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h04 (Mirror: 8'h00)         
+      TX_ARDQ3_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h04 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+            P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+            P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0                    -     @9247                                                         
+      TX_ARDQ4_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h04 (Mirror: 8'h00)           
+      TX_ARDQ5_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h04 (Mirror: 8'h00)          
+      TX_ARDQ6_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h04 (Mirror: 8'h00)         
+      TX_ARDQ7_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h04 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+            P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+            P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0                    -     @9275                                                         
+      TX_ARDQM0_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h04 (Mirror: 8'h00)           
+      TX_ARWCK_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00                         
+      TX_ARWCKB_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x04, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+            P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1                    -     @7833                                                         
+      TX_ARDQ0_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h34 (Mirror: 8'h00)           
+      TX_ARDQ1_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h34 (Mirror: 8'h00)          
+      TX_ARDQ2_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h34 (Mirror: 8'h00)         
+      TX_ARDQ3_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h34 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+            P_Fld(0x34, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x34, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+            P_Fld(0x34, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1                    -     @7847                                                         
+      TX_ARDQ4_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h34 (Mirror: 8'h00)           
+      TX_ARDQ5_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h34 (Mirror: 8'h00)          
+      TX_ARDQ6_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h34 (Mirror: 8'h00)         
+      TX_ARDQ7_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h34 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+            P_Fld(0x34, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x34, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+            P_Fld(0x34, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1                    -     @7874                                                         
+      TX_ARDQM0_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h34 (Mirror: 8'h00)           
+      TX_ARWCK_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00                         
+      TX_ARWCKB_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+            P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1                    -     @9240                                                         
+      TX_ARDQ0_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h08 (Mirror: 8'h00)           
+      TX_ARDQ1_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h08 (Mirror: 8'h00)          
+      TX_ARDQ2_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h08 (Mirror: 8'h00)         
+      TX_ARDQ3_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h08 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+            P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+            P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1                    -     @9254                                                         
+      TX_ARDQ4_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h08 (Mirror: 8'h00)           
+      TX_ARDQ5_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h08 (Mirror: 8'h00)          
+      TX_ARDQ6_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h08 (Mirror: 8'h00)         
+      TX_ARDQ7_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h08 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+            P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+            P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1                    -     @9281                                                         
+      TX_ARDQM0_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h08 (Mirror: 8'h00)           
+      TX_ARWCK_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00                         
+      TX_ARWCKB_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+            P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_TX_RANKCTL_0                               ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0                         -     @5651                                                         
+      TXRANKINCTL_TXDLY                            uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[3:0]=4'h2 (Mirror: 4'h0)                 
+      TXRANKINCTL                                  uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[7:4]=4'h2 (Mirror: 4'h0)                 
+      TXRANKINCTL_ROOT                             uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[11:8]=4'h0                               
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) |
+            P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT));
+    #endif
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit:
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter:
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_AC_DERATING0_0                             ral_reg_DRAMC_blk_SHU_AC_DERATING0_0                       -     @5538                                                         
+      ACDERATEEN                                   uvm_reg_field                                              ...    RW SHU_AC_DERATING0_0[0:0]=1'h0                              
+      TRRD_DERATE                                  uvm_reg_field                                              ...    RW SHU_AC_DERATING0_0[18:16]=3'h5 (Mirror: 3'h0)             
+      TRCD_DERATE                                  uvm_reg_field                                              ...    RW SHU_AC_DERATING0_0[27:24]=4'h9 (Mirror: 4'h0)             
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !(CODE_SIZE_REDUCE && AC_TIMING_DERATE_ENABLE)
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING0, P_Fld(0x0, SHU_AC_DERATING0_ACDERATEEN) |
+            P_Fld(0x5, SHU_AC_DERATING0_TRRD_DERATE) | P_Fld(0x9, SHU_AC_DERATING0_TRCD_DERATE));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_AC_DERATING1_0                             ral_reg_DRAMC_blk_SHU_AC_DERATING1_0                       -     @5544                                                         
+      TRPAB_DERATE                                 uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[3:0]=4'h9 (Mirror: 4'h0)               
+      TRP_DERATE                                   uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[11:8]=4'h8 (Mirror: 4'h0)              
+      TRAS_DERATE                                  uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[21:16]=6'h0c (Mirror: 6'h00)           
+      TRC_DERATE                                   uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[28:24]=5'h00                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING1, P_Fld(0x9, SHU_AC_DERATING1_TRPAB_DERATE) |
+            P_Fld(0x8, SHU_AC_DERATING1_TRP_DERATE) | P_Fld(0x0c, SHU_AC_DERATING1_TRAS_DERATE) |
+            P_Fld(0x00, SHU_AC_DERATING1_TRC_DERATE));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_AC_DERATING_05T_0                          ral_reg_DRAMC_blk_SHU_AC_DERATING_05T_0                    -     @5551                                                         
+      TRC_05T_DERATE                               uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[0:0]=1'h0                           
+      TRCD_05T_DERATE                              uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[6:6]=1'h1 (Mirror: 1'h0)            
+      TRP_05T_DERATE                               uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[7:7]=1'h0                           
+      TRPAB_05T_DERATE                             uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[8:8]=1'h1 (Mirror: 1'h0)            
+      TRAS_05T_DERATE                              uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[9:9]=1'h0                           
+      TRRD_05T_DERATE                              uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[12:12]=1'h0                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING_05T, P_Fld(0x0, SHU_AC_DERATING_05T_TRC_05T_DERATE) |
+            P_Fld(0x1, SHU_AC_DERATING_05T_TRCD_05T_DERATE) | P_Fld(0x0, SHU_AC_DERATING_05T_TRP_05T_DERATE) |
+            P_Fld(0x1, SHU_AC_DERATING_05T_TRPAB_05T_DERATE) | P_Fld(0x0, SHU_AC_DERATING_05T_TRAS_05T_DERATE) |
+            P_Fld(0x0, SHU_AC_DERATING_05T_TRRD_05T_DERATE));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SREF_CTRL_0                                ral_reg_DRAMC_blk_SHU_SREF_CTRL_0                          -     @5322                                                         
+      CKEHCMD                                      uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[5:4]=2'h3                                 
+      SREF_CK_DLY                                  uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0)                
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) |
+            P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_HMR4_DVFS_CTRL0_0                          ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0                    -     @5341                                                         
+      FSPCHG_PRDCNT                                uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h75 (Mirror: 8'h00)         
+      REFRCNT                                      uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000                      
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x75, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+            P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_AC_TIME_05T_0                              ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0                        -     @5504                                                         
+      TRC_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[0:0]=1'h0                               
+      TRFCPB_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[1:1]=1'h0                               
+      TRFC_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[2:2]=1'h1 (Mirror: 1'h0)                
+      TPBR2PBR_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[3:3]=1'h0                               
+      TXP_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[4:4]=1'h1 (Mirror: 1'h0)                
+      TRTP_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[5:5]=1'h0                               
+      TRCD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[6:6]=1'h1 (Mirror: 1'h0)                
+      TRP_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[7:7]=1'h0                               
+      TRPAB_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[8:8]=1'h1 (Mirror: 1'h0)                
+      TRAS_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[9:9]=1'h1 (Mirror: 1'h0)                
+      TWR_M05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0)              
+      TRRD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[12:12]=1'h0                             
+      TFAW_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[13:13]=1'h0                             
+      TCKEPRD_05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[14:14]=1'h0                             
+      TR2PD_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[15:15]=1'h0                             
+      TWTPD_M05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[16:16]=1'h1 (Mirror: 1'h0)              
+      TMRRI_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[17:17]=1'h0                             
+      TMRWCKEL_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[18:18]=1'h0                             
+      BGTRRD_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[19:19]=1'h0                             
+      BGTCCD_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[20:20]=1'h0                             
+      BGTWTR_M05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[21:21]=1'h0                             
+      TR2W_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[22:22]=1'h0                             
+      TWTR_M05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[23:23]=1'h0                             
+      XRTR2W_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[24:24]=1'h0                             
+      TMRD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[25:25]=1'h1 (Mirror: 1'h0)              
+      TMRW_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[26:26]=1'h0                             
+      TMRR2MRW_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[27:27]=1'h1 (Mirror: 1'h0)              
+      TW2MRW_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[28:28]=1'h0                             
+      TR2MRW_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[29:29]=1'h1 (Mirror: 1'h0)              
+      TPBR2ACT_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[30:30]=1'h1 (Mirror: 1'h0)              
+      XRTW2R_M05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[31:31]=1'h0                             
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T,
+            P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTWTR_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T));
+
+     #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRFC_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TXP_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRCD_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRPAB_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTPD_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TMRRI_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRWCKEL_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTPD_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TMRRI_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRWCKEL_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TWTR_M05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TMRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRW_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TMRR2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TR2MRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TPBR2ACT_05T));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM_XRT_0                                ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0                          -     @5497                                                         
+      XRTR2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[4:0]=5'h03 (Mirror: 5'h01)                
+      XRTR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[13:8]=6'h08 (Mirror: 6'h01)               
+      XRTW2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[19:16]=4'h1                               
+      XRTW2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[28:24]=5'h05 (Mirror: 5'h01)              
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x03, SHU_ACTIM_XRT_XRTR2R) |
+            P_Fld(0x08, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x1, SHU_ACTIM_XRT_XRTW2R) |
+            P_Fld(0x05, SHU_ACTIM_XRT_XRTW2W));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM0_0                                   ral_reg_DRAMC_blk_SHU_ACTIM0_0                             -     @5443                                                         
+      TWTR                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[5:0]=6'h08 (Mirror: 6'h01)                   
+      TWR                                          uvm_reg_field                                              ...    RW SHU_ACTIM0_0[15:8]=8'h0d (Mirror: 8'h06)                  
+      TRRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[18:16]=3'h4 (Mirror: 3'h0)                   
+      TRCD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[27:24]=4'h8 (Mirror: 4'h2)                   
+      CKELCKCNT                                    uvm_reg_field                                              ...    RW SHU_ACTIM0_0[31:28]=4'h3 (Mirror: 4'h0)                   
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x08, SHU_ACTIM0_TWTR) |
+            P_Fld(0x0d, SHU_ACTIM0_TWR) | P_Fld(0x4, SHU_ACTIM0_TRRD) |
+            P_Fld(0x8, SHU_ACTIM0_TRCD) | P_Fld(0x3, SHU_ACTIM0_CKELCKCNT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM1_0                                   ral_reg_DRAMC_blk_SHU_ACTIM1_0                             -     @5451                                                         
+      TRPAB                                        uvm_reg_field                                              ...    RW SHU_ACTIM1_0[3:0]=4'h8 (Mirror: 4'ha)                     
+      TMRWCKEL                                     uvm_reg_field                                              ...    RW SHU_ACTIM1_0[7:4]=4'h8                                    
+      TRP                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[11:8]=4'h7 (Mirror: 4'h2)                    
+      TRAS                                         uvm_reg_field                                              ...    RW SHU_ACTIM1_0[21:16]=6'h0b (Mirror: 6'h04)                 
+      TRC                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[28:24]=5'h00 (Mirror: 5'h05)                 
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x8, SHU_ACTIM1_TRPAB) |
+            P_Fld(0x8, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x7, SHU_ACTIM1_TRP) |
+            P_Fld(0x0b, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM2_0                                   ral_reg_DRAMC_blk_SHU_ACTIM2_0                             -     @5459                                                         
+      TXP                                          uvm_reg_field                                              ...    RW SHU_ACTIM2_0[3:0]=4'h0                                    
+      TMRRI                                        uvm_reg_field                                              ...    RW SHU_ACTIM2_0[8:4]=5'h0c (Mirror: 5'h0e)                   
+      TRTP                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[14:12]=3'h2 (Mirror: 3'h0)                   
+      TR2W                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[21:16]=6'h09 (Mirror: 6'h00)                 
+      TFAW                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[28:24]=5'h0b (Mirror: 5'h05)                 
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x0, SHU_ACTIM2_TXP) |
+            P_Fld(0x0c, SHU_ACTIM2_TMRRI) | P_Fld(0x2, SHU_ACTIM2_TRTP) |
+            P_Fld(0x09, SHU_ACTIM2_TR2W) | P_Fld(0x0b, SHU_ACTIM2_TFAW));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM3_0                                   ral_reg_DRAMC_blk_SHU_ACTIM3_0                             -     @5467                                                         
+      TRFCPB                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[7:0]=8'h4d (Mirror: 8'h00)                   
+      MANTMRR                                      uvm_reg_field                                              ...    RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0)                    
+      TR2MRR                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0)                   
+      TRFC                                         uvm_reg_field                                              ...    RW SHU_ACTIM3_0[23:16]=8'ha5 (Mirror: 8'h00)                 
+      TWTR_L                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[29:24]=6'h00                                 
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x4d, SHU_ACTIM3_TRFCPB) |
+            P_Fld(0x4, SHU_ACTIM3_TR2MRR) | P_Fld(0xa5, SHU_ACTIM3_TRFC));
+    #endif
+
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x4, SHU_ACTIM3_MANTMRR) |
+            P_Fld(0x00, SHU_ACTIM3_TWTR_L));
+    #if !CODE_SIZE_REDUCE
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM4_0                                   ral_reg_DRAMC_blk_SHU_ACTIM4_0                             -     @5475                                                         
+      TXREFCNT                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[9:0]=10'h0b5 (Mirror: 10'h028)               
+      TMRR2MRW                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[15:10]=6'h0d (Mirror: 6'h00)                 
+      TMRR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM4_0[21:16]=6'h0c (Mirror: 6'h00)                 
+      TZQCS                                        uvm_reg_field                                              ...    RW SHU_ACTIM4_0[31:24]=8'h28 (Mirror: 8'h00)                 
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x0b5, SHU_ACTIM4_TXREFCNT) |
+            P_Fld(0x0d, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0c, SHU_ACTIM4_TMRR2W) |
+            P_Fld(0x28, SHU_ACTIM4_TZQCS));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM5_0                                   ral_reg_DRAMC_blk_SHU_ACTIM5_0                             -     @5482                                                         
+      TR2PD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[6:0]=7'h0e (Mirror: 7'h00)                   
+      TWTPD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[14:8]=7'h10 (Mirror: 7'h00)                  
+      TPBR2PBR                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[23:16]=8'h23 (Mirror: 8'h00)                 
+      TPBR2ACT                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[29:28]=2'h0                                  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x0e, SHU_ACTIM5_TR2PD) |
+            P_Fld(0x10, SHU_ACTIM5_TWTPD) | P_Fld(0x23, SHU_ACTIM5_TPBR2PBR) |
+            P_Fld(0x0, SHU_ACTIM5_TPBR2ACT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM6_0                                   ral_reg_DRAMC_blk_SHU_ACTIM6_0                             -     @5489                                                         
+      TZQLAT2                                      uvm_reg_field                                              ...    RW SHU_ACTIM6_0[4:0]=5'h0e (Mirror: 5'h1f)                   
+      TMRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[11:8]=4'h7 (Mirror: 4'h0)                    
+      TMRW                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0)                   
+      TW2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[25:20]=6'h0a (Mirror: 6'h00)                 
+      TR2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[31:26]=6'h10 (Mirror: 6'h13)                 
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x0e, SHU_ACTIM6_TZQLAT2) |
+            P_Fld(0x7, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) |
+            P_Fld(0x0a, SHU_ACTIM6_TW2MRW) | P_Fld(0x10, SHU_ACTIM6_TR2MRW));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_CKECTRL_0                                  ral_reg_DRAMC_blk_SHU_CKECTRL_0                            -     @5567                                                         
+      TPDE_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0)                    
+      TPDX_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[1:1]=1'h0                                   
+      TPDE                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[14:12]=3'h1                                 
+      TPDX                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[18:16]=3'h1                                 
+      TCKEPRD                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[22:20]=3'h3 (Mirror: 3'h2)                  
+      TCKESRX                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0)                  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) |
+            P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) |
+            P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x3, SHU_CKECTRL_TCKEPRD));
+    #endif
+
+    vIO32WriteFldAlign(DRAMC_REG_SHU_CKECTRL, 0x3, SHU_CKECTRL_TCKESRX);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_0                                     ral_reg_DRAMC_blk_SHU_MISC_0                               -     @5671                                                         
+      REQQUE_MAXCNT                                uvm_reg_field                                              ...    RW SHU_MISC_0[3:0]=4'h2                                      
+      DCMDLYREF                                    uvm_reg_field                                              ...    RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4)                     
+      DAREFEN                                      uvm_reg_field                                              ...    RW SHU_MISC_0[30:30]=1'h0                                    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x7, SHU_MISC_DCMDLYREF) |
+            P_Fld(0x0, SHU_MISC_DAREFEN));
+
+    #if !CODE_SIZE_REDUCE
+	vIO32WriteFldAlign(DRAMC_REG_SHU_MISC, 0x2, SHU_MISC_REQQUE_MAXCNT);
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter.
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit.
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ8_0                            -     @8226                                                         
+      R_DMRXDVS_UPD_FORCE_CYC_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[14:0]=15'h00e7 (Mirror: 15'h0000)            
+      R_DMRXDVS_UPD_FORCE_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[15:15]=1'h0                                  
+      R_DMRANK_RXDLY_PIPE_CG_IG_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[19:19]=1'h0                                  
+      R_RMRODTEN_CG_IG_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[20:20]=1'h0                                  
+      R_RMRX_TOPHY_CG_IG_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)                   
+      R_DMRXDVS_RDSEL_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[22:22]=1'h0                                  
+      R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0            uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[23:23]=1'h0                                  
+      R_DMRXDLY_CG_IG_B0                           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)                   
+      R_DMDQSIEN_FLAG_SYNC_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[26:26]=1'h0                                  
+      R_DMDQSIEN_FLAG_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[27:27]=1'h0                                  
+      R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0               uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[28:28]=1'h0                                  
+      R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[29:29]=1'h0                                  
+      R_DMRANK_PIPE_CG_IG_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[30:30]=1'h0                                  
+      R_DMRANK_CHG_PIPE_CG_IG_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[31:31]=1'h0                                  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+            P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+    #endif
+
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x00e7, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ8_0                            -     @9633                                                         
+      R_DMRXDVS_UPD_FORCE_CYC_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[14:0]=15'h00e7 (Mirror: 15'h0000)            
+      R_DMRXDVS_UPD_FORCE_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[15:15]=1'h0                                  
+      R_DMRANK_RXDLY_PIPE_CG_IG_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[19:19]=1'h0                                  
+      R_RMRODTEN_CG_IG_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[20:20]=1'h0                                  
+      R_RMRX_TOPHY_CG_IG_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)                   
+      R_DMRXDVS_RDSEL_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[22:22]=1'h0                                  
+      R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1            uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[23:23]=1'h0                                  
+      R_DMRXDLY_CG_IG_B1                           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)                   
+      R_DMDQSIEN_FLAG_SYNC_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[26:26]=1'h0                                  
+      R_DMDQSIEN_FLAG_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[27:27]=1'h0                                  
+      R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1               uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[28:28]=1'h0                                  
+      R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[29:29]=1'h0                                  
+      R_DMRANK_PIPE_CG_IG_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[30:30]=1'h0                                  
+      R_DMRANK_CHG_PIPE_CG_IG_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[31:31]=1'h0                                  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x00e7, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+            P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ5_0                            -     @8126                                                         
+      RG_RX_ARDQ_VREF_SEL_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[5:0]=6'h0e                                   
+      RG_RX_ARDQ_VREF_BYPASS_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[6:6]=1'h0                                    
+      RG_ARPI_FB_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[13:8]=6'h00                                  
+      RG_RX_ARDQS0_DQSIEN_DLY_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[18:16]=3'h0                                  
+      RG_RX_ARDQS_DQSIEN_RB_DLY_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[19:19]=1'h0                                  
+      RG_RX_ARDQS0_DVS_DLY_B0                      uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[23:20]=4'h4 (Mirror: 4'h0)                   
+      RG_RX_ARDQ_FIFO_DQSI_DLY_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[31:29]=3'h0                                  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) |
+            P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) |
+            P_Fld(0x4, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ5_0                            -     @9533                                                         
+      RG_RX_ARDQ_VREF_SEL_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[5:0]=6'h0e                                   
+      RG_RX_ARDQ_VREF_BYPASS_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[6:6]=1'h0                                    
+      RG_ARPI_FB_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[13:8]=6'h00                                  
+      RG_RX_ARDQS0_DQSIEN_DLY_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[18:16]=3'h0                                  
+      RG_RX_ARDQS_DQSIEN_RB_DLY_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[19:19]=1'h0                                  
+      RG_RX_ARDQS0_DVS_DLY_B1                      uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[23:20]=4'h4 (Mirror: 4'h0)                   
+      RG_RX_ARDQ_FIFO_DQSI_DLY_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[31:29]=3'h0                                  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) |
+            P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) |
+            P_Fld(0x4, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0                    -     @7888                                                         
+      RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h6d (Mirror: 8'h00)           
+      RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h6d (Mirror: 8'h00)          
+      RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h6d (Mirror: 8'h00)         
+      RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h6d (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x6d, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) |
+            P_Fld(0x6d, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x6d, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+            P_Fld(0x6d, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0                    -     @7902                                                         
+      RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h6d (Mirror: 8'h00)           
+      RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h6d (Mirror: 8'h00)          
+      RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h6d (Mirror: 8'h00)         
+      RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h6d (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x6d, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+            P_Fld(0x6d, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+            P_Fld(0x6d, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0                    -     @7916                                                         
+      RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h6d (Mirror: 8'h00)           
+      RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h6d (Mirror: 8'h00)          
+      RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h6d (Mirror: 8'h00)         
+      RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h6d (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x6d, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+            P_Fld(0x6d, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+            P_Fld(0x6d, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0                    -     @7930                                                         
+      RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h6d (Mirror: 8'h00)           
+      RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h6d (Mirror: 8'h00)          
+      RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h6d (Mirror: 8'h00)         
+      RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h6d (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x6d, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+            P_Fld(0x6d, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+            P_Fld(0x6d, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0                    -     @7944                                                         
+      RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h6d (Mirror: 8'h00)           
+      RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h6d (Mirror: 8'h00)          
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x6d, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+            P_Fld(0x6d, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0                    -     @7954                                                         
+      RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h061 (Mirror: 9'h000)         
+      RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h061 (Mirror: 9'h000)       
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x061, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+            P_Fld(0x061, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1                    -     @7895                                                         
+      RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h6c (Mirror: 8'h00)           
+      RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h6c (Mirror: 8'h00)          
+      RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h6c (Mirror: 8'h00)         
+      RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h6c (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET),
+            P_Fld(0x6c, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) |
+            P_Fld(0x6c, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+    P_Fld(0x6c, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+	#endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1                    -     @7909                                                         
+      RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h6c (Mirror: 8'h00)           
+      RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h6c (Mirror: 8'h00)          
+      RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h6c (Mirror: 8'h00)         
+      RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h6c (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+            P_Fld(0x6c, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+            P_Fld(0x6c, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1                    -     @7923                                                         
+      RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h6c (Mirror: 8'h00)           
+      RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h6c (Mirror: 8'h00)          
+      RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h6c (Mirror: 8'h00)         
+      RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h6c (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+            P_Fld(0x6c, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+            P_Fld(0x6c, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1                    -     @7937                                                         
+      RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h6c (Mirror: 8'h00)           
+      RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h6c (Mirror: 8'h00)          
+      RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h6c (Mirror: 8'h00)         
+      RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h6c (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+            P_Fld(0x6c, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+            P_Fld(0x6c, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1                    -     @7949                                                         
+      RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h6c (Mirror: 8'h00)           
+      RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h6c (Mirror: 8'h00)          
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+            P_Fld(0x6c, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1                    -     @7959                                                         
+      RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h060 (Mirror: 9'h000)         
+      RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h060 (Mirror: 9'h000)       
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x060, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+            P_Fld(0x060, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0                    -     @9295                                                         
+      RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h6d (Mirror: 8'h00)           
+      RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h6d (Mirror: 8'h00)          
+      RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h6d (Mirror: 8'h00)         
+      RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h6d (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x6d, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) |
+            P_Fld(0x6d, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+	
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x6d, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+            P_Fld(0x6d, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0                    -     @9309                                                         
+      RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h6d (Mirror: 8'h00)           
+      RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h6d (Mirror: 8'h00)          
+      RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h6d (Mirror: 8'h00)         
+      RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h6d (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x6d, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+            P_Fld(0x6d, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+            P_Fld(0x6d, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0                    -     @9323                                                         
+      RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h6d (Mirror: 8'h00)           
+      RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h6d (Mirror: 8'h00)          
+      RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h6d (Mirror: 8'h00)         
+      RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h6d (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x6d, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+            P_Fld(0x6d, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+            P_Fld(0x6d, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0                    -     @9337                                                         
+      RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h6d (Mirror: 8'h00)           
+      RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h6d (Mirror: 8'h00)          
+      RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h6d (Mirror: 8'h00)         
+      RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h6d (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x6d, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+            P_Fld(0x6d, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+            P_Fld(0x6d, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0                    -     @9351                                                         
+      RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h6d (Mirror: 8'h00)           
+      RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h6d (Mirror: 8'h00)          
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x6d, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+            P_Fld(0x6d, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0                    -     @9361                                                         
+      RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h061 (Mirror: 9'h000)         
+      RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h061 (Mirror: 9'h000)       
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x061, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+            P_Fld(0x061, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1                    -     @9302                                                         
+      RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h6c (Mirror: 8'h00)           
+      RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h6c (Mirror: 8'h00)          
+      RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h6c (Mirror: 8'h00)         
+      RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h6c (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET),
+            P_Fld(0x6c, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) |
+            P_Fld(0x6c, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+            P_Fld(0x6c, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1                    -     @9316                                                         
+      RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h6c (Mirror: 8'h00)           
+      RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h6c (Mirror: 8'h00)          
+      RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h6c (Mirror: 8'h00)         
+      RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h6c (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+            P_Fld(0x6c, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+            P_Fld(0x6c, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1                    -     @9330                                                         
+      RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h6c (Mirror: 8'h00)           
+      RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h6c (Mirror: 8'h00)          
+      RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h6c (Mirror: 8'h00)         
+      RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h6c (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+            P_Fld(0x6c, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+            P_Fld(0x6c, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1                    -     @9344                                                         
+      RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h6c (Mirror: 8'h00)           
+      RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h6c (Mirror: 8'h00)          
+      RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h6c (Mirror: 8'h00)         
+      RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h6c (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+            P_Fld(0x6c, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+            P_Fld(0x6c, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1                    -     @9356                                                         
+      RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h6c (Mirror: 8'h00)           
+      RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h6c (Mirror: 8'h00)          
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+            P_Fld(0x6c, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1                    -     @9366                                                         
+      RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h060 (Mirror: 9'h000)         
+      RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h060 (Mirror: 9'h000)       
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x060, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+            P_Fld(0x060, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ9                                         ral_reg_DDRPHY_blk_B0_DQ9                                  -     @7782                                                         
+      RG_RX_ARDQ_STBEN_RESETB_B0                   uvm_reg_field                                              ...    RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0)                           
+      RG_RX_ARDQS0_STBEN_RESETB_B0                 uvm_reg_field                                              ...    RW B0_DQ9[4:4]=1'h0                                          
+      RG_RX_ARDQS0_DQSIENMODE_B0                   uvm_reg_field                                              ...    RW B0_DQ9[5:5]=1'h0                                          
+      R_DMRXDVS_R_F_DLY_RK_OPT_B0                  uvm_reg_field                                              ...    RW B0_DQ9[6:6]=1'h1                                          
+      R_DMRXFIFO_STBENCMP_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ9[7:7]=1'h0                                          
+      R_IN_GATE_EN_LOW_OPT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[15:8]=8'h00                                        
+      R_DMDQSIEN_VALID_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[18:16]=3'h0                                        
+      R_DMDQSIEN_RDSEL_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[22:20]=3'h0                                        
+      R_DMRXDVS_VALID_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[26:24]=3'h0                                        
+      R_DMRXDVS_RDSEL_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[30:28]=3'h0                                        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
+            P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
+            P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
+            P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
+            P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
+            P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ9                                         ral_reg_DDRPHY_blk_B1_DQ9                                  -     @9189                                                         
+      RG_RX_ARDQ_STBEN_RESETB_B1                   uvm_reg_field                                              ...    RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0)                           
+      RG_RX_ARDQS0_STBEN_RESETB_B1                 uvm_reg_field                                              ...    RW B1_DQ9[4:4]=1'h0                                          
+      RG_RX_ARDQS0_DQSIENMODE_B1                   uvm_reg_field                                              ...    RW B1_DQ9[5:5]=1'h0                                          
+      R_DMRXDVS_R_F_DLY_RK_OPT_B1                  uvm_reg_field                                              ...    RW B1_DQ9[6:6]=1'h1                                          
+      R_DMRXFIFO_STBENCMP_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ9[7:7]=1'h0                                          
+      R_IN_GATE_EN_LOW_OPT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[15:8]=8'h00                                        
+      R_DMDQSIEN_VALID_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[18:16]=3'h0                                        
+      R_DMDQSIEN_RDSEL_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[22:20]=3'h0                                        
+      R_DMRXDVS_VALID_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[26:24]=3'h0                                        
+      R_DMRXDVS_RDSEL_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[30:28]=3'h0                                        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
+            P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
+            P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
+            P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
+            P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
+            P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ4                                         ral_reg_DDRPHY_blk_B0_DQ4                                  -     @7711                                                         
+      RG_RX_ARDQS_EYE_R_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[6:0]=7'h75 (Mirror: 7'h00)                         
+      RG_RX_ARDQS_EYE_F_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[14:8]=7'h75 (Mirror: 7'h00)                        
+      RG_RX_ARDQ_EYE_R_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[21:16]=6'h2d (Mirror: 6'h00)                       
+      RG_RX_ARDQ_EYE_F_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[29:24]=6'h2d (Mirror: 6'h00)                       
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x75, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) |
+            P_Fld(0x75, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x2d, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) |
+            P_Fld(0x2d, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ4                                         ral_reg_DDRPHY_blk_B1_DQ4                                  -     @9118                                                         
+      RG_RX_ARDQS_EYE_R_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[6:0]=7'h75 (Mirror: 7'h00)                         
+      RG_RX_ARDQS_EYE_F_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[14:8]=7'h75 (Mirror: 7'h00)                        
+      RG_RX_ARDQ_EYE_R_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[21:16]=6'h2d (Mirror: 6'h00)                       
+      RG_RX_ARDQ_EYE_F_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[29:24]=6'h2d (Mirror: 6'h00)                       
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x75, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) |
+            P_Fld(0x75, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x2d, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) |
+            P_Fld(0x2d, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ5                                         ral_reg_DDRPHY_blk_B0_DQ5                                  -     @7718                                                         
+      RG_RX_ARDQ_EYE_VREF_SEL_B0                   uvm_reg_field                                              ...    RW B0_DQ5[13:8]=6'h0e                                        
+      RG_RX_ARDQ_VREF_EN_B0                        uvm_reg_field                                              ...    RW B0_DQ5[16:16]=1'h0                                        
+      RG_RX_ARDQ_EYE_VREF_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ5[17:17]=1'h0                                        
+      RG_RX_ARDQ_EYE_SEL_B0                        uvm_reg_field                                              ...    RW B0_DQ5[23:20]=4'h0                                        
+      RG_RX_ARDQ_EYE_EN_B0                         uvm_reg_field                                              ...    RW B0_DQ5[24:24]=1'h0                                        
+      RG_RX_ARDQ_EYE_STBEN_RESETB_B0               uvm_reg_field                                              ...    RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0)                         
+      RG_RX_ARDQS0_DVS_EN_B0                       uvm_reg_field                                              ...    RW B0_DQ5[31:31]=1'h0                                        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x0e, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) |
+            P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) |
+            P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) |
+            P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ5                                         ral_reg_DDRPHY_blk_B1_DQ5                                  -     @9125                                                         
+      RG_RX_ARDQ_EYE_VREF_SEL_B1                   uvm_reg_field                                              ...    RW B1_DQ5[13:8]=6'h0e                                        
+      RG_RX_ARDQ_VREF_EN_B1                        uvm_reg_field                                              ...    RW B1_DQ5[16:16]=1'h0                                        
+      RG_RX_ARDQ_EYE_VREF_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ5[17:17]=1'h0                                        
+      RG_RX_ARDQ_EYE_SEL_B1                        uvm_reg_field                                              ...    RW B1_DQ5[23:20]=4'h0                                        
+      RG_RX_ARDQ_EYE_EN_B1                         uvm_reg_field                                              ...    RW B1_DQ5[24:24]=1'h0                                        
+      RG_RX_ARDQ_EYE_STBEN_RESETB_B1               uvm_reg_field                                              ...    RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0)                         
+      RG_RX_ARDQS0_DVS_EN_B1                       uvm_reg_field                                              ...    RW B1_DQ5[31:31]=1'h0                                        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x0e, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) |
+            P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) |
+            P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) |
+            P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT
+    //    Exit body
+}
+
+
+void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p)
+{
+    //    Enter body
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter:
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_RDSEL_TRACK_0                         ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0                  -     @13241                                                     
+      DMDATLAT_i                                   uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h10 (Mirror: 5'h00)      
+      RDSEL_HWSAVE_MSK                             uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0)        
+      RDSEL_TRACK_EN                               uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0                       
+      SHU_GW_THRD_NEG                              uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfcb (Mirror: 12'h000) 
+      SHU_GW_THRD_POS                              uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h035 (Mirror: 12'h000)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x10, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) |
+            P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) |
+            P_Fld(0xfcb, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x035, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RDAT_0                                ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0                         -     @13111                                                     
+      DATLAT                                       uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[4:0]=5'h10 (Mirror: 5'h00)             
+      DATLAT_DSEL                                  uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[12:8]=5'h0f (Mirror: 5'h00)            
+      DATLAT_DSEL_PHY                              uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[20:16]=5'h0f (Mirror: 5'h00)           
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x10, MISC_SHU_RDAT_DATLAT) |
+            P_Fld(0x0f, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0f, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
+    #endif
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_PHY_RX_CTRL_0                         ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0                  -     @13047                                                     
+      RANK_RXDLY_UPDLAT_EN                         uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0)        
+      RANK_RXDLY_UPD_OFFSET                        uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0)       
+      RX_IN_GATE_EN_PRE_OFFSET                     uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0)      
+      RX_IN_GATE_EN_HEAD                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h1 (Mirror: 3'h0)      
+      RX_IN_GATE_EN_TAIL                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0)      
+      RX_IN_BUFF_EN_HEAD                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h2 (Mirror: 3'h0)      
+      RX_IN_BUFF_EN_TAIL                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0                     
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) |
+            P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) |
+            P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) |
+            P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RANKCTL_0                             ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0                      -     @13037                                                     
+      RANKINCTL_RXDLY                              uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[3:0]=4'h4 (Mirror: 4'h0)            
+      RANK_RXDLY_OPT                               uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[4:4]=1'h1                           
+      RANKSEL_SELPH_FRUN                           uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[15:15]=1'h1 (Mirror: 1'h0)          
+      RANKINCTL_STB                                uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[19:16]=4'h6 (Mirror: 4'h0)          
+      RANKINCTL                                    uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[23:20]=4'h5 (Mirror: 4'h0)          
+      RANKINCTL_ROOT1                              uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[27:24]=4'h5 (Mirror: 4'h0)          
+      RANKINCTL_PHY                                uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[31:28]=4'h8 (Mirror: 4'h0)          
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) |
+            P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x1, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) |
+            P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_STB));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL) |
+            P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x8, MISC_SHU_RANKCTL_RANKINCTL_PHY));
+    #endif
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RANK_SEL_LAT_0                        ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0                 -     @13264                                                     
+      RANK_SEL_LAT_B0                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0)       
+      RANK_SEL_LAT_B1                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0)       
+      RANK_SEL_LAT_CA                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0)      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
+            P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
+
+    #if !CODE_SIZE_REDUCE
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCTL_0_0                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0                  -     @12858                                                     
+      DQSINCTL                                     uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h7 (Mirror: 4'h0)        
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL);
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                      
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCTL_0_1                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1                  -     @12862                                                     
+      DQSINCTL                                     uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h7 (Mirror: 4'h0)        
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0         -     @8012                                                         
+      DQSIEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h1 (Mirror: 4'h0)  
+      DQSIEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h5 (Mirror: 4'h0)  
+      DQSIEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0)
+      DQSIEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+            P_Fld(0x5, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+            P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_PI_DLY_0_0                    ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0             -     @8026                                                         
+      DQSIEN_PI_B0                                 uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h01 (Mirror: 7'h00)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x01, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1         -     @8019                                                         
+      DQSIEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h9 (Mirror: 4'h0)  
+      DQSIEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hd (Mirror: 4'h0)  
+      DQSIEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0)
+      DQSIEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x9, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+            P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+            P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_PI_DLY_0_1                    ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1             -     @8030                                                         
+      DQSIEN_PI_B0                                 uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h08 (Mirror: 7'h00)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x08, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0         -     @9435                                                         
+      DQSIEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h1 (Mirror: 4'h0)  
+      DQSIEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h5 (Mirror: 4'h0)  
+      DQSIEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0)
+      DQSIEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+            P_Fld(0x5, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+            P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_PI_DLY_0_0                    ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0             -     @9449                                                         
+      DQSIEN_PI_B1                                 uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h01 (Mirror: 7'h00)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x01, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1         -     @9442                                                         
+      DQSIEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h9 (Mirror: 4'h0)  
+      DQSIEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hd (Mirror: 4'h0)  
+      DQSIEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0)
+      DQSIEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x9, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+            P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+            P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_PI_DLY_0_1                    ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1             -     @9453                                                         
+      DQSIEN_PI_B1                                 uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h08 (Mirror: 7'h00)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x08, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_ODTCTRL_0                             ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0                      -     @13057                                                        
+      RODTEN                                       uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0)               
+      RODTENSTB_SELPH_CG_IG                        uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[1:1]=1'h0                              
+      RODT_LAT                                     uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[7:4]=4'h7 (Mirror: 4'h0)               
+      RODTEN_SELPH_FRUN                            uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[15:15]=1'h0                            
+      RODTDLY_LAT_OPT                              uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[25:24]=2'h0                            
+      FIXRODT                                      uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[27:27]=1'h0                            
+      RODTEN_OPT                                   uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[29:29]=1'h1                            
+      RODTE2                                       uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0)             
+      RODTE                                        uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0)             
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) |
+            P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) |
+            P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_ODTCTRL, 0x7, MISC_SHU_ODTCTRL_RODT_LAT);
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ7_0                            -     @8204                                                         
+      R_DMRANKRXDVS_B0                             uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[3:0]=4'h0                                    
+      R_DMDQMDBI_EYE_SHU_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[6:6]=1'h0                                    
+      R_DMDQMDBI_SHU_B0                            uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[7:7]=1'h0                                    
+      R_DMRXDVS_DQM_FLAGSEL_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[11:8]=4'h0                                   
+      R_DMRXDVS_PBYTE_FLAG_OPT_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[12:12]=1'h0                                  
+      R_DMRXDVS_PBYTE_DQM_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[13:13]=1'h0                                  
+      R_DMRXTRACK_DQM_EN_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[14:14]=1'h0                                  
+      R_DMRODTEN_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)                   
+      R_DMARPI_CG_FB2DLL_DCM_EN_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[16:16]=1'h0                                  
+      R_DMTX_ARPI_CG_DQ_NEW_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[17:17]=1'h0                                  
+      R_DMTX_ARPI_CG_DQS_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[18:18]=1'h0                                  
+      R_DMTX_ARPI_CG_DQM_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[19:19]=1'h0                                  
+      R_LP4Y_SDN_MODE_DQS0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[20:20]=1'h0                                  
+      R_DMRXRANK_DQ_EN_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)                   
+      R_DMRXRANK_DQ_LAT_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[27:25]=3'h2 (Mirror: 3'h0)                   
+      R_DMRXRANK_DQS_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)                   
+      R_DMRXRANK_DQS_LAT_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[31:29]=3'h1 (Mirror: 3'h0)                   
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ7_0                            -     @9627                                                         
+      R_DMRANKRXDVS_B1                             uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[3:0]=4'h0                                    
+      R_DMDQMDBI_EYE_SHU_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[6:6]=1'h0                                    
+      R_DMDQMDBI_SHU_B1                            uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[7:7]=1'h0                                    
+      R_DMRXDVS_DQM_FLAGSEL_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[11:8]=4'h0                                   
+      R_DMRXDVS_PBYTE_FLAG_OPT_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[12:12]=1'h0                                  
+      R_DMRXDVS_PBYTE_DQM_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[13:13]=1'h0                                  
+      R_DMRXTRACK_DQM_EN_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[14:14]=1'h0                                  
+      R_DMRODTEN_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)                   
+      R_DMARPI_CG_FB2DLL_DCM_EN_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[16:16]=1'h0                                  
+      R_DMTX_ARPI_CG_DQ_NEW_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[17:17]=1'h0                                  
+      R_DMTX_ARPI_CG_DQS_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[18:18]=1'h0                                  
+      R_DMTX_ARPI_CG_DQM_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[19:19]=1'h0                                  
+      R_LP4Y_SDN_MODE_DQS1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[20:20]=1'h0                                  
+      R_DMRXRANK_DQ_EN_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)                   
+      R_DMRXRANK_DQ_LAT_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[27:25]=3'h2 (Mirror: 3'h0)                   
+      R_DMRXRANK_DQS_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)                   
+      R_DMRXRANK_DQS_LAT_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[31:29]=3'h1 (Mirror: 3'h0)                   
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0         -     @8034                                                         
+      RODTEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0)  
+      RODTEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0)  
+      RODTEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0               
+      RODTEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0               
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+            P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1         -     @8041                                                         
+      RODTEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h4 (Mirror: 3'h0)  
+      RODTEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h4 (Mirror: 3'h0)  
+      RODTEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0)
+      RODTEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0               
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+            P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0         -     @9457                                                         
+      RODTEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0)  
+      RODTEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0)  
+      RODTEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0               
+      RODTEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0               
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+            P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1         -     @9464                                                         
+      RODTEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h4 (Mirror: 3'h0)  
+      RODTEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h4 (Mirror: 3'h0)  
+      RODTEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0)
+      RODTEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0               
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+            P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RX_CG_SET0_0                               ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0                         -     @5361                                                         
+      DLE_LAST_EXTEND3                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[0:0]=1'h0                                
+      READ_START_EXTEND3                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[1:1]=1'h0                                
+      DLE_LAST_EXTEND2                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0)                 
+      READ_START_EXTEND2                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0)                 
+      DLE_LAST_EXTEND1                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0)                 
+      READ_START_EXTEND1                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0)                 
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) |
+            P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) |
+            P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
+            P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_RANK_SEL_STB_0                        ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0                 -     @13227                                                        
+      RANK_SEL_STB_EN                              uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0)          
+      RANK_SEL_STB_EN_B23                          uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0                         
+      RANK_SEL_STB_SERMODE                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0                         
+      RANK_SEL_STB_TRACK                           uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0)          
+      RANK_SEL_RXDLY_TRACK                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0                         
+      RANK_SEL_STB_PHASE_EN                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h0                         
+      RANK_SEL_PHSINCTL                            uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h6 (Mirror: 4'h0)         
+      RANK_SEL_STB_UI_PLUS                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0                       
+      RANK_SEL_STB_MCK_PLUS                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0                       
+      RANK_SEL_STB_UI_MINUS                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h2 (Mirror: 4'h0)        
+      RANK_SEL_STB_MCK_MINUS                       uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0                       
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) |
+            P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) |
+            P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) |
+            P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x6, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) |
+            P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) |
+            P_Fld(0x2, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCAL_0_0                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0                  -     @12876                                                        
+      DQSIENLLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00)         
+      DQSIENLLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0)           
+      DQSIENHLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00)        
+      DQSIENHLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCAL_0_1                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1                  -     @12883                                                        
+      DQSIENLLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00)         
+      DQSIENLLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0)           
+      DQSIENHLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00)        
+      DQSIENHLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_INI_UIPI_0_0                         ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0                  -     @7990                                                         
+      CURR_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00)         
+      CURR_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00)        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x01, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+            P_Fld(0x11, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_INI_UIPI_0_0                         ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0                  -     @9413                                                         
+      CURR_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00)         
+      CURR_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00)        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x01, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+            P_Fld(0x11, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_INI_UIPI_0_1                         ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1                  -     @7995                                                         
+      CURR_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00)         
+      CURR_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00)        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+            P_Fld(0x19, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_INI_UIPI_0_1                         ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1                  -     @9418                                                         
+      CURR_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00)         
+      CURR_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00)        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+            P_Fld(0x19, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_NEXT_INI_UIPI_0_0                    ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0             -     @8000                                                         
+      NEXT_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00)    
+      NEXT_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00)   
+      NEXT_INI_UI_P1_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h15 (Mirror: 8'h00)  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x01, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+            P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x15, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_NEXT_INI_UIPI_0_0                    ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0             -     @9423                                                         
+      NEXT_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00)    
+      NEXT_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00)   
+      NEXT_INI_UI_P1_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h15 (Mirror: 8'h00)  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x01, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+            P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x15, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_NEXT_INI_UIPI_0_1                    ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1             -     @8006                                                         
+      NEXT_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00)    
+      NEXT_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00)   
+      NEXT_INI_UI_P1_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h1d (Mirror: 8'h00)  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+            P_Fld(0x19, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x1d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_NEXT_INI_UIPI_0_1                    ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1             -     @9429                                                         
+      NEXT_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00)    
+      NEXT_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00)   
+      NEXT_INI_UI_P1_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h1d (Mirror: 8'h00)  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+            P_Fld(0x19, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x1d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit:
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter:
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_DQ0_0_0                              ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0                       -     @7970                                                         
+      RG_RX_ARDQS0_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0                               
+      RG_RX_ARDQS0_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0                               
+      SW_ARPI_DQ_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[13:8]=6'h13 (Mirror: 6'h00)             
+      SW_ARPI_DQM_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[21:16]=6'h13 (Mirror: 6'h00)            
+      ARPI_PBYTE_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00                            
+      DA_ARPI_DDR400_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0                             
+      DA_RX_ARDQSIEN_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0                             
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x13, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+            P_Fld(0x13, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_DQ0_0_0                              ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0                       -     @9393                                                         
+      RG_RX_ARDQS1_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0                               
+      RG_RX_ARDQS1_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0                               
+      SW_ARPI_DQ_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[13:8]=6'h16 (Mirror: 6'h00)             
+      SW_ARPI_DQM_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[21:16]=6'h16 (Mirror: 6'h00)            
+      ARPI_PBYTE_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00                            
+      DA_ARPI_DDR400_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0                             
+      DA_RX_ARDQSIEN_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0                             
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x16, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+            P_Fld(0x16, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1));
+    #endif
+
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_DQ0_0_1                              ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1                       -     @7980                                                         
+      RG_RX_ARDQS0_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0                               
+      RG_RX_ARDQS0_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0                               
+      SW_ARPI_DQ_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[13:8]=6'h2b (Mirror: 6'h00)             
+      SW_ARPI_DQM_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[21:16]=6'h2b (Mirror: 6'h00)            
+      ARPI_PBYTE_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[29:24]=6'h01 (Mirror: 6'h00)            
+      DA_ARPI_DDR400_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0                             
+      DA_RX_ARDQSIEN_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0                             
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2b, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+            P_Fld(0x2b, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x01, SHU_R0_B0_DQ0_ARPI_PBYTE_B0));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_DQ0_0_1                              ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1                       -     @9403                                                         
+      RG_RX_ARDQS1_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0                               
+      RG_RX_ARDQS1_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0                               
+      SW_ARPI_DQ_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[13:8]=6'h2b (Mirror: 6'h00)             
+      SW_ARPI_DQM_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[21:16]=6'h2b (Mirror: 6'h00)            
+      ARPI_PBYTE_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[29:24]=6'h01 (Mirror: 6'h00)            
+      DA_ARPI_DDR400_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0                             
+      DA_RX_ARDQSIEN_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0                             
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2b, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+            P_Fld(0x2b, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x01, SHU_R0_B1_DQ0_ARPI_PBYTE_B1));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_DCM_CTRL0_0                                ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0                          -     @5064                                                         
+      DDRPHY_CLK_EN_OPT                            uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0)                  
+      DPHY_CMD_CLKEN_EXTCNT                        uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[10:8]=3'h3                                
+      DDRPHY_CLK_DYN_GATING_SEL                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0)                
+      APHYPI_CKCGL_CNT                             uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[19:16]=4'h2                               
+      APHYPI_CKCGH_CNT                             uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[23:20]=4'h4                               
+      FASTWAKE2                                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[29:29]=1'h0                               
+      FASTWAKE                                     uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[31:31]=1'h1                               
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+            P_Fld(0x3, SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+            P_Fld(0x2, SHU_DCM_CTRL0_APHYPI_CKCGL_CNT) | P_Fld(0x4, SHU_DCM_CTRL0_APHYPI_CKCGH_CNT) |
+            P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_APHY_TX_PICG_CTRL_0                        ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0                  -     @5416                                                         
+      DDRPHY_CLK_EN_COMB_TX_PICG_CNT               uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h3 (Mirror: 4'h0)          
+      DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1             uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h3 (Mirror: 3'h0)          
+      DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0             uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h3 (Mirror: 3'h0)         
+      DPHY_TX_DCM_EXTCNT                           uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[15:12]=4'h2                       
+      DDRPHY_CLK_EN_COMB_TX_OPT                    uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0)        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) |
+            P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) |
+            P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_APHY_TX_PICG_CTRL_0_0                    ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0              -     @4954                                                         
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h4 (Mirror: 3'h0)      
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h3 (Mirror: 3'h0)      
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x4, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+            P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_APHY_TX_PICG_CTRL_0_1                    ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1              -     @4959                                                         
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h4 (Mirror: 3'h0)      
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h3 (Mirror: 3'h0)      
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+            P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_NEW_XRW2W_CTRL_0                           ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0                     -     @5410                                                         
+      TX_PI_UPDCTL_B0                              uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h2 (Mirror: 3'h0)           
+      TX_PI_UPDCTL_B1                              uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h2 (Mirror: 3'h0)           
+      TXPI_UPD_MODE                                uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1)           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) |
+            P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_DQS0_0                               ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0                         -     @5309                                                         
+      TXDLY_DQS0                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[2:0]=3'h4 (Mirror: 3'h1)                 
+      TXDLY_DQS1                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[6:4]=3'h4 (Mirror: 3'h1)                 
+      TXDLY_DQS2                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[10:8]=3'h1                               
+      TXDLY_DQS3                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[14:12]=3'h1                              
+      TXDLY_OEN_DQS0                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[18:16]=3'h4 (Mirror: 3'h1)               
+      TXDLY_OEN_DQS1                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[22:20]=3'h4 (Mirror: 3'h1)               
+      TXDLY_OEN_DQS2                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[26:24]=3'h1                              
+      TXDLY_OEN_DQS3                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[30:28]=3'h1                              
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) |
+            P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) |
+            P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS1));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_DQS1_0                               ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0                         -     @5320                                                         
+      dly_DQS0                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[3:0]=4'h5 (Mirror: 4'h1)                 
+      dly_DQS1                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[7:4]=4'h5 (Mirror: 4'h1)                 
+      dly_DQS2                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[11:8]=4'h1                               
+      dly_DQS3                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[15:12]=4'h1                              
+      dly_oen_DQS0                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[19:16]=4'h2 (Mirror: 4'h1)               
+      dly_oen_DQS1                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[23:20]=4'h2 (Mirror: 4'h1)               
+      dly_oen_DQS2                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[27:24]=4'h1                              
+      dly_oen_DQS3                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[31:28]=4'h1                              
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS0) |
+            P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS0) |
+            P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ0_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0                      -     @4774                                                         
+      TXDLY_DQ0                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[2:0]=3'h4 (Mirror: 3'h1)              
+      TXDLY_DQ1                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[6:4]=3'h4 (Mirror: 3'h1)              
+      TXDLY_DQ2                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1                            
+      TXDLY_DQ3                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1                           
+      TXDLY_OEN_DQ0                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[18:16]=3'h4 (Mirror: 3'h1)            
+      TXDLY_OEN_DQ1                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[22:20]=3'h4 (Mirror: 3'h1)            
+      TXDLY_OEN_DQ2                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1                           
+      TXDLY_OEN_DQ3                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+            P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+            P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ1_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0                      -     @4796                                                         
+      TXDLY_DQM0                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[2:0]=3'h4 (Mirror: 3'h1)              
+      TXDLY_DQM1                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[6:4]=3'h4 (Mirror: 3'h1)              
+      TXDLY_DQM2                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1                            
+      TXDLY_DQM3                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1                           
+      TXDLY_OEN_DQM0                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[18:16]=3'h4 (Mirror: 3'h1)            
+      TXDLY_OEN_DQM1                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[22:20]=3'h4 (Mirror: 3'h1)            
+      TXDLY_OEN_DQM2                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1                           
+      TXDLY_OEN_DQM3                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+            P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+            P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ2_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0                      -     @4818                                                         
+      dly_DQ0                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[3:0]=4'h6 (Mirror: 4'h1)              
+      dly_DQ1                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[7:4]=4'h6 (Mirror: 4'h1)              
+      dly_DQ2                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1                            
+      dly_DQ3                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1                           
+      dly_oen_DQ0                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[19:16]=4'h3 (Mirror: 4'h1)            
+      dly_oen_DQ1                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[23:20]=4'h3 (Mirror: 4'h1)            
+      dly_oen_DQ2                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1                           
+      dly_oen_DQ3                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ0) |
+            P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+            P_Fld(0x3, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ3_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0                      -     @4840                                                         
+      dly_DQM0                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[3:0]=4'h6 (Mirror: 4'h1)              
+      dly_DQM1                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[7:4]=4'h6 (Mirror: 4'h1)              
+      dly_DQM2                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1                            
+      dly_DQM3                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1                           
+      dly_oen_DQM0                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[19:16]=4'h3 (Mirror: 4'h1)            
+      dly_oen_DQM1                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[23:20]=4'h3 (Mirror: 4'h1)            
+      dly_oen_DQM2                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1                           
+      dly_oen_DQM3                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM0) |
+            P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+            P_Fld(0x3, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ0_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1                      -     @4785                                                         
+      TXDLY_DQ0                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[2:0]=3'h4 (Mirror: 3'h1)              
+      TXDLY_DQ1                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[6:4]=3'h4 (Mirror: 3'h1)              
+      TXDLY_DQ2                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1                            
+      TXDLY_DQ3                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1                           
+      TXDLY_OEN_DQ0                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[18:16]=3'h4 (Mirror: 3'h1)            
+      TXDLY_OEN_DQ1                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[22:20]=3'h4 (Mirror: 3'h1)            
+      TXDLY_OEN_DQ2                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1                           
+      TXDLY_OEN_DQ3                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+            P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+            P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ1_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1                      -     @4807                                                         
+      TXDLY_DQM0                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[2:0]=3'h4 (Mirror: 3'h1)              
+      TXDLY_DQM1                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[6:4]=3'h4 (Mirror: 3'h1)              
+      TXDLY_DQM2                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1                            
+      TXDLY_DQM3                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1                           
+      TXDLY_OEN_DQM0                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[18:16]=3'h4 (Mirror: 3'h1)            
+      TXDLY_OEN_DQM1                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[22:20]=3'h4 (Mirror: 3'h1)            
+      TXDLY_OEN_DQM2                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1                           
+      TXDLY_OEN_DQM3                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+            P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+            P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ2_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1                      -     @4829                                                         
+      dly_DQ0                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[3:0]=4'h7 (Mirror: 4'h1)              
+      dly_DQ1                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[7:4]=4'h7 (Mirror: 4'h1)              
+      dly_DQ2                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1                            
+      dly_DQ3                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1                           
+      dly_oen_DQ0                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[19:16]=4'h4 (Mirror: 4'h1)            
+      dly_oen_DQ1                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[23:20]=4'h4 (Mirror: 4'h1)            
+      dly_oen_DQ2                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1                           
+      dly_oen_DQ3                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x7, SHURK_SELPH_DQ2_DLY_DQ0) |
+            P_Fld(0x7, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+            P_Fld(0x4, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ3_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1                      -     @4851                                                         
+      dly_DQM0                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[3:0]=4'h7 (Mirror: 4'h1)              
+      dly_DQM1                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[7:4]=4'h7 (Mirror: 4'h1)              
+      dly_DQM2                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1                            
+      dly_DQM3                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1                           
+      dly_oen_DQM0                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[19:16]=4'h4 (Mirror: 4'h1)            
+      dly_oen_DQM1                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[23:20]=4'h4 (Mirror: 4'h1)            
+      dly_oen_DQM2                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1                           
+      dly_oen_DQM3                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x7, SHURK_SELPH_DQ3_DLY_DQM0) |
+            P_Fld(0x7, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+            P_Fld(0x4, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL1_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0                    -     @4862                                                         
+      BOOT_ORIG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h013 (Mirror: 11'h000)     
+      BOOT_ORIG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h016 (Mirror: 11'h000)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x013, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+            P_Fld(0x016, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL2_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0                    -     @4872                                                         
+      BOOT_TARG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h013 (Mirror: 11'h000)     
+      BOOT_TARG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h016 (Mirror: 11'h000)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x013, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+            P_Fld(0x016, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL5_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0                    -     @4910                                                         
+      BOOT_TARG_UI_RK0_DQM0                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h013 (Mirror: 11'h000)     
+      BOOT_TARG_UI_RK0_DQM1                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h016 (Mirror: 11'h000)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x013, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+            P_Fld(0x016, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL1_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1                    -     @4867                                                         
+      BOOT_ORIG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h02b (Mirror: 11'h000)     
+      BOOT_ORIG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h02b (Mirror: 11'h000)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02b, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+            P_Fld(0x02b, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL2_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1                    -     @4877                                                         
+      BOOT_TARG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h02b (Mirror: 11'h000)     
+      BOOT_TARG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h02b (Mirror: 11'h000)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02b, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+            P_Fld(0x02b, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL5_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1                    -     @4915                                                         
+      BOOT_TARG_UI_RK0_DQM0                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h02b (Mirror: 11'h000)     
+      BOOT_TARG_UI_RK0_DQM1                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h02b (Mirror: 11'h000)    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02b, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+            P_Fld(0x02b, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_PI_0_0                                   ral_reg_DRAMC_blk_SHURK_PI_0_0                             -     @4920                                                         
+      RK0_ARPI_DQ_B1                               uvm_reg_field                                              ...    RW SHURK_PI_0_0[5:0]=6'h16 (Mirror: 6'h00)                   
+      RK0_ARPI_DQ_B0                               uvm_reg_field                                              ...    RW SHURK_PI_0_0[13:8]=6'h13 (Mirror: 6'h00)                  
+      RK0_ARPI_DQM_B1                              uvm_reg_field                                              ...    RW SHURK_PI_0_0[21:16]=6'h16 (Mirror: 6'h00)                 
+      RK0_ARPI_DQM_B0                              uvm_reg_field                                              ...    RW SHURK_PI_0_0[29:24]=6'h13 (Mirror: 6'h00)                 
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x16, SHURK_PI_RK0_ARPI_DQ_B1) |
+            P_Fld(0x13, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x16, SHURK_PI_RK0_ARPI_DQM_B1) |
+            P_Fld(0x13, SHURK_PI_RK0_ARPI_DQM_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_PI_0_1                                   ral_reg_DRAMC_blk_SHURK_PI_0_1                             -     @4927                                                         
+      RK0_ARPI_DQ_B1                               uvm_reg_field                                              ...    RW SHURK_PI_0_1[5:0]=6'h2b (Mirror: 6'h00)                   
+      RK0_ARPI_DQ_B0                               uvm_reg_field                                              ...    RW SHURK_PI_0_1[13:8]=6'h2b (Mirror: 6'h00)                  
+      RK0_ARPI_DQM_B1                              uvm_reg_field                                              ...    RW SHURK_PI_0_1[21:16]=6'h2b (Mirror: 6'h00)                 
+      RK0_ARPI_DQM_B0                              uvm_reg_field                                              ...    RW SHURK_PI_0_1[29:24]=6'h2b (Mirror: 6'h00)                 
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2b, SHURK_PI_RK0_ARPI_DQ_B1) |
+            P_Fld(0x2b, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x2b, SHURK_PI_RK0_ARPI_DQM_B1) |
+            P_Fld(0x2b, SHURK_PI_RK0_ARPI_DQM_B0));
+
+    #if !CODE_SIZE_REDUCE
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0                    -     @7816                                                         
+      TX_ARDQ0_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h10 (Mirror: 8'h00)           
+      TX_ARDQ1_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h10 (Mirror: 8'h00)          
+      TX_ARDQ2_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h10 (Mirror: 8'h00)         
+      TX_ARDQ3_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h10 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+            P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+            P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0                    -     @7830                                                         
+      TX_ARDQ4_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h10 (Mirror: 8'h00)           
+      TX_ARDQ5_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h10 (Mirror: 8'h00)          
+      TX_ARDQ6_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h10 (Mirror: 8'h00)         
+      TX_ARDQ7_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h10 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+            P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+            P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0                    -     @7858                                                         
+      TX_ARDQM0_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h10 (Mirror: 8'h00)           
+      TX_ARWCK_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00                         
+      TX_ARWCKB_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x10, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+            P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0                    -     @9239                                                         
+      TX_ARDQ0_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h04 (Mirror: 8'h00)           
+      TX_ARDQ1_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h04 (Mirror: 8'h00)          
+      TX_ARDQ2_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h04 (Mirror: 8'h00)         
+      TX_ARDQ3_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h04 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+            P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+            P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0                    -     @9253                                                         
+      TX_ARDQ4_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h04 (Mirror: 8'h00)           
+      TX_ARDQ5_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h04 (Mirror: 8'h00)          
+      TX_ARDQ6_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h04 (Mirror: 8'h00)         
+      TX_ARDQ7_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h04 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+            P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+            P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0                    -     @9281                                                         
+      TX_ARDQM0_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h04 (Mirror: 8'h00)           
+      TX_ARWCK_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00                         
+      TX_ARWCKB_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x04, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+            P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1                    -     @7823                                                         
+      TX_ARDQ0_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h08 (Mirror: 8'h00)           
+      TX_ARDQ1_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h08 (Mirror: 8'h00)          
+      TX_ARDQ2_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h08 (Mirror: 8'h00)         
+      TX_ARDQ3_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h08 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+            P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+            P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1                    -     @7837                                                         
+      TX_ARDQ4_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h08 (Mirror: 8'h00)           
+      TX_ARDQ5_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h08 (Mirror: 8'h00)          
+      TX_ARDQ6_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h08 (Mirror: 8'h00)         
+      TX_ARDQ7_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h08 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+            P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+            P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1                    -     @7864                                                         
+      TX_ARDQM0_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h08 (Mirror: 8'h00)           
+      TX_ARWCK_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00                         
+      TX_ARWCKB_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+            P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1                    -     @9246                                                         
+      TX_ARDQ0_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h08 (Mirror: 8'h00)           
+      TX_ARDQ1_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h08 (Mirror: 8'h00)          
+      TX_ARDQ2_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h08 (Mirror: 8'h00)         
+      TX_ARDQ3_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h08 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+            P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+            P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1                    -     @9260                                                         
+      TX_ARDQ4_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h08 (Mirror: 8'h00)           
+      TX_ARDQ5_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h08 (Mirror: 8'h00)          
+      TX_ARDQ6_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h08 (Mirror: 8'h00)         
+      TX_ARDQ7_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h08 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+            P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+            P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1                    -     @9287                                                         
+      TX_ARDQM0_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h08 (Mirror: 8'h00)           
+      TX_ARWCK_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00                         
+      TX_ARWCKB_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+            P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_TX_RANKCTL_0                               ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0                         -     @5384                                                         
+      TXRANKINCTL_TXDLY                            uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[3:0]=4'h1 (Mirror: 4'h0)                 
+      TXRANKINCTL                                  uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[7:4]=4'h1 (Mirror: 4'h0)                 
+      TXRANKINCTL_ROOT                             uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[11:8]=4'h0                               
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) |
+            P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT));
+    #endif
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit:
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter:
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_AC_DERATING0_0                             ral_reg_DRAMC_blk_SHU_AC_DERATING0_0                       -     @5271                                                         
+      ACDERATEEN                                   uvm_reg_field                                              ...    RW SHU_AC_DERATING0_0[0:0]=1'h0                              
+      TRRD_DERATE                                  uvm_reg_field                                              ...    RW SHU_AC_DERATING0_0[18:16]=3'h5 (Mirror: 3'h0)             
+      TRCD_DERATE                                  uvm_reg_field                                              ...    RW SHU_AC_DERATING0_0[27:24]=4'hb (Mirror: 4'h0)             
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !(CODE_SIZE_REDUCE && AC_TIMING_DERATE_ENABLE)
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING0, P_Fld(0x0, SHU_AC_DERATING0_ACDERATEEN) |
+            P_Fld(0x5, SHU_AC_DERATING0_TRRD_DERATE) | P_Fld(0xb, SHU_AC_DERATING0_TRCD_DERATE));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_AC_DERATING1_0                             ral_reg_DRAMC_blk_SHU_AC_DERATING1_0                       -     @5277                                                         
+      TRPAB_DERATE                                 uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[3:0]=4'hb (Mirror: 4'h0)               
+      TRP_DERATE                                   uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[11:8]=4'h9 (Mirror: 4'h0)              
+      TRAS_DERATE                                  uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[21:16]=6'h0f (Mirror: 6'h00)           
+      TRC_DERATE                                   uvm_reg_field                                              ...    RW SHU_AC_DERATING1_0[28:24]=5'h00                           
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING1, P_Fld(0xb, SHU_AC_DERATING1_TRPAB_DERATE) |
+            P_Fld(0x9, SHU_AC_DERATING1_TRP_DERATE) | P_Fld(0x0f, SHU_AC_DERATING1_TRAS_DERATE) |
+            P_Fld(0x00, SHU_AC_DERATING1_TRC_DERATE));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_AC_DERATING_05T_0                          ral_reg_DRAMC_blk_SHU_AC_DERATING_05T_0                    -     @5284                                                         
+      TRC_05T_DERATE                               uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[0:0]=1'h0                           
+      TRCD_05T_DERATE                              uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[6:6]=1'h0                           
+      TRP_05T_DERATE                               uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[7:7]=1'h1 (Mirror: 1'h0)            
+      TRPAB_05T_DERATE                             uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[8:8]=1'h0                           
+      TRAS_05T_DERATE                              uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[9:9]=1'h0                           
+      TRRD_05T_DERATE                              uvm_reg_field                                              ...    RW SHU_AC_DERATING_05T_0[12:12]=1'h1 (Mirror: 1'h0)          
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING_05T, P_Fld(0x0, SHU_AC_DERATING_05T_TRC_05T_DERATE) |
+            P_Fld(0x0, SHU_AC_DERATING_05T_TRCD_05T_DERATE) | P_Fld(0x1, SHU_AC_DERATING_05T_TRP_05T_DERATE) |
+            P_Fld(0x0, SHU_AC_DERATING_05T_TRPAB_05T_DERATE) | P_Fld(0x0, SHU_AC_DERATING_05T_TRAS_05T_DERATE) |
+            P_Fld(0x1, SHU_AC_DERATING_05T_TRRD_05T_DERATE));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SREF_CTRL_0                                ral_reg_DRAMC_blk_SHU_SREF_CTRL_0                          -     @5055                                                         
+      CKEHCMD                                      uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[5:4]=2'h3                                 
+      SREF_CK_DLY                                  uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0)                
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) |
+            P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_HMR4_DVFS_CTRL0_0                          ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0                    -     @5074                                                         
+      FSPCHG_PRDCNT                                uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h86 (Mirror: 8'h00)         
+      REFRCNT                                      uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000                      
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x86, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+            P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_AC_TIME_05T_0                              ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0                        -     @5237                                                         
+      TRC_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[0:0]=1'h0                               
+      TRFCPB_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[1:1]=1'h1 (Mirror: 1'h0)                
+      TRFC_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[2:2]=1'h0                               
+      TPBR2PBR_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[3:3]=1'h0                               
+      TXP_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[4:4]=1'h0                               
+      TRTP_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[5:5]=1'h1 (Mirror: 1'h0)                
+      TRCD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[6:6]=1'h0                               
+      TRP_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[7:7]=1'h1 (Mirror: 1'h0)                
+      TRPAB_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[8:8]=1'h0                               
+      TRAS_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[9:9]=1'h0                               
+      TWR_M05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[10:10]=1'h0                             
+      TRRD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[12:12]=1'h0                             
+      TFAW_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[13:13]=1'h0                             
+      TCKEPRD_05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[14:14]=1'h0                             
+      TR2PD_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[15:15]=1'h1 (Mirror: 1'h0)              
+      TWTPD_M05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[16:16]=1'h0                             
+      TMRRI_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[17:17]=1'h0                             
+      TMRWCKEL_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[18:18]=1'h1 (Mirror: 1'h0)              
+      BGTRRD_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[19:19]=1'h0                             
+      BGTCCD_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[20:20]=1'h0                             
+      BGTWTR_M05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[21:21]=1'h0                             
+      TR2W_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[22:22]=1'h0                             
+      TWTR_M05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[23:23]=1'h1 (Mirror: 1'h0)              
+      XRTR2W_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[24:24]=1'h0                             
+      TMRD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[25:25]=1'h0                             
+      TMRW_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[26:26]=1'h1 (Mirror: 1'h0)              
+      TMRR2MRW_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[27:27]=1'h0                             
+      TW2MRW_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[28:28]=1'h0                             
+      TR2MRW_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[29:29]=1'h0                             
+      TPBR2ACT_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[30:30]=1'h0                             
+      XRTW2R_M05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[31:31]=1'h0                             
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T,
+            P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTWTR_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TXP_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRCD_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TWR_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TR2PD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TWTPD_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TMRRI_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRWCKEL_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTR_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TMRD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRW_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TMRR2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T));
+    /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM_XRT_0                                ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0                          -     @5230                                                         
+      XRTR2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[4:0]=5'h03 (Mirror: 5'h01)                
+      XRTR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[13:8]=6'h08 (Mirror: 6'h01)               
+      XRTW2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[19:16]=4'h1                               
+      XRTW2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[28:24]=5'h05 (Mirror: 5'h01)              
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x03, SHU_ACTIM_XRT_XRTR2R) |
+            P_Fld(0x08, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x1, SHU_ACTIM_XRT_XRTW2R) |
+            P_Fld(0x05, SHU_ACTIM_XRT_XRTW2W));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM0_0                                   ral_reg_DRAMC_blk_SHU_ACTIM0_0                             -     @5176                                                         
+      TWTR                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[5:0]=6'h0a (Mirror: 6'h01)                   
+      TWR                                          uvm_reg_field                                              ...    RW SHU_ACTIM0_0[15:8]=8'h0f (Mirror: 8'h06)                  
+      TRRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[18:16]=3'h3 (Mirror: 3'h0)                   
+      TRCD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[27:24]=4'ha (Mirror: 4'h2)                   
+      CKELCKCNT                                    uvm_reg_field                                              ...    RW SHU_ACTIM0_0[31:28]=4'h3 (Mirror: 4'h0)                   
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x0a, SHU_ACTIM0_TWTR) |
+            P_Fld(0x0f, SHU_ACTIM0_TWR) | P_Fld(0x3, SHU_ACTIM0_TRRD) |
+            P_Fld(0xa, SHU_ACTIM0_TRCD) | P_Fld(0x3, SHU_ACTIM0_CKELCKCNT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM1_0                                   ral_reg_DRAMC_blk_SHU_ACTIM1_0                             -     @5184                                                         
+      TRPAB                                        uvm_reg_field                                              ...    RW SHU_ACTIM1_0[3:0]=4'ha                                    
+      TMRWCKEL                                     uvm_reg_field                                              ...    RW SHU_ACTIM1_0[7:4]=4'h8                                    
+      TRP                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[11:8]=4'h8 (Mirror: 4'h2)                    
+      TRAS                                         uvm_reg_field                                              ...    RW SHU_ACTIM1_0[21:16]=6'h0e (Mirror: 6'h04)                 
+      TRC                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[28:24]=5'h00 (Mirror: 5'h05)                 
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0xa, SHU_ACTIM1_TRPAB) |
+            P_Fld(0x8, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x8, SHU_ACTIM1_TRP) |
+            P_Fld(0x0e, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM2_0                                   ral_reg_DRAMC_blk_SHU_ACTIM2_0                             -     @5192                                                         
+      TXP                                          uvm_reg_field                                              ...    RW SHU_ACTIM2_0[3:0]=4'h1 (Mirror: 4'h0)                     
+      TMRRI                                        uvm_reg_field                                              ...    RW SHU_ACTIM2_0[8:4]=5'h0e                                   
+      TRTP                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[14:12]=3'h2 (Mirror: 3'h0)                   
+      TR2W                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[21:16]=6'h09 (Mirror: 6'h00)                 
+      TFAW                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[28:24]=5'h08 (Mirror: 5'h05)                 
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x1, SHU_ACTIM2_TXP) |
+            P_Fld(0x0e, SHU_ACTIM2_TMRRI) | P_Fld(0x2, SHU_ACTIM2_TRTP) |
+            P_Fld(0x09, SHU_ACTIM2_TR2W) | P_Fld(0x08, SHU_ACTIM2_TFAW));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM3_0                                   ral_reg_DRAMC_blk_SHU_ACTIM3_0                             -     @5200                                                         
+      TRFCPB                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[7:0]=8'h59 (Mirror: 8'h00)                   
+      MANTMRR                                      uvm_reg_field                                              ...    RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0)                    
+      TR2MRR                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0)                   
+      TRFC                                         uvm_reg_field                                              ...    RW SHU_ACTIM3_0[23:16]=8'hbf (Mirror: 8'h00)                 
+      TWTR_L                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[29:24]=6'h00                                 
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x59, SHU_ACTIM3_TRFCPB) |
+            P_Fld(0x4, SHU_ACTIM3_TR2MRR) | P_Fld(0xbf, SHU_ACTIM3_TRFC));
+    #endif
+		vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x4, SHU_ACTIM3_MANTMRR) |
+            P_Fld(0x00, SHU_ACTIM3_TWTR_L));
+
+    #if !CODE_SIZE_REDUCE
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM4_0                                   ral_reg_DRAMC_blk_SHU_ACTIM4_0                             -     @5208                                                         
+      TXREFCNT                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[9:0]=10'h0cf (Mirror: 10'h028)               
+      TMRR2MRW                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[15:10]=6'h0f (Mirror: 6'h00)                 
+      TMRR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM4_0[21:16]=6'h0b (Mirror: 6'h00)                 
+      TZQCS                                        uvm_reg_field                                              ...    RW SHU_ACTIM4_0[31:24]=8'h2e (Mirror: 8'h00)                 
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x0cf, SHU_ACTIM4_TXREFCNT) |
+            P_Fld(0x0f, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0b, SHU_ACTIM4_TMRR2W) |
+            P_Fld(0x2e, SHU_ACTIM4_TZQCS));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM5_0                                   ral_reg_DRAMC_blk_SHU_ACTIM5_0                             -     @5215                                                         
+      TR2PD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[6:0]=7'h0f (Mirror: 7'h00)                   
+      TWTPD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[14:8]=7'h12 (Mirror: 7'h00)                  
+      TPBR2PBR                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[23:16]=8'h29 (Mirror: 8'h00)                 
+      TPBR2ACT                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[29:28]=2'h0                                  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x0f, SHU_ACTIM5_TR2PD) |
+            P_Fld(0x12, SHU_ACTIM5_TWTPD) | P_Fld(0x29, SHU_ACTIM5_TPBR2PBR) |
+            P_Fld(0x0, SHU_ACTIM5_TPBR2ACT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM6_0                                   ral_reg_DRAMC_blk_SHU_ACTIM6_0                             -     @5222                                                         
+      TZQLAT2                                      uvm_reg_field                                              ...    RW SHU_ACTIM6_0[4:0]=5'h10 (Mirror: 5'h1f)                   
+      TMRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[11:8]=4'h8 (Mirror: 4'h0)                    
+      TMRW                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0)                   
+      TW2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[25:20]=6'h0b (Mirror: 6'h00)                 
+      TR2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[31:26]=6'h12 (Mirror: 6'h13)                 
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x10, SHU_ACTIM6_TZQLAT2) |
+            P_Fld(0x8, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) |
+            P_Fld(0x0b, SHU_ACTIM6_TW2MRW) | P_Fld(0x12, SHU_ACTIM6_TR2MRW));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_CKECTRL_0                                  ral_reg_DRAMC_blk_SHU_CKECTRL_0                            -     @5300                                                         
+      TPDE_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0)                    
+      TPDX_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[1:1]=1'h0                                   
+      TPDE                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[14:12]=3'h1                                 
+      TPDX                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[18:16]=3'h1                                 
+      TCKEPRD                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[22:20]=3'h3 (Mirror: 3'h2)                  
+      TCKESRX                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0)                  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) |
+            P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) |
+            P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x3, SHU_CKECTRL_TCKEPRD));
+    #endif
+
+    vIO32WriteFldAlign(DRAMC_REG_SHU_CKECTRL, 0x3, SHU_CKECTRL_TCKESRX);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_0                                     ral_reg_DRAMC_blk_SHU_MISC_0                               -     @5404                                                         
+      REQQUE_MAXCNT                                uvm_reg_field                                              ...    RW SHU_MISC_0[3:0]=4'h2                                      
+      DCMDLYREF                                    uvm_reg_field                                              ...    RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4)                     
+      DAREFEN                                      uvm_reg_field                                              ...    RW SHU_MISC_0[30:30]=1'h0                                    
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x7, SHU_MISC_DCMDLYREF) |
+    P_Fld(0x0, SHU_MISC_DAREFEN));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldAlign(DRAMC_REG_SHU_MISC, 0x2, SHU_MISC_REQQUE_MAXCNT);
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter.
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit.
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ8_0                            -     @8224                                                         
+      R_DMRXDVS_UPD_FORCE_CYC_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000)            
+      R_DMRXDVS_UPD_FORCE_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[15:15]=1'h0                                  
+      R_DMRANK_RXDLY_PIPE_CG_IG_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[19:19]=1'h0                                  
+      R_RMRODTEN_CG_IG_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[20:20]=1'h0                                  
+      R_RMRX_TOPHY_CG_IG_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)                   
+      R_DMRXDVS_RDSEL_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[22:22]=1'h0                                  
+      R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0            uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[23:23]=1'h0                                  
+      R_DMRXDLY_CG_IG_B0                           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)                   
+      R_DMDQSIEN_FLAG_SYNC_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[26:26]=1'h0                                  
+      R_DMDQSIEN_FLAG_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[27:27]=1'h0                                  
+      R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0               uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[28:28]=1'h0                                  
+      R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[29:29]=1'h0                                  
+      R_DMRANK_PIPE_CG_IG_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[30:30]=1'h0                                  
+      R_DMRANK_CHG_PIPE_CG_IG_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[31:31]=1'h0                                  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+            P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+    #endif
+
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ8_0                            -     @9647                                                         
+      R_DMRXDVS_UPD_FORCE_CYC_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000)            
+      R_DMRXDVS_UPD_FORCE_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[15:15]=1'h0                                  
+      R_DMRANK_RXDLY_PIPE_CG_IG_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[19:19]=1'h0                                  
+      R_RMRODTEN_CG_IG_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[20:20]=1'h0                                  
+      R_RMRX_TOPHY_CG_IG_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)                   
+      R_DMRXDVS_RDSEL_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[22:22]=1'h0                                  
+      R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1            uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[23:23]=1'h0                                  
+      R_DMRXDLY_CG_IG_B1                           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)                   
+      R_DMDQSIEN_FLAG_SYNC_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[26:26]=1'h0                                  
+      R_DMDQSIEN_FLAG_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[27:27]=1'h0                                  
+      R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1               uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[28:28]=1'h0                                  
+      R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[29:29]=1'h0                                  
+      R_DMRANK_PIPE_CG_IG_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[30:30]=1'h0                                  
+      R_DMRANK_CHG_PIPE_CG_IG_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[31:31]=1'h0                                  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+            P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+    #endif
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ5_0                            -     @8124                                                         
+      RG_RX_ARDQ_VREF_SEL_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[5:0]=6'h0e                                   
+      RG_RX_ARDQ_VREF_BYPASS_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[6:6]=1'h0                                    
+      RG_ARPI_FB_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[13:8]=6'h00                                  
+      RG_RX_ARDQS0_DQSIEN_DLY_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[18:16]=3'h0                                  
+      RG_RX_ARDQS_DQSIEN_RB_DLY_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[19:19]=1'h0                                  
+      RG_RX_ARDQS0_DVS_DLY_B0                      uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[23:20]=4'h3 (Mirror: 4'h0)                   
+      RG_RX_ARDQ_FIFO_DQSI_DLY_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[31:29]=3'h0                                  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) |
+            P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) |
+            P_Fld(0x3, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ5_0                            -     @9547                                                         
+      RG_RX_ARDQ_VREF_SEL_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[5:0]=6'h0e                                   
+      RG_RX_ARDQ_VREF_BYPASS_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[6:6]=1'h0                                    
+      RG_ARPI_FB_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[13:8]=6'h00                                  
+      RG_RX_ARDQS0_DQSIEN_DLY_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[18:16]=3'h0                                  
+      RG_RX_ARDQS_DQSIEN_RB_DLY_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[19:19]=1'h0                                  
+      RG_RX_ARDQS0_DVS_DLY_B1                      uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[23:20]=4'h3 (Mirror: 4'h0)                   
+      RG_RX_ARDQ_FIFO_DQSI_DLY_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[31:29]=3'h0                                  
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) |
+            P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) |
+            P_Fld(0x3, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0                    -     @7878                                                         
+      RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h54 (Mirror: 8'h00)           
+      RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h54 (Mirror: 8'h00)          
+      RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h54 (Mirror: 8'h00)         
+      RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h54 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x54, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) |
+            P_Fld(0x54, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+	
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x54, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+            P_Fld(0x54, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0                    -     @7892                                                         
+      RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h54 (Mirror: 8'h00)           
+      RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h54 (Mirror: 8'h00)          
+      RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h54 (Mirror: 8'h00)         
+      RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h54 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x54, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+            P_Fld(0x54, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+            P_Fld(0x54, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0                    -     @7906                                                         
+      RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h54 (Mirror: 8'h00)           
+      RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h54 (Mirror: 8'h00)          
+      RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h54 (Mirror: 8'h00)         
+      RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h54 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x54, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+            P_Fld(0x54, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+            P_Fld(0x54, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0                    -     @7920                                                         
+      RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h54 (Mirror: 8'h00)           
+      RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h54 (Mirror: 8'h00)          
+      RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h54 (Mirror: 8'h00)         
+      RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h54 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x54, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+            P_Fld(0x54, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+            P_Fld(0x54, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0                    -     @7934                                                         
+      RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h54 (Mirror: 8'h00)           
+      RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h54 (Mirror: 8'h00)          
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x54, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+            P_Fld(0x54, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0                    -     @7944                                                         
+      RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h04a (Mirror: 9'h000)         
+      RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h04a (Mirror: 9'h000)       
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x04a, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+            P_Fld(0x04a, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1                    -     @7885                                                         
+      RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h46 (Mirror: 8'h00)           
+      RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h46 (Mirror: 8'h00)          
+      RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h46 (Mirror: 8'h00)         
+      RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h46 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) |
+            P_Fld(0x46, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+
+	#if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+            P_Fld(0x46, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1                    -     @7899                                                         
+      RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h46 (Mirror: 8'h00)           
+      RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h46 (Mirror: 8'h00)          
+      RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h46 (Mirror: 8'h00)         
+      RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h46 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+            P_Fld(0x46, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+            P_Fld(0x46, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1                    -     @7913                                                         
+      RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h46 (Mirror: 8'h00)           
+      RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h46 (Mirror: 8'h00)          
+      RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h46 (Mirror: 8'h00)         
+      RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h46 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+            P_Fld(0x46, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+            P_Fld(0x46, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1                    -     @7927                                                         
+      RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h46 (Mirror: 8'h00)           
+      RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h46 (Mirror: 8'h00)          
+      RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h46 (Mirror: 8'h00)         
+      RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h46 (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+            P_Fld(0x46, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+            P_Fld(0x46, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1                    -     @7939                                                         
+      RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h46 (Mirror: 8'h00)           
+      RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h46 (Mirror: 8'h00)          
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+            P_Fld(0x46, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1                    -     @7949                                                         
+      RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h038 (Mirror: 9'h000)         
+      RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h038 (Mirror: 9'h000)       
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x038, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+            P_Fld(0x038, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0                    -     @9301                                                         
+      RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'hcd (Mirror: 8'h00)           
+      RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'hcd (Mirror: 8'h00)          
+      RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'hcd (Mirror: 8'h00)         
+      RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'hcd (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0xcd, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) |
+            P_Fld(0xcd, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0xcd, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+            P_Fld(0xcd, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0                    -     @9315                                                         
+      RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'hcd (Mirror: 8'h00)           
+      RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'hcd (Mirror: 8'h00)          
+      RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'hcd (Mirror: 8'h00)         
+      RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'hcd (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0xcd, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+            P_Fld(0xcd, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+            P_Fld(0xcd, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0                    -     @9329                                                         
+      RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'hcd (Mirror: 8'h00)           
+      RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'hcd (Mirror: 8'h00)          
+      RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'hcd (Mirror: 8'h00)         
+      RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'hcd (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0xcd, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+            P_Fld(0xcd, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+            P_Fld(0xcd, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0                    -     @9343                                                         
+      RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'hcd (Mirror: 8'h00)           
+      RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'hcd (Mirror: 8'h00)          
+      RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'hcd (Mirror: 8'h00)         
+      RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'hcd (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0xcd, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+            P_Fld(0xcd, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+            P_Fld(0xcd, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0                    -     @9357                                                         
+      RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'hcd (Mirror: 8'h00)           
+      RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'hcd (Mirror: 8'h00)          
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0xcd, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+            P_Fld(0xcd, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+    #endif
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0                    -     @9367                                                         
+      RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h0bd (Mirror: 9'h000)         
+      RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h0bd (Mirror: 9'h000)       
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x0bd, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+            P_Fld(0x0bd, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1                    -     @9308                                                         
+      RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'hfe (Mirror: 8'h00)           
+      RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'hfe (Mirror: 8'h00)          
+      RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'hfe (Mirror: 8'h00)         
+      RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'hfe (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) |
+            P_Fld(0xfe, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+            P_Fld(0xfe, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1                    -     @9322                                                         
+      RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'hfe (Mirror: 8'h00)           
+      RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'hfe (Mirror: 8'h00)          
+      RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'hfe (Mirror: 8'h00)         
+      RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'hfe (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+            P_Fld(0xfe, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+            P_Fld(0xfe, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1                    -     @9336                                                         
+      RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'hfe (Mirror: 8'h00)           
+      RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'hfe (Mirror: 8'h00)          
+      RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'hfe (Mirror: 8'h00)         
+      RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'hfe (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+            P_Fld(0xfe, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+            P_Fld(0xfe, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1                    -     @9350                                                         
+      RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'hfe (Mirror: 8'h00)           
+      RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'hfe (Mirror: 8'h00)          
+      RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'hfe (Mirror: 8'h00)         
+      RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'hfe (Mirror: 8'h00)         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+            P_Fld(0xfe, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+            P_Fld(0xfe, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1                    -     @9362                                                         
+      RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'hfe (Mirror: 8'h00)           
+      RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'hfe (Mirror: 8'h00)          
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if !CODE_SIZE_REDUCE
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+            P_Fld(0xfe, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1                    -     @9372                                                         
+      RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h0f4 (Mirror: 9'h000)         
+      RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h0f4 (Mirror: 9'h000)       
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0f4, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+            P_Fld(0x0f4, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ9                                         ral_reg_DDRPHY_blk_B0_DQ9                                  -     @7772                                                         
+      RG_RX_ARDQ_STBEN_RESETB_B0                   uvm_reg_field                                              ...    RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0)                           
+      RG_RX_ARDQS0_STBEN_RESETB_B0                 uvm_reg_field                                              ...    RW B0_DQ9[4:4]=1'h0                                          
+      RG_RX_ARDQS0_DQSIENMODE_B0                   uvm_reg_field                                              ...    RW B0_DQ9[5:5]=1'h0                                          
+      R_DMRXDVS_R_F_DLY_RK_OPT_B0                  uvm_reg_field                                              ...    RW B0_DQ9[6:6]=1'h1                                          
+      R_DMRXFIFO_STBENCMP_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ9[7:7]=1'h0                                          
+      R_IN_GATE_EN_LOW_OPT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[15:8]=8'h00                                        
+      R_DMDQSIEN_VALID_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[18:16]=3'h0                                        
+      R_DMDQSIEN_RDSEL_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[22:20]=3'h0                                        
+      R_DMRXDVS_VALID_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[26:24]=3'h0                                        
+      R_DMRXDVS_RDSEL_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[30:28]=3'h0                                        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
+            P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
+            P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
+            P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
+            P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
+            P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ9                                         ral_reg_DDRPHY_blk_B1_DQ9                                  -     @9195                                                         
+      RG_RX_ARDQ_STBEN_RESETB_B1                   uvm_reg_field                                              ...    RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0)                           
+      RG_RX_ARDQS0_STBEN_RESETB_B1                 uvm_reg_field                                              ...    RW B1_DQ9[4:4]=1'h0                                          
+      RG_RX_ARDQS0_DQSIENMODE_B1                   uvm_reg_field                                              ...    RW B1_DQ9[5:5]=1'h0                                          
+      R_DMRXDVS_R_F_DLY_RK_OPT_B1                  uvm_reg_field                                              ...    RW B1_DQ9[6:6]=1'h1                                          
+      R_DMRXFIFO_STBENCMP_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ9[7:7]=1'h0                                          
+      R_IN_GATE_EN_LOW_OPT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[15:8]=8'h00                                        
+      R_DMDQSIEN_VALID_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[18:16]=3'h0                                        
+      R_DMDQSIEN_RDSEL_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[22:20]=3'h0                                        
+      R_DMRXDVS_VALID_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[26:24]=3'h0                                        
+      R_DMRXDVS_RDSEL_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[30:28]=3'h0                                        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
+            P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
+            P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
+            P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
+            P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
+            P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ4                                         ral_reg_DDRPHY_blk_B0_DQ4                                  -     @7701                                                         
+      RG_RX_ARDQS_EYE_R_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[6:0]=7'h5a (Mirror: 7'h00)                         
+      RG_RX_ARDQS_EYE_F_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[14:8]=7'h5a (Mirror: 7'h00)                        
+      RG_RX_ARDQ_EYE_R_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[21:16]=6'h14 (Mirror: 6'h00)                       
+      RG_RX_ARDQ_EYE_F_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[29:24]=6'h14 (Mirror: 6'h00)                       
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x5a, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) |
+            P_Fld(0x5a, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x14, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) |
+            P_Fld(0x14, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ4                                         ral_reg_DDRPHY_blk_B1_DQ4                                  -     @9124                                                         
+      RG_RX_ARDQS_EYE_R_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[6:0]=7'h53 (Mirror: 7'h00)                         
+      RG_RX_ARDQS_EYE_F_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[14:8]=7'h53 (Mirror: 7'h00)                        
+      RG_RX_ARDQ_EYE_R_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[21:16]=6'h0d (Mirror: 6'h00)                       
+      RG_RX_ARDQ_EYE_F_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[29:24]=6'h0d (Mirror: 6'h00)                       
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x53, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) |
+            P_Fld(0x53, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x0d, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) |
+            P_Fld(0x0d, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ5                                         ral_reg_DDRPHY_blk_B0_DQ5                                  -     @7708                                                         
+      RG_RX_ARDQ_EYE_VREF_SEL_B0                   uvm_reg_field                                              ...    RW B0_DQ5[13:8]=6'h0e                                        
+      RG_RX_ARDQ_VREF_EN_B0                        uvm_reg_field                                              ...    RW B0_DQ5[16:16]=1'h0                                        
+      RG_RX_ARDQ_EYE_VREF_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ5[17:17]=1'h0                                        
+      RG_RX_ARDQ_EYE_SEL_B0                        uvm_reg_field                                              ...    RW B0_DQ5[23:20]=4'h0                                        
+      RG_RX_ARDQ_EYE_EN_B0                         uvm_reg_field                                              ...    RW B0_DQ5[24:24]=1'h0                                        
+      RG_RX_ARDQ_EYE_STBEN_RESETB_B0               uvm_reg_field                                              ...    RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0)                         
+      RG_RX_ARDQS0_DVS_EN_B0                       uvm_reg_field                                              ...    RW B0_DQ5[31:31]=1'h0                                        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x0e, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) |
+            P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) |
+            P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) |
+            P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value                                                         
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ5                                         ral_reg_DDRPHY_blk_B1_DQ5                                  -     @9131                                                         
+      RG_RX_ARDQ_EYE_VREF_SEL_B1                   uvm_reg_field                                              ...    RW B1_DQ5[13:8]=6'h0e                                        
+      RG_RX_ARDQ_VREF_EN_B1                        uvm_reg_field                                              ...    RW B1_DQ5[16:16]=1'h0                                        
+      RG_RX_ARDQ_EYE_VREF_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ5[17:17]=1'h0                                        
+      RG_RX_ARDQ_EYE_SEL_B1                        uvm_reg_field                                              ...    RW B1_DQ5[23:20]=4'h0                                        
+      RG_RX_ARDQ_EYE_EN_B1                         uvm_reg_field                                              ...    RW B1_DQ5[24:24]=1'h0                                        
+      RG_RX_ARDQ_EYE_STBEN_RESETB_B1               uvm_reg_field                                              ...    RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0)                         
+      RG_RX_ARDQS0_DVS_EN_B1                       uvm_reg_field                                              ...    RW B1_DQ5[31:31]=1'h0                                        
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x0e, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) |
+            P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) |
+            P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) |
+            P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT
+    //    Exit body
+}
+
+
+void TX_Path_Algorithm(DRAMC_CTX_T *p)
+{
+
+    U8 u1RandIdx = 0;
+    U8 WL = 0;
+    U8 u1DQS_TotalUI = 0;
+    U8 u1DQS_OE_TotalUI = 0;
+    U8 u1DQS_MCK, u1DQS_UI;
+    U8 u1DQS_OE_MCK, u1DQS_OE_UI;
+    U8 u1Small_ui_to_large;
+    U8 u1TxDQOEShift = 0;
+
+    u1Small_ui_to_large = u1MCK2UI_DivShift(p);
+    WL = Get_WL_by_MR_LP4(0, (u1MR02Value[p->dram_fsp]&0x3F)>>3);
+    u1DQS_TotalUI = WL*DFS_TOP[0].CKR*2 + 1;
+    #if ENABLE_WDQS_MODE_2
+    u1TxDQOEShift = WDQSMode2AcTxOEShift(p);
+    #else
+    u1TxDQOEShift = TX_DQ_OE_SHIFT_LP4;
+    #endif
+    u1DQS_OE_TotalUI = u1DQS_TotalUI - u1TxDQOEShift;
+
+    u1DQS_UI = u1DQS_TotalUI - ((u1DQS_TotalUI >> u1Small_ui_to_large) << u1Small_ui_to_large);
+    u1DQS_MCK = (u1DQS_TotalUI >> u1Small_ui_to_large);
+
+    u1DQS_OE_UI = u1DQS_OE_TotalUI - ((u1DQS_OE_TotalUI >> u1Small_ui_to_large) << u1Small_ui_to_large);
+    u1DQS_OE_MCK = (u1DQS_OE_TotalUI >> u1Small_ui_to_large);
+
+    //u1DQ_UI  = WL*DFS_TOP[0].CKR*2 - u1WDBI_EN*(DFS_TOP[0].DQ_P2S_RATIO) + (tDQSS+tDQS2DQ)*1000000/DFS_TOP[0].data_rate;
+
+    mcSHOW_DBG_MSG3(("[TX_path_calculate] data rate=%d, WL=%d, DQS_TotalUI=%d\n", DFS_TOP[0].data_rate, WL, u1DQS_TotalUI));
+    mcSHOW_DBG_MSG3(("[TX_path_calculate] DQS = (%d,%d) DQS_OE = (%d,%d)\n", u1DQS_MCK, u1DQS_UI, u1DQS_OE_MCK, u1DQS_OE_UI));
+
+    for(u1RandIdx = 0; u1RandIdx < p->support_rank_num; u1RandIdx ++)
+    {
+        vIO32WriteFldMulti_All(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(u1DQS_MCK, SHU_SELPH_DQS0_TXDLY_DQS0)
+                                                | P_Fld(u1DQS_MCK, SHU_SELPH_DQS0_TXDLY_DQS1)
+                                                | P_Fld(u1DQS_OE_MCK, SHU_SELPH_DQS0_TXDLY_OEN_DQS0)
+                                                | P_Fld(u1DQS_OE_MCK, SHU_SELPH_DQS0_TXDLY_OEN_DQS1));
+
+        vIO32WriteFldMulti_All(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(u1DQS_UI, SHU_SELPH_DQS1_DLY_DQS0)
+                                                | P_Fld(u1DQS_UI, SHU_SELPH_DQS1_DLY_DQS1)
+                                                | P_Fld(u1DQS_OE_UI, SHU_SELPH_DQS1_DLY_OEN_DQS0)
+                                                | P_Fld(u1DQS_OE_UI, SHU_SELPH_DQS1_DLY_OEN_DQS1));    
+    }
+}
+
+
+void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p)
+{
+    //    Enter body
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Enter:
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_DRVING1_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING1_0                      -     @12634
+      DQDRVN2                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[4:0]=5'h09 (Mirror: 5'h00)
+      DQDRVP2                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[9:5]=5'h07 (Mirror: 5'h00)
+      DQSDRVN1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[14:10]=5'h09 (Mirror: 5'h00)
+      DQSDRVP1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[19:15]=5'h07 (Mirror: 5'h00)
+      DQSDRVN2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[24:20]=5'h09 (Mirror: 5'h00)
+      DQSDRVP2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[29:25]=5'h07 (Mirror: 5'h00)
+      DIS_IMP_ODTN_track                           uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[30:30]=1'h0
+      DIS_IMPCAL_HW                                uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[31:31]=1'h0
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(0x09, SHU_MISC_DRVING1_DQDRVN2) |
+            P_Fld(0x07, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN1) |
+            P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN2) |
+            P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x1, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) |
+            P_Fld(0x1, SHU_MISC_DRVING1_DIS_IMPCAL_HW));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_DRVING2_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING2_0                      -     @12645
+      CMDDRVN1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[4:0]=5'h09 (Mirror: 5'h00)
+      CMDDRVP1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[9:5]=5'h07 (Mirror: 5'h00)
+      CMDDRVN2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[14:10]=5'h09 (Mirror: 5'h00)
+      CMDDRVP2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[19:15]=5'h07 (Mirror: 5'h00)
+      DQDRVN1                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[24:20]=5'h09 (Mirror: 5'h00)
+      DQDRVP1                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[29:25]=5'h07 (Mirror: 5'h00)
+      DIS_IMPCAL_ODT_EN                            uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[31:31]=1'h1 (Mirror: 1'h0)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2, P_Fld(0xF, SHU_MISC_DRVING2_CMDDRVN1) |
+            P_Fld(0x07, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0xF, SHU_MISC_DRVING2_CMDDRVN2) |
+            P_Fld(0x07, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x09, SHU_MISC_DRVING2_DQDRVN1) |
+            P_Fld(0x07, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x1, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_DRVING3_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING3_0                      -     @12655
+      DQODTN2                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[4:0]=5'h0a (Mirror: 5'h00)
+      DQODTP2                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[9:5]=5'h0a (Mirror: 5'h00)
+      DQSODTN                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[14:10]=5'h0a (Mirror: 5'h00)
+      DQSODTP                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[19:15]=5'h0a (Mirror: 5'h00)
+      DQSODTN2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[24:20]=5'h0a (Mirror: 5'h00)
+      DQSODTP2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[29:25]=5'h0a (Mirror: 5'h00)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3, P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) |
+            P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) |
+            P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) |
+            P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_DRVING4_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING4_0                      -     @12664
+      CMDODTN1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[4:0]=5'h0a (Mirror: 5'h00)
+      CMDODTP1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[9:5]=5'h0a (Mirror: 5'h00)
+      CMDODTN2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[14:10]=5'h0a (Mirror: 5'h00)
+      CMDODTP2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[19:15]=5'h0a (Mirror: 5'h00)
+      DQODTN1                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[24:20]=5'h0a (Mirror: 5'h00)
+      DQODTP1                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[29:25]=5'h0a (Mirror: 5'h00)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4, P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) |
+            P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) |
+            P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) |
+            P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_DRVING6_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING6_0                      -     @12682
+      IMP_TXDLY_CMD                                uvm_reg_field                                              ...    RW SHU_MISC_DRVING6_0[5:0]=6'h07 (Mirror: 6'h01)
+      DQCODTN1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING6_0[24:20]=5'h00
+      DQCODTP1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING6_0[29:25]=5'h00
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6, P_Fld(0x07, SHU_MISC_DRVING6_IMP_TXDLY_CMD) |
+            P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_IMPCAL1_0                             ral_reg_DDRPHY_blk_SHU_MISC_IMPCAL1_0                      -     @12625
+      IMPCAL_CHKCYCLE                              uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[2:0]=3'h3 (Mirror: 3'h4)
+      IMPDRVP                                      uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[8:4]=5'h00
+      IMPDRVN                                      uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[16:12]=5'h00
+      IMPCAL_CALEN_CYCLE                           uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[19:17]=3'h4
+      IMPCALCNT                                    uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[27:20]=8'h03 (Mirror: 8'h00)
+      IMPCAL_CALICNT                               uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[31:28]=4'h8
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1, P_Fld(0x3, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) |
+            P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) |
+            P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) |
+            P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Exit:
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter:
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_RDSEL_TRACK_0                         ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0                  -     @12734
+      DMDATLAT_i                                   uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h0a (Mirror: 5'h00)
+      RDSEL_HWSAVE_MSK                             uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0)
+      RDSEL_TRACK_EN                               uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0
+      SHU_GW_THRD_NEG                              uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfeb (Mirror: 12'h000)
+      SHU_GW_THRD_POS                              uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h015 (Mirror: 12'h000)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x0a, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) |
+            P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) |
+            P_Fld(0xfeb, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x015, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RDAT_0                                ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0                         -     @12604
+      DATLAT                                       uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[4:0]=5'h0a (Mirror: 5'h00)
+      DATLAT_DSEL                                  uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[12:8]=5'h09 (Mirror: 5'h00)
+      DATLAT_DSEL_PHY                              uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[20:16]=5'h09 (Mirror: 5'h00)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x0a, MISC_SHU_RDAT_DATLAT) |
+            P_Fld(0x09, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x09, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_PHY_RX_CTRL_0                         ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0                  -     @12540
+      RANK_RXDLY_UPDLAT_EN                         uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0)
+      RANK_RXDLY_UPD_OFFSET                        uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0)
+      RX_IN_GATE_EN_PRE_OFFSET                     uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0)
+      RX_IN_GATE_EN_HEAD                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h0
+      RX_IN_GATE_EN_TAIL                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0)
+      RX_IN_BUFF_EN_HEAD                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h0
+      RX_IN_BUFF_EN_TAIL                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) |
+            P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) |
+            P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) |
+            P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RANKCTL_0                             ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0                      -     @12530
+      RANKINCTL_RXDLY                              uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[3:0]=4'h0
+      RANK_RXDLY_OPT                               uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[4:4]=1'h1
+      RANKSEL_SELPH_FRUN                           uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[15:15]=1'h0
+      RANKINCTL_STB                                uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[19:16]=4'h2 (Mirror: 4'h0)
+      RANKINCTL                                    uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[23:20]=4'h0
+      RANKINCTL_ROOT1                              uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[27:24]=4'h0
+      RANKINCTL_PHY                                uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[31:28]=4'h3 (Mirror: 4'h0)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) |
+            P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) |
+            P_Fld(0x2, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL) |
+            P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x3, MISC_SHU_RANKCTL_RANKINCTL_PHY));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RANK_SEL_LAT_0                        ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0                 -     @12757
+      RANK_SEL_LAT_B0                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0)
+      RANK_SEL_LAT_B1                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0)
+      RANK_SEL_LAT_CA                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
+            P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCTL_0_0                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0                  -     @12352
+      DQSINCTL                                     uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h2 (Mirror: 4'h0)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL);
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCTL_0_1                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1                  -     @12356
+      DQSINCTL                                     uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h2 (Mirror: 4'h0)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*0x80), 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL);
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0         -     @7624
+      DQSIEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h9 (Mirror: 4'h0)
+      DQSIEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hd (Mirror: 4'h0)
+      DQSIEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0
+      DQSIEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x9, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+            P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_PI_DLY_0_0                    ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0             -     @7638
+      DQSIEN_PI_B0                                 uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00)
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0b, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1         -     @7631
+      DQSIEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0)
+      DQSIEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0
+      DQSIEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0
+      DQSIEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*0x80), P_Fld(0xc, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+            P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_PI_DLY_0_1                    ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1             -     @7642
+      DQSIEN_PI_B0                                 uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*0x80), 0x11, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0         -     @9027
+      DQSIEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h9 (Mirror: 4'h0)
+      DQSIEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hd (Mirror: 4'h0)
+      DQSIEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0
+      DQSIEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x9, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+            P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_PI_DLY_0_0                    ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0             -     @9041
+      DQSIEN_PI_B1                                 uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0b, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1         -     @9034
+      DQSIEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0)
+      DQSIEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0
+      DQSIEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0
+      DQSIEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*0x80), P_Fld(0xc, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+            P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_PI_DLY_0_1                    ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1             -     @9045
+      DQSIEN_PI_B1                                 uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*0x80), 0x11, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_ODTCTRL_0                             ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0                      -     @12550
+      RODTEN                                       uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0)
+      RODTENSTB_SELPH_CG_IG                        uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[1:1]=1'h0
+      RODT_LAT                                     uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[7:4]=4'h1 (Mirror: 4'h0)
+      RODTEN_SELPH_FRUN                            uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[15:15]=1'h0
+      RODTDLY_LAT_OPT                              uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[25:24]=2'h0
+      FIXRODT                                      uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[27:27]=1'h0
+      RODTEN_OPT                                   uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[29:29]=1'h1
+      RODTE2                                       uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0)
+      RODTE                                        uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODT_LAT) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) |
+            P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ7_0                            -     @7808
+      R_DMRANKRXDVS_B0                             uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[3:0]=4'h0
+      R_DMDQMDBI_EYE_SHU_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[6:6]=1'h0
+      R_DMDQMDBI_SHU_B0                            uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[7:7]=1'h0
+      R_DMRXDVS_DQM_FLAGSEL_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[11:8]=4'h0
+      R_DMRXDVS_PBYTE_FLAG_OPT_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[12:12]=1'h0
+      R_DMRXDVS_PBYTE_DQM_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[13:13]=1'h0
+      R_DMRXTRACK_DQM_EN_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[14:14]=1'h0
+      R_DMRODTEN_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)
+      R_DMARPI_CG_FB2DLL_DCM_EN_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[16:16]=1'h0
+      R_DMTX_ARPI_CG_DQ_NEW_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[17:17]=1'h0
+      R_DMTX_ARPI_CG_DQS_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[18:18]=1'h0
+      R_DMTX_ARPI_CG_DQM_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[19:19]=1'h0
+      R_LP4Y_SDN_MODE_DQS0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[20:20]=1'h0
+      R_DMRXRANK_DQ_EN_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)
+      R_DMRXRANK_DQ_LAT_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0)
+      R_DMRXRANK_DQS_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)
+      R_DMRXRANK_DQS_LAT_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[31:29]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ7_0                            -     @9211
+      R_DMRANKRXDVS_B1                             uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[3:0]=4'h0
+      R_DMDQMDBI_EYE_SHU_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[6:6]=1'h0
+      R_DMDQMDBI_SHU_B1                            uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[7:7]=1'h0
+      R_DMRXDVS_DQM_FLAGSEL_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[11:8]=4'h0
+      R_DMRXDVS_PBYTE_FLAG_OPT_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[12:12]=1'h0
+      R_DMRXDVS_PBYTE_DQM_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[13:13]=1'h0
+      R_DMRXTRACK_DQM_EN_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[14:14]=1'h0
+      R_DMRODTEN_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)
+      R_DMARPI_CG_FB2DLL_DCM_EN_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[16:16]=1'h0
+      R_DMTX_ARPI_CG_DQ_NEW_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[17:17]=1'h0
+      R_DMTX_ARPI_CG_DQS_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[18:18]=1'h0
+      R_DMTX_ARPI_CG_DQM_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[19:19]=1'h0
+      R_LP4Y_SDN_MODE_DQS1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[20:20]=1'h0
+      R_DMRXRANK_DQ_EN_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)
+      R_DMRXRANK_DQ_LAT_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0)
+      R_DMRXRANK_DQS_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)
+      R_DMRXRANK_DQS_LAT_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[31:29]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0         -     @7646
+      RODTEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0)
+      RODTEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0)
+      RODTEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0
+      RODTEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+            P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1         -     @7653
+      RODTEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0)
+      RODTEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0)
+      RODTEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0
+      RODTEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*0x80), P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+            P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0         -     @9049
+      RODTEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0)
+      RODTEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0)
+      RODTEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0
+      RODTEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+            P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1         -     @9056
+      RODTEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0)
+      RODTEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0)
+      RODTEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0
+      RODTEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*0x80), P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+            P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RX_CG_SET0_0                               ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0                         -     @5323
+      DLE_LAST_EXTEND3                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[0:0]=1'h0
+      READ_START_EXTEND3                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[1:1]=1'h0
+      DLE_LAST_EXTEND2                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[2:2]=1'h0
+      READ_START_EXTEND2                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[3:3]=1'h0
+      DLE_LAST_EXTEND1                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0)
+      READ_START_EXTEND1                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) |
+            P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) |
+            P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
+            P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_RANK_SEL_STB_0                        ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0                 -     @12720
+      RANK_SEL_STB_EN                              uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0)
+      RANK_SEL_STB_EN_B23                          uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0
+      RANK_SEL_STB_SERMODE                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0
+      RANK_SEL_STB_TRACK                           uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0)
+      RANK_SEL_RXDLY_TRACK                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0
+      RANK_SEL_STB_PHASE_EN                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h1 (Mirror: 1'h0)
+      RANK_SEL_PHSINCTL                            uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h3 (Mirror: 4'h0)
+      RANK_SEL_STB_UI_PLUS                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0
+      RANK_SEL_STB_MCK_PLUS                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0
+      RANK_SEL_STB_UI_MINUS                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h1 (Mirror: 4'h0)
+      RANK_SEL_STB_MCK_MINUS                       uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) |
+            P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) |
+            P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) |
+            P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x3, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) |
+            P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) |
+            P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCAL_0_0                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0                  -     @12370
+      DQSIENLLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00)
+      DQSIENLLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0)
+      DQSIENHLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00)
+      DQSIENHLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCAL_0_1                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1                  -     @12377
+      DQSIENLLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00)
+      DQSIENLLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0)
+      DQSIENHLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00)
+      DQSIENHLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*0x80), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_INI_UIPI_0_0                         ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0                  -     @7602
+      CURR_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)
+      CURR_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+            P_Fld(0x09, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_INI_UIPI_0_0                         ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0                  -     @9005
+      CURR_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)
+      CURR_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+            P_Fld(0x09, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_INI_UIPI_0_1                         ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1                  -     @7607
+      CURR_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00)
+      CURR_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*0x80), P_Fld(0x11, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+            P_Fld(0x0c, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_INI_UIPI_0_1                         ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1                  -     @9010
+      CURR_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00)
+      CURR_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*0x80), P_Fld(0x11, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+            P_Fld(0x0c, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_NEXT_INI_UIPI_0_0                    ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0             -     @7612
+      NEXT_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)
+      NEXT_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00)
+      NEXT_INI_UI_P1_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h0d (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+            P_Fld(0x09, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_NEXT_INI_UIPI_0_0                    ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0             -     @9015
+      NEXT_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)
+      NEXT_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00)
+      NEXT_INI_UI_P1_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h0d (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+            P_Fld(0x09, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_NEXT_INI_UIPI_0_1                    ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1             -     @7618
+      NEXT_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00)
+      NEXT_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00)
+      NEXT_INI_UI_P1_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*0x80), P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+            P_Fld(0x0c, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x10, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_NEXT_INI_UIPI_0_1                    ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1             -     @9021
+      NEXT_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00)
+      NEXT_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00)
+      NEXT_INI_UI_P1_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*0x80), P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+            P_Fld(0x0c, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x10, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit:
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter:
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_DQ0_0_0                              ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0                       -     @7582
+      RG_RX_ARDQS0_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0
+      RG_RX_ARDQS0_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0
+      SW_ARPI_DQ_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[13:8]=6'h1d (Mirror: 6'h00)
+      SW_ARPI_DQM_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[21:16]=6'h1d (Mirror: 6'h00)
+      ARPI_PBYTE_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00
+      DA_ARPI_DDR400_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0
+      DA_RX_ARDQSIEN_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x1d, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+            P_Fld(0x1d, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_DQ0_0_0                              ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0                       -     @8985
+      RG_RX_ARDQS1_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0
+      RG_RX_ARDQS1_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0
+      SW_ARPI_DQ_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[13:8]=6'h1d (Mirror: 6'h00)
+      SW_ARPI_DQM_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[21:16]=6'h1d (Mirror: 6'h00)
+      ARPI_PBYTE_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00
+      DA_ARPI_DDR400_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0
+      DA_RX_ARDQSIEN_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x1d, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+            P_Fld(0x1d, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_DQ0_0_1                              ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1                       -     @7592
+      RG_RX_ARDQS0_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0
+      RG_RX_ARDQS0_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0
+      SW_ARPI_DQ_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[13:8]=6'h0d (Mirror: 6'h00)
+      SW_ARPI_DQM_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[21:16]=6'h0d (Mirror: 6'h00)
+      ARPI_PBYTE_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00
+      DA_ARPI_DDR400_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0
+      DA_RX_ARDQSIEN_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*0x80), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0d, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+            P_Fld(0x0d, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_DQ0_0_1                              ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1                       -     @8995
+      RG_RX_ARDQS1_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0
+      RG_RX_ARDQS1_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0
+      SW_ARPI_DQ_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[13:8]=6'h13 (Mirror: 6'h00)
+      SW_ARPI_DQM_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[21:16]=6'h13 (Mirror: 6'h00)
+      ARPI_PBYTE_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00
+      DA_ARPI_DDR400_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0
+      DA_RX_ARDQSIEN_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*0x80), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x13, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+            P_Fld(0x13, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_DCM_CTRL0_0                                ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0                          -     @5027
+      DDRPHY_CLK_EN_OPT                            uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0)
+      DPHY_CMDDCM_EXTCNT                           uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[11:8]=4'h4
+      DDRPHY_CLK_DYN_GATING_SEL                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0)
+      CKE_EXTNONPD_CNT                             uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[19:16]=4'h0
+      FASTWAKE2                                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[29:29]=1'h0
+      FASTWAKE                                     uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[31:31]=1'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if (fcFOR_CHIP_ID == fcA60868)
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+            P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+            P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) |
+            P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+    #elif(fcFOR_CHIP_ID == fcPetrus)
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+            P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+            P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) |
+            P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_APHY_TX_PICG_CTRL_0                        ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0                  -     @5377
+      DDRPHY_CLK_EN_COMB_TX_PICG_CNT               uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h7 (Mirror: 4'h0)
+      DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1             uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h1 (Mirror: 3'h0)
+      DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0             uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h0
+      DDRPHY_CLK_EN_COMB_TX_OPT                    uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x7, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) |
+            P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) |
+            P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_APHY_TX_PICG_CTRL_0_0                    ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0              -     @4926
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h1 (Mirror: 3'h0)
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x1, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+            P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_APHY_TX_PICG_CTRL_0_1                    ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1              -     @4931
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h1 (Mirror: 3'h0)
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*0x200), P_Fld(0x1, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+            P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_NEW_XRW2W_CTRL_0                           ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0                     -     @5371
+      TX_PI_UPDCTL_B0                              uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h0
+      TX_PI_UPDCTL_B1                              uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h0
+      TXPI_UPD_MODE                                uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) |
+            P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_DQS0_0                               ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0                         -     @5271
+      TXDLY_DQS0                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[2:0]=3'h2 (Mirror: 3'h1)
+      TXDLY_DQS1                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[6:4]=3'h2 (Mirror: 3'h1)
+      TXDLY_DQS2                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[10:8]=3'h1
+      TXDLY_DQS3                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[14:12]=3'h1
+      TXDLY_OEN_DQS0                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[18:16]=3'h1
+      TXDLY_OEN_DQS1                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[22:20]=3'h1
+      TXDLY_OEN_DQS2                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[26:24]=3'h1
+      TXDLY_OEN_DQS3                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[30:28]=3'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS0) |
+            P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) |
+            P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_DQS1_0                               ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0                         -     @5282
+      dly_DQS0                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[3:0]=4'h1
+      dly_DQS1                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[7:4]=4'h1
+      dly_DQS2                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[11:8]=4'h1
+      dly_DQS3                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[15:12]=4'h1
+      dly_oen_DQS0                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[19:16]=4'h6 (Mirror: 4'h1)
+      dly_oen_DQS1                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[23:20]=4'h6 (Mirror: 4'h1)
+      dly_oen_DQS2                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[27:24]=4'h1
+      dly_oen_DQS3                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[31:28]=4'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS0) |
+            P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS0) |
+            P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ0_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0                      -     @4746
+      TXDLY_DQ0                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[2:0]=3'h2 (Mirror: 3'h1)
+      TXDLY_DQ1                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[6:4]=3'h2 (Mirror: 3'h1)
+      TXDLY_DQ2                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1
+      TXDLY_DQ3                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1
+      TXDLY_OEN_DQ0                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[18:16]=3'h1
+      TXDLY_OEN_DQ1                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[22:20]=3'h1
+      TXDLY_OEN_DQ2                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1
+      TXDLY_OEN_DQ3                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+            P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ1_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0                      -     @4768
+      TXDLY_DQM0                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[2:0]=3'h2 (Mirror: 3'h1)
+      TXDLY_DQM1                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[6:4]=3'h2 (Mirror: 3'h1)
+      TXDLY_DQM2                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1
+      TXDLY_DQM3                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1
+      TXDLY_OEN_DQM0                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[18:16]=3'h1
+      TXDLY_OEN_DQM1                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[22:20]=3'h1
+      TXDLY_OEN_DQM2                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1
+      TXDLY_OEN_DQM3                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+            P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ2_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0                      -     @4790
+      dly_DQ0                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[3:0]=4'h1
+      dly_DQ1                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[7:4]=4'h1
+      dly_DQ2                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1
+      dly_DQ3                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1
+      dly_oen_DQ0                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[19:16]=4'h6 (Mirror: 4'h1)
+      dly_oen_DQ1                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[23:20]=4'h6 (Mirror: 4'h1)
+      dly_oen_DQ2                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1
+      dly_oen_DQ3                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+            P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ3_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0                      -     @4812
+      dly_DQM0                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[3:0]=4'h1
+      dly_DQM1                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[7:4]=4'h1
+      dly_DQM2                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1
+      dly_DQM3                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1
+      dly_oen_DQM0                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[19:16]=4'h6 (Mirror: 4'h1)
+      dly_oen_DQM1                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[23:20]=4'h6 (Mirror: 4'h1)
+      dly_oen_DQM2                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1
+      dly_oen_DQM3                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+            P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ0_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1                      -     @4757
+      TXDLY_DQ0                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[2:0]=3'h2 (Mirror: 3'h1)
+      TXDLY_DQ1                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[6:4]=3'h2 (Mirror: 3'h1)
+      TXDLY_DQ2                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1
+      TXDLY_DQ3                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1
+      TXDLY_OEN_DQ0                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[18:16]=3'h1
+      TXDLY_OEN_DQ1                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[22:20]=3'h1
+      TXDLY_OEN_DQ2                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1
+      TXDLY_OEN_DQ3                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*0x200), P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+            P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ1_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1                      -     @4779
+      TXDLY_DQM0                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[2:0]=3'h2 (Mirror: 3'h1)
+      TXDLY_DQM1                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[6:4]=3'h2 (Mirror: 3'h1)
+      TXDLY_DQM2                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1
+      TXDLY_DQM3                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1
+      TXDLY_OEN_DQM0                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[18:16]=3'h1
+      TXDLY_OEN_DQM1                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[22:20]=3'h1
+      TXDLY_OEN_DQM2                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1
+      TXDLY_OEN_DQM3                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*0x200), P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+            P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ2_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1                      -     @4801
+      dly_DQ0                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[3:0]=4'h2 (Mirror: 4'h1)
+      dly_DQ1                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[7:4]=4'h2 (Mirror: 4'h1)
+      dly_DQ2                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1
+      dly_DQ3                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1
+      dly_oen_DQ0                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[19:16]=4'h7 (Mirror: 4'h1)
+      dly_oen_DQ1                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[23:20]=4'h7 (Mirror: 4'h1)
+      dly_oen_DQ2                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1
+      dly_oen_DQ3                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*0x200), P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ0) |
+            P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+            P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ3_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1                      -     @4823
+      dly_DQM0                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[3:0]=4'h2 (Mirror: 4'h1)
+      dly_DQM1                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[7:4]=4'h2 (Mirror: 4'h1)
+      dly_DQM2                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1
+      dly_DQM3                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1
+      dly_oen_DQM0                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[19:16]=4'h7 (Mirror: 4'h1)
+      dly_oen_DQM1                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[23:20]=4'h7 (Mirror: 4'h1)
+      dly_oen_DQM2                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1
+      dly_oen_DQM3                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*0x200), P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM0) |
+            P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+            P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL1_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0                    -     @4834
+      BOOT_ORIG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h01d (Mirror: 11'h000)
+      BOOT_ORIG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h01d (Mirror: 11'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x01d, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+            P_Fld(0x01d, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL2_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0                    -     @4844
+      BOOT_TARG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h01d (Mirror: 11'h000)
+      BOOT_TARG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h01d (Mirror: 11'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x01d, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+            P_Fld(0x01d, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL5_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0                    -     @4882
+      BOOT_TARG_UI_RK0_DQM0                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h01d (Mirror: 11'h000)
+      BOOT_TARG_UI_RK0_DQM1                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h01d (Mirror: 11'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x01d, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+            P_Fld(0x01d, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL1_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1                    -     @4839
+      BOOT_ORIG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h00d (Mirror: 11'h000)
+      BOOT_ORIG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h013 (Mirror: 11'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*0x200), P_Fld(0x00d, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+            P_Fld(0x013, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL2_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1                    -     @4849
+      BOOT_TARG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h00d (Mirror: 11'h000)
+      BOOT_TARG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h013 (Mirror: 11'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*0x200), P_Fld(0x00d, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+            P_Fld(0x013, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL5_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1                    -     @4887
+      BOOT_TARG_UI_RK0_DQM0                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h00d (Mirror: 11'h000)
+      BOOT_TARG_UI_RK0_DQM1                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h013 (Mirror: 11'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*0x200), P_Fld(0x00d, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+            P_Fld(0x013, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_PI_0_0                                   ral_reg_DRAMC_blk_SHURK_PI_0_0                             -     @4892
+      RK0_ARPI_DQ_B1                               uvm_reg_field                                              ...    RW SHURK_PI_0_0[5:0]=6'h1d (Mirror: 6'h00)
+      RK0_ARPI_DQ_B0                               uvm_reg_field                                              ...    RW SHURK_PI_0_0[13:8]=6'h1d (Mirror: 6'h00)
+      RK0_ARPI_DQM_B1                              uvm_reg_field                                              ...    RW SHURK_PI_0_0[21:16]=6'h1d (Mirror: 6'h00)
+      RK0_ARPI_DQM_B0                              uvm_reg_field                                              ...    RW SHURK_PI_0_0[29:24]=6'h1d (Mirror: 6'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQ_B1) |
+            P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQM_B1) |
+            P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQM_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_PI_0_1                                   ral_reg_DRAMC_blk_SHURK_PI_0_1                             -     @4899
+      RK0_ARPI_DQ_B1                               uvm_reg_field                                              ...    RW SHURK_PI_0_1[5:0]=6'h13 (Mirror: 6'h00)
+      RK0_ARPI_DQ_B0                               uvm_reg_field                                              ...    RW SHURK_PI_0_1[13:8]=6'h0d (Mirror: 6'h00)
+      RK0_ARPI_DQM_B1                              uvm_reg_field                                              ...    RW SHURK_PI_0_1[21:16]=6'h13 (Mirror: 6'h00)
+      RK0_ARPI_DQM_B0                              uvm_reg_field                                              ...    RW SHURK_PI_0_1[29:24]=6'h0d (Mirror: 6'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*0x200), P_Fld(0x13, SHURK_PI_RK0_ARPI_DQ_B1) |
+            P_Fld(0x0d, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x13, SHURK_PI_RK0_ARPI_DQM_B1) |
+            P_Fld(0x0d, SHURK_PI_RK0_ARPI_DQM_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0                    -     @7428
+      TX_ARDQ0_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h10 (Mirror: 8'h00)
+      TX_ARDQ1_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h10 (Mirror: 8'h00)
+      TX_ARDQ2_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h10 (Mirror: 8'h00)
+      TX_ARDQ3_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h10 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+            P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+            P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0                    -     @7442
+      TX_ARDQ4_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h10 (Mirror: 8'h00)
+      TX_ARDQ5_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h10 (Mirror: 8'h00)
+      TX_ARDQ6_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h10 (Mirror: 8'h00)
+      TX_ARDQ7_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h10 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+            P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+            P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0                    -     @7470
+      TX_ARDQM0_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h10 (Mirror: 8'h00)
+      TX_ARWCK_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00
+      TX_ARWCKB_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x10, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+            P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0                    -     @8831
+      TX_ARDQ0_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h14 (Mirror: 8'h00)
+      TX_ARDQ1_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h14 (Mirror: 8'h00)
+      TX_ARDQ2_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h14 (Mirror: 8'h00)
+      TX_ARDQ3_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h14 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+            P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+            P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0                    -     @8845
+      TX_ARDQ4_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h14 (Mirror: 8'h00)
+      TX_ARDQ5_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h14 (Mirror: 8'h00)
+      TX_ARDQ6_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h14 (Mirror: 8'h00)
+      TX_ARDQ7_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h14 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+            P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+            P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0                    -     @8873
+      TX_ARDQM0_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h14 (Mirror: 8'h00)
+      TX_ARWCK_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00
+      TX_ARWCKB_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x14, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+            P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1                    -     @7435
+      TX_ARDQ0_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h3c (Mirror: 8'h00)
+      TX_ARDQ1_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h3c (Mirror: 8'h00)
+      TX_ARDQ2_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h3c (Mirror: 8'h00)
+      TX_ARDQ3_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h3c (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*0x80), P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+            P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+            P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1                    -     @7449
+      TX_ARDQ4_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h3c (Mirror: 8'h00)
+      TX_ARDQ5_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h3c (Mirror: 8'h00)
+      TX_ARDQ6_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h3c (Mirror: 8'h00)
+      TX_ARDQ7_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h3c (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*0x80), P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+            P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+            P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1                    -     @7476
+      TX_ARDQM0_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h3c (Mirror: 8'h00)
+      TX_ARWCK_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00
+      TX_ARWCKB_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*0x80), P_Fld(0x3c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+            P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ9_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ9_0                            -     @7845
+      RG_ARPI_RESERVE_B0                           uvm_reg_field                                              ...    RW SHU_B0_DQ9_0[31:0]=32'hbf31f45b (Mirror: 32'hbf33f45b)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9, 0xbf31f45b, SHU_B0_DQ9_RG_ARPI_RESERVE_B0);
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit:
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Enter:
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_CA1_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA1_0                          -     @5041
+      TXDLY_CS                                     uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[2:0]=3'h0 (Mirror: 3'h1)
+      TXDLY_CKE                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[6:4]=3'h0 (Mirror: 3'h1)
+      TXDLY_ODT                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[10:8]=3'h0 (Mirror: 3'h1)
+      TXDLY_RESET                                  uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[14:12]=3'h0 (Mirror: 3'h1)
+      TXDLY_WE                                     uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[18:16]=3'h0 (Mirror: 3'h1)
+      TXDLY_CAS                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[22:20]=3'h0 (Mirror: 3'h1)
+      TXDLY_RAS                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[26:24]=3'h0 (Mirror: 3'h1)
+      TXDLY_CS1                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[30:28]=3'h0 (Mirror: 3'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) |
+            P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) |
+            P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) |
+            P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) |
+            P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_CA2_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA2_0                          -     @5052
+      TXDLY_BA0                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[2:0]=3'h0 (Mirror: 3'h1)
+      TXDLY_BA1                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[6:4]=3'h0 (Mirror: 3'h1)
+      TXDLY_BA2                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[10:8]=3'h0 (Mirror: 3'h1)
+      TXDLY_CMD                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[20:16]=5'h01
+      TXDLY_CKE1                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[26:24]=3'h0 (Mirror: 3'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) |
+            P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) |
+            P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_CA3_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA3_0                          -     @5060
+      TXDLY_RA0                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[2:0]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA1                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[6:4]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA2                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[10:8]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA3                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[14:12]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA4                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[18:16]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA5                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[22:20]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA6                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[26:24]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA7                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[30:28]=3'h0 (Mirror: 3'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) |
+            P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) |
+            P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) |
+            P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) |
+            P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_CA4_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA4_0                          -     @5071
+      TXDLY_RA8                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[2:0]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA9                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[6:4]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA10                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[10:8]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA11                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[14:12]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA12                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[18:16]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA13                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[22:20]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA14                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[26:24]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA15                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[30:28]=3'h0 (Mirror: 3'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) |
+            P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) |
+            P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) |
+            P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) |
+            P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_CA5_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA5_0                          -     @5082
+      dly_CS                                       uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[2:0]=3'h1
+      dly_CKE                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[6:4]=3'h1
+      dly_ODT                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[10:8]=3'h0 (Mirror: 3'h1)
+      dly_RESET                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[14:12]=3'h1
+      dly_WE                                       uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[18:16]=3'h1
+      dly_CAS                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[22:20]=3'h1
+      dly_RAS                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[26:24]=3'h1
+      dly_CS1                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[30:28]=3'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5, P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) |
+            P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) |
+            P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) |
+            P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) |
+            P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter:
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SREF_CTRL_0                                ral_reg_DRAMC_blk_SHU_SREF_CTRL_0                          -     @5018
+      CKEHCMD                                      uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[5:4]=2'h3
+      SREF_CK_DLY                                  uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) |
+            P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_HMR4_DVFS_CTRL0_0                          ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0                    -     @5036
+      FSPCHG_PRDCNT                                uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h32 (Mirror: 8'h00)
+      REFRCNT                                      uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x32, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+            P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_AC_TIME_05T_0                              ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0                        -     @5199
+      TRC_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[0:0]=1'h0
+      TRFCPB_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[1:1]=1'h0
+      TRFC_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[2:2]=1'h0
+      TPBR2PBR_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[3:3]=1'h0
+      TXP_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[4:4]=1'h0
+      TRTP_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[5:5]=1'h1 (Mirror: 1'h0)
+      TRCD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[6:6]=1'h0
+      TRP_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[7:7]=1'h1 (Mirror: 1'h0)
+      TRPAB_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[8:8]=1'h0
+      TRAS_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[9:9]=1'h0
+      TWR_M05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0)
+      TRRD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[12:12]=1'h0
+      TFAW_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[13:13]=1'h0
+      TCKEPRD_05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[14:14]=1'h0
+      TR2PD_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[15:15]=1'h0
+      TWTPD_M05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[16:16]=1'h1 (Mirror: 1'h0)
+      TMRRI_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[17:17]=1'h1 (Mirror: 1'h0)
+      TMRWCKEL_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[18:18]=1'h0
+      BGTRRD_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[19:19]=1'h0
+      BGTCCD_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[20:20]=1'h0
+      BGTWTR_M05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[21:21]=1'h1 (Mirror: 1'h0)
+      TR2W_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[22:22]=1'h0
+      TWTR_M05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[23:23]=1'h1 (Mirror: 1'h0)
+      XRTR2W_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[24:24]=1'h0
+      TMRD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[25:25]=1'h0
+      TMRW_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[26:26]=1'h1 (Mirror: 1'h0)
+      TMRR2MRW_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[27:27]=1'h1 (Mirror: 1'h0)
+      TW2MRW_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[28:28]=1'h1 (Mirror: 1'h0)
+      TR2MRW_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[29:29]=1'h0
+      TPBR2ACT_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[30:30]=1'h0
+      XRTW2R_M05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TXP_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRCD_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRRI_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_BGTWTR_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTR_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRD_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRR2MRW_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM_XRT_0                                ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0                          -     @5192
+      XRTR2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[4:0]=5'h03 (Mirror: 5'h01)
+      XRTR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[13:8]=6'h03 (Mirror: 6'h01)
+      XRTW2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[19:16]=4'h3 (Mirror: 4'h1)
+      XRTW2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[28:24]=5'h03 (Mirror: 5'h01)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x03, SHU_ACTIM_XRT_XRTR2R) |
+            P_Fld(0x03, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x3, SHU_ACTIM_XRT_XRTW2R) |
+            P_Fld(0x4, SHU_ACTIM_XRT_XRTW2W));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM0_0                                   ral_reg_DRAMC_blk_SHU_ACTIM0_0                             -     @5138
+      TWTR                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[3:0]=4'h4 (Mirror: 4'h1)
+      CKELCKCNT                                    uvm_reg_field                                              ...    RW SHU_ACTIM0_0[6:4]=3'h2 (Mirror: 3'h0)
+      TWR                                          uvm_reg_field                                              ...    RW SHU_ACTIM0_0[15:8]=8'h08 (Mirror: 8'h06)
+      TRRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[18:16]=3'h1 (Mirror: 3'h0)
+      TRCD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[27:24]=4'h4 (Mirror: 4'h2)
+      TWTR_L                                       uvm_reg_field                                              ...    RW SHU_ACTIM0_0[31:28]=4'h7 (Mirror: 4'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if (fcFOR_CHIP_ID == fcA60868)
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x4, SHU_ACTIM0_TWTR) |
+            P_Fld(0x2, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x08, SHU_ACTIM0_TWR) |
+            P_Fld(0x1, SHU_ACTIM0_TRRD) | P_Fld(0x4, SHU_ACTIM0_TRCD) |
+            P_Fld(0x7, SHU_ACTIM0_TWTR_L));
+    #elif (fcFOR_CHIP_ID == fcPetrus)
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x4, SHU_ACTIM0_TWTR) |
+            P_Fld(0x2, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x08, SHU_ACTIM0_TWR) |
+            P_Fld(0x1, SHU_ACTIM0_TRRD) | P_Fld(0x4, SHU_ACTIM0_TRCD));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM1_0                                   ral_reg_DRAMC_blk_SHU_ACTIM1_0                             -     @5147
+      TRPAB                                        uvm_reg_field                                              ...    RW SHU_ACTIM1_0[3:0]=4'h3 (Mirror: 4'ha)
+      TMRWCKEL                                     uvm_reg_field                                              ...    RW SHU_ACTIM1_0[7:4]=4'h4 (Mirror: 4'h8)
+      TRP                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[11:8]=4'h2
+      TRAS                                         uvm_reg_field                                              ...    RW SHU_ACTIM1_0[21:16]=6'h00 (Mirror: 6'h04)
+      TRC                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[28:24]=5'h04 (Mirror: 5'h05)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x3, SHU_ACTIM1_TRPAB) |
+            P_Fld(0x4, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x2, SHU_ACTIM1_TRP) |
+            P_Fld(0x00, SHU_ACTIM1_TRAS) | P_Fld(0x04, SHU_ACTIM1_TRC));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM2_0                                   ral_reg_DRAMC_blk_SHU_ACTIM2_0                             -     @5155
+      TXP                                          uvm_reg_field                                              ...    RW SHU_ACTIM2_0[3:0]=4'h0
+      TMRRI                                        uvm_reg_field                                              ...    RW SHU_ACTIM2_0[8:4]=5'h05 (Mirror: 5'h0e)
+      TRTP                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[14:12]=3'h1 (Mirror: 3'h0)
+      TR2W                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[21:16]=6'h03 (Mirror: 6'h00)
+      TFAW                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[28:24]=5'h00 (Mirror: 5'h05)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x0, SHU_ACTIM2_TXP) |
+            P_Fld(0x05, SHU_ACTIM2_TMRRI) | P_Fld(0x1, SHU_ACTIM2_TRTP) |
+            P_Fld(0x03, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM3_0                                   ral_reg_DRAMC_blk_SHU_ACTIM3_0                             -     @5163
+      TRFCPB                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[7:0]=8'h10 (Mirror: 8'h00)
+      MANTMRR                                      uvm_reg_field                                              ...    RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0)
+      TR2MRR                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0)
+      TRFC                                         uvm_reg_field                                              ...    RW SHU_ACTIM3_0[23:16]=8'h2c (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x10, SHU_ACTIM3_TRFCPB) |
+            P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) |
+            P_Fld(0x2c, SHU_ACTIM3_TRFC));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM4_0                                   ral_reg_DRAMC_blk_SHU_ACTIM4_0                             -     @5170
+      TXREFCNT                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[9:0]=10'h03a (Mirror: 10'h028)
+      TMRR2MRW                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[15:10]=6'h07 (Mirror: 6'h00)
+      TMRR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM4_0[21:16]=6'h05 (Mirror: 6'h00)
+      TZQCS                                        uvm_reg_field                                              ...    RW SHU_ACTIM4_0[31:24]=8'h10 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x03a, SHU_ACTIM4_TXREFCNT) |
+            P_Fld(0x07, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x05, SHU_ACTIM4_TMRR2W) |
+            P_Fld(0x10, SHU_ACTIM4_TZQCS));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM5_0                                   ral_reg_DRAMC_blk_SHU_ACTIM5_0                             -     @5177
+      TR2PD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[6:0]=7'h08 (Mirror: 7'h00)
+      TWTPD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[14:8]=7'h09 (Mirror: 7'h00)
+      TPBR2PBR                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[23:16]=8'h12 (Mirror: 8'h00)
+      TPBR2ACT                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[29:28]=2'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x08, SHU_ACTIM5_TR2PD) |
+            P_Fld(0x09, SHU_ACTIM5_TWTPD) | P_Fld(0x12, SHU_ACTIM5_TPBR2PBR) |
+            P_Fld(0x0, SHU_ACTIM5_TPBR2ACT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM6_0                                   ral_reg_DRAMC_blk_SHU_ACTIM6_0                             -     @5184
+      TZQLAT2                                      uvm_reg_field                                              ...    RW SHU_ACTIM6_0[4:0]=5'h06 (Mirror: 5'h1f)
+      TMRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[11:8]=4'h3 (Mirror: 4'h0)
+      TMRW                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[15:12]=4'h2 (Mirror: 4'h0)
+      TW2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[25:20]=6'h06 (Mirror: 6'h00)
+      TR2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[31:26]=6'h07 (Mirror: 6'h13)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x06, SHU_ACTIM6_TZQLAT2) |
+            P_Fld(0x3, SHU_ACTIM6_TMRD) | P_Fld(0x2, SHU_ACTIM6_TMRW) |
+            P_Fld(0x06, SHU_ACTIM6_TW2MRW) | P_Fld(0x07, SHU_ACTIM6_TR2MRW));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_CKECTRL_0                                  ral_reg_DRAMC_blk_SHU_CKECTRL_0                            -     @5262
+      TPDE_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0)
+      TPDX_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[1:1]=1'h0
+      TPDE                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[14:12]=3'h1
+      TPDX                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[18:16]=3'h1
+      TCKEPRD                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[22:20]=3'h1 (Mirror: 3'h2)
+      TCKESRX                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) |
+            P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) |
+            P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x1, SHU_CKECTRL_TCKEPRD) |
+            P_Fld(0x3, SHU_CKECTRL_TCKESRX));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_0                                     ral_reg_DRAMC_blk_SHU_MISC_0                               -     @5365
+      REQQUE_MAXCNT                                uvm_reg_field                                              ...    RW SHU_MISC_0[3:0]=4'h2
+      DCMDLYREF                                    uvm_reg_field                                              ...    RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4)
+      DAREFEN                                      uvm_reg_field                                              ...    RW SHU_MISC_0[30:30]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) |
+            P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter.
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit.
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ8_0                            -     @7828
+      R_DMRXDVS_UPD_FORCE_CYC_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[14:0]=15'h0063 (Mirror: 15'h0000)
+      R_DMRXDVS_UPD_FORCE_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[15:15]=1'h0
+      R_DMRANK_RXDLY_PIPE_CG_IG_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[19:19]=1'h0
+      R_RMRODTEN_CG_IG_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[20:20]=1'h0
+      R_RMRX_TOPHY_CG_IG_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)
+      R_DMRXDVS_RDSEL_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[22:22]=1'h0
+      R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0            uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[23:23]=1'h0
+      R_DMRXDLY_CG_IG_B0                           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)
+      R_DMDQSIEN_FLAG_SYNC_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[26:26]=1'h0
+      R_DMDQSIEN_FLAG_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[27:27]=1'h0
+      R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0               uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[28:28]=1'h0
+      R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[29:29]=1'h0
+      R_DMRANK_PIPE_CG_IG_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[30:30]=1'h0
+      R_DMRANK_CHG_PIPE_CG_IG_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0063, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+            P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ8_0                            -     @9231
+      R_DMRXDVS_UPD_FORCE_CYC_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[14:0]=15'h0063 (Mirror: 15'h0000)
+      R_DMRXDVS_UPD_FORCE_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[15:15]=1'h0
+      R_DMRANK_RXDLY_PIPE_CG_IG_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[19:19]=1'h0
+      R_RMRODTEN_CG_IG_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[20:20]=1'h0
+      R_RMRX_TOPHY_CG_IG_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)
+      R_DMRXDVS_RDSEL_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[22:22]=1'h0
+      R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1            uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[23:23]=1'h0
+      R_DMRXDLY_CG_IG_B1                           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)
+      R_DMDQSIEN_FLAG_SYNC_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[26:26]=1'h0
+      R_DMDQSIEN_FLAG_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[27:27]=1'h0
+      R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1               uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[28:28]=1'h0
+      R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[29:29]=1'h0
+      R_DMRANK_PIPE_CG_IG_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[30:30]=1'h0
+      R_DMRANK_CHG_PIPE_CG_IG_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0063, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+            P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ5_0                            -     @7728
+      RG_RX_ARDQ_VREF_SEL_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[5:0]=6'h0e
+      RG_RX_ARDQ_VREF_BYPASS_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[6:6]=1'h0
+      RG_ARPI_FB_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[13:8]=6'h00
+      RG_RX_ARDQS0_DQSIEN_DLY_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[18:16]=3'h0
+      RG_RX_ARDQS_DQSIEN_RB_DLY_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[19:19]=1'h0
+      RG_RX_ARDQS0_DVS_DLY_B0                      uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[23:20]=4'h5 (Mirror: 4'h0)
+      RG_RX_ARDQ_FIFO_DQSI_DLY_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[31:29]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x20, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) |
+            P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) |
+            P_Fld(0x5, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0));  //RX_ARDQ_VREF_SEL_B0 is useless
+
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ5_0                            -     @9131
+      RG_RX_ARDQ_VREF_SEL_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[5:0]=6'h0e
+      RG_RX_ARDQ_VREF_BYPASS_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[6:6]=1'h0
+      RG_ARPI_FB_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[13:8]=6'h00
+      RG_RX_ARDQS0_DQSIEN_DLY_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[18:16]=3'h0
+      RG_RX_ARDQS_DQSIEN_RB_DLY_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[19:19]=1'h0
+      RG_RX_ARDQS0_DVS_DLY_B1                      uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[23:20]=4'h5 (Mirror: 4'h0)
+      RG_RX_ARDQ_FIFO_DQSI_DLY_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[31:29]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x20, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) |
+            P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) |
+            P_Fld(0x5, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); //RX_ARDQ_VREF_SEL_B0 is useless
+
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0                    -     @7490
+      RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h9f (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x9f, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+            P_Fld(0x9f, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
+            P_Fld(0x9f, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0                    -     @7504
+      RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h9f (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x9f, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+            P_Fld(0x9f, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+            P_Fld(0x9f, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0                    -     @7518
+      RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h9f (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x9f, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+            P_Fld(0x9f, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+            P_Fld(0x9f, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0                    -     @7532
+      RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h9f (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x9f, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+            P_Fld(0x9f, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+            P_Fld(0x9f, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0                    -     @7546
+      RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h9f (Mirror: 8'h00)
+      RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h9f (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x9f, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+            P_Fld(0x9f, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0                    -     @7556
+      RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h0e5 (Mirror: 9'h000)
+      RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h0e5 (Mirror: 9'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x0e5, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+            P_Fld(0x0e5, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1                    -     @7497
+      RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h9e (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*0x80), P_Fld(0x9e, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+            P_Fld(0x9e, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
+            P_Fld(0x9e, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1                    -     @7511
+      RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h9e (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*0x80), P_Fld(0x9e, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+            P_Fld(0x9e, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+            P_Fld(0x9e, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1                    -     @7525
+      RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h9e (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*0x80), P_Fld(0x9e, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+            P_Fld(0x9e, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+            P_Fld(0x9e, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1                    -     @7539
+      RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h9e (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*0x80), P_Fld(0x9e, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+            P_Fld(0x9e, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+            P_Fld(0x9e, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1                    -     @7551
+      RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h9e (Mirror: 8'h00)
+      RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h9e (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*0x80), P_Fld(0x9e, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+            P_Fld(0x9e, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1                    -     @7561
+      RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h0e4 (Mirror: 9'h000)
+      RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h0e4 (Mirror: 9'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*0x80), P_Fld(0x0e4, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+            P_Fld(0x0e4, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0                    -     @8893
+      RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h9f (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x9f, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+            P_Fld(0x9f, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
+            P_Fld(0x9f, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0                    -     @8907
+      RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h9f (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x9f, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+            P_Fld(0x9f, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+            P_Fld(0x9f, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0                    -     @8921
+      RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h9f (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x9f, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+            P_Fld(0x9f, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+            P_Fld(0x9f, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0                    -     @8935
+      RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h9f (Mirror: 8'h00)
+      RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h9f (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x9f, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+            P_Fld(0x9f, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+            P_Fld(0x9f, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0                    -     @8949
+      RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h9f (Mirror: 8'h00)
+      RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h9f (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x9f, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+            P_Fld(0x9f, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0                    -     @8959
+      RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h0e5 (Mirror: 9'h000)
+      RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h0e5 (Mirror: 9'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x0e5, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+            P_Fld(0x0e5, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1                    -     @8900
+      RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h9e (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*0x80), P_Fld(0x9e, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+            P_Fld(0x9e, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
+            P_Fld(0x9e, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1                    -     @8914
+      RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h9e (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*0x80), P_Fld(0x9e, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+            P_Fld(0x9e, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+            P_Fld(0x9e, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1                    -     @8928
+      RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h9e (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*0x80), P_Fld(0x9e, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+            P_Fld(0x9e, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+            P_Fld(0x9e, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1                    -     @8942
+      RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h9e (Mirror: 8'h00)
+      RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h9e (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*0x80), P_Fld(0x9e, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+            P_Fld(0x9e, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+            P_Fld(0x9e, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1                    -     @8954
+      RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h9e (Mirror: 8'h00)
+      RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h9e (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*0x80), P_Fld(0x9e, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+            P_Fld(0x9e, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1                    -     @8964
+      RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h0e4 (Mirror: 9'h000)
+      RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h0e4 (Mirror: 9'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*0x80), P_Fld(0x0e4, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+            P_Fld(0x0e4, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ9                                         ral_reg_DDRPHY_blk_B0_DQ9                                  -     @7384
+      RG_RX_ARDQ_STBEN_RESETB_B0                   uvm_reg_field                                              ...    RW B0_DQ9[0:0]=1'h0 (Mirror: 1'h1)
+      RG_RX_ARDQS0_STBEN_RESETB_B0                 uvm_reg_field                                              ...    RW B0_DQ9[4:4]=1'h1
+      RG_RX_ARDQS0_DQSIENMODE_B0                   uvm_reg_field                                              ...    RW B0_DQ9[5:5]=1'h0
+      R_DMRXDVS_R_F_DLY_RK_OPT_B0                  uvm_reg_field                                              ...    RW B0_DQ9[6:6]=1'h1
+      R_DMRXFIFO_STBENCMP_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ9[7:7]=1'h0
+      R_IN_GATE_EN_LOW_OPT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[15:8]=8'h00
+      R_DMDQSIEN_VALID_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[18:16]=3'h0
+      R_DMDQSIEN_RDSEL_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[22:20]=3'h0
+      R_DMRXDVS_VALID_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[26:24]=3'h0
+      R_DMRXDVS_RDSEL_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[30:28]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
+            P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
+            P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
+            P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
+            P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
+            P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ9                                         ral_reg_DDRPHY_blk_B1_DQ9                                  -     @8787
+      RG_RX_ARDQ_STBEN_RESETB_B1                   uvm_reg_field                                              ...    RW B1_DQ9[0:0]=1'h0 (Mirror: 1'h1)
+      RG_RX_ARDQS0_STBEN_RESETB_B1                 uvm_reg_field                                              ...    RW B1_DQ9[4:4]=1'h1
+      RG_RX_ARDQS0_DQSIENMODE_B1                   uvm_reg_field                                              ...    RW B1_DQ9[5:5]=1'h0
+      R_DMRXDVS_R_F_DLY_RK_OPT_B1                  uvm_reg_field                                              ...    RW B1_DQ9[6:6]=1'h1
+      R_DMRXFIFO_STBENCMP_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ9[7:7]=1'h0
+      R_IN_GATE_EN_LOW_OPT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[15:8]=8'h00
+      R_DMDQSIEN_VALID_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[18:16]=3'h0
+      R_DMDQSIEN_RDSEL_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[22:20]=3'h0
+      R_DMRXDVS_VALID_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[26:24]=3'h0
+      R_DMRXDVS_RDSEL_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[30:28]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
+            P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
+            P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
+            P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
+            P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
+            P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ9                                         ral_reg_DDRPHY_blk_B0_DQ9                                  -     @7384
+      RG_RX_ARDQ_STBEN_RESETB_B0                   uvm_reg_field                                              ...    RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0)
+      RG_RX_ARDQS0_STBEN_RESETB_B0                 uvm_reg_field                                              ...    RW B0_DQ9[4:4]=1'h1
+      RG_RX_ARDQS0_DQSIENMODE_B0                   uvm_reg_field                                              ...    RW B0_DQ9[5:5]=1'h0
+      R_DMRXDVS_R_F_DLY_RK_OPT_B0                  uvm_reg_field                                              ...    RW B0_DQ9[6:6]=1'h1
+      R_DMRXFIFO_STBENCMP_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ9[7:7]=1'h0
+      R_IN_GATE_EN_LOW_OPT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[15:8]=8'h00
+      R_DMDQSIEN_VALID_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[18:16]=3'h0
+      R_DMDQSIEN_RDSEL_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[22:20]=3'h0
+      R_DMRXDVS_VALID_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[26:24]=3'h0
+      R_DMRXDVS_RDSEL_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[30:28]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
+            P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
+            P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
+            P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
+            P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
+            P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ9                                         ral_reg_DDRPHY_blk_B1_DQ9                                  -     @8787
+      RG_RX_ARDQ_STBEN_RESETB_B1                   uvm_reg_field                                              ...    RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0)
+      RG_RX_ARDQS0_STBEN_RESETB_B1                 uvm_reg_field                                              ...    RW B1_DQ9[4:4]=1'h1
+      RG_RX_ARDQS0_DQSIENMODE_B1                   uvm_reg_field                                              ...    RW B1_DQ9[5:5]=1'h0
+      R_DMRXDVS_R_F_DLY_RK_OPT_B1                  uvm_reg_field                                              ...    RW B1_DQ9[6:6]=1'h1
+      R_DMRXFIFO_STBENCMP_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ9[7:7]=1'h0
+      R_IN_GATE_EN_LOW_OPT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[15:8]=8'h00
+      R_DMDQSIEN_VALID_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[18:16]=3'h0
+      R_DMDQSIEN_RDSEL_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[22:20]=3'h0
+      R_DMRXDVS_VALID_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[26:24]=3'h0
+      R_DMRXDVS_RDSEL_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[30:28]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
+            P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
+            P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
+            P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
+            P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
+            P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ4                                         ral_reg_DDRPHY_blk_B0_DQ4                                  -     @7313
+      RG_RX_ARDQS_EYE_R_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[6:0]=7'h29 (Mirror: 7'h00)
+      RG_RX_ARDQS_EYE_F_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[14:8]=7'h29 (Mirror: 7'h00)
+      RG_RX_ARDQ_EYE_R_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[21:16]=6'h1f (Mirror: 6'h00)
+      RG_RX_ARDQ_EYE_F_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[29:24]=6'h1f (Mirror: 6'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x29, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) |
+            P_Fld(0x29, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x1f, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) |
+            P_Fld(0x1f, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ4                                         ral_reg_DDRPHY_blk_B1_DQ4                                  -     @8716
+      RG_RX_ARDQS_EYE_R_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[6:0]=7'h29 (Mirror: 7'h00)
+      RG_RX_ARDQS_EYE_F_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[14:8]=7'h29 (Mirror: 7'h00)
+      RG_RX_ARDQ_EYE_R_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[21:16]=6'h1f (Mirror: 6'h00)
+      RG_RX_ARDQ_EYE_F_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[29:24]=6'h1f (Mirror: 6'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x29, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) |
+            P_Fld(0x29, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x1f, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) |
+            P_Fld(0x1f, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ5                                         ral_reg_DDRPHY_blk_B0_DQ5                                  -     @7320
+      RG_RX_ARDQ_EYE_VREF_SEL_B0                   uvm_reg_field                                              ...    RW B0_DQ5[13:8]=6'h10
+      RG_RX_ARDQ_VREF_EN_B0                        uvm_reg_field                                              ...    RW B0_DQ5[16:16]=1'h1
+      RG_RX_ARDQ_EYE_VREF_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ5[17:17]=1'h1
+      RG_RX_ARDQ_EYE_SEL_B0                        uvm_reg_field                                              ...    RW B0_DQ5[23:20]=4'h0
+      RG_RX_ARDQ_EYE_EN_B0                         uvm_reg_field                                              ...    RW B0_DQ5[24:24]=1'h1
+      RG_RX_ARDQ_EYE_STBEN_RESETB_B0               uvm_reg_field                                              ...    RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0)
+      RG_RX_ARDQS0_DVS_EN_B0                       uvm_reg_field                                              ...    RW B0_DQ5[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x10, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) |
+            P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) |
+            P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) |
+            P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ5                                         ral_reg_DDRPHY_blk_B1_DQ5                                  -     @8723
+      RG_RX_ARDQ_EYE_VREF_SEL_B1                   uvm_reg_field                                              ...    RW B1_DQ5[13:8]=6'h10
+      RG_RX_ARDQ_VREF_EN_B1                        uvm_reg_field                                              ...    RW B1_DQ5[16:16]=1'h1
+      RG_RX_ARDQ_EYE_VREF_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ5[17:17]=1'h1
+      RG_RX_ARDQ_EYE_SEL_B1                        uvm_reg_field                                              ...    RW B1_DQ5[23:20]=4'h0
+      RG_RX_ARDQ_EYE_EN_B1                         uvm_reg_field                                              ...    RW B1_DQ5[24:24]=1'h1
+      RG_RX_ARDQ_EYE_STBEN_RESETB_B1               uvm_reg_field                                              ...    RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0)
+      RG_RX_ARDQS0_DVS_EN_B1                       uvm_reg_field                                              ...    RW B1_DQ5[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x10, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) |
+            P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) |
+            P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) |
+            P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Enter
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_COMMON0_0                                  ral_reg_DRAMC_blk_SHU_COMMON0_0                            -     @5001
+      FREQDIV4                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[0:0]=1'h1 (Mirror: 1'h0)
+      FDIV2                                        uvm_reg_field                                              ...    RW SHU_COMMON0_0[1:1]=1'h0
+      FREQDIV8                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[2:2]=1'h0
+      DM64BITEN                                    uvm_reg_field                                              ...    RW SHU_COMMON0_0[4:4]=1'h1 (Mirror: 1'h0)
+      DLE256EN                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[5:5]=1'h0
+      LP5BGEN                                      uvm_reg_field                                              ...    RW SHU_COMMON0_0[6:6]=1'h0
+      LP5WCKON                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[7:7]=1'h0
+      CL2                                          uvm_reg_field                                              ...    RW SHU_COMMON0_0[8:8]=1'h0
+      BL2                                          uvm_reg_field                                              ...    RW SHU_COMMON0_0[9:9]=1'h0
+      BL4                                          uvm_reg_field                                              ...    RW SHU_COMMON0_0[10:10]=1'h1 (Mirror: 1'h0)
+      LP5BGOTF                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[11:11]=1'h0
+      BC4OTF                                       uvm_reg_field                                              ...    RW SHU_COMMON0_0[12:12]=1'h1
+      LP5HEFF_MODE                                 uvm_reg_field                                              ...    RW SHU_COMMON0_0[13:13]=1'h0
+      SHU_COMMON0_RSV                              uvm_reg_field                                              ...    RW SHU_COMMON0_0[31:15]=17'h00000
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0, P_Fld(0x1, SHU_COMMON0_FREQDIV4) |
+            P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x0, SHU_COMMON0_FREQDIV8) |
+            P_Fld(0x1, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) |
+            P_Fld(0x0, SHU_COMMON0_LP5BGEN) | P_Fld(0x0, SHU_COMMON0_LP5WCKON) |
+            P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) |
+            P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) |
+            P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x0, SHU_COMMON0_LP5HEFF_MODE) |
+            P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIMING_CONF_0                            ral_reg_DRAMC_blk_SHU_ACTIMING_CONF_0                      -     @5255
+      SCINTV                                       uvm_reg_field                                              ...    RW SHU_ACTIMING_CONF_0[5:0]=6'h26 (Mirror: 6'h2a)
+      TRFCPBIG                                     uvm_reg_field                                              ...    RW SHU_ACTIMING_CONF_0[8:8]=1'h0
+      REFBW_FR                                     uvm_reg_field                                              ...    RW SHU_ACTIMING_CONF_0[25:16]=10'h000
+      TREFBWIG                                     uvm_reg_field                                              ...    RW SHU_ACTIMING_CONF_0[31:31]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF, P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) |
+            P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) |
+            P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_DCM_CTRL0_0                                ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0                          -     @5027
+      DDRPHY_CLK_EN_OPT                            uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[7:7]=1'h1
+      DPHY_CMDDCM_EXTCNT                           uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[11:8]=4'h4
+      DDRPHY_CLK_DYN_GATING_SEL                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[15:12]=4'h5
+      CKE_EXTNONPD_CNT                             uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[19:16]=4'h0
+      FASTWAKE2                                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[29:29]=1'h1 (Mirror: 1'h0)
+      FASTWAKE                                     uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[31:31]=1'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if (fcFOR_CHIP_ID == fcA60868)
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+            P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+            P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) |
+            P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+    #elif (fcFOR_CHIP_ID == fcPetrus)
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+            P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+            P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) |
+            P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_CONF0_0                                    ral_reg_DRAMC_blk_SHU_CONF0_0                              -     @5356
+      DMPGTIM                                      uvm_reg_field                                              ...    RW SHU_CONF0_0[5:0]=6'h3f (Mirror: 6'h08)
+      ADVREFEN                                     uvm_reg_field                                              ...    RW SHU_CONF0_0[6:6]=1'h0
+      ADVPREEN                                     uvm_reg_field                                              ...    RW SHU_CONF0_0[7:7]=1'h1 (Mirror: 1'h0)
+      PBREFEN                                      uvm_reg_field                                              ...    RW SHU_CONF0_0[8:8]=1'h1 (Mirror: 1'h0)
+      REFTHD                                       uvm_reg_field                                              ...    RW SHU_CONF0_0[15:12]=4'h1 (Mirror: 4'h0)
+      REQQUE_DEPTH                                 uvm_reg_field                                              ...    RW SHU_CONF0_0[19:16]=4'h8
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x3f, SHU_CONF0_DMPGTIM) |
+            P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) |
+            P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) |
+            P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MATYPE_0                                   ral_reg_DRAMC_blk_SHU_MATYPE_0                             -     @4996
+      MATYPE                                       uvm_reg_field                                              ...    RW SHU_MATYPE_0[1:0]=2'h2 (Mirror: 2'h0)
+      NORMPOP_LEN                                  uvm_reg_field                                              ...    RW SHU_MATYPE_0[6:4]=3'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE, P_Fld(0x2, SHU_MATYPE_MATYPE) |
+            P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SCHEDULER_0                                ral_reg_DRAMC_blk_SHU_SCHEDULER_0                          -     @5023
+      DUALSCHEN                                    uvm_reg_field                                              ...    RW SHU_SCHEDULER_0[2:2]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DRAMC_REG_SHU_SCHEDULER, 0x1, SHU_SCHEDULER_DUALSCHEN);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    TX_SET0                                        ral_reg_DRAMC_blk_TX_SET0                                  -     @3899
+      TXRANK                                       uvm_reg_field                                              ...    RW TX_SET0[1:0]=2'h0
+      TXRANKFIX                                    uvm_reg_field                                              ...    RW TX_SET0[2:2]=1'h0
+      DDRPHY_COMB_CG_SEL                           uvm_reg_field                                              ...    RW TX_SET0[3:3]=1'h0
+      TX_DQM_DEFAULT                               uvm_reg_field                                              ...    RW TX_SET0[4:4]=1'h1
+      DQBUS_X32                                    uvm_reg_field                                              ...    RW TX_SET0[5:5]=1'h0
+      OE_DOWNGRADE                                 uvm_reg_field                                              ...    RW TX_SET0[6:6]=1'h0
+      DQ16COM1                                     uvm_reg_field                                              ...    RW TX_SET0[21:21]=1'h0
+      WPRE2T                                       uvm_reg_field                                              ...    RW TX_SET0[22:22]=1'h1 (Mirror: 1'h0)
+      DRSCLR_EN                                    uvm_reg_field                                              ...    RW TX_SET0[24:24]=1'h0
+      DRSCLR_RK0_EN                                uvm_reg_field                                              ...    RW TX_SET0[25:25]=1'h0
+      ARPI_CAL_E2OPT                               uvm_reg_field                                              ...    RW TX_SET0[26:26]=1'h0
+      TX_DLY_CAL_E2OPT                             uvm_reg_field                                              ...    RW TX_SET0[27:27]=1'h0
+      DQS_OE_OP1_DIS                               uvm_reg_field                                              ...    RW TX_SET0[28:28]=1'h0
+      DQS_OE_OP2_EN                                uvm_reg_field                                              ...    RW TX_SET0[29:29]=1'h0
+      RK_SCINPUT_OPT                               uvm_reg_field                                              ...    RW TX_SET0[30:30]=1'h0
+      DRAMOEN                                      uvm_reg_field                                              ...    RW TX_SET0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_TX_SET0, P_Fld(0x0, TX_SET0_TXRANK) |
+            P_Fld(0x0, TX_SET0_TXRANKFIX) | P_Fld(0x0, TX_SET0_DDRPHY_COMB_CG_SEL) |
+            P_Fld(0x1, TX_SET0_TX_DQM_DEFAULT) | P_Fld(0x0, TX_SET0_DQBUS_X32) |
+            P_Fld(0x0, TX_SET0_OE_DOWNGRADE) | P_Fld(0x0, TX_SET0_DQ16COM1) |
+            P_Fld(0x1, TX_SET0_WPRE2T) | P_Fld(0x0, TX_SET0_DRSCLR_EN) |
+            P_Fld(0x0, TX_SET0_DRSCLR_RK0_EN) | P_Fld(0x0, TX_SET0_ARPI_CAL_E2OPT) |
+            P_Fld(0x0, TX_SET0_TX_DLY_CAL_E2OPT) | P_Fld(0x0, TX_SET0_DQS_OE_OP1_DIS) |
+            P_Fld(0x0, TX_SET0_DQS_OE_OP2_EN) | P_Fld(0x0, TX_SET0_RK_SCINPUT_OPT) |
+            P_Fld(0x0, TX_SET0_DRAMOEN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_TX_SET0_0                                  ral_reg_DRAMC_blk_SHU_TX_SET0_0                            -     @5306
+      DQOE_CNT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[3:0]=4'h0
+      DQOE_OPT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[4:4]=1'h0
+      TXUPD_SEL                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[7:6]=2'h0
+      TXUPD_W2R_SEL                                uvm_reg_field                                              ...    RW SHU_TX_SET0_0[10:8]=3'h5 (Mirror: 3'h0)
+      WECC_EN                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[11:11]=1'h0
+      DBIWR                                        uvm_reg_field                                              ...    RW SHU_TX_SET0_0[12:12]=1'h0
+      WDATRGO                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[13:13]=1'h0
+      TWPSTEXT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[14:14]=1'h0
+      WPST1P5T                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[15:15]=1'h0
+      TXOEN_AUTOSET_OFFSET                         uvm_reg_field                                              ...    RW SHU_TX_SET0_0[19:16]=4'h3
+      TWCKPST                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[21:20]=2'h1
+      OE_EXT2UI                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[24:22]=3'h1 (Mirror: 3'h0)
+      DQS2DQ_FILT_PITHRD                           uvm_reg_field                                              ...    RW SHU_TX_SET0_0[30:25]=6'h0e
+      TXOEN_AUTOSET_EN                             uvm_reg_field                                              ...    RW SHU_TX_SET0_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if (fcFOR_CHIP_ID == fcA60868)
+    vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+            P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+            P_Fld(0x5, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+            P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+            P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x0, SHU_TX_SET0_WPST1P5T) |
+            P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+            P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+            P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+    #elif (fcFOR_CHIP_ID == fcPetrus)
+    vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+            P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+            P_Fld(0x5, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+            P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+            P_Fld(0x0, SHU_TX_SET0_WPST1P5T) |
+            P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+            P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+            P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_STBCAL1_0                             ral_reg_DDRPHY_blk_MISC_SHU_STBCAL1_0                      -     @12514
+      DLLFRZRFCOPT                                 uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[1:0]=2'h0
+      DLLFRZWROPT                                  uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[5:4]=2'h0
+      r_rstbcnt_latch_opt                          uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[10:8]=3'h0
+      STB_UPDMASK_EN                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[11:11]=1'h1 (Mirror: 1'h0)
+      STB_UPDMASKCYC                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[15:12]=4'h9 (Mirror: 4'h0)
+      DQSINCTL_PRE_SEL                             uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[16:16]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1, P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) |
+            P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) |
+            P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) |
+            P_Fld(0x0, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_STBCAL_0                              ral_reg_DDRPHY_blk_MISC_SHU_STBCAL_0                       -     @12499
+      DMSTBLAT                                     uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[3:0]=4'h0
+      PICGLAT                                      uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[6:4]=3'h1 (Mirror: 3'h0)
+      DQSG_MODE                                    uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[8:8]=1'h1 (Mirror: 1'h0)
+      DQSIEN_PICG_MODE                             uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[9:9]=1'h1 (Mirror: 1'h0)
+      DQSIEN_DQSSTB_MODE                           uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[13:12]=2'h1
+      DQSIEN_BURST_MODE                            uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[14:14]=1'h1
+      DQSIEN_SELPH_FRUN                            uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[15:15]=1'h0
+      STBCALEN                                     uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[16:16]=1'h1 (Mirror: 1'h0)
+      STB_SELPHCALEN                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[17:17]=1'h1 (Mirror: 1'h0)
+      DQSIEN_4TO1_EN                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[20:20]=1'h0
+      DQSIEN_8TO1_EN                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[21:21]=1'h0
+      DQSIEN_16TO1_EN                              uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[22:22]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL, P_Fld(0x0, MISC_SHU_STBCAL_DMSTBLAT) |
+            P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) |
+            P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) |
+            P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) |
+            P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) |
+            P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) |
+            P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RODTENSTB_0                           ral_reg_DDRPHY_blk_MISC_SHU_RODTENSTB_0                    -     @12562
+      RODTENSTB_TRACK_EN                           uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[0:0]=1'h1 (Mirror: 1'h0)
+      RODTEN_P1_ENABLE                             uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[1:1]=1'h0
+      RODTENSTB_4BYTE_EN                           uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[2:2]=1'h0
+      RODTENSTB_TRACK_UDFLWCTRL                    uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[3:3]=1'h1 (Mirror: 1'h0)
+      RODTENSTB_SELPH_MODE                         uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[4:4]=1'h1
+      RODTENSTB_SELPH_BY_BITTIME                   uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[5:5]=1'h0
+      RODTENSTB__UI_OFFSET                         uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[11:8]=4'h4 (Mirror: 4'h0)
+      RODTENSTB_MCK_OFFSET                         uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[15:12]=4'h0
+      RODTENSTB_EXT                                uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[31:16]=16'h0008 (Mirror: 16'h0000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) |
+            P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) |
+            P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) |
+            P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x4, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) |
+            P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RX_SELPH_MODE_0                       ral_reg_DDRPHY_blk_MISC_SHU_RX_SELPH_MODE_0                -     @12751
+      DQSIEN_SELPH_SERMODE                         uvm_reg_field                                              ...    RW MISC_SHU_RX_SELPH_MODE_0[1:0]=2'h2 (Mirror: 2'h0)
+      RODT_SELPH_SERMODE                           uvm_reg_field                                              ...    RW MISC_SHU_RX_SELPH_MODE_0[5:4]=2'h1 (Mirror: 2'h0)
+      RANK_SELPH_SERMODE                           uvm_reg_field                                              ...    RW MISC_SHU_RX_SELPH_MODE_0[7:6]=2'h1 (Mirror: 2'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE, P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) |
+            P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Enter
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Enter
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_HWSET_MR13_0                               ral_reg_DRAMC_blk_SHU_HWSET_MR13_0                         -     @5127
+      HWSET_MR13_MRSMA                             uvm_reg_field                                              ...    RW SHU_HWSET_MR13_0[12:0]=13'h000d
+      HWSET_MR13_OP                                uvm_reg_field                                              ...    RW SHU_HWSET_MR13_0[23:16]=8'h08 (Mirror: 8'hc8)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR13, P_Fld(0x000d, SHU_HWSET_MR13_HWSET_MR13_MRSMA) |
+            P_Fld(0x08, SHU_HWSET_MR13_HWSET_MR13_OP));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_HWSET_VRCG_0                               ral_reg_DRAMC_blk_SHU_HWSET_VRCG_0                         -     @5132
+      HWSET_VRCG_MRSMA                             uvm_reg_field                                              ...    RW SHU_HWSET_VRCG_0[12:0]=13'h000d
+      HWSET_VRCG_OP                                uvm_reg_field                                              ...    RW SHU_HWSET_VRCG_0[23:16]=8'h00 (Mirror: 8'hc0)
+      VRCGDIS_PRDCNT                               uvm_reg_field                                              ...    RW SHU_HWSET_VRCG_0[31:24]=8'h00
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_VRCG, P_Fld(0x000d, SHU_HWSET_VRCG_HWSET_VRCG_MRSMA) |
+            P_Fld(0x00, SHU_HWSET_VRCG_HWSET_VRCG_OP) | P_Fld(0x00, SHU_HWSET_VRCG_VRCGDIS_PRDCNT));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Enter
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_FREQ_RATIO_SET0_0                          ral_reg_DRAMC_blk_SHU_FREQ_RATIO_SET0_0                    -     @5384
+      tDQSCK_JUMP_RATIO3                           uvm_reg_field                                              ...    RW SHU_FREQ_RATIO_SET0_0[7:0]=8'h20 (Mirror: 8'h00)
+      tDQSCK_JUMP_RATIO2                           uvm_reg_field                                              ...    RW SHU_FREQ_RATIO_SET0_0[15:8]=8'h2b (Mirror: 8'h00)
+      tDQSCK_JUMP_RATIO1                           uvm_reg_field                                              ...    RW SHU_FREQ_RATIO_SET0_0[23:16]=8'h18 (Mirror: 8'h00)
+      tDQSCK_JUMP_RATIO0                           uvm_reg_field                                              ...    RW SHU_FREQ_RATIO_SET0_0[31:24]=8'h20 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) |
+            P_Fld(0x2b, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x18, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) |
+            P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Enter
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_DVFSDLL_0                             ral_reg_DDRPHY_blk_MISC_SHU_DVFSDLL_0                      -     @12523
+      r_bypass_1st_dll                             uvm_reg_field                                              ...    RW MISC_SHU_DVFSDLL_0[0:0]=1'h1 (Mirror: 1'h0)
+      r_bypass_2nd_dll                             uvm_reg_field                                              ...    RW MISC_SHU_DVFSDLL_0[1:1]=1'h0
+      r_dll_idle                                   uvm_reg_field                                              ...    RW MISC_SHU_DVFSDLL_0[10:4]=7'h5a (Mirror: 7'h46)
+      r_2nd_dll_idle                               uvm_reg_field                                              ...    RW MISC_SHU_DVFSDLL_0[22:16]=7'h5a
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x1, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) |
+            P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) |
+            P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Exit
+        mcDELAY_US(1);
+
+        mcDELAY_US(1);
+
+    /*TINFO=---===BROADCAST OFF!===---*/
+         DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Enter
+        mcDELAY_US(1);
+
+        mcDELAY_US(1);
+
+    /*TINFO=---===BROADCAST ON!===---*/
+         DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Exit
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_DQSOSCR_0                                  ral_reg_DRAMC_blk_SHU_DQSOSCR_0                            -     @5338
+      DQSOSCRCNT                                   uvm_reg_field                                              ...    RW SHU_DQSOSCR_0[7:0]=8'h08 (Mirror: 8'h00)
+      DQSOSC_ADV_SEL                               uvm_reg_field                                              ...    RW SHU_DQSOSCR_0[9:8]=2'h0
+      DQSOSC_DRS_ADV_SEL                           uvm_reg_field                                              ...    RW SHU_DQSOSCR_0[11:10]=2'h0
+      DQSOSC_DELTA                                 uvm_reg_field                                              ...    RW SHU_DQSOSCR_0[31:16]=16'hffff
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR, P_Fld(0x08, SHU_DQSOSCR_DQSOSCRCNT) |
+            P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) |
+            P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_DQSOSC_SET0_0                              ral_reg_DRAMC_blk_SHU_DQSOSC_SET0_0                        -     @5332
+      DQSOSCENDIS                                  uvm_reg_field                                              ...    RW SHU_DQSOSC_SET0_0[0:0]=1'h1
+      DQSOSC_PRDCNT                                uvm_reg_field                                              ...    RW SHU_DQSOSC_SET0_0[13:4]=10'h011 (Mirror: 10'h00f)
+      DQSOSCENCNT                                  uvm_reg_field                                              ...    RW SHU_DQSOSC_SET0_0[31:16]=16'h0002
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0, P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) |
+            P_Fld(0x011, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQSOSC_0_0                               ral_reg_DRAMC_blk_SHURK_DQSOSC_0_0                         -     @4906
+      DQSOSC_BASE_RK0                              uvm_reg_field                                              ...    RW SHURK_DQSOSC_0_0[15:0]=16'h0866 (Mirror: 16'h0000)
+      DQSOSC_BASE_RK0_B1                           uvm_reg_field                                              ...    RW SHURK_DQSOSC_0_0[31:16]=16'h0866 (Mirror: 16'h0000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC, P_Fld(0x0866, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
+            P_Fld(0x0866, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQSOSC_0_1                               ral_reg_DRAMC_blk_SHURK_DQSOSC_0_1                         -     @4911
+      DQSOSC_BASE_RK0                              uvm_reg_field                                              ...    RW SHURK_DQSOSC_0_1[15:0]=16'h0399 (Mirror: 16'h0000)
+      DQSOSC_BASE_RK0_B1                           uvm_reg_field                                              ...    RW SHURK_DQSOSC_0_1[31:16]=16'h0399 (Mirror: 16'h0000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*0x200), P_Fld(0x0399, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
+            P_Fld(0x0399, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQSOSC_THRD_0_0                          ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_0                    -     @4916
+      DQSOSCTHRD_INC                               uvm_reg_field                                              ...    RW SHURK_DQSOSC_THRD_0_0[11:0]=12'h0ac (Mirror: 12'h001)
+      DQSOSCTHRD_DEC                               uvm_reg_field                                              ...    RW SHURK_DQSOSC_THRD_0_0[27:16]=12'h072 (Mirror: 12'h001)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD, P_Fld(0x0ac, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
+            P_Fld(0x072, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQSOSC_THRD_0_1                          ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_1                    -     @4921
+      DQSOSCTHRD_INC                               uvm_reg_field                                              ...    RW SHURK_DQSOSC_THRD_0_1[11:0]=12'h01f (Mirror: 12'h001)
+      DQSOSCTHRD_DEC                               uvm_reg_field                                              ...    RW SHURK_DQSOSC_THRD_0_1[27:16]=12'h015 (Mirror: 12'h001)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*0x200), P_Fld(0x01f, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
+            P_Fld(0x015, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_TX_SET0_0                                  ral_reg_DRAMC_blk_SHU_TX_SET0_0                            -     @5306
+      DQOE_CNT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[3:0]=4'h0
+      DQOE_OPT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[4:4]=1'h0
+      TXUPD_SEL                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[7:6]=2'h0
+      TXUPD_W2R_SEL                                uvm_reg_field                                              ...    RW SHU_TX_SET0_0[10:8]=3'h5
+      WECC_EN                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[11:11]=1'h0
+      DBIWR                                        uvm_reg_field                                              ...    RW SHU_TX_SET0_0[12:12]=1'h0
+      WDATRGO                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[13:13]=1'h0
+      TWPSTEXT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[14:14]=1'h0
+      WPST1P5T                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[15:15]=1'h0
+      TXOEN_AUTOSET_OFFSET                         uvm_reg_field                                              ...    RW SHU_TX_SET0_0[19:16]=4'h3
+      TWCKPST                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[21:20]=2'h1
+      OE_EXT2UI                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[24:22]=3'h1
+      DQS2DQ_FILT_PITHRD                           uvm_reg_field                                              ...    RW SHU_TX_SET0_0[30:25]=6'h08 (Mirror: 6'h0e)
+      TXOEN_AUTOSET_EN                             uvm_reg_field                                              ...    RW SHU_TX_SET0_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    #if (fcFOR_CHIP_ID == fcA60868)
+    vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+            P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+            P_Fld(0x5, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+            P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+            P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x0, SHU_TX_SET0_WPST1P5T) |
+            P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+            P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x08, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+            P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+    #elif (fcFOR_CHIP_ID == fcPetrus)
+    vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+            P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+            P_Fld(0x5, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+            P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+            P_Fld(0x0, SHU_TX_SET0_WPST1P5T) |
+            P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+            P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x08, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+            P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+    #endif
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ZQ_SET0_0                                  ral_reg_DRAMC_blk_SHU_ZQ_SET0_0                            -     @5351
+      ZQCSCNT                                      uvm_reg_field                                              ...    RW SHU_ZQ_SET0_0[15:0]=16'h0005 (Mirror: 16'h0000)
+      TZQLAT                                       uvm_reg_field                                              ...    RW SHU_ZQ_SET0_0[31:27]=5'h1b
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) |
+            P_Fld(0x1b, SHU_ZQ_SET0_TZQLAT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_HMR4_DVFS_CTRL0_0                          ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0                    -     @5036
+      FSPCHG_PRDCNT                                uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h32
+      REFRCNT                                      uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h005 (Mirror: 12'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x32, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+            P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ8_0                            -     @7828
+      R_DMRXDVS_UPD_FORCE_CYC_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[14:0]=15'h0063
+      R_DMRXDVS_UPD_FORCE_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[15:15]=1'h1 (Mirror: 1'h0)
+      R_DMRANK_RXDLY_PIPE_CG_IG_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[19:19]=1'h0
+      R_RMRODTEN_CG_IG_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[20:20]=1'h0
+      R_RMRX_TOPHY_CG_IG_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[21:21]=1'h1
+      R_DMRXDVS_RDSEL_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[22:22]=1'h0
+      R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0            uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[23:23]=1'h0
+      R_DMRXDLY_CG_IG_B0                           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[24:24]=1'h1
+      R_DMDQSIEN_FLAG_SYNC_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[26:26]=1'h0
+      R_DMDQSIEN_FLAG_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[27:27]=1'h0
+      R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0               uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[28:28]=1'h0
+      R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[29:29]=1'h0
+      R_DMRANK_PIPE_CG_IG_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[30:30]=1'h0
+      R_DMRANK_CHG_PIPE_CG_IG_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0063, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+            P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+            P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ8_0                            -     @9231
+      R_DMRXDVS_UPD_FORCE_CYC_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[14:0]=15'h0063
+      R_DMRXDVS_UPD_FORCE_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[15:15]=1'h1 (Mirror: 1'h0)
+      R_DMRANK_RXDLY_PIPE_CG_IG_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[19:19]=1'h0
+      R_RMRODTEN_CG_IG_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[20:20]=1'h0
+      R_RMRX_TOPHY_CG_IG_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[21:21]=1'h1
+      R_DMRXDVS_RDSEL_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[22:22]=1'h0
+      R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1            uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[23:23]=1'h0
+      R_DMRXDLY_CG_IG_B1                           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[24:24]=1'h1
+      R_DMDQSIEN_FLAG_SYNC_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[26:26]=1'h0
+      R_DMDQSIEN_FLAG_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[27:27]=1'h0
+      R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1               uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[28:28]=1'h0
+      R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[29:29]=1'h0
+      R_DMRANK_PIPE_CG_IG_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[30:30]=1'h0
+      R_DMRANK_CHG_PIPE_CG_IG_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0063, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+            P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+            P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ7_0                            -     @7808
+      R_DMRANKRXDVS_B0                             uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[3:0]=4'h0
+      R_DMDQMDBI_EYE_SHU_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[6:6]=1'h0
+      R_DMDQMDBI_SHU_B0                            uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[7:7]=1'h0
+      R_DMRXDVS_DQM_FLAGSEL_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[11:8]=4'hd (Mirror: 4'h0)
+      R_DMRXDVS_PBYTE_FLAG_OPT_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[12:12]=1'h0
+      R_DMRXDVS_PBYTE_DQM_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[13:13]=1'h0
+      R_DMRXTRACK_DQM_EN_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[14:14]=1'h0
+      R_DMRODTEN_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[15:15]=1'h1
+      R_DMARPI_CG_FB2DLL_DCM_EN_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[16:16]=1'h0
+      R_DMTX_ARPI_CG_DQ_NEW_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[17:17]=1'h0
+      R_DMTX_ARPI_CG_DQS_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[18:18]=1'h0
+      R_DMTX_ARPI_CG_DQM_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[19:19]=1'h0
+      R_LP4Y_SDN_MODE_DQS0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[20:20]=1'h0
+      R_DMRXRANK_DQ_EN_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[24:24]=1'h1
+      R_DMRXRANK_DQ_LAT_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[27:25]=3'h1
+      R_DMRXRANK_DQS_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[28:28]=1'h1
+      R_DMRXRANK_DQS_LAT_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[31:29]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+            P_Fld(0xd, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ7_0                            -     @9211
+      R_DMRANKRXDVS_B1                             uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[3:0]=4'h0
+      R_DMDQMDBI_EYE_SHU_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[6:6]=1'h0
+      R_DMDQMDBI_SHU_B1                            uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[7:7]=1'h0
+      R_DMRXDVS_DQM_FLAGSEL_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[11:8]=4'hd (Mirror: 4'h0)
+      R_DMRXDVS_PBYTE_FLAG_OPT_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[12:12]=1'h0
+      R_DMRXDVS_PBYTE_DQM_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[13:13]=1'h0
+      R_DMRXTRACK_DQM_EN_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[14:14]=1'h0
+      R_DMRODTEN_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[15:15]=1'h1
+      R_DMARPI_CG_FB2DLL_DCM_EN_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[16:16]=1'h0
+      R_DMTX_ARPI_CG_DQ_NEW_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[17:17]=1'h0
+      R_DMTX_ARPI_CG_DQS_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[18:18]=1'h0
+      R_DMTX_ARPI_CG_DQM_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[19:19]=1'h0
+      R_LP4Y_SDN_MODE_DQS1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[20:20]=1'h0
+      R_DMRXRANK_DQ_EN_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[24:24]=1'h1
+      R_DMRXRANK_DQ_LAT_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[27:25]=3'h1
+      R_DMRXRANK_DQS_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[28:28]=1'h1
+      R_DMRXRANK_DQS_LAT_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[31:29]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+            P_Fld(0xd, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ11_0                                  ral_reg_DDRPHY_blk_SHU_B0_DQ11_0                           -     @7794
+      RG_RX_ARDQ_RANK_SEL_SER_EN_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[0:0]=1'h0
+      RG_RX_ARDQ_RANK_SEL_LAT_EN_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[1:1]=1'h0
+      RG_RX_ARDQ_OFFSETC_LAT_EN_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[2:2]=1'h0
+      RG_RX_ARDQ_OFFSETC_EN_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[3:3]=1'h0
+      RG_RX_ARDQ_OFFSETC_BIAS_EN_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[4:4]=1'h0
+      RG_RX_ARDQ_FRATE_EN_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[5:5]=1'h0
+      RG_RX_ARDQ_CDR_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[6:6]=1'h0
+      RG_RX_ARDQ_DVS_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[7:7]=1'h1 (Mirror: 1'h0)
+      RG_RX_ARDQ_DVS_DLY_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[11:8]=4'h0
+      RG_RX_ARDQ_DES_MODE_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[17:16]=2'h2
+      RG_RX_ARDQ_BW_SEL_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[19:18]=2'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11, P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) |
+            P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ11_0                                  ral_reg_DDRPHY_blk_SHU_B1_DQ11_0                           -     @9197
+      RG_RX_ARDQ_RANK_SEL_SER_EN_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[0:0]=1'h0
+      RG_RX_ARDQ_RANK_SEL_LAT_EN_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[1:1]=1'h0
+      RG_RX_ARDQ_OFFSETC_LAT_EN_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[2:2]=1'h0
+      RG_RX_ARDQ_OFFSETC_EN_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[3:3]=1'h0
+      RG_RX_ARDQ_OFFSETC_BIAS_EN_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[4:4]=1'h0
+      RG_RX_ARDQ_FRATE_EN_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[5:5]=1'h0
+      RG_RX_ARDQ_CDR_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[6:6]=1'h0
+      RG_RX_ARDQ_DVS_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[7:7]=1'h1 (Mirror: 1'h0)
+      RG_RX_ARDQ_DVS_DLY_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[11:8]=4'h0
+      RG_RX_ARDQ_DES_MODE_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[17:16]=2'h2
+      RG_RX_ARDQ_BW_SEL_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[19:18]=2'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11, P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) |
+            P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1));
+    //    Exit body
+}
+
+#if 0
+void CInit_golden_mini_freq_related_vseq_LP4_1600_SHU1(DRAMC_CTX_T *p)
+{
+//    Enter body
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, IMP golden setting Enter:
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x09, SHU_MISC_DRVING1_DQDRVN2) |
+        P_Fld(0x07, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN1) |
+        P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN2) |
+        P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) |
+        P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMPCAL_HW));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x09, SHU_MISC_DRVING2_CMDDRVN1) |
+        P_Fld(0x07, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x09, SHU_MISC_DRVING2_CMDDRVN2) |
+        P_Fld(0x07, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x09, SHU_MISC_DRVING2_DQDRVN1) |
+        P_Fld(0x07, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x1, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) |
+        P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) |
+        P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) |
+        P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) |
+        P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) |
+        P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) |
+        P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x07, SHU_MISC_DRVING6_IMP_TXDLY_CMD) |
+        P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) |
+        P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) |
+        P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) |
+        P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT));
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, IMP golden setting Exit:
+    mcDELAY_US(1);
+
+    mcDELAY_US(1);
+
+     DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA) |
+        P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA) | P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA) |
+        P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CA_CA) |
+        P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CLK_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA) |
+        P_Fld(0x1, SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0) |
+        P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_MCTL_B0) | P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0) |
+        P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B0) |
+        P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1) |
+        P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_MCTL_B1) | P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1) |
+        P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B1) |
+        P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA) | P_Fld(0x1, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA) |
+        P_Fld(0x15, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA) |
+        P_Fld(0x3, SHU_CA_CMD1_RG_ARPI_MIDPI_CAP_SEL_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_VTH_SEL_CA) |
+        P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_8PHASE_XLATCH_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B0) | P_Fld(0x1, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0) |
+        P_Fld(0x0e, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0) |
+        P_Fld(0x3, SHU_B0_DQ1_RG_ARPI_MIDPI_CAP_SEL_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_VTH_SEL_B0) |
+        P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1) | P_Fld(0x1, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1) |
+        P_Fld(0x0a, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1) |
+        P_Fld(0x3, SHU_B1_DQ1_RG_ARPI_MIDPI_CAP_SEL_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_VTH_SEL_B1) |
+        P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD14+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA) |
+        P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_AUX_SER_MODE_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_PRE_DATA_SEL_CA) |
+        P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_SWAP_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA) |
+        P_Fld(0x50, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ10+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ14+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0) |
+        P_Fld(0x1, SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B0) |
+        P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B0) |
+        P_Fld(0x1, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0) | P_Fld(0x00, SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ10+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ14+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1) |
+        P_Fld(0x1, SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B1) |
+        P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B1) |
+        P_Fld(0x1, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1) | P_Fld(0x00, SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_CA) |
+        P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_EN_CA) |
+        P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_CA) |
+        P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GAIN_BOOST_CA) | P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_GAIN_CA) |
+        P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_DIV_EN_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA) |
+        P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B0) |
+        P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_EN_B0) |
+        P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B0) |
+        P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GAIN_BOOST_B0) | P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_GAIN_B0) |
+        P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_DIV_EN_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0) |
+        P_Fld(0x1, SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B1) |
+        P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_EN_B1) |
+        P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B1) |
+        P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GAIN_BOOST_B1) | P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_GAIN_B1) |
+        P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_DIV_EN_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1) |
+        P_Fld(0x1, SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x894a, SHU_PLL0_RG_RPHYPLL_TOP_REV) |
+        P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_SER_MODE) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_PREDIV_EN) |
+        P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_EN) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_TSHIFT) |
+        P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_DIV) | P_Fld(0x00, SHU_PLL0_RG_RPLLGP_DLINE_MON_DLY) |
+        P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_EN));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_PLL1_RG_RPHYPLLGP_CK_SEL) |
+        P_Fld(0x0, SHU_PLL1_RG_RPLLGP_PLLCK_VSEL) | P_Fld(0x1, SHU_PLL1_R_SHU_AUTO_PLL_MUX) |
+        P_Fld(0x0, SHU_PLL1_RG_RPHYPLL_DDR400_EN));
+vIO32WriteFldAlign(DDRPHY_REG_SHU_PLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x1, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU);
+vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00fe, SHU_PHYPLL0_RG_RPHYPLL_RESERVED) |
+        P_Fld(0x2, SHU_PHYPLL0_RG_RPHYPLL_FS) | P_Fld(0x7, SHU_PHYPLL0_RG_RPHYPLL_BW) |
+        P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_ICHP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_IBIAS) |
+        P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BLP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BR) |
+        P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BP));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN) |
+        P_Fld(0x1, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_PHYPLL2_RG_RPHYPLL_POSDIV) |
+        P_Fld(0x1, SHU_PHYPLL2_RG_RPHYPLL_PREDIV));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL) |
+        P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_GLITCH_FREE_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_LVR_REFSEL) |
+        P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_DIV3_EN) | P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_FS_EN) |
+        P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_FBKSEL) | P_Fld(0x2, SHU_PHYPLL3_RG_RPHYPLL_RST_DLY) |
+        P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONREF_EN) |
+        P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONVC_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00fe, SHU_CLRPLL0_RG_RCLRPLL_RESERVED) |
+        P_Fld(0x2, SHU_CLRPLL0_RG_RCLRPLL_FS) | P_Fld(0x7, SHU_CLRPLL0_RG_RCLRPLL_BW) |
+        P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_ICHP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_IBIAS) |
+        P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BLP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BR) |
+        P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BP));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN) |
+        P_Fld(0x1, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CLRPLL2_RG_RCLRPLL_POSDIV) |
+        P_Fld(0x1, SHU_CLRPLL2_RG_RCLRPLL_PREDIV));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_CA_CMD5_RG_RX_ARCMD_VREF_SEL) |
+        P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS) | P_Fld(0x00, SHU_CA_CMD5_RG_ARPI_FB_CA) |
+        P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_RB_DLY) |
+        P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_FIFO_DQSI_DLY));
+vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD9+(1*SHU_GRP_DDRPHY_OFFSET), 0x716c0638, SHU_CA_CMD9_RG_ARPI_RESERVE_CA);
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_MIDPI_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_MIDPI_CTRL_MIDPI_ENABLE) |
+        P_Fld(0x1, MISC_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE));
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT) |
+        P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT) | P_Fld(0x0, MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT) |
+        P_Fld(0x0, MISC_SHU_RDAT1_RDATDIV2) | P_Fld(0x1, MISC_SHU_RDAT1_RDATDIV4));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0) |
+        P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0) |
+        P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0) |
+        P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1) |
+        P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1) |
+        P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1) |
+        P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1));
+vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9+(1*SHU_GRP_DDRPHY_OFFSET), 0xd4f91bb7, SHU_B0_DQ9_RG_ARPI_RESERVE_B0);
+vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9+(1*SHU_GRP_DDRPHY_OFFSET), 0x53b8f566, SHU_B1_DQ9_RG_ARPI_RESERVE_B1);
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD7_R_DMRANKRXDVS_CA) |
+        P_Fld(0x0, SHU_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA) | P_Fld(0x0, SHU_CA_CMD7_R_DMRODTEN_CA) |
+        P_Fld(0x0, SHU_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA) | P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW) |
+        P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW) | P_Fld(0x0, SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK) |
+        P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_LAT) |
+        P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_LAT));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_AD_ARFB_CK_EN_CA) |
+        P_Fld(0x3, SHU_CA_DLL1_RG_ARDLL_DIV_MODE_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA) |
+        P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_TRACKING_CA_EN_CA) |
+        P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA) |
+        P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PS_EN_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA) |
+        P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDIV_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) |
+        P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA) |
+        P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_DIV_MCTL_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PGAIN_CA) |
+        P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA));
+vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_DLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x15ba2788, SHU_CA_DLL2_RG_ARCMD_REV);
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B0) |
+        P_Fld(0x3, SHU_B0_DLL1_RG_ARDLL_DIV_MODE_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0) |
+        P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0) |
+        P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0) |
+        P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PS_EN_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0) |
+        P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDIV_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0) |
+        P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0) |
+        P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_DIV_MCTL_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PGAIN_B0) |
+        P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B1) |
+        P_Fld(0x3, SHU_B1_DLL1_RG_ARDLL_DIV_MODE_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1) |
+        P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1) |
+        P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1) |
+        P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PS_EN_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1) |
+        P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDIV_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1) |
+        P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1) |
+        P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_DIV_MCTL_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PGAIN_B1) |
+        P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1));
+vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x0cebb192, SHU_B0_DLL2_RG_ARDQ_REV_B0);
+vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x4b99094e, SHU_B1_DLL2_RG_ARDQ_REV_B1);
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_FRATE_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_CDR_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_DLY_CA) |
+        P_Fld(0x2, SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) |
+        P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) |
+        P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA) |
+        P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA) |
+        P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA) |
+        P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA) |
+        P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU) |
+        P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0) |
+        P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0) |
+        P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0) |
+        P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU) |
+        P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1) |
+        P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1) |
+        P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1) |
+        P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU) |
+        P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1));
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Exit
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD6+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA) |
+        P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA) | P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA) |
+        P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CA_CA) |
+        P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CLK_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA) |
+        P_Fld(0x1, SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ6+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0) |
+        P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_MCTL_B0) | P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0) |
+        P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B0) |
+        P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ6+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1) |
+        P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_MCTL_B1) | P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1) |
+        P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B1) |
+        P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA) | P_Fld(0x1, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA) |
+        P_Fld(0x03, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA) |
+        P_Fld(0x3, SHU_CA_CMD1_RG_ARPI_MIDPI_CAP_SEL_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_VTH_SEL_CA) |
+        P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_8PHASE_XLATCH_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B0) | P_Fld(0x1, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0) |
+        P_Fld(0x05, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0) |
+        P_Fld(0x3, SHU_B0_DQ1_RG_ARPI_MIDPI_CAP_SEL_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_VTH_SEL_B0) |
+        P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1) | P_Fld(0x1, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1) |
+        P_Fld(0x07, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1) |
+        P_Fld(0x3, SHU_B1_DQ1_RG_ARPI_MIDPI_CAP_SEL_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_VTH_SEL_B1) |
+        P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD14+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA) |
+        P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_AUX_SER_MODE_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_PRE_DATA_SEL_CA) |
+        P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_SWAP_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA) |
+        P_Fld(0x50, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ10+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ14+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0) |
+        P_Fld(0x1, SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B0) |
+        P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B0) |
+        P_Fld(0x1, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0) | P_Fld(0x00, SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ10+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ14+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1) |
+        P_Fld(0x1, SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B1) |
+        P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B1) |
+        P_Fld(0x1, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1) | P_Fld(0x00, SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_CA) |
+        P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_EN_CA) |
+        P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_CA) |
+        P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GAIN_BOOST_CA) | P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_GAIN_CA) |
+        P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_DIV_EN_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA) |
+        P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B0) |
+        P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_EN_B0) |
+        P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B0) |
+        P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GAIN_BOOST_B0) | P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_GAIN_B0) |
+        P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_DIV_EN_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0) |
+        P_Fld(0x1, SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B1) |
+        P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_EN_B1) |
+        P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B1) |
+        P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GAIN_BOOST_B1) | P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_GAIN_B1) |
+        P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_DIV_EN_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1) |
+        P_Fld(0x1, SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0825, SHU_PLL0_RG_RPHYPLL_TOP_REV) |
+        P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_SER_MODE) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_PREDIV_EN) |
+        P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_EN) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_TSHIFT) |
+        P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_DIV) | P_Fld(0x00, SHU_PLL0_RG_RPLLGP_DLINE_MON_DLY) |
+        P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_EN));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_PLL1_RG_RPHYPLLGP_CK_SEL) |
+        P_Fld(0x0, SHU_PLL1_RG_RPLLGP_PLLCK_VSEL) | P_Fld(0x1, SHU_PLL1_R_SHU_AUTO_PLL_MUX) |
+        P_Fld(0x0, SHU_PLL1_RG_RPHYPLL_DDR400_EN));
+vIO32WriteFldAlign(DDRPHY_REG_SHU_PLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x1, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU);
+vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00fe, SHU_PHYPLL0_RG_RPHYPLL_RESERVED) |
+        P_Fld(0x2, SHU_PHYPLL0_RG_RPHYPLL_FS) | P_Fld(0x7, SHU_PHYPLL0_RG_RPHYPLL_BW) |
+        P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_ICHP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_IBIAS) |
+        P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BLP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BR) |
+        P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BP));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN) |
+        P_Fld(0x1, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_PHYPLL2_RG_RPHYPLL_POSDIV) |
+        P_Fld(0x1, SHU_PHYPLL2_RG_RPHYPLL_PREDIV));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL3+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL) |
+        P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_GLITCH_FREE_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_LVR_REFSEL) |
+        P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_DIV3_EN) | P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_FS_EN) |
+        P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_FBKSEL) | P_Fld(0x2, SHU_PHYPLL3_RG_RPHYPLL_RST_DLY) |
+        P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONREF_EN) |
+        P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONVC_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00fe, SHU_CLRPLL0_RG_RCLRPLL_RESERVED) |
+        P_Fld(0x2, SHU_CLRPLL0_RG_RCLRPLL_FS) | P_Fld(0x7, SHU_CLRPLL0_RG_RCLRPLL_BW) |
+        P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_ICHP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_IBIAS) |
+        P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BLP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BR) |
+        P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BP));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN) |
+        P_Fld(0x1, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CLRPLL2_RG_RCLRPLL_POSDIV) |
+        P_Fld(0x1, SHU_CLRPLL2_RG_RCLRPLL_PREDIV));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD5+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_CA_CMD5_RG_RX_ARCMD_VREF_SEL) |
+        P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS) | P_Fld(0x00, SHU_CA_CMD5_RG_ARPI_FB_CA) |
+        P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_RB_DLY) |
+        P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_FIFO_DQSI_DLY));
+vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD9+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x4103911e, SHU_CA_CMD9_RG_ARPI_RESERVE_CA);
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_MIDPI_CTRL+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, MISC_SHU_MIDPI_CTRL_MIDPI_ENABLE) |
+        P_Fld(0x1, MISC_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE));
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT) |
+        P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT) | P_Fld(0x0, MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT) |
+        P_Fld(0x0, MISC_SHU_RDAT1_RDATDIV2) | P_Fld(0x1, MISC_SHU_RDAT1_RDATDIV4));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0) |
+        P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0) |
+        P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0) |
+        P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1) |
+        P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1) |
+        P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1) |
+        P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1));
+vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0xfa9fd5c2, SHU_B0_DQ9_RG_ARPI_RESERVE_B0);
+vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x6b9a7ebf, SHU_B1_DQ9_RG_ARPI_RESERVE_B1);
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD7+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_CMD7_R_DMRANKRXDVS_CA) |
+        P_Fld(0x0, SHU_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA) | P_Fld(0x0, SHU_CA_CMD7_R_DMRODTEN_CA) |
+        P_Fld(0x0, SHU_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA) | P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW) |
+        P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW) | P_Fld(0x0, SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK) |
+        P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_LAT) |
+        P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_LAT));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_AD_ARFB_CK_EN_CA) |
+        P_Fld(0x3, SHU_CA_DLL1_RG_ARDLL_DIV_MODE_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA) |
+        P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_TRACKING_CA_EN_CA) |
+        P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA) |
+        P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PS_EN_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA) |
+        P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDIV_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) |
+        P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA) |
+        P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_DIV_MCTL_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PGAIN_CA) |
+        P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA));
+vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_DLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x1793f0fe, SHU_CA_DLL2_RG_ARCMD_REV);
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B0) |
+        P_Fld(0x3, SHU_B0_DLL1_RG_ARDLL_DIV_MODE_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0) |
+        P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0) |
+        P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0) |
+        P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PS_EN_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0) |
+        P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDIV_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0) |
+        P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0) |
+        P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_DIV_MCTL_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PGAIN_B0) |
+        P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B1) |
+        P_Fld(0x3, SHU_B1_DLL1_RG_ARDLL_DIV_MODE_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1) |
+        P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1) |
+        P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1) |
+        P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PS_EN_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1) |
+        P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDIV_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1) |
+        P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1) |
+        P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_DIV_MCTL_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PGAIN_B1) |
+        P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1));
+vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0xb357f9bf, SHU_B0_DLL2_RG_ARDQ_REV_B0);
+vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x7e18d6d9, SHU_B1_DLL2_RG_ARDQ_REV_B1);
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD11+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_FRATE_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_CDR_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_DLY_CA) |
+        P_Fld(0x2, SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) |
+        P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) |
+        P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA) |
+        P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA) |
+        P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA) |
+        P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA) |
+        P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU) |
+        P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) |
+        P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0) |
+        P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0) |
+        P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0) |
+        P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU) |
+        P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1) |
+        P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1) |
+        P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1) |
+        P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU) |
+        P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1));
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Exit
+    mcDELAY_US(1);
+
+    mcDELAY_US(1);
+
+     DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter
+vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN) |
+        P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN) | P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN) |
+        P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN) | P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA) |
+        P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0) |
+        P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0) |
+        P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0) |
+        P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1) |
+        P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1) |
+        P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1) |
+        P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1));
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, TX_MODE_SET related setting Enter
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0) |
+        P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0) |
+        P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0) |
+        P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1) |
+        P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1) |
+        P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1) |
+        P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1));
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, RX data path setting Enter:
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x10, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) |
+        P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) |
+        P_Fld(0xff0, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x010, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS));
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x10, MISC_SHU_RDAT_DATLAT) |
+        P_Fld(0x0f, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0f, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) |
+        P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) |
+        P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) |
+        P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x2, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) |
+        P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) |
+        P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x3, MISC_SHU_RANKCTL_RANKINCTL) |
+        P_Fld(0x3, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL_PHY));
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
+        P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
+vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*SHU_GRP_DDRPHY_OFFSET), 0x5, MISC_SHU_RK_DQSCTL_DQSINCTL);
+vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), 0x5, MISC_SHU_RK_DQSCTL_DQSINCTL);
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xa, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+        P_Fld(0xc, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+        P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), 0x19, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+        P_Fld(0xf, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+        P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), 0x05, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xa, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+        P_Fld(0xc, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+        P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), 0x19, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+        P_Fld(0xf, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+        P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), 0x05, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) |
+        P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x4, MISC_SHU_ODTCTRL_RODT_LAT) |
+        P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) |
+        P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) |
+        P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+        P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+        P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+        P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+        P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+        P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+        P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+        P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+        P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) |
+        P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) |
+        P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
+        P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) |
+        P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) |
+        P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) |
+        P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x6, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) |
+        P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) |
+        P_Fld(0x2, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS));
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x19, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+        P_Fld(0x0a, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x19, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+        P_Fld(0x0a, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x05, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+        P_Fld(0x0d, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x05, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+        P_Fld(0x0d, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x19, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+        P_Fld(0x0a, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0c, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x19, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+        P_Fld(0x0a, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0c, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x05, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+        P_Fld(0x0d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x05, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+        P_Fld(0x0d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, RX data path setting Exit:
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, TX data path setting Enter:
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x17, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+        P_Fld(0x17, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
+        P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+        P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
+        P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0a, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+        P_Fld(0x0a, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
+        P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x06, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+        P_Fld(0x06, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
+        P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+        P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x6, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+        P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) |
+        P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0xa, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) |
+        P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) |
+        P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+        P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+        P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) |
+        P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE));
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) |
+        P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) |
+        P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) |
+        P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) |
+        P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+        P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+        P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+        P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+        P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+        P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+        P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+        P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+        P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+        P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+        P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ0) |
+        P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+        P_Fld(0x3, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM0) |
+        P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+        P_Fld(0x3, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x017, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+        P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x017, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+        P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x017, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+        P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x00a, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+        P_Fld(0x006, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x00a, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+        P_Fld(0x006, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x00a, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+        P_Fld(0x006, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B1) |
+        P_Fld(0x17, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B1) |
+        P_Fld(0x17, SHURK_PI_RK0_ARPI_DQM_B0));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x06, SHURK_PI_RK0_ARPI_DQ_B1) |
+        P_Fld(0x0a, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x06, SHURK_PI_RK0_ARPI_DQM_B1) |
+        P_Fld(0x0a, SHURK_PI_RK0_ARPI_DQM_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x38, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+        P_Fld(0x38, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x38, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+        P_Fld(0x38, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x38, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+        P_Fld(0x38, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x38, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+        P_Fld(0x38, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x38, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+        P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x2c, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+        P_Fld(0x2c, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x2c, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+        P_Fld(0x2c, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x2c, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+        P_Fld(0x2c, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x2c, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+        P_Fld(0x2c, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x2c, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+        P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+        P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+        P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+        P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+        P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+        P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+        P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+        P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+        P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+        P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x3c, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+        P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) |
+        P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT));
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, TX data path setting Exit:
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, TX CA golden setting Enter:
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) |
+        P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) |
+        P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) |
+        P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) |
+        P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1));
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) |
+        P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) |
+        P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1));
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) |
+        P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) |
+        P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) |
+        P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) |
+        P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7));
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) |
+        P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) |
+        P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) |
+        P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) |
+        P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15));
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) |
+        P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) |
+        P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) |
+        P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) |
+        P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1));
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, TX CA golden setting Exit
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, AC timing Enter:
+vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) |
+        P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY));
+vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4b, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+        P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x06, SHU_ACTIM_XRT_XRTR2R) |
+        P_Fld(0x0a, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x6, SHU_ACTIM_XRT_XRTW2R) |
+        P_Fld(0x07, SHU_ACTIM_XRT_XRTW2W));
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0xa, SHU_ACTIM0_TWTR) |
+        P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x0e, SHU_ACTIM0_TWR) |
+        P_Fld(0x3, SHU_ACTIM0_TRRD) | P_Fld(0x6, SHU_ACTIM0_TRCD) |
+        P_Fld(0x3, SHU_ACTIM0_TWTR_L));
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x5, SHU_ACTIM1_TRPAB) |
+        P_Fld(0x7, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x4, SHU_ACTIM1_TRP) |
+        P_Fld(0x05, SHU_ACTIM1_TRAS) | P_Fld(0x0a, SHU_ACTIM1_TRC));
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_ACTIM2_TXP) |
+        P_Fld(0x08, SHU_ACTIM2_TMRRI) | P_Fld(0x1, SHU_ACTIM2_TRTP) |
+        P_Fld(0x0a, SHU_ACTIM2_TR2W) | P_Fld(0x05, SHU_ACTIM2_TFAW));
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1f, SHU_ACTIM3_TRFCPB) |
+        P_Fld(0x8, SHU_ACTIM3_MANTMRR) | P_Fld(0x8, SHU_ACTIM3_TR2MRR) |
+        P_Fld(0x49, SHU_ACTIM3_TRFC));
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x057, SHU_ACTIM4_TXREFCNT) |
+        P_Fld(0x0f, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0c, SHU_ACTIM4_TMRR2W) |
+        P_Fld(0x1a, SHU_ACTIM4_TZQCS));
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x10, SHU_ACTIM5_TR2PD) |
+        P_Fld(0x11, SHU_ACTIM5_TWTPD) | P_Fld(0x1c, SHU_ACTIM5_TPBR2PBR) |
+        P_Fld(0x0, SHU_ACTIM5_TPBR2ACT));
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0a, SHU_ACTIM6_TZQLAT2) |
+        P_Fld(0x5, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) |
+        P_Fld(0x0d, SHU_ACTIM6_TW2MRW) | P_Fld(0x12, SHU_ACTIM6_TR2MRW));
+vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_CKECTRL_TPDE_05T) |
+        P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x3, SHU_CKECTRL_TPDE) |
+        P_Fld(0x2, SHU_CKECTRL_TPDX) | P_Fld(0x2, SHU_CKECTRL_TCKEPRD) |
+        P_Fld(0x3, SHU_CKECTRL_TCKESRX));
+vIO32WriteFldMulti(DRAMC_REG_SHU_MISC+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) |
+        P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_TX_PIPE_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_CMD_TXPIPE_BYPASS_EN) |
+        P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CK_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_TX_PIPE_BYPASS_EN) |
+        P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_CS_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_SKIP_TXPIPE_BYPASS));
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, AC timing Exit
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, RX cross-rank improve setting Enter.
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, RX cross-rank improve setting Exit.
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, RX input delay line set
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x004a, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+        P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x004a, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+        P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) |
+        P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) |
+        P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) |
+        P_Fld(0x6, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) |
+        P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) |
+        P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) |
+        P_Fld(0x6, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+        P_Fld(0xe5, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0xe5, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
+        P_Fld(0xe5, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+        P_Fld(0xe5, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0xe5, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+        P_Fld(0xe5, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+        P_Fld(0xe5, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0xe5, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+        P_Fld(0xe5, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+        P_Fld(0xe5, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0xe5, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+        P_Fld(0xe5, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+        P_Fld(0xe5, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x18a, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+        P_Fld(0x18a, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+        P_Fld(0xe4, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0xe4, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
+        P_Fld(0xe4, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+        P_Fld(0xe4, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0xe4, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+        P_Fld(0xe4, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+        P_Fld(0xe4, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0xe4, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+        P_Fld(0xe4, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+        P_Fld(0xe4, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0xe4, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+        P_Fld(0xe4, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+        P_Fld(0xe4, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x189, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+        P_Fld(0x189, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+        P_Fld(0xe5, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0xe5, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
+        P_Fld(0xe5, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+        P_Fld(0xe5, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0xe5, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+        P_Fld(0xe5, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+        P_Fld(0xe5, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0xe5, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+        P_Fld(0xe5, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+        P_Fld(0xe5, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0xe5, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+        P_Fld(0xe5, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0xe5, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+        P_Fld(0xe5, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x18a, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+        P_Fld(0x18a, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+        P_Fld(0xe4, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0xe4, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
+        P_Fld(0xe4, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+        P_Fld(0xe4, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0xe4, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+        P_Fld(0xe4, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+        P_Fld(0xe4, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0xe4, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+        P_Fld(0xe4, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+        P_Fld(0xe4, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0xe4, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+        P_Fld(0xe4, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xe4, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+        P_Fld(0xe4, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x189, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+        P_Fld(0x189, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, RX input delay line set EXIT
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, DRAMC other fixed register Enter
+vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_COMMON0_FREQDIV4) |
+        P_Fld(0x1, SHU_COMMON0_FDIV2) | P_Fld(0x0, SHU_COMMON0_FREQDIV8) |
+        P_Fld(0x0, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) |
+        P_Fld(0x0, SHU_COMMON0_LP5BGEN) | P_Fld(0x0, SHU_COMMON0_LP5WCKON) |
+        P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) |
+        P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) |
+        P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x0, SHU_COMMON0_LP5HEFF_MODE) |
+        P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV));
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) |
+        P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) |
+        P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG));
+vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+        P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x6, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+        P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) |
+        P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x3f, SHU_CONF0_DMPGTIM) |
+        P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) |
+        P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) |
+        P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH));
+vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_MATYPE_MATYPE) |
+        P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN));
+vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+        P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+        P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+        P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x1, SHU_TX_SET0_WDATRGO) |
+        P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x0, SHU_TX_SET0_WPST1P5T) |
+        P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+        P_Fld(0x0, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+        P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) |
+        P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) |
+        P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) |
+        P_Fld(0x0, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL));
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_STBCAL_DMSTBLAT) |
+        P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) |
+        P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) |
+        P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) |
+        P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) |
+        P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) |
+        P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN));
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT));
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT));
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) |
+        P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) |
+        P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) |
+        P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) |
+        P_Fld(0x2, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT));
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) |
+        P_Fld(0x0, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x0, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE));
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, DRAMC other fixed register Exit
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, DBI gen by frequency Enter
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, DBI gen by frequency Exit
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, DVFS_WLRL_setting Enter
+vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR13+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x000d, SHU_HWSET_MR13_HWSET_MR13_MRSMA) |
+        P_Fld(0x08, SHU_HWSET_MR13_HWSET_MR13_OP));
+vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_VRCG+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x000d, SHU_HWSET_VRCG_HWSET_VRCG_MRSMA) |
+        P_Fld(0x00, SHU_HWSET_VRCG_HWSET_VRCG_OP) | P_Fld(0x00, SHU_HWSET_VRCG_VRCGDIS_PRDCNT));
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, DVFS_WLRL_setting Exit
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, jump_ratio_setting_txrx_SHU_8_group Enter
+vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x00, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) |
+        P_Fld(0x00, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) |
+        P_Fld(0x2b, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0));
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, jump_ratio_setting_txrx_SHU_8_group Exit
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, dvfs_config_shuffle_registers Enter
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) |
+        P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) |
+        P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE));
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, dvfs_config_shuffle_registers Exit
+    mcDELAY_US(1);
+
+    mcDELAY_US(1);
+
+     DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, sram_read_timing_option Enter
+    mcDELAY_US(1);
+
+    mcDELAY_US(1);
+
+     DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+//    ========>SHUFFLE GROUP: 1, need_fifo: 1, sram_read_timing_option Exit
+vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0c, SHU_DQSOSCR_DQSOSCRCNT) |
+        P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) |
+        P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA));
+vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) |
+        P_Fld(0x021, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0b06, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
+        P_Fld(0x0b06, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x04b9, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
+        P_Fld(0x04b9, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x128, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
+        P_Fld(0x0c5, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x036, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
+        P_Fld(0x024, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
+vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+        P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+        P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+        P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x1, SHU_TX_SET0_WDATRGO) |
+        P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x0, SHU_TX_SET0_WPST1P5T) |
+        P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+        P_Fld(0x0, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x06, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+        P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_DQSOSC_SET0_DQSOSCENDIS) |
+        P_Fld(0x021, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT));
+vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0000, SHU_ZQ_SET0_ZQCSCNT) |
+        P_Fld(0x1d, SHU_ZQ_SET0_TZQLAT));
+vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) |
+        P_Fld(0x1d, SHU_ZQ_SET0_TZQLAT));
+vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4b, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+        P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x004a, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+        P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+        P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x004a, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+        P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+        P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+        P_Fld(0xb, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+        P_Fld(0xb, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) |
+        P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0));
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) |
+        P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1));
+//    Exit body
+}
+#endif
+
+void CInit_golden_mini_freq_related_vseq_LP4_4266(DRAMC_CTX_T *p)
+{
+//    Enter body
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Enter:
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_DRVING1_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING1_0                      -     @12634
+  DQDRVN2                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[4:0]=5'h08 (Mirror: 5'h00)
+  DQDRVP2                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[9:5]=5'h06 (Mirror: 5'h00)
+  DQSDRVN1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[14:10]=5'h08 (Mirror: 5'h00)
+  DQSDRVP1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[19:15]=5'h06 (Mirror: 5'h00)
+  DQSDRVN2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[24:20]=5'h08 (Mirror: 5'h00)
+  DQSDRVP2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[29:25]=5'h06 (Mirror: 5'h00)
+  DIS_IMP_ODTN_track                           uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[30:30]=1'h0
+  DIS_IMPCAL_HW                                uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[31:31]=1'h0
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(0x08, SHU_MISC_DRVING1_DQDRVN2) |
+        P_Fld(0x06, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN1) |
+        P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN2) |
+        P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x1, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) |
+        P_Fld(0x1, SHU_MISC_DRVING1_DIS_IMPCAL_HW));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_DRVING2_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING2_0                      -     @12645
+  CMDDRVN1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[4:0]=5'h08 (Mirror: 5'h00)
+  CMDDRVP1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[9:5]=5'h06 (Mirror: 5'h00)
+  CMDDRVN2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[14:10]=5'h08 (Mirror: 5'h00)
+  CMDDRVP2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[19:15]=5'h06 (Mirror: 5'h00)
+  DQDRVN1                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[24:20]=5'h08 (Mirror: 5'h00)
+  DQDRVP1                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[29:25]=5'h06 (Mirror: 5'h00)
+  DIS_IMPCAL_ODT_EN                            uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[31:31]=1'h0
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2, P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN1) |
+        P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN2) |
+        P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x08, SHU_MISC_DRVING2_DQDRVN1) |
+        P_Fld(0x06, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_DRVING3_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING3_0                      -     @12655
+  DQODTN2                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[4:0]=5'h0a (Mirror: 5'h00)
+  DQODTP2                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[9:5]=5'h0a (Mirror: 5'h00)
+  DQSODTN                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[14:10]=5'h0a (Mirror: 5'h00)
+  DQSODTP                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[19:15]=5'h0a (Mirror: 5'h00)
+  DQSODTN2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[24:20]=5'h0a (Mirror: 5'h00)
+  DQSODTP2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[29:25]=5'h0a (Mirror: 5'h00)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3, P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) |
+        P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) |
+        P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) |
+        P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_DRVING4_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING4_0                      -     @12664
+  CMDODTN1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[4:0]=5'h0a (Mirror: 5'h00)
+  CMDODTP1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[9:5]=5'h0a (Mirror: 5'h00)
+  CMDODTN2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[14:10]=5'h0a (Mirror: 5'h00)
+  CMDODTP2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[19:15]=5'h0a (Mirror: 5'h00)
+  DQODTN1                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[24:20]=5'h0a (Mirror: 5'h00)
+  DQODTP1                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[29:25]=5'h0a (Mirror: 5'h00)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4, P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) |
+        P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) |
+        P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) |
+        P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_DRVING6_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING6_0                      -     @12682
+  IMP_TXDLY_CMD                                uvm_reg_field                                              ...    RW SHU_MISC_DRVING6_0[5:0]=6'h0a (Mirror: 6'h01)
+  DQCODTN1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING6_0[24:20]=5'h00
+  DQCODTP1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING6_0[29:25]=5'h00
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6, P_Fld(0x0a, SHU_MISC_DRVING6_IMP_TXDLY_CMD) |
+        P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_IMPCAL1_0                             ral_reg_DDRPHY_blk_SHU_MISC_IMPCAL1_0                      -     @12625
+  IMPCAL_CHKCYCLE                              uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[2:0]=3'h7 (Mirror: 3'h4)
+  IMPDRVP                                      uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[8:4]=5'h00
+  IMPDRVN                                      uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[16:12]=5'h00
+  IMPCAL_CALEN_CYCLE                           uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[19:17]=3'h4
+  IMPCALCNT                                    uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[27:20]=8'h03 (Mirror: 8'h00)
+  IMPCAL_CALICNT                               uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[31:28]=4'h8
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1, P_Fld(0x7, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) |
+        P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) |
+        P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) |
+        P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Exit:
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter:
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_RDSEL_TRACK_0                         ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0                  -     @12734
+  DMDATLAT_i                                   uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h10 (Mirror: 5'h00)
+  RDSEL_HWSAVE_MSK                             uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0)
+  RDSEL_TRACK_EN                               uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0
+  SHU_GW_THRD_NEG                              uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfcb (Mirror: 12'h000)
+  SHU_GW_THRD_POS                              uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h035 (Mirror: 12'h000)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x10, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) |
+        P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) |
+        P_Fld(0xfcb, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x035, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RDAT_0                                ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0                         -     @12604
+  DATLAT                                       uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[4:0]=5'h10 (Mirror: 5'h00)
+  DATLAT_DSEL                                  uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[12:8]=5'h10 (Mirror: 5'h00)
+  DATLAT_DSEL_PHY                              uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[20:16]=5'h10 (Mirror: 5'h00)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x10, MISC_SHU_RDAT_DATLAT) |
+        P_Fld(0x10, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x10, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_PHY_RX_CTRL_0                         ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0                  -     @12540
+  RANK_RXDLY_UPDLAT_EN                         uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0)
+  RANK_RXDLY_UPD_OFFSET                        uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0)
+  RX_IN_GATE_EN_PRE_OFFSET                     uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0)
+  RX_IN_GATE_EN_HEAD                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h1 (Mirror: 3'h0)
+  RX_IN_GATE_EN_TAIL                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0)
+  RX_IN_BUFF_EN_HEAD                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h3 (Mirror: 3'h0)
+  RX_IN_BUFF_EN_TAIL                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) |
+        P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) |
+        P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) |
+        P_Fld(0x3, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RANKCTL_0                             ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0                      -     @12530
+  RANKINCTL_RXDLY                              uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[3:0]=4'h5 (Mirror: 4'h0)
+  RANK_RXDLY_OPT                               uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[4:4]=1'h1
+  RANKSEL_SELPH_FRUN                           uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[15:15]=1'h0
+  RANKINCTL_STB                                uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[19:16]=4'h8 (Mirror: 4'h0)
+  RANKINCTL                                    uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[23:20]=4'h6 (Mirror: 4'h0)
+  RANKINCTL_ROOT1                              uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[27:24]=4'h6 (Mirror: 4'h0)
+  RANKINCTL_PHY                                uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[31:28]=4'h9 (Mirror: 4'h0)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) |
+        P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) |
+        P_Fld(0x8, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL) |
+        P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x9, MISC_SHU_RANKCTL_RANKINCTL_PHY));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RANK_SEL_LAT_0                        ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0                 -     @12757
+  RANK_SEL_LAT_B0                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0)
+  RANK_SEL_LAT_B1                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0)
+  RANK_SEL_LAT_CA                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
+        P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RK_DQSCTL_0_0                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0                  -     @12352
+  DQSINCTL                                     uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h8 (Mirror: 4'h0)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x8, MISC_SHU_RK_DQSCTL_DQSINCTL);
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RK_DQSCTL_0_1                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1                  -     @12356
+  DQSINCTL                                     uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h8 (Mirror: 4'h0)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x8, MISC_SHU_RK_DQSCTL_DQSINCTL);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0         -     @7624
+  DQSIEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h1 (Mirror: 4'h0)
+  DQSIEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h5 (Mirror: 4'h0)
+  DQSIEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0)
+  DQSIEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+        P_Fld(0x5, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+        P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_DQSIEN_PI_DLY_0_0                    ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0             -     @7638
+  DQSIEN_PI_B0                                 uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h01 (Mirror: 7'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x01, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1         -     @7631
+  DQSIEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h9 (Mirror: 4'h0)
+  DQSIEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hd (Mirror: 4'h0)
+  DQSIEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0)
+  DQSIEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x9, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+        P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+        P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_DQSIEN_PI_DLY_0_1                    ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1             -     @7642
+  DQSIEN_PI_B0                                 uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h08 (Mirror: 7'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x08, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0         -     @9027
+  DQSIEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h1 (Mirror: 4'h0)
+  DQSIEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h5 (Mirror: 4'h0)
+  DQSIEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0)
+  DQSIEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+        P_Fld(0x5, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+        P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_DQSIEN_PI_DLY_0_0                    ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0             -     @9041
+  DQSIEN_PI_B1                                 uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h01 (Mirror: 7'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x01, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1         -     @9034
+  DQSIEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h9 (Mirror: 4'h0)
+  DQSIEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hd (Mirror: 4'h0)
+  DQSIEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0)
+  DQSIEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x9, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+        P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+        P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_DQSIEN_PI_DLY_0_1                    ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1             -     @9045
+  DQSIEN_PI_B1                                 uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h08 (Mirror: 7'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x08, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_ODTCTRL_0                             ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0                      -     @12550
+  RODTEN                                       uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0)
+  RODTENSTB_SELPH_CG_IG                        uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[1:1]=1'h0
+  RODT_LAT                                     uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[7:4]=4'h8 (Mirror: 4'h0)
+  RODTEN_SELPH_FRUN                            uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[15:15]=1'h0
+  RODTDLY_LAT_OPT                              uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[25:24]=2'h0
+  FIXRODT                                      uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[27:27]=1'h0
+  RODTEN_OPT                                   uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[29:29]=1'h1
+  RODTE2                                       uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0)
+  RODTE                                        uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) |
+        P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x8, MISC_SHU_ODTCTRL_RODT_LAT) |
+        P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) |
+        P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) |
+        P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ7_0                            -     @7808
+  R_DMRANKRXDVS_B0                             uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[3:0]=4'h0
+  R_DMDQMDBI_EYE_SHU_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[6:6]=1'h0
+  R_DMDQMDBI_SHU_B0                            uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[7:7]=1'h0
+  R_DMRXDVS_DQM_FLAGSEL_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[11:8]=4'h0
+  R_DMRXDVS_PBYTE_FLAG_OPT_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[12:12]=1'h0
+  R_DMRXDVS_PBYTE_DQM_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[13:13]=1'h0
+  R_DMRXTRACK_DQM_EN_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[14:14]=1'h0
+  R_DMRODTEN_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)
+  R_DMARPI_CG_FB2DLL_DCM_EN_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[16:16]=1'h0
+  R_DMTX_ARPI_CG_DQ_NEW_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[17:17]=1'h0
+  R_DMTX_ARPI_CG_DQS_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[18:18]=1'h0
+  R_DMTX_ARPI_CG_DQM_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[19:19]=1'h0
+  R_LP4Y_SDN_MODE_DQS0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[20:20]=1'h0
+  R_DMRXRANK_DQ_EN_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)
+  R_DMRXRANK_DQ_LAT_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[27:25]=3'h2 (Mirror: 3'h0)
+  R_DMRXRANK_DQS_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)
+  R_DMRXRANK_DQS_LAT_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[31:29]=3'h1 (Mirror: 3'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ7_0                            -     @9211
+  R_DMRANKRXDVS_B1                             uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[3:0]=4'h0
+  R_DMDQMDBI_EYE_SHU_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[6:6]=1'h0
+  R_DMDQMDBI_SHU_B1                            uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[7:7]=1'h0
+  R_DMRXDVS_DQM_FLAGSEL_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[11:8]=4'h0
+  R_DMRXDVS_PBYTE_FLAG_OPT_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[12:12]=1'h0
+  R_DMRXDVS_PBYTE_DQM_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[13:13]=1'h0
+  R_DMRXTRACK_DQM_EN_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[14:14]=1'h0
+  R_DMRODTEN_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)
+  R_DMARPI_CG_FB2DLL_DCM_EN_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[16:16]=1'h0
+  R_DMTX_ARPI_CG_DQ_NEW_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[17:17]=1'h0
+  R_DMTX_ARPI_CG_DQS_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[18:18]=1'h0
+  R_DMTX_ARPI_CG_DQM_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[19:19]=1'h0
+  R_LP4Y_SDN_MODE_DQS1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[20:20]=1'h0
+  R_DMRXRANK_DQ_EN_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)
+  R_DMRXRANK_DQ_LAT_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[27:25]=3'h2 (Mirror: 3'h0)
+  R_DMRXRANK_DQS_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)
+  R_DMRXRANK_DQS_LAT_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[31:29]=3'h1 (Mirror: 3'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_RX_PIPE_CTRL_0                        ral_reg_DDRPHY_blk_SHU_MISC_RX_PIPE_CTRL_0                 -     @12704
+  RX_PIPE_BYPASS_EN                            uvm_reg_field                                              ...    RW SHU_MISC_RX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x1, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0         -     @7646
+  RODTEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0)
+  RODTEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0)
+  RODTEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0
+  RODTEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+        P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+        P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1         -     @7653
+  RODTEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h4 (Mirror: 3'h0)
+  RODTEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h4 (Mirror: 3'h0)
+  RODTEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0)
+  RODTEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+        P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+        P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0         -     @9049
+  RODTEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0)
+  RODTEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0)
+  RODTEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0
+  RODTEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+        P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+        P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1         -     @9056
+  RODTEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h4 (Mirror: 3'h0)
+  RODTEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h4 (Mirror: 3'h0)
+  RODTEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0)
+  RODTEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+        P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+        P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RX_CG_SET0_0                               ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0                         -     @5323
+  DLE_LAST_EXTEND3                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[0:0]=1'h0
+  READ_START_EXTEND3                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[1:1]=1'h0
+  DLE_LAST_EXTEND2                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0)
+  READ_START_EXTEND2                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0)
+  DLE_LAST_EXTEND1                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0)
+  READ_START_EXTEND1                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) |
+        P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) |
+        P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
+        P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_RANK_SEL_STB_0                        ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0                 -     @12720
+  RANK_SEL_STB_EN                              uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0)
+  RANK_SEL_STB_EN_B23                          uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0
+  RANK_SEL_STB_SERMODE                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0
+  RANK_SEL_STB_TRACK                           uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0)
+  RANK_SEL_RXDLY_TRACK                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0
+  RANK_SEL_STB_PHASE_EN                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h1 (Mirror: 1'h0)
+  RANK_SEL_PHSINCTL                            uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h9 (Mirror: 4'h0)
+  RANK_SEL_STB_UI_PLUS                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0
+  RANK_SEL_STB_MCK_PLUS                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0
+  RANK_SEL_STB_UI_MINUS                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h1 (Mirror: 4'h0)
+  RANK_SEL_STB_MCK_MINUS                       uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) |
+        P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) |
+        P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) |
+        P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x9, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) |
+        P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) |
+        P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RK_DQSCAL_0_0                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0                  -     @12370
+  DQSIENLLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00)
+  DQSIENLLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0)
+  DQSIENHLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00)
+  DQSIENHLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RK_DQSCAL_0_1                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1                  -     @12377
+  DQSIENLLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00)
+  DQSIENLLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0)
+  DQSIENHLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00)
+  DQSIENHLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_INI_UIPI_0_0                         ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0                  -     @7602
+  CURR_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00)
+  CURR_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x01, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+        P_Fld(0x11, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_INI_UIPI_0_0                         ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0                  -     @9005
+  CURR_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00)
+  CURR_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x01, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+        P_Fld(0x11, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_INI_UIPI_0_1                         ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1                  -     @7607
+  CURR_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00)
+  CURR_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+        P_Fld(0x19, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_INI_UIPI_0_1                         ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1                  -     @9010
+  CURR_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00)
+  CURR_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+        P_Fld(0x19, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_NEXT_INI_UIPI_0_0                    ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0             -     @7612
+  NEXT_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00)
+  NEXT_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00)
+  NEXT_INI_UI_P1_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h15 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x01, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+        P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x15, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_NEXT_INI_UIPI_0_0                    ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0             -     @9015
+  NEXT_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00)
+  NEXT_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00)
+  NEXT_INI_UI_P1_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h15 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x01, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+        P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x15, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_NEXT_INI_UIPI_0_1                    ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1             -     @7618
+  NEXT_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00)
+  NEXT_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00)
+  NEXT_INI_UI_P1_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h1d (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+        P_Fld(0x19, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x1d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_NEXT_INI_UIPI_0_1                    ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1             -     @9021
+  NEXT_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00)
+  NEXT_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00)
+  NEXT_INI_UI_P1_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h1d (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+        P_Fld(0x19, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x1d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit:
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter:
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_DQ0_0_0                              ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0                       -     @7582
+  RG_RX_ARDQS0_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0
+  RG_RX_ARDQS0_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0
+  SW_ARPI_DQ_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[13:8]=6'h15 (Mirror: 6'h00)
+  SW_ARPI_DQM_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[21:16]=6'h15 (Mirror: 6'h00)
+  ARPI_PBYTE_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00
+  DA_ARPI_DDR400_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0
+  DA_RX_ARDQSIEN_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x15, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+        P_Fld(0x15, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
+        P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_DQ0_0_0                              ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0                       -     @8985
+  RG_RX_ARDQS1_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0
+  RG_RX_ARDQS1_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0
+  SW_ARPI_DQ_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[13:8]=6'h15 (Mirror: 6'h00)
+  SW_ARPI_DQM_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[21:16]=6'h15 (Mirror: 6'h00)
+  ARPI_PBYTE_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00
+  DA_ARPI_DDR400_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0
+  DA_RX_ARDQSIEN_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x15, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+        P_Fld(0x15, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
+        P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_DQ0_0_1                              ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1                       -     @7592
+  RG_RX_ARDQS0_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0
+  RG_RX_ARDQS0_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0
+  SW_ARPI_DQ_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[13:8]=6'h24 (Mirror: 6'h00)
+  SW_ARPI_DQM_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[21:16]=6'h24 (Mirror: 6'h00)
+  ARPI_PBYTE_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00
+  DA_ARPI_DDR400_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0
+  DA_RX_ARDQSIEN_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x24, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+        P_Fld(0x24, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
+        P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_DQ0_0_1                              ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1                       -     @8995
+  RG_RX_ARDQS1_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0
+  RG_RX_ARDQS1_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0
+  SW_ARPI_DQ_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[13:8]=6'h22 (Mirror: 6'h00)
+  SW_ARPI_DQM_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[21:16]=6'h22 (Mirror: 6'h00)
+  ARPI_PBYTE_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00
+  DA_ARPI_DDR400_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0
+  DA_RX_ARDQSIEN_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x22, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+        P_Fld(0x22, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
+        P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_DCM_CTRL0_0                                ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0                          -     @5027
+  DDRPHY_CLK_EN_OPT                            uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0)
+  DPHY_CMDDCM_EXTCNT                           uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[11:8]=4'h4
+  DDRPHY_CLK_DYN_GATING_SEL                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0)
+  CKE_EXTNONPD_CNT                             uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[19:16]=4'h0
+  FASTWAKE2                                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[29:29]=1'h0
+  FASTWAKE                                     uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[31:31]=1'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+#if (fcFOR_CHIP_ID == fcA60868)
+vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+        P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+        P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) |
+        P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+#elif (fcFOR_CHIP_ID == fcPetrus)
+vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+        P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+        P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) |
+        P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_APHY_TX_PICG_CTRL_0                        ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0                  -     @5377
+  DDRPHY_CLK_EN_COMB_TX_PICG_CNT               uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h7 (Mirror: 4'h0)
+  DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1             uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h3 (Mirror: 3'h0)
+  DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0             uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h3 (Mirror: 3'h0)
+  DDRPHY_CLK_EN_COMB_TX_OPT                    uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x7, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) |
+        P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) |
+        P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_APHY_TX_PICG_CTRL_0_0                    ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0              -     @4926
+  DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h3 (Mirror: 3'h0)
+  DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h3 (Mirror: 3'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+        P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_APHY_TX_PICG_CTRL_0_1                    ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1              -     @4931
+  DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h4 (Mirror: 3'h0)
+  DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h3 (Mirror: 3'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+        P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_NEW_XRW2W_CTRL_0                           ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0                     -     @5371
+  TX_PI_UPDCTL_B0                              uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h3 (Mirror: 3'h0)
+  TX_PI_UPDCTL_B1                              uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h3 (Mirror: 3'h0)
+  TXPI_UPD_MODE                                uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) |
+        P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SELPH_DQS0_0                               ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0                         -     @5271
+  TXDLY_DQS0                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[2:0]=3'h4 (Mirror: 3'h1)
+  TXDLY_DQS1                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[6:4]=3'h4 (Mirror: 3'h1)
+  TXDLY_DQS2                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[10:8]=3'h1
+  TXDLY_DQS3                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[14:12]=3'h1
+  TXDLY_OEN_DQS0                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[18:16]=3'h4 (Mirror: 3'h1)
+  TXDLY_OEN_DQS1                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[22:20]=3'h4 (Mirror: 3'h1)
+  TXDLY_OEN_DQS2                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[26:24]=3'h1
+  TXDLY_OEN_DQS3                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[30:28]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) |
+        P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) |
+        P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) |
+        P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) |
+        P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SELPH_DQS1_0                               ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0                         -     @5282
+  dly_DQS0                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[3:0]=4'h5 (Mirror: 4'h1)
+  dly_DQS1                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[7:4]=4'h5 (Mirror: 4'h1)
+  dly_DQS2                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[11:8]=4'h1
+  dly_DQS3                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[15:12]=4'h1
+  dly_oen_DQS0                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[19:16]=4'h2 (Mirror: 4'h1)
+  dly_oen_DQS1                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[23:20]=4'h2 (Mirror: 4'h1)
+  dly_oen_DQS2                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[27:24]=4'h1
+  dly_oen_DQS3                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[31:28]=4'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS0) |
+        P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) |
+        P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS0) |
+        P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) |
+        P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ0_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0                      -     @4746
+  TXDLY_DQ0                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[2:0]=3'h3 (Mirror: 3'h1)
+  TXDLY_DQ1                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[6:4]=3'h3 (Mirror: 3'h1)
+  TXDLY_DQ2                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1
+  TXDLY_DQ3                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1
+  TXDLY_OEN_DQ0                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[18:16]=3'h4 (Mirror: 3'h1)
+  TXDLY_OEN_DQ1                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[22:20]=3'h4 (Mirror: 3'h1)
+  TXDLY_OEN_DQ2                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1
+  TXDLY_OEN_DQ3                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+        P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+        P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ1_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0                      -     @4768
+  TXDLY_DQM0                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[2:0]=3'h3 (Mirror: 3'h1)
+  TXDLY_DQM1                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[6:4]=3'h3 (Mirror: 3'h1)
+  TXDLY_DQM2                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1
+  TXDLY_DQM3                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1
+  TXDLY_OEN_DQM0                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[18:16]=3'h4 (Mirror: 3'h1)
+  TXDLY_OEN_DQM1                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[22:20]=3'h4 (Mirror: 3'h1)
+  TXDLY_OEN_DQM2                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1
+  TXDLY_OEN_DQM3                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+        P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+        P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ2_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0                      -     @4790
+  dly_DQ0                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[3:0]=4'h6 (Mirror: 4'h1)
+  dly_DQ1                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[7:4]=4'h6 (Mirror: 4'h1)
+  dly_DQ2                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1
+  dly_DQ3                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1
+  dly_oen_DQ0                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[19:16]=4'h3 (Mirror: 4'h1)
+  dly_oen_DQ1                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[23:20]=4'h3 (Mirror: 4'h1)
+  dly_oen_DQ2                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1
+  dly_oen_DQ3                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ0) |
+        P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+        P_Fld(0x3, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ3_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0                      -     @4812
+  dly_DQM0                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[3:0]=4'h6 (Mirror: 4'h1)
+  dly_DQM1                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[7:4]=4'h6 (Mirror: 4'h1)
+  dly_DQM2                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1
+  dly_DQM3                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1
+  dly_oen_DQM0                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[19:16]=4'h3 (Mirror: 4'h1)
+  dly_oen_DQM1                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[23:20]=4'h3 (Mirror: 4'h1)
+  dly_oen_DQM2                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1
+  dly_oen_DQM3                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM0) |
+        P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+        P_Fld(0x3, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ0_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1                      -     @4757
+  TXDLY_DQ0                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[2:0]=3'h3 (Mirror: 3'h1)
+  TXDLY_DQ1                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[6:4]=3'h3 (Mirror: 3'h1)
+  TXDLY_DQ2                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1
+  TXDLY_DQ3                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1
+  TXDLY_OEN_DQ0                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[18:16]=3'h4 (Mirror: 3'h1)
+  TXDLY_OEN_DQ1                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[22:20]=3'h4 (Mirror: 3'h1)
+  TXDLY_OEN_DQ2                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1
+  TXDLY_OEN_DQ3                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+        P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+        P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ1_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1                      -     @4779
+  TXDLY_DQM0                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[2:0]=3'h3 (Mirror: 3'h1)
+  TXDLY_DQM1                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[6:4]=3'h3 (Mirror: 3'h1)
+  TXDLY_DQM2                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1
+  TXDLY_DQM3                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1
+  TXDLY_OEN_DQM0                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[18:16]=3'h4 (Mirror: 3'h1)
+  TXDLY_OEN_DQM1                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[22:20]=3'h4 (Mirror: 3'h1)
+  TXDLY_OEN_DQM2                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1
+  TXDLY_OEN_DQM3                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+        P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+        P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ2_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1                      -     @4801
+  dly_DQ0                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[3:0]=4'h7 (Mirror: 4'h1)
+  dly_DQ1                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[7:4]=4'h7 (Mirror: 4'h1)
+  dly_DQ2                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1
+  dly_DQ3                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1
+  dly_oen_DQ0                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[19:16]=4'h4 (Mirror: 4'h1)
+  dly_oen_DQ1                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[23:20]=4'h4 (Mirror: 4'h1)
+  dly_oen_DQ2                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1
+  dly_oen_DQ3                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x7, SHURK_SELPH_DQ2_DLY_DQ0) |
+        P_Fld(0x7, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+        P_Fld(0x4, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ3_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1                      -     @4823
+  dly_DQM0                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[3:0]=4'h7 (Mirror: 4'h1)
+  dly_DQM1                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[7:4]=4'h7 (Mirror: 4'h1)
+  dly_DQM2                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1
+  dly_DQM3                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1
+  dly_oen_DQM0                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[19:16]=4'h4 (Mirror: 4'h1)
+  dly_oen_DQM1                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[23:20]=4'h4 (Mirror: 4'h1)
+  dly_oen_DQM2                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1
+  dly_oen_DQM3                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x7, SHURK_SELPH_DQ3_DLY_DQM0) |
+        P_Fld(0x7, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+        P_Fld(0x4, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL1_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0                    -     @4834
+  BOOT_ORIG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h015 (Mirror: 11'h000)
+  BOOT_ORIG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h015 (Mirror: 11'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x015, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+        P_Fld(0x015, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL2_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0                    -     @4844
+  BOOT_TARG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h015 (Mirror: 11'h000)
+  BOOT_TARG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h015 (Mirror: 11'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x015, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+        P_Fld(0x015, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL5_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0                    -     @4882
+  BOOT_TARG_UI_RK0_DQM0                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h015 (Mirror: 11'h000)
+  BOOT_TARG_UI_RK0_DQM1                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h015 (Mirror: 11'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x015, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+        P_Fld(0x015, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL1_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1                    -     @4839
+  BOOT_ORIG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h024 (Mirror: 11'h000)
+  BOOT_ORIG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h022 (Mirror: 11'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x024, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+        P_Fld(0x022, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL2_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1                    -     @4849
+  BOOT_TARG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h024 (Mirror: 11'h000)
+  BOOT_TARG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h022 (Mirror: 11'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x024, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+        P_Fld(0x022, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL5_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1                    -     @4887
+  BOOT_TARG_UI_RK0_DQM0                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h024 (Mirror: 11'h000)
+  BOOT_TARG_UI_RK0_DQM1                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h022 (Mirror: 11'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x024, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+        P_Fld(0x022, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_PI_0_0                                   ral_reg_DRAMC_blk_SHURK_PI_0_0                             -     @4892
+  RK0_ARPI_DQ_B1                               uvm_reg_field                                              ...    RW SHURK_PI_0_0[5:0]=6'h15 (Mirror: 6'h00)
+  RK0_ARPI_DQ_B0                               uvm_reg_field                                              ...    RW SHURK_PI_0_0[13:8]=6'h15 (Mirror: 6'h00)
+  RK0_ARPI_DQM_B1                              uvm_reg_field                                              ...    RW SHURK_PI_0_0[21:16]=6'h15 (Mirror: 6'h00)
+  RK0_ARPI_DQM_B0                              uvm_reg_field                                              ...    RW SHURK_PI_0_0[29:24]=6'h15 (Mirror: 6'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x15, SHURK_PI_RK0_ARPI_DQ_B1) |
+        P_Fld(0x15, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x15, SHURK_PI_RK0_ARPI_DQM_B1) |
+        P_Fld(0x15, SHURK_PI_RK0_ARPI_DQM_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_PI_0_1                                   ral_reg_DRAMC_blk_SHURK_PI_0_1                             -     @4899
+  RK0_ARPI_DQ_B1                               uvm_reg_field                                              ...    RW SHURK_PI_0_1[5:0]=6'h22 (Mirror: 6'h00)
+  RK0_ARPI_DQ_B0                               uvm_reg_field                                              ...    RW SHURK_PI_0_1[13:8]=6'h24 (Mirror: 6'h00)
+  RK0_ARPI_DQM_B1                              uvm_reg_field                                              ...    RW SHURK_PI_0_1[21:16]=6'h22 (Mirror: 6'h00)
+  RK0_ARPI_DQM_B0                              uvm_reg_field                                              ...    RW SHURK_PI_0_1[29:24]=6'h24 (Mirror: 6'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x22, SHURK_PI_RK0_ARPI_DQ_B1) |
+        P_Fld(0x24, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x22, SHURK_PI_RK0_ARPI_DQM_B1) |
+        P_Fld(0x24, SHURK_PI_RK0_ARPI_DQM_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_TXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0                    -     @7428
+  TX_ARDQ0_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h08 (Mirror: 8'h00)
+  TX_ARDQ1_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h08 (Mirror: 8'h00)
+  TX_ARDQ2_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h08 (Mirror: 8'h00)
+  TX_ARDQ3_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h08 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+        P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+        P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_TXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0                    -     @7442
+  TX_ARDQ4_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h08 (Mirror: 8'h00)
+  TX_ARDQ5_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h08 (Mirror: 8'h00)
+  TX_ARDQ6_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h08 (Mirror: 8'h00)
+  TX_ARDQ7_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h08 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+        P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+        P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_TXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0                    -     @7470
+  TX_ARDQM0_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h08 (Mirror: 8'h00)
+  TX_ARWCK_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00
+  TX_ARWCKB_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x08, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+        P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_TXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0                    -     @8831
+  TX_ARDQ0_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h08 (Mirror: 8'h00)
+  TX_ARDQ1_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h08 (Mirror: 8'h00)
+  TX_ARDQ2_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h08 (Mirror: 8'h00)
+  TX_ARDQ3_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h08 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+        P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+        P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_TXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0                    -     @8845
+  TX_ARDQ4_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h08 (Mirror: 8'h00)
+  TX_ARDQ5_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h08 (Mirror: 8'h00)
+  TX_ARDQ6_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h08 (Mirror: 8'h00)
+  TX_ARDQ7_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h08 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+        P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+        P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_TXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0                    -     @8873
+  TX_ARDQM0_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h08 (Mirror: 8'h00)
+  TX_ARWCK_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00
+  TX_ARWCKB_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x08, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+        P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_TXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1                    -     @7435
+  TX_ARDQ0_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h20 (Mirror: 8'h00)
+  TX_ARDQ1_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h20 (Mirror: 8'h00)
+  TX_ARDQ2_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h20 (Mirror: 8'h00)
+  TX_ARDQ3_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h20 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+        P_Fld(0x20, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x20, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+        P_Fld(0x20, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_TXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1                    -     @7449
+  TX_ARDQ4_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h20 (Mirror: 8'h00)
+  TX_ARDQ5_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h20 (Mirror: 8'h00)
+  TX_ARDQ6_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h20 (Mirror: 8'h00)
+  TX_ARDQ7_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h20 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+        P_Fld(0x20, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x20, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+        P_Fld(0x20, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_TXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1                    -     @7476
+  TX_ARDQM0_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h20 (Mirror: 8'h00)
+  TX_ARWCK_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00
+  TX_ARWCKB_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+        P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_TXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1                    -     @8838
+  TX_ARDQ0_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h28 (Mirror: 8'h00)
+  TX_ARDQ1_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h28 (Mirror: 8'h00)
+  TX_ARDQ2_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h28 (Mirror: 8'h00)
+  TX_ARDQ3_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h28 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x28, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+        P_Fld(0x28, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x28, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+        P_Fld(0x28, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_TXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1                    -     @8852
+  TX_ARDQ4_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h28 (Mirror: 8'h00)
+  TX_ARDQ5_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h28 (Mirror: 8'h00)
+  TX_ARDQ6_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h28 (Mirror: 8'h00)
+  TX_ARDQ7_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h28 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x28, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+        P_Fld(0x28, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x28, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+        P_Fld(0x28, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_TXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1                    -     @8879
+  TX_ARDQM0_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h28 (Mirror: 8'h00)
+  TX_ARWCK_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00
+  TX_ARWCKB_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x28, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+        P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_TX_RANKCTL_0                               ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0                         -     @5345
+  TXRANKINCTL_TXDLY                            uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[3:0]=4'h2 (Mirror: 4'h0)
+  TXRANKINCTL                                  uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[7:4]=4'h2 (Mirror: 4'h0)
+  TXRANKINCTL_ROOT                             uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[11:8]=4'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) |
+        P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ9_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ9_0                            -     @7845
+  RG_ARPI_RESERVE_B0                           uvm_reg_field                                              ...    RW SHU_B0_DQ9_0[31:0]=32'h31105ab1 (Mirror: 32'h31165ab1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9, 0x31105ab1, SHU_B0_DQ9_RG_ARPI_RESERVE_B0);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ9_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ9_0                            -     @9248
+  RG_ARPI_RESERVE_B1                           uvm_reg_field                                              ...    RW SHU_B1_DQ9_0[31:0]=32'hd5713d50 (Mirror: 32'hd5733d50)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9, 0xd5713d50, SHU_B1_DQ9_RG_ARPI_RESERVE_B1);
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit:
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Enter:
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SELPH_CA1_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA1_0                          -     @5041
+  TXDLY_CS                                     uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[2:0]=3'h0 (Mirror: 3'h1)
+  TXDLY_CKE                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[6:4]=3'h0 (Mirror: 3'h1)
+  TXDLY_ODT                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[10:8]=3'h0 (Mirror: 3'h1)
+  TXDLY_RESET                                  uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[14:12]=3'h0 (Mirror: 3'h1)
+  TXDLY_WE                                     uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[18:16]=3'h0 (Mirror: 3'h1)
+  TXDLY_CAS                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[22:20]=3'h0 (Mirror: 3'h1)
+  TXDLY_RAS                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[26:24]=3'h0 (Mirror: 3'h1)
+  TXDLY_CS1                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[30:28]=3'h0 (Mirror: 3'h1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) |
+        P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) |
+        P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) |
+        P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) |
+        P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SELPH_CA2_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA2_0                          -     @5052
+  TXDLY_BA0                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[2:0]=3'h0 (Mirror: 3'h1)
+  TXDLY_BA1                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[6:4]=3'h0 (Mirror: 3'h1)
+  TXDLY_BA2                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[10:8]=3'h0 (Mirror: 3'h1)
+  TXDLY_CMD                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[20:16]=5'h01
+  TXDLY_CKE1                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[26:24]=3'h0 (Mirror: 3'h1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) |
+        P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) |
+        P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SELPH_CA3_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA3_0                          -     @5060
+  TXDLY_RA0                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[2:0]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA1                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[6:4]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA2                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[10:8]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA3                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[14:12]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA4                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[18:16]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA5                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[22:20]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA6                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[26:24]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA7                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[30:28]=3'h0 (Mirror: 3'h1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) |
+        P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) |
+        P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) |
+        P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) |
+        P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SELPH_CA4_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA4_0                          -     @5071
+  TXDLY_RA8                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[2:0]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA9                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[6:4]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA10                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[10:8]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA11                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[14:12]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA12                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[18:16]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA13                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[22:20]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA14                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[26:24]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA15                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[30:28]=3'h0 (Mirror: 3'h1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) |
+        P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) |
+        P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) |
+        P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) |
+        P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SELPH_CA5_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA5_0                          -     @5082
+  dly_CS                                       uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[2:0]=3'h1
+  dly_CKE                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[6:4]=3'h1
+  dly_ODT                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[10:8]=3'h0 (Mirror: 3'h1)
+  dly_RESET                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[14:12]=3'h1
+  dly_WE                                       uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[18:16]=3'h1
+  dly_CAS                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[22:20]=3'h1
+  dly_RAS                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[26:24]=3'h1
+  dly_CS1                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[30:28]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5, P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) |
+        P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) |
+        P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) |
+        P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) |
+        P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Exit
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter:
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SREF_CTRL_0                                ral_reg_DRAMC_blk_SHU_SREF_CTRL_0                          -     @5018
+  CKEHCMD                                      uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[5:4]=2'h3
+  SREF_CK_DLY                                  uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) |
+        P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_HMR4_DVFS_CTRL0_0                          ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0                    -     @5036
+  FSPCHG_PRDCNT                                uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h86 (Mirror: 8'h00)
+  REFRCNT                                      uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x86, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+        P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_AC_TIME_05T_0                              ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0                        -     @5199
+  TRC_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[0:0]=1'h0
+  TRFCPB_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[1:1]=1'h0
+  TRFC_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[2:2]=1'h1 (Mirror: 1'h0)
+  TPBR2PBR_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[3:3]=1'h0
+  TXP_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[4:4]=1'h1 (Mirror: 1'h0)
+  TRTP_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[5:5]=1'h1 (Mirror: 1'h0)
+  TRCD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[6:6]=1'h0
+  TRP_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[7:7]=1'h1 (Mirror: 1'h0)
+  TRPAB_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[8:8]=1'h0
+  TRAS_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[9:9]=1'h0
+  TWR_M05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[10:10]=1'h0
+  TRRD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[12:12]=1'h1 (Mirror: 1'h0)
+  TFAW_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[13:13]=1'h1 (Mirror: 1'h0)
+  TCKEPRD_05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[14:14]=1'h0
+  TR2PD_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[15:15]=1'h1 (Mirror: 1'h0)
+  TWTPD_M05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[16:16]=1'h0
+  TMRRI_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[17:17]=1'h0
+  TMRWCKEL_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[18:18]=1'h1 (Mirror: 1'h0)
+  BGTRRD_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[19:19]=1'h0
+  BGTCCD_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[20:20]=1'h0
+  BGTWTR_M05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[21:21]=1'h1 (Mirror: 1'h0)
+  TR2W_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[22:22]=1'h0
+  TWTR_M05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[23:23]=1'h1 (Mirror: 1'h0)
+  XRTR2W_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[24:24]=1'h0
+  TMRD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[25:25]=1'h1 (Mirror: 1'h0)
+  TMRW_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[26:26]=1'h1 (Mirror: 1'h0)
+  TMRR2MRW_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[27:27]=1'h0
+  TW2MRW_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[28:28]=1'h0
+  TR2MRW_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[29:29]=1'h0
+  TPBR2ACT_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[30:30]=1'h0
+  XRTW2R_M05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRFC_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TXP_05T) |
+        P_Fld(0x1, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRCD_05T) |
+        P_Fld(0x1, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TWR_M05T) |
+        P_Fld(0x1, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TFAW_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TR2PD_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRRI_05T) |
+        P_Fld(0x1, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_BGTWTR_M05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTR_M05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRD_05T) |
+        P_Fld(0x1, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRR2MRW_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM_XRT_0                                ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0                          -     @5192
+  XRTR2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[4:0]=5'h03 (Mirror: 5'h01)
+  XRTR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[13:8]=6'h08 (Mirror: 6'h01)
+  XRTW2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[19:16]=4'h1
+  XRTW2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[28:24]=5'h05 (Mirror: 5'h01)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x03, SHU_ACTIM_XRT_XRTR2R) |
+        P_Fld(0x08, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x1, SHU_ACTIM_XRT_XRTW2R) |
+        P_Fld(0x05, SHU_ACTIM_XRT_XRTW2W));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM0_0                                   ral_reg_DRAMC_blk_SHU_ACTIM0_0                             -     @5138
+  TWTR                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[3:0]=4'ha (Mirror: 4'h1)
+  CKELCKCNT                                    uvm_reg_field                                              ...    RW SHU_ACTIM0_0[6:4]=3'h3 (Mirror: 3'h0)
+  TWR                                          uvm_reg_field                                              ...    RW SHU_ACTIM0_0[15:8]=8'h10 (Mirror: 8'h06)
+  TRRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[18:16]=3'h4 (Mirror: 3'h0)
+  TRCD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[27:24]=4'ha (Mirror: 4'h2)
+  TWTR_L                                       uvm_reg_field                                              ...    RW SHU_ACTIM0_0[31:28]=4'hc (Mirror: 4'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+#if (fcFOR_CHIP_ID == fcA60868)
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0xa, SHU_ACTIM0_TWTR) |
+        P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x10, SHU_ACTIM0_TWR) |
+        P_Fld(0x4, SHU_ACTIM0_TRRD) | P_Fld(0xa, SHU_ACTIM0_TRCD) |
+        P_Fld(0xc, SHU_ACTIM0_TWTR_L));
+#elif (fcFOR_CHIP_ID == fcPetrus)
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0xa, SHU_ACTIM0_TWTR) |
+        P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x10, SHU_ACTIM0_TWR) |
+        P_Fld(0x4, SHU_ACTIM0_TRRD) | P_Fld(0xa, SHU_ACTIM0_TRCD));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM1_0                                   ral_reg_DRAMC_blk_SHU_ACTIM1_0                             -     @5147
+  TRPAB                                        uvm_reg_field                                              ...    RW SHU_ACTIM1_0[3:0]=4'ha
+  TMRWCKEL                                     uvm_reg_field                                              ...    RW SHU_ACTIM1_0[7:4]=4'h8
+  TRP                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[11:8]=4'h8 (Mirror: 4'h2)
+  TRAS                                         uvm_reg_field                                              ...    RW SHU_ACTIM1_0[21:16]=6'h0e (Mirror: 6'h04)
+  TRC                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[28:24]=5'h19 (Mirror: 5'h05)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0xa, SHU_ACTIM1_TRPAB) |
+        P_Fld(0x8, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x8, SHU_ACTIM1_TRP) |
+        P_Fld(0x0e, SHU_ACTIM1_TRAS) | P_Fld(0x19, SHU_ACTIM1_TRC));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM2_0                                   ral_reg_DRAMC_blk_SHU_ACTIM2_0                             -     @5155
+  TXP                                          uvm_reg_field                                              ...    RW SHU_ACTIM2_0[3:0]=4'h2 (Mirror: 4'h0)
+  TMRRI                                        uvm_reg_field                                              ...    RW SHU_ACTIM2_0[8:4]=5'h0e
+  TRTP                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[14:12]=3'h3 (Mirror: 3'h0)
+  TR2W                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[21:16]=6'h09 (Mirror: 6'h00)
+  TFAW                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[28:24]=5'h0d (Mirror: 5'h05)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x2, SHU_ACTIM2_TXP) |
+        P_Fld(0x0e, SHU_ACTIM2_TMRRI) | P_Fld(0x3, SHU_ACTIM2_TRTP) |
+        P_Fld(0x09, SHU_ACTIM2_TR2W) | P_Fld(0x0d, SHU_ACTIM2_TFAW));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM3_0                                   ral_reg_DRAMC_blk_SHU_ACTIM3_0                             -     @5163
+  TRFCPB                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[7:0]=8'h3f (Mirror: 8'h00)
+  MANTMRR                                      uvm_reg_field                                              ...    RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0)
+  TR2MRR                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0)
+  TRFC                                         uvm_reg_field                                              ...    RW SHU_ACTIM3_0[23:16]=8'h89 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x3f, SHU_ACTIM3_TRFCPB) |
+        P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) |
+        P_Fld(0x89, SHU_ACTIM3_TRFC));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM4_0                                   ral_reg_DRAMC_blk_SHU_ACTIM4_0                             -     @5170
+  TXREFCNT                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[9:0]=10'h09a (Mirror: 10'h028)
+  TMRR2MRW                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[15:10]=6'h0f (Mirror: 6'h00)
+  TMRR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM4_0[21:16]=6'h0b (Mirror: 6'h00)
+  TZQCS                                        uvm_reg_field                                              ...    RW SHU_ACTIM4_0[31:24]=8'h2e (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x09a, SHU_ACTIM4_TXREFCNT) |
+        P_Fld(0x0f, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0b, SHU_ACTIM4_TMRR2W) |
+        P_Fld(0x2e, SHU_ACTIM4_TZQCS));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM5_0                                   ral_reg_DRAMC_blk_SHU_ACTIM5_0                             -     @5177
+  TR2PD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[6:0]=7'h0f (Mirror: 7'h00)
+  TWTPD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[14:8]=7'h12 (Mirror: 7'h00)
+  TPBR2PBR                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[23:16]=8'h30 (Mirror: 8'h00)
+  TPBR2ACT                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[29:28]=2'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x0f, SHU_ACTIM5_TR2PD) |
+        P_Fld(0x12, SHU_ACTIM5_TWTPD) | P_Fld(0x30, SHU_ACTIM5_TPBR2PBR) |
+        P_Fld(0x0, SHU_ACTIM5_TPBR2ACT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM6_0                                   ral_reg_DRAMC_blk_SHU_ACTIM6_0                             -     @5184
+  TZQLAT2                                      uvm_reg_field                                              ...    RW SHU_ACTIM6_0[4:0]=5'h10 (Mirror: 5'h1f)
+  TMRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[11:8]=4'h7 (Mirror: 4'h0)
+  TMRW                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0)
+  TW2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[25:20]=6'h0b (Mirror: 6'h00)
+  TR2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[31:26]=6'h12 (Mirror: 6'h13)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x10, SHU_ACTIM6_TZQLAT2) |
+        P_Fld(0x7, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) |
+        P_Fld(0x0b, SHU_ACTIM6_TW2MRW) | P_Fld(0x12, SHU_ACTIM6_TR2MRW));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_CKECTRL_0                                  ral_reg_DRAMC_blk_SHU_CKECTRL_0                            -     @5262
+  TPDE_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0)
+  TPDX_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[1:1]=1'h0
+  TPDE                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[14:12]=3'h1
+  TPDX                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[18:16]=3'h1
+  TCKEPRD                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[22:20]=3'h4 (Mirror: 3'h2)
+  TCKESRX                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) |
+        P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) |
+        P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x4, SHU_CKECTRL_TCKEPRD) |
+        P_Fld(0x3, SHU_CKECTRL_TCKESRX));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_0                                     ral_reg_DRAMC_blk_SHU_MISC_0                               -     @5365
+  REQQUE_MAXCNT                                uvm_reg_field                                              ...    RW SHU_MISC_0[3:0]=4'h2
+  DCMDLYREF                                    uvm_reg_field                                              ...    RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4)
+  DAREFEN                                      uvm_reg_field                                              ...    RW SHU_MISC_0[30:30]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) |
+        P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_TX_PIPE_CTRL_0                        ral_reg_DDRPHY_blk_SHU_MISC_TX_PIPE_CTRL_0                 -     @12708
+  CMD_TXPIPE_BYPASS_EN                         uvm_reg_field                                              ...    RW SHU_MISC_TX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0)
+  CK_TXPIPE_BYPASS_EN                          uvm_reg_field                                              ...    RW SHU_MISC_TX_PIPE_CTRL_0[1:1]=1'h1 (Mirror: 1'h0)
+  TX_PIPE_BYPASS_EN                            uvm_reg_field                                              ...    RW SHU_MISC_TX_PIPE_CTRL_0[2:2]=1'h0
+  CS_TXPIPE_BYPASS_EN                          uvm_reg_field                                              ...    RW SHU_MISC_TX_PIPE_CTRL_0[3:3]=1'h1 (Mirror: 1'h0)
+  SKIP_TXPIPE_BYPASS                           uvm_reg_field                                              ...    RW SHU_MISC_TX_PIPE_CTRL_0[8:8]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_TX_PIPE_CTRL, P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CMD_TXPIPE_BYPASS_EN) |
+        P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CK_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_TX_PIPE_BYPASS_EN) |
+        P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CS_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_SKIP_TXPIPE_BYPASS));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter.
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit.
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ8_0                            -     @7828
+  R_DMRXDVS_UPD_FORCE_CYC_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000)
+  R_DMRXDVS_UPD_FORCE_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[15:15]=1'h0
+  R_DMRANK_RXDLY_PIPE_CG_IG_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[19:19]=1'h0
+  R_RMRODTEN_CG_IG_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[20:20]=1'h0
+  R_RMRX_TOPHY_CG_IG_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)
+  R_DMRXDVS_RDSEL_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[22:22]=1'h0
+  R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0            uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[23:23]=1'h0
+  R_DMRXDLY_CG_IG_B0                           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)
+  R_DMDQSIEN_FLAG_SYNC_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[26:26]=1'h0
+  R_DMDQSIEN_FLAG_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[27:27]=1'h0
+  R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0               uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[28:28]=1'h0
+  R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[29:29]=1'h0
+  R_DMRANK_PIPE_CG_IG_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[30:30]=1'h0
+  R_DMRANK_CHG_PIPE_CG_IG_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+        P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ8_0                            -     @9231
+  R_DMRXDVS_UPD_FORCE_CYC_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000)
+  R_DMRXDVS_UPD_FORCE_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[15:15]=1'h0
+  R_DMRANK_RXDLY_PIPE_CG_IG_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[19:19]=1'h0
+  R_RMRODTEN_CG_IG_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[20:20]=1'h0
+  R_RMRX_TOPHY_CG_IG_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)
+  R_DMRXDVS_RDSEL_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[22:22]=1'h0
+  R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1            uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[23:23]=1'h0
+  R_DMRXDLY_CG_IG_B1                           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)
+  R_DMDQSIEN_FLAG_SYNC_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[26:26]=1'h0
+  R_DMDQSIEN_FLAG_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[27:27]=1'h0
+  R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1               uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[28:28]=1'h0
+  R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[29:29]=1'h0
+  R_DMRANK_PIPE_CG_IG_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[30:30]=1'h0
+  R_DMRANK_CHG_PIPE_CG_IG_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+        P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ5_0                            -     @7728
+  RG_RX_ARDQ_VREF_SEL_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[5:0]=6'h0e
+  RG_RX_ARDQ_VREF_BYPASS_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[6:6]=1'h0
+  RG_ARPI_FB_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[13:8]=6'h00
+  RG_RX_ARDQS0_DQSIEN_DLY_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[18:16]=3'h0
+  RG_RX_ARDQS_DQSIEN_RB_DLY_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[19:19]=1'h0
+  RG_RX_ARDQS0_DVS_DLY_B0                      uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[23:20]=4'h3 (Mirror: 4'h0)
+  RG_RX_ARDQ_FIFO_DQSI_DLY_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[31:29]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) |
+        P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) |
+        P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) |
+        P_Fld(0x3, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ5_0                            -     @9131
+  RG_RX_ARDQ_VREF_SEL_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[5:0]=6'h0e
+  RG_RX_ARDQ_VREF_BYPASS_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[6:6]=1'h0
+  RG_ARPI_FB_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[13:8]=6'h00
+  RG_RX_ARDQS0_DQSIEN_DLY_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[18:16]=3'h0
+  RG_RX_ARDQS_DQSIEN_RB_DLY_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[19:19]=1'h0
+  RG_RX_ARDQS0_DVS_DLY_B1                      uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[23:20]=4'h3 (Mirror: 4'h0)
+  RG_RX_ARDQ_FIFO_DQSI_DLY_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[31:29]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) |
+        P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) |
+        P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) |
+        P_Fld(0x3, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0                    -     @7490
+  RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h6f (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x6f, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+        P_Fld(0x6f, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
+        P_Fld(0x6f, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0                    -     @7504
+  RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h6f (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x6f, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+        P_Fld(0x6f, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+        P_Fld(0x6f, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0                    -     @7518
+  RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h6f (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x6f, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+        P_Fld(0x6f, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+        P_Fld(0x6f, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0                    -     @7532
+  RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h6f (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x6f, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+        P_Fld(0x6f, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+        P_Fld(0x6f, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0                    -     @7546
+  RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h6f (Mirror: 8'h00)
+  RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h6f (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x6f, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+        P_Fld(0x6f, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0                    -     @7556
+  RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h02f (Mirror: 9'h000)
+  RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h02f (Mirror: 9'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x02f, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+        P_Fld(0x02f, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1                    -     @7497
+  RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h6e (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+        P_Fld(0x6e, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
+        P_Fld(0x6e, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1                    -     @7511
+  RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h6e (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+        P_Fld(0x6e, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+        P_Fld(0x6e, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1                    -     @7525
+  RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h6e (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+        P_Fld(0x6e, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+        P_Fld(0x6e, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1                    -     @7539
+  RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h6e (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+        P_Fld(0x6e, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+        P_Fld(0x6e, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1                    -     @7551
+  RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h6e (Mirror: 8'h00)
+  RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h6e (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+        P_Fld(0x6e, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1                    -     @7561
+  RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h02e (Mirror: 9'h000)
+  RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h02e (Mirror: 9'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x02e, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+        P_Fld(0x02e, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0                    -     @8893
+  RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h6f (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x6f, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+        P_Fld(0x6f, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
+        P_Fld(0x6f, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0                    -     @8907
+  RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h6f (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x6f, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+        P_Fld(0x6f, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+        P_Fld(0x6f, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0                    -     @8921
+  RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h6f (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x6f, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+        P_Fld(0x6f, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+        P_Fld(0x6f, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0                    -     @8935
+  RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h6f (Mirror: 8'h00)
+  RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h6f (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x6f, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+        P_Fld(0x6f, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+        P_Fld(0x6f, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0                    -     @8949
+  RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h6f (Mirror: 8'h00)
+  RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h6f (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x6f, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+        P_Fld(0x6f, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0                    -     @8959
+  RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h02f (Mirror: 9'h000)
+  RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h02f (Mirror: 9'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x02f, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+        P_Fld(0x02f, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1                    -     @8900
+  RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h6e (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+        P_Fld(0x6e, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
+        P_Fld(0x6e, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1                    -     @8914
+  RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h6e (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+        P_Fld(0x6e, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+        P_Fld(0x6e, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1                    -     @8928
+  RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h6e (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+        P_Fld(0x6e, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+        P_Fld(0x6e, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1                    -     @8942
+  RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h6e (Mirror: 8'h00)
+  RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h6e (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+        P_Fld(0x6e, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+        P_Fld(0x6e, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1                    -     @8954
+  RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h6e (Mirror: 8'h00)
+  RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h6e (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+        P_Fld(0x6e, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1                    -     @8964
+  RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h02e (Mirror: 9'h000)
+  RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h02e (Mirror: 9'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x02e, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+        P_Fld(0x02e, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B0_DQ9                                         ral_reg_DDRPHY_blk_B0_DQ9                                  -     @7384
+  RG_RX_ARDQ_STBEN_RESETB_B0                   uvm_reg_field                                              ...    RW B0_DQ9[0:0]=1'h0 (Mirror: 1'h1)
+  RG_RX_ARDQS0_STBEN_RESETB_B0                 uvm_reg_field                                              ...    RW B0_DQ9[4:4]=1'h1
+  RG_RX_ARDQS0_DQSIENMODE_B0                   uvm_reg_field                                              ...    RW B0_DQ9[5:5]=1'h0
+  R_DMRXDVS_R_F_DLY_RK_OPT_B0                  uvm_reg_field                                              ...    RW B0_DQ9[6:6]=1'h1
+  R_DMRXFIFO_STBENCMP_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ9[7:7]=1'h0
+  R_IN_GATE_EN_LOW_OPT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[15:8]=8'h00
+  R_DMDQSIEN_VALID_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[18:16]=3'h0
+  R_DMDQSIEN_RDSEL_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[22:20]=3'h0
+  R_DMRXDVS_VALID_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[26:24]=3'h0
+  R_DMRXDVS_RDSEL_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[30:28]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
+        P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
+        P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
+        P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
+        P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
+        P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B1_DQ9                                         ral_reg_DDRPHY_blk_B1_DQ9                                  -     @8787
+  RG_RX_ARDQ_STBEN_RESETB_B1                   uvm_reg_field                                              ...    RW B1_DQ9[0:0]=1'h0 (Mirror: 1'h1)
+  RG_RX_ARDQS0_STBEN_RESETB_B1                 uvm_reg_field                                              ...    RW B1_DQ9[4:4]=1'h1
+  RG_RX_ARDQS0_DQSIENMODE_B1                   uvm_reg_field                                              ...    RW B1_DQ9[5:5]=1'h0
+  R_DMRXDVS_R_F_DLY_RK_OPT_B1                  uvm_reg_field                                              ...    RW B1_DQ9[6:6]=1'h1
+  R_DMRXFIFO_STBENCMP_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ9[7:7]=1'h0
+  R_IN_GATE_EN_LOW_OPT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[15:8]=8'h00
+  R_DMDQSIEN_VALID_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[18:16]=3'h0
+  R_DMDQSIEN_RDSEL_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[22:20]=3'h0
+  R_DMRXDVS_VALID_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[26:24]=3'h0
+  R_DMRXDVS_RDSEL_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[30:28]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
+        P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
+        P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
+        P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
+        P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
+        P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B0_DQ9                                         ral_reg_DDRPHY_blk_B0_DQ9                                  -     @7384
+  RG_RX_ARDQ_STBEN_RESETB_B0                   uvm_reg_field                                              ...    RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0)
+  RG_RX_ARDQS0_STBEN_RESETB_B0                 uvm_reg_field                                              ...    RW B0_DQ9[4:4]=1'h1
+  RG_RX_ARDQS0_DQSIENMODE_B0                   uvm_reg_field                                              ...    RW B0_DQ9[5:5]=1'h0
+  R_DMRXDVS_R_F_DLY_RK_OPT_B0                  uvm_reg_field                                              ...    RW B0_DQ9[6:6]=1'h1
+  R_DMRXFIFO_STBENCMP_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ9[7:7]=1'h0
+  R_IN_GATE_EN_LOW_OPT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[15:8]=8'h00
+  R_DMDQSIEN_VALID_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[18:16]=3'h0
+  R_DMDQSIEN_RDSEL_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[22:20]=3'h0
+  R_DMRXDVS_VALID_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[26:24]=3'h0
+  R_DMRXDVS_RDSEL_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[30:28]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
+        P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
+        P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
+        P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
+        P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
+        P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B1_DQ9                                         ral_reg_DDRPHY_blk_B1_DQ9                                  -     @8787
+  RG_RX_ARDQ_STBEN_RESETB_B1                   uvm_reg_field                                              ...    RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0)
+  RG_RX_ARDQS0_STBEN_RESETB_B1                 uvm_reg_field                                              ...    RW B1_DQ9[4:4]=1'h1
+  RG_RX_ARDQS0_DQSIENMODE_B1                   uvm_reg_field                                              ...    RW B1_DQ9[5:5]=1'h0
+  R_DMRXDVS_R_F_DLY_RK_OPT_B1                  uvm_reg_field                                              ...    RW B1_DQ9[6:6]=1'h1
+  R_DMRXFIFO_STBENCMP_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ9[7:7]=1'h0
+  R_IN_GATE_EN_LOW_OPT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[15:8]=8'h00
+  R_DMDQSIEN_VALID_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[18:16]=3'h0
+  R_DMDQSIEN_RDSEL_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[22:20]=3'h0
+  R_DMRXDVS_VALID_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[26:24]=3'h0
+  R_DMRXDVS_RDSEL_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[30:28]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
+        P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
+        P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
+        P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
+        P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
+        P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B0_DQ4                                         ral_reg_DDRPHY_blk_B0_DQ4                                  -     @7313
+  RG_RX_ARDQS_EYE_R_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[6:0]=7'h75 (Mirror: 7'h00)
+  RG_RX_ARDQS_EYE_F_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[14:8]=7'h75 (Mirror: 7'h00)
+  RG_RX_ARDQ_EYE_R_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[21:16]=6'h2f (Mirror: 6'h00)
+  RG_RX_ARDQ_EYE_F_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[29:24]=6'h2f (Mirror: 6'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x75, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) |
+        P_Fld(0x75, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x2f, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) |
+        P_Fld(0x2f, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B1_DQ4                                         ral_reg_DDRPHY_blk_B1_DQ4                                  -     @8716
+  RG_RX_ARDQS_EYE_R_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[6:0]=7'h75 (Mirror: 7'h00)
+  RG_RX_ARDQS_EYE_F_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[14:8]=7'h75 (Mirror: 7'h00)
+  RG_RX_ARDQ_EYE_R_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[21:16]=6'h2f (Mirror: 6'h00)
+  RG_RX_ARDQ_EYE_F_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[29:24]=6'h2f (Mirror: 6'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x75, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) |
+        P_Fld(0x75, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x2f, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) |
+        P_Fld(0x2f, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B0_DQ5                                         ral_reg_DDRPHY_blk_B0_DQ5                                  -     @7320
+  RG_RX_ARDQ_EYE_VREF_SEL_B0                   uvm_reg_field                                              ...    RW B0_DQ5[13:8]=6'h10
+  RG_RX_ARDQ_VREF_EN_B0                        uvm_reg_field                                              ...    RW B0_DQ5[16:16]=1'h1
+  RG_RX_ARDQ_EYE_VREF_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ5[17:17]=1'h1
+  RG_RX_ARDQ_EYE_SEL_B0                        uvm_reg_field                                              ...    RW B0_DQ5[23:20]=4'h0
+  RG_RX_ARDQ_EYE_EN_B0                         uvm_reg_field                                              ...    RW B0_DQ5[24:24]=1'h1
+  RG_RX_ARDQ_EYE_STBEN_RESETB_B0               uvm_reg_field                                              ...    RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0)
+  RG_RX_ARDQS0_DVS_EN_B0                       uvm_reg_field                                              ...    RW B0_DQ5[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x10, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) |
+        P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) |
+        P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) |
+        P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B1_DQ5                                         ral_reg_DDRPHY_blk_B1_DQ5                                  -     @8723
+  RG_RX_ARDQ_EYE_VREF_SEL_B1                   uvm_reg_field                                              ...    RW B1_DQ5[13:8]=6'h10
+  RG_RX_ARDQ_VREF_EN_B1                        uvm_reg_field                                              ...    RW B1_DQ5[16:16]=1'h1
+  RG_RX_ARDQ_EYE_VREF_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ5[17:17]=1'h1
+  RG_RX_ARDQ_EYE_SEL_B1                        uvm_reg_field                                              ...    RW B1_DQ5[23:20]=4'h0
+  RG_RX_ARDQ_EYE_EN_B1                         uvm_reg_field                                              ...    RW B1_DQ5[24:24]=1'h1
+  RG_RX_ARDQ_EYE_STBEN_RESETB_B1               uvm_reg_field                                              ...    RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0)
+  RG_RX_ARDQS0_DVS_EN_B1                       uvm_reg_field                                              ...    RW B1_DQ5[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x10, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) |
+        P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) |
+        P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) |
+        P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Enter
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_COMMON0_0                                  ral_reg_DRAMC_blk_SHU_COMMON0_0                            -     @5001
+  FREQDIV4                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[0:0]=1'h1 (Mirror: 1'h0)
+  FDIV2                                        uvm_reg_field                                              ...    RW SHU_COMMON0_0[1:1]=1'h0
+  FREQDIV8                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[2:2]=1'h0
+  DM64BITEN                                    uvm_reg_field                                              ...    RW SHU_COMMON0_0[4:4]=1'h1 (Mirror: 1'h0)
+  DLE256EN                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[5:5]=1'h0
+  LP5BGEN                                      uvm_reg_field                                              ...    RW SHU_COMMON0_0[6:6]=1'h0
+  LP5WCKON                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[7:7]=1'h0
+  CL2                                          uvm_reg_field                                              ...    RW SHU_COMMON0_0[8:8]=1'h0
+  BL2                                          uvm_reg_field                                              ...    RW SHU_COMMON0_0[9:9]=1'h0
+  BL4                                          uvm_reg_field                                              ...    RW SHU_COMMON0_0[10:10]=1'h1 (Mirror: 1'h0)
+  LP5BGOTF                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[11:11]=1'h0
+  BC4OTF                                       uvm_reg_field                                              ...    RW SHU_COMMON0_0[12:12]=1'h1
+  LP5HEFF_MODE                                 uvm_reg_field                                              ...    RW SHU_COMMON0_0[13:13]=1'h0
+  SHU_COMMON0_RSV                              uvm_reg_field                                              ...    RW SHU_COMMON0_0[31:15]=17'h00000
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0, P_Fld(0x1, SHU_COMMON0_FREQDIV4) |
+        P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x0, SHU_COMMON0_FREQDIV8) |
+        P_Fld(0x1, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) |
+        P_Fld(0x0, SHU_COMMON0_LP5BGEN) | P_Fld(0x0, SHU_COMMON0_LP5WCKON) |
+        P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) |
+        P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) |
+        P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x0, SHU_COMMON0_LP5HEFF_MODE) |
+        P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIMING_CONF_0                            ral_reg_DRAMC_blk_SHU_ACTIMING_CONF_0                      -     @5255
+  SCINTV                                       uvm_reg_field                                              ...    RW SHU_ACTIMING_CONF_0[5:0]=6'h26 (Mirror: 6'h2a)
+  TRFCPBIG                                     uvm_reg_field                                              ...    RW SHU_ACTIMING_CONF_0[8:8]=1'h0
+  REFBW_FR                                     uvm_reg_field                                              ...    RW SHU_ACTIMING_CONF_0[25:16]=10'h000
+  TREFBWIG                                     uvm_reg_field                                              ...    RW SHU_ACTIMING_CONF_0[31:31]=1'h1 (Mirror: 1'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF, P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) |
+        P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) |
+        P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_DCM_CTRL0_0                                ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0                          -     @5027
+  DDRPHY_CLK_EN_OPT                            uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[7:7]=1'h1
+  DPHY_CMDDCM_EXTCNT                           uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[11:8]=4'h4
+  DDRPHY_CLK_DYN_GATING_SEL                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[15:12]=4'h5
+  CKE_EXTNONPD_CNT                             uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[19:16]=4'h0
+  FASTWAKE2                                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[29:29]=1'h1 (Mirror: 1'h0)
+  FASTWAKE                                     uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[31:31]=1'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+#if (fcFOR_CHIP_ID == fcA60868)
+vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+        P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+        P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) |
+        P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+#elif (fcFOR_CHIP_ID == fcPetrus)
+vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+        P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+        P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) |
+        P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_CONF0_0                                    ral_reg_DRAMC_blk_SHU_CONF0_0                              -     @5356
+  DMPGTIM                                      uvm_reg_field                                              ...    RW SHU_CONF0_0[5:0]=6'h3f (Mirror: 6'h08)
+  ADVREFEN                                     uvm_reg_field                                              ...    RW SHU_CONF0_0[6:6]=1'h0
+  ADVPREEN                                     uvm_reg_field                                              ...    RW SHU_CONF0_0[7:7]=1'h1 (Mirror: 1'h0)
+  PBREFEN                                      uvm_reg_field                                              ...    RW SHU_CONF0_0[8:8]=1'h1 (Mirror: 1'h0)
+  REFTHD                                       uvm_reg_field                                              ...    RW SHU_CONF0_0[15:12]=4'h1 (Mirror: 4'h0)
+  REQQUE_DEPTH                                 uvm_reg_field                                              ...    RW SHU_CONF0_0[19:16]=4'h8
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x3f, SHU_CONF0_DMPGTIM) |
+        P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) |
+        P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) |
+        P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MATYPE_0                                   ral_reg_DRAMC_blk_SHU_MATYPE_0                             -     @4996
+  MATYPE                                       uvm_reg_field                                              ...    RW SHU_MATYPE_0[1:0]=2'h2 (Mirror: 2'h0)
+  NORMPOP_LEN                                  uvm_reg_field                                              ...    RW SHU_MATYPE_0[6:4]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE, P_Fld(0x2, SHU_MATYPE_MATYPE) |
+        P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SCHEDULER_0                                ral_reg_DRAMC_blk_SHU_SCHEDULER_0                          -     @5023
+  DUALSCHEN                                    uvm_reg_field                                              ...    RW SHU_SCHEDULER_0[2:2]=1'h1 (Mirror: 1'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DRAMC_REG_SHU_SCHEDULER, 0x1, SHU_SCHEDULER_DUALSCHEN);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+TX_SET0                                        ral_reg_DRAMC_blk_TX_SET0                                  -     @3899
+  TXRANK                                       uvm_reg_field                                              ...    RW TX_SET0[1:0]=2'h0
+  TXRANKFIX                                    uvm_reg_field                                              ...    RW TX_SET0[2:2]=1'h0
+  DDRPHY_COMB_CG_SEL                           uvm_reg_field                                              ...    RW TX_SET0[3:3]=1'h0
+  TX_DQM_DEFAULT                               uvm_reg_field                                              ...    RW TX_SET0[4:4]=1'h1
+  DQBUS_X32                                    uvm_reg_field                                              ...    RW TX_SET0[5:5]=1'h0
+  OE_DOWNGRADE                                 uvm_reg_field                                              ...    RW TX_SET0[6:6]=1'h0
+  DQ16COM1                                     uvm_reg_field                                              ...    RW TX_SET0[21:21]=1'h0
+  WPRE2T                                       uvm_reg_field                                              ...    RW TX_SET0[22:22]=1'h1 (Mirror: 1'h0)
+  DRSCLR_EN                                    uvm_reg_field                                              ...    RW TX_SET0[24:24]=1'h0
+  DRSCLR_RK0_EN                                uvm_reg_field                                              ...    RW TX_SET0[25:25]=1'h0
+  ARPI_CAL_E2OPT                               uvm_reg_field                                              ...    RW TX_SET0[26:26]=1'h0
+  TX_DLY_CAL_E2OPT                             uvm_reg_field                                              ...    RW TX_SET0[27:27]=1'h0
+  DQS_OE_OP1_DIS                               uvm_reg_field                                              ...    RW TX_SET0[28:28]=1'h0
+  DQS_OE_OP2_EN                                uvm_reg_field                                              ...    RW TX_SET0[29:29]=1'h0
+  RK_SCINPUT_OPT                               uvm_reg_field                                              ...    RW TX_SET0[30:30]=1'h0
+  DRAMOEN                                      uvm_reg_field                                              ...    RW TX_SET0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_TX_SET0, P_Fld(0x0, TX_SET0_TXRANK) |
+        P_Fld(0x0, TX_SET0_TXRANKFIX) | P_Fld(0x0, TX_SET0_DDRPHY_COMB_CG_SEL) |
+        P_Fld(0x1, TX_SET0_TX_DQM_DEFAULT) | P_Fld(0x0, TX_SET0_DQBUS_X32) |
+        P_Fld(0x0, TX_SET0_OE_DOWNGRADE) | P_Fld(0x0, TX_SET0_DQ16COM1) |
+        P_Fld(0x1, TX_SET0_WPRE2T) | P_Fld(0x0, TX_SET0_DRSCLR_EN) |
+        P_Fld(0x0, TX_SET0_DRSCLR_RK0_EN) | P_Fld(0x0, TX_SET0_ARPI_CAL_E2OPT) |
+        P_Fld(0x0, TX_SET0_TX_DLY_CAL_E2OPT) | P_Fld(0x0, TX_SET0_DQS_OE_OP1_DIS) |
+        P_Fld(0x0, TX_SET0_DQS_OE_OP2_EN) | P_Fld(0x0, TX_SET0_RK_SCINPUT_OPT) |
+        P_Fld(0x0, TX_SET0_DRAMOEN));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_TX_SET0_0                                  ral_reg_DRAMC_blk_SHU_TX_SET0_0                            -     @5306
+  DQOE_CNT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[3:0]=4'h0
+  DQOE_OPT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[4:4]=1'h0
+  TXUPD_SEL                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[7:6]=2'h0
+  TXUPD_W2R_SEL                                uvm_reg_field                                              ...    RW SHU_TX_SET0_0[10:8]=3'h2 (Mirror: 3'h0)
+  WECC_EN                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[11:11]=1'h0
+  DBIWR                                        uvm_reg_field                                              ...    RW SHU_TX_SET0_0[12:12]=1'h0
+  WDATRGO                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[13:13]=1'h0
+  TWPSTEXT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[14:14]=1'h0
+  WPST1P5T                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[15:15]=1'h1 (Mirror: 1'h0)
+  TXOEN_AUTOSET_OFFSET                         uvm_reg_field                                              ...    RW SHU_TX_SET0_0[19:16]=4'h3
+  TWCKPST                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[21:20]=2'h1
+  OE_EXT2UI                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[24:22]=3'h1 (Mirror: 3'h0)
+  DQS2DQ_FILT_PITHRD                           uvm_reg_field                                              ...    RW SHU_TX_SET0_0[30:25]=6'h0e
+  TXOEN_AUTOSET_EN                             uvm_reg_field                                              ...    RW SHU_TX_SET0_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+#if (fcFOR_CHIP_ID == fcA60868)
+vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+        P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+        P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+        P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+        P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
+        P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+        P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+        P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+#elif (fcFOR_CHIP_ID == fcPetrus)
+vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+        P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+        P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+        P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+        P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
+        P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+        P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+        P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_STBCAL1_0                             ral_reg_DDRPHY_blk_MISC_SHU_STBCAL1_0                      -     @12514
+  DLLFRZRFCOPT                                 uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[1:0]=2'h0
+  DLLFRZWROPT                                  uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[5:4]=2'h0
+  r_rstbcnt_latch_opt                          uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[10:8]=3'h0
+  STB_UPDMASK_EN                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[11:11]=1'h1 (Mirror: 1'h0)
+  STB_UPDMASKCYC                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[15:12]=4'h9 (Mirror: 4'h0)
+  DQSINCTL_PRE_SEL                             uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[16:16]=1'h1 (Mirror: 1'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1, P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) |
+        P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) |
+        P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) |
+        P_Fld(0x1, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_STBCAL_0                              ral_reg_DDRPHY_blk_MISC_SHU_STBCAL_0                       -     @12499
+  DMSTBLAT                                     uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[3:0]=4'h2 (Mirror: 4'h0)
+  PICGLAT                                      uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[6:4]=3'h1 (Mirror: 3'h0)
+  DQSG_MODE                                    uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[8:8]=1'h1 (Mirror: 1'h0)
+  DQSIEN_PICG_MODE                             uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[9:9]=1'h1 (Mirror: 1'h0)
+  DQSIEN_DQSSTB_MODE                           uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[13:12]=2'h1
+  DQSIEN_BURST_MODE                            uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[14:14]=1'h1
+  DQSIEN_SELPH_FRUN                            uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[15:15]=1'h0
+  STBCALEN                                     uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[16:16]=1'h1 (Mirror: 1'h0)
+  STB_SELPHCALEN                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[17:17]=1'h1 (Mirror: 1'h0)
+  DQSIEN_4TO1_EN                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[20:20]=1'h0
+  DQSIEN_8TO1_EN                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[21:21]=1'h0
+  DQSIEN_16TO1_EN                              uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[22:22]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL, P_Fld(0x2, MISC_SHU_STBCAL_DMSTBLAT) |
+        P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) |
+        P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) |
+        P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) |
+        P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) |
+        P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) |
+        P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RODTENSTB_0                           ral_reg_DDRPHY_blk_MISC_SHU_RODTENSTB_0                    -     @12562
+  RODTENSTB_TRACK_EN                           uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[0:0]=1'h1 (Mirror: 1'h0)
+  RODTEN_P1_ENABLE                             uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[1:1]=1'h0
+  RODTENSTB_4BYTE_EN                           uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[2:2]=1'h0
+  RODTENSTB_TRACK_UDFLWCTRL                    uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[3:3]=1'h1 (Mirror: 1'h0)
+  RODTENSTB_SELPH_MODE                         uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[4:4]=1'h1
+  RODTENSTB_SELPH_BY_BITTIME                   uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[5:5]=1'h0
+  RODTENSTB__UI_OFFSET                         uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[11:8]=4'h4 (Mirror: 4'h0)
+  RODTENSTB_MCK_OFFSET                         uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[15:12]=4'h0
+  RODTENSTB_EXT                                uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[31:16]=16'h0008 (Mirror: 16'h0000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) |
+        P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) |
+        P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) |
+        P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x4, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) |
+        P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RX_SELPH_MODE_0                       ral_reg_DDRPHY_blk_MISC_SHU_RX_SELPH_MODE_0                -     @12751
+  DQSIEN_SELPH_SERMODE                         uvm_reg_field                                              ...    RW MISC_SHU_RX_SELPH_MODE_0[1:0]=2'h2 (Mirror: 2'h0)
+  RODT_SELPH_SERMODE                           uvm_reg_field                                              ...    RW MISC_SHU_RX_SELPH_MODE_0[5:4]=2'h1 (Mirror: 2'h0)
+  RANK_SELPH_SERMODE                           uvm_reg_field                                              ...    RW MISC_SHU_RX_SELPH_MODE_0[7:6]=2'h1 (Mirror: 2'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE, P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) |
+        P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Exit
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Enter
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ7_0                            -     @7808
+  R_DMRANKRXDVS_B0                             uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[3:0]=4'h0
+  R_DMDQMDBI_EYE_SHU_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[6:6]=1'h1 (Mirror: 1'h0)
+  R_DMDQMDBI_SHU_B0                            uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[7:7]=1'h1 (Mirror: 1'h0)
+  R_DMRXDVS_DQM_FLAGSEL_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[11:8]=4'h0
+  R_DMRXDVS_PBYTE_FLAG_OPT_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[12:12]=1'h0
+  R_DMRXDVS_PBYTE_DQM_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[13:13]=1'h0
+  R_DMRXTRACK_DQM_EN_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[14:14]=1'h0
+  R_DMRODTEN_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[15:15]=1'h1
+  R_DMARPI_CG_FB2DLL_DCM_EN_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[16:16]=1'h0
+  R_DMTX_ARPI_CG_DQ_NEW_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[17:17]=1'h0
+  R_DMTX_ARPI_CG_DQS_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[18:18]=1'h0
+  R_DMTX_ARPI_CG_DQM_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[19:19]=1'h0
+  R_LP4Y_SDN_MODE_DQS0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[20:20]=1'h0
+  R_DMRXRANK_DQ_EN_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[24:24]=1'h1
+  R_DMRXRANK_DQ_LAT_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[27:25]=3'h2
+  R_DMRXRANK_DQS_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[28:28]=1'h1
+  R_DMRXRANK_DQS_LAT_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[31:29]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ7_0                            -     @9211
+  R_DMRANKRXDVS_B1                             uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[3:0]=4'h0
+  R_DMDQMDBI_EYE_SHU_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[6:6]=1'h1 (Mirror: 1'h0)
+  R_DMDQMDBI_SHU_B1                            uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[7:7]=1'h1 (Mirror: 1'h0)
+  R_DMRXDVS_DQM_FLAGSEL_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[11:8]=4'h0
+  R_DMRXDVS_PBYTE_FLAG_OPT_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[12:12]=1'h0
+  R_DMRXDVS_PBYTE_DQM_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[13:13]=1'h0
+  R_DMRXTRACK_DQM_EN_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[14:14]=1'h0
+  R_DMRODTEN_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[15:15]=1'h1
+  R_DMARPI_CG_FB2DLL_DCM_EN_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[16:16]=1'h0
+  R_DMTX_ARPI_CG_DQ_NEW_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[17:17]=1'h0
+  R_DMTX_ARPI_CG_DQS_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[18:18]=1'h0
+  R_DMTX_ARPI_CG_DQM_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[19:19]=1'h0
+  R_LP4Y_SDN_MODE_DQS1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[20:20]=1'h0
+  R_DMRXRANK_DQ_EN_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[24:24]=1'h1
+  R_DMRXRANK_DQ_LAT_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[27:25]=3'h2
+  R_DMRXRANK_DQS_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[28:28]=1'h1
+  R_DMRXRANK_DQS_LAT_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[31:29]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_TX_SET0_0                                  ral_reg_DRAMC_blk_SHU_TX_SET0_0                            -     @5306
+  DQOE_CNT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[3:0]=4'h0
+  DQOE_OPT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[4:4]=1'h0
+  TXUPD_SEL                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[7:6]=2'h0
+  TXUPD_W2R_SEL                                uvm_reg_field                                              ...    RW SHU_TX_SET0_0[10:8]=3'h2
+  WECC_EN                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[11:11]=1'h0
+  DBIWR                                        uvm_reg_field                                              ...    RW SHU_TX_SET0_0[12:12]=1'h1 (Mirror: 1'h0)
+  WDATRGO                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[13:13]=1'h0
+  TWPSTEXT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[14:14]=1'h0
+  WPST1P5T                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[15:15]=1'h1
+  TXOEN_AUTOSET_OFFSET                         uvm_reg_field                                              ...    RW SHU_TX_SET0_0[19:16]=4'h3
+  TWCKPST                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[21:20]=2'h1
+  OE_EXT2UI                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[24:22]=3'h1
+  DQS2DQ_FILT_PITHRD                           uvm_reg_field                                              ...    RW SHU_TX_SET0_0[30:25]=6'h0e
+  TXOEN_AUTOSET_EN                             uvm_reg_field                                              ...    RW SHU_TX_SET0_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+#if (fcFOR_CHIP_ID == fcA60868)
+vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+        P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+        P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+        P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+        P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
+        P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+        P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+        P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+#elif (fcFOR_CHIP_ID == fcPetrus)
+vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+        P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+        P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+        P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+        P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
+        P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+        P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+        P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+#endif
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Exit
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Enter
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_HWSET_MR2_0                                ral_reg_DRAMC_blk_SHU_HWSET_MR2_0                          -     @5122
+  HWSET_MR2_MRSMA                              uvm_reg_field                                              ...    RW SHU_HWSET_MR2_0[12:0]=13'h0002
+  HWSET_MR2_OP                                 uvm_reg_field                                              ...    RW SHU_HWSET_MR2_0[23:16]=8'h3f (Mirror: 8'h12)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR2, P_Fld(0x0002, SHU_HWSET_MR2_HWSET_MR2_MRSMA) |
+        P_Fld(0x3f, SHU_HWSET_MR2_HWSET_MR2_OP));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Exit
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Enter
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_FREQ_RATIO_SET0_0                          ral_reg_DRAMC_blk_SHU_FREQ_RATIO_SET0_0                    -     @5384
+  tDQSCK_JUMP_RATIO3                           uvm_reg_field                                              ...    RW SHU_FREQ_RATIO_SET0_0[7:0]=8'h20 (Mirror: 8'h00)
+  tDQSCK_JUMP_RATIO2                           uvm_reg_field                                              ...    RW SHU_FREQ_RATIO_SET0_0[15:8]=8'h72 (Mirror: 8'h00)
+  tDQSCK_JUMP_RATIO1                           uvm_reg_field                                              ...    RW SHU_FREQ_RATIO_SET0_0[23:16]=8'h09 (Mirror: 8'h00)
+  tDQSCK_JUMP_RATIO0                           uvm_reg_field                                              ...    RW SHU_FREQ_RATIO_SET0_0[31:24]=8'h20 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) |
+        P_Fld(0x72, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x09, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) |
+        P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Exit
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Enter
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_DVFSDLL_0                             ral_reg_DDRPHY_blk_MISC_SHU_DVFSDLL_0                      -     @12523
+  r_bypass_1st_dll                             uvm_reg_field                                              ...    RW MISC_SHU_DVFSDLL_0[0:0]=1'h0
+  r_bypass_2nd_dll                             uvm_reg_field                                              ...    RW MISC_SHU_DVFSDLL_0[1:1]=1'h0
+  r_dll_idle                                   uvm_reg_field                                              ...    RW MISC_SHU_DVFSDLL_0[10:4]=7'h5a (Mirror: 7'h46)
+  r_2nd_dll_idle                               uvm_reg_field                                              ...    RW MISC_SHU_DVFSDLL_0[22:16]=7'h5a
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) |
+        P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) |
+        P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Exit
+    mcDELAY_US(1);
+
+    mcDELAY_US(1);
+
+/*TINFO=---===BROADCAST OFF!===---*/
+     DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Enter
+    mcDELAY_US(1);
+
+    mcDELAY_US(1);
+
+/*TINFO=---===BROADCAST ON!===---*/
+     DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Exit
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_DQSOSCR_0                                  ral_reg_DRAMC_blk_SHU_DQSOSCR_0                            -     @5338
+  DQSOSCRCNT                                   uvm_reg_field                                              ...    RW SHU_DQSOSCR_0[7:0]=8'h15 (Mirror: 8'h00)
+  DQSOSC_ADV_SEL                               uvm_reg_field                                              ...    RW SHU_DQSOSCR_0[9:8]=2'h0
+  DQSOSC_DRS_ADV_SEL                           uvm_reg_field                                              ...    RW SHU_DQSOSCR_0[11:10]=2'h0
+  DQSOSC_DELTA                                 uvm_reg_field                                              ...    RW SHU_DQSOSCR_0[31:16]=16'hffff
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR, P_Fld(0x15, SHU_DQSOSCR_DQSOSCRCNT) |
+        P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) |
+        P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_DQSOSC_SET0_0                              ral_reg_DRAMC_blk_SHU_DQSOSC_SET0_0                        -     @5332
+  DQSOSCENDIS                                  uvm_reg_field                                              ...    RW SHU_DQSOSC_SET0_0[0:0]=1'h1
+  DQSOSC_PRDCNT                                uvm_reg_field                                              ...    RW SHU_DQSOSC_SET0_0[13:4]=10'h012 (Mirror: 10'h00f)
+  DQSOSCENCNT                                  uvm_reg_field                                              ...    RW SHU_DQSOSC_SET0_0[31:16]=16'h0002
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0, P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) |
+        P_Fld(0x012, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQSOSC_0_0                               ral_reg_DRAMC_blk_SHURK_DQSOSC_0_0                         -     @4906
+  DQSOSC_BASE_RK0                              uvm_reg_field                                              ...    RW SHURK_DQSOSC_0_0[15:0]=16'h0326 (Mirror: 16'h0000)
+  DQSOSC_BASE_RK0_B1                           uvm_reg_field                                              ...    RW SHURK_DQSOSC_0_0[31:16]=16'h0326 (Mirror: 16'h0000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC, P_Fld(0x0326, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
+        P_Fld(0x0326, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQSOSC_0_1                               ral_reg_DRAMC_blk_SHURK_DQSOSC_0_1                         -     @4911
+  DQSOSC_BASE_RK0                              uvm_reg_field                                              ...    RW SHURK_DQSOSC_0_1[15:0]=16'h0159 (Mirror: 16'h0000)
+  DQSOSC_BASE_RK0_B1                           uvm_reg_field                                              ...    RW SHURK_DQSOSC_0_1[31:16]=16'h0159 (Mirror: 16'h0000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0159, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
+        P_Fld(0x0159, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQSOSC_THRD_0_0                          ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_0                    -     @4916
+  DQSOSCTHRD_INC                               uvm_reg_field                                              ...    RW SHURK_DQSOSC_THRD_0_0[11:0]=12'h018 (Mirror: 12'h001)
+  DQSOSCTHRD_DEC                               uvm_reg_field                                              ...    RW SHURK_DQSOSC_THRD_0_0[27:16]=12'h010 (Mirror: 12'h001)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD, P_Fld(0x018, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
+        P_Fld(0x010, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQSOSC_THRD_0_1                          ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_1                    -     @4921
+  DQSOSCTHRD_INC                               uvm_reg_field                                              ...    RW SHURK_DQSOSC_THRD_0_1[11:0]=12'h004 (Mirror: 12'h001)
+  DQSOSCTHRD_DEC                               uvm_reg_field                                              ...    RW SHURK_DQSOSC_THRD_0_1[27:16]=12'h002 (Mirror: 12'h001)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x004, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
+        P_Fld(0x002, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_TX_SET0_0                                  ral_reg_DRAMC_blk_SHU_TX_SET0_0                            -     @5306
+  DQOE_CNT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[3:0]=4'h0
+  DQOE_OPT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[4:4]=1'h0
+  TXUPD_SEL                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[7:6]=2'h0
+  TXUPD_W2R_SEL                                uvm_reg_field                                              ...    RW SHU_TX_SET0_0[10:8]=3'h2
+  WECC_EN                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[11:11]=1'h0
+  DBIWR                                        uvm_reg_field                                              ...    RW SHU_TX_SET0_0[12:12]=1'h1
+  WDATRGO                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[13:13]=1'h0
+  TWPSTEXT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[14:14]=1'h0
+  WPST1P5T                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[15:15]=1'h1
+  TXOEN_AUTOSET_OFFSET                         uvm_reg_field                                              ...    RW SHU_TX_SET0_0[19:16]=4'h3
+  TWCKPST                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[21:20]=2'h1
+  OE_EXT2UI                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[24:22]=3'h1
+  DQS2DQ_FILT_PITHRD                           uvm_reg_field                                              ...    RW SHU_TX_SET0_0[30:25]=6'h17 (Mirror: 6'h0e)
+  TXOEN_AUTOSET_EN                             uvm_reg_field                                              ...    RW SHU_TX_SET0_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+#if (fcFOR_CHIP_ID == fcA60868)
+vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+        P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+        P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+        P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+        P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
+        P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+        P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x17, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+        P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+#elif (fcFOR_CHIP_ID == fcPetrus)
+vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+        P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+        P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+        P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+        P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
+        P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+        P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x17, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+        P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ZQ_SET0_0                                  ral_reg_DRAMC_blk_SHU_ZQ_SET0_0                            -     @5351
+  ZQCSCNT                                      uvm_reg_field                                              ...    RW SHU_ZQ_SET0_0[15:0]=16'h0000
+  TZQLAT                                       uvm_reg_field                                              ...    RW SHU_ZQ_SET0_0[31:27]=5'h1d (Mirror: 5'h1b)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0000, SHU_ZQ_SET0_ZQCSCNT) |
+        P_Fld(0x1d, SHU_ZQ_SET0_TZQLAT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ZQ_SET0_0                                  ral_reg_DRAMC_blk_SHU_ZQ_SET0_0                            -     @5351
+  ZQCSCNT                                      uvm_reg_field                                              ...    RW SHU_ZQ_SET0_0[15:0]=16'h0005 (Mirror: 16'h0000)
+  TZQLAT                                       uvm_reg_field                                              ...    RW SHU_ZQ_SET0_0[31:27]=5'h1d
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) |
+        P_Fld(0x1d, SHU_ZQ_SET0_TZQLAT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_HMR4_DVFS_CTRL0_0                          ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0                    -     @5036
+  FSPCHG_PRDCNT                                uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h86
+  REFRCNT                                      uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h005 (Mirror: 12'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x86, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+        P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ8_0                            -     @7828
+  R_DMRXDVS_UPD_FORCE_CYC_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[14:0]=15'h0100
+  R_DMRXDVS_UPD_FORCE_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[15:15]=1'h1 (Mirror: 1'h0)
+  R_DMRANK_RXDLY_PIPE_CG_IG_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[19:19]=1'h0
+  R_RMRODTEN_CG_IG_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[20:20]=1'h0
+  R_RMRX_TOPHY_CG_IG_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[21:21]=1'h1
+  R_DMRXDVS_RDSEL_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[22:22]=1'h0
+  R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0            uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[23:23]=1'h0
+  R_DMRXDLY_CG_IG_B0                           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[24:24]=1'h1
+  R_DMDQSIEN_FLAG_SYNC_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[26:26]=1'h0
+  R_DMDQSIEN_FLAG_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[27:27]=1'h0
+  R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0               uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[28:28]=1'h0
+  R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[29:29]=1'h0
+  R_DMRANK_PIPE_CG_IG_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[30:30]=1'h0
+  R_DMRANK_CHG_PIPE_CG_IG_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+        P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+        P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ8_0                            -     @9231
+  R_DMRXDVS_UPD_FORCE_CYC_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[14:0]=15'h0100
+  R_DMRXDVS_UPD_FORCE_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[15:15]=1'h1 (Mirror: 1'h0)
+  R_DMRANK_RXDLY_PIPE_CG_IG_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[19:19]=1'h0
+  R_RMRODTEN_CG_IG_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[20:20]=1'h0
+  R_RMRX_TOPHY_CG_IG_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[21:21]=1'h1
+  R_DMRXDVS_RDSEL_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[22:22]=1'h0
+  R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1            uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[23:23]=1'h0
+  R_DMRXDLY_CG_IG_B1                           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[24:24]=1'h1
+  R_DMDQSIEN_FLAG_SYNC_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[26:26]=1'h0
+  R_DMDQSIEN_FLAG_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[27:27]=1'h0
+  R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1               uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[28:28]=1'h0
+  R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[29:29]=1'h0
+  R_DMRANK_PIPE_CG_IG_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[30:30]=1'h0
+  R_DMRANK_CHG_PIPE_CG_IG_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+        P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+        P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ7_0                            -     @7808
+  R_DMRANKRXDVS_B0                             uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[3:0]=4'h0
+  R_DMDQMDBI_EYE_SHU_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[6:6]=1'h1
+  R_DMDQMDBI_SHU_B0                            uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[7:7]=1'h1
+  R_DMRXDVS_DQM_FLAGSEL_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[11:8]=4'hb (Mirror: 4'h0)
+  R_DMRXDVS_PBYTE_FLAG_OPT_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[12:12]=1'h0
+  R_DMRXDVS_PBYTE_DQM_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[13:13]=1'h1 (Mirror: 1'h0)
+  R_DMRXTRACK_DQM_EN_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[14:14]=1'h1 (Mirror: 1'h0)
+  R_DMRODTEN_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[15:15]=1'h1
+  R_DMARPI_CG_FB2DLL_DCM_EN_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[16:16]=1'h0
+  R_DMTX_ARPI_CG_DQ_NEW_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[17:17]=1'h0
+  R_DMTX_ARPI_CG_DQS_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[18:18]=1'h0
+  R_DMTX_ARPI_CG_DQM_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[19:19]=1'h0
+  R_LP4Y_SDN_MODE_DQS0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[20:20]=1'h0
+  R_DMRXRANK_DQ_EN_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[24:24]=1'h1
+  R_DMRXRANK_DQ_LAT_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[27:25]=3'h2
+  R_DMRXRANK_DQS_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[28:28]=1'h1
+  R_DMRXRANK_DQS_LAT_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[31:29]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+        P_Fld(0xb, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ7_0                            -     @9211
+  R_DMRANKRXDVS_B1                             uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[3:0]=4'h0
+  R_DMDQMDBI_EYE_SHU_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[6:6]=1'h1
+  R_DMDQMDBI_SHU_B1                            uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[7:7]=1'h1
+  R_DMRXDVS_DQM_FLAGSEL_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[11:8]=4'hb (Mirror: 4'h0)
+  R_DMRXDVS_PBYTE_FLAG_OPT_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[12:12]=1'h0
+  R_DMRXDVS_PBYTE_DQM_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[13:13]=1'h1 (Mirror: 1'h0)
+  R_DMRXTRACK_DQM_EN_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[14:14]=1'h1 (Mirror: 1'h0)
+  R_DMRODTEN_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[15:15]=1'h1
+  R_DMARPI_CG_FB2DLL_DCM_EN_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[16:16]=1'h0
+  R_DMTX_ARPI_CG_DQ_NEW_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[17:17]=1'h0
+  R_DMTX_ARPI_CG_DQS_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[18:18]=1'h0
+  R_DMTX_ARPI_CG_DQM_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[19:19]=1'h0
+  R_LP4Y_SDN_MODE_DQS1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[20:20]=1'h0
+  R_DMRXRANK_DQ_EN_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[24:24]=1'h1
+  R_DMRXRANK_DQ_LAT_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[27:25]=3'h2
+  R_DMRXRANK_DQS_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[28:28]=1'h1
+  R_DMRXRANK_DQS_LAT_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[31:29]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+        P_Fld(0xb, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ11_0                                  ral_reg_DDRPHY_blk_SHU_B0_DQ11_0                           -     @7794
+  RG_RX_ARDQ_RANK_SEL_SER_EN_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[0:0]=1'h0
+  RG_RX_ARDQ_RANK_SEL_LAT_EN_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[1:1]=1'h0
+  RG_RX_ARDQ_OFFSETC_LAT_EN_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[2:2]=1'h0
+  RG_RX_ARDQ_OFFSETC_EN_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[3:3]=1'h0
+  RG_RX_ARDQ_OFFSETC_BIAS_EN_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[4:4]=1'h0
+  RG_RX_ARDQ_FRATE_EN_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[5:5]=1'h0
+  RG_RX_ARDQ_CDR_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[6:6]=1'h0
+  RG_RX_ARDQ_DVS_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[7:7]=1'h1 (Mirror: 1'h0)
+  RG_RX_ARDQ_DVS_DLY_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[11:8]=4'h0
+  RG_RX_ARDQ_DES_MODE_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[17:16]=2'h2
+  RG_RX_ARDQ_BW_SEL_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[19:18]=2'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11, P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) |
+        P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ11_0                                  ral_reg_DDRPHY_blk_SHU_B1_DQ11_0                           -     @9197
+  RG_RX_ARDQ_RANK_SEL_SER_EN_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[0:0]=1'h0
+  RG_RX_ARDQ_RANK_SEL_LAT_EN_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[1:1]=1'h0
+  RG_RX_ARDQ_OFFSETC_LAT_EN_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[2:2]=1'h0
+  RG_RX_ARDQ_OFFSETC_EN_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[3:3]=1'h0
+  RG_RX_ARDQ_OFFSETC_BIAS_EN_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[4:4]=1'h0
+  RG_RX_ARDQ_FRATE_EN_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[5:5]=1'h0
+  RG_RX_ARDQ_CDR_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[6:6]=1'h0
+  RG_RX_ARDQ_DVS_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[7:7]=1'h1 (Mirror: 1'h0)
+  RG_RX_ARDQ_DVS_DLY_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[11:8]=4'h0
+  RG_RX_ARDQ_DES_MODE_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[17:16]=2'h2
+  RG_RX_ARDQ_BW_SEL_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[19:18]=2'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11, P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) |
+        P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1));
+//    Exit body
+}
+
+
+#if __LP5_COMBO__
+void CInit_golden_mini_freq_related_vseq_LP5_3200(DRAMC_CTX_T *p)
+{
+    //    Enter body
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Enter:
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_DRVING1_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING1_0                      -     @12634
+      DQDRVN2                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[4:0]=5'h08 (Mirror: 5'h00)
+      DQDRVP2                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[9:5]=5'h06 (Mirror: 5'h00)
+      DQSDRVN1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[14:10]=5'h08 (Mirror: 5'h00)
+      DQSDRVP1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[19:15]=5'h06 (Mirror: 5'h00)
+      DQSDRVN2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[24:20]=5'h08 (Mirror: 5'h00)
+      DQSDRVP2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[29:25]=5'h06 (Mirror: 5'h00)
+      DIS_IMP_ODTN_track                           uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[30:30]=1'h0
+      DIS_IMPCAL_HW                                uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[31:31]=1'h0
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(0x08, SHU_MISC_DRVING1_DQDRVN2) |
+            P_Fld(0x06, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN1) |
+            P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN2) |
+            P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) |
+            P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMPCAL_HW));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_DRVING2_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING2_0                      -     @12645
+      CMDDRVN1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[4:0]=5'h08 (Mirror: 5'h00)
+      CMDDRVP1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[9:5]=5'h06 (Mirror: 5'h00)
+      CMDDRVN2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[14:10]=5'h08 (Mirror: 5'h00)
+      CMDDRVP2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[19:15]=5'h06 (Mirror: 5'h00)
+      DQDRVN1                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[24:20]=5'h08 (Mirror: 5'h00)
+      DQDRVP1                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[29:25]=5'h06 (Mirror: 5'h00)
+      DIS_IMPCAL_ODT_EN                            uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[31:31]=1'h0
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2, P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN1) |
+            P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN2) |
+            P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x08, SHU_MISC_DRVING2_DQDRVN1) |
+            P_Fld(0x06, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_DRVING3_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING3_0                      -     @12655
+      DQODTN2                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[4:0]=5'h0a (Mirror: 5'h00)
+      DQODTP2                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[9:5]=5'h0a (Mirror: 5'h00)
+      DQSODTN                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[14:10]=5'h0a (Mirror: 5'h00)
+      DQSODTP                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[19:15]=5'h0a (Mirror: 5'h00)
+      DQSODTN2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[24:20]=5'h0a (Mirror: 5'h00)
+      DQSODTP2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[29:25]=5'h0a (Mirror: 5'h00)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3, P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) |
+            P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) |
+            P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) |
+            P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_DRVING4_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING4_0                      -     @12664
+      CMDODTN1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[4:0]=5'h0a (Mirror: 5'h00)
+      CMDODTP1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[9:5]=5'h0a (Mirror: 5'h00)
+      CMDODTN2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[14:10]=5'h0a (Mirror: 5'h00)
+      CMDODTP2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[19:15]=5'h0a (Mirror: 5'h00)
+      DQODTN1                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[24:20]=5'h0a (Mirror: 5'h00)
+      DQODTP1                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[29:25]=5'h0a (Mirror: 5'h00)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4, P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) |
+            P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) |
+            P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) |
+            P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_DRVING6_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING6_0                      -     @12682
+      IMP_TXDLY_CMD                                uvm_reg_field                                              ...    RW SHU_MISC_DRVING6_0[5:0]=6'h09 (Mirror: 6'h01)
+      DQCODTN1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING6_0[24:20]=5'h00
+      DQCODTP1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING6_0[29:25]=5'h00
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6, P_Fld(0x09, SHU_MISC_DRVING6_IMP_TXDLY_CMD) |
+            P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_IMPCAL1_0                             ral_reg_DDRPHY_blk_SHU_MISC_IMPCAL1_0                      -     @12625
+      IMPCAL_CHKCYCLE                              uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[2:0]=3'h5 (Mirror: 3'h4)
+      IMPDRVP                                      uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[8:4]=5'h00
+      IMPDRVN                                      uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[16:12]=5'h00
+      IMPCAL_CALEN_CYCLE                           uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[19:17]=3'h4
+      IMPCALCNT                                    uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[27:20]=8'h03 (Mirror: 8'h00)
+      IMPCAL_CALICNT                               uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[31:28]=4'h8
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1, P_Fld(0x5, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) |
+            P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) |
+            P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) |
+            P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Exit:
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter:
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_RDSEL_TRACK_0                         ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0                  -     @12734
+      DMDATLAT_i                                   uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h0e (Mirror: 5'h00)
+      RDSEL_HWSAVE_MSK                             uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0)
+      RDSEL_TRACK_EN                               uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0
+      SHU_GW_THRD_NEG                              uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfd7 (Mirror: 12'h000)
+      SHU_GW_THRD_POS                              uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h029 (Mirror: 12'h000)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x0e, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) |
+            P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) |
+            P_Fld(0xfd7, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x029, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RDAT_0                                ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0                         -     @12604
+      DATLAT                                       uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[4:0]=5'h0e (Mirror: 5'h00)
+      DATLAT_DSEL                                  uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[12:8]=5'h0e (Mirror: 5'h00)
+      DATLAT_DSEL_PHY                              uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[20:16]=5'h0e (Mirror: 5'h00)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x0e, MISC_SHU_RDAT_DATLAT) |
+            P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_PHY_RX_CTRL_0                         ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0                  -     @12540
+      RANK_RXDLY_UPDLAT_EN                         uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0)
+      RANK_RXDLY_UPD_OFFSET                        uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0)
+      RX_IN_GATE_EN_PRE_OFFSET                     uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0)
+      RX_IN_GATE_EN_HEAD                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h1 (Mirror: 3'h0)
+      RX_IN_GATE_EN_TAIL                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0)
+      RX_IN_BUFF_EN_HEAD                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h2 (Mirror: 3'h0)
+      RX_IN_BUFF_EN_TAIL                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) |
+            P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) |
+            P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) |
+            P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RANKCTL_0                             ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0                      -     @12530
+      RANKINCTL_RXDLY                              uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[3:0]=4'h4 (Mirror: 4'h0)
+      RANK_RXDLY_OPT                               uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[4:4]=1'h1
+      RANKSEL_SELPH_FRUN                           uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[15:15]=1'h0
+      RANKINCTL_STB                                uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[19:16]=4'h7 (Mirror: 4'h0)
+      RANKINCTL                                    uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[23:20]=4'h5 (Mirror: 4'h0)
+      RANKINCTL_ROOT1                              uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[27:24]=4'h5 (Mirror: 4'h0)
+      RANKINCTL_PHY                                uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[31:28]=4'h8 (Mirror: 4'h0)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) |
+            P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) |
+            P_Fld(0x7, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL) |
+            P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x8, MISC_SHU_RANKCTL_RANKINCTL_PHY));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RANK_SEL_LAT_0                        ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0                 -     @12757
+      RANK_SEL_LAT_B0                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0)
+      RANK_SEL_LAT_B1                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0)
+      RANK_SEL_LAT_CA                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
+            P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCTL_0_0                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0                  -     @12352
+      DQSINCTL                                     uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h7 (Mirror: 4'h0)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL);
+    /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCTL_0_1                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1                  -     @12356
+      DQSINCTL                                     uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h7 (Mirror: 4'h0)
+    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL);
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0         -     @7624
+      DQSIEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'ha (Mirror: 4'h0)
+      DQSIEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'he (Mirror: 4'h0)
+      DQSIEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0
+      DQSIEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0xa, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+            P_Fld(0xe, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+    /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_PI_DLY_0_0                    ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0             -     @7638
+      DQSIEN_PI_B0                                 uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0f (Mirror: 7'h00)
+    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0f, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1         -     @7631
+      DQSIEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0)
+      DQSIEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0
+      DQSIEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0
+      DQSIEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+            P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_DQSIEN_PI_DLY_0_1                    ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1             -     @7642
+      DQSIEN_PI_B0                                 uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x11, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0         -     @9027
+      DQSIEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'ha (Mirror: 4'h0)
+      DQSIEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'he (Mirror: 4'h0)
+      DQSIEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0
+      DQSIEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0xa, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+            P_Fld(0xe, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_PI_DLY_0_0                    ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0             -     @9041
+      DQSIEN_PI_B1                                 uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0f (Mirror: 7'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0f, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1         -     @9034
+      DQSIEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0)
+      DQSIEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0
+      DQSIEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0
+      DQSIEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+            P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_DQSIEN_PI_DLY_0_1                    ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1             -     @9045
+      DQSIEN_PI_B1                                 uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x11, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_ODTCTRL_0                             ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0                      -     @12550
+      RODTEN                                       uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0)
+      RODTENSTB_SELPH_CG_IG                        uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[1:1]=1'h0
+      RODT_LAT                                     uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[7:4]=4'h6 (Mirror: 4'h0)
+      RODTEN_SELPH_FRUN                            uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[15:15]=1'h0
+      RODTDLY_LAT_OPT                              uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[25:24]=2'h0
+      FIXRODT                                      uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[27:27]=1'h0
+      RODTEN_OPT                                   uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[29:29]=1'h1
+      RODTE2                                       uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0)
+      RODTE                                        uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x6, MISC_SHU_ODTCTRL_RODT_LAT) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) |
+            P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ7_0                            -     @7808
+      R_DMRANKRXDVS_B0                             uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[3:0]=4'h0
+      R_DMDQMDBI_EYE_SHU_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[6:6]=1'h0
+      R_DMDQMDBI_SHU_B0                            uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[7:7]=1'h0
+      R_DMRXDVS_DQM_FLAGSEL_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[11:8]=4'h0
+      R_DMRXDVS_PBYTE_FLAG_OPT_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[12:12]=1'h0
+      R_DMRXDVS_PBYTE_DQM_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[13:13]=1'h0
+      R_DMRXTRACK_DQM_EN_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[14:14]=1'h0
+      R_DMRODTEN_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)
+      R_DMARPI_CG_FB2DLL_DCM_EN_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[16:16]=1'h0
+      R_DMTX_ARPI_CG_DQ_NEW_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[17:17]=1'h0
+      R_DMTX_ARPI_CG_DQS_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[18:18]=1'h0
+      R_DMTX_ARPI_CG_DQM_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[19:19]=1'h0
+      R_LP4Y_SDN_MODE_DQS0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[20:20]=1'h0
+      R_DMRXRANK_DQ_EN_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)
+      R_DMRXRANK_DQ_LAT_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0)
+      R_DMRXRANK_DQS_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)
+      R_DMRXRANK_DQS_LAT_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[31:29]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ7_0                            -     @9211
+      R_DMRANKRXDVS_B1                             uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[3:0]=4'h0
+      R_DMDQMDBI_EYE_SHU_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[6:6]=1'h0
+      R_DMDQMDBI_SHU_B1                            uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[7:7]=1'h0
+      R_DMRXDVS_DQM_FLAGSEL_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[11:8]=4'h0
+      R_DMRXDVS_PBYTE_FLAG_OPT_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[12:12]=1'h0
+      R_DMRXDVS_PBYTE_DQM_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[13:13]=1'h0
+      R_DMRXTRACK_DQM_EN_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[14:14]=1'h0
+      R_DMRODTEN_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)
+      R_DMARPI_CG_FB2DLL_DCM_EN_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[16:16]=1'h0
+      R_DMTX_ARPI_CG_DQ_NEW_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[17:17]=1'h0
+      R_DMTX_ARPI_CG_DQS_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[18:18]=1'h0
+      R_DMTX_ARPI_CG_DQM_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[19:19]=1'h0
+      R_LP4Y_SDN_MODE_DQS1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[20:20]=1'h0
+      R_DMRXRANK_DQ_EN_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)
+      R_DMRXRANK_DQ_LAT_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0)
+      R_DMRXRANK_DQS_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)
+      R_DMRXRANK_DQS_LAT_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[31:29]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_RX_PIPE_CTRL_0                        ral_reg_DDRPHY_blk_SHU_MISC_RX_PIPE_CTRL_0                 -     @12704
+      RX_PIPE_BYPASS_EN                            uvm_reg_field                                              ...    RW SHU_MISC_RX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x1, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0         -     @7646
+      RODTEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h5 (Mirror: 3'h0)
+      RODTEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h5 (Mirror: 3'h0)
+      RODTEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0
+      RODTEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x5, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+            P_Fld(0x5, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1         -     @7653
+      RODTEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0)
+      RODTEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0)
+      RODTEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0
+      RODTEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+            P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0         -     @9049
+      RODTEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h5 (Mirror: 3'h0)
+      RODTEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h5 (Mirror: 3'h0)
+      RODTEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0
+      RODTEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x5, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+            P_Fld(0x5, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1         -     @9056
+      RODTEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0)
+      RODTEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0)
+      RODTEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0
+      RODTEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+            P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_RX_CG_SET0_0                               ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0                         -     @5323
+      DLE_LAST_EXTEND3                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[0:0]=1'h0
+      READ_START_EXTEND3                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[1:1]=1'h0
+      DLE_LAST_EXTEND2                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0)
+      READ_START_EXTEND2                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0)
+      DLE_LAST_EXTEND1                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0)
+      READ_START_EXTEND1                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) |
+            P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) |
+            P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
+            P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_RANK_SEL_STB_0                        ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0                 -     @12720
+      RANK_SEL_STB_EN                              uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0)
+      RANK_SEL_STB_EN_B23                          uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0
+      RANK_SEL_STB_SERMODE                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0
+      RANK_SEL_STB_TRACK                           uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0)
+      RANK_SEL_RXDLY_TRACK                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0
+      RANK_SEL_STB_PHASE_EN                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h1 (Mirror: 1'h0)
+      RANK_SEL_PHSINCTL                            uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h8 (Mirror: 4'h0)
+      RANK_SEL_STB_UI_PLUS                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0
+      RANK_SEL_STB_MCK_PLUS                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0
+      RANK_SEL_STB_UI_MINUS                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h1 (Mirror: 4'h0)
+      RANK_SEL_STB_MCK_MINUS                       uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) |
+            P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) |
+            P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) |
+            P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x8, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) |
+            P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) |
+            P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCAL_0_0                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0                  -     @12370
+      DQSIENLLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00)
+      DQSIENLLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0)
+      DQSIENHLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00)
+      DQSIENHLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RK_DQSCAL_0_1                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1                  -     @12377
+      DQSIENLLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00)
+      DQSIENLLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0)
+      DQSIENHLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00)
+      DQSIENHLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_INI_UIPI_0_0                         ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0                  -     @7602
+      CURR_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00)
+      CURR_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h0a (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0f, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+            P_Fld(0x0a, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_INI_UIPI_0_0                         ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0                  -     @9005
+      CURR_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00)
+      CURR_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h0a (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0f, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+            P_Fld(0x0a, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_INI_UIPI_0_1                         ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1                  -     @7607
+      CURR_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00)
+      CURR_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+            P_Fld(0x0c, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_INI_UIPI_0_1                         ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1                  -     @9010
+      CURR_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00)
+      CURR_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+            P_Fld(0x0c, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_NEXT_INI_UIPI_0_0                    ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0             -     @7612
+      NEXT_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00)
+      NEXT_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h0a (Mirror: 8'h00)
+      NEXT_INI_UI_P1_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h0e (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+            P_Fld(0x0a, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0e, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_NEXT_INI_UIPI_0_0                    ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0             -     @9015
+      NEXT_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00)
+      NEXT_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h0a (Mirror: 8'h00)
+      NEXT_INI_UI_P1_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h0e (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+            P_Fld(0x0a, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0e, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_NEXT_INI_UIPI_0_1                    ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1             -     @7618
+      NEXT_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00)
+      NEXT_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00)
+      NEXT_INI_UI_P1_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+            P_Fld(0x0c, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x10, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_NEXT_INI_UIPI_0_1                    ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1             -     @9021
+      NEXT_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00)
+      NEXT_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00)
+      NEXT_INI_UI_P1_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+            P_Fld(0x0c, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x10, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit:
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter:
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_CA_CMD0_0_0                             ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_0                      -     @10426
+      RG_RX_ARCLK_R_DLY_DUTY                       uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[2:0]=3'h0
+      RG_RX_ARCLK_F_DLY_DUTY                       uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[6:4]=3'h0
+      RG_ARPI_CS                                   uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[13:8]=6'h00
+      RG_ARPI_CMD                                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[21:16]=6'h10 (Mirror: 6'h00)
+      RG_ARPI_CLK                                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[29:24]=6'h00
+      DA_ARPI_DDR400_0D5UI_RK0_CA                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[30:30]=1'h0
+      DA_RX_ARDQSIEN_0D5UI_RK0_CA                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
+            P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
+            P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_DQ0_0_0                              ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0                       -     @7582
+      RG_RX_ARDQS0_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0
+      RG_RX_ARDQS0_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0
+      SW_ARPI_DQ_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[13:8]=6'h0f (Mirror: 6'h00)
+      SW_ARPI_DQM_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[21:16]=6'h0f (Mirror: 6'h00)
+      ARPI_PBYTE_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00
+      DA_ARPI_DDR400_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0
+      DA_RX_ARDQSIEN_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0f, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+            P_Fld(0x0f, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_DQ0_0_0                              ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0                       -     @8985
+      RG_RX_ARDQS1_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0
+      RG_RX_ARDQS1_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0
+      SW_ARPI_DQ_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[13:8]=6'h18 (Mirror: 6'h00)
+      SW_ARPI_DQM_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[21:16]=6'h18 (Mirror: 6'h00)
+      ARPI_PBYTE_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00
+      DA_ARPI_DDR400_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0
+      DA_RX_ARDQSIEN_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+            P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_CA_CMD0_0_1                             ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_1                      -     @10436
+      RG_RX_ARCLK_R_DLY_DUTY                       uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[2:0]=3'h0
+      RG_RX_ARCLK_F_DLY_DUTY                       uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[6:4]=3'h0
+      RG_ARPI_CS                                   uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[13:8]=6'h00
+      RG_ARPI_CMD                                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[21:16]=6'h10 (Mirror: 6'h00)
+      RG_ARPI_CLK                                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[29:24]=6'h00
+      DA_ARPI_DDR400_0D5UI_RK0_CA                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[30:30]=1'h0
+      DA_RX_ARDQSIEN_0D5UI_RK0_CA                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
+            P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
+            P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_DQ0_0_1                              ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1                       -     @7592
+      RG_RX_ARDQS0_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0
+      RG_RX_ARDQS0_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0
+      SW_ARPI_DQ_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[13:8]=6'h0e (Mirror: 6'h00)
+      SW_ARPI_DQM_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[21:16]=6'h0e (Mirror: 6'h00)
+      ARPI_PBYTE_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00
+      DA_ARPI_DDR400_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0
+      DA_RX_ARDQSIEN_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0e, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+            P_Fld(0x0e, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_DQ0_0_1                              ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1                       -     @8995
+      RG_RX_ARDQS1_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0
+      RG_RX_ARDQS1_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0
+      SW_ARPI_DQ_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[13:8]=6'h15 (Mirror: 6'h00)
+      SW_ARPI_DQM_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[21:16]=6'h15 (Mirror: 6'h00)
+      ARPI_PBYTE_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00
+      DA_ARPI_DDR400_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0
+      DA_RX_ARDQSIEN_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x15, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+            P_Fld(0x15, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_DCM_CTRL0_0                                ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0                          -     @5027
+      DDRPHY_CLK_EN_OPT                            uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0)
+      DPHY_CMDDCM_EXTCNT                           uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[11:8]=4'h4
+      DDRPHY_CLK_DYN_GATING_SEL                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0)
+      CKE_EXTNONPD_CNT                             uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[19:16]=4'h0
+      FASTWAKE2                                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[29:29]=1'h0
+      FASTWAKE                                     uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[31:31]=1'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+            P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+            P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) |
+            P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_APHY_TX_PICG_CTRL_0                        ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0                  -     @5377
+      DDRPHY_CLK_EN_COMB_TX_PICG_CNT               uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h8 (Mirror: 4'h0)
+      DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1             uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h3 (Mirror: 3'h0)
+      DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0             uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h3 (Mirror: 3'h0)
+      DDRPHY_CLK_EN_COMB_TX_OPT                    uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x8, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) |
+            P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) |
+            P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_APHY_TX_PICG_CTRL_0_0                    ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0              -     @4926
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h3 (Mirror: 3'h0)
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h3 (Mirror: 3'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+            P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_APHY_TX_PICG_CTRL_0_1                    ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1              -     @4931
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h3 (Mirror: 3'h0)
+      DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h3 (Mirror: 3'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+            P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_NEW_XRW2W_CTRL_0                           ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0                     -     @5371
+      TX_PI_UPDCTL_B0                              uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h3 (Mirror: 3'h0)
+      TX_PI_UPDCTL_B1                              uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h3 (Mirror: 3'h0)
+      TXPI_UPD_MODE                                uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) |
+            P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_DQS0_0                               ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0                         -     @5271
+      TXDLY_DQS0                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[2:0]=3'h4 (Mirror: 3'h1)
+      TXDLY_DQS1                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[6:4]=3'h4 (Mirror: 3'h1)
+      TXDLY_DQS2                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[10:8]=3'h1
+      TXDLY_DQS3                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[14:12]=3'h1
+      TXDLY_OEN_DQS0                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[18:16]=3'h4 (Mirror: 3'h1)
+      TXDLY_OEN_DQS1                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[22:20]=3'h4 (Mirror: 3'h1)
+      TXDLY_OEN_DQS2                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[26:24]=3'h1
+      TXDLY_OEN_DQS3                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[30:28]=3'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) |
+            P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) |
+            P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_DQS1_0                               ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0                         -     @5282
+      dly_DQS0                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[3:0]=4'h6 (Mirror: 4'h1)
+      dly_DQS1                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[7:4]=4'h7 (Mirror: 4'h1)
+      dly_DQS2                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[11:8]=4'h1
+      dly_DQS3                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[15:12]=4'h1
+      dly_oen_DQS0                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[19:16]=4'h3 (Mirror: 4'h1)
+      dly_oen_DQS1                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[23:20]=4'h4 (Mirror: 4'h1)
+      dly_oen_DQS2                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[27:24]=4'h1
+      dly_oen_DQS3                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[31:28]=4'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x6, SHU_SELPH_DQS1_DLY_DQS0) |
+            P_Fld(0x7, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x3, SHU_SELPH_DQS1_DLY_OEN_DQS0) |
+            P_Fld(0x4, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ0_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0                      -     @4746
+      TXDLY_DQ0                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[2:0]=3'h4 (Mirror: 3'h1)
+      TXDLY_DQ1                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[6:4]=3'h4 (Mirror: 3'h1)
+      TXDLY_DQ2                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1
+      TXDLY_DQ3                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1
+      TXDLY_OEN_DQ0                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[18:16]=3'h4 (Mirror: 3'h1)
+      TXDLY_OEN_DQ1                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[22:20]=3'h4 (Mirror: 3'h1)
+      TXDLY_OEN_DQ2                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1
+      TXDLY_OEN_DQ3                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+            P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+            P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ1_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0                      -     @4768
+      TXDLY_DQM0                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[2:0]=3'h4 (Mirror: 3'h1)
+      TXDLY_DQM1                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[6:4]=3'h4 (Mirror: 3'h1)
+      TXDLY_DQM2                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1
+      TXDLY_DQM3                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1
+      TXDLY_OEN_DQM0                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[18:16]=3'h4 (Mirror: 3'h1)
+      TXDLY_OEN_DQM1                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[22:20]=3'h4 (Mirror: 3'h1)
+      TXDLY_OEN_DQM2                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1
+      TXDLY_OEN_DQM3                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+            P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+            P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ2_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0                      -     @4790
+      dly_DQ0                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[3:0]=4'h5 (Mirror: 4'h1)
+      dly_DQ1                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[7:4]=4'h5 (Mirror: 4'h1)
+      dly_DQ2                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1
+      dly_DQ3                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1
+      dly_oen_DQ0                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[19:16]=4'h1
+      dly_oen_DQ1                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[23:20]=4'h1
+      dly_oen_DQ2                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1
+      dly_oen_DQ3                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x5, SHURK_SELPH_DQ2_DLY_DQ0) |
+            P_Fld(0x5, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ3_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0                      -     @4812
+      dly_DQM0                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[3:0]=4'h5 (Mirror: 4'h1)
+      dly_DQM1                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[7:4]=4'h5 (Mirror: 4'h1)
+      dly_DQM2                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1
+      dly_DQM3                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1
+      dly_oen_DQM0                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[19:16]=4'h1
+      dly_oen_DQM1                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[23:20]=4'h1
+      dly_oen_DQM2                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1
+      dly_oen_DQM3                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x5, SHURK_SELPH_DQ3_DLY_DQM0) |
+            P_Fld(0x5, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ0_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1                      -     @4757
+      TXDLY_DQ0                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[2:0]=3'h4 (Mirror: 3'h1)
+      TXDLY_DQ1                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[6:4]=3'h4 (Mirror: 3'h1)
+      TXDLY_DQ2                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1
+      TXDLY_DQ3                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1
+      TXDLY_OEN_DQ0                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[18:16]=3'h4 (Mirror: 3'h1)
+      TXDLY_OEN_DQ1                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[22:20]=3'h4 (Mirror: 3'h1)
+      TXDLY_OEN_DQ2                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1
+      TXDLY_OEN_DQ3                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+            P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+            P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ1_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1                      -     @4779
+      TXDLY_DQM0                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[2:0]=3'h4 (Mirror: 3'h1)
+      TXDLY_DQM1                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[6:4]=3'h4 (Mirror: 3'h1)
+      TXDLY_DQM2                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1
+      TXDLY_DQM3                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1
+      TXDLY_OEN_DQM0                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[18:16]=3'h4 (Mirror: 3'h1)
+      TXDLY_OEN_DQM1                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[22:20]=3'h4 (Mirror: 3'h1)
+      TXDLY_OEN_DQM2                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1
+      TXDLY_OEN_DQM3                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+            P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+            P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ2_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1                      -     @4801
+      dly_DQ0                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[3:0]=4'h6 (Mirror: 4'h1)
+      dly_DQ1                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[7:4]=4'h6 (Mirror: 4'h1)
+      dly_DQ2                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1
+      dly_DQ3                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1
+      dly_oen_DQ0                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[19:16]=4'h2 (Mirror: 4'h1)
+      dly_oen_DQ1                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[23:20]=4'h2 (Mirror: 4'h1)
+      dly_oen_DQ2                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1
+      dly_oen_DQ3                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ0) |
+            P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+            P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_SELPH_DQ3_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1                      -     @4823
+      dly_DQM0                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[3:0]=4'h6 (Mirror: 4'h1)
+      dly_DQM1                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[7:4]=4'h6 (Mirror: 4'h1)
+      dly_DQM2                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1
+      dly_DQM3                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1
+      dly_oen_DQM0                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[19:16]=4'h2 (Mirror: 4'h1)
+      dly_oen_DQM1                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[23:20]=4'h2 (Mirror: 4'h1)
+      dly_oen_DQM2                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1
+      dly_oen_DQM3                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM0) |
+            P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+            P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL1_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0                    -     @4834
+      BOOT_ORIG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h00f (Mirror: 11'h000)
+      BOOT_ORIG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h018 (Mirror: 11'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x00f, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+            P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL2_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0                    -     @4844
+      BOOT_TARG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h00f (Mirror: 11'h000)
+      BOOT_TARG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h018 (Mirror: 11'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x00f, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+            P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL5_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0                    -     @4882
+      BOOT_TARG_UI_RK0_DQM0                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h00f (Mirror: 11'h000)
+      BOOT_TARG_UI_RK0_DQM1                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h018 (Mirror: 11'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x00f, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+            P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL1_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1                    -     @4839
+      BOOT_ORIG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h00e (Mirror: 11'h000)
+      BOOT_ORIG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h015 (Mirror: 11'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x00e, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+            P_Fld(0x015, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL2_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1                    -     @4849
+      BOOT_TARG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h00e (Mirror: 11'h000)
+      BOOT_TARG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h015 (Mirror: 11'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x00e, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+            P_Fld(0x015, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQS2DQ_CAL5_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1                    -     @4887
+      BOOT_TARG_UI_RK0_DQM0                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h00e (Mirror: 11'h000)
+      BOOT_TARG_UI_RK0_DQM1                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h015 (Mirror: 11'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x00e, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+            P_Fld(0x015, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_PI_0_0                                   ral_reg_DRAMC_blk_SHURK_PI_0_0                             -     @4892
+      RK0_ARPI_DQ_B1                               uvm_reg_field                                              ...    RW SHURK_PI_0_0[5:0]=6'h18 (Mirror: 6'h00)
+      RK0_ARPI_DQ_B0                               uvm_reg_field                                              ...    RW SHURK_PI_0_0[13:8]=6'h0f (Mirror: 6'h00)
+      RK0_ARPI_DQM_B1                              uvm_reg_field                                              ...    RW SHURK_PI_0_0[21:16]=6'h18 (Mirror: 6'h00)
+      RK0_ARPI_DQM_B0                              uvm_reg_field                                              ...    RW SHURK_PI_0_0[29:24]=6'h0f (Mirror: 6'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B1) |
+            P_Fld(0x0f, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B1) |
+            P_Fld(0x0f, SHURK_PI_RK0_ARPI_DQM_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_PI_0_1                                   ral_reg_DRAMC_blk_SHURK_PI_0_1                             -     @4899
+      RK0_ARPI_DQ_B1                               uvm_reg_field                                              ...    RW SHURK_PI_0_1[5:0]=6'h15 (Mirror: 6'h00)
+      RK0_ARPI_DQ_B0                               uvm_reg_field                                              ...    RW SHURK_PI_0_1[13:8]=6'h0e (Mirror: 6'h00)
+      RK0_ARPI_DQM_B1                              uvm_reg_field                                              ...    RW SHURK_PI_0_1[21:16]=6'h15 (Mirror: 6'h00)
+      RK0_ARPI_DQM_B0                              uvm_reg_field                                              ...    RW SHURK_PI_0_1[29:24]=6'h0e (Mirror: 6'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x15, SHURK_PI_RK0_ARPI_DQ_B1) |
+            P_Fld(0x0e, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x15, SHURK_PI_RK0_ARPI_DQM_B1) |
+            P_Fld(0x0e, SHURK_PI_RK0_ARPI_DQM_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0                    -     @7428
+      TX_ARDQ0_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h2c (Mirror: 8'h00)
+      TX_ARDQ1_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h2c (Mirror: 8'h00)
+      TX_ARDQ2_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h2c (Mirror: 8'h00)
+      TX_ARDQ3_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h2c (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+            P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+            P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0                    -     @7442
+      TX_ARDQ4_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h2c (Mirror: 8'h00)
+      TX_ARDQ5_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h2c (Mirror: 8'h00)
+      TX_ARDQ6_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h2c (Mirror: 8'h00)
+      TX_ARDQ7_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h2c (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+            P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+            P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0                    -     @7470
+      TX_ARDQM0_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h2c (Mirror: 8'h00)
+      TX_ARWCK_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00
+      TX_ARWCKB_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x2c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+            P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1                    -     @7435
+      TX_ARDQ0_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h2c (Mirror: 8'h00)
+      TX_ARDQ1_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h2c (Mirror: 8'h00)
+      TX_ARDQ2_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h2c (Mirror: 8'h00)
+      TX_ARDQ3_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h2c (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+            P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+            P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1                    -     @7449
+      TX_ARDQ4_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h2c (Mirror: 8'h00)
+      TX_ARDQ5_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h2c (Mirror: 8'h00)
+      TX_ARDQ6_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h2c (Mirror: 8'h00)
+      TX_ARDQ7_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h2c (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+            P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+            P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_TXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1                    -     @7476
+      TX_ARDQM0_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h2c (Mirror: 8'h00)
+      TX_ARWCK_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00
+      TX_ARWCKB_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+            P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1                    -     @8838
+      TX_ARDQ0_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h08 (Mirror: 8'h00)
+      TX_ARDQ1_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h08 (Mirror: 8'h00)
+      TX_ARDQ2_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h08 (Mirror: 8'h00)
+      TX_ARDQ3_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h08 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+            P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+            P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1                    -     @8852
+      TX_ARDQ4_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h08 (Mirror: 8'h00)
+      TX_ARDQ5_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h08 (Mirror: 8'h00)
+      TX_ARDQ6_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h08 (Mirror: 8'h00)
+      TX_ARDQ7_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h08 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+            P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+            P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_TXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1                    -     @8879
+      TX_ARDQM0_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h08 (Mirror: 8'h00)
+      TX_ARWCK_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00
+      TX_ARWCKB_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+            P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_TX_RANKCTL_0                               ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0                         -     @5345
+      TXRANKINCTL_TXDLY                            uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[3:0]=4'h2 (Mirror: 4'h0)
+      TXRANKINCTL                                  uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[7:4]=4'h2 (Mirror: 4'h0)
+      TXRANKINCTL_ROOT                             uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[11:8]=4'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) |
+            P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit:
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Enter
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_WCK_WR_MCK_0_0                           ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_0                     -     @4936
+      WCK_WR_B0_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_WR_MCK_0_0[3:0]=4'h3 (Mirror: 4'h1)
+      WCK_WR_B1_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_WR_MCK_0_0[7:4]=4'h3 (Mirror: 4'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK, P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) |
+            P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_WCK_WR_MCK_0_1                           ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_1                     -     @4941
+      WCK_WR_B0_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_WR_MCK_0_1[3:0]=4'h3 (Mirror: 4'h1)
+      WCK_WR_B1_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_WR_MCK_0_1[7:4]=4'h3 (Mirror: 4'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) |
+            P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_WCK_RD_MCK_0_0                           ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_0                     -     @4946
+      WCK_RD_B0_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_RD_MCK_0_0[3:0]=4'h4 (Mirror: 4'h1)
+      WCK_RD_B1_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_RD_MCK_0_0[7:4]=4'h4 (Mirror: 4'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK, P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
+            P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_WCK_RD_MCK_0_1                           ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_1                     -     @4951
+      WCK_RD_B0_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_RD_MCK_0_1[3:0]=4'h4 (Mirror: 4'h1)
+      WCK_RD_B1_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_RD_MCK_0_1[7:4]=4'h4 (Mirror: 4'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
+            P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_WCK_FS_MCK_0_0                           ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_0                     -     @4956
+      WCK_FS_B0_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_FS_MCK_0_0[3:0]=4'h2 (Mirror: 4'h1)
+      WCK_FS_B1_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_FS_MCK_0_0[7:4]=4'h2 (Mirror: 4'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK, P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) |
+            P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_WCK_FS_MCK_0_1                           ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_1                     -     @4961
+      WCK_FS_B0_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_FS_MCK_0_1[3:0]=4'h2 (Mirror: 4'h1)
+      WCK_FS_B1_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_FS_MCK_0_1[7:4]=4'h2 (Mirror: 4'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) |
+            P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_WCK_FS_UI_0_0                            ral_reg_DRAMC_blk_SHURK_WCK_FS_UI_0_0                      -     @4986
+      WCK_FS_B0_UI                                 uvm_reg_field                                              ...    RW SHURK_WCK_FS_UI_0_0[3:0]=4'h5 (Mirror: 4'h1)
+      WCK_FS_B1_UI                                 uvm_reg_field                                              ...    RW SHURK_WCK_FS_UI_0_0[7:4]=4'h5 (Mirror: 4'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI, P_Fld(0x5, SHURK_WCK_FS_UI_WCK_FS_B0_UI) |
+            P_Fld(0x5, SHURK_WCK_FS_UI_WCK_FS_B1_UI));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_WCK_FS_UI_0_1                            ral_reg_DRAMC_blk_SHURK_WCK_FS_UI_0_1                      -     @4991
+      WCK_FS_B0_UI                                 uvm_reg_field                                              ...    RW SHURK_WCK_FS_UI_0_1[3:0]=4'h5 (Mirror: 4'h1)
+      WCK_FS_B1_UI                                 uvm_reg_field                                              ...    RW SHURK_WCK_FS_UI_0_1[7:4]=4'h5 (Mirror: 4'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_WCK_FS_UI_WCK_FS_B0_UI) |
+            P_Fld(0x5, SHURK_WCK_FS_UI_WCK_FS_B1_UI));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Enter:
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_CA1_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA1_0                          -     @5041
+      TXDLY_CS                                     uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[2:0]=3'h0 (Mirror: 3'h1)
+      TXDLY_CKE                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[6:4]=3'h0 (Mirror: 3'h1)
+      TXDLY_ODT                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[10:8]=3'h0 (Mirror: 3'h1)
+      TXDLY_RESET                                  uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[14:12]=3'h0 (Mirror: 3'h1)
+      TXDLY_WE                                     uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[18:16]=3'h0 (Mirror: 3'h1)
+      TXDLY_CAS                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[22:20]=3'h0 (Mirror: 3'h1)
+      TXDLY_RAS                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[26:24]=3'h0 (Mirror: 3'h1)
+      TXDLY_CS1                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[30:28]=3'h0 (Mirror: 3'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) |
+            P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) |
+            P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) |
+            P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) |
+            P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_CA2_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA2_0                          -     @5052
+      TXDLY_BA0                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[2:0]=3'h0 (Mirror: 3'h1)
+      TXDLY_BA1                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[6:4]=3'h0 (Mirror: 3'h1)
+      TXDLY_BA2                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[10:8]=3'h0 (Mirror: 3'h1)
+      TXDLY_CMD                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[20:16]=5'h01
+      TXDLY_CKE1                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[26:24]=3'h0 (Mirror: 3'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) |
+            P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) |
+            P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_CA3_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA3_0                          -     @5060
+      TXDLY_RA0                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[2:0]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA1                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[6:4]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA2                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[10:8]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA3                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[14:12]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA4                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[18:16]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA5                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[22:20]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA6                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[26:24]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA7                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[30:28]=3'h0 (Mirror: 3'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) |
+            P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) |
+            P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) |
+            P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) |
+            P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_CA4_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA4_0                          -     @5071
+      TXDLY_RA8                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[2:0]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA9                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[6:4]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA10                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[10:8]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA11                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[14:12]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA12                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[18:16]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA13                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[22:20]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA14                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[26:24]=3'h0 (Mirror: 3'h1)
+      TXDLY_RA15                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[30:28]=3'h0 (Mirror: 3'h1)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) |
+            P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) |
+            P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) |
+            P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) |
+            P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SELPH_CA5_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA5_0                          -     @5082
+      dly_CS                                       uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[2:0]=3'h1
+      dly_CKE                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[6:4]=3'h1
+      dly_ODT                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[10:8]=3'h0 (Mirror: 3'h1)
+      dly_RESET                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[14:12]=3'h1
+      dly_WE                                       uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[18:16]=3'h1
+      dly_CAS                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[22:20]=3'h1
+      dly_RAS                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[26:24]=3'h1
+      dly_CS1                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[30:28]=3'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5, P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) |
+            P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) |
+            P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) |
+            P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) |
+            P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter:
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SREF_CTRL_0                                ral_reg_DRAMC_blk_SHU_SREF_CTRL_0                          -     @5018
+      CKEHCMD                                      uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[5:4]=2'h3
+      SREF_CK_DLY                                  uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) |
+            P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_HMR4_DVFS_CTRL0_0                          ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0                    -     @5036
+      FSPCHG_PRDCNT                                uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h64 (Mirror: 8'h00)
+      REFRCNT                                      uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x64, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+            P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_AC_TIME_05T_0                              ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0                        -     @5199
+      TRC_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[0:0]=1'h1 (Mirror: 1'h0)
+      TRFCPB_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[1:1]=1'h0
+      TRFC_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[2:2]=1'h0
+      TPBR2PBR_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[3:3]=1'h0
+      TXP_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[4:4]=1'h1 (Mirror: 1'h0)
+      TRTP_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[5:5]=1'h0
+      TRCD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[6:6]=1'h1 (Mirror: 1'h0)
+      TRP_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[7:7]=1'h1 (Mirror: 1'h0)
+      TRPAB_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[8:8]=1'h1 (Mirror: 1'h0)
+      TRAS_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[9:9]=1'h0
+      TWR_M05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0)
+      TRRD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[12:12]=1'h0
+      TFAW_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[13:13]=1'h0
+      TCKEPRD_05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[14:14]=1'h0
+      TR2PD_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[15:15]=1'h0
+      TWTPD_M05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[16:16]=1'h1 (Mirror: 1'h0)
+      TMRRI_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[17:17]=1'h1 (Mirror: 1'h0)
+      TMRWCKEL_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[18:18]=1'h0
+      BGTRRD_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[19:19]=1'h0
+      BGTCCD_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[20:20]=1'h0
+      BGTWTR_M05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[21:21]=1'h0
+      TR2W_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[22:22]=1'h1 (Mirror: 1'h0)
+      TWTR_M05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[23:23]=1'h0
+      XRTR2W_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[24:24]=1'h0
+      TMRD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[25:25]=1'h0
+      TMRW_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[26:26]=1'h0
+      TMRR2MRW_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[27:27]=1'h0
+      TW2MRW_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[28:28]=1'h0
+      TR2MRW_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[29:29]=1'h0
+      TPBR2ACT_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[30:30]=1'h0
+      XRTW2R_M05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x1, SHU_AC_TIME_05T_TRC_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TXP_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRCD_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRPAB_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRRI_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTWTR_M05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TWTR_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRD_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRR2MRW_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM_XRT_0                                ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0                          -     @5192
+      XRTR2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[4:0]=5'h09 (Mirror: 5'h01)
+      XRTR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[13:8]=6'h0b (Mirror: 6'h01)
+      XRTW2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[19:16]=4'h6 (Mirror: 4'h1)
+      XRTW2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[28:24]=5'h06 (Mirror: 5'h01)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x09, SHU_ACTIM_XRT_XRTR2R) |
+            P_Fld(0x0b, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x6, SHU_ACTIM_XRT_XRTW2R) |
+            P_Fld(0x06, SHU_ACTIM_XRT_XRTW2W));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM0_0                                   ral_reg_DRAMC_blk_SHU_ACTIM0_0                             -     @5138
+      TWTR                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[3:0]=4'h9 (Mirror: 4'h1)
+      CKELCKCNT                                    uvm_reg_field                                              ...    RW SHU_ACTIM0_0[6:4]=3'h3 (Mirror: 3'h0)
+      TWR                                          uvm_reg_field                                              ...    RW SHU_ACTIM0_0[15:8]=8'h13 (Mirror: 8'h06)
+      TRRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[18:16]=3'h2 (Mirror: 3'h0)
+      TRCD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[27:24]=4'h7 (Mirror: 4'h2)
+      TWTR_L                                       uvm_reg_field                                              ...    RW SHU_ACTIM0_0[31:28]=4'h9 (Mirror: 4'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x9, SHU_ACTIM0_TWTR) |
+            P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x13, SHU_ACTIM0_TWR) |
+            P_Fld(0x2, SHU_ACTIM0_TRRD) | P_Fld(0x7, SHU_ACTIM0_TRCD) |
+            P_Fld(0x9, SHU_ACTIM0_TWTR_L));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM1_0                                   ral_reg_DRAMC_blk_SHU_ACTIM1_0                             -     @5147
+      TRPAB                                        uvm_reg_field                                              ...    RW SHU_ACTIM1_0[3:0]=4'h8 (Mirror: 4'ha)
+      TMRWCKEL                                     uvm_reg_field                                              ...    RW SHU_ACTIM1_0[7:4]=4'h8
+      TRP                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[11:8]=4'h7 (Mirror: 4'h2)
+      TRAS                                         uvm_reg_field                                              ...    RW SHU_ACTIM1_0[21:16]=6'h08 (Mirror: 6'h04)
+      TRC                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[28:24]=5'h10 (Mirror: 5'h05)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x8, SHU_ACTIM1_TRPAB) |
+            P_Fld(0x8, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x7, SHU_ACTIM1_TRP) |
+            P_Fld(0x08, SHU_ACTIM1_TRAS) | P_Fld(0x10, SHU_ACTIM1_TRC));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM2_0                                   ral_reg_DRAMC_blk_SHU_ACTIM2_0                             -     @5155
+      TXP                                          uvm_reg_field                                              ...    RW SHU_ACTIM2_0[3:0]=4'h2 (Mirror: 4'h0)
+      TMRRI                                        uvm_reg_field                                              ...    RW SHU_ACTIM2_0[8:4]=5'h0b (Mirror: 5'h0e)
+      TRTP                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[14:12]=3'h2 (Mirror: 3'h0)
+      TR2W                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[21:16]=6'h06 (Mirror: 6'h00)
+      TFAW                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[28:24]=5'h00 (Mirror: 5'h05)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x2, SHU_ACTIM2_TXP) |
+            P_Fld(0x0b, SHU_ACTIM2_TMRRI) | P_Fld(0x2, SHU_ACTIM2_TRTP) |
+            P_Fld(0x06, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM3_0                                   ral_reg_DRAMC_blk_SHU_ACTIM3_0                             -     @5163
+      TRFCPB                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[7:0]=8'h2c (Mirror: 8'h00)
+      MANTMRR                                      uvm_reg_field                                              ...    RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0)
+      TR2MRR                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0)
+      TRFC                                         uvm_reg_field                                              ...    RW SHU_ACTIM3_0[23:16]=8'h64 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x2c, SHU_ACTIM3_TRFCPB) |
+            P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) |
+            P_Fld(0x64, SHU_ACTIM3_TRFC));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM4_0                                   ral_reg_DRAMC_blk_SHU_ACTIM4_0                             -     @5170
+      TXREFCNT                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[9:0]=10'h073 (Mirror: 10'h028)
+      TMRR2MRW                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[15:10]=6'h0f (Mirror: 6'h00)
+      TMRR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM4_0[21:16]=6'h0c (Mirror: 6'h00)
+      TZQCS                                        uvm_reg_field                                              ...    RW SHU_ACTIM4_0[31:24]=8'h22 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x073, SHU_ACTIM4_TXREFCNT) |
+            P_Fld(0x0f, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0c, SHU_ACTIM4_TMRR2W) |
+            P_Fld(0x22, SHU_ACTIM4_TZQCS));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM5_0                                   ral_reg_DRAMC_blk_SHU_ACTIM5_0                             -     @5177
+      TR2PD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[6:0]=7'h11 (Mirror: 7'h00)
+      TWTPD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[14:8]=7'h16 (Mirror: 7'h00)
+      TPBR2PBR                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[23:16]=8'h24 (Mirror: 8'h00)
+      TPBR2ACT                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[29:28]=2'h3 (Mirror: 2'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x11, SHU_ACTIM5_TR2PD) |
+            P_Fld(0x16, SHU_ACTIM5_TWTPD) | P_Fld(0x24, SHU_ACTIM5_TPBR2PBR) |
+            P_Fld(0x3, SHU_ACTIM5_TPBR2ACT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM6_0                                   ral_reg_DRAMC_blk_SHU_ACTIM6_0                             -     @5184
+      TZQLAT2                                      uvm_reg_field                                              ...    RW SHU_ACTIM6_0[4:0]=5'h0c (Mirror: 5'h1f)
+      TMRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[11:8]=4'h6 (Mirror: 4'h0)
+      TMRW                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0)
+      TW2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[25:20]=6'h0a (Mirror: 6'h00)
+      TR2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[31:26]=6'h0f (Mirror: 6'h13)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x0c, SHU_ACTIM6_TZQLAT2) |
+            P_Fld(0x6, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) |
+            P_Fld(0x0a, SHU_ACTIM6_TW2MRW) | P_Fld(0x0f, SHU_ACTIM6_TR2MRW));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_CKECTRL_0                                  ral_reg_DRAMC_blk_SHU_CKECTRL_0                            -     @5262
+      TPDE_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0)
+      TPDX_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[1:1]=1'h1 (Mirror: 1'h0)
+      TPDE                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[14:12]=3'h2 (Mirror: 3'h1)
+      TPDX                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[18:16]=3'h1
+      TCKEPRD                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[22:20]=3'h4 (Mirror: 3'h2)
+      TCKESRX                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) |
+            P_Fld(0x1, SHU_CKECTRL_TPDX_05T) | P_Fld(0x2, SHU_CKECTRL_TPDE) |
+            P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x4, SHU_CKECTRL_TCKEPRD) |
+            P_Fld(0x3, SHU_CKECTRL_TCKESRX));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MISC_0                                     ral_reg_DRAMC_blk_SHU_MISC_0                               -     @5365
+      REQQUE_MAXCNT                                uvm_reg_field                                              ...    RW SHU_MISC_0[3:0]=4'h2
+      DCMDLYREF                                    uvm_reg_field                                              ...    RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4)
+      DAREFEN                                      uvm_reg_field                                              ...    RW SHU_MISC_0[30:30]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) |
+            P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_LP5_CMD_0                                  ral_reg_DRAMC_blk_SHU_LP5_CMD_0                            -     @5427
+      LP5_CMD1TO2EN                                uvm_reg_field                                              ...    RW SHU_LP5_CMD_0[0:0]=1'h0
+      TCSH                                         uvm_reg_field                                              ...    RW SHU_LP5_CMD_0[7:4]=4'h5 (Mirror: 4'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_LP5_CMD, P_Fld(0x0, SHU_LP5_CMD_LP5_CMD1TO2EN) |
+            P_Fld(0x5, SHU_LP5_CMD_TCSH));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIM7_0                                   ral_reg_DRAMC_blk_SHU_ACTIM7_0                             -     @5436
+      TCSH_CSCAL                                   uvm_reg_field                                              ...    RW SHU_ACTIM7_0[3:0]=4'h3 (Mirror: 4'h0)
+      TCACSH                                       uvm_reg_field                                              ...    RW SHU_ACTIM7_0[7:4]=4'h1 (Mirror: 4'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM7, P_Fld(0x3, SHU_ACTIM7_TCSH_CSCAL) |
+            P_Fld(0x1, SHU_ACTIM7_TCACSH));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_WCKCTRL_0                                  ral_reg_DRAMC_blk_SHU_WCKCTRL_0                            -     @5407
+      WCKRDOFF                                     uvm_reg_field                                              ...    RW SHU_WCKCTRL_0[5:0]=6'h0c (Mirror: 6'h00)
+      WCKRDOFF_05T                                 uvm_reg_field                                              ...    RW SHU_WCKCTRL_0[7:7]=1'h0
+      WCKWROFF                                     uvm_reg_field                                              ...    RW SHU_WCKCTRL_0[13:8]=6'h08 (Mirror: 6'h00)
+      WCKWROFF_05T                                 uvm_reg_field                                              ...    RW SHU_WCKCTRL_0[15:15]=1'h0
+      WCKDUAL                                      uvm_reg_field                                              ...    RW SHU_WCKCTRL_0[16:16]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_WCKCTRL, P_Fld(0x0c, SHU_WCKCTRL_WCKRDOFF) |
+            P_Fld(0x0, SHU_WCKCTRL_WCKRDOFF_05T) | P_Fld(0x08, SHU_WCKCTRL_WCKWROFF) |
+            P_Fld(0x0, SHU_WCKCTRL_WCKWROFF_05T) | P_Fld(0x0, SHU_WCKCTRL_WCKDUAL));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter.
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit.
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ8_0                            -     @7828
+      R_DMRXDVS_UPD_FORCE_CYC_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[14:0]=15'h00c4 (Mirror: 15'h0000)
+      R_DMRXDVS_UPD_FORCE_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[15:15]=1'h0
+      R_DMRANK_RXDLY_PIPE_CG_IG_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[19:19]=1'h0
+      R_RMRODTEN_CG_IG_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[20:20]=1'h0
+      R_RMRX_TOPHY_CG_IG_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)
+      R_DMRXDVS_RDSEL_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[22:22]=1'h0
+      R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0            uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[23:23]=1'h0
+      R_DMRXDLY_CG_IG_B0                           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)
+      R_DMDQSIEN_FLAG_SYNC_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[26:26]=1'h0
+      R_DMDQSIEN_FLAG_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[27:27]=1'h0
+      R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0               uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[28:28]=1'h0
+      R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[29:29]=1'h0
+      R_DMRANK_PIPE_CG_IG_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[30:30]=1'h0
+      R_DMRANK_CHG_PIPE_CG_IG_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x00c4, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+            P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ8_0                            -     @9231
+      R_DMRXDVS_UPD_FORCE_CYC_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[14:0]=15'h00c4 (Mirror: 15'h0000)
+      R_DMRXDVS_UPD_FORCE_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[15:15]=1'h0
+      R_DMRANK_RXDLY_PIPE_CG_IG_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[19:19]=1'h0
+      R_RMRODTEN_CG_IG_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[20:20]=1'h0
+      R_RMRX_TOPHY_CG_IG_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)
+      R_DMRXDVS_RDSEL_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[22:22]=1'h0
+      R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1            uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[23:23]=1'h0
+      R_DMRXDLY_CG_IG_B1                           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)
+      R_DMDQSIEN_FLAG_SYNC_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[26:26]=1'h0
+      R_DMDQSIEN_FLAG_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[27:27]=1'h0
+      R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1               uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[28:28]=1'h0
+      R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[29:29]=1'h0
+      R_DMRANK_PIPE_CG_IG_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[30:30]=1'h0
+      R_DMRANK_CHG_PIPE_CG_IG_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x00c4, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+            P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B0_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ5_0                            -     @7728
+      RG_RX_ARDQ_VREF_SEL_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[5:0]=6'h0e
+      RG_RX_ARDQ_VREF_BYPASS_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[6:6]=1'h0
+      RG_ARPI_FB_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[13:8]=6'h00
+      RG_RX_ARDQS0_DQSIEN_DLY_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[18:16]=3'h0
+      RG_RX_ARDQS_DQSIEN_RB_DLY_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[19:19]=1'h0
+      RG_RX_ARDQS0_DVS_DLY_B0                      uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[23:20]=4'h4 (Mirror: 4'h0)
+      RG_RX_ARDQ_FIFO_DQSI_DLY_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[31:29]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) |
+            P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) |
+            P_Fld(0x4, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_B1_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ5_0                            -     @9131
+      RG_RX_ARDQ_VREF_SEL_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[5:0]=6'h0e
+      RG_RX_ARDQ_VREF_BYPASS_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[6:6]=1'h0
+      RG_ARPI_FB_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[13:8]=6'h00
+      RG_RX_ARDQS0_DQSIEN_DLY_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[18:16]=3'h0
+      RG_RX_ARDQS_DQSIEN_RB_DLY_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[19:19]=1'h0
+      RG_RX_ARDQS0_DVS_DLY_B1                      uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[23:20]=4'h4 (Mirror: 4'h0)
+      RG_RX_ARDQ_FIFO_DQSI_DLY_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[31:29]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) |
+            P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) |
+            P_Fld(0x4, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0                    -     @7490
+      RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h76 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x76, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+            P_Fld(0x76, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x76, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
+            P_Fld(0x76, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0                    -     @7504
+      RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h76 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x76, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+            P_Fld(0x76, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x76, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+            P_Fld(0x76, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0                    -     @7518
+      RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h76 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x76, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+            P_Fld(0x76, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x76, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+            P_Fld(0x76, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0                    -     @7532
+      RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h76 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x76, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+            P_Fld(0x76, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x76, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+            P_Fld(0x76, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0                    -     @7546
+      RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h76 (Mirror: 8'h00)
+      RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h76 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x76, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+            P_Fld(0x76, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0                    -     @7556
+      RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h047 (Mirror: 9'h000)
+      RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h047 (Mirror: 9'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x047, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+            P_Fld(0x047, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1                    -     @7497
+      RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h75 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1                    -     @7511
+      RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h75 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1                    -     @7525
+      RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h75 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1                    -     @7539
+      RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h75 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1                    -     @7551
+      RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h75 (Mirror: 8'h00)
+      RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h75 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+            P_Fld(0x75, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B0_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1                    -     @7561
+      RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h046 (Mirror: 9'h000)
+      RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h046 (Mirror: 9'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x046, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+            P_Fld(0x046, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0                    -     @8893
+      RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h76 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x76, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+            P_Fld(0x76, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x76, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
+            P_Fld(0x76, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0                    -     @8907
+      RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h76 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x76, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+            P_Fld(0x76, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x76, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+            P_Fld(0x76, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0                    -     @8921
+      RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h76 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x76, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+            P_Fld(0x76, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x76, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+            P_Fld(0x76, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0                    -     @8935
+      RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h76 (Mirror: 8'h00)
+      RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h76 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x76, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+            P_Fld(0x76, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x76, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+            P_Fld(0x76, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0                    -     @8949
+      RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h76 (Mirror: 8'h00)
+      RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h76 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x76, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+            P_Fld(0x76, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0                    -     @8959
+      RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h047 (Mirror: 9'h000)
+      RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h047 (Mirror: 9'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x047, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+            P_Fld(0x047, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1                    -     @8900
+      RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h75 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1                    -     @8914
+      RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h75 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1                    -     @8928
+      RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h75 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1                    -     @8942
+      RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h75 (Mirror: 8'h00)
+      RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h75 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1                    -     @8954
+      RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h75 (Mirror: 8'h00)
+      RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h75 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+            P_Fld(0x75, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_R0_B1_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1                    -     @8964
+      RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h046 (Mirror: 9'h000)
+      RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h046 (Mirror: 9'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x046, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+            P_Fld(0x046, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ9                                         ral_reg_DDRPHY_blk_B0_DQ9                                  -     @7384
+      RG_RX_ARDQ_STBEN_RESETB_B0                   uvm_reg_field                                              ...    RW B0_DQ9[0:0]=1'h0 (Mirror: 1'h1)
+      RG_RX_ARDQS0_STBEN_RESETB_B0                 uvm_reg_field                                              ...    RW B0_DQ9[4:4]=1'h1
+      RG_RX_ARDQS0_DQSIENMODE_B0                   uvm_reg_field                                              ...    RW B0_DQ9[5:5]=1'h0
+      R_DMRXDVS_R_F_DLY_RK_OPT_B0                  uvm_reg_field                                              ...    RW B0_DQ9[6:6]=1'h1
+      R_DMRXFIFO_STBENCMP_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ9[7:7]=1'h0
+      R_IN_GATE_EN_LOW_OPT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[15:8]=8'h00
+      R_DMDQSIEN_VALID_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[18:16]=3'h0
+      R_DMDQSIEN_RDSEL_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[22:20]=3'h0
+      R_DMRXDVS_VALID_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[26:24]=3'h0
+      R_DMRXDVS_RDSEL_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[30:28]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
+            P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
+            P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
+            P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
+            P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
+            P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ9                                         ral_reg_DDRPHY_blk_B1_DQ9                                  -     @8787
+      RG_RX_ARDQ_STBEN_RESETB_B1                   uvm_reg_field                                              ...    RW B1_DQ9[0:0]=1'h0 (Mirror: 1'h1)
+      RG_RX_ARDQS0_STBEN_RESETB_B1                 uvm_reg_field                                              ...    RW B1_DQ9[4:4]=1'h1
+      RG_RX_ARDQS0_DQSIENMODE_B1                   uvm_reg_field                                              ...    RW B1_DQ9[5:5]=1'h0
+      R_DMRXDVS_R_F_DLY_RK_OPT_B1                  uvm_reg_field                                              ...    RW B1_DQ9[6:6]=1'h1
+      R_DMRXFIFO_STBENCMP_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ9[7:7]=1'h0
+      R_IN_GATE_EN_LOW_OPT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[15:8]=8'h00
+      R_DMDQSIEN_VALID_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[18:16]=3'h0
+      R_DMDQSIEN_RDSEL_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[22:20]=3'h0
+      R_DMRXDVS_VALID_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[26:24]=3'h0
+      R_DMRXDVS_RDSEL_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[30:28]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
+            P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
+            P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
+            P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
+            P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
+            P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ9                                         ral_reg_DDRPHY_blk_B0_DQ9                                  -     @7384
+      RG_RX_ARDQ_STBEN_RESETB_B0                   uvm_reg_field                                              ...    RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0)
+      RG_RX_ARDQS0_STBEN_RESETB_B0                 uvm_reg_field                                              ...    RW B0_DQ9[4:4]=1'h1
+      RG_RX_ARDQS0_DQSIENMODE_B0                   uvm_reg_field                                              ...    RW B0_DQ9[5:5]=1'h0
+      R_DMRXDVS_R_F_DLY_RK_OPT_B0                  uvm_reg_field                                              ...    RW B0_DQ9[6:6]=1'h1
+      R_DMRXFIFO_STBENCMP_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ9[7:7]=1'h0
+      R_IN_GATE_EN_LOW_OPT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[15:8]=8'h00
+      R_DMDQSIEN_VALID_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[18:16]=3'h0
+      R_DMDQSIEN_RDSEL_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[22:20]=3'h0
+      R_DMRXDVS_VALID_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[26:24]=3'h0
+      R_DMRXDVS_RDSEL_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[30:28]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
+            P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
+            P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
+            P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
+            P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
+            P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ9                                         ral_reg_DDRPHY_blk_B1_DQ9                                  -     @8787
+      RG_RX_ARDQ_STBEN_RESETB_B1                   uvm_reg_field                                              ...    RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0)
+      RG_RX_ARDQS0_STBEN_RESETB_B1                 uvm_reg_field                                              ...    RW B1_DQ9[4:4]=1'h1
+      RG_RX_ARDQS0_DQSIENMODE_B1                   uvm_reg_field                                              ...    RW B1_DQ9[5:5]=1'h0
+      R_DMRXDVS_R_F_DLY_RK_OPT_B1                  uvm_reg_field                                              ...    RW B1_DQ9[6:6]=1'h1
+      R_DMRXFIFO_STBENCMP_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ9[7:7]=1'h0
+      R_IN_GATE_EN_LOW_OPT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[15:8]=8'h00
+      R_DMDQSIEN_VALID_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[18:16]=3'h0
+      R_DMDQSIEN_RDSEL_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[22:20]=3'h0
+      R_DMRXDVS_VALID_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[26:24]=3'h0
+      R_DMRXDVS_RDSEL_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[30:28]=3'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
+            P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
+            P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
+            P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
+            P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
+            P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ4                                         ral_reg_DDRPHY_blk_B0_DQ4                                  -     @7313
+      RG_RX_ARDQS_EYE_R_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[6:0]=7'h7e (Mirror: 7'h00)
+      RG_RX_ARDQS_EYE_F_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[14:8]=7'h7e (Mirror: 7'h00)
+      RG_RX_ARDQ_EYE_R_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[21:16]=6'h36 (Mirror: 6'h00)
+      RG_RX_ARDQ_EYE_F_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[29:24]=6'h36 (Mirror: 6'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x7e, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) |
+            P_Fld(0x7e, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x36, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) |
+            P_Fld(0x36, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ4                                         ral_reg_DDRPHY_blk_B1_DQ4                                  -     @8716
+      RG_RX_ARDQS_EYE_R_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[6:0]=7'h7e (Mirror: 7'h00)
+      RG_RX_ARDQS_EYE_F_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[14:8]=7'h7e (Mirror: 7'h00)
+      RG_RX_ARDQ_EYE_R_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[21:16]=6'h36 (Mirror: 6'h00)
+      RG_RX_ARDQ_EYE_F_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[29:24]=6'h36 (Mirror: 6'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x7e, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) |
+            P_Fld(0x7e, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x36, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) |
+            P_Fld(0x36, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B0_DQ5                                         ral_reg_DDRPHY_blk_B0_DQ5                                  -     @7320
+      RG_RX_ARDQ_EYE_VREF_SEL_B0                   uvm_reg_field                                              ...    RW B0_DQ5[13:8]=6'h10
+      RG_RX_ARDQ_VREF_EN_B0                        uvm_reg_field                                              ...    RW B0_DQ5[16:16]=1'h1
+      RG_RX_ARDQ_EYE_VREF_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ5[17:17]=1'h1
+      RG_RX_ARDQ_EYE_SEL_B0                        uvm_reg_field                                              ...    RW B0_DQ5[23:20]=4'h0
+      RG_RX_ARDQ_EYE_EN_B0                         uvm_reg_field                                              ...    RW B0_DQ5[24:24]=1'h1
+      RG_RX_ARDQ_EYE_STBEN_RESETB_B0               uvm_reg_field                                              ...    RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0)
+      RG_RX_ARDQS0_DVS_EN_B0                       uvm_reg_field                                              ...    RW B0_DQ5[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x10, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) |
+            P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) |
+            P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) |
+            P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    B1_DQ5                                         ral_reg_DDRPHY_blk_B1_DQ5                                  -     @8723
+      RG_RX_ARDQ_EYE_VREF_SEL_B1                   uvm_reg_field                                              ...    RW B1_DQ5[13:8]=6'h10
+      RG_RX_ARDQ_VREF_EN_B1                        uvm_reg_field                                              ...    RW B1_DQ5[16:16]=1'h1
+      RG_RX_ARDQ_EYE_VREF_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ5[17:17]=1'h1
+      RG_RX_ARDQ_EYE_SEL_B1                        uvm_reg_field                                              ...    RW B1_DQ5[23:20]=4'h0
+      RG_RX_ARDQ_EYE_EN_B1                         uvm_reg_field                                              ...    RW B1_DQ5[24:24]=1'h1
+      RG_RX_ARDQ_EYE_STBEN_RESETB_B1               uvm_reg_field                                              ...    RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0)
+      RG_RX_ARDQS0_DVS_EN_B1                       uvm_reg_field                                              ...    RW B1_DQ5[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x10, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) |
+            P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) |
+            P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) |
+            P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Enter
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_COMMON0_0                                  ral_reg_DRAMC_blk_SHU_COMMON0_0                            -     @5001
+      FREQDIV4                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[0:0]=1'h1 (Mirror: 1'h0)
+      FDIV2                                        uvm_reg_field                                              ...    RW SHU_COMMON0_0[1:1]=1'h0
+      FREQDIV8                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[2:2]=1'h0
+      DM64BITEN                                    uvm_reg_field                                              ...    RW SHU_COMMON0_0[4:4]=1'h1 (Mirror: 1'h0)
+      DLE256EN                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[5:5]=1'h0
+      LP5BGEN                                      uvm_reg_field                                              ...    RW SHU_COMMON0_0[6:6]=1'h0
+      LP5WCKON                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[7:7]=1'h0
+      CL2                                          uvm_reg_field                                              ...    RW SHU_COMMON0_0[8:8]=1'h0
+      BL2                                          uvm_reg_field                                              ...    RW SHU_COMMON0_0[9:9]=1'h0
+      BL4                                          uvm_reg_field                                              ...    RW SHU_COMMON0_0[10:10]=1'h1 (Mirror: 1'h0)
+      LP5BGOTF                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[11:11]=1'h0
+      BC4OTF                                       uvm_reg_field                                              ...    RW SHU_COMMON0_0[12:12]=1'h1
+      LP5HEFF_MODE                                 uvm_reg_field                                              ...    RW SHU_COMMON0_0[13:13]=1'h0
+      SHU_COMMON0_RSV                              uvm_reg_field                                              ...    RW SHU_COMMON0_0[31:15]=17'h00000
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0, P_Fld(0x1, SHU_COMMON0_FREQDIV4) |
+            P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x0, SHU_COMMON0_FREQDIV8) |
+            P_Fld(0x1, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) |
+            P_Fld(0x0, SHU_COMMON0_LP5BGEN) | P_Fld(0x0, SHU_COMMON0_LP5WCKON) |
+            P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) |
+            P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) |
+            P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x0, SHU_COMMON0_LP5HEFF_MODE) |
+            P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_WCKCTRL_1_0                                ral_reg_DRAMC_blk_SHU_WCKCTRL_1_0                          -     @5415
+      WCKSYNC_PRE_MODE                             uvm_reg_field                                              ...    RW SHU_WCKCTRL_1_0[0:0]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DRAMC_REG_SHU_WCKCTRL_1, 0x1, SHU_WCKCTRL_1_WCKSYNC_PRE_MODE);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ACTIMING_CONF_0                            ral_reg_DRAMC_blk_SHU_ACTIMING_CONF_0                      -     @5255
+      SCINTV                                       uvm_reg_field                                              ...    RW SHU_ACTIMING_CONF_0[5:0]=6'h26 (Mirror: 6'h2a)
+      TRFCPBIG                                     uvm_reg_field                                              ...    RW SHU_ACTIMING_CONF_0[8:8]=1'h0
+      REFBW_FR                                     uvm_reg_field                                              ...    RW SHU_ACTIMING_CONF_0[25:16]=10'h000
+      TREFBWIG                                     uvm_reg_field                                              ...    RW SHU_ACTIMING_CONF_0[31:31]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF, P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) |
+            P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) |
+            P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_DCM_CTRL0_0                                ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0                          -     @5027
+      DDRPHY_CLK_EN_OPT                            uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[7:7]=1'h1
+      DPHY_CMDDCM_EXTCNT                           uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[11:8]=4'h4
+      DDRPHY_CLK_DYN_GATING_SEL                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[15:12]=4'h5
+      CKE_EXTNONPD_CNT                             uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[19:16]=4'h0
+      FASTWAKE2                                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[29:29]=1'h1 (Mirror: 1'h0)
+      FASTWAKE                                     uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[31:31]=1'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+            P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+            P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) |
+            P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_CONF0_0                                    ral_reg_DRAMC_blk_SHU_CONF0_0                              -     @5356
+      DMPGTIM                                      uvm_reg_field                                              ...    RW SHU_CONF0_0[5:0]=6'h3f (Mirror: 6'h08)
+      ADVREFEN                                     uvm_reg_field                                              ...    RW SHU_CONF0_0[6:6]=1'h0
+      ADVPREEN                                     uvm_reg_field                                              ...    RW SHU_CONF0_0[7:7]=1'h1 (Mirror: 1'h0)
+      PBREFEN                                      uvm_reg_field                                              ...    RW SHU_CONF0_0[8:8]=1'h1 (Mirror: 1'h0)
+      REFTHD                                       uvm_reg_field                                              ...    RW SHU_CONF0_0[15:12]=4'h1 (Mirror: 4'h0)
+      REQQUE_DEPTH                                 uvm_reg_field                                              ...    RW SHU_CONF0_0[19:16]=4'h8
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x3f, SHU_CONF0_DMPGTIM) |
+            P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) |
+            P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) |
+            P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_MATYPE_0                                   ral_reg_DRAMC_blk_SHU_MATYPE_0                             -     @4996
+      MATYPE                                       uvm_reg_field                                              ...    RW SHU_MATYPE_0[1:0]=2'h2 (Mirror: 2'h0)
+      NORMPOP_LEN                                  uvm_reg_field                                              ...    RW SHU_MATYPE_0[6:4]=3'h1
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE, P_Fld(0x2, SHU_MATYPE_MATYPE) |
+            P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_SCHEDULER_0                                ral_reg_DRAMC_blk_SHU_SCHEDULER_0                          -     @5023
+      DUALSCHEN                                    uvm_reg_field                                              ...    RW SHU_SCHEDULER_0[2:2]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldAlign(DRAMC_REG_SHU_SCHEDULER, 0x1, SHU_SCHEDULER_DUALSCHEN);
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    TX_SET0                                        ral_reg_DRAMC_blk_TX_SET0                                  -     @3899
+      TXRANK                                       uvm_reg_field                                              ...    RW TX_SET0[1:0]=2'h0
+      TXRANKFIX                                    uvm_reg_field                                              ...    RW TX_SET0[2:2]=1'h0
+      DDRPHY_COMB_CG_SEL                           uvm_reg_field                                              ...    RW TX_SET0[3:3]=1'h0
+      TX_DQM_DEFAULT                               uvm_reg_field                                              ...    RW TX_SET0[4:4]=1'h1
+      DQBUS_X32                                    uvm_reg_field                                              ...    RW TX_SET0[5:5]=1'h0
+      OE_DOWNGRADE                                 uvm_reg_field                                              ...    RW TX_SET0[6:6]=1'h0
+      DQ16COM1                                     uvm_reg_field                                              ...    RW TX_SET0[21:21]=1'h0
+      WPRE2T                                       uvm_reg_field                                              ...    RW TX_SET0[22:22]=1'h1 (Mirror: 1'h0)
+      DRSCLR_EN                                    uvm_reg_field                                              ...    RW TX_SET0[24:24]=1'h0
+      DRSCLR_RK0_EN                                uvm_reg_field                                              ...    RW TX_SET0[25:25]=1'h0
+      ARPI_CAL_E2OPT                               uvm_reg_field                                              ...    RW TX_SET0[26:26]=1'h0
+      TX_DLY_CAL_E2OPT                             uvm_reg_field                                              ...    RW TX_SET0[27:27]=1'h0
+      DQS_OE_OP1_DIS                               uvm_reg_field                                              ...    RW TX_SET0[28:28]=1'h0
+      DQS_OE_OP2_EN                                uvm_reg_field                                              ...    RW TX_SET0[29:29]=1'h0
+      RK_SCINPUT_OPT                               uvm_reg_field                                              ...    RW TX_SET0[30:30]=1'h0
+      DRAMOEN                                      uvm_reg_field                                              ...    RW TX_SET0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_TX_SET0, P_Fld(0x0, TX_SET0_TXRANK) |
+            P_Fld(0x0, TX_SET0_TXRANKFIX) | P_Fld(0x0, TX_SET0_DDRPHY_COMB_CG_SEL) |
+            P_Fld(0x1, TX_SET0_TX_DQM_DEFAULT) | P_Fld(0x0, TX_SET0_DQBUS_X32) |
+            P_Fld(0x0, TX_SET0_OE_DOWNGRADE) | P_Fld(0x0, TX_SET0_DQ16COM1) |
+            P_Fld(0x1, TX_SET0_WPRE2T) | P_Fld(0x0, TX_SET0_DRSCLR_EN) |
+            P_Fld(0x0, TX_SET0_DRSCLR_RK0_EN) | P_Fld(0x0, TX_SET0_ARPI_CAL_E2OPT) |
+            P_Fld(0x0, TX_SET0_TX_DLY_CAL_E2OPT) | P_Fld(0x0, TX_SET0_DQS_OE_OP1_DIS) |
+            P_Fld(0x0, TX_SET0_DQS_OE_OP2_EN) | P_Fld(0x0, TX_SET0_RK_SCINPUT_OPT) |
+            P_Fld(0x0, TX_SET0_DRAMOEN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_TX_SET0_0                                  ral_reg_DRAMC_blk_SHU_TX_SET0_0                            -     @5306
+      DQOE_CNT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[3:0]=4'h0
+      DQOE_OPT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[4:4]=1'h0
+      TXUPD_SEL                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[7:6]=2'h0
+      TXUPD_W2R_SEL                                uvm_reg_field                                              ...    RW SHU_TX_SET0_0[10:8]=3'h2 (Mirror: 3'h0)
+      WECC_EN                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[11:11]=1'h0
+      DBIWR                                        uvm_reg_field                                              ...    RW SHU_TX_SET0_0[12:12]=1'h0
+      WDATRGO                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[13:13]=1'h0
+      TWPSTEXT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[14:14]=1'h0
+      WPST1P5T                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[15:15]=1'h1 (Mirror: 1'h0)
+      TXOEN_AUTOSET_OFFSET                         uvm_reg_field                                              ...    RW SHU_TX_SET0_0[19:16]=4'h3
+      TWCKPST                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[21:20]=2'h1
+      OE_EXT2UI                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[24:22]=3'h1 (Mirror: 3'h0)
+      DQS2DQ_FILT_PITHRD                           uvm_reg_field                                              ...    RW SHU_TX_SET0_0[30:25]=6'h0e
+      TXOEN_AUTOSET_EN                             uvm_reg_field                                              ...    RW SHU_TX_SET0_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+            P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+            P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+            P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+            P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
+            P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+            P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+            P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_STBCAL1_0                             ral_reg_DDRPHY_blk_MISC_SHU_STBCAL1_0                      -     @12514
+      DLLFRZRFCOPT                                 uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[1:0]=2'h0
+      DLLFRZWROPT                                  uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[5:4]=2'h0
+      r_rstbcnt_latch_opt                          uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[10:8]=3'h0
+      STB_UPDMASK_EN                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[11:11]=1'h1 (Mirror: 1'h0)
+      STB_UPDMASKCYC                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[15:12]=4'h9 (Mirror: 4'h0)
+      DQSINCTL_PRE_SEL                             uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[16:16]=1'h1 (Mirror: 1'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1, P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) |
+            P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) |
+            P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) |
+            P_Fld(0x1, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_STBCAL_0                              ral_reg_DDRPHY_blk_MISC_SHU_STBCAL_0                       -     @12499
+      DMSTBLAT                                     uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[3:0]=4'h2 (Mirror: 4'h0)
+      PICGLAT                                      uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[6:4]=3'h1 (Mirror: 3'h0)
+      DQSG_MODE                                    uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[8:8]=1'h1 (Mirror: 1'h0)
+      DQSIEN_PICG_MODE                             uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[9:9]=1'h1 (Mirror: 1'h0)
+      DQSIEN_DQSSTB_MODE                           uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[13:12]=2'h1
+      DQSIEN_BURST_MODE                            uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[14:14]=1'h1
+      DQSIEN_SELPH_FRUN                            uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[15:15]=1'h0
+      STBCALEN                                     uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[16:16]=1'h1 (Mirror: 1'h0)
+      STB_SELPHCALEN                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[17:17]=1'h1 (Mirror: 1'h0)
+      DQSIEN_4TO1_EN                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[20:20]=1'h0
+      DQSIEN_8TO1_EN                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[21:21]=1'h0
+      DQSIEN_16TO1_EN                              uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[22:22]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL, P_Fld(0x2, MISC_SHU_STBCAL_DMSTBLAT) |
+            P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) |
+            P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) |
+            P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) |
+            P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) |
+            P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) |
+            P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RODTENSTB_0                           ral_reg_DDRPHY_blk_MISC_SHU_RODTENSTB_0                    -     @12562
+      RODTENSTB_TRACK_EN                           uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[0:0]=1'h1 (Mirror: 1'h0)
+      RODTEN_P1_ENABLE                             uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[1:1]=1'h0
+      RODTENSTB_4BYTE_EN                           uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[2:2]=1'h0
+      RODTENSTB_TRACK_UDFLWCTRL                    uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[3:3]=1'h1 (Mirror: 1'h0)
+      RODTENSTB_SELPH_MODE                         uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[4:4]=1'h1
+      RODTENSTB_SELPH_BY_BITTIME                   uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[5:5]=1'h0
+      RODTENSTB__UI_OFFSET                         uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[11:8]=4'h4 (Mirror: 4'h0)
+      RODTENSTB_MCK_OFFSET                         uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[15:12]=4'h0
+      RODTENSTB_EXT                                uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[31:16]=16'h0008 (Mirror: 16'h0000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) |
+            P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) |
+            P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) |
+            P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x4, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) |
+            P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_RX_SELPH_MODE_0                       ral_reg_DDRPHY_blk_MISC_SHU_RX_SELPH_MODE_0                -     @12751
+      DQSIEN_SELPH_SERMODE                         uvm_reg_field                                              ...    RW MISC_SHU_RX_SELPH_MODE_0[1:0]=2'h2 (Mirror: 2'h0)
+      RODT_SELPH_SERMODE                           uvm_reg_field                                              ...    RW MISC_SHU_RX_SELPH_MODE_0[5:4]=2'h1 (Mirror: 2'h0)
+      RANK_SELPH_SERMODE                           uvm_reg_field                                              ...    RW MISC_SHU_RX_SELPH_MODE_0[7:6]=2'h1 (Mirror: 2'h0)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE, P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) |
+            P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Enter
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Enter
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_HWSET_MR13_0                               ral_reg_DRAMC_blk_SHU_HWSET_MR13_0                         -     @5127
+      HWSET_MR13_MRSMA                             uvm_reg_field                                              ...    RW SHU_HWSET_MR13_0[12:0]=13'h000d
+      HWSET_MR13_OP                                uvm_reg_field                                              ...    RW SHU_HWSET_MR13_0[23:16]=8'h08 (Mirror: 8'hc8)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR13, P_Fld(0x000d, SHU_HWSET_MR13_HWSET_MR13_MRSMA) |
+            P_Fld(0x08, SHU_HWSET_MR13_HWSET_MR13_OP));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_HWSET_VRCG_0                               ral_reg_DRAMC_blk_SHU_HWSET_VRCG_0                         -     @5132
+      HWSET_VRCG_MRSMA                             uvm_reg_field                                              ...    RW SHU_HWSET_VRCG_0[12:0]=13'h000d
+      HWSET_VRCG_OP                                uvm_reg_field                                              ...    RW SHU_HWSET_VRCG_0[23:16]=8'h00 (Mirror: 8'hc0)
+      VRCGDIS_PRDCNT                               uvm_reg_field                                              ...    RW SHU_HWSET_VRCG_0[31:24]=8'h00
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_VRCG, P_Fld(0x000d, SHU_HWSET_VRCG_HWSET_VRCG_MRSMA) |
+            P_Fld(0x00, SHU_HWSET_VRCG_HWSET_VRCG_OP) | P_Fld(0x00, SHU_HWSET_VRCG_VRCGDIS_PRDCNT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_HWSET_MR2_0                                ral_reg_DRAMC_blk_SHU_HWSET_MR2_0                          -     @5122
+      HWSET_MR2_MRSMA                              uvm_reg_field                                              ...    RW SHU_HWSET_MR2_0[12:0]=13'h0002
+      HWSET_MR2_OP                                 uvm_reg_field                                              ...    RW SHU_HWSET_MR2_0[23:16]=8'h2d (Mirror: 8'h12)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR2, P_Fld(0x0002, SHU_HWSET_MR2_HWSET_MR2_MRSMA) |
+            P_Fld(0x2d, SHU_HWSET_MR2_HWSET_MR2_OP));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Enter
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_FREQ_RATIO_SET0_0                          ral_reg_DRAMC_blk_SHU_FREQ_RATIO_SET0_0                    -     @5384
+      tDQSCK_JUMP_RATIO3                           uvm_reg_field                                              ...    RW SHU_FREQ_RATIO_SET0_0[7:0]=8'h20 (Mirror: 8'h00)
+      tDQSCK_JUMP_RATIO2                           uvm_reg_field                                              ...    RW SHU_FREQ_RATIO_SET0_0[15:8]=8'h55 (Mirror: 8'h00)
+      tDQSCK_JUMP_RATIO1                           uvm_reg_field                                              ...    RW SHU_FREQ_RATIO_SET0_0[23:16]=8'h0c (Mirror: 8'h00)
+      tDQSCK_JUMP_RATIO0                           uvm_reg_field                                              ...    RW SHU_FREQ_RATIO_SET0_0[31:24]=8'h20 (Mirror: 8'h00)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) |
+            P_Fld(0x55, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x0c, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) |
+            P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Exit
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Enter
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    MISC_SHU_DVFSDLL_0                             ral_reg_DDRPHY_blk_MISC_SHU_DVFSDLL_0                      -     @12523
+      r_bypass_1st_dll                             uvm_reg_field                                              ...    RW MISC_SHU_DVFSDLL_0[0:0]=1'h0
+      r_bypass_2nd_dll                             uvm_reg_field                                              ...    RW MISC_SHU_DVFSDLL_0[1:1]=1'h0
+      r_dll_idle                                   uvm_reg_field                                              ...    RW MISC_SHU_DVFSDLL_0[10:4]=7'h5a (Mirror: 7'h46)
+      r_2nd_dll_idle                               uvm_reg_field                                              ...    RW MISC_SHU_DVFSDLL_0[22:16]=7'h5a
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) |
+            P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) |
+            P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE));
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Exit
+        mcDELAY_US(1);
+
+        mcDELAY_US(1);
+
+    /*TINFO=---===BROADCAST OFF!===---*/
+         DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Enter
+        mcDELAY_US(1);
+
+        mcDELAY_US(1);
+
+    /*TINFO=---===BROADCAST ON!===---*/
+         DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    //    ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Exit
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_DQSOSCR_0                                  ral_reg_DRAMC_blk_SHU_DQSOSCR_0                            -     @5338
+      DQSOSCRCNT                                   uvm_reg_field                                              ...    RW SHU_DQSOSCR_0[7:0]=8'h10 (Mirror: 8'h00)
+      DQSOSC_ADV_SEL                               uvm_reg_field                                              ...    RW SHU_DQSOSCR_0[9:8]=2'h0
+      DQSOSC_DRS_ADV_SEL                           uvm_reg_field                                              ...    RW SHU_DQSOSCR_0[11:10]=2'h0
+      DQSOSC_DELTA                                 uvm_reg_field                                              ...    RW SHU_DQSOSCR_0[31:16]=16'hffff
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR, P_Fld(0x10, SHU_DQSOSCR_DQSOSCRCNT) |
+            P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) |
+            P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_DQSOSC_SET0_0                              ral_reg_DRAMC_blk_SHU_DQSOSC_SET0_0                        -     @5332
+      DQSOSCENDIS                                  uvm_reg_field                                              ...    RW SHU_DQSOSC_SET0_0[0:0]=1'h1
+      DQSOSC_PRDCNT                                uvm_reg_field                                              ...    RW SHU_DQSOSC_SET0_0[13:4]=10'h011 (Mirror: 10'h00f)
+      DQSOSCENCNT                                  uvm_reg_field                                              ...    RW SHU_DQSOSC_SET0_0[31:16]=16'h0002
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0, P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) |
+            P_Fld(0x011, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQSOSC_0_0                               ral_reg_DRAMC_blk_SHURK_DQSOSC_0_0                         -     @4906
+      DQSOSC_BASE_RK0                              uvm_reg_field                                              ...    RW SHURK_DQSOSC_0_0[15:0]=16'h0317 (Mirror: 16'h0000)
+      DQSOSC_BASE_RK0_B1                           uvm_reg_field                                              ...    RW SHURK_DQSOSC_0_0[31:16]=16'h0317 (Mirror: 16'h0000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC, P_Fld(0x0317, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
+            P_Fld(0x0317, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQSOSC_0_1                               ral_reg_DRAMC_blk_SHURK_DQSOSC_0_1                         -     @4911
+      DQSOSC_BASE_RK0                              uvm_reg_field                                              ...    RW SHURK_DQSOSC_0_1[15:0]=16'h01c4 (Mirror: 16'h0000)
+      DQSOSC_BASE_RK0_B1                           uvm_reg_field                                              ...    RW SHURK_DQSOSC_0_1[31:16]=16'h01c4 (Mirror: 16'h0000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x01c4, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
+            P_Fld(0x01c4, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQSOSC_THRD_0_0                          ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_0                    -     @4916
+      DQSOSCTHRD_INC                               uvm_reg_field                                              ...    RW SHURK_DQSOSC_THRD_0_0[11:0]=12'h017 (Mirror: 12'h001)
+      DQSOSCTHRD_DEC                               uvm_reg_field                                              ...    RW SHURK_DQSOSC_THRD_0_0[27:16]=12'h00f (Mirror: 12'h001)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD, P_Fld(0x017, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
+            P_Fld(0x00f, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHURK_DQSOSC_THRD_0_1                          ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_1                    -     @4921
+      DQSOSCTHRD_INC                               uvm_reg_field                                              ...    RW SHURK_DQSOSC_THRD_0_1[11:0]=12'h007 (Mirror: 12'h001)
+      DQSOSCTHRD_DEC                               uvm_reg_field                                              ...    RW SHURK_DQSOSC_THRD_0_1[27:16]=12'h005 (Mirror: 12'h001)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x007, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
+            P_Fld(0x005, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_TX_SET0_0                                  ral_reg_DRAMC_blk_SHU_TX_SET0_0                            -     @5306
+      DQOE_CNT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[3:0]=4'h0
+      DQOE_OPT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[4:4]=1'h0
+      TXUPD_SEL                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[7:6]=2'h0
+      TXUPD_W2R_SEL                                uvm_reg_field                                              ...    RW SHU_TX_SET0_0[10:8]=3'h2
+      WECC_EN                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[11:11]=1'h0
+      DBIWR                                        uvm_reg_field                                              ...    RW SHU_TX_SET0_0[12:12]=1'h0
+      WDATRGO                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[13:13]=1'h0
+      TWPSTEXT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[14:14]=1'h0
+      WPST1P5T                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[15:15]=1'h1
+      TXOEN_AUTOSET_OFFSET                         uvm_reg_field                                              ...    RW SHU_TX_SET0_0[19:16]=4'h3
+      TWCKPST                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[21:20]=2'h1
+      OE_EXT2UI                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[24:22]=3'h1
+      DQS2DQ_FILT_PITHRD                           uvm_reg_field                                              ...    RW SHU_TX_SET0_0[30:25]=6'h0d (Mirror: 6'h0e)
+      TXOEN_AUTOSET_EN                             uvm_reg_field                                              ...    RW SHU_TX_SET0_0[31:31]=1'h0
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+            P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+            P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+            P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+            P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
+            P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+            P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0d, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+            P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_ZQ_SET0_0                                  ral_reg_DRAMC_blk_SHU_ZQ_SET0_0                            -     @5351
+      ZQCSCNT                                      uvm_reg_field                                              ...    RW SHU_ZQ_SET0_0[15:0]=16'h0005 (Mirror: 16'h0000)
+      TZQLAT                                       uvm_reg_field                                              ...    RW SHU_ZQ_SET0_0[31:27]=5'h1b
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) |
+            P_Fld(0x1b, SHU_ZQ_SET0_TZQLAT));
+    /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    Name                                           Type                                                       Size  Value
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    SHU_HMR4_DVFS_CTRL0_0                          ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0                    -     @5036
+      FSPCHG_PRDCNT                                uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h64
+      REFRCNT                                      uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h005 (Mirror: 12'h000)
+    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x64, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+            P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+    //    Exit body
+    }
+
+void CInit_golden_mini_freq_related_vseq_LP5_3200_SHU1(DRAMC_CTX_T *p)
+{
+    //    Enter body
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, IMP golden setting Enter:
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x09, SHU_MISC_DRVING1_DQDRVN2) |
+            P_Fld(0x07, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN1) |
+            P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN2) |
+            P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) |
+            P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMPCAL_HW));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x09, SHU_MISC_DRVING2_CMDDRVN1) |
+            P_Fld(0x07, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x09, SHU_MISC_DRVING2_CMDDRVN2) |
+            P_Fld(0x07, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x09, SHU_MISC_DRVING2_DQDRVN1) |
+            P_Fld(0x07, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x1, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) |
+            P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) |
+            P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) |
+            P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) |
+            P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) |
+            P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) |
+            P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x07, SHU_MISC_DRVING6_IMP_TXDLY_CMD) |
+            P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) |
+            P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) |
+            P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) |
+            P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT));
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, IMP golden setting Exit:
+        mcDELAY_US(1);
+
+        mcDELAY_US(1);
+
+         DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA) |
+            P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA) | P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA) |
+            P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CA_CA) |
+            P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CLK_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA) |
+            P_Fld(0x1, SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0) |
+            P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_MCTL_B0) | P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B0) |
+            P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1) |
+            P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_MCTL_B1) | P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B1) |
+            P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA) |
+            P_Fld(0x09, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA) |
+            P_Fld(0x3, SHU_CA_CMD1_RG_ARPI_MIDPI_CAP_SEL_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_VTH_SEL_CA) |
+            P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_8PHASE_XLATCH_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0) |
+            P_Fld(0x1f, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0) |
+            P_Fld(0x3, SHU_B0_DQ1_RG_ARPI_MIDPI_CAP_SEL_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_VTH_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1) | P_Fld(0x1, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1) |
+            P_Fld(0x1b, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1) |
+            P_Fld(0x3, SHU_B1_DQ1_RG_ARPI_MIDPI_CAP_SEL_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_VTH_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD14+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x3, SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA) |
+            P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_AUX_SER_MODE_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_PRE_DATA_SEL_CA) |
+            P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_SWAP_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA) |
+            P_Fld(0x00, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA) |
+            P_Fld(0x1, SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_PRE_DATA_SEL_CA) |
+            P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_SWAP_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_CG_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_SEL_CA) |
+            P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCS_MCKIO_SEL_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_DATA_TIE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_DATA_TIE_EN_CA));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ10+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ14+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B0) |
+            P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B0) |
+            P_Fld(0x1, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0) | P_Fld(0x59, SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ10+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ14+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1) |
+            P_Fld(0x3, SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B1) |
+            P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B1) |
+            P_Fld(0x1, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1) | P_Fld(0x7d, SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_CA) |
+            P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_EN_CA) |
+            P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_CA) |
+            P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GAIN_BOOST_CA) | P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_GAIN_CA) |
+            P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_DIV_EN_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA) |
+            P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B0) |
+            P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_EN_B0) |
+            P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B0) |
+            P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GAIN_BOOST_B0) | P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_GAIN_B0) |
+            P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_DIV_EN_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0) |
+            P_Fld(0x1, SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B1) |
+            P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_EN_B1) |
+            P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B1) |
+            P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GAIN_BOOST_B1) | P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_GAIN_B1) |
+            P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_DIV_EN_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1) |
+            P_Fld(0x1, SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x947a, SHU_PLL0_RG_RPHYPLL_TOP_REV) |
+            P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_SER_MODE) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_PREDIV_EN) |
+            P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_EN) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_TSHIFT) |
+            P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_DIV) | P_Fld(0x00, SHU_PLL0_RG_RPLLGP_DLINE_MON_DLY) |
+            P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_EN));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_PLL1_RG_RPHYPLLGP_CK_SEL) |
+            P_Fld(0x0, SHU_PLL1_RG_RPLLGP_PLLCK_VSEL) | P_Fld(0x1, SHU_PLL1_R_SHU_AUTO_PLL_MUX) |
+            P_Fld(0x0, SHU_PLL1_RG_RPHYPLL_DDR400_EN));
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_PLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x1, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU);
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00fe, SHU_PHYPLL0_RG_RPHYPLL_RESERVED) |
+            P_Fld(0x2, SHU_PHYPLL0_RG_RPHYPLL_FS) | P_Fld(0x7, SHU_PHYPLL0_RG_RPHYPLL_BW) |
+            P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_ICHP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_IBIAS) |
+            P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BLP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BR) |
+            P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BP));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN) |
+            P_Fld(0x1, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_PHYPLL2_RG_RPHYPLL_POSDIV) |
+            P_Fld(0x1, SHU_PHYPLL2_RG_RPHYPLL_PREDIV));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL) |
+            P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_GLITCH_FREE_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_LVR_REFSEL) |
+            P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_DIV3_EN) | P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_FS_EN) |
+            P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_FBKSEL) | P_Fld(0x2, SHU_PHYPLL3_RG_RPHYPLL_RST_DLY) |
+            P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONREF_EN) |
+            P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONVC_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00fe, SHU_CLRPLL0_RG_RCLRPLL_RESERVED) |
+            P_Fld(0x2, SHU_CLRPLL0_RG_RCLRPLL_FS) | P_Fld(0x7, SHU_CLRPLL0_RG_RCLRPLL_BW) |
+            P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_ICHP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_IBIAS) |
+            P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BLP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BR) |
+            P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BP));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN) |
+            P_Fld(0x1, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CLRPLL2_RG_RCLRPLL_POSDIV) |
+            P_Fld(0x1, SHU_CLRPLL2_RG_RCLRPLL_PREDIV));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_CA_CMD5_RG_RX_ARCMD_VREF_SEL) |
+            P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS) | P_Fld(0x00, SHU_CA_CMD5_RG_ARPI_FB_CA) |
+            P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_RB_DLY) |
+            P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_FIFO_DQSI_DLY));
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD9+(1*SHU_GRP_DDRPHY_OFFSET), 0x3338ac63, SHU_CA_CMD9_RG_ARPI_RESERVE_CA);
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_MIDPI_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_MIDPI_CTRL_MIDPI_ENABLE) |
+            P_Fld(0x1, MISC_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE));
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT) |
+            P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT) | P_Fld(0x0, MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT) |
+            P_Fld(0x0, MISC_SHU_RDAT1_RDATDIV2) | P_Fld(0x1, MISC_SHU_RDAT1_RDATDIV4));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0) | P_Fld(0x2, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1));
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9+(1*SHU_GRP_DDRPHY_OFFSET), 0x7f8d04df, SHU_B0_DQ9_RG_ARPI_RESERVE_B0);
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9+(1*SHU_GRP_DDRPHY_OFFSET), 0xa40fc3b2, SHU_B1_DQ9_RG_ARPI_RESERVE_B1);
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD7_R_DMRANKRXDVS_CA) |
+            P_Fld(0x0, SHU_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA) | P_Fld(0x0, SHU_CA_CMD7_R_DMRODTEN_CA) |
+            P_Fld(0x0, SHU_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA) | P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW) |
+            P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW) | P_Fld(0x0, SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK) |
+            P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_LAT) |
+            P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_LAT));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_AD_ARFB_CK_EN_CA) |
+            P_Fld(0x3, SHU_CA_DLL1_RG_ARDLL_DIV_MODE_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA) |
+            P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_TRACKING_CA_EN_CA) |
+            P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_CA) | P_Fld(0x3, SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA) |
+            P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PS_EN_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA) |
+            P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDIV_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) |
+            P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA) |
+            P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_DIV_MCTL_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PGAIN_CA) |
+            P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA));
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_DLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x3f6e1851, SHU_CA_DLL2_RG_ARCMD_REV);
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B0) |
+            P_Fld(0x3, SHU_B0_DLL1_RG_ARDLL_DIV_MODE_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0) |
+            P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0) |
+            P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0) |
+            P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PS_EN_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0) |
+            P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDIV_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0) |
+            P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0) |
+            P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_DIV_MCTL_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PGAIN_B0) |
+            P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B1) |
+            P_Fld(0x3, SHU_B1_DLL1_RG_ARDLL_DIV_MODE_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1) |
+            P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1) |
+            P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B1) | P_Fld(0x3, SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1) |
+            P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PS_EN_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1) |
+            P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDIV_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1) |
+            P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1) |
+            P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_DIV_MCTL_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PGAIN_B1) |
+            P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1));
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x8461c1a1, SHU_B0_DLL2_RG_ARDQ_REV_B0);
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0xad90b805, SHU_B1_DLL2_RG_ARDQ_REV_B1);
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_FRATE_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_CDR_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_DLY_CA) |
+            P_Fld(0x2, SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) |
+            P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) |
+            P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA) |
+            P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA) |
+            P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA) |
+            P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA) |
+            P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU) |
+            P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0) |
+            P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0) |
+            P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0) |
+            P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU) |
+            P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1) |
+            P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1) |
+            P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1) |
+            P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU) |
+            P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1));
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Exit
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD6+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA) |
+            P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA) | P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA) |
+            P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CA_CA) |
+            P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CLK_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA) |
+            P_Fld(0x1, SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ6+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0) |
+            P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_MCTL_B0) | P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B0) |
+            P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ6+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1) |
+            P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_MCTL_B1) | P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B1) |
+            P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA) |
+            P_Fld(0x10, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA) |
+            P_Fld(0x3, SHU_CA_CMD1_RG_ARPI_MIDPI_CAP_SEL_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_VTH_SEL_CA) |
+            P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_8PHASE_XLATCH_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0) |
+            P_Fld(0x08, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0) |
+            P_Fld(0x3, SHU_B0_DQ1_RG_ARPI_MIDPI_CAP_SEL_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_VTH_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1) |
+            P_Fld(0x02, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1) |
+            P_Fld(0x3, SHU_B1_DQ1_RG_ARPI_MIDPI_CAP_SEL_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_VTH_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD14+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x2, SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA) |
+            P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_AUX_SER_MODE_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_PRE_DATA_SEL_CA) |
+            P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_SWAP_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA) |
+            P_Fld(0x00, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD13+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA) |
+            P_Fld(0x1, SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_PRE_DATA_SEL_CA) |
+            P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_SWAP_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_CG_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_SEL_CA) |
+            P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCS_MCKIO_SEL_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_DATA_TIE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_DATA_TIE_EN_CA));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ10+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ14+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B0) |
+            P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B0) |
+            P_Fld(0x1, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0) | P_Fld(0x76, SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ10+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ14+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1) |
+            P_Fld(0x3, SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B1) |
+            P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B1) |
+            P_Fld(0x1, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1) | P_Fld(0x4c, SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_CA) |
+            P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_EN_CA) |
+            P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_CA) |
+            P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GAIN_BOOST_CA) | P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_GAIN_CA) |
+            P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_DIV_EN_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA) |
+            P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B0) |
+            P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_EN_B0) |
+            P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B0) |
+            P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GAIN_BOOST_B0) | P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_GAIN_B0) |
+            P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_DIV_EN_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0) |
+            P_Fld(0x1, SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B1) |
+            P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_EN_B1) |
+            P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B1) |
+            P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GAIN_BOOST_B1) | P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_GAIN_B1) |
+            P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_DIV_EN_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1) |
+            P_Fld(0x1, SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1d17, SHU_PLL0_RG_RPHYPLL_TOP_REV) |
+            P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_SER_MODE) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_PREDIV_EN) |
+            P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_EN) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_TSHIFT) |
+            P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_DIV) | P_Fld(0x00, SHU_PLL0_RG_RPLLGP_DLINE_MON_DLY) |
+            P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_EN));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_PLL1_RG_RPHYPLLGP_CK_SEL) |
+            P_Fld(0x0, SHU_PLL1_RG_RPLLGP_PLLCK_VSEL) | P_Fld(0x1, SHU_PLL1_R_SHU_AUTO_PLL_MUX) |
+            P_Fld(0x0, SHU_PLL1_RG_RPHYPLL_DDR400_EN));
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_PLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x1, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU);
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00fe, SHU_PHYPLL0_RG_RPHYPLL_RESERVED) |
+            P_Fld(0x2, SHU_PHYPLL0_RG_RPHYPLL_FS) | P_Fld(0x7, SHU_PHYPLL0_RG_RPHYPLL_BW) |
+            P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_ICHP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_IBIAS) |
+            P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BLP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BR) |
+            P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BP));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN) |
+            P_Fld(0x1, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_PHYPLL2_RG_RPHYPLL_POSDIV) |
+            P_Fld(0x1, SHU_PHYPLL2_RG_RPHYPLL_PREDIV));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL3+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL) |
+            P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_GLITCH_FREE_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_LVR_REFSEL) |
+            P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_DIV3_EN) | P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_FS_EN) |
+            P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_FBKSEL) | P_Fld(0x2, SHU_PHYPLL3_RG_RPHYPLL_RST_DLY) |
+            P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONREF_EN) |
+            P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONVC_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00fe, SHU_CLRPLL0_RG_RCLRPLL_RESERVED) |
+            P_Fld(0x2, SHU_CLRPLL0_RG_RCLRPLL_FS) | P_Fld(0x7, SHU_CLRPLL0_RG_RCLRPLL_BW) |
+            P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_ICHP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_IBIAS) |
+            P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BLP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BR) |
+            P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BP));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN) |
+            P_Fld(0x1, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CLRPLL2_RG_RCLRPLL_POSDIV) |
+            P_Fld(0x1, SHU_CLRPLL2_RG_RCLRPLL_PREDIV));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD5+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_CA_CMD5_RG_RX_ARCMD_VREF_SEL) |
+            P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS) | P_Fld(0x00, SHU_CA_CMD5_RG_ARPI_FB_CA) |
+            P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_RB_DLY) |
+            P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_FIFO_DQSI_DLY));
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD9+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0xd084ae4a, SHU_CA_CMD9_RG_ARPI_RESERVE_CA);
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_MIDPI_CTRL+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, MISC_SHU_MIDPI_CTRL_MIDPI_ENABLE) |
+            P_Fld(0x1, MISC_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE));
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT) |
+            P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT) | P_Fld(0x0, MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT) |
+            P_Fld(0x0, MISC_SHU_RDAT1_RDATDIV2) | P_Fld(0x1, MISC_SHU_RDAT1_RDATDIV4));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0) | P_Fld(0x3, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1) | P_Fld(0x2, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1));
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x27759cf9, SHU_B0_DQ9_RG_ARPI_RESERVE_B0);
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x5a41c75f, SHU_B1_DQ9_RG_ARPI_RESERVE_B1);
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD7+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_CMD7_R_DMRANKRXDVS_CA) |
+            P_Fld(0x0, SHU_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA) | P_Fld(0x0, SHU_CA_CMD7_R_DMRODTEN_CA) |
+            P_Fld(0x0, SHU_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA) | P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW) |
+            P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW) | P_Fld(0x0, SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK) |
+            P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_LAT) |
+            P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_LAT));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_AD_ARFB_CK_EN_CA) |
+            P_Fld(0x3, SHU_CA_DLL1_RG_ARDLL_DIV_MODE_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA) |
+            P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_TRACKING_CA_EN_CA) |
+            P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_CA) | P_Fld(0x2, SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA) |
+            P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PS_EN_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA) |
+            P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDIV_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) |
+            P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA) |
+            P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_DIV_MCTL_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PGAIN_CA) |
+            P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA));
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_DLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x249e9d9e, SHU_CA_DLL2_RG_ARCMD_REV);
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B0) |
+            P_Fld(0x3, SHU_B0_DLL1_RG_ARDLL_DIV_MODE_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0) |
+            P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0) |
+            P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B0) | P_Fld(0x2, SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0) |
+            P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PS_EN_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0) |
+            P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDIV_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0) |
+            P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0) |
+            P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_DIV_MCTL_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PGAIN_B0) |
+            P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B1) |
+            P_Fld(0x3, SHU_B1_DLL1_RG_ARDLL_DIV_MODE_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1) |
+            P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1) |
+            P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B1) | P_Fld(0x3, SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1) |
+            P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PS_EN_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1) |
+            P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDIV_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1) |
+            P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1) |
+            P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_DIV_MCTL_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PGAIN_B1) |
+            P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1));
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x23566f78, SHU_B0_DLL2_RG_ARDQ_REV_B0);
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0xaec2cdcb, SHU_B1_DLL2_RG_ARDQ_REV_B1);
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD11+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_FRATE_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_CDR_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_DLY_CA) |
+            P_Fld(0x2, SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) |
+            P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) |
+            P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA) |
+            P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA) |
+            P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA) |
+            P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA) |
+            P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU) |
+            P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) |
+            P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0) |
+            P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0) |
+            P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0) |
+            P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU) |
+            P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1) |
+            P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1) |
+            P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1) |
+            P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU) |
+            P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1));
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Exit
+        mcDELAY_US(1);
+
+        mcDELAY_US(1);
+
+         DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN) |
+            P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN) | P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN) |
+            P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN) | P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA) |
+            P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0) |
+            P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0) |
+            P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0) |
+            P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1) |
+            P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1) |
+            P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1) |
+            P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1));
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, TX_MODE_SET related setting Enter
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0) | P_Fld(0x2, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1));
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, RX data path setting Enter:
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0f, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) |
+            P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) |
+            P_Fld(0xff0, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x010, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS));
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0f, MISC_SHU_RDAT_DATLAT) |
+            P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) |
+            P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) |
+            P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) |
+            P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x3, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) |
+            P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) |
+            P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL) |
+            P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_PHY));
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
+            P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*SHU_GRP_DDRPHY_OFFSET), 0x6, MISC_SHU_RK_DQSCTL_DQSINCTL);
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), 0x6, MISC_SHU_RK_DQSCTL_DQSINCTL);
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x4, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+            P_Fld(0x6, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), 0x1e, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x5, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+            P_Fld(0x7, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), 0x17, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x4, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+            P_Fld(0x6, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), 0x1e, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x5, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+            P_Fld(0x7, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), 0x17, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x3, MISC_SHU_ODTCTRL_RODT_LAT) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) |
+            P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) |
+            P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+            P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+            P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+            P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+            P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+            P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+            P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) |
+            P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) |
+            P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
+            P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) |
+            P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) |
+            P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) |
+            P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x7, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) |
+            P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) |
+            P_Fld(0x2, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS));
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1e, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+            P_Fld(0x04, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1e, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+            P_Fld(0x04, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+            P_Fld(0x05, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+            P_Fld(0x05, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1e, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+            P_Fld(0x04, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x06, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1e, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+            P_Fld(0x04, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x06, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+            P_Fld(0x05, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x07, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+            P_Fld(0x05, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x07, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, RX data path setting Exit:
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, TX data path setting Enter:
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
+            P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
+            P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x1d, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+            P_Fld(0x1d, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+            P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
+            P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
+            P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x09, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+            P_Fld(0x09, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
+            P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x09, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+            P_Fld(0x09, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
+            P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+            P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x6, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+            P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) |
+            P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0xa, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) |
+            P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) |
+            P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+            P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+            P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) |
+            P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) |
+            P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) |
+            P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) |
+            P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+            P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+            P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+            P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+            P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_SELPH_DQ2_DLY_DQ0) |
+            P_Fld(0x0, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_SELPH_DQ3_DLY_DQM0) |
+            P_Fld(0x0, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+            P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+            P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+            P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+            P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+            P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+            P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+            P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+            P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x01d, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+            P_Fld(0x01f, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x01d, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+            P_Fld(0x01f, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x01d, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+            P_Fld(0x01f, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x009, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+            P_Fld(0x009, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x009, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+            P_Fld(0x009, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x009, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+            P_Fld(0x009, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQ_B1) |
+            P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQM_B1) |
+            P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQM_B0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x09, SHURK_PI_RK0_ARPI_DQ_B1) |
+            P_Fld(0x09, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x09, SHURK_PI_RK0_ARPI_DQM_B1) |
+            P_Fld(0x09, SHURK_PI_RK0_ARPI_DQM_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+            P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+            P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+            P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+            P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+            P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+            P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+            P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+            P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+            P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+            P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+            P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+            P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+            P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+            P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+            P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) |
+            P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT));
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9+(1*SHU_GRP_DDRPHY_OFFSET), 0x7f8904df, SHU_B0_DQ9_RG_ARPI_RESERVE_B0);
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9+(1*SHU_GRP_DDRPHY_OFFSET), 0xa409c3b2, SHU_B1_DQ9_RG_ARPI_RESERVE_B1);
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, TX data path setting Exit:
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, TX WCK auto-generation set Enter
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) |
+            P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) |
+            P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
+            P_Fld(0x0, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
+            P_Fld(0x0, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) |
+            P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) |
+            P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_UI+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_WCK_WR_UI_WCK_WR_B0_UI) |
+            P_Fld(0x0, SHURK_WCK_WR_UI_WCK_WR_B1_UI));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_UI+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_WCK_WR_UI_WCK_WR_B0_UI) |
+            P_Fld(0x0, SHURK_WCK_WR_UI_WCK_WR_B1_UI));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_WCK_RD_UI_WCK_RD_B0_UI) |
+            P_Fld(0x0, SHURK_WCK_RD_UI_WCK_RD_B1_UI));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_WCK_RD_UI_WCK_RD_B0_UI) |
+            P_Fld(0x0, SHURK_WCK_RD_UI_WCK_RD_B1_UI));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_WCK_FS_UI_WCK_FS_B0_UI) |
+            P_Fld(0x0, SHURK_WCK_FS_UI_WCK_FS_B1_UI));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_WCK_FS_UI_WCK_FS_B0_UI) |
+            P_Fld(0x0, SHURK_WCK_FS_UI_WCK_FS_B1_UI));
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, TX WCK auto-generation set Exit
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, TX CA golden setting Enter:
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) |
+            P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) |
+            P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) |
+            P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) |
+            P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) |
+            P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) |
+            P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) |
+            P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) |
+            P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) |
+            P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) |
+            P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) |
+            P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) |
+            P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) |
+            P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) |
+            P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) |
+            P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) |
+            P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) |
+            P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) |
+            P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1));
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, TX CA golden setting Exit
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, AC timing Enter:
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) |
+            P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x26, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+            P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_AC_TIME_05T_TRC_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TXP_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRCD_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRRI_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_BGTWTR_M05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTR_M05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRD_05T) |
+            P_Fld(0x1, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRR2MRW_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) |
+            P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0d, SHU_ACTIM_XRT_XRTR2R) |
+            P_Fld(0x03, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x4, SHU_ACTIM_XRT_XRTW2R) |
+            P_Fld(0x04, SHU_ACTIM_XRT_XRTW2W));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHU_ACTIM0_TWTR) |
+            P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x06, SHU_ACTIM0_TWR) |
+            P_Fld(0x0, SHU_ACTIM0_TRRD) | P_Fld(0x3, SHU_ACTIM0_TRCD) |
+            P_Fld(0xe, SHU_ACTIM0_TWTR_L));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_ACTIM1_TRPAB) |
+            P_Fld(0x3, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x1, SHU_ACTIM1_TRP) |
+            P_Fld(0x00, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_ACTIM2_TXP) |
+            P_Fld(0x05, SHU_ACTIM2_TMRRI) | P_Fld(0x1, SHU_ACTIM2_TRTP) |
+            P_Fld(0x04, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x09, SHU_ACTIM3_TRFCPB) |
+            P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) |
+            P_Fld(0x1e, SHU_ACTIM3_TRFC));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x02b, SHU_ACTIM4_TXREFCNT) |
+            P_Fld(0x38, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x05, SHU_ACTIM4_TMRR2W) |
+            P_Fld(0x0c, SHU_ACTIM4_TZQCS));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x08, SHU_ACTIM5_TR2PD) |
+            P_Fld(0x08, SHU_ACTIM5_TWTPD) | P_Fld(0x0e, SHU_ACTIM5_TPBR2PBR) |
+            P_Fld(0x0, SHU_ACTIM5_TPBR2ACT));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x05, SHU_ACTIM6_TZQLAT2) |
+            P_Fld(0x2, SHU_ACTIM6_TMRD) | P_Fld(0x0, SHU_ACTIM6_TMRW) |
+            P_Fld(0x22, SHU_ACTIM6_TW2MRW) | P_Fld(0x13, SHU_ACTIM6_TR2MRW));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_CKECTRL_TPDE_05T) |
+            P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) |
+            P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x3, SHU_CKECTRL_TCKEPRD) |
+            P_Fld(0x3, SHU_CKECTRL_TCKESRX));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_MISC+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) |
+            P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_LP5_CMD+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_LP5_CMD_LP5_CMD1TO2EN) |
+            P_Fld(0xb, SHU_LP5_CMD_TCSH));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM7+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0xb, SHU_ACTIM7_TCSH_CSCAL) |
+            P_Fld(0xb, SHU_ACTIM7_TCACSH));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_WCKCTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2b, SHU_WCKCTRL_WCKRDOFF) |
+            P_Fld(0x0, SHU_WCKCTRL_WCKRDOFF_05T) | P_Fld(0x2b, SHU_WCKCTRL_WCKWROFF) |
+            P_Fld(0x0, SHU_WCKCTRL_WCKWROFF_05T) | P_Fld(0x0, SHU_WCKCTRL_WCKDUAL));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_TX_PIPE_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_CMD_TXPIPE_BYPASS_EN) |
+            P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CK_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_TX_PIPE_BYPASS_EN) |
+            P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_CS_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_SKIP_TXPIPE_BYPASS));
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, AC timing Exit
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, RX cross-rank improve setting Enter.
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, RX cross-rank improve setting Exit.
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, RX input delay line set
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x004a, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+            P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+            P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x004a, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+            P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+            P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) |
+            P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) |
+            P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) |
+            P_Fld(0x6, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) |
+            P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) |
+            P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) |
+            P_Fld(0x6, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+            P_Fld(0x17, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x17, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
+            P_Fld(0x17, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+            P_Fld(0x17, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x17, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+            P_Fld(0x17, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+            P_Fld(0x17, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x17, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+            P_Fld(0x17, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+            P_Fld(0x17, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x17, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+            P_Fld(0x17, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+            P_Fld(0x17, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0be, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+            P_Fld(0x0be, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+            P_Fld(0x16, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x16, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
+            P_Fld(0x16, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+            P_Fld(0x16, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x16, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+            P_Fld(0x16, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+            P_Fld(0x16, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x16, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+            P_Fld(0x16, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+            P_Fld(0x16, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x16, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+            P_Fld(0x16, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+            P_Fld(0x16, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0bd, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+            P_Fld(0x0bd, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+            P_Fld(0x17, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x17, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
+            P_Fld(0x17, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+            P_Fld(0x17, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x17, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+            P_Fld(0x17, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+            P_Fld(0x17, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x17, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+            P_Fld(0x17, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+            P_Fld(0x17, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x17, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+            P_Fld(0x17, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+            P_Fld(0x17, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0be, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+            P_Fld(0x0be, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+            P_Fld(0x16, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x16, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
+            P_Fld(0x16, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+            P_Fld(0x16, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x16, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+            P_Fld(0x16, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+            P_Fld(0x16, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x16, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+            P_Fld(0x16, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+            P_Fld(0x16, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x16, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+            P_Fld(0x16, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+            P_Fld(0x16, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0bd, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+            P_Fld(0x0bd, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, RX input delay line set EXIT
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, DRAMC other fixed register Enter
+    vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_COMMON0_FREQDIV4) |
+            P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x1, SHU_COMMON0_FREQDIV8) |
+            P_Fld(0x0, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) |
+            P_Fld(0x0, SHU_COMMON0_LP5BGEN) | P_Fld(0x1, SHU_COMMON0_LP5WCKON) |
+            P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) |
+            P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) |
+            P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x1, SHU_COMMON0_LP5HEFF_MODE) |
+            P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV));
+    vIO32WriteFldAlign(DRAMC_REG_SHU_WCKCTRL_1+(1*SHU_GRP_DRAMC_OFFSET), 0x1, SHU_WCKCTRL_1_WCKSYNC_PRE_MODE);
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) |
+            P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) |
+            P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+            P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x6, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+            P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) |
+            P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x3f, SHU_CONF0_DMPGTIM) |
+            P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) |
+            P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) |
+            P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_MATYPE_MATYPE) |
+            P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN));
+    vIO32WriteFldAlign(DRAMC_REG_SHU_SCHEDULER+(1*SHU_GRP_DRAMC_OFFSET), 0x1, SHU_SCHEDULER_DUALSCHEN);
+    vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+            P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+            P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+            P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+            P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x0, SHU_TX_SET0_WPST1P5T) |
+            P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+            P_Fld(0x0, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+            P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) |
+            P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) |
+            P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) |
+            P_Fld(0x0, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL));
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_STBCAL_DMSTBLAT) |
+            P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) |
+            P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) |
+            P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) |
+            P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) |
+            P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) |
+            P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN));
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT));
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT) |
+            P_Fld(0x1, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT));
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) |
+            P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) |
+            P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) |
+            P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) |
+            P_Fld(0x2, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT));
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) |
+            P_Fld(0x0, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x0, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE));
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, DRAMC other fixed register Exit
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, DBI gen by frequency Enter
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, DBI gen by frequency Exit
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, DVFS_WLRL_setting Enter
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR13+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x000d, SHU_HWSET_MR13_HWSET_MR13_MRSMA) |
+            P_Fld(0x08, SHU_HWSET_MR13_HWSET_MR13_OP));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_VRCG+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x000d, SHU_HWSET_VRCG_HWSET_VRCG_MRSMA) |
+            P_Fld(0x00, SHU_HWSET_VRCG_HWSET_VRCG_OP) | P_Fld(0x00, SHU_HWSET_VRCG_VRCGDIS_PRDCNT));
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, DVFS_WLRL_setting Exit
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, jump_ratio_setting_txrx_SHU_8_group Enter
+    vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x00, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) |
+            P_Fld(0x00, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) |
+            P_Fld(0x55, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0));
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, jump_ratio_setting_txrx_SHU_8_group Exit
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, dvfs_config_shuffle_registers Enter
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) |
+            P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) |
+            P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE));
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, dvfs_config_shuffle_registers Exit
+        mcDELAY_US(1);
+
+        mcDELAY_US(1);
+
+         DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, sram_read_timing_option Enter
+        mcDELAY_US(1);
+
+        mcDELAY_US(1);
+
+         DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    //    ========>SHUFFLE GROUP: 1, need_fifo: 1, sram_read_timing_option Exit
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0c, SHU_DQSOSCR_DQSOSCRCNT) |
+            P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) |
+            P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) |
+            P_Fld(0x021, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0844, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
+            P_Fld(0x0844, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x04b9, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
+            P_Fld(0x04b9, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0a6, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
+            P_Fld(0x06f, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x036, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
+            P_Fld(0x024, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+            P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+            P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+            P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+            P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x0, SHU_TX_SET0_WPST1P5T) |
+            P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+            P_Fld(0x0, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x06, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+            P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_DQSOSC_SET0_DQSOSCENDIS) |
+            P_Fld(0x021, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) |
+            P_Fld(0x1b, SHU_ZQ_SET0_TZQLAT));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x26, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+            P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+    //    Exit body
+}
+
+void CInit_golden_mini_freq_related_vseq_LP5_4266(DRAMC_CTX_T *p)
+{
+//    Enter body
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Enter:
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_DRVING1_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING1_0                      -     @12634
+  DQDRVN2                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[4:0]=5'h08 (Mirror: 5'h00)
+  DQDRVP2                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[9:5]=5'h06 (Mirror: 5'h00)
+  DQSDRVN1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[14:10]=5'h08 (Mirror: 5'h00)
+  DQSDRVP1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[19:15]=5'h06 (Mirror: 5'h00)
+  DQSDRVN2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[24:20]=5'h08 (Mirror: 5'h00)
+  DQSDRVP2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[29:25]=5'h06 (Mirror: 5'h00)
+  DIS_IMP_ODTN_track                           uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[30:30]=1'h0
+  DIS_IMPCAL_HW                                uvm_reg_field                                              ...    RW SHU_MISC_DRVING1_0[31:31]=1'h0
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(0x08, SHU_MISC_DRVING1_DQDRVN2) |
+        P_Fld(0x06, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN1) |
+        P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN2) |
+        P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) |
+        P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMPCAL_HW));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_DRVING2_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING2_0                      -     @12645
+  CMDDRVN1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[4:0]=5'h08 (Mirror: 5'h00)
+  CMDDRVP1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[9:5]=5'h06 (Mirror: 5'h00)
+  CMDDRVN2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[14:10]=5'h08 (Mirror: 5'h00)
+  CMDDRVP2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[19:15]=5'h06 (Mirror: 5'h00)
+  DQDRVN1                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[24:20]=5'h08 (Mirror: 5'h00)
+  DQDRVP1                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[29:25]=5'h06 (Mirror: 5'h00)
+  DIS_IMPCAL_ODT_EN                            uvm_reg_field                                              ...    RW SHU_MISC_DRVING2_0[31:31]=1'h0
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2, P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN1) |
+        P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN2) |
+        P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x08, SHU_MISC_DRVING2_DQDRVN1) |
+        P_Fld(0x06, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_DRVING3_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING3_0                      -     @12655
+  DQODTN2                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[4:0]=5'h0a (Mirror: 5'h00)
+  DQODTP2                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[9:5]=5'h0a (Mirror: 5'h00)
+  DQSODTN                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[14:10]=5'h0a (Mirror: 5'h00)
+  DQSODTP                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[19:15]=5'h0a (Mirror: 5'h00)
+  DQSODTN2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[24:20]=5'h0a (Mirror: 5'h00)
+  DQSODTP2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING3_0[29:25]=5'h0a (Mirror: 5'h00)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3, P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) |
+        P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) |
+        P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) |
+        P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_DRVING4_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING4_0                      -     @12664
+  CMDODTN1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[4:0]=5'h0a (Mirror: 5'h00)
+  CMDODTP1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[9:5]=5'h0a (Mirror: 5'h00)
+  CMDODTN2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[14:10]=5'h0a (Mirror: 5'h00)
+  CMDODTP2                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[19:15]=5'h0a (Mirror: 5'h00)
+  DQODTN1                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[24:20]=5'h0a (Mirror: 5'h00)
+  DQODTP1                                      uvm_reg_field                                              ...    RW SHU_MISC_DRVING4_0[29:25]=5'h0a (Mirror: 5'h00)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4, P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) |
+        P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) |
+        P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) |
+        P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_DRVING6_0                             ral_reg_DDRPHY_blk_SHU_MISC_DRVING6_0                      -     @12682
+  IMP_TXDLY_CMD                                uvm_reg_field                                              ...    RW SHU_MISC_DRVING6_0[5:0]=6'h0d (Mirror: 6'h01)
+  DQCODTN1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING6_0[24:20]=5'h00
+  DQCODTP1                                     uvm_reg_field                                              ...    RW SHU_MISC_DRVING6_0[29:25]=5'h00
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6, P_Fld(0x0d, SHU_MISC_DRVING6_IMP_TXDLY_CMD) |
+        P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_IMPCAL1_0                             ral_reg_DDRPHY_blk_SHU_MISC_IMPCAL1_0                      -     @12625
+  IMPCAL_CHKCYCLE                              uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[2:0]=3'h7 (Mirror: 3'h4)
+  IMPDRVP                                      uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[8:4]=5'h00
+  IMPDRVN                                      uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[16:12]=5'h00
+  IMPCAL_CALEN_CYCLE                           uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[19:17]=3'h4
+  IMPCALCNT                                    uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[27:20]=8'h03 (Mirror: 8'h00)
+  IMPCAL_CALICNT                               uvm_reg_field                                              ...    RW SHU_MISC_IMPCAL1_0[31:28]=4'h8
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1, P_Fld(0x7, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) |
+        P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) |
+        P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) |
+        P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Exit:
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter:
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_RDSEL_TRACK_0                         ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0                  -     @12734
+  DMDATLAT_i                                   uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h13 (Mirror: 5'h00)
+  RDSEL_HWSAVE_MSK                             uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0)
+  RDSEL_TRACK_EN                               uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0
+  SHU_GW_THRD_NEG                              uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfcb (Mirror: 12'h000)
+  SHU_GW_THRD_POS                              uvm_reg_field                                              ...    RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h035 (Mirror: 12'h000)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x13, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) |
+        P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) |
+        P_Fld(0xfcb, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x035, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RDAT_0                                ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0                         -     @12604
+  DATLAT                                       uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[4:0]=5'h13 (Mirror: 5'h00)
+  DATLAT_DSEL                                  uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[12:8]=5'h12 (Mirror: 5'h00)
+  DATLAT_DSEL_PHY                              uvm_reg_field                                              ...    RW MISC_SHU_RDAT_0[20:16]=5'h12 (Mirror: 5'h00)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x13, MISC_SHU_RDAT_DATLAT) |
+        P_Fld(0x12, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x12, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_PHY_RX_CTRL_0                         ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0                  -     @12540
+  RANK_RXDLY_UPDLAT_EN                         uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0)
+  RANK_RXDLY_UPD_OFFSET                        uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0)
+  RX_IN_GATE_EN_PRE_OFFSET                     uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0)
+  RX_IN_GATE_EN_HEAD                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h1 (Mirror: 3'h0)
+  RX_IN_GATE_EN_TAIL                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0)
+  RX_IN_BUFF_EN_HEAD                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h3 (Mirror: 3'h0)
+  RX_IN_BUFF_EN_TAIL                           uvm_reg_field                                              ...    RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) |
+        P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) |
+        P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) |
+        P_Fld(0x3, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RANKCTL_0                             ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0                      -     @12530
+  RANKINCTL_RXDLY                              uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[3:0]=4'h8 (Mirror: 4'h0)
+  RANK_RXDLY_OPT                               uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[4:4]=1'h1
+  RANKSEL_SELPH_FRUN                           uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[15:15]=1'h0
+  RANKINCTL_STB                                uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[19:16]=4'hb (Mirror: 4'h0)
+  RANKINCTL                                    uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[23:20]=4'h9 (Mirror: 4'h0)
+  RANKINCTL_ROOT1                              uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[27:24]=4'h9 (Mirror: 4'h0)
+  RANKINCTL_PHY                                uvm_reg_field                                              ...    RW MISC_SHU_RANKCTL_0[31:28]=4'hc (Mirror: 4'h0)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x8, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) |
+        P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) |
+        P_Fld(0xb, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x9, MISC_SHU_RANKCTL_RANKINCTL) |
+        P_Fld(0x9, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0xc, MISC_SHU_RANKCTL_RANKINCTL_PHY));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RANK_SEL_LAT_0                        ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0                 -     @12757
+  RANK_SEL_LAT_B0                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0)
+  RANK_SEL_LAT_B1                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0)
+  RANK_SEL_LAT_CA                              uvm_reg_field                                              ...    RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
+        P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RK_DQSCTL_0_0                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0                  -     @12352
+  DQSINCTL                                     uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'hb (Mirror: 4'h0)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0xb, MISC_SHU_RK_DQSCTL_DQSINCTL);
+/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RK_DQSCTL_0_1                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1                  -     @12356
+  DQSINCTL                                     uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'hb (Mirror: 4'h0)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0xb, MISC_SHU_RK_DQSCTL_DQSINCTL);
+/*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0         -     @7624
+  DQSIEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'hb (Mirror: 4'h0)
+  DQSIEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hf (Mirror: 4'h0)
+  DQSIEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0
+  DQSIEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0xb, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+        P_Fld(0xf, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+        P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+/*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_DQSIEN_PI_DLY_0_0                    ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0             -     @7638
+  DQSIEN_PI_B0                                 uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h05 (Mirror: 7'h00)
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x05, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1         -     @7631
+  DQSIEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hd (Mirror: 4'h0)
+  DQSIEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h1 (Mirror: 4'h0)
+  DQSIEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0
+  DQSIEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+        P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+        P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_DQSIEN_PI_DLY_0_1                    ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1             -     @7642
+  DQSIEN_PI_B0                                 uvm_reg_field                                              ...    RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h1b (Mirror: 7'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1b, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0         -     @9027
+  DQSIEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'hb (Mirror: 4'h0)
+  DQSIEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hf (Mirror: 4'h0)
+  DQSIEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0
+  DQSIEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0xb, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+        P_Fld(0xf, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+        P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_DQSIEN_PI_DLY_0_0                    ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0             -     @9041
+  DQSIEN_PI_B1                                 uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h05 (Mirror: 7'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x05, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1         -     @9034
+  DQSIEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hd (Mirror: 4'h0)
+  DQSIEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h1 (Mirror: 4'h0)
+  DQSIEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0
+  DQSIEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+        P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+        P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_DQSIEN_PI_DLY_0_1                    ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1             -     @9045
+  DQSIEN_PI_B1                                 uvm_reg_field                                              ...    RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h1b (Mirror: 7'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1b, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_ODTCTRL_0                             ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0                      -     @12550
+  RODTEN                                       uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0)
+  RODTENSTB_SELPH_CG_IG                        uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[1:1]=1'h0
+  RODT_LAT                                     uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[7:4]=4'ha (Mirror: 4'h0)
+  RODTEN_SELPH_FRUN                            uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[15:15]=1'h0
+  RODTDLY_LAT_OPT                              uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[25:24]=2'h0
+  FIXRODT                                      uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[27:27]=1'h0
+  RODTEN_OPT                                   uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[29:29]=1'h1
+  RODTE2                                       uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0)
+  RODTE                                        uvm_reg_field                                              ...    RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) |
+        P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0xa, MISC_SHU_ODTCTRL_RODT_LAT) |
+        P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) |
+        P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) |
+        P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ7_0                            -     @7808
+  R_DMRANKRXDVS_B0                             uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[3:0]=4'h0
+  R_DMDQMDBI_EYE_SHU_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[6:6]=1'h0
+  R_DMDQMDBI_SHU_B0                            uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[7:7]=1'h0
+  R_DMRXDVS_DQM_FLAGSEL_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[11:8]=4'h0
+  R_DMRXDVS_PBYTE_FLAG_OPT_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[12:12]=1'h0
+  R_DMRXDVS_PBYTE_DQM_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[13:13]=1'h0
+  R_DMRXTRACK_DQM_EN_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[14:14]=1'h0
+  R_DMRODTEN_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)
+  R_DMARPI_CG_FB2DLL_DCM_EN_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[16:16]=1'h0
+  R_DMTX_ARPI_CG_DQ_NEW_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[17:17]=1'h0
+  R_DMTX_ARPI_CG_DQS_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[18:18]=1'h0
+  R_DMTX_ARPI_CG_DQM_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[19:19]=1'h0
+  R_LP4Y_SDN_MODE_DQS0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[20:20]=1'h0
+  R_DMRXRANK_DQ_EN_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)
+  R_DMRXRANK_DQ_LAT_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[27:25]=3'h2 (Mirror: 3'h0)
+  R_DMRXRANK_DQS_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)
+  R_DMRXRANK_DQS_LAT_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[31:29]=3'h1 (Mirror: 3'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ7_0                            -     @9211
+  R_DMRANKRXDVS_B1                             uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[3:0]=4'h0
+  R_DMDQMDBI_EYE_SHU_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[6:6]=1'h0
+  R_DMDQMDBI_SHU_B1                            uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[7:7]=1'h0
+  R_DMRXDVS_DQM_FLAGSEL_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[11:8]=4'h0
+  R_DMRXDVS_PBYTE_FLAG_OPT_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[12:12]=1'h0
+  R_DMRXDVS_PBYTE_DQM_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[13:13]=1'h0
+  R_DMRXTRACK_DQM_EN_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[14:14]=1'h0
+  R_DMRODTEN_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)
+  R_DMARPI_CG_FB2DLL_DCM_EN_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[16:16]=1'h0
+  R_DMTX_ARPI_CG_DQ_NEW_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[17:17]=1'h0
+  R_DMTX_ARPI_CG_DQS_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[18:18]=1'h0
+  R_DMTX_ARPI_CG_DQM_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[19:19]=1'h0
+  R_LP4Y_SDN_MODE_DQS1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[20:20]=1'h0
+  R_DMRXRANK_DQ_EN_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)
+  R_DMRXRANK_DQ_LAT_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[27:25]=3'h2 (Mirror: 3'h0)
+  R_DMRXRANK_DQS_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)
+  R_DMRXRANK_DQS_LAT_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[31:29]=3'h1 (Mirror: 3'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0         -     @7646
+  RODTEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h6 (Mirror: 3'h0)
+  RODTEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h6 (Mirror: 3'h0)
+  RODTEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0
+  RODTEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x6, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+        P_Fld(0x6, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+        P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1         -     @7653
+  RODTEN_UI_P0_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h0
+  RODTEN_UI_P1_B0                              uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h0
+  RODTEN_MCK_P0_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0)
+  RODTEN_MCK_P1_B0                             uvm_reg_field                                              ...    RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+        P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+        P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0                ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0         -     @9049
+  RODTEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h6 (Mirror: 3'h0)
+  RODTEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h6 (Mirror: 3'h0)
+  RODTEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0
+  RODTEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x6, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+        P_Fld(0x6, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+        P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1                ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1         -     @9056
+  RODTEN_UI_P0_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h0
+  RODTEN_UI_P1_B1                              uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h0
+  RODTEN_MCK_P0_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0)
+  RODTEN_MCK_P1_B1                             uvm_reg_field                                              ...    RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+        P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+        P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_RX_CG_SET0_0                               ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0                         -     @5323
+  DLE_LAST_EXTEND3                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[0:0]=1'h1 (Mirror: 1'h0)
+  READ_START_EXTEND3                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[1:1]=1'h1 (Mirror: 1'h0)
+  DLE_LAST_EXTEND2                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0)
+  READ_START_EXTEND2                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0)
+  DLE_LAST_EXTEND1                             uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0)
+  READ_START_EXTEND1                           uvm_reg_field                                              ...    RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) |
+        P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) |
+        P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
+        P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_RANK_SEL_STB_0                        ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0                 -     @12720
+  RANK_SEL_STB_EN                              uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0)
+  RANK_SEL_STB_EN_B23                          uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0
+  RANK_SEL_STB_SERMODE                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0
+  RANK_SEL_STB_TRACK                           uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0)
+  RANK_SEL_RXDLY_TRACK                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0
+  RANK_SEL_STB_PHASE_EN                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h1 (Mirror: 1'h0)
+  RANK_SEL_PHSINCTL                            uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'hc (Mirror: 4'h0)
+  RANK_SEL_STB_UI_PLUS                         uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0
+  RANK_SEL_STB_MCK_PLUS                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0
+  RANK_SEL_STB_UI_MINUS                        uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h1 (Mirror: 4'h0)
+  RANK_SEL_STB_MCK_MINUS                       uvm_reg_field                                              ...    RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) |
+        P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) |
+        P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) |
+        P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0xc, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) |
+        P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) |
+        P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RK_DQSCAL_0_0                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0                  -     @12370
+  DQSIENLLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00)
+  DQSIENLLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0)
+  DQSIENHLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00)
+  DQSIENHLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RK_DQSCAL_0_1                         ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1                  -     @12377
+  DQSIENLLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00)
+  DQSIENLLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0)
+  DQSIENHLMT                                   uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00)
+  DQSIENHLMTEN                                 uvm_reg_field                                              ...    RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+        P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_INI_UIPI_0_0                         ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0                  -     @7602
+  CURR_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h05 (Mirror: 7'h00)
+  CURR_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h0b (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x05, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+        P_Fld(0x0b, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_INI_UIPI_0_0                         ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0                  -     @9005
+  CURR_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h05 (Mirror: 7'h00)
+  CURR_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h0b (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x05, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+        P_Fld(0x0b, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_INI_UIPI_0_1                         ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1                  -     @7607
+  CURR_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h1b (Mirror: 7'h00)
+  CURR_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h0d (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1b, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+        P_Fld(0x0d, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_INI_UIPI_0_1                         ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1                  -     @9010
+  CURR_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h1b (Mirror: 7'h00)
+  CURR_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h0d (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1b, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+        P_Fld(0x0d, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_NEXT_INI_UIPI_0_0                    ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0             -     @7612
+  NEXT_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h05 (Mirror: 7'h00)
+  NEXT_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h0b (Mirror: 8'h00)
+  NEXT_INI_UI_P1_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h0f (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x05, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+        P_Fld(0x0b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_NEXT_INI_UIPI_0_0                    ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0             -     @9015
+  NEXT_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h05 (Mirror: 7'h00)
+  NEXT_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h0b (Mirror: 8'h00)
+  NEXT_INI_UI_P1_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h0f (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x05, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+        P_Fld(0x0b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_NEXT_INI_UIPI_0_1                    ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1             -     @7618
+  NEXT_INI_PI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h1b (Mirror: 7'h00)
+  NEXT_INI_UI_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h0d (Mirror: 8'h00)
+  NEXT_INI_UI_P1_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h11 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+        P_Fld(0x0d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_NEXT_INI_UIPI_0_1                    ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1             -     @9021
+  NEXT_INI_PI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h1b (Mirror: 7'h00)
+  NEXT_INI_UI_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h0d (Mirror: 8'h00)
+  NEXT_INI_UI_P1_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h11 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+        P_Fld(0x0d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit:
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter:
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_CA_CMD0_0_0                             ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_0                      -     @10426
+  RG_RX_ARCLK_R_DLY_DUTY                       uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[2:0]=3'h0
+  RG_RX_ARCLK_F_DLY_DUTY                       uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[6:4]=3'h0
+  RG_ARPI_CS                                   uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[13:8]=6'h00
+  RG_ARPI_CMD                                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[21:16]=6'h20 (Mirror: 6'h00)
+  RG_ARPI_CLK                                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[29:24]=6'h00
+  DA_ARPI_DDR400_0D5UI_RK0_CA                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[30:30]=1'h0
+  DA_RX_ARDQSIEN_0D5UI_RK0_CA                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
+        P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
+        P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_DQ0_0_0                              ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0                       -     @7582
+  RG_RX_ARDQS0_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0
+  RG_RX_ARDQS0_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0
+  SW_ARPI_DQ_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[13:8]=6'h1f (Mirror: 6'h00)
+  SW_ARPI_DQM_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[21:16]=6'h1f (Mirror: 6'h00)
+  ARPI_PBYTE_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00
+  DA_ARPI_DDR400_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0
+  DA_RX_ARDQSIEN_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x1f, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+        P_Fld(0x1f, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
+        P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_DQ0_0_0                              ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0                       -     @8985
+  RG_RX_ARDQS1_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0
+  RG_RX_ARDQS1_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0
+  SW_ARPI_DQ_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[13:8]=6'h25 (Mirror: 6'h00)
+  SW_ARPI_DQM_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[21:16]=6'h25 (Mirror: 6'h00)
+  ARPI_PBYTE_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00
+  DA_ARPI_DDR400_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0
+  DA_RX_ARDQSIEN_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x25, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+        P_Fld(0x25, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
+        P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_CA_CMD0_0_1                             ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_1                      -     @10436
+  RG_RX_ARCLK_R_DLY_DUTY                       uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[2:0]=3'h0
+  RG_RX_ARCLK_F_DLY_DUTY                       uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[6:4]=3'h0
+  RG_ARPI_CS                                   uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[13:8]=6'h00
+  RG_ARPI_CMD                                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[21:16]=6'h20 (Mirror: 6'h00)
+  RG_ARPI_CLK                                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[29:24]=6'h00
+  DA_ARPI_DDR400_0D5UI_RK0_CA                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[30:30]=1'h0
+  DA_RX_ARDQSIEN_0D5UI_RK0_CA                  uvm_reg_field                                              ...    RW SHU_R0_CA_CMD0_0_1[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
+        P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
+        P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_DQ0_0_1                              ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1                       -     @7592
+  RG_RX_ARDQS0_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0
+  RG_RX_ARDQS0_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0
+  SW_ARPI_DQ_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[13:8]=6'h2c (Mirror: 6'h00)
+  SW_ARPI_DQM_B0                               uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[21:16]=6'h2c (Mirror: 6'h00)
+  ARPI_PBYTE_B0                                uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00
+  DA_ARPI_DDR400_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0
+  DA_RX_ARDQSIEN_0D5UI_RK0_B0                  uvm_reg_field                                              ...    RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x2c, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+        P_Fld(0x2c, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
+        P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_DQ0_0_1                              ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1                       -     @8995
+  RG_RX_ARDQS1_R_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0
+  RG_RX_ARDQS1_F_DLY_DUTY                      uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0
+  SW_ARPI_DQ_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[13:8]=6'h1f (Mirror: 6'h00)
+  SW_ARPI_DQM_B1                               uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[21:16]=6'h1f (Mirror: 6'h00)
+  ARPI_PBYTE_B1                                uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00
+  DA_ARPI_DDR400_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0
+  DA_RX_ARDQSIEN_0D5UI_RK0_B1                  uvm_reg_field                                              ...    RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+        P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+        P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
+        P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_DCM_CTRL0_0                                ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0                          -     @5027
+  DDRPHY_CLK_EN_OPT                            uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0)
+  DPHY_CMDDCM_EXTCNT                           uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[11:8]=4'h4
+  DDRPHY_CLK_DYN_GATING_SEL                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0)
+  CKE_EXTNONPD_CNT                             uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[19:16]=4'h0
+  FASTWAKE2                                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[29:29]=1'h0
+  FASTWAKE                                     uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[31:31]=1'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+        P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+        P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) |
+        P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_APHY_TX_PICG_CTRL_0                        ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0                  -     @5377
+  DDRPHY_CLK_EN_COMB_TX_PICG_CNT               uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h8 (Mirror: 4'h0)
+  DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1             uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h4 (Mirror: 3'h0)
+  DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0             uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h3 (Mirror: 3'h0)
+  DDRPHY_CLK_EN_COMB_TX_OPT                    uvm_reg_field                                              ...    RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x8, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) |
+        P_Fld(0x4, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) |
+        P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_APHY_TX_PICG_CTRL_0_0                    ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0              -     @4926
+  DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h5 (Mirror: 3'h0)
+  DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h4 (Mirror: 3'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x5, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+        P_Fld(0x4, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_APHY_TX_PICG_CTRL_0_1                    ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1              -     @4931
+  DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h5 (Mirror: 3'h0)
+  DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0           uvm_reg_field                                              ...    RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h4 (Mirror: 3'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+        P_Fld(0x4, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_NEW_XRW2W_CTRL_0                           ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0                     -     @5371
+  TX_PI_UPDCTL_B0                              uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h4 (Mirror: 3'h0)
+  TX_PI_UPDCTL_B1                              uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h4 (Mirror: 3'h0)
+  TXPI_UPD_MODE                                uvm_reg_field                                              ...    RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x4, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) |
+        P_Fld(0x4, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SELPH_DQS0_0                               ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0                         -     @5271
+  TXDLY_DQS0                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[2:0]=3'h5 (Mirror: 3'h1)
+  TXDLY_DQS1                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[6:4]=3'h5 (Mirror: 3'h1)
+  TXDLY_DQS2                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[10:8]=3'h1
+  TXDLY_DQS3                                   uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[14:12]=3'h1
+  TXDLY_OEN_DQS0                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[18:16]=3'h4 (Mirror: 3'h1)
+  TXDLY_OEN_DQS1                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[22:20]=3'h5 (Mirror: 3'h1)
+  TXDLY_OEN_DQS2                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[26:24]=3'h1
+  TXDLY_OEN_DQS3                               uvm_reg_field                                              ...    RW SHU_SELPH_DQS0_0[30:28]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x5, SHU_SELPH_DQS0_TXDLY_DQS0) |
+        P_Fld(0x5, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) |
+        P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) |
+        P_Fld(0x5, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) |
+        P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SELPH_DQS1_0                               ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0                         -     @5282
+  dly_DQS0                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[3:0]=4'h2 (Mirror: 4'h1)
+  dly_DQS1                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[7:4]=4'h3 (Mirror: 4'h1)
+  dly_DQS2                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[11:8]=4'h1
+  dly_DQS3                                     uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[15:12]=4'h1
+  dly_oen_DQS0                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[19:16]=4'h7 (Mirror: 4'h1)
+  dly_oen_DQS1                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[23:20]=4'h0 (Mirror: 4'h1)
+  dly_oen_DQS2                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[27:24]=4'h1
+  dly_oen_DQS3                                 uvm_reg_field                                              ...    RW SHU_SELPH_DQS1_0[31:28]=4'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x2, SHU_SELPH_DQS1_DLY_DQS0) |
+        P_Fld(0x3, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) |
+        P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x7, SHU_SELPH_DQS1_DLY_OEN_DQS0) |
+        P_Fld(0x0, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) |
+        P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ0_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0                      -     @4746
+  TXDLY_DQ0                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[2:0]=3'h5 (Mirror: 3'h1)
+  TXDLY_DQ1                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[6:4]=3'h5 (Mirror: 3'h1)
+  TXDLY_DQ2                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1
+  TXDLY_DQ3                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1
+  TXDLY_OEN_DQ0                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[18:16]=3'h5 (Mirror: 3'h1)
+  TXDLY_OEN_DQ1                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[22:20]=3'h5 (Mirror: 3'h1)
+  TXDLY_OEN_DQ2                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1
+  TXDLY_OEN_DQ3                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+        P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+        P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ1_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0                      -     @4768
+  TXDLY_DQM0                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[2:0]=3'h5 (Mirror: 3'h1)
+  TXDLY_DQM1                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[6:4]=3'h5 (Mirror: 3'h1)
+  TXDLY_DQM2                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1
+  TXDLY_DQM3                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1
+  TXDLY_OEN_DQM0                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[18:16]=3'h5 (Mirror: 3'h1)
+  TXDLY_OEN_DQM1                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[22:20]=3'h5 (Mirror: 3'h1)
+  TXDLY_OEN_DQM2                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1
+  TXDLY_OEN_DQM3                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+        P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+        P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ2_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0                      -     @4790
+  dly_DQ0                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[3:0]=4'h1
+  dly_DQ1                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[7:4]=4'h1
+  dly_DQ2                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1
+  dly_DQ3                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1
+  dly_oen_DQ0                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[19:16]=4'h5 (Mirror: 4'h1)
+  dly_oen_DQ1                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[23:20]=4'h5 (Mirror: 4'h1)
+  dly_oen_DQ2                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1
+  dly_oen_DQ3                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x5, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+        P_Fld(0x5, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ3_0_0                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0                      -     @4812
+  dly_DQM0                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[3:0]=4'h1
+  dly_DQM1                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[7:4]=4'h1
+  dly_DQM2                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1
+  dly_DQM3                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1
+  dly_oen_DQM0                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[19:16]=4'h5 (Mirror: 4'h1)
+  dly_oen_DQM1                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[23:20]=4'h5 (Mirror: 4'h1)
+  dly_oen_DQM2                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1
+  dly_oen_DQM3                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x5, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+        P_Fld(0x5, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ0_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1                      -     @4757
+  TXDLY_DQ0                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[2:0]=3'h5 (Mirror: 3'h1)
+  TXDLY_DQ1                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[6:4]=3'h5 (Mirror: 3'h1)
+  TXDLY_DQ2                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1
+  TXDLY_DQ3                                    uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1
+  TXDLY_OEN_DQ0                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[18:16]=3'h5 (Mirror: 3'h1)
+  TXDLY_OEN_DQ1                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[22:20]=3'h5 (Mirror: 3'h1)
+  TXDLY_OEN_DQ2                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1
+  TXDLY_OEN_DQ3                                uvm_reg_field                                              ...    RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+        P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+        P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ1_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1                      -     @4779
+  TXDLY_DQM0                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[2:0]=3'h5 (Mirror: 3'h1)
+  TXDLY_DQM1                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[6:4]=3'h5 (Mirror: 3'h1)
+  TXDLY_DQM2                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1
+  TXDLY_DQM3                                   uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1
+  TXDLY_OEN_DQM0                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[18:16]=3'h5 (Mirror: 3'h1)
+  TXDLY_OEN_DQM1                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[22:20]=3'h5 (Mirror: 3'h1)
+  TXDLY_OEN_DQM2                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1
+  TXDLY_OEN_DQM3                               uvm_reg_field                                              ...    RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+        P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+        P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ2_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1                      -     @4801
+  dly_DQ0                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[3:0]=4'h2 (Mirror: 4'h1)
+  dly_DQ1                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[7:4]=4'h2 (Mirror: 4'h1)
+  dly_DQ2                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1
+  dly_DQ3                                      uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1
+  dly_oen_DQ0                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[19:16]=4'h6 (Mirror: 4'h1)
+  dly_oen_DQ1                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[23:20]=4'h6 (Mirror: 4'h1)
+  dly_oen_DQ2                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1
+  dly_oen_DQ3                                  uvm_reg_field                                              ...    RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ0) |
+        P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+        P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+        P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_SELPH_DQ3_0_1                            ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1                      -     @4823
+  dly_DQM0                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[3:0]=4'h2 (Mirror: 4'h1)
+  dly_DQM1                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[7:4]=4'h2 (Mirror: 4'h1)
+  dly_DQM2                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1
+  dly_DQM3                                     uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1
+  dly_oen_DQM0                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[19:16]=4'h6 (Mirror: 4'h1)
+  dly_oen_DQM1                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[23:20]=4'h6 (Mirror: 4'h1)
+  dly_oen_DQM2                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1
+  dly_oen_DQM3                                 uvm_reg_field                                              ...    RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM0) |
+        P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+        P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+        P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL1_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0                    -     @4834
+  BOOT_ORIG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h01f (Mirror: 11'h000)
+  BOOT_ORIG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h025 (Mirror: 11'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x01f, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+        P_Fld(0x025, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL2_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0                    -     @4844
+  BOOT_TARG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h01f (Mirror: 11'h000)
+  BOOT_TARG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h025 (Mirror: 11'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x01f, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+        P_Fld(0x025, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL5_0_0                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0                    -     @4882
+  BOOT_TARG_UI_RK0_DQM0                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h01f (Mirror: 11'h000)
+  BOOT_TARG_UI_RK0_DQM1                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h025 (Mirror: 11'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x01f, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+        P_Fld(0x025, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL1_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1                    -     @4839
+  BOOT_ORIG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h02c (Mirror: 11'h000)
+  BOOT_ORIG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h01f (Mirror: 11'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02c, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+        P_Fld(0x01f, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL2_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1                    -     @4849
+  BOOT_TARG_UI_RK0_DQ0                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h02c (Mirror: 11'h000)
+  BOOT_TARG_UI_RK0_DQ1                         uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h01f (Mirror: 11'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02c, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+        P_Fld(0x01f, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQS2DQ_CAL5_0_1                          ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1                    -     @4887
+  BOOT_TARG_UI_RK0_DQM0                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h02c (Mirror: 11'h000)
+  BOOT_TARG_UI_RK0_DQM1                        uvm_reg_field                                              ...    RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h01f (Mirror: 11'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02c, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+        P_Fld(0x01f, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_PI_0_0                                   ral_reg_DRAMC_blk_SHURK_PI_0_0                             -     @4892
+  RK0_ARPI_DQ_B1                               uvm_reg_field                                              ...    RW SHURK_PI_0_0[5:0]=6'h25 (Mirror: 6'h00)
+  RK0_ARPI_DQ_B0                               uvm_reg_field                                              ...    RW SHURK_PI_0_0[13:8]=6'h1f (Mirror: 6'h00)
+  RK0_ARPI_DQM_B1                              uvm_reg_field                                              ...    RW SHURK_PI_0_0[21:16]=6'h25 (Mirror: 6'h00)
+  RK0_ARPI_DQM_B0                              uvm_reg_field                                              ...    RW SHURK_PI_0_0[29:24]=6'h1f (Mirror: 6'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x25, SHURK_PI_RK0_ARPI_DQ_B1) |
+        P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x25, SHURK_PI_RK0_ARPI_DQM_B1) |
+        P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQM_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_PI_0_1                                   ral_reg_DRAMC_blk_SHURK_PI_0_1                             -     @4899
+  RK0_ARPI_DQ_B1                               uvm_reg_field                                              ...    RW SHURK_PI_0_1[5:0]=6'h1f (Mirror: 6'h00)
+  RK0_ARPI_DQ_B0                               uvm_reg_field                                              ...    RW SHURK_PI_0_1[13:8]=6'h2c (Mirror: 6'h00)
+  RK0_ARPI_DQM_B1                              uvm_reg_field                                              ...    RW SHURK_PI_0_1[21:16]=6'h1f (Mirror: 6'h00)
+  RK0_ARPI_DQM_B0                              uvm_reg_field                                              ...    RW SHURK_PI_0_1[29:24]=6'h2c (Mirror: 6'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQ_B1) |
+        P_Fld(0x2c, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQM_B1) |
+        P_Fld(0x2c, SHURK_PI_RK0_ARPI_DQM_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_TXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0                    -     @7428
+  TX_ARDQ0_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h14 (Mirror: 8'h00)
+  TX_ARDQ1_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h14 (Mirror: 8'h00)
+  TX_ARDQ2_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h14 (Mirror: 8'h00)
+  TX_ARDQ3_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h14 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+        P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+        P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_TXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0                    -     @7442
+  TX_ARDQ4_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h14 (Mirror: 8'h00)
+  TX_ARDQ5_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h14 (Mirror: 8'h00)
+  TX_ARDQ6_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h14 (Mirror: 8'h00)
+  TX_ARDQ7_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h14 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+        P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+        P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_TXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0                    -     @7470
+  TX_ARDQM0_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h14 (Mirror: 8'h00)
+  TX_ARWCK_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00
+  TX_ARWCKB_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x14, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+        P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_TXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1                    -     @7435
+  TX_ARDQ0_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h04 (Mirror: 8'h00)
+  TX_ARDQ1_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h04 (Mirror: 8'h00)
+  TX_ARDQ2_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h04 (Mirror: 8'h00)
+  TX_ARDQ3_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h04 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x04, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+        P_Fld(0x04, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x04, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+        P_Fld(0x04, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_TXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1                    -     @7449
+  TX_ARDQ4_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h04 (Mirror: 8'h00)
+  TX_ARDQ5_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h04 (Mirror: 8'h00)
+  TX_ARDQ6_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h04 (Mirror: 8'h00)
+  TX_ARDQ7_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h04 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x04, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+        P_Fld(0x04, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x04, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+        P_Fld(0x04, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_TXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1                    -     @7476
+  TX_ARDQM0_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h04 (Mirror: 8'h00)
+  TX_ARWCK_DLY_B0                              uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00
+  TX_ARWCKB_DLY_B0                             uvm_reg_field                                              ...    RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x04, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+        P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_TXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1                    -     @8838
+  TX_ARDQ0_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h34 (Mirror: 8'h00)
+  TX_ARDQ1_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h34 (Mirror: 8'h00)
+  TX_ARDQ2_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h34 (Mirror: 8'h00)
+  TX_ARDQ3_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h34 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+        P_Fld(0x34, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x34, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+        P_Fld(0x34, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_TXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1                    -     @8852
+  TX_ARDQ4_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h34 (Mirror: 8'h00)
+  TX_ARDQ5_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h34 (Mirror: 8'h00)
+  TX_ARDQ6_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h34 (Mirror: 8'h00)
+  TX_ARDQ7_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h34 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+        P_Fld(0x34, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x34, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+        P_Fld(0x34, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_TXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1                    -     @8879
+  TX_ARDQM0_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h34 (Mirror: 8'h00)
+  TX_ARWCK_DLY_B1                              uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00
+  TX_ARWCKB_DLY_B1                             uvm_reg_field                                              ...    RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+        P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_TX_RANKCTL_0                               ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0                         -     @5345
+  TXRANKINCTL_TXDLY                            uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[3:0]=4'h3 (Mirror: 4'h0)
+  TXRANKINCTL                                  uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[7:4]=4'h3 (Mirror: 4'h0)
+  TXRANKINCTL_ROOT                             uvm_reg_field                                              ...    RW SHU_TX_RANKCTL_0[11:8]=4'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x3, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) |
+        P_Fld(0x3, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ9_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ9_0                            -     @9248
+  RG_ARPI_RESERVE_B1                           uvm_reg_field                                              ...    RW SHU_B1_DQ9_0[31:0]=32'hce301f15 (Mirror: 32'hce341f15)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9, 0xce301f15, SHU_B1_DQ9_RG_ARPI_RESERVE_B1);
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit:
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Enter
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_WCK_WR_MCK_0_0                           ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_0                     -     @4936
+  WCK_WR_B0_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_WR_MCK_0_0[3:0]=4'h5 (Mirror: 4'h1)
+  WCK_WR_B1_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_WR_MCK_0_0[7:4]=4'h5 (Mirror: 4'h1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK, P_Fld(0x5, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) |
+        P_Fld(0x5, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_WCK_WR_MCK_0_1                           ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_1                     -     @4941
+  WCK_WR_B0_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_WR_MCK_0_1[3:0]=4'h5 (Mirror: 4'h1)
+  WCK_WR_B1_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_WR_MCK_0_1[7:4]=4'h5 (Mirror: 4'h1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) |
+        P_Fld(0x5, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_WCK_RD_MCK_0_0                           ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_0                     -     @4946
+  WCK_RD_B0_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_RD_MCK_0_0[3:0]=4'h8 (Mirror: 4'h1)
+  WCK_RD_B1_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_RD_MCK_0_0[7:4]=4'h8 (Mirror: 4'h1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+#if LP5_DDR4266_RDBI_WORKAROUND
+vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK, P_Fld(0x8, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
+        P_Fld(0x8, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
+#else
+vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK, P_Fld(0x7, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
+        P_Fld(0x7, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
+#endif
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_WCK_RD_MCK_0_1                           ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_1                     -     @4951
+  WCK_RD_B0_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_RD_MCK_0_1[3:0]=4'h8 (Mirror: 4'h1)
+  WCK_RD_B1_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_RD_MCK_0_1[7:4]=4'h8 (Mirror: 4'h1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x8, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
+        P_Fld(0x8, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_WCK_FS_MCK_0_0                           ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_0                     -     @4956
+  WCK_FS_B0_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_FS_MCK_0_0[3:0]=4'h4 (Mirror: 4'h1)
+  WCK_FS_B1_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_FS_MCK_0_0[7:4]=4'h4 (Mirror: 4'h1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK, P_Fld(0x4, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) |
+        P_Fld(0x4, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_WCK_FS_MCK_0_1                           ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_1                     -     @4961
+  WCK_FS_B0_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_FS_MCK_0_1[3:0]=4'h4 (Mirror: 4'h1)
+  WCK_FS_B1_MCK                                uvm_reg_field                                              ...    RW SHURK_WCK_FS_MCK_0_1[7:4]=4'h4 (Mirror: 4'h1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) |
+        P_Fld(0x4, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Exit
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Enter:
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SELPH_CA1_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA1_0                          -     @5041
+  TXDLY_CS                                     uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[2:0]=3'h0 (Mirror: 3'h1)
+  TXDLY_CKE                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[6:4]=3'h0 (Mirror: 3'h1)
+  TXDLY_ODT                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[10:8]=3'h0 (Mirror: 3'h1)
+  TXDLY_RESET                                  uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[14:12]=3'h0 (Mirror: 3'h1)
+  TXDLY_WE                                     uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[18:16]=3'h0 (Mirror: 3'h1)
+  TXDLY_CAS                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[22:20]=3'h0 (Mirror: 3'h1)
+  TXDLY_RAS                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[26:24]=3'h0 (Mirror: 3'h1)
+  TXDLY_CS1                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA1_0[30:28]=3'h0 (Mirror: 3'h1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) |
+        P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) |
+        P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) |
+        P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) |
+        P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SELPH_CA2_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA2_0                          -     @5052
+  TXDLY_BA0                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[2:0]=3'h0 (Mirror: 3'h1)
+  TXDLY_BA1                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[6:4]=3'h0 (Mirror: 3'h1)
+  TXDLY_BA2                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[10:8]=3'h0 (Mirror: 3'h1)
+  TXDLY_CMD                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[20:16]=5'h01
+  TXDLY_CKE1                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA2_0[26:24]=3'h0 (Mirror: 3'h1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) |
+        P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) |
+        P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SELPH_CA3_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA3_0                          -     @5060
+  TXDLY_RA0                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[2:0]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA1                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[6:4]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA2                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[10:8]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA3                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[14:12]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA4                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[18:16]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA5                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[22:20]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA6                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[26:24]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA7                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA3_0[30:28]=3'h0 (Mirror: 3'h1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) |
+        P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) |
+        P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) |
+        P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) |
+        P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SELPH_CA4_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA4_0                          -     @5071
+  TXDLY_RA8                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[2:0]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA9                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[6:4]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA10                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[10:8]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA11                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[14:12]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA12                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[18:16]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA13                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[22:20]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA14                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[26:24]=3'h0 (Mirror: 3'h1)
+  TXDLY_RA15                                   uvm_reg_field                                              ...    RW SHU_SELPH_CA4_0[30:28]=3'h0 (Mirror: 3'h1)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) |
+        P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) |
+        P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) |
+        P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) |
+        P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SELPH_CA5_0                                ral_reg_DRAMC_blk_SHU_SELPH_CA5_0                          -     @5082
+  dly_CS                                       uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[2:0]=3'h1
+  dly_CKE                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[6:4]=3'h1
+  dly_ODT                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[10:8]=3'h0 (Mirror: 3'h1)
+  dly_RESET                                    uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[14:12]=3'h1
+  dly_WE                                       uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[18:16]=3'h1
+  dly_CAS                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[22:20]=3'h1
+  dly_RAS                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[26:24]=3'h1
+  dly_CS1                                      uvm_reg_field                                              ...    RW SHU_SELPH_CA5_0[30:28]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5, P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) |
+        P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) |
+        P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) |
+        P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) |
+        P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Exit
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter:
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_SREF_CTRL_0                                ral_reg_DRAMC_blk_SHU_SREF_CTRL_0                          -     @5018
+  CKEHCMD                                      uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[5:4]=2'h3
+  SREF_CK_DLY                                  uvm_reg_field                                              ...    RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) |
+        P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_HMR4_DVFS_CTRL0_0                          ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0                    -     @5036
+  FSPCHG_PRDCNT                                uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h86 (Mirror: 8'h00)
+  REFRCNT                                      uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x86, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+        P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_AC_TIME_05T_0                              ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0                        -     @5199
+  TRC_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[0:0]=1'h0
+  TRFCPB_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[1:1]=1'h0
+  TRFC_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[2:2]=1'h0
+  TPBR2PBR_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[3:3]=1'h0
+  TXP_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[4:4]=1'h0
+  TRTP_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[5:5]=1'h0
+  TRCD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[6:6]=1'h0
+  TRP_05T                                      uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[7:7]=1'h0
+  TRPAB_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[8:8]=1'h0
+  TRAS_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[9:9]=1'h0
+  TWR_M05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0)
+  TRRD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[12:12]=1'h0
+  TFAW_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[13:13]=1'h0
+  TCKEPRD_05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[14:14]=1'h0
+  TR2PD_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[15:15]=1'h0
+  TWTPD_M05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[16:16]=1'h1 (Mirror: 1'h0)
+  TMRRI_05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[17:17]=1'h0
+  TMRWCKEL_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[18:18]=1'h0
+  BGTRRD_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[19:19]=1'h0
+  BGTCCD_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[20:20]=1'h0
+  BGTWTR_M05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[21:21]=1'h1 (Mirror: 1'h0)
+  TR2W_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[22:22]=1'h0
+  TWTR_M05T                                    uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[23:23]=1'h1 (Mirror: 1'h0)
+  XRTR2W_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[24:24]=1'h1 (Mirror: 1'h0)
+  TMRD_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[25:25]=1'h0
+  TMRW_05T                                     uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[26:26]=1'h0
+  TMRR2MRW_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[27:27]=1'h0
+  TW2MRW_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[28:28]=1'h0
+  TR2MRW_05T                                   uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[29:29]=1'h0
+  TPBR2ACT_05T                                 uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[30:30]=1'h0
+  XRTW2R_M05T                                  uvm_reg_field                                              ...    RW SHU_AC_TIME_05T_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TXP_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRCD_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) |
+        P_Fld(0x1, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRRI_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_BGTWTR_M05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTR_M05T) |
+        P_Fld(0x1, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRD_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRR2MRW_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) |
+        P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM_XRT_0                                ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0                          -     @5192
+  XRTR2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[4:0]=5'h09 (Mirror: 5'h01)
+  XRTR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[13:8]=6'h0e (Mirror: 6'h01)
+  XRTW2R                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[19:16]=4'h0 (Mirror: 4'h1)
+  XRTW2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM_XRT_0[28:24]=5'h0d (Mirror: 5'h01)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x09, SHU_ACTIM_XRT_XRTR2R) |
+        P_Fld(0x0e, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x0, SHU_ACTIM_XRT_XRTW2R) |
+        P_Fld(0x0d, SHU_ACTIM_XRT_XRTW2W));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM0_0                                   ral_reg_DRAMC_blk_SHU_ACTIM0_0                             -     @5138
+  TWTR                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[3:0]=4'h9 (Mirror: 4'h1)
+  CKELCKCNT                                    uvm_reg_field                                              ...    RW SHU_ACTIM0_0[6:4]=3'h3 (Mirror: 3'h0)
+  TWR                                          uvm_reg_field                                              ...    RW SHU_ACTIM0_0[15:8]=8'h25 (Mirror: 8'h06)
+  TRRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[18:16]=3'h3 (Mirror: 3'h0)
+  TRCD                                         uvm_reg_field                                              ...    RW SHU_ACTIM0_0[27:24]=4'ha (Mirror: 4'h2)
+  TWTR_L                                       uvm_reg_field                                              ...    RW SHU_ACTIM0_0[31:28]=4'hf (Mirror: 4'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x9, SHU_ACTIM0_TWTR) |
+        P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x25, SHU_ACTIM0_TWR) |
+        P_Fld(0x3, SHU_ACTIM0_TRRD) | P_Fld(0xa, SHU_ACTIM0_TRCD) |
+        P_Fld(0xf, SHU_ACTIM0_TWTR_L));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM1_0                                   ral_reg_DRAMC_blk_SHU_ACTIM1_0                             -     @5147
+  TRPAB                                        uvm_reg_field                                              ...    RW SHU_ACTIM1_0[3:0]=4'hc (Mirror: 4'ha)
+  TMRWCKEL                                     uvm_reg_field                                              ...    RW SHU_ACTIM1_0[7:4]=4'he (Mirror: 4'h8)
+  TRP                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[11:8]=4'ha (Mirror: 4'h2)
+  TRAS                                         uvm_reg_field                                              ...    RW SHU_ACTIM1_0[21:16]=6'h0e (Mirror: 6'h04)
+  TRC                                          uvm_reg_field                                              ...    RW SHU_ACTIM1_0[28:24]=5'h19 (Mirror: 5'h05)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0xc, SHU_ACTIM1_TRPAB) |
+        P_Fld(0xe, SHU_ACTIM1_TMRWCKEL) | P_Fld(0xa, SHU_ACTIM1_TRP) |
+        P_Fld(0x0e, SHU_ACTIM1_TRAS) | P_Fld(0x19, SHU_ACTIM1_TRC));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM2_0                                   ral_reg_DRAMC_blk_SHU_ACTIM2_0                             -     @5155
+  TXP                                          uvm_reg_field                                              ...    RW SHU_ACTIM2_0[3:0]=4'h3 (Mirror: 4'h0)
+  TMRRI                                        uvm_reg_field                                              ...    RW SHU_ACTIM2_0[8:4]=5'h0f (Mirror: 5'h0e)
+  TRTP                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[14:12]=3'h4 (Mirror: 3'h0)
+  TR2W                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[21:16]=6'h12 (Mirror: 6'h00)
+  TFAW                                         uvm_reg_field                                              ...    RW SHU_ACTIM2_0[28:24]=5'h0d (Mirror: 5'h05)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x3, SHU_ACTIM2_TXP) |
+        P_Fld(0x0f, SHU_ACTIM2_TMRRI) | P_Fld(0x4, SHU_ACTIM2_TRTP) |
+        P_Fld(0x12, SHU_ACTIM2_TR2W) | P_Fld(0x0d, SHU_ACTIM2_TFAW));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM3_0                                   ral_reg_DRAMC_blk_SHU_ACTIM3_0                             -     @5163
+  TRFCPB                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[7:0]=8'h3f (Mirror: 8'h00)
+  MANTMRR                                      uvm_reg_field                                              ...    RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0)
+  TR2MRR                                       uvm_reg_field                                              ...    RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0)
+  TRFC                                         uvm_reg_field                                              ...    RW SHU_ACTIM3_0[23:16]=8'h8a (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x3f, SHU_ACTIM3_TRFCPB) |
+        P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) |
+        P_Fld(0x8a, SHU_ACTIM3_TRFC));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM4_0                                   ral_reg_DRAMC_blk_SHU_ACTIM4_0                             -     @5170
+  TXREFCNT                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[9:0]=10'h09a (Mirror: 10'h028)
+  TMRR2MRW                                     uvm_reg_field                                              ...    RW SHU_ACTIM4_0[15:10]=6'h1b (Mirror: 6'h00)
+  TMRR2W                                       uvm_reg_field                                              ...    RW SHU_ACTIM4_0[21:16]=6'h17 (Mirror: 6'h00)
+  TZQCS                                        uvm_reg_field                                              ...    RW SHU_ACTIM4_0[31:24]=8'h2e (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x09a, SHU_ACTIM4_TXREFCNT) |
+        P_Fld(0x1b, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x17, SHU_ACTIM4_TMRR2W) |
+        P_Fld(0x2e, SHU_ACTIM4_TZQCS));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM5_0                                   ral_reg_DRAMC_blk_SHU_ACTIM5_0                             -     @5177
+  TR2PD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[6:0]=7'h20 (Mirror: 7'h00)
+  TWTPD                                        uvm_reg_field                                              ...    RW SHU_ACTIM5_0[14:8]=7'h23 (Mirror: 7'h00)
+  TPBR2PBR                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[23:16]=8'h30 (Mirror: 8'h00)
+  TPBR2ACT                                     uvm_reg_field                                              ...    RW SHU_ACTIM5_0[29:28]=2'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x20, SHU_ACTIM5_TR2PD) |
+        P_Fld(0x23, SHU_ACTIM5_TWTPD) | P_Fld(0x30, SHU_ACTIM5_TPBR2PBR) |
+        P_Fld(0x0, SHU_ACTIM5_TPBR2ACT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM6_0                                   ral_reg_DRAMC_blk_SHU_ACTIM6_0                             -     @5184
+  TZQLAT2                                      uvm_reg_field                                              ...    RW SHU_ACTIM6_0[4:0]=5'h10 (Mirror: 5'h1f)
+  TMRD                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[11:8]=4'ha (Mirror: 4'h0)
+  TMRW                                         uvm_reg_field                                              ...    RW SHU_ACTIM6_0[15:12]=4'ha (Mirror: 4'h0)
+  TW2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[25:20]=6'h17 (Mirror: 6'h00)
+  TR2MRW                                       uvm_reg_field                                              ...    RW SHU_ACTIM6_0[31:26]=6'h20 (Mirror: 6'h13)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x10, SHU_ACTIM6_TZQLAT2) |
+        P_Fld(0xa, SHU_ACTIM6_TMRD) | P_Fld(0xa, SHU_ACTIM6_TMRW) |
+        P_Fld(0x17, SHU_ACTIM6_TW2MRW) | P_Fld(0x20, SHU_ACTIM6_TR2MRW));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_CKECTRL_0                                  ral_reg_DRAMC_blk_SHU_CKECTRL_0                            -     @5262
+  TPDE_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0)
+  TPDX_05T                                     uvm_reg_field                                              ...    RW SHU_CKECTRL_0[1:1]=1'h0
+  TPDE                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[14:12]=3'h1
+  TPDX                                         uvm_reg_field                                              ...    RW SHU_CKECTRL_0[18:16]=3'h1
+  TCKEPRD                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[22:20]=3'h4 (Mirror: 3'h2)
+  TCKESRX                                      uvm_reg_field                                              ...    RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) |
+        P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) |
+        P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x4, SHU_CKECTRL_TCKEPRD) |
+        P_Fld(0x3, SHU_CKECTRL_TCKESRX));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_0                                     ral_reg_DRAMC_blk_SHU_MISC_0                               -     @5365
+  REQQUE_MAXCNT                                uvm_reg_field                                              ...    RW SHU_MISC_0[3:0]=4'h2
+  DCMDLYREF                                    uvm_reg_field                                              ...    RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4)
+  DAREFEN                                      uvm_reg_field                                              ...    RW SHU_MISC_0[30:30]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) |
+        P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_LP5_CMD_0                                  ral_reg_DRAMC_blk_SHU_LP5_CMD_0                            -     @5427
+  LP5_CMD1TO2EN                                uvm_reg_field                                              ...    RW SHU_LP5_CMD_0[0:0]=1'h0
+  TCSH                                         uvm_reg_field                                              ...    RW SHU_LP5_CMD_0[7:4]=4'h4 (Mirror: 4'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_LP5_CMD, P_Fld(0x0, SHU_LP5_CMD_LP5_CMD1TO2EN) |
+        P_Fld(0x4, SHU_LP5_CMD_TCSH));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIM7_0                                   ral_reg_DRAMC_blk_SHU_ACTIM7_0                             -     @5436
+  TCSH_CSCAL                                   uvm_reg_field                                              ...    RW SHU_ACTIM7_0[3:0]=4'h4 (Mirror: 4'h0)
+  TCACSH                                       uvm_reg_field                                              ...    RW SHU_ACTIM7_0[7:4]=4'h3 (Mirror: 4'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM7, P_Fld(0x4, SHU_ACTIM7_TCSH_CSCAL) |
+        P_Fld(0x3, SHU_ACTIM7_TCACSH));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_WCKCTRL_0                                  ral_reg_DRAMC_blk_SHU_WCKCTRL_0                            -     @5407
+  WCKRDOFF                                     uvm_reg_field                                              ...    RW SHU_WCKCTRL_0[5:0]=6'h13 (Mirror: 6'h00)
+  WCKRDOFF_05T                                 uvm_reg_field                                              ...    RW SHU_WCKCTRL_0[7:7]=1'h0
+  WCKWROFF                                     uvm_reg_field                                              ...    RW SHU_WCKCTRL_0[13:8]=6'h0c (Mirror: 6'h00)
+  WCKWROFF_05T                                 uvm_reg_field                                              ...    RW SHU_WCKCTRL_0[15:15]=1'h0
+  WCKDUAL                                      uvm_reg_field                                              ...    RW SHU_WCKCTRL_0[16:16]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_WCKCTRL, P_Fld(0x13, SHU_WCKCTRL_WCKRDOFF) |
+        P_Fld(0x0, SHU_WCKCTRL_WCKRDOFF_05T) | P_Fld(0x0c, SHU_WCKCTRL_WCKWROFF) |
+        P_Fld(0x0, SHU_WCKCTRL_WCKWROFF_05T) | P_Fld(0x0, SHU_WCKCTRL_WCKDUAL));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MISC_TX_PIPE_CTRL_0                        ral_reg_DDRPHY_blk_SHU_MISC_TX_PIPE_CTRL_0                 -     @12708
+  CMD_TXPIPE_BYPASS_EN                         uvm_reg_field                                              ...    RW SHU_MISC_TX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0)
+  CK_TXPIPE_BYPASS_EN                          uvm_reg_field                                              ...    RW SHU_MISC_TX_PIPE_CTRL_0[1:1]=1'h1 (Mirror: 1'h0)
+  TX_PIPE_BYPASS_EN                            uvm_reg_field                                              ...    RW SHU_MISC_TX_PIPE_CTRL_0[2:2]=1'h0
+  CS_TXPIPE_BYPASS_EN                          uvm_reg_field                                              ...    RW SHU_MISC_TX_PIPE_CTRL_0[3:3]=1'h0
+  SKIP_TXPIPE_BYPASS                           uvm_reg_field                                              ...    RW SHU_MISC_TX_PIPE_CTRL_0[8:8]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_TX_PIPE_CTRL, P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CMD_TXPIPE_BYPASS_EN) |
+        P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CK_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_TX_PIPE_BYPASS_EN) |
+        P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_CS_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_SKIP_TXPIPE_BYPASS));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter.
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit.
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ8_0                            -     @7828
+  R_DMRXDVS_UPD_FORCE_CYC_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000)
+  R_DMRXDVS_UPD_FORCE_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[15:15]=1'h0
+  R_DMRANK_RXDLY_PIPE_CG_IG_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[19:19]=1'h0
+  R_RMRODTEN_CG_IG_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[20:20]=1'h0
+  R_RMRX_TOPHY_CG_IG_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)
+  R_DMRXDVS_RDSEL_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[22:22]=1'h0
+  R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0            uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[23:23]=1'h0
+  R_DMRXDLY_CG_IG_B0                           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)
+  R_DMDQSIEN_FLAG_SYNC_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[26:26]=1'h0
+  R_DMDQSIEN_FLAG_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[27:27]=1'h0
+  R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0               uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[28:28]=1'h0
+  R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[29:29]=1'h0
+  R_DMRANK_PIPE_CG_IG_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[30:30]=1'h0
+  R_DMRANK_CHG_PIPE_CG_IG_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+        P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ8_0                            -     @9231
+  R_DMRXDVS_UPD_FORCE_CYC_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000)
+  R_DMRXDVS_UPD_FORCE_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[15:15]=1'h0
+  R_DMRANK_RXDLY_PIPE_CG_IG_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[19:19]=1'h0
+  R_RMRODTEN_CG_IG_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[20:20]=1'h0
+  R_RMRX_TOPHY_CG_IG_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)
+  R_DMRXDVS_RDSEL_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[22:22]=1'h0
+  R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1            uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[23:23]=1'h0
+  R_DMRXDLY_CG_IG_B1                           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)
+  R_DMDQSIEN_FLAG_SYNC_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[26:26]=1'h0
+  R_DMDQSIEN_FLAG_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[27:27]=1'h0
+  R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1               uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[28:28]=1'h0
+  R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[29:29]=1'h0
+  R_DMRANK_PIPE_CG_IG_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[30:30]=1'h0
+  R_DMRANK_CHG_PIPE_CG_IG_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+        P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ5_0                            -     @7728
+  RG_RX_ARDQ_VREF_SEL_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[5:0]=6'h0e
+  RG_RX_ARDQ_VREF_BYPASS_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[6:6]=1'h0
+  RG_ARPI_FB_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[13:8]=6'h00
+  RG_RX_ARDQS0_DQSIEN_DLY_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[18:16]=3'h0
+  RG_RX_ARDQS_DQSIEN_RB_DLY_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[19:19]=1'h0
+  RG_RX_ARDQS0_DVS_DLY_B0                      uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[23:20]=4'h3 (Mirror: 4'h0)
+  RG_RX_ARDQ_FIFO_DQSI_DLY_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ5_0[31:29]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) |
+        P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) |
+        P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) |
+        P_Fld(0x3, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ5_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ5_0                            -     @9131
+  RG_RX_ARDQ_VREF_SEL_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[5:0]=6'h0e
+  RG_RX_ARDQ_VREF_BYPASS_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[6:6]=1'h0
+  RG_ARPI_FB_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[13:8]=6'h00
+  RG_RX_ARDQS0_DQSIEN_DLY_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[18:16]=3'h0
+  RG_RX_ARDQS_DQSIEN_RB_DLY_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[19:19]=1'h0
+  RG_RX_ARDQS0_DVS_DLY_B1                      uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[23:20]=4'h3 (Mirror: 4'h0)
+  RG_RX_ARDQ_FIFO_DQSI_DLY_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ5_0[31:29]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) |
+        P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) |
+        P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) |
+        P_Fld(0x3, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0                    -     @7490
+  RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h59 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x59, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+        P_Fld(0x59, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x59, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
+        P_Fld(0x59, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0                    -     @7504
+  RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h59 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x59, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+        P_Fld(0x59, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x59, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+        P_Fld(0x59, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0                    -     @7518
+  RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h59 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x59, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+        P_Fld(0x59, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x59, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+        P_Fld(0x59, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0                    -     @7532
+  RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h59 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x59, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+        P_Fld(0x59, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x59, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+        P_Fld(0x59, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0                    -     @7546
+  RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h59 (Mirror: 8'h00)
+  RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h59 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x59, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+        P_Fld(0x59, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0                    -     @7556
+  RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h016 (Mirror: 9'h000)
+  RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h016 (Mirror: 9'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x016, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+        P_Fld(0x016, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1                    -     @7497
+  RX_ARDQ0_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ0_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ1_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ1_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h58 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+        P_Fld(0x58, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x58, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
+        P_Fld(0x58, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1                    -     @7511
+  RX_ARDQ2_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ2_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ3_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ3_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h58 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+        P_Fld(0x58, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x58, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+        P_Fld(0x58, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1                    -     @7525
+  RX_ARDQ4_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ4_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ5_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ5_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h58 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+        P_Fld(0x58, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x58, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+        P_Fld(0x58, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1                    -     @7539
+  RX_ARDQ6_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ6_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ7_R_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ7_F_DLY_B0                            uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h58 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+        P_Fld(0x58, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x58, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+        P_Fld(0x58, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1                    -     @7551
+  RX_ARDQM0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h58 (Mirror: 8'h00)
+  RX_ARDQM0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h58 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+        P_Fld(0x58, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B0_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1                    -     @7561
+  RX_ARDQS0_R_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h015 (Mirror: 9'h000)
+  RX_ARDQS0_F_DLY_B0                           uvm_reg_field                                              ...    RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h015 (Mirror: 9'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x015, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+        P_Fld(0x015, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY0_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0                    -     @8893
+  RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h59 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x59, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+        P_Fld(0x59, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x59, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
+        P_Fld(0x59, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY1_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0                    -     @8907
+  RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h59 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x59, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+        P_Fld(0x59, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x59, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+        P_Fld(0x59, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY2_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0                    -     @8921
+  RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h59 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x59, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+        P_Fld(0x59, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x59, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+        P_Fld(0x59, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY3_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0                    -     @8935
+  RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h59 (Mirror: 8'h00)
+  RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h59 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x59, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+        P_Fld(0x59, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x59, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+        P_Fld(0x59, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY4_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0                    -     @8949
+  RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h59 (Mirror: 8'h00)
+  RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h59 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x59, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+        P_Fld(0x59, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY5_0_0                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0                    -     @8959
+  RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h016 (Mirror: 9'h000)
+  RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h016 (Mirror: 9'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x016, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+        P_Fld(0x016, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY0_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1                    -     @8900
+  RX_ARDQ0_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ0_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ1_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ1_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h58 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+        P_Fld(0x58, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x58, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
+        P_Fld(0x58, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY1_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1                    -     @8914
+  RX_ARDQ2_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ2_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ3_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ3_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h58 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+        P_Fld(0x58, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x58, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+        P_Fld(0x58, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY2_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1                    -     @8928
+  RX_ARDQ4_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ4_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ5_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ5_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h58 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+        P_Fld(0x58, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x58, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+        P_Fld(0x58, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY3_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1                    -     @8942
+  RX_ARDQ6_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ6_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ7_R_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h58 (Mirror: 8'h00)
+  RX_ARDQ7_F_DLY_B1                            uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h58 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+        P_Fld(0x58, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x58, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+        P_Fld(0x58, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY4_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1                    -     @8954
+  RX_ARDQM0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h58 (Mirror: 8'h00)
+  RX_ARDQM0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h58 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+        P_Fld(0x58, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_R0_B1_RXDLY5_0_1                           ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1                    -     @8964
+  RX_ARDQS0_R_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h015 (Mirror: 9'h000)
+  RX_ARDQS0_F_DLY_B1                           uvm_reg_field                                              ...    RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h015 (Mirror: 9'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x015, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+        P_Fld(0x015, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B0_DQ9                                         ral_reg_DDRPHY_blk_B0_DQ9                                  -     @7384
+  RG_RX_ARDQ_STBEN_RESETB_B0                   uvm_reg_field                                              ...    RW B0_DQ9[0:0]=1'h0 (Mirror: 1'h1)
+  RG_RX_ARDQS0_STBEN_RESETB_B0                 uvm_reg_field                                              ...    RW B0_DQ9[4:4]=1'h1
+  RG_RX_ARDQS0_DQSIENMODE_B0                   uvm_reg_field                                              ...    RW B0_DQ9[5:5]=1'h0
+  R_DMRXDVS_R_F_DLY_RK_OPT_B0                  uvm_reg_field                                              ...    RW B0_DQ9[6:6]=1'h1
+  R_DMRXFIFO_STBENCMP_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ9[7:7]=1'h0
+  R_IN_GATE_EN_LOW_OPT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[15:8]=8'h00
+  R_DMDQSIEN_VALID_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[18:16]=3'h0
+  R_DMDQSIEN_RDSEL_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[22:20]=3'h0
+  R_DMRXDVS_VALID_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[26:24]=3'h0
+  R_DMRXDVS_RDSEL_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[30:28]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
+        P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
+        P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
+        P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
+        P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
+        P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B1_DQ9                                         ral_reg_DDRPHY_blk_B1_DQ9                                  -     @8787
+  RG_RX_ARDQ_STBEN_RESETB_B1                   uvm_reg_field                                              ...    RW B1_DQ9[0:0]=1'h0 (Mirror: 1'h1)
+  RG_RX_ARDQS0_STBEN_RESETB_B1                 uvm_reg_field                                              ...    RW B1_DQ9[4:4]=1'h1
+  RG_RX_ARDQS0_DQSIENMODE_B1                   uvm_reg_field                                              ...    RW B1_DQ9[5:5]=1'h0
+  R_DMRXDVS_R_F_DLY_RK_OPT_B1                  uvm_reg_field                                              ...    RW B1_DQ9[6:6]=1'h1
+  R_DMRXFIFO_STBENCMP_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ9[7:7]=1'h0
+  R_IN_GATE_EN_LOW_OPT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[15:8]=8'h00
+  R_DMDQSIEN_VALID_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[18:16]=3'h0
+  R_DMDQSIEN_RDSEL_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[22:20]=3'h0
+  R_DMRXDVS_VALID_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[26:24]=3'h0
+  R_DMRXDVS_RDSEL_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[30:28]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
+        P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
+        P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
+        P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
+        P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
+        P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B0_DQ9                                         ral_reg_DDRPHY_blk_B0_DQ9                                  -     @7384
+  RG_RX_ARDQ_STBEN_RESETB_B0                   uvm_reg_field                                              ...    RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0)
+  RG_RX_ARDQS0_STBEN_RESETB_B0                 uvm_reg_field                                              ...    RW B0_DQ9[4:4]=1'h1
+  RG_RX_ARDQS0_DQSIENMODE_B0                   uvm_reg_field                                              ...    RW B0_DQ9[5:5]=1'h0
+  R_DMRXDVS_R_F_DLY_RK_OPT_B0                  uvm_reg_field                                              ...    RW B0_DQ9[6:6]=1'h1
+  R_DMRXFIFO_STBENCMP_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ9[7:7]=1'h0
+  R_IN_GATE_EN_LOW_OPT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[15:8]=8'h00
+  R_DMDQSIEN_VALID_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[18:16]=3'h0
+  R_DMDQSIEN_RDSEL_LAT_B0                      uvm_reg_field                                              ...    RW B0_DQ9[22:20]=3'h0
+  R_DMRXDVS_VALID_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[26:24]=3'h0
+  R_DMRXDVS_RDSEL_LAT_B0                       uvm_reg_field                                              ...    RW B0_DQ9[30:28]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
+        P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
+        P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
+        P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
+        P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
+        P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B1_DQ9                                         ral_reg_DDRPHY_blk_B1_DQ9                                  -     @8787
+  RG_RX_ARDQ_STBEN_RESETB_B1                   uvm_reg_field                                              ...    RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0)
+  RG_RX_ARDQS0_STBEN_RESETB_B1                 uvm_reg_field                                              ...    RW B1_DQ9[4:4]=1'h1
+  RG_RX_ARDQS0_DQSIENMODE_B1                   uvm_reg_field                                              ...    RW B1_DQ9[5:5]=1'h0
+  R_DMRXDVS_R_F_DLY_RK_OPT_B1                  uvm_reg_field                                              ...    RW B1_DQ9[6:6]=1'h1
+  R_DMRXFIFO_STBENCMP_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ9[7:7]=1'h0
+  R_IN_GATE_EN_LOW_OPT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[15:8]=8'h00
+  R_DMDQSIEN_VALID_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[18:16]=3'h0
+  R_DMDQSIEN_RDSEL_LAT_B1                      uvm_reg_field                                              ...    RW B1_DQ9[22:20]=3'h0
+  R_DMRXDVS_VALID_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[26:24]=3'h0
+  R_DMRXDVS_RDSEL_LAT_B1                       uvm_reg_field                                              ...    RW B1_DQ9[30:28]=3'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
+        P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
+        P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
+        P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
+        P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
+        P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B0_DQ4                                         ral_reg_DDRPHY_blk_B0_DQ4                                  -     @7313
+  RG_RX_ARDQS_EYE_R_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[6:0]=7'h5f (Mirror: 7'h00)
+  RG_RX_ARDQS_EYE_F_DLY_B0                     uvm_reg_field                                              ...    RW B0_DQ4[14:8]=7'h5f (Mirror: 7'h00)
+  RG_RX_ARDQ_EYE_R_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[21:16]=6'h19 (Mirror: 6'h00)
+  RG_RX_ARDQ_EYE_F_DLY_B0                      uvm_reg_field                                              ...    RW B0_DQ4[29:24]=6'h19 (Mirror: 6'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x5f, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) |
+        P_Fld(0x5f, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x19, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) |
+        P_Fld(0x19, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B1_DQ4                                         ral_reg_DDRPHY_blk_B1_DQ4                                  -     @8716
+  RG_RX_ARDQS_EYE_R_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[6:0]=7'h5f (Mirror: 7'h00)
+  RG_RX_ARDQS_EYE_F_DLY_B1                     uvm_reg_field                                              ...    RW B1_DQ4[14:8]=7'h5f (Mirror: 7'h00)
+  RG_RX_ARDQ_EYE_R_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[21:16]=6'h19 (Mirror: 6'h00)
+  RG_RX_ARDQ_EYE_F_DLY_B1                      uvm_reg_field                                              ...    RW B1_DQ4[29:24]=6'h19 (Mirror: 6'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x5f, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) |
+        P_Fld(0x5f, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x19, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) |
+        P_Fld(0x19, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B0_DQ5                                         ral_reg_DDRPHY_blk_B0_DQ5                                  -     @7320
+  RG_RX_ARDQ_EYE_VREF_SEL_B0                   uvm_reg_field                                              ...    RW B0_DQ5[13:8]=6'h10
+  RG_RX_ARDQ_VREF_EN_B0                        uvm_reg_field                                              ...    RW B0_DQ5[16:16]=1'h1
+  RG_RX_ARDQ_EYE_VREF_EN_B0                    uvm_reg_field                                              ...    RW B0_DQ5[17:17]=1'h1
+  RG_RX_ARDQ_EYE_SEL_B0                        uvm_reg_field                                              ...    RW B0_DQ5[23:20]=4'h0
+  RG_RX_ARDQ_EYE_EN_B0                         uvm_reg_field                                              ...    RW B0_DQ5[24:24]=1'h1
+  RG_RX_ARDQ_EYE_STBEN_RESETB_B0               uvm_reg_field                                              ...    RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0)
+  RG_RX_ARDQS0_DVS_EN_B0                       uvm_reg_field                                              ...    RW B0_DQ5[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x10, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) |
+        P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) |
+        P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) |
+        P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+B1_DQ5                                         ral_reg_DDRPHY_blk_B1_DQ5                                  -     @8723
+  RG_RX_ARDQ_EYE_VREF_SEL_B1                   uvm_reg_field                                              ...    RW B1_DQ5[13:8]=6'h10
+  RG_RX_ARDQ_VREF_EN_B1                        uvm_reg_field                                              ...    RW B1_DQ5[16:16]=1'h1
+  RG_RX_ARDQ_EYE_VREF_EN_B1                    uvm_reg_field                                              ...    RW B1_DQ5[17:17]=1'h1
+  RG_RX_ARDQ_EYE_SEL_B1                        uvm_reg_field                                              ...    RW B1_DQ5[23:20]=4'h0
+  RG_RX_ARDQ_EYE_EN_B1                         uvm_reg_field                                              ...    RW B1_DQ5[24:24]=1'h1
+  RG_RX_ARDQ_EYE_STBEN_RESETB_B1               uvm_reg_field                                              ...    RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0)
+  RG_RX_ARDQS0_DVS_EN_B1                       uvm_reg_field                                              ...    RW B1_DQ5[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x10, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) |
+        P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) |
+        P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) |
+        P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Enter
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_COMMON0_0                                  ral_reg_DRAMC_blk_SHU_COMMON0_0                            -     @5001
+  FREQDIV4                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[0:0]=1'h1 (Mirror: 1'h0)
+  FDIV2                                        uvm_reg_field                                              ...    RW SHU_COMMON0_0[1:1]=1'h0
+  FREQDIV8                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[2:2]=1'h0
+  DM64BITEN                                    uvm_reg_field                                              ...    RW SHU_COMMON0_0[4:4]=1'h1 (Mirror: 1'h0)
+  DLE256EN                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[5:5]=1'h0
+  LP5BGEN                                      uvm_reg_field                                              ...    RW SHU_COMMON0_0[6:6]=1'h1 (Mirror: 1'h0)
+  LP5WCKON                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[7:7]=1'h1 (Mirror: 1'h0)
+  CL2                                          uvm_reg_field                                              ...    RW SHU_COMMON0_0[8:8]=1'h0
+  BL2                                          uvm_reg_field                                              ...    RW SHU_COMMON0_0[9:9]=1'h0
+  BL4                                          uvm_reg_field                                              ...    RW SHU_COMMON0_0[10:10]=1'h1 (Mirror: 1'h0)
+  LP5BGOTF                                     uvm_reg_field                                              ...    RW SHU_COMMON0_0[11:11]=1'h0
+  BC4OTF                                       uvm_reg_field                                              ...    RW SHU_COMMON0_0[12:12]=1'h1
+  LP5HEFF_MODE                                 uvm_reg_field                                              ...    RW SHU_COMMON0_0[13:13]=1'h1 (Mirror: 1'h0)
+  SHU_COMMON0_RSV                              uvm_reg_field                                              ...    RW SHU_COMMON0_0[31:15]=17'h00000
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0, P_Fld(0x1, SHU_COMMON0_FREQDIV4) |
+        P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x0, SHU_COMMON0_FREQDIV8) |
+        P_Fld(0x1, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) |
+        P_Fld(0x1, SHU_COMMON0_LP5BGEN) | P_Fld(0x1, SHU_COMMON0_LP5WCKON) |
+        P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) |
+        P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) |
+        P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x1, SHU_COMMON0_LP5HEFF_MODE) |
+        P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_LP5_CMD_0                                  ral_reg_DRAMC_blk_SHU_LP5_CMD_0                            -     @5427
+  LP5_CMD1TO2EN                                uvm_reg_field                                              ...    RW SHU_LP5_CMD_0[0:0]=1'h1 (Mirror: 1'h0)
+  TCSH                                         uvm_reg_field                                              ...    RW SHU_LP5_CMD_0[7:4]=4'h4
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_LP5_CMD, P_Fld(0x1, SHU_LP5_CMD_LP5_CMD1TO2EN) |
+        P_Fld(0x4, SHU_LP5_CMD_TCSH));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ACTIMING_CONF_0                            ral_reg_DRAMC_blk_SHU_ACTIMING_CONF_0                      -     @5255
+  SCINTV                                       uvm_reg_field                                              ...    RW SHU_ACTIMING_CONF_0[5:0]=6'h26 (Mirror: 6'h2a)
+  TRFCPBIG                                     uvm_reg_field                                              ...    RW SHU_ACTIMING_CONF_0[8:8]=1'h0
+  REFBW_FR                                     uvm_reg_field                                              ...    RW SHU_ACTIMING_CONF_0[25:16]=10'h000
+  TREFBWIG                                     uvm_reg_field                                              ...    RW SHU_ACTIMING_CONF_0[31:31]=1'h1 (Mirror: 1'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF, P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) |
+        P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) |
+        P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_DCM_CTRL0_0                                ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0                          -     @5027
+  DDRPHY_CLK_EN_OPT                            uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[7:7]=1'h1
+  DPHY_CMDDCM_EXTCNT                           uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[11:8]=4'h4
+  DDRPHY_CLK_DYN_GATING_SEL                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[15:12]=4'h5
+  CKE_EXTNONPD_CNT                             uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[19:16]=4'h0
+  FASTWAKE2                                    uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[29:29]=1'h1 (Mirror: 1'h0)
+  FASTWAKE                                     uvm_reg_field                                              ...    RW SHU_DCM_CTRL0_0[31:31]=1'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+        P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+        P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) |
+        P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_CONF0_0                                    ral_reg_DRAMC_blk_SHU_CONF0_0                              -     @5356
+  DMPGTIM                                      uvm_reg_field                                              ...    RW SHU_CONF0_0[5:0]=6'h3f (Mirror: 6'h08)
+  ADVREFEN                                     uvm_reg_field                                              ...    RW SHU_CONF0_0[6:6]=1'h0
+  ADVPREEN                                     uvm_reg_field                                              ...    RW SHU_CONF0_0[7:7]=1'h1 (Mirror: 1'h0)
+  PBREFEN                                      uvm_reg_field                                              ...    RW SHU_CONF0_0[8:8]=1'h1 (Mirror: 1'h0)
+  REFTHD                                       uvm_reg_field                                              ...    RW SHU_CONF0_0[15:12]=4'h1 (Mirror: 4'h0)
+  REQQUE_DEPTH                                 uvm_reg_field                                              ...    RW SHU_CONF0_0[19:16]=4'h8
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x3f, SHU_CONF0_DMPGTIM) |
+        P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) |
+        P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) |
+        P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_MATYPE_0                                   ral_reg_DRAMC_blk_SHU_MATYPE_0                             -     @4996
+  MATYPE                                       uvm_reg_field                                              ...    RW SHU_MATYPE_0[1:0]=2'h2 (Mirror: 2'h0)
+  NORMPOP_LEN                                  uvm_reg_field                                              ...    RW SHU_MATYPE_0[6:4]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE, P_Fld(0x2, SHU_MATYPE_MATYPE) |
+        P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+TX_SET0                                        ral_reg_DRAMC_blk_TX_SET0                                  -     @3899
+  TXRANK                                       uvm_reg_field                                              ...    RW TX_SET0[1:0]=2'h0
+  TXRANKFIX                                    uvm_reg_field                                              ...    RW TX_SET0[2:2]=1'h0
+  DDRPHY_COMB_CG_SEL                           uvm_reg_field                                              ...    RW TX_SET0[3:3]=1'h0
+  TX_DQM_DEFAULT                               uvm_reg_field                                              ...    RW TX_SET0[4:4]=1'h1
+  DQBUS_X32                                    uvm_reg_field                                              ...    RW TX_SET0[5:5]=1'h0
+  OE_DOWNGRADE                                 uvm_reg_field                                              ...    RW TX_SET0[6:6]=1'h0
+  DQ16COM1                                     uvm_reg_field                                              ...    RW TX_SET0[21:21]=1'h0
+  WPRE2T                                       uvm_reg_field                                              ...    RW TX_SET0[22:22]=1'h1 (Mirror: 1'h0)
+  DRSCLR_EN                                    uvm_reg_field                                              ...    RW TX_SET0[24:24]=1'h0
+  DRSCLR_RK0_EN                                uvm_reg_field                                              ...    RW TX_SET0[25:25]=1'h0
+  ARPI_CAL_E2OPT                               uvm_reg_field                                              ...    RW TX_SET0[26:26]=1'h0
+  TX_DLY_CAL_E2OPT                             uvm_reg_field                                              ...    RW TX_SET0[27:27]=1'h0
+  DQS_OE_OP1_DIS                               uvm_reg_field                                              ...    RW TX_SET0[28:28]=1'h0
+  DQS_OE_OP2_EN                                uvm_reg_field                                              ...    RW TX_SET0[29:29]=1'h0
+  RK_SCINPUT_OPT                               uvm_reg_field                                              ...    RW TX_SET0[30:30]=1'h0
+  DRAMOEN                                      uvm_reg_field                                              ...    RW TX_SET0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_TX_SET0, P_Fld(0x0, TX_SET0_TXRANK) |
+        P_Fld(0x0, TX_SET0_TXRANKFIX) | P_Fld(0x0, TX_SET0_DDRPHY_COMB_CG_SEL) |
+        P_Fld(0x1, TX_SET0_TX_DQM_DEFAULT) | P_Fld(0x0, TX_SET0_DQBUS_X32) |
+        P_Fld(0x0, TX_SET0_OE_DOWNGRADE) | P_Fld(0x0, TX_SET0_DQ16COM1) |
+        P_Fld(0x1, TX_SET0_WPRE2T) | P_Fld(0x0, TX_SET0_DRSCLR_EN) |
+        P_Fld(0x0, TX_SET0_DRSCLR_RK0_EN) | P_Fld(0x0, TX_SET0_ARPI_CAL_E2OPT) |
+        P_Fld(0x0, TX_SET0_TX_DLY_CAL_E2OPT) | P_Fld(0x0, TX_SET0_DQS_OE_OP1_DIS) |
+        P_Fld(0x0, TX_SET0_DQS_OE_OP2_EN) | P_Fld(0x0, TX_SET0_RK_SCINPUT_OPT) |
+        P_Fld(0x0, TX_SET0_DRAMOEN));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_TX_SET0_0                                  ral_reg_DRAMC_blk_SHU_TX_SET0_0                            -     @5306
+  DQOE_CNT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[3:0]=4'h0
+  DQOE_OPT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[4:4]=1'h0
+  TXUPD_SEL                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[7:6]=2'h0
+  TXUPD_W2R_SEL                                uvm_reg_field                                              ...    RW SHU_TX_SET0_0[10:8]=3'h2 (Mirror: 3'h0)
+  WECC_EN                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[11:11]=1'h0
+  DBIWR                                        uvm_reg_field                                              ...    RW SHU_TX_SET0_0[12:12]=1'h0
+  WDATRGO                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[13:13]=1'h0
+  TWPSTEXT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[14:14]=1'h0
+  WPST1P5T                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[15:15]=1'h1 (Mirror: 1'h0)
+  TXOEN_AUTOSET_OFFSET                         uvm_reg_field                                              ...    RW SHU_TX_SET0_0[19:16]=4'h3
+  TWCKPST                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[21:20]=2'h1
+  OE_EXT2UI                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[24:22]=3'h1 (Mirror: 3'h0)
+  DQS2DQ_FILT_PITHRD                           uvm_reg_field                                              ...    RW SHU_TX_SET0_0[30:25]=6'h0e
+  TXOEN_AUTOSET_EN                             uvm_reg_field                                              ...    RW SHU_TX_SET0_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+        P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+        P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+        P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+        P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
+        P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+        P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+        P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_STBCAL1_0                             ral_reg_DDRPHY_blk_MISC_SHU_STBCAL1_0                      -     @12514
+  DLLFRZRFCOPT                                 uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[1:0]=2'h0
+  DLLFRZWROPT                                  uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[5:4]=2'h0
+  r_rstbcnt_latch_opt                          uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[10:8]=3'h0
+  STB_UPDMASK_EN                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[11:11]=1'h1 (Mirror: 1'h0)
+  STB_UPDMASKCYC                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[15:12]=4'h9 (Mirror: 4'h0)
+  DQSINCTL_PRE_SEL                             uvm_reg_field                                              ...    RW MISC_SHU_STBCAL1_0[16:16]=1'h1 (Mirror: 1'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1, P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) |
+        P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) |
+        P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) |
+        P_Fld(0x1, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_STBCAL_0                              ral_reg_DDRPHY_blk_MISC_SHU_STBCAL_0                       -     @12499
+  DMSTBLAT                                     uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[3:0]=4'h2 (Mirror: 4'h0)
+  PICGLAT                                      uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[6:4]=3'h1 (Mirror: 3'h0)
+  DQSG_MODE                                    uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[8:8]=1'h1 (Mirror: 1'h0)
+  DQSIEN_PICG_MODE                             uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[9:9]=1'h1 (Mirror: 1'h0)
+  DQSIEN_DQSSTB_MODE                           uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[13:12]=2'h2 (Mirror: 2'h1)
+  DQSIEN_BURST_MODE                            uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[14:14]=1'h1
+  DQSIEN_SELPH_FRUN                            uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[15:15]=1'h0
+  STBCALEN                                     uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[16:16]=1'h1 (Mirror: 1'h0)
+  STB_SELPHCALEN                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[17:17]=1'h1 (Mirror: 1'h0)
+  DQSIEN_4TO1_EN                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[20:20]=1'h0
+  DQSIEN_8TO1_EN                               uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[21:21]=1'h0
+  DQSIEN_16TO1_EN                              uvm_reg_field                                              ...    RW MISC_SHU_STBCAL_0[22:22]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL, P_Fld(0x2, MISC_SHU_STBCAL_DMSTBLAT) |
+        P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) |
+        P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x2, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) |
+        P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) |
+        P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) |
+        P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) |
+        P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RODTENSTB_0                           ral_reg_DDRPHY_blk_MISC_SHU_RODTENSTB_0                    -     @12562
+  RODTENSTB_TRACK_EN                           uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[0:0]=1'h1 (Mirror: 1'h0)
+  RODTEN_P1_ENABLE                             uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[1:1]=1'h0
+  RODTENSTB_4BYTE_EN                           uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[2:2]=1'h0
+  RODTENSTB_TRACK_UDFLWCTRL                    uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[3:3]=1'h1 (Mirror: 1'h0)
+  RODTENSTB_SELPH_MODE                         uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[4:4]=1'h1
+  RODTENSTB_SELPH_BY_BITTIME                   uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[5:5]=1'h0
+  RODTENSTB__UI_OFFSET                         uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[11:8]=4'h4 (Mirror: 4'h0)
+  RODTENSTB_MCK_OFFSET                         uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[15:12]=4'h0
+  RODTENSTB_EXT                                uvm_reg_field                                              ...    RW MISC_SHU_RODTENSTB_0[31:16]=16'h0008 (Mirror: 16'h0000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) |
+        P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) |
+        P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) |
+        P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x4, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) |
+        P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_RX_SELPH_MODE_0                       ral_reg_DDRPHY_blk_MISC_SHU_RX_SELPH_MODE_0                -     @12751
+  DQSIEN_SELPH_SERMODE                         uvm_reg_field                                              ...    RW MISC_SHU_RX_SELPH_MODE_0[1:0]=2'h2 (Mirror: 2'h0)
+  RODT_SELPH_SERMODE                           uvm_reg_field                                              ...    RW MISC_SHU_RX_SELPH_MODE_0[5:4]=2'h1 (Mirror: 2'h0)
+  RANK_SELPH_SERMODE                           uvm_reg_field                                              ...    RW MISC_SHU_RX_SELPH_MODE_0[7:6]=2'h1 (Mirror: 2'h0)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE, P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) |
+        P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Exit
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Enter
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ7_0                            -     @7808
+  R_DMRANKRXDVS_B0                             uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[3:0]=4'h0
+  R_DMDQMDBI_EYE_SHU_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[6:6]=1'h1 (Mirror: 1'h0)
+  R_DMDQMDBI_SHU_B0                            uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[7:7]=1'h1 (Mirror: 1'h0)
+  R_DMRXDVS_DQM_FLAGSEL_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[11:8]=4'h0
+  R_DMRXDVS_PBYTE_FLAG_OPT_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[12:12]=1'h0
+  R_DMRXDVS_PBYTE_DQM_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[13:13]=1'h0
+  R_DMRXTRACK_DQM_EN_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[14:14]=1'h0
+  R_DMRODTEN_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[15:15]=1'h1
+  R_DMARPI_CG_FB2DLL_DCM_EN_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[16:16]=1'h0
+  R_DMTX_ARPI_CG_DQ_NEW_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[17:17]=1'h0
+  R_DMTX_ARPI_CG_DQS_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[18:18]=1'h0
+  R_DMTX_ARPI_CG_DQM_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[19:19]=1'h0
+  R_LP4Y_SDN_MODE_DQS0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[20:20]=1'h0
+  R_DMRXRANK_DQ_EN_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[24:24]=1'h1
+  R_DMRXRANK_DQ_LAT_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[27:25]=3'h2
+  R_DMRXRANK_DQS_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[28:28]=1'h1
+  R_DMRXRANK_DQS_LAT_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[31:29]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ7_0                            -     @9211
+  R_DMRANKRXDVS_B1                             uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[3:0]=4'h0
+  R_DMDQMDBI_EYE_SHU_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[6:6]=1'h1 (Mirror: 1'h0)
+  R_DMDQMDBI_SHU_B1                            uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[7:7]=1'h1 (Mirror: 1'h0)
+  R_DMRXDVS_DQM_FLAGSEL_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[11:8]=4'h0
+  R_DMRXDVS_PBYTE_FLAG_OPT_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[12:12]=1'h0
+  R_DMRXDVS_PBYTE_DQM_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[13:13]=1'h0
+  R_DMRXTRACK_DQM_EN_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[14:14]=1'h0
+  R_DMRODTEN_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[15:15]=1'h1
+  R_DMARPI_CG_FB2DLL_DCM_EN_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[16:16]=1'h0
+  R_DMTX_ARPI_CG_DQ_NEW_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[17:17]=1'h0
+  R_DMTX_ARPI_CG_DQS_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[18:18]=1'h0
+  R_DMTX_ARPI_CG_DQM_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[19:19]=1'h0
+  R_LP4Y_SDN_MODE_DQS1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[20:20]=1'h0
+  R_DMRXRANK_DQ_EN_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[24:24]=1'h1
+  R_DMRXRANK_DQ_LAT_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[27:25]=3'h2
+  R_DMRXRANK_DQS_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[28:28]=1'h1
+  R_DMRXRANK_DQS_LAT_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[31:29]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_TX_SET0_0                                  ral_reg_DRAMC_blk_SHU_TX_SET0_0                            -     @5306
+  DQOE_CNT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[3:0]=4'h0
+  DQOE_OPT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[4:4]=1'h0
+  TXUPD_SEL                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[7:6]=2'h0
+  TXUPD_W2R_SEL                                uvm_reg_field                                              ...    RW SHU_TX_SET0_0[10:8]=3'h2
+  WECC_EN                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[11:11]=1'h0
+  DBIWR                                        uvm_reg_field                                              ...    RW SHU_TX_SET0_0[12:12]=1'h1 (Mirror: 1'h0)
+  WDATRGO                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[13:13]=1'h0
+  TWPSTEXT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[14:14]=1'h0
+  WPST1P5T                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[15:15]=1'h1
+  TXOEN_AUTOSET_OFFSET                         uvm_reg_field                                              ...    RW SHU_TX_SET0_0[19:16]=4'h3
+  TWCKPST                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[21:20]=2'h1
+  OE_EXT2UI                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[24:22]=3'h1
+  DQS2DQ_FILT_PITHRD                           uvm_reg_field                                              ...    RW SHU_TX_SET0_0[30:25]=6'h0e
+  TXOEN_AUTOSET_EN                             uvm_reg_field                                              ...    RW SHU_TX_SET0_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+        P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+        P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+        P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+        P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
+        P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+        P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+        P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Exit
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Enter
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_HWSET_MR2_0                                ral_reg_DRAMC_blk_SHU_HWSET_MR2_0                          -     @5122
+  HWSET_MR2_MRSMA                              uvm_reg_field                                              ...    RW SHU_HWSET_MR2_0[12:0]=13'h0002
+  HWSET_MR2_OP                                 uvm_reg_field                                              ...    RW SHU_HWSET_MR2_0[23:16]=8'h3f (Mirror: 8'h12)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR2, P_Fld(0x0002, SHU_HWSET_MR2_HWSET_MR2_MRSMA) |
+        P_Fld(0x3f, SHU_HWSET_MR2_HWSET_MR2_OP));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Exit
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Enter
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_FREQ_RATIO_SET0_0                          ral_reg_DRAMC_blk_SHU_FREQ_RATIO_SET0_0                    -     @5384
+  tDQSCK_JUMP_RATIO3                           uvm_reg_field                                              ...    RW SHU_FREQ_RATIO_SET0_0[7:0]=8'h20 (Mirror: 8'h00)
+  tDQSCK_JUMP_RATIO2                           uvm_reg_field                                              ...    RW SHU_FREQ_RATIO_SET0_0[15:8]=8'h72 (Mirror: 8'h00)
+  tDQSCK_JUMP_RATIO1                           uvm_reg_field                                              ...    RW SHU_FREQ_RATIO_SET0_0[23:16]=8'h09 (Mirror: 8'h00)
+  tDQSCK_JUMP_RATIO0                           uvm_reg_field                                              ...    RW SHU_FREQ_RATIO_SET0_0[31:24]=8'h20 (Mirror: 8'h00)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) |
+        P_Fld(0x72, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x09, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) |
+        P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Exit
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Enter
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+MISC_SHU_DVFSDLL_0                             ral_reg_DDRPHY_blk_MISC_SHU_DVFSDLL_0                      -     @12523
+  r_bypass_1st_dll                             uvm_reg_field                                              ...    RW MISC_SHU_DVFSDLL_0[0:0]=1'h0
+  r_bypass_2nd_dll                             uvm_reg_field                                              ...    RW MISC_SHU_DVFSDLL_0[1:1]=1'h0
+  r_dll_idle                                   uvm_reg_field                                              ...    RW MISC_SHU_DVFSDLL_0[10:4]=7'h5a (Mirror: 7'h46)
+  r_2nd_dll_idle                               uvm_reg_field                                              ...    RW MISC_SHU_DVFSDLL_0[22:16]=7'h5a
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) |
+        P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) |
+        P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE));
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Exit
+    mcDELAY_US(1);
+
+    mcDELAY_US(1);
+
+/*TINFO=---===BROADCAST OFF!===---*/
+     DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Enter
+    mcDELAY_US(1);
+
+    mcDELAY_US(1);
+
+/*TINFO=---===BROADCAST ON!===---*/
+     DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+//    ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Exit
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_DQSOSCR_0                                  ral_reg_DRAMC_blk_SHU_DQSOSCR_0                            -     @5338
+  DQSOSCRCNT                                   uvm_reg_field                                              ...    RW SHU_DQSOSCR_0[7:0]=8'h15 (Mirror: 8'h00)
+  DQSOSC_ADV_SEL                               uvm_reg_field                                              ...    RW SHU_DQSOSCR_0[9:8]=2'h0
+  DQSOSC_DRS_ADV_SEL                           uvm_reg_field                                              ...    RW SHU_DQSOSCR_0[11:10]=2'h0
+  DQSOSC_DELTA                                 uvm_reg_field                                              ...    RW SHU_DQSOSCR_0[31:16]=16'hffff
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR, P_Fld(0x15, SHU_DQSOSCR_DQSOSCRCNT) |
+        P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) |
+        P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_DQSOSC_SET0_0                              ral_reg_DRAMC_blk_SHU_DQSOSC_SET0_0                        -     @5332
+  DQSOSCENDIS                                  uvm_reg_field                                              ...    RW SHU_DQSOSC_SET0_0[0:0]=1'h1
+  DQSOSC_PRDCNT                                uvm_reg_field                                              ...    RW SHU_DQSOSC_SET0_0[13:4]=10'h012 (Mirror: 10'h00f)
+  DQSOSCENCNT                                  uvm_reg_field                                              ...    RW SHU_DQSOSC_SET0_0[31:16]=16'h0002
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0, P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) |
+        P_Fld(0x012, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQSOSC_0_0                               ral_reg_DRAMC_blk_SHURK_DQSOSC_0_0                         -     @4906
+  DQSOSC_BASE_RK0                              uvm_reg_field                                              ...    RW SHURK_DQSOSC_0_0[15:0]=16'h025c (Mirror: 16'h0000)
+  DQSOSC_BASE_RK0_B1                           uvm_reg_field                                              ...    RW SHURK_DQSOSC_0_0[31:16]=16'h025c (Mirror: 16'h0000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC, P_Fld(0x025c, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
+        P_Fld(0x025c, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQSOSC_0_1                               ral_reg_DRAMC_blk_SHURK_DQSOSC_0_1                         -     @4911
+  DQSOSC_BASE_RK0                              uvm_reg_field                                              ...    RW SHURK_DQSOSC_0_1[15:0]=16'h0159 (Mirror: 16'h0000)
+  DQSOSC_BASE_RK0_B1                           uvm_reg_field                                              ...    RW SHURK_DQSOSC_0_1[31:16]=16'h0159 (Mirror: 16'h0000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0159, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
+        P_Fld(0x0159, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQSOSC_THRD_0_0                          ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_0                    -     @4916
+  DQSOSCTHRD_INC                               uvm_reg_field                                              ...    RW SHURK_DQSOSC_THRD_0_0[11:0]=12'h00d (Mirror: 12'h001)
+  DQSOSCTHRD_DEC                               uvm_reg_field                                              ...    RW SHURK_DQSOSC_THRD_0_0[27:16]=12'h009 (Mirror: 12'h001)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD, P_Fld(0x00d, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
+        P_Fld(0x009, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHURK_DQSOSC_THRD_0_1                          ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_1                    -     @4921
+  DQSOSCTHRD_INC                               uvm_reg_field                                              ...    RW SHURK_DQSOSC_THRD_0_1[11:0]=12'h004 (Mirror: 12'h001)
+  DQSOSCTHRD_DEC                               uvm_reg_field                                              ...    RW SHURK_DQSOSC_THRD_0_1[27:16]=12'h002 (Mirror: 12'h001)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x004, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
+        P_Fld(0x002, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_TX_SET0_0                                  ral_reg_DRAMC_blk_SHU_TX_SET0_0                            -     @5306
+  DQOE_CNT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[3:0]=4'h0
+  DQOE_OPT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[4:4]=1'h0
+  TXUPD_SEL                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[7:6]=2'h0
+  TXUPD_W2R_SEL                                uvm_reg_field                                              ...    RW SHU_TX_SET0_0[10:8]=3'h2
+  WECC_EN                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[11:11]=1'h0
+  DBIWR                                        uvm_reg_field                                              ...    RW SHU_TX_SET0_0[12:12]=1'h1
+  WDATRGO                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[13:13]=1'h0
+  TWPSTEXT                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[14:14]=1'h0
+  WPST1P5T                                     uvm_reg_field                                              ...    RW SHU_TX_SET0_0[15:15]=1'h1
+  TXOEN_AUTOSET_OFFSET                         uvm_reg_field                                              ...    RW SHU_TX_SET0_0[19:16]=4'h3
+  TWCKPST                                      uvm_reg_field                                              ...    RW SHU_TX_SET0_0[21:20]=2'h1
+  OE_EXT2UI                                    uvm_reg_field                                              ...    RW SHU_TX_SET0_0[24:22]=3'h1
+  DQS2DQ_FILT_PITHRD                           uvm_reg_field                                              ...    RW SHU_TX_SET0_0[30:25]=6'h17 (Mirror: 6'h0e)
+  TXOEN_AUTOSET_EN                             uvm_reg_field                                              ...    RW SHU_TX_SET0_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+        P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+        P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+        P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+        P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
+        P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+        P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x17, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+        P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ZQ_SET0_0                                  ral_reg_DRAMC_blk_SHU_ZQ_SET0_0                            -     @5351
+  ZQCSCNT                                      uvm_reg_field                                              ...    RW SHU_ZQ_SET0_0[15:0]=16'h0000
+  TZQLAT                                       uvm_reg_field                                              ...    RW SHU_ZQ_SET0_0[31:27]=5'h1f (Mirror: 5'h1b)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0000, SHU_ZQ_SET0_ZQCSCNT) |
+        P_Fld(0x1f, SHU_ZQ_SET0_TZQLAT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_ZQ_SET0_0                                  ral_reg_DRAMC_blk_SHU_ZQ_SET0_0                            -     @5351
+  ZQCSCNT                                      uvm_reg_field                                              ...    RW SHU_ZQ_SET0_0[15:0]=16'h0005 (Mirror: 16'h0000)
+  TZQLAT                                       uvm_reg_field                                              ...    RW SHU_ZQ_SET0_0[31:27]=5'h1f
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) |
+        P_Fld(0x1f, SHU_ZQ_SET0_TZQLAT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_HMR4_DVFS_CTRL0_0                          ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0                    -     @5036
+  FSPCHG_PRDCNT                                uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h86
+  REFRCNT                                      uvm_reg_field                                              ...    RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h005 (Mirror: 12'h000)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x86, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+        P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ8_0                            -     @7828
+  R_DMRXDVS_UPD_FORCE_CYC_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[14:0]=15'h0100
+  R_DMRXDVS_UPD_FORCE_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[15:15]=1'h1 (Mirror: 1'h0)
+  R_DMRANK_RXDLY_PIPE_CG_IG_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[19:19]=1'h0
+  R_RMRODTEN_CG_IG_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[20:20]=1'h0
+  R_RMRX_TOPHY_CG_IG_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[21:21]=1'h1
+  R_DMRXDVS_RDSEL_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[22:22]=1'h0
+  R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0            uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[23:23]=1'h0
+  R_DMRXDLY_CG_IG_B0                           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[24:24]=1'h1
+  R_DMDQSIEN_FLAG_SYNC_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[26:26]=1'h0
+  R_DMDQSIEN_FLAG_PIPE_CG_IG_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[27:27]=1'h0
+  R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0               uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[28:28]=1'h0
+  R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0           uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[29:29]=1'h0
+  R_DMRANK_PIPE_CG_IG_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[30:30]=1'h0
+  R_DMRANK_CHG_PIPE_CG_IG_B0                   uvm_reg_field                                              ...    RW SHU_B0_DQ8_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+        P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+        P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+        P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ8_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ8_0                            -     @9231
+  R_DMRXDVS_UPD_FORCE_CYC_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[14:0]=15'h0100
+  R_DMRXDVS_UPD_FORCE_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[15:15]=1'h1 (Mirror: 1'h0)
+  R_DMRANK_RXDLY_PIPE_CG_IG_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[19:19]=1'h0
+  R_RMRODTEN_CG_IG_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[20:20]=1'h0
+  R_RMRX_TOPHY_CG_IG_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[21:21]=1'h1
+  R_DMRXDVS_RDSEL_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[22:22]=1'h0
+  R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1            uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[23:23]=1'h0
+  R_DMRXDLY_CG_IG_B1                           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[24:24]=1'h1
+  R_DMDQSIEN_FLAG_SYNC_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[26:26]=1'h0
+  R_DMDQSIEN_FLAG_PIPE_CG_IG_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[27:27]=1'h0
+  R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1               uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[28:28]=1'h0
+  R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1           uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[29:29]=1'h0
+  R_DMRANK_PIPE_CG_IG_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[30:30]=1'h0
+  R_DMRANK_CHG_PIPE_CG_IG_B1                   uvm_reg_field                                              ...    RW SHU_B1_DQ8_0[31:31]=1'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+        P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+        P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+        P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B0_DQ7_0                            -     @7808
+  R_DMRANKRXDVS_B0                             uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[3:0]=4'h0
+  R_DMDQMDBI_EYE_SHU_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[6:6]=1'h1
+  R_DMDQMDBI_SHU_B0                            uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[7:7]=1'h1
+  R_DMRXDVS_DQM_FLAGSEL_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[11:8]=4'ha (Mirror: 4'h0)
+  R_DMRXDVS_PBYTE_FLAG_OPT_B0                  uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[12:12]=1'h0
+  R_DMRXDVS_PBYTE_DQM_EN_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[13:13]=1'h1 (Mirror: 1'h0)
+  R_DMRXTRACK_DQM_EN_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[14:14]=1'h1 (Mirror: 1'h0)
+  R_DMRODTEN_B0                                uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[15:15]=1'h1
+  R_DMARPI_CG_FB2DLL_DCM_EN_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[16:16]=1'h0
+  R_DMTX_ARPI_CG_DQ_NEW_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[17:17]=1'h0
+  R_DMTX_ARPI_CG_DQS_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[18:18]=1'h0
+  R_DMTX_ARPI_CG_DQM_NEW_B0                    uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[19:19]=1'h0
+  R_LP4Y_SDN_MODE_DQS0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[20:20]=1'h0
+  R_DMRXRANK_DQ_EN_B0                          uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[24:24]=1'h1
+  R_DMRXRANK_DQ_LAT_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[27:25]=3'h2
+  R_DMRXRANK_DQS_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[28:28]=1'h1
+  R_DMRXRANK_DQS_LAT_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ7_0[31:29]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+        P_Fld(0xa, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+        P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+        P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ7_0                                   ral_reg_DDRPHY_blk_SHU_B1_DQ7_0                            -     @9211
+  R_DMRANKRXDVS_B1                             uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[3:0]=4'h0
+  R_DMDQMDBI_EYE_SHU_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[6:6]=1'h1
+  R_DMDQMDBI_SHU_B1                            uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[7:7]=1'h1
+  R_DMRXDVS_DQM_FLAGSEL_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[11:8]=4'ha (Mirror: 4'h0)
+  R_DMRXDVS_PBYTE_FLAG_OPT_B1                  uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[12:12]=1'h0
+  R_DMRXDVS_PBYTE_DQM_EN_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[13:13]=1'h1 (Mirror: 1'h0)
+  R_DMRXTRACK_DQM_EN_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[14:14]=1'h1 (Mirror: 1'h0)
+  R_DMRODTEN_B1                                uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[15:15]=1'h1
+  R_DMARPI_CG_FB2DLL_DCM_EN_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[16:16]=1'h0
+  R_DMTX_ARPI_CG_DQ_NEW_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[17:17]=1'h0
+  R_DMTX_ARPI_CG_DQS_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[18:18]=1'h0
+  R_DMTX_ARPI_CG_DQM_NEW_B1                    uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[19:19]=1'h0
+  R_LP4Y_SDN_MODE_DQS1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[20:20]=1'h0
+  R_DMRXRANK_DQ_EN_B1                          uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[24:24]=1'h1
+  R_DMRXRANK_DQ_LAT_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[27:25]=3'h2
+  R_DMRXRANK_DQS_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[28:28]=1'h1
+  R_DMRXRANK_DQS_LAT_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ7_0[31:29]=3'h1
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+        P_Fld(0xa, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+        P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+        P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B0_DQ11_0                                  ral_reg_DDRPHY_blk_SHU_B0_DQ11_0                           -     @7794
+  RG_RX_ARDQ_RANK_SEL_SER_EN_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[0:0]=1'h0
+  RG_RX_ARDQ_RANK_SEL_LAT_EN_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[1:1]=1'h0
+  RG_RX_ARDQ_OFFSETC_LAT_EN_B0                 uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[2:2]=1'h0
+  RG_RX_ARDQ_OFFSETC_EN_B0                     uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[3:3]=1'h0
+  RG_RX_ARDQ_OFFSETC_BIAS_EN_B0                uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[4:4]=1'h0
+  RG_RX_ARDQ_FRATE_EN_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[5:5]=1'h0
+  RG_RX_ARDQ_CDR_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[6:6]=1'h0
+  RG_RX_ARDQ_DVS_EN_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[7:7]=1'h1 (Mirror: 1'h0)
+  RG_RX_ARDQ_DVS_DLY_B0                        uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[11:8]=4'h0
+  RG_RX_ARDQ_DES_MODE_B0                       uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[17:16]=2'h2
+  RG_RX_ARDQ_BW_SEL_B0                         uvm_reg_field                                              ...    RW SHU_B0_DQ11_0[19:18]=2'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11, P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) |
+        P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) |
+        P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) |
+        P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0));
+/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Name                                           Type                                                       Size  Value
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+SHU_B1_DQ11_0                                  ral_reg_DDRPHY_blk_SHU_B1_DQ11_0                           -     @9197
+  RG_RX_ARDQ_RANK_SEL_SER_EN_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[0:0]=1'h0
+  RG_RX_ARDQ_RANK_SEL_LAT_EN_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[1:1]=1'h0
+  RG_RX_ARDQ_OFFSETC_LAT_EN_B1                 uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[2:2]=1'h0
+  RG_RX_ARDQ_OFFSETC_EN_B1                     uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[3:3]=1'h0
+  RG_RX_ARDQ_OFFSETC_BIAS_EN_B1                uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[4:4]=1'h0
+  RG_RX_ARDQ_FRATE_EN_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[5:5]=1'h0
+  RG_RX_ARDQ_CDR_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[6:6]=1'h0
+  RG_RX_ARDQ_DVS_EN_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[7:7]=1'h1 (Mirror: 1'h0)
+  RG_RX_ARDQ_DVS_DLY_B1                        uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[11:8]=4'h0
+  RG_RX_ARDQ_DES_MODE_B1                       uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[17:16]=2'h2
+  RG_RX_ARDQ_BW_SEL_B1                         uvm_reg_field                                              ...    RW SHU_B1_DQ11_0[19:18]=2'h0
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11, P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) |
+        P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) |
+        P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) |
+        P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1));
+//    Exit body
+}
+
+void CInit_golden_mini_freq_related_vseq_LP5_5500(DRAMC_CTX_T *p)
+{
+	//	  Enter body
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Enter:
+	/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value													   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_MISC_DRVING1_0							   ral_reg_DDRPHY_blk_SHU_MISC_DRVING1_0					  - 	@12634													   
+	  DQDRVN2									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING1_0[4:0]=5'h08 (Mirror: 5'h00)		   
+	  DQDRVP2									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING1_0[9:5]=5'h06 (Mirror: 5'h00)		   
+	  DQSDRVN1									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING1_0[14:10]=5'h08 (Mirror: 5'h00) 	   
+	  DQSDRVP1									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING1_0[19:15]=5'h06 (Mirror: 5'h00) 	   
+	  DQSDRVN2									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING1_0[24:20]=5'h08 (Mirror: 5'h00) 	   
+	  DQSDRVP2									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING1_0[29:25]=5'h06 (Mirror: 5'h00) 	   
+	  DIS_IMP_ODTN_track						   uvm_reg_field											  ...	 RW SHU_MISC_DRVING1_0[30:30]=1'h0						   
+	  DIS_IMPCAL_HW 							   uvm_reg_field											  ...	 RW SHU_MISC_DRVING1_0[31:31]=1'h0						   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(0x08, SHU_MISC_DRVING1_DQDRVN2) |
+			P_Fld(0x06, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN1) |
+			P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN2) |
+			P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) |
+			P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMPCAL_HW));
+	/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value													   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_MISC_DRVING2_0							   ral_reg_DDRPHY_blk_SHU_MISC_DRVING2_0					  - 	@12645													   
+	  CMDDRVN1									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING2_0[4:0]=5'h08 (Mirror: 5'h00)		   
+	  CMDDRVP1									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING2_0[9:5]=5'h06 (Mirror: 5'h00)		   
+	  CMDDRVN2									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING2_0[14:10]=5'h08 (Mirror: 5'h00) 	   
+	  CMDDRVP2									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING2_0[19:15]=5'h06 (Mirror: 5'h00) 	   
+	  DQDRVN1									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING2_0[24:20]=5'h08 (Mirror: 5'h00) 	   
+	  DQDRVP1									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING2_0[29:25]=5'h06 (Mirror: 5'h00) 	   
+	  DIS_IMPCAL_ODT_EN 						   uvm_reg_field											  ...	 RW SHU_MISC_DRVING2_0[31:31]=1'h0						   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2, P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN1) |
+			P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN2) |
+			P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x08, SHU_MISC_DRVING2_DQDRVN1) |
+			P_Fld(0x06, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN));
+	/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value													   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_MISC_DRVING3_0							   ral_reg_DDRPHY_blk_SHU_MISC_DRVING3_0					  - 	@12655													   
+	  DQODTN2									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING3_0[4:0]=5'h0a (Mirror: 5'h00)		   
+	  DQODTP2									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING3_0[9:5]=5'h0a (Mirror: 5'h00)		   
+	  DQSODTN									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING3_0[14:10]=5'h0a (Mirror: 5'h00) 	   
+	  DQSODTP									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING3_0[19:15]=5'h0a (Mirror: 5'h00) 	   
+	  DQSODTN2									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING3_0[24:20]=5'h0a (Mirror: 5'h00) 	   
+	  DQSODTP2									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING3_0[29:25]=5'h0a (Mirror: 5'h00) 	   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3, P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) |
+			P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) |
+			P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) |
+			P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2));
+	/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value													   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_MISC_DRVING4_0							   ral_reg_DDRPHY_blk_SHU_MISC_DRVING4_0					  - 	@12664													   
+	  CMDODTN1									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING4_0[4:0]=5'h0a (Mirror: 5'h00)		   
+	  CMDODTP1									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING4_0[9:5]=5'h0a (Mirror: 5'h00)		   
+	  CMDODTN2									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING4_0[14:10]=5'h0a (Mirror: 5'h00) 	   
+	  CMDODTP2									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING4_0[19:15]=5'h0a (Mirror: 5'h00) 	   
+	  DQODTN1									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING4_0[24:20]=5'h0a (Mirror: 5'h00) 	   
+	  DQODTP1									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING4_0[29:25]=5'h0a (Mirror: 5'h00) 	   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4, P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) |
+			P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) |
+			P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) |
+			P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1));
+	/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value													   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_MISC_DRVING6_0							   ral_reg_DDRPHY_blk_SHU_MISC_DRVING6_0					  - 	@12682													   
+	  IMP_TXDLY_CMD 							   uvm_reg_field											  ...	 RW SHU_MISC_DRVING6_0[5:0]=6'h11 (Mirror: 6'h01)		   
+	  DQCODTN1									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING6_0[24:20]=5'h00 					   
+	  DQCODTP1									   uvm_reg_field											  ...	 RW SHU_MISC_DRVING6_0[29:25]=5'h00 					   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6, P_Fld(0x11, SHU_MISC_DRVING6_IMP_TXDLY_CMD) |
+			P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1));
+	/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value													   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_MISC_IMPCAL1_0							   ral_reg_DDRPHY_blk_SHU_MISC_IMPCAL1_0					  - 	@12625													   
+	  IMPCAL_CHKCYCLE							   uvm_reg_field											  ...	 RW SHU_MISC_IMPCAL1_0[2:0]=3'h1 (Mirror: 3'h4) 		   
+	  IMPDRVP									   uvm_reg_field											  ...	 RW SHU_MISC_IMPCAL1_0[8:4]=5'h00						   
+	  IMPDRVN									   uvm_reg_field											  ...	 RW SHU_MISC_IMPCAL1_0[16:12]=5'h00 					   
+	  IMPCAL_CALEN_CYCLE						   uvm_reg_field											  ...	 RW SHU_MISC_IMPCAL1_0[19:17]=3'h4						   
+	  IMPCALCNT 								   uvm_reg_field											  ...	 RW SHU_MISC_IMPCAL1_0[27:20]=8'h03 (Mirror: 8'h00) 	   
+	  IMPCAL_CALICNT							   uvm_reg_field											  ...	 RW SHU_MISC_IMPCAL1_0[31:28]=4'h8						   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1, P_Fld(0x1, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) |
+			P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) |
+			P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) |
+			P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT));
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Exit:
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter:
+	/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value													   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_MISC_RDSEL_TRACK_0						   ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0				  - 	@12734													   
+	  DMDATLAT_i								   uvm_reg_field											  ...	 RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h0d (Mirror: 5'h00)	   
+	  RDSEL_HWSAVE_MSK							   uvm_reg_field											  ...	 RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0) 	   
+	  RDSEL_TRACK_EN							   uvm_reg_field											  ...	 RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0					   
+	  SHU_GW_THRD_NEG							   uvm_reg_field											  ...	 RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfb9 (Mirror: 12'h000) 
+	  SHU_GW_THRD_POS							   uvm_reg_field											  ...	 RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h047 (Mirror: 12'h000)
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x0d, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) |
+			P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) |
+			P_Fld(0xfb9, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x047, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS));
+	/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value													   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	MISC_SHU_RDAT_0 							   ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0						  - 	@12604													   
+	  DATLAT									   uvm_reg_field											  ...	 RW MISC_SHU_RDAT_0[4:0]=5'h0d (Mirror: 5'h00)			   
+	  DATLAT_DSEL								   uvm_reg_field											  ...	 RW MISC_SHU_RDAT_0[12:8]=5'h0c (Mirror: 5'h00) 		   
+	  DATLAT_DSEL_PHY							   uvm_reg_field											  ...	 RW MISC_SHU_RDAT_0[20:16]=5'h0c (Mirror: 5'h00)		   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x0d, MISC_SHU_RDAT_DATLAT) |
+			P_Fld(0x0c, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0c, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
+	/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value													   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	MISC_SHU_PHY_RX_CTRL_0						   ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0				  - 	@12540													   
+	  RANK_RXDLY_UPDLAT_EN						   uvm_reg_field											  ...	 RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0) 	   
+	  RANK_RXDLY_UPD_OFFSET 					   uvm_reg_field											  ...	 RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0)	   
+	  RX_IN_GATE_EN_PRE_OFFSET					   uvm_reg_field											  ...	 RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0)	   
+	  RX_IN_GATE_EN_HEAD						   uvm_reg_field											  ...	 RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h0					   
+	  RX_IN_GATE_EN_TAIL						   uvm_reg_field											  ...	 RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0)	   
+	  RX_IN_BUFF_EN_HEAD						   uvm_reg_field											  ...	 RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h1 (Mirror: 3'h0)	   
+	  RX_IN_BUFF_EN_TAIL						   uvm_reg_field											  ...	 RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0					   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) |
+			P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) |
+			P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) |
+			P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));
+	/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value													   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	MISC_SHU_RANKCTL_0							   ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0					  - 	@12530													   
+	  RANKINCTL_RXDLY							   uvm_reg_field											  ...	 RW MISC_SHU_RANKCTL_0[3:0]=4'hf (Mirror: 4'h0) 		   
+	  RANK_RXDLY_OPT							   uvm_reg_field											  ...	 RW MISC_SHU_RANKCTL_0[4:4]=1'h1						   
+	  RANKSEL_SELPH_FRUN						   uvm_reg_field											  ...	 RW MISC_SHU_RANKCTL_0[15:15]=1'h0						   
+	  RANKINCTL_STB 							   uvm_reg_field											  ...	 RW MISC_SHU_RANKCTL_0[19:16]=4'h2 (Mirror: 4'h0)		   
+	  RANKINCTL 								   uvm_reg_field											  ...	 RW MISC_SHU_RANKCTL_0[23:20]=4'h0						   
+	  RANKINCTL_ROOT1							   uvm_reg_field											  ...	 RW MISC_SHU_RANKCTL_0[27:24]=4'h0						   
+	  RANKINCTL_PHY 							   uvm_reg_field											  ...	 RW MISC_SHU_RANKCTL_0[31:28]=4'h4 (Mirror: 4'h0)		   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0xf, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) |
+			P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) |
+			P_Fld(0x2, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL) |
+			P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_PHY));
+	/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value													   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	MISC_SHU_RANK_SEL_LAT_0 					   ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0				  - 	@12757													   
+	  RANK_SEL_LAT_B0							   uvm_reg_field											  ...	 RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h1 (Mirror: 4'h0)	   
+	  RANK_SEL_LAT_B1							   uvm_reg_field											  ...	 RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h1 (Mirror: 4'h0)	   
+	  RANK_SEL_LAT_CA							   uvm_reg_field											  ...	 RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h1 (Mirror: 4'h0)	   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x1, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
+			P_Fld(0x1, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x1, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
+	/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value													   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	MISC_SHU_RK_DQSCTL_0_0						   ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0				  - 	@12352													   
+	  DQSINCTL									   uvm_reg_field											  ...	 RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h2 (Mirror: 4'h0) 	   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL);
+	/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value													   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	MISC_SHU_RK_DQSCTL_0_1						   ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1				  - 	@12356													   
+	  DQSINCTL									   uvm_reg_field											  ...	 RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h2 (Mirror: 4'h0) 	   
+	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL);
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 			   ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0		  - 	@7624														  
+	  DQSIEN_UI_P0_B0							   uvm_reg_field											  ...	 RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'hf (Mirror: 4'h0)  
+	  DQSIEN_UI_P1_B0							   uvm_reg_field											  ...	 RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h7 (Mirror: 4'h0)  
+	  DQSIEN_MCK_P0_B0							   uvm_reg_field											  ...	 RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0)
+	  DQSIEN_MCK_P1_B0							   uvm_reg_field											  ...	 RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h2 (Mirror: 4'h0)
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0xf, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+			P_Fld(0x7, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+			P_Fld(0x2, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_RK_B0_DQSIEN_PI_DLY_0_0 				   ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0			  - 	@7638														  
+	  DQSIEN_PI_B0								   uvm_reg_field											  ...	 RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0b, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 			   ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1		  - 	@7631														  
+	  DQSIEN_UI_P0_B0							   uvm_reg_field											  ...	 RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h2 (Mirror: 4'h0)  
+	  DQSIEN_UI_P1_B0							   uvm_reg_field											  ...	 RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'ha (Mirror: 4'h0)  
+	  DQSIEN_MCK_P0_B0							   uvm_reg_field											  ...	 RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h2 (Mirror: 4'h0)
+	  DQSIEN_MCK_P1_B0							   uvm_reg_field											  ...	 RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h2 (Mirror: 4'h0)
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+			P_Fld(0xa, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x2, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+			P_Fld(0x2, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_RK_B0_DQSIEN_PI_DLY_0_1 				   ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1			  - 	@7642														  
+	  DQSIEN_PI_B0								   uvm_reg_field											  ...	 RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h1e (Mirror: 7'h00)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1e, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 			   ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0		  - 	@9027														  
+	  DQSIEN_UI_P0_B1							   uvm_reg_field											  ...	 RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'hf (Mirror: 4'h0)  
+	  DQSIEN_UI_P1_B1							   uvm_reg_field											  ...	 RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h7 (Mirror: 4'h0)  
+	  DQSIEN_MCK_P0_B1							   uvm_reg_field											  ...	 RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0)
+	  DQSIEN_MCK_P1_B1							   uvm_reg_field											  ...	 RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h2 (Mirror: 4'h0)
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0xf, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+			P_Fld(0x7, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+			P_Fld(0x2, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_RK_B1_DQSIEN_PI_DLY_0_0 				   ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0			  - 	@9041														  
+	  DQSIEN_PI_B1								   uvm_reg_field											  ...	 RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0b, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 			   ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1		  - 	@9034														  
+	  DQSIEN_UI_P0_B1							   uvm_reg_field											  ...	 RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h2 (Mirror: 4'h0)  
+	  DQSIEN_UI_P1_B1							   uvm_reg_field											  ...	 RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'ha (Mirror: 4'h0)  
+	  DQSIEN_MCK_P0_B1							   uvm_reg_field											  ...	 RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h2 (Mirror: 4'h0)
+	  DQSIEN_MCK_P1_B1							   uvm_reg_field											  ...	 RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h2 (Mirror: 4'h0)
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+			P_Fld(0xa, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x2, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+			P_Fld(0x2, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_RK_B1_DQSIEN_PI_DLY_0_1 				   ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1			  - 	@9045														  
+	  DQSIEN_PI_B1								   uvm_reg_field											  ...	 RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h1e (Mirror: 7'h00)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1e, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	MISC_SHU_ODTCTRL_0							   ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0					  - 	@12550														  
+	  RODTEN									   uvm_reg_field											  ...	 RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0) 			  
+	  RODTENSTB_SELPH_CG_IG 					   uvm_reg_field											  ...	 RW MISC_SHU_ODTCTRL_0[1:1]=1'h0							  
+	  RODT_LAT									   uvm_reg_field											  ...	 RW MISC_SHU_ODTCTRL_0[7:4]=4'h0							  
+	  RODTEN_SELPH_FRUN 						   uvm_reg_field											  ...	 RW MISC_SHU_ODTCTRL_0[15:15]=1'h0							  
+	  RODTDLY_LAT_OPT							   uvm_reg_field											  ...	 RW MISC_SHU_ODTCTRL_0[25:24]=2'h0							  
+	  FIXRODT									   uvm_reg_field											  ...	 RW MISC_SHU_ODTCTRL_0[27:27]=1'h0							  
+	  RODTEN_OPT								   uvm_reg_field											  ...	 RW MISC_SHU_ODTCTRL_0[29:29]=1'h1							  
+	  RODTE2									   uvm_reg_field											  ...	 RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0)			  
+	  RODTE 									   uvm_reg_field											  ...	 RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) |
+			P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODT_LAT) |
+			P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) |
+			P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) |
+			P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B0_DQ7_0								   ral_reg_DDRPHY_blk_SHU_B0_DQ7_0							  - 	@7808														  
+	  R_DMRANKRXDVS_B0							   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[3:0]=4'h0									  
+	  R_DMDQMDBI_EYE_SHU_B0 					   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[6:6]=1'h0									  
+	  R_DMDQMDBI_SHU_B0 						   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[7:7]=1'h0									  
+	  R_DMRXDVS_DQM_FLAGSEL_B0					   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[11:8]=4'h0 								  
+	  R_DMRXDVS_PBYTE_FLAG_OPT_B0				   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[12:12]=1'h0								  
+	  R_DMRXDVS_PBYTE_DQM_EN_B0 				   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[13:13]=1'h0								  
+	  R_DMRXTRACK_DQM_EN_B0 					   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[14:14]=1'h0								  
+	  R_DMRODTEN_B0 							   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) 				  
+	  R_DMARPI_CG_FB2DLL_DCM_EN_B0				   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[16:16]=1'h0								  
+	  R_DMTX_ARPI_CG_DQ_NEW_B0					   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[17:17]=1'h0								  
+	  R_DMTX_ARPI_CG_DQS_NEW_B0 				   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[18:18]=1'h0								  
+	  R_DMTX_ARPI_CG_DQM_NEW_B0 				   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[19:19]=1'h0								  
+	  R_LP4Y_SDN_MODE_DQS0						   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[20:20]=1'h0								  
+	  R_DMRXRANK_DQ_EN_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) 				  
+	  R_DMRXRANK_DQ_LAT_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) 				  
+	  R_DMRXRANK_DQS_EN_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) 				  
+	  R_DMRXRANK_DQS_LAT_B0 					   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[31:29]=3'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+			P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+			P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+			P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+			P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+			P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+			P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+			P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+			P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B1_DQ7_0								   ral_reg_DDRPHY_blk_SHU_B1_DQ7_0							  - 	@9211														  
+	  R_DMRANKRXDVS_B1							   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[3:0]=4'h0									  
+	  R_DMDQMDBI_EYE_SHU_B1 					   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[6:6]=1'h0									  
+	  R_DMDQMDBI_SHU_B1 						   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[7:7]=1'h0									  
+	  R_DMRXDVS_DQM_FLAGSEL_B1					   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[11:8]=4'h0 								  
+	  R_DMRXDVS_PBYTE_FLAG_OPT_B1				   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[12:12]=1'h0								  
+	  R_DMRXDVS_PBYTE_DQM_EN_B1 				   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[13:13]=1'h0								  
+	  R_DMRXTRACK_DQM_EN_B1 					   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[14:14]=1'h0								  
+	  R_DMRODTEN_B1 							   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) 				  
+	  R_DMARPI_CG_FB2DLL_DCM_EN_B1				   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[16:16]=1'h0								  
+	  R_DMTX_ARPI_CG_DQ_NEW_B1					   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[17:17]=1'h0								  
+	  R_DMTX_ARPI_CG_DQS_NEW_B1 				   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[18:18]=1'h0								  
+	  R_DMTX_ARPI_CG_DQM_NEW_B1 				   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[19:19]=1'h0								  
+	  R_LP4Y_SDN_MODE_DQS1						   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[20:20]=1'h0								  
+	  R_DMRXRANK_DQ_EN_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) 				  
+	  R_DMRXRANK_DQ_LAT_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) 				  
+	  R_DMRXRANK_DQS_EN_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) 				  
+	  R_DMRXRANK_DQS_LAT_B1 					   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[31:29]=3'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+			P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+			P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+			P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+			P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+			P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+			P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+			P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+			P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 			   ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0		  - 	@7646														  
+	  RODTEN_UI_P0_B0							   uvm_reg_field											  ...	 RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h2 (Mirror: 3'h0)  
+	  RODTEN_UI_P1_B0							   uvm_reg_field											  ...	 RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h2 (Mirror: 3'h0)  
+	  RODTEN_MCK_P0_B0							   uvm_reg_field											  ...	 RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h3 (Mirror: 3'h0)
+	  RODTEN_MCK_P1_B0							   uvm_reg_field											  ...	 RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+			P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+			P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 			   ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1		  - 	@7653														  
+	  RODTEN_UI_P0_B0							   uvm_reg_field											  ...	 RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h5 (Mirror: 3'h0)  
+	  RODTEN_UI_P1_B0							   uvm_reg_field											  ...	 RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h5 (Mirror: 3'h0)  
+	  RODTEN_MCK_P0_B0							   uvm_reg_field											  ...	 RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h3 (Mirror: 3'h0)
+	  RODTEN_MCK_P1_B0							   uvm_reg_field											  ...	 RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x5, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+			P_Fld(0x5, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+			P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 			   ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0		  - 	@9049														  
+	  RODTEN_UI_P0_B1							   uvm_reg_field											  ...	 RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h2 (Mirror: 3'h0)  
+	  RODTEN_UI_P1_B1							   uvm_reg_field											  ...	 RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h2 (Mirror: 3'h0)  
+	  RODTEN_MCK_P0_B1							   uvm_reg_field											  ...	 RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h3 (Mirror: 3'h0)
+	  RODTEN_MCK_P1_B1							   uvm_reg_field											  ...	 RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+			P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+			P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 			   ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1		  - 	@9056														  
+	  RODTEN_UI_P0_B1							   uvm_reg_field											  ...	 RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h5 (Mirror: 3'h0)  
+	  RODTEN_UI_P1_B1							   uvm_reg_field											  ...	 RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h5 (Mirror: 3'h0)  
+	  RODTEN_MCK_P0_B1							   uvm_reg_field											  ...	 RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h3 (Mirror: 3'h0)
+	  RODTEN_MCK_P1_B1							   uvm_reg_field											  ...	 RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x5, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+			P_Fld(0x5, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+			P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_RX_CG_SET0_0							   ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0						  - 	@5323														  
+	  DLE_LAST_EXTEND3							   uvm_reg_field											  ...	 RW SHU_RX_CG_SET0_0[0:0]=1'h0								  
+	  READ_START_EXTEND3						   uvm_reg_field											  ...	 RW SHU_RX_CG_SET0_0[1:1]=1'h0								  
+	  DLE_LAST_EXTEND2							   uvm_reg_field											  ...	 RW SHU_RX_CG_SET0_0[2:2]=1'h0								  
+	  READ_START_EXTEND2						   uvm_reg_field											  ...	 RW SHU_RX_CG_SET0_0[3:3]=1'h0								  
+	  DLE_LAST_EXTEND1							   uvm_reg_field											  ...	 RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0)				  
+	  READ_START_EXTEND1						   uvm_reg_field											  ...	 RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0)				  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) |
+			P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) |
+			P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
+			P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B0_RANK_SELPH_UI_DLY_0					   ral_reg_DDRPHY_blk_SHU_B0_RANK_SELPH_UI_DLY_0			  - 	@7890														  
+	  RANKSEL_UI_DLY_P0_B0						   uvm_reg_field											  ...	 RW SHU_B0_RANK_SELPH_UI_DLY_0[2:0]=3'h0					  
+	  RANKSEL_UI_DLY_P1_B0						   uvm_reg_field											  ...	 RW SHU_B0_RANK_SELPH_UI_DLY_0[6:4]=3'h0					  
+	  RANKSEL_MCK_DLY_P0_B0 					   uvm_reg_field											  ...	 RW SHU_B0_RANK_SELPH_UI_DLY_0[18:16]=3'h1 (Mirror: 3'h0)	  
+	  RANKSEL_MCK_DLY_P1_B0 					   uvm_reg_field											  ...	 RW SHU_B0_RANK_SELPH_UI_DLY_0[22:20]=3'h1 (Mirror: 3'h0)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_RANK_SELPH_UI_DLY, P_Fld(0x0, SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P0_B0) |
+			P_Fld(0x0, SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P1_B0) | P_Fld(0x1, SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B0) |
+			P_Fld(0x1, SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B1_RANK_SELPH_UI_DLY_0					   ral_reg_DDRPHY_blk_SHU_B1_RANK_SELPH_UI_DLY_0			  - 	@9293														  
+	  RANKSEL_UI_DLY_P0_B1						   uvm_reg_field											  ...	 RW SHU_B1_RANK_SELPH_UI_DLY_0[2:0]=3'h0					  
+	  RANKSEL_UI_DLY_P1_B1						   uvm_reg_field											  ...	 RW SHU_B1_RANK_SELPH_UI_DLY_0[6:4]=3'h0					  
+	  RANKSEL_MCK_DLY_P0_B1 					   uvm_reg_field											  ...	 RW SHU_B1_RANK_SELPH_UI_DLY_0[18:16]=3'h1 (Mirror: 3'h0)	  
+	  RANKSEL_MCK_DLY_P1_B1 					   uvm_reg_field											  ...	 RW SHU_B1_RANK_SELPH_UI_DLY_0[22:20]=3'h1 (Mirror: 3'h0)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_RANK_SELPH_UI_DLY, P_Fld(0x0, SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P0_B1) |
+			P_Fld(0x0, SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P1_B1) | P_Fld(0x1, SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B1) |
+			P_Fld(0x1, SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_MISC_RANK_SEL_STB_0 					   ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0				  - 	@12720														  
+	  RANK_SEL_STB_EN							   uvm_reg_field											  ...	 RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0)		  
+	  RANK_SEL_STB_EN_B23						   uvm_reg_field											  ...	 RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0						  
+	  RANK_SEL_STB_SERMODE						   uvm_reg_field											  ...	 RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0						  
+	  RANK_SEL_STB_TRACK						   uvm_reg_field											  ...	 RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0)		  
+	  RANK_SEL_RXDLY_TRACK						   uvm_reg_field											  ...	 RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0						  
+	  RANK_SEL_STB_PHASE_EN 					   uvm_reg_field											  ...	 RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h1 (Mirror: 1'h0)		  
+	  RANK_SEL_PHSINCTL 						   uvm_reg_field											  ...	 RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h3 (Mirror: 4'h0)		  
+	  RANK_SEL_STB_UI_PLUS						   uvm_reg_field											  ...	 RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0 					  
+	  RANK_SEL_STB_MCK_PLUS 					   uvm_reg_field											  ...	 RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0 					  
+	  RANK_SEL_STB_UI_MINUS 					   uvm_reg_field											  ...	 RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h0 					  
+	  RANK_SEL_STB_MCK_MINUS					   uvm_reg_field											  ...	 RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0 					  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) |
+			P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) |
+			P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) |
+			P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x3, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) |
+			P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) |
+			P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	MISC_SHU_RK_DQSCAL_0_0						   ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0				  - 	@12370														  
+	  DQSIENLLMT								   uvm_reg_field											  ...	 RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00)		  
+	  DQSIENLLMTEN								   uvm_reg_field											  ...	 RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0) 		  
+	  DQSIENHLMT								   uvm_reg_field											  ...	 RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00)		  
+	  DQSIENHLMTEN								   uvm_reg_field											  ...	 RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+			P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+			P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	MISC_SHU_RK_DQSCAL_0_1						   ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1				  - 	@12377														  
+	  DQSIENLLMT								   uvm_reg_field											  ...	 RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00)		  
+	  DQSIENLLMTEN								   uvm_reg_field											  ...	 RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0) 		  
+	  DQSIENHLMT								   uvm_reg_field											  ...	 RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00)		  
+	  DQSIENHLMTEN								   uvm_reg_field											  ...	 RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
+			P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
+			P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_INI_UIPI_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0				  - 	@7602														  
+	  CURR_INI_PI_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)		  
+	  CURR_INI_UI_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h1f (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+			P_Fld(0x1f, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_INI_UIPI_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0				  - 	@9005														  
+	  CURR_INI_PI_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)		  
+	  CURR_INI_UI_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h1f (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+			P_Fld(0x1f, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_INI_UIPI_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1				  - 	@7607														  
+	  CURR_INI_PI_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h1e (Mirror: 7'h00)		  
+	  CURR_INI_UI_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h22 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1e, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
+			P_Fld(0x22, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_INI_UIPI_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1				  - 	@9010														  
+	  CURR_INI_PI_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h1e (Mirror: 7'h00)		  
+	  CURR_INI_UI_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h22 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1e, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
+			P_Fld(0x22, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_NEXT_INI_UIPI_0_0 				   ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0			  - 	@7612														  
+	  NEXT_INI_PI_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)	  
+	  NEXT_INI_UI_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h1f (Mirror: 8'h00)   
+	  NEXT_INI_UI_P1_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h27 (Mirror: 8'h00)  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+			P_Fld(0x1f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x27, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_NEXT_INI_UIPI_0_0 				   ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0			  - 	@9015														  
+	  NEXT_INI_PI_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)	  
+	  NEXT_INI_UI_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h1f (Mirror: 8'h00)   
+	  NEXT_INI_UI_P1_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h27 (Mirror: 8'h00)  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+			P_Fld(0x1f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x27, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_NEXT_INI_UIPI_0_1 				   ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1			  - 	@7618														  
+	  NEXT_INI_PI_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h1e (Mirror: 7'h00)	  
+	  NEXT_INI_UI_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h22 (Mirror: 8'h00)   
+	  NEXT_INI_UI_P1_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h2a (Mirror: 8'h00)  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1e, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
+			P_Fld(0x22, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x2a, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_NEXT_INI_UIPI_0_1 				   ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1			  - 	@9021														  
+	  NEXT_INI_PI_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h1e (Mirror: 7'h00)	  
+	  NEXT_INI_UI_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h22 (Mirror: 8'h00)   
+	  NEXT_INI_UI_P1_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h2a (Mirror: 8'h00)  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1e, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
+			P_Fld(0x22, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x2a, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit:
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter:
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_CA_CMD0_0_0							   ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_0					  - 	@10426														  
+	  RG_RX_ARCLK_R_DLY_DUTY					   uvm_reg_field											  ...	 RW SHU_R0_CA_CMD0_0_0[2:0]=3'h0							  
+	  RG_RX_ARCLK_F_DLY_DUTY					   uvm_reg_field											  ...	 RW SHU_R0_CA_CMD0_0_0[6:4]=3'h0							  
+	  RG_ARPI_CS								   uvm_reg_field											  ...	 RW SHU_R0_CA_CMD0_0_0[13:8]=6'h00							  
+	  RG_ARPI_CMD								   uvm_reg_field											  ...	 RW SHU_R0_CA_CMD0_0_0[21:16]=6'h10 (Mirror: 6'h00) 		  
+	  RG_ARPI_CLK								   uvm_reg_field											  ...	 RW SHU_R0_CA_CMD0_0_0[29:24]=6'h00 						  
+	  DA_ARPI_DDR400_0D5UI_RK0_CA				   uvm_reg_field											  ...	 RW SHU_R0_CA_CMD0_0_0[30:30]=1'h0							  
+	  DA_RX_ARDQSIEN_0D5UI_RK0_CA				   uvm_reg_field											  ...	 RW SHU_R0_CA_CMD0_0_0[31:31]=1'h0							  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
+			P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
+			P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
+			P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_DQ0_0_0							   ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 					  - 	@7582														  
+	  RG_RX_ARDQS0_R_DLY_DUTY					   uvm_reg_field											  ...	 RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0 							  
+	  RG_RX_ARDQS0_F_DLY_DUTY					   uvm_reg_field											  ...	 RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0 							  
+	  SW_ARPI_DQ_B0 							   uvm_reg_field											  ...	 RW SHU_R0_B0_DQ0_0_0[13:8]=6'h26 (Mirror: 6'h00)			  
+	  SW_ARPI_DQM_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_DQ0_0_0[21:16]=6'h26 (Mirror: 6'h00)			  
+	  ARPI_PBYTE_B0 							   uvm_reg_field											  ...	 RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00							  
+	  DA_ARPI_DDR400_0D5UI_RK0_B0				   uvm_reg_field											  ...	 RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0							  
+	  DA_RX_ARDQSIEN_0D5UI_RK0_B0				   uvm_reg_field											  ...	 RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0							  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+			P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x26, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+			P_Fld(0x26, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
+			P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_DQ0_0_0							   ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 					  - 	@8985														  
+	  RG_RX_ARDQS1_R_DLY_DUTY					   uvm_reg_field											  ...	 RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0 							  
+	  RG_RX_ARDQS1_F_DLY_DUTY					   uvm_reg_field											  ...	 RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0 							  
+	  SW_ARPI_DQ_B1 							   uvm_reg_field											  ...	 RW SHU_R0_B1_DQ0_0_0[13:8]=6'h21 (Mirror: 6'h00)			  
+	  SW_ARPI_DQM_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_DQ0_0_0[21:16]=6'h21 (Mirror: 6'h00)			  
+	  ARPI_PBYTE_B1 							   uvm_reg_field											  ...	 RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00							  
+	  DA_ARPI_DDR400_0D5UI_RK0_B1				   uvm_reg_field											  ...	 RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0							  
+	  DA_RX_ARDQSIEN_0D5UI_RK0_B1				   uvm_reg_field											  ...	 RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0							  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+			P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x21, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+			P_Fld(0x21, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
+			P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_CA_CMD0_0_1							   ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_1					  - 	@10436														  
+	  RG_RX_ARCLK_R_DLY_DUTY					   uvm_reg_field											  ...	 RW SHU_R0_CA_CMD0_0_1[2:0]=3'h0							  
+	  RG_RX_ARCLK_F_DLY_DUTY					   uvm_reg_field											  ...	 RW SHU_R0_CA_CMD0_0_1[6:4]=3'h0							  
+	  RG_ARPI_CS								   uvm_reg_field											  ...	 RW SHU_R0_CA_CMD0_0_1[13:8]=6'h00							  
+	  RG_ARPI_CMD								   uvm_reg_field											  ...	 RW SHU_R0_CA_CMD0_0_1[21:16]=6'h10 (Mirror: 6'h00) 		  
+	  RG_ARPI_CLK								   uvm_reg_field											  ...	 RW SHU_R0_CA_CMD0_0_1[29:24]=6'h00 						  
+	  DA_ARPI_DDR400_0D5UI_RK0_CA				   uvm_reg_field											  ...	 RW SHU_R0_CA_CMD0_0_1[30:30]=1'h0							  
+	  DA_RX_ARDQSIEN_0D5UI_RK0_CA				   uvm_reg_field											  ...	 RW SHU_R0_CA_CMD0_0_1[31:31]=1'h0							  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
+			P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
+			P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
+			P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_DQ0_0_1							   ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 					  - 	@7592														  
+	  RG_RX_ARDQS0_R_DLY_DUTY					   uvm_reg_field											  ...	 RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0 							  
+	  RG_RX_ARDQS0_F_DLY_DUTY					   uvm_reg_field											  ...	 RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0 							  
+	  SW_ARPI_DQ_B0 							   uvm_reg_field											  ...	 RW SHU_R0_B0_DQ0_0_1[13:8]=6'h21 (Mirror: 6'h00)			  
+	  SW_ARPI_DQM_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_DQ0_0_1[21:16]=6'h21 (Mirror: 6'h00)			  
+	  ARPI_PBYTE_B0 							   uvm_reg_field											  ...	 RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00							  
+	  DA_ARPI_DDR400_0D5UI_RK0_B0				   uvm_reg_field											  ...	 RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0							  
+	  DA_RX_ARDQSIEN_0D5UI_RK0_B0				   uvm_reg_field											  ...	 RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0							  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
+			P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x21, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+			P_Fld(0x21, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
+			P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_DQ0_0_1							   ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 					  - 	@8995														  
+	  RG_RX_ARDQS1_R_DLY_DUTY					   uvm_reg_field											  ...	 RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0 							  
+	  RG_RX_ARDQS1_F_DLY_DUTY					   uvm_reg_field											  ...	 RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0 							  
+	  SW_ARPI_DQ_B1 							   uvm_reg_field											  ...	 RW SHU_R0_B1_DQ0_0_1[13:8]=6'h22 (Mirror: 6'h00)			  
+	  SW_ARPI_DQM_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_DQ0_0_1[21:16]=6'h22 (Mirror: 6'h00)			  
+	  ARPI_PBYTE_B1 							   uvm_reg_field											  ...	 RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00							  
+	  DA_ARPI_DDR400_0D5UI_RK0_B1				   uvm_reg_field											  ...	 RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0							  
+	  DA_RX_ARDQSIEN_0D5UI_RK0_B1				   uvm_reg_field											  ...	 RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0							  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
+			P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x22, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+			P_Fld(0x22, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
+			P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_DCM_CTRL0_0 							   ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0						  - 	@5027														  
+	  DDRPHY_CLK_EN_OPT 						   uvm_reg_field											  ...	 RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0)				  
+	  DPHY_CMDDCM_EXTCNT						   uvm_reg_field											  ...	 RW SHU_DCM_CTRL0_0[11:8]=4'h4								  
+	  DDRPHY_CLK_DYN_GATING_SEL 				   uvm_reg_field											  ...	 RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0)				  
+	  CKE_EXTNONPD_CNT							   uvm_reg_field											  ...	 RW SHU_DCM_CTRL0_0[19:16]=4'h0 							  
+	  FASTWAKE2 								   uvm_reg_field											  ...	 RW SHU_DCM_CTRL0_0[29:29]=1'h0 							  
+	  FASTWAKE									   uvm_reg_field											  ...	 RW SHU_DCM_CTRL0_0[31:31]=1'h1 							  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+			P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+			P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) |
+			P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_APHY_TX_PICG_CTRL_0 					   ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0				  - 	@5377														  
+	  DDRPHY_CLK_EN_COMB_TX_PICG_CNT			   uvm_reg_field											  ...	 RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h8 (Mirror: 4'h0)		  
+	  DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1			   uvm_reg_field											  ...	 RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h1 (Mirror: 3'h0)		  
+	  DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0			   uvm_reg_field											  ...	 RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h1 (Mirror: 3'h0)		  
+	  DDRPHY_CLK_EN_COMB_TX_OPT 				   uvm_reg_field											  ...	 RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x8, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) |
+			P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) |
+			P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_APHY_TX_PICG_CTRL_0_0 				   ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0			  - 	@4926														  
+	  DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1		   uvm_reg_field											  ...	 RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h2 (Mirror: 3'h0)	  
+	  DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0		   uvm_reg_field											  ...	 RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h2 (Mirror: 3'h0)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x2, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+			P_Fld(0x2, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_APHY_TX_PICG_CTRL_0_1 				   ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1			  - 	@4931														  
+	  DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1		   uvm_reg_field											  ...	 RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h2 (Mirror: 3'h0)	  
+	  DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0		   uvm_reg_field											  ...	 RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h2 (Mirror: 3'h0)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
+			P_Fld(0x2, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_NEW_XRW2W_CTRL_0						   ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0					  - 	@5371														  
+	  TX_PI_UPDCTL_B0							   uvm_reg_field											  ...	 RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h2 (Mirror: 3'h0) 		  
+	  TX_PI_UPDCTL_B1							   uvm_reg_field											  ...	 RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h2 (Mirror: 3'h0) 		  
+	  TXPI_UPD_MODE 							   uvm_reg_field											  ...	 RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1) 		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) |
+			P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_SELPH_DQS0_0							   ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0						  - 	@5271														  
+	  TXDLY_DQS0								   uvm_reg_field											  ...	 RW SHU_SELPH_DQS0_0[2:0]=3'h2 (Mirror: 3'h1)				  
+	  TXDLY_DQS1								   uvm_reg_field											  ...	 RW SHU_SELPH_DQS0_0[6:4]=3'h2 (Mirror: 3'h1)				  
+	  TXDLY_DQS2								   uvm_reg_field											  ...	 RW SHU_SELPH_DQS0_0[10:8]=3'h1 							  
+	  TXDLY_DQS3								   uvm_reg_field											  ...	 RW SHU_SELPH_DQS0_0[14:12]=3'h1							  
+	  TXDLY_OEN_DQS0							   uvm_reg_field											  ...	 RW SHU_SELPH_DQS0_0[18:16]=3'h2 (Mirror: 3'h1) 			  
+	  TXDLY_OEN_DQS1							   uvm_reg_field											  ...	 RW SHU_SELPH_DQS0_0[22:20]=3'h2 (Mirror: 3'h1) 			  
+	  TXDLY_OEN_DQS2							   uvm_reg_field											  ...	 RW SHU_SELPH_DQS0_0[26:24]=3'h1							  
+	  TXDLY_OEN_DQS3							   uvm_reg_field											  ...	 RW SHU_SELPH_DQS0_0[30:28]=3'h1							  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS0) |
+			P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) |
+			P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) |
+			P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) |
+			P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_SELPH_DQS1_0							   ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0						  - 	@5282														  
+	  dly_DQS0									   uvm_reg_field											  ...	 RW SHU_SELPH_DQS1_0[3:0]=4'hd (Mirror: 4'h1)				  
+	  dly_DQS1									   uvm_reg_field											  ...	 RW SHU_SELPH_DQS1_0[7:4]=4'he (Mirror: 4'h1)				  
+	  dly_DQS2									   uvm_reg_field											  ...	 RW SHU_SELPH_DQS1_0[11:8]=4'h1 							  
+	  dly_DQS3									   uvm_reg_field											  ...	 RW SHU_SELPH_DQS1_0[15:12]=4'h1							  
+	  dly_oen_DQS0								   uvm_reg_field											  ...	 RW SHU_SELPH_DQS1_0[19:16]=4'ha (Mirror: 4'h1) 			  
+	  dly_oen_DQS1								   uvm_reg_field											  ...	 RW SHU_SELPH_DQS1_0[23:20]=4'hb (Mirror: 4'h1) 			  
+	  dly_oen_DQS2								   uvm_reg_field											  ...	 RW SHU_SELPH_DQS1_0[27:24]=4'h1							  
+	  dly_oen_DQS3								   uvm_reg_field											  ...	 RW SHU_SELPH_DQS1_0[31:28]=4'h1							  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0xd, SHU_SELPH_DQS1_DLY_DQS0) |
+			P_Fld(0xe, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) |
+			P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0xa, SHU_SELPH_DQS1_DLY_OEN_DQS0) |
+			P_Fld(0xb, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) |
+			P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_SELPH_DQ0_0_0 						   ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0					  - 	@4746														  
+	  TXDLY_DQ0 								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ0_0_0[2:0]=3'h2 (Mirror: 3'h1)			  
+	  TXDLY_DQ1 								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ0_0_0[6:4]=3'h2 (Mirror: 3'h1)			  
+	  TXDLY_DQ2 								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1							  
+	  TXDLY_DQ3 								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1 						  
+	  TXDLY_OEN_DQ0 							   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ0_0_0[18:16]=3'h3 (Mirror: 3'h1)			  
+	  TXDLY_OEN_DQ1 							   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ0_0_0[22:20]=3'h3 (Mirror: 3'h1)			  
+	  TXDLY_OEN_DQ2 							   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1 						  
+	  TXDLY_OEN_DQ3 							   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1 						  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+			P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+			P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+			P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+			P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_SELPH_DQ1_0_0 						   ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0					  - 	@4768														  
+	  TXDLY_DQM0								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ1_0_0[2:0]=3'h2 (Mirror: 3'h1)			  
+	  TXDLY_DQM1								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ1_0_0[6:4]=3'h2 (Mirror: 3'h1)			  
+	  TXDLY_DQM2								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1							  
+	  TXDLY_DQM3								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1 						  
+	  TXDLY_OEN_DQM0							   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ1_0_0[18:16]=3'h3 (Mirror: 3'h1)			  
+	  TXDLY_OEN_DQM1							   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ1_0_0[22:20]=3'h3 (Mirror: 3'h1)			  
+	  TXDLY_OEN_DQM2							   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1 						  
+	  TXDLY_OEN_DQM3							   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1 						  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+			P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+			P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+			P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+			P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_SELPH_DQ2_0_0 						   ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0					  - 	@4790														  
+	  dly_DQ0									   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ2_0_0[3:0]=4'hb (Mirror: 4'h1)			  
+	  dly_DQ1									   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ2_0_0[7:4]=4'hb (Mirror: 4'h1)			  
+	  dly_DQ2									   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1							  
+	  dly_DQ3									   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1 						  
+	  dly_oen_DQ0								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ2_0_0[19:16]=4'h7 (Mirror: 4'h1)			  
+	  dly_oen_DQ1								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ2_0_0[23:20]=4'h7 (Mirror: 4'h1)			  
+	  dly_oen_DQ2								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1 						  
+	  dly_oen_DQ3								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1 						  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0xb, SHURK_SELPH_DQ2_DLY_DQ0) |
+			P_Fld(0xb, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+			P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+			P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+			P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_SELPH_DQ3_0_0 						   ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0					  - 	@4812														  
+	  dly_DQM0									   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ3_0_0[3:0]=4'hb (Mirror: 4'h1)			  
+	  dly_DQM1									   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ3_0_0[7:4]=4'hb (Mirror: 4'h1)			  
+	  dly_DQM2									   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1							  
+	  dly_DQM3									   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1 						  
+	  dly_oen_DQM0								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ3_0_0[19:16]=4'h7 (Mirror: 4'h1)			  
+	  dly_oen_DQM1								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ3_0_0[23:20]=4'h7 (Mirror: 4'h1)			  
+	  dly_oen_DQM2								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1 						  
+	  dly_oen_DQM3								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1 						  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0xb, SHURK_SELPH_DQ3_DLY_DQM0) |
+			P_Fld(0xb, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+			P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+			P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+			P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_SELPH_DQ0_0_1 						   ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1					  - 	@4757														  
+	  TXDLY_DQ0 								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ0_0_1[2:0]=3'h2 (Mirror: 3'h1)			  
+	  TXDLY_DQ1 								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ0_0_1[6:4]=3'h2 (Mirror: 3'h1)			  
+	  TXDLY_DQ2 								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1							  
+	  TXDLY_DQ3 								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1 						  
+	  TXDLY_OEN_DQ0 							   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ0_0_1[18:16]=3'h3 (Mirror: 3'h1)			  
+	  TXDLY_OEN_DQ1 							   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ0_0_1[22:20]=3'h3 (Mirror: 3'h1)			  
+	  TXDLY_OEN_DQ2 							   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1 						  
+	  TXDLY_OEN_DQ3 							   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1 						  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) |
+			P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
+			P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+			P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
+			P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_SELPH_DQ1_0_1 						   ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1					  - 	@4779														  
+	  TXDLY_DQM0								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ1_0_1[2:0]=3'h2 (Mirror: 3'h1)			  
+	  TXDLY_DQM1								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ1_0_1[6:4]=3'h2 (Mirror: 3'h1)			  
+	  TXDLY_DQM2								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1							  
+	  TXDLY_DQM3								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1 						  
+	  TXDLY_OEN_DQM0							   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ1_0_1[18:16]=3'h3 (Mirror: 3'h1)			  
+	  TXDLY_OEN_DQM1							   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ1_0_1[22:20]=3'h3 (Mirror: 3'h1)			  
+	  TXDLY_OEN_DQM2							   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1 						  
+	  TXDLY_OEN_DQM3							   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1 						  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) |
+			P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
+			P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+			P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
+			P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_SELPH_DQ2_0_1 						   ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1					  - 	@4801														  
+	  dly_DQ0									   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ2_0_1[3:0]=4'hd (Mirror: 4'h1)			  
+	  dly_DQ1									   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ2_0_1[7:4]=4'hd (Mirror: 4'h1)			  
+	  dly_DQ2									   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1							  
+	  dly_DQ3									   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1 						  
+	  dly_oen_DQ0								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ2_0_1[19:16]=4'h9 (Mirror: 4'h1)			  
+	  dly_oen_DQ1								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ2_0_1[23:20]=4'h9 (Mirror: 4'h1)			  
+	  dly_oen_DQ2								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1 						  
+	  dly_oen_DQ3								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1 						  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0xd, SHURK_SELPH_DQ2_DLY_DQ0) |
+			P_Fld(0xd, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
+			P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x9, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+			P_Fld(0x9, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
+			P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_SELPH_DQ3_0_1 						   ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1					  - 	@4823														  
+	  dly_DQM0									   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ3_0_1[3:0]=4'hd (Mirror: 4'h1)			  
+	  dly_DQM1									   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ3_0_1[7:4]=4'hd (Mirror: 4'h1)			  
+	  dly_DQM2									   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1							  
+	  dly_DQM3									   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1 						  
+	  dly_oen_DQM0								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ3_0_1[19:16]=4'h9 (Mirror: 4'h1)			  
+	  dly_oen_DQM1								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ3_0_1[23:20]=4'h9 (Mirror: 4'h1)			  
+	  dly_oen_DQM2								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1 						  
+	  dly_oen_DQM3								   uvm_reg_field											  ...	 RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1 						  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0xd, SHURK_SELPH_DQ3_DLY_DQM0) |
+			P_Fld(0xd, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
+			P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x9, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+			P_Fld(0x9, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
+			P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_DQS2DQ_CAL1_0_0						   ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0					  - 	@4834														  
+	  BOOT_ORIG_UI_RK0_DQ0						   uvm_reg_field											  ...	 RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h026 (Mirror: 11'h000)	  
+	  BOOT_ORIG_UI_RK0_DQ1						   uvm_reg_field											  ...	 RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h021 (Mirror: 11'h000)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x026, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+			P_Fld(0x021, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_DQS2DQ_CAL2_0_0						   ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0					  - 	@4844														  
+	  BOOT_TARG_UI_RK0_DQ0						   uvm_reg_field											  ...	 RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h026 (Mirror: 11'h000)	  
+	  BOOT_TARG_UI_RK0_DQ1						   uvm_reg_field											  ...	 RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h021 (Mirror: 11'h000)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x026, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+			P_Fld(0x021, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_DQS2DQ_CAL5_0_0						   ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0					  - 	@4882														  
+	  BOOT_TARG_UI_RK0_DQM0 					   uvm_reg_field											  ...	 RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h026 (Mirror: 11'h000)	  
+	  BOOT_TARG_UI_RK0_DQM1 					   uvm_reg_field											  ...	 RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h021 (Mirror: 11'h000)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x026, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+			P_Fld(0x021, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_DQS2DQ_CAL1_0_1						   ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1					  - 	@4839														  
+	  BOOT_ORIG_UI_RK0_DQ0						   uvm_reg_field											  ...	 RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h021 (Mirror: 11'h000)	  
+	  BOOT_ORIG_UI_RK0_DQ1						   uvm_reg_field											  ...	 RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h022 (Mirror: 11'h000)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x021, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
+			P_Fld(0x022, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_DQS2DQ_CAL2_0_1						   ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1					  - 	@4849														  
+	  BOOT_TARG_UI_RK0_DQ0						   uvm_reg_field											  ...	 RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h021 (Mirror: 11'h000)	  
+	  BOOT_TARG_UI_RK0_DQ1						   uvm_reg_field											  ...	 RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h022 (Mirror: 11'h000)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x021, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
+			P_Fld(0x022, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_DQS2DQ_CAL5_0_1						   ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1					  - 	@4887														  
+	  BOOT_TARG_UI_RK0_DQM0 					   uvm_reg_field											  ...	 RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h021 (Mirror: 11'h000)	  
+	  BOOT_TARG_UI_RK0_DQM1 					   uvm_reg_field											  ...	 RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h022 (Mirror: 11'h000)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x021, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
+			P_Fld(0x022, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_PI_0_0								   ral_reg_DRAMC_blk_SHURK_PI_0_0							  - 	@4892														  
+	  RK0_ARPI_DQ_B1							   uvm_reg_field											  ...	 RW SHURK_PI_0_0[5:0]=6'h21 (Mirror: 6'h00) 				  
+	  RK0_ARPI_DQ_B0							   uvm_reg_field											  ...	 RW SHURK_PI_0_0[13:8]=6'h26 (Mirror: 6'h00)				  
+	  RK0_ARPI_DQM_B1							   uvm_reg_field											  ...	 RW SHURK_PI_0_0[21:16]=6'h21 (Mirror: 6'h00)				  
+	  RK0_ARPI_DQM_B0							   uvm_reg_field											  ...	 RW SHURK_PI_0_0[29:24]=6'h26 (Mirror: 6'h00)				  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x21, SHURK_PI_RK0_ARPI_DQ_B1) |
+			P_Fld(0x26, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x21, SHURK_PI_RK0_ARPI_DQM_B1) |
+			P_Fld(0x26, SHURK_PI_RK0_ARPI_DQM_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_PI_0_1								   ral_reg_DRAMC_blk_SHURK_PI_0_1							  - 	@4899														  
+	  RK0_ARPI_DQ_B1							   uvm_reg_field											  ...	 RW SHURK_PI_0_1[5:0]=6'h22 (Mirror: 6'h00) 				  
+	  RK0_ARPI_DQ_B0							   uvm_reg_field											  ...	 RW SHURK_PI_0_1[13:8]=6'h21 (Mirror: 6'h00)				  
+	  RK0_ARPI_DQM_B1							   uvm_reg_field											  ...	 RW SHURK_PI_0_1[21:16]=6'h22 (Mirror: 6'h00)				  
+	  RK0_ARPI_DQM_B0							   uvm_reg_field											  ...	 RW SHURK_PI_0_1[29:24]=6'h21 (Mirror: 6'h00)				  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x22, SHURK_PI_RK0_ARPI_DQ_B1) |
+			P_Fld(0x21, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x22, SHURK_PI_RK0_ARPI_DQM_B1) |
+			P_Fld(0x21, SHURK_PI_RK0_ARPI_DQM_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_TXDLY0_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0					  - 	@7428														  
+	  TX_ARDQ0_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h2c (Mirror: 8'h00) 		  
+	  TX_ARDQ1_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h2c (Mirror: 8'h00)		  
+	  TX_ARDQ2_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h2c (Mirror: 8'h00)		  
+	  TX_ARDQ3_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h2c (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+			P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+			P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_TXDLY1_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0					  - 	@7442														  
+	  TX_ARDQ4_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h2c (Mirror: 8'h00) 		  
+	  TX_ARDQ5_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h2c (Mirror: 8'h00)		  
+	  TX_ARDQ6_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h2c (Mirror: 8'h00)		  
+	  TX_ARDQ7_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h2c (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+			P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+			P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_TXDLY3_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0					  - 	@7470														  
+	  TX_ARDQM0_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h2c (Mirror: 8'h00) 		  
+	  TX_ARWCK_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00						  
+	  TX_ARWCKB_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00						  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x2c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+			P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_TXDLY0_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0					  - 	@8831														  
+	  TX_ARDQ0_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h3c (Mirror: 8'h00) 		  
+	  TX_ARDQ1_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h3c (Mirror: 8'h00)		  
+	  TX_ARDQ2_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h3c (Mirror: 8'h00)		  
+	  TX_ARDQ3_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h3c (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+			P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+			P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_TXDLY1_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0					  - 	@8845														  
+	  TX_ARDQ4_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h3c (Mirror: 8'h00) 		  
+	  TX_ARDQ5_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h3c (Mirror: 8'h00)		  
+	  TX_ARDQ6_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h3c (Mirror: 8'h00)		  
+	  TX_ARDQ7_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h3c (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+			P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+			P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_TXDLY3_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0					  - 	@8873														  
+	  TX_ARDQM0_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h3c (Mirror: 8'h00) 		  
+	  TX_ARWCK_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00						  
+	  TX_ARWCKB_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00						  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x3c, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+			P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_TXDLY0_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1					  - 	@7435														  
+	  TX_ARDQ0_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h1c (Mirror: 8'h00) 		  
+	  TX_ARDQ1_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h1c (Mirror: 8'h00)		  
+	  TX_ARDQ2_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h1c (Mirror: 8'h00)		  
+	  TX_ARDQ3_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h1c (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
+			P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
+			P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_TXDLY1_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1					  - 	@7449														  
+	  TX_ARDQ4_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h1c (Mirror: 8'h00) 		  
+	  TX_ARDQ5_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h1c (Mirror: 8'h00)		  
+	  TX_ARDQ6_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h1c (Mirror: 8'h00)		  
+	  TX_ARDQ7_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h1c (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
+			P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
+			P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_TXDLY3_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1					  - 	@7476														  
+	  TX_ARDQM0_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h1c (Mirror: 8'h00) 		  
+	  TX_ARWCK_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00						  
+	  TX_ARWCKB_DLY_B0							   uvm_reg_field											  ...	 RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00						  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
+			P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_TXDLY0_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1					  - 	@8838														  
+	  TX_ARDQ0_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h18 (Mirror: 8'h00) 		  
+	  TX_ARDQ1_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h18 (Mirror: 8'h00)		  
+	  TX_ARDQ2_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h18 (Mirror: 8'h00)		  
+	  TX_ARDQ3_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h18 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x18, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
+			P_Fld(0x18, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x18, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
+			P_Fld(0x18, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_TXDLY1_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1					  - 	@8852														  
+	  TX_ARDQ4_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h18 (Mirror: 8'h00) 		  
+	  TX_ARDQ5_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h18 (Mirror: 8'h00)		  
+	  TX_ARDQ6_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h18 (Mirror: 8'h00)		  
+	  TX_ARDQ7_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h18 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x18, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
+			P_Fld(0x18, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x18, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
+			P_Fld(0x18, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_TXDLY3_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1					  - 	@8879														  
+	  TX_ARDQM0_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h18 (Mirror: 8'h00) 		  
+	  TX_ARWCK_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00						  
+	  TX_ARWCKB_DLY_B1							   uvm_reg_field											  ...	 RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00						  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x18, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
+			P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_TX_RANKCTL_0							   ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0						  - 	@5345														  
+	  TXRANKINCTL_TXDLY 						   uvm_reg_field											  ...	 RW SHU_TX_RANKCTL_0[3:0]=4'h1 (Mirror: 4'h0)				  
+	  TXRANKINCTL								   uvm_reg_field											  ...	 RW SHU_TX_RANKCTL_0[7:4]=4'h1 (Mirror: 4'h0)				  
+	  TXRANKINCTL_ROOT							   uvm_reg_field											  ...	 RW SHU_TX_RANKCTL_0[11:8]=4'h0 							  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) |
+			P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B0_DQ9_0								   ral_reg_DDRPHY_blk_SHU_B0_DQ9_0							  - 	@7845														  
+	  RG_ARPI_RESERVE_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ9_0[31:0]=32'h0c410eb3 (Mirror: 32'h0c430eb3)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9, 0x0c410eb3, SHU_B0_DQ9_RG_ARPI_RESERVE_B0);
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B1_DQ9_0								   ral_reg_DDRPHY_blk_SHU_B1_DQ9_0							  - 	@9248														  
+	  RG_ARPI_RESERVE_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ9_0[31:0]=32'hfa89b179 (Mirror: 32'hfa8bb179)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9, 0xfa89b179, SHU_B1_DQ9_RG_ARPI_RESERVE_B1);
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit:
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Enter
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_WCK_WR_MCK_0_0						   ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_0					  - 	@4936														  
+	  WCK_WR_B0_MCK 							   uvm_reg_field											  ...	 RW SHURK_WCK_WR_MCK_0_0[3:0]=4'h3 (Mirror: 4'h1)			  
+	  WCK_WR_B1_MCK 							   uvm_reg_field											  ...	 RW SHURK_WCK_WR_MCK_0_0[7:4]=4'h3 (Mirror: 4'h1)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK, P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) |
+			P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_WCK_WR_MCK_0_1						   ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_1					  - 	@4941														  
+	  WCK_WR_B0_MCK 							   uvm_reg_field											  ...	 RW SHURK_WCK_WR_MCK_0_1[3:0]=4'h3 (Mirror: 4'h1)			  
+	  WCK_WR_B1_MCK 							   uvm_reg_field											  ...	 RW SHURK_WCK_WR_MCK_0_1[7:4]=4'h3 (Mirror: 4'h1)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) |
+			P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_WCK_RD_MCK_0_0						   ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_0					  - 	@4946														  
+	  WCK_RD_B0_MCK 							   uvm_reg_field											  ...	 RW SHURK_WCK_RD_MCK_0_0[3:0]=4'h5 (Mirror: 4'h1)			  
+	  WCK_RD_B1_MCK 							   uvm_reg_field											  ...	 RW SHURK_WCK_RD_MCK_0_0[7:4]=4'h5 (Mirror: 4'h1)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+    #if LP5_DDR4266_RDBI_WORKAROUND
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK, P_Fld(0x5, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
+			P_Fld(0x5, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
+    #else
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK, P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
+            P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
+    #endif
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_WCK_RD_MCK_0_1						   ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_1					  - 	@4951														  
+	  WCK_RD_B0_MCK 							   uvm_reg_field											  ...	 RW SHURK_WCK_RD_MCK_0_1[3:0]=4'h5 (Mirror: 4'h1)			  
+	  WCK_RD_B1_MCK 							   uvm_reg_field											  ...	 RW SHURK_WCK_RD_MCK_0_1[7:4]=4'h5 (Mirror: 4'h1)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+    #if LP5_DDR4266_RDBI_WORKAROUND
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
+			P_Fld(0x5, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
+    #else
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
+            P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
+    #endif
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_WCK_FS_MCK_0_0						   ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_0					  - 	@4956														  
+	  WCK_FS_B0_MCK 							   uvm_reg_field											  ...	 RW SHURK_WCK_FS_MCK_0_0[3:0]=4'h2 (Mirror: 4'h1)			  
+	  WCK_FS_B1_MCK 							   uvm_reg_field											  ...	 RW SHURK_WCK_FS_MCK_0_0[7:4]=4'h2 (Mirror: 4'h1)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK, P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) |
+			P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_WCK_FS_MCK_0_1						   ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_1					  - 	@4961														  
+	  WCK_FS_B0_MCK 							   uvm_reg_field											  ...	 RW SHURK_WCK_FS_MCK_0_1[3:0]=4'h2 (Mirror: 4'h1)			  
+	  WCK_FS_B1_MCK 							   uvm_reg_field											  ...	 RW SHURK_WCK_FS_MCK_0_1[7:4]=4'h2 (Mirror: 4'h1)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) |
+			P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_WCK_WR_UI_0_0 						   ral_reg_DRAMC_blk_SHURK_WCK_WR_UI_0_0					  - 	@4966														  
+	  WCK_WR_B0_UI								   uvm_reg_field											  ...	 RW SHURK_WCK_WR_UI_0_0[3:0]=4'h3 (Mirror: 4'h1)			  
+	  WCK_WR_B1_UI								   uvm_reg_field											  ...	 RW SHURK_WCK_WR_UI_0_0[7:4]=4'h3 (Mirror: 4'h1)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_UI, P_Fld(0x3, SHURK_WCK_WR_UI_WCK_WR_B0_UI) |
+			P_Fld(0x3, SHURK_WCK_WR_UI_WCK_WR_B1_UI));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_WCK_WR_UI_0_1 						   ral_reg_DRAMC_blk_SHURK_WCK_WR_UI_0_1					  - 	@4971														  
+	  WCK_WR_B0_UI								   uvm_reg_field											  ...	 RW SHURK_WCK_WR_UI_0_1[3:0]=4'h3 (Mirror: 4'h1)			  
+	  WCK_WR_B1_UI								   uvm_reg_field											  ...	 RW SHURK_WCK_WR_UI_0_1[7:4]=4'h3 (Mirror: 4'h1)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_UI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_WCK_WR_UI_WCK_WR_B0_UI) |
+			P_Fld(0x3, SHURK_WCK_WR_UI_WCK_WR_B1_UI));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_WCK_RD_UI_0_0 						   ral_reg_DRAMC_blk_SHURK_WCK_RD_UI_0_0					  - 	@4976														  
+	  WCK_RD_B0_UI								   uvm_reg_field											  ...	 RW SHURK_WCK_RD_UI_0_0[3:0]=4'h3 (Mirror: 4'h1)			  
+	  WCK_RD_B1_UI								   uvm_reg_field											  ...	 RW SHURK_WCK_RD_UI_0_0[7:4]=4'h3 (Mirror: 4'h1)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+    #if LP5_DDR4266_RDBI_WORKAROUND
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI, P_Fld(0x3, SHURK_WCK_RD_UI_WCK_RD_B0_UI) |
+			P_Fld(0x3, SHURK_WCK_RD_UI_WCK_RD_B1_UI));
+    #else
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI, P_Fld(0xb, SHURK_WCK_RD_UI_WCK_RD_B0_UI) |
+            P_Fld(0xb, SHURK_WCK_RD_UI_WCK_RD_B1_UI));
+    #endif
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_WCK_RD_UI_0_1 						   ral_reg_DRAMC_blk_SHURK_WCK_RD_UI_0_1					  - 	@4981														  
+	  WCK_RD_B0_UI								   uvm_reg_field											  ...	 RW SHURK_WCK_RD_UI_0_1[3:0]=4'h3 (Mirror: 4'h1)			  
+	  WCK_RD_B1_UI								   uvm_reg_field											  ...	 RW SHURK_WCK_RD_UI_0_1[7:4]=4'h3 (Mirror: 4'h1)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+    #if LP5_DDR4266_RDBI_WORKAROUND
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_WCK_RD_UI_WCK_RD_B0_UI) |
+			P_Fld(0x3, SHURK_WCK_RD_UI_WCK_RD_B1_UI));
+    #else
+    vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0xb, SHURK_WCK_RD_UI_WCK_RD_B0_UI) |
+            P_Fld(0xb, SHURK_WCK_RD_UI_WCK_RD_B1_UI));
+    #endif
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_WCK_FS_UI_0_0 						   ral_reg_DRAMC_blk_SHURK_WCK_FS_UI_0_0					  - 	@4986														  
+	  WCK_FS_B0_UI								   uvm_reg_field											  ...	 RW SHURK_WCK_FS_UI_0_0[3:0]=4'hb (Mirror: 4'h1)			  
+	  WCK_FS_B1_UI								   uvm_reg_field											  ...	 RW SHURK_WCK_FS_UI_0_0[7:4]=4'hb (Mirror: 4'h1)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI, P_Fld(0xb, SHURK_WCK_FS_UI_WCK_FS_B0_UI) |
+			P_Fld(0xb, SHURK_WCK_FS_UI_WCK_FS_B1_UI));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_WCK_FS_UI_0_1 						   ral_reg_DRAMC_blk_SHURK_WCK_FS_UI_0_1					  - 	@4991														  
+	  WCK_FS_B0_UI								   uvm_reg_field											  ...	 RW SHURK_WCK_FS_UI_0_1[3:0]=4'hb (Mirror: 4'h1)			  
+	  WCK_FS_B1_UI								   uvm_reg_field											  ...	 RW SHURK_WCK_FS_UI_0_1[7:4]=4'hb (Mirror: 4'h1)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0xb, SHURK_WCK_FS_UI_WCK_FS_B0_UI) |
+			P_Fld(0xb, SHURK_WCK_FS_UI_WCK_FS_B1_UI));
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Exit
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Enter:
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_SELPH_CA1_0 							   ral_reg_DRAMC_blk_SHU_SELPH_CA1_0						  - 	@5041														  
+	  TXDLY_CS									   uvm_reg_field											  ...	 RW SHU_SELPH_CA1_0[2:0]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_CKE 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA1_0[6:4]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_ODT 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA1_0[10:8]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_RESET								   uvm_reg_field											  ...	 RW SHU_SELPH_CA1_0[14:12]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_WE									   uvm_reg_field											  ...	 RW SHU_SELPH_CA1_0[18:16]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_CAS 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA1_0[22:20]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_RAS 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA1_0[26:24]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_CS1 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA1_0[30:28]=3'h0 (Mirror: 3'h1)				  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) |
+			P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) |
+			P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) |
+			P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) |
+			P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_SELPH_CA2_0 							   ral_reg_DRAMC_blk_SHU_SELPH_CA2_0						  - 	@5052														  
+	  TXDLY_BA0 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA2_0[2:0]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_BA1 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA2_0[6:4]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_BA2 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA2_0[10:8]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_CMD 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA2_0[20:16]=5'h01							  
+	  TXDLY_CKE1								   uvm_reg_field											  ...	 RW SHU_SELPH_CA2_0[26:24]=3'h0 (Mirror: 3'h1)				  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) |
+			P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) |
+			P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_SELPH_CA3_0 							   ral_reg_DRAMC_blk_SHU_SELPH_CA3_0						  - 	@5060														  
+	  TXDLY_RA0 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA3_0[2:0]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_RA1 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA3_0[6:4]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_RA2 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA3_0[10:8]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_RA3 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA3_0[14:12]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_RA4 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA3_0[18:16]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_RA5 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA3_0[22:20]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_RA6 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA3_0[26:24]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_RA7 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA3_0[30:28]=3'h0 (Mirror: 3'h1)				  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) |
+			P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) |
+			P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) |
+			P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) |
+			P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_SELPH_CA4_0 							   ral_reg_DRAMC_blk_SHU_SELPH_CA4_0						  - 	@5071														  
+	  TXDLY_RA8 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA4_0[2:0]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_RA9 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA4_0[6:4]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_RA10								   uvm_reg_field											  ...	 RW SHU_SELPH_CA4_0[10:8]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_RA11								   uvm_reg_field											  ...	 RW SHU_SELPH_CA4_0[14:12]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_RA12								   uvm_reg_field											  ...	 RW SHU_SELPH_CA4_0[18:16]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_RA13								   uvm_reg_field											  ...	 RW SHU_SELPH_CA4_0[22:20]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_RA14								   uvm_reg_field											  ...	 RW SHU_SELPH_CA4_0[26:24]=3'h0 (Mirror: 3'h1)				  
+	  TXDLY_RA15								   uvm_reg_field											  ...	 RW SHU_SELPH_CA4_0[30:28]=3'h0 (Mirror: 3'h1)				  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) |
+			P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) |
+			P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) |
+			P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) |
+			P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_SELPH_CA5_0 							   ral_reg_DRAMC_blk_SHU_SELPH_CA5_0						  - 	@5082														  
+	  dly_CS									   uvm_reg_field											  ...	 RW SHU_SELPH_CA5_0[2:0]=3'h1								  
+	  dly_CKE									   uvm_reg_field											  ...	 RW SHU_SELPH_CA5_0[6:4]=3'h1								  
+	  dly_ODT									   uvm_reg_field											  ...	 RW SHU_SELPH_CA5_0[10:8]=3'h0 (Mirror: 3'h1)				  
+	  dly_RESET 								   uvm_reg_field											  ...	 RW SHU_SELPH_CA5_0[14:12]=3'h1 							  
+	  dly_WE									   uvm_reg_field											  ...	 RW SHU_SELPH_CA5_0[18:16]=3'h1 							  
+	  dly_CAS									   uvm_reg_field											  ...	 RW SHU_SELPH_CA5_0[22:20]=3'h1 							  
+	  dly_RAS									   uvm_reg_field											  ...	 RW SHU_SELPH_CA5_0[26:24]=3'h1 							  
+	  dly_CS1									   uvm_reg_field											  ...	 RW SHU_SELPH_CA5_0[30:28]=3'h1 							  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5, P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) |
+			P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) |
+			P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) |
+			P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) |
+			P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1));
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Exit
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter:
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_SREF_CTRL_0 							   ral_reg_DRAMC_blk_SHU_SREF_CTRL_0						  - 	@5018														  
+	  CKEHCMD									   uvm_reg_field											  ...	 RW SHU_SREF_CTRL_0[5:4]=2'h0 (Mirror: 2'h3)				  
+	  SREF_CK_DLY								   uvm_reg_field											  ...	 RW SHU_SREF_CTRL_0[29:28]=2'h0 							  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x0, SHU_SREF_CTRL_CKEHCMD) |
+			P_Fld(0x0, SHU_SREF_CTRL_SREF_CK_DLY));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_HMR4_DVFS_CTRL0_0						   ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0					  - 	@5036														  
+	  FSPCHG_PRDCNT 							   uvm_reg_field											  ...	 RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h67 (Mirror: 8'h00)		  
+	  REFRCNT									   uvm_reg_field											  ...	 RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000					  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x67, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+			P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_AC_TIME_05T_0							   ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0						  - 	@5199														  
+	  TRC_05T									   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[0:0]=1'h1 (Mirror: 1'h0)				  
+	  TRFCPB_05T								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[1:1]=1'h0 							  
+	  TRFC_05T									   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[2:2]=1'h1 (Mirror: 1'h0)				  
+	  TPBR2PBR_05T								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[3:3]=1'h1 (Mirror: 1'h0)				  
+	  TXP_05T									   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[4:4]=1'h1 (Mirror: 1'h0)				  
+	  TRTP_05T									   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[5:5]=1'h0 							  
+	  TRCD_05T									   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[6:6]=1'h1 (Mirror: 1'h0)				  
+	  TRP_05T									   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[7:7]=1'h0 							  
+	  TRPAB_05T 								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[8:8]=1'h0 							  
+	  TRAS_05T									   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[9:9]=1'h0 							  
+	  TWR_M05T									   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0)			  
+	  TRRD_05T									   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[12:12]=1'h1 (Mirror: 1'h0)			  
+	  TFAW_05T									   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[13:13]=1'h1 (Mirror: 1'h0)			  
+	  TCKEPRD_05T								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[14:14]=1'h0							  
+	  TR2PD_05T 								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[15:15]=1'h0							  
+	  TWTPD_M05T								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[16:16]=1'h0							  
+	  TMRRI_05T 								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[17:17]=1'h1 (Mirror: 1'h0)			  
+	  TMRWCKEL_05T								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[18:18]=1'h1 (Mirror: 1'h0)			  
+	  BGTRRD_05T								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[19:19]=1'h0							  
+	  BGTCCD_05T								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[20:20]=1'h0							  
+	  BGTWTR_M05T								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[21:21]=1'h0							  
+	  TR2W_05T									   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[22:22]=1'h1 (Mirror: 1'h0)			  
+	  TWTR_M05T 								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[23:23]=1'h0							  
+	  XRTR2W_05T								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[24:24]=1'h0							  
+	  TMRD_05T									   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[25:25]=1'h1 (Mirror: 1'h0)			  
+	  TMRW_05T									   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[26:26]=1'h0							  
+	  TMRR2MRW_05T								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[27:27]=1'h1 (Mirror: 1'h0)			  
+	  TW2MRW_05T								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[28:28]=1'h1 (Mirror: 1'h0)			  
+	  TR2MRW_05T								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[29:29]=1'h0							  
+	  TPBR2ACT_05T								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[30:30]=1'h1 (Mirror: 1'h0)			  
+	  XRTW2R_M05T								   uvm_reg_field											  ...	 RW SHU_AC_TIME_05T_0[31:31]=1'h1 (Mirror: 1'h0)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x1, SHU_AC_TIME_05T_TRC_05T) |
+			P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRFC_05T) |
+			P_Fld(0x1, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TXP_05T) |
+			P_Fld(0x0, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRCD_05T) |
+			P_Fld(0x0, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) |
+			P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) |
+			P_Fld(0x1, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TFAW_05T) |
+			P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) |
+			P_Fld(0x0, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRRI_05T) |
+			P_Fld(0x1, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) |
+			P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTWTR_M05T) |
+			P_Fld(0x1, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TWTR_M05T) |
+			P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRD_05T) |
+			P_Fld(0x0, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRR2MRW_05T) |
+			P_Fld(0x1, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) |
+			P_Fld(0x1, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x1, SHU_AC_TIME_05T_XRTW2R_M05T));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_ACTIM_XRT_0 							   ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0						  - 	@5192														  
+	  XRTR2R									   uvm_reg_field											  ...	 RW SHU_ACTIM_XRT_0[4:0]=5'h1b (Mirror: 5'h01)				  
+	  XRTR2W									   uvm_reg_field											  ...	 RW SHU_ACTIM_XRT_0[13:8]=6'h27 (Mirror: 6'h01) 			  
+	  XRTW2R									   uvm_reg_field											  ...	 RW SHU_ACTIM_XRT_0[19:16]=4'h8 (Mirror: 4'h1)				  
+	  XRTW2W									   uvm_reg_field											  ...	 RW SHU_ACTIM_XRT_0[28:24]=5'h00 (Mirror: 5'h01)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x1b, SHU_ACTIM_XRT_XRTR2R) |
+			P_Fld(0x27, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x8, SHU_ACTIM_XRT_XRTW2R) |
+			P_Fld(0x00, SHU_ACTIM_XRT_XRTW2W));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_ACTIM0_0								   ral_reg_DRAMC_blk_SHU_ACTIM0_0							  - 	@5138														  
+	  TWTR										   uvm_reg_field											  ...	 RW SHU_ACTIM0_0[3:0]=4'h6 (Mirror: 4'h1)					  
+	  CKELCKCNT 								   uvm_reg_field											  ...	 RW SHU_ACTIM0_0[6:4]=3'h2 (Mirror: 3'h0)					  
+	  TWR										   uvm_reg_field											  ...	 RW SHU_ACTIM0_0[15:8]=8'hba (Mirror: 8'h06)				  
+	  TRRD										   uvm_reg_field											  ...	 RW SHU_ACTIM0_0[18:16]=3'h0								  
+	  TRCD										   uvm_reg_field											  ...	 RW SHU_ACTIM0_0[27:24]=4'ha (Mirror: 4'h2) 				  
+	  TWTR_L									   uvm_reg_field											  ...	 RW SHU_ACTIM0_0[31:28]=4'hf (Mirror: 4'h0) 				  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x6, SHU_ACTIM0_TWTR) |
+			P_Fld(0x2, SHU_ACTIM0_CKELCKCNT) | P_Fld(0xba, SHU_ACTIM0_TWR) |
+			P_Fld(0x0, SHU_ACTIM0_TRRD) | P_Fld(0xa, SHU_ACTIM0_TRCD) |
+			P_Fld(0xf, SHU_ACTIM0_TWTR_L));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_ACTIM1_0								   ral_reg_DRAMC_blk_SHU_ACTIM1_0							  - 	@5147														  
+	  TRPAB 									   uvm_reg_field											  ...	 RW SHU_ACTIM1_0[3:0]=4'hd (Mirror: 4'ha)					  
+	  TMRWCKEL									   uvm_reg_field											  ...	 RW SHU_ACTIM1_0[7:4]=4'h1 (Mirror: 4'h8)					  
+	  TRP										   uvm_reg_field											  ...	 RW SHU_ACTIM1_0[11:8]=4'h6 (Mirror: 4'h2)					  
+	  TRAS										   uvm_reg_field											  ...	 RW SHU_ACTIM1_0[21:16]=6'h07 (Mirror: 6'h04)				  
+	  TRC										   uvm_reg_field											  ...	 RW SHU_ACTIM1_0[28:24]=5'h13 (Mirror: 5'h05)				  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0xd, SHU_ACTIM1_TRPAB) |
+			P_Fld(0x1, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x6, SHU_ACTIM1_TRP) |
+			P_Fld(0x07, SHU_ACTIM1_TRAS) | P_Fld(0x13, SHU_ACTIM1_TRC));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_ACTIM2_0								   ral_reg_DRAMC_blk_SHU_ACTIM2_0							  - 	@5155														  
+	  TXP										   uvm_reg_field											  ...	 RW SHU_ACTIM2_0[3:0]=4'ha (Mirror: 4'h0)					  
+	  TMRRI 									   uvm_reg_field											  ...	 RW SHU_ACTIM2_0[8:4]=5'h17 (Mirror: 5'h0e) 				  
+	  TRTP										   uvm_reg_field											  ...	 RW SHU_ACTIM2_0[14:12]=3'h3 (Mirror: 3'h0) 				  
+	  TR2W										   uvm_reg_field											  ...	 RW SHU_ACTIM2_0[21:16]=6'h33 (Mirror: 6'h00)				  
+	  TFAW										   uvm_reg_field											  ...	 RW SHU_ACTIM2_0[28:24]=5'h1c (Mirror: 5'h05)				  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0xa, SHU_ACTIM2_TXP) |
+			P_Fld(0x17, SHU_ACTIM2_TMRRI) | P_Fld(0x3, SHU_ACTIM2_TRTP) |
+			P_Fld(0x33, SHU_ACTIM2_TR2W) | P_Fld(0x1c, SHU_ACTIM2_TFAW));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_ACTIM3_0								   ral_reg_DRAMC_blk_SHU_ACTIM3_0							  - 	@5163														  
+	  TRFCPB									   uvm_reg_field											  ...	 RW SHU_ACTIM3_0[7:0]=8'h2b (Mirror: 8'h00) 				  
+	  MANTMRR									   uvm_reg_field											  ...	 RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0)					  
+	  TR2MRR									   uvm_reg_field											  ...	 RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0) 				  
+	  TRFC										   uvm_reg_field											  ...	 RW SHU_ACTIM3_0[23:16]=8'h4c (Mirror: 8'h00)				  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x2b, SHU_ACTIM3_TRFCPB) |
+			P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) |
+			P_Fld(0x4c, SHU_ACTIM3_TRFC));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_ACTIM4_0								   ral_reg_DRAMC_blk_SHU_ACTIM4_0							  - 	@5170														  
+	  TXREFCNT									   uvm_reg_field											  ...	 RW SHU_ACTIM4_0[9:0]=10'h197 (Mirror: 10'h028) 			  
+	  TMRR2MRW									   uvm_reg_field											  ...	 RW SHU_ACTIM4_0[15:10]=6'h0d (Mirror: 6'h00)				  
+	  TMRR2W									   uvm_reg_field											  ...	 RW SHU_ACTIM4_0[21:16]=6'h1f (Mirror: 6'h00)				  
+	  TZQCS 									   uvm_reg_field											  ...	 RW SHU_ACTIM4_0[31:24]=8'h12 (Mirror: 8'h00)				  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x197, SHU_ACTIM4_TXREFCNT) |
+			P_Fld(0x0d, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x1f, SHU_ACTIM4_TMRR2W) |
+			P_Fld(0x12, SHU_ACTIM4_TZQCS));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_ACTIM5_0								   ral_reg_DRAMC_blk_SHU_ACTIM5_0							  - 	@5177														  
+	  TR2PD 									   uvm_reg_field											  ...	 RW SHU_ACTIM5_0[6:0]=7'h0a (Mirror: 7'h00) 				  
+	  TWTPD 									   uvm_reg_field											  ...	 RW SHU_ACTIM5_0[14:8]=7'h6a (Mirror: 7'h00)				  
+	  TPBR2PBR									   uvm_reg_field											  ...	 RW SHU_ACTIM5_0[23:16]=8'h82 (Mirror: 8'h00)				  
+	  TPBR2ACT									   uvm_reg_field											  ...	 RW SHU_ACTIM5_0[29:28]=2'h3 (Mirror: 2'h0) 				  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x0a, SHU_ACTIM5_TR2PD) |
+			P_Fld(0x6a, SHU_ACTIM5_TWTPD) | P_Fld(0x82, SHU_ACTIM5_TPBR2PBR) |
+			P_Fld(0x3, SHU_ACTIM5_TPBR2ACT));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_ACTIM6_0								   ral_reg_DRAMC_blk_SHU_ACTIM6_0							  - 	@5184														  
+	  TZQLAT2									   uvm_reg_field											  ...	 RW SHU_ACTIM6_0[4:0]=5'h04 (Mirror: 5'h1f) 				  
+	  TMRD										   uvm_reg_field											  ...	 RW SHU_ACTIM6_0[11:8]=4'h7 (Mirror: 4'h0)					  
+	  TMRW										   uvm_reg_field											  ...	 RW SHU_ACTIM6_0[15:12]=4'h4 (Mirror: 4'h0) 				  
+	  TW2MRW									   uvm_reg_field											  ...	 RW SHU_ACTIM6_0[25:20]=6'h30 (Mirror: 6'h00)				  
+	  TR2MRW									   uvm_reg_field											  ...	 RW SHU_ACTIM6_0[31:26]=6'h1c (Mirror: 6'h13)				  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x04, SHU_ACTIM6_TZQLAT2) |
+			P_Fld(0x7, SHU_ACTIM6_TMRD) | P_Fld(0x4, SHU_ACTIM6_TMRW) |
+			P_Fld(0x30, SHU_ACTIM6_TW2MRW) | P_Fld(0x1c, SHU_ACTIM6_TR2MRW));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_CKECTRL_0								   ral_reg_DRAMC_blk_SHU_CKECTRL_0							  - 	@5262														  
+	  TPDE_05T									   uvm_reg_field											  ...	 RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0)					  
+	  TPDX_05T									   uvm_reg_field											  ...	 RW SHU_CKECTRL_0[1:1]=1'h0 								  
+	  TPDE										   uvm_reg_field											  ...	 RW SHU_CKECTRL_0[14:12]=3'h4 (Mirror: 3'h1)				  
+	  TPDX										   uvm_reg_field											  ...	 RW SHU_CKECTRL_0[18:16]=3'h0 (Mirror: 3'h1)				  
+	  TCKEPRD									   uvm_reg_field											  ...	 RW SHU_CKECTRL_0[22:20]=3'h5 (Mirror: 3'h2)				  
+	  TCKESRX									   uvm_reg_field											  ...	 RW SHU_CKECTRL_0[25:24]=2'h1 (Mirror: 2'h0)				  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) |
+			P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x4, SHU_CKECTRL_TPDE) |
+			P_Fld(0x0, SHU_CKECTRL_TPDX) | P_Fld(0x5, SHU_CKECTRL_TCKEPRD) |
+			P_Fld(0x1, SHU_CKECTRL_TCKESRX));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_MISC_0									   ral_reg_DRAMC_blk_SHU_MISC_0 							  - 	@5365														  
+	  REQQUE_MAXCNT 							   uvm_reg_field											  ...	 RW SHU_MISC_0[3:0]=4'h2									  
+	  DCMDLYREF 								   uvm_reg_field											  ...	 RW SHU_MISC_0[18:16]=3'h1 (Mirror: 3'h4)					  
+	  DAREFEN									   uvm_reg_field											  ...	 RW SHU_MISC_0[30:30]=1'h0									  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) |
+			P_Fld(0x1, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_LP5_CMD_0								   ral_reg_DRAMC_blk_SHU_LP5_CMD_0							  - 	@5427														  
+	  LP5_CMD1TO2EN 							   uvm_reg_field											  ...	 RW SHU_LP5_CMD_0[0:0]=1'h0 								  
+	  TCSH										   uvm_reg_field											  ...	 RW SHU_LP5_CMD_0[7:4]=4'hb (Mirror: 4'h0)					  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_LP5_CMD, P_Fld(0x0, SHU_LP5_CMD_LP5_CMD1TO2EN) |
+			P_Fld(0xb, SHU_LP5_CMD_TCSH));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_ACTIM7_0								   ral_reg_DRAMC_blk_SHU_ACTIM7_0							  - 	@5436														  
+	  TCSH_CSCAL								   uvm_reg_field											  ...	 RW SHU_ACTIM7_0[3:0]=4'hb (Mirror: 4'h0)					  
+	  TCACSH									   uvm_reg_field											  ...	 RW SHU_ACTIM7_0[7:4]=4'h2 (Mirror: 4'h0)					  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM7, P_Fld(0xb, SHU_ACTIM7_TCSH_CSCAL) |
+			P_Fld(0x2, SHU_ACTIM7_TCACSH));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_WCKCTRL_0								   ral_reg_DRAMC_blk_SHU_WCKCTRL_0							  - 	@5407														  
+	  WCKRDOFF									   uvm_reg_field											  ...	 RW SHU_WCKCTRL_0[5:0]=6'h18 (Mirror: 6'h00)				  
+	  WCKRDOFF_05T								   uvm_reg_field											  ...	 RW SHU_WCKCTRL_0[7:7]=1'h1 (Mirror: 1'h0)					  
+	  WCKWROFF									   uvm_reg_field											  ...	 RW SHU_WCKCTRL_0[13:8]=6'h02 (Mirror: 6'h00)				  
+	  WCKWROFF_05T								   uvm_reg_field											  ...	 RW SHU_WCKCTRL_0[15:15]=1'h1 (Mirror: 1'h0)				  
+	  WCKDUAL									   uvm_reg_field											  ...	 RW SHU_WCKCTRL_0[16:16]=1'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_WCKCTRL, P_Fld(0x18, SHU_WCKCTRL_WCKRDOFF) |
+			P_Fld(0x1, SHU_WCKCTRL_WCKRDOFF_05T) | P_Fld(0x02, SHU_WCKCTRL_WCKWROFF) |
+			P_Fld(0x1, SHU_WCKCTRL_WCKWROFF_05T) | P_Fld(0x0, SHU_WCKCTRL_WCKDUAL));
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter.
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit.
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B0_DQ8_0								   ral_reg_DDRPHY_blk_SHU_B0_DQ8_0							  - 	@7828														  
+	  R_DMRXDVS_UPD_FORCE_CYC_B0				   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[14:0]=15'h0157 (Mirror: 15'h0000)			  
+	  R_DMRXDVS_UPD_FORCE_EN_B0 				   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[15:15]=1'h0								  
+	  R_DMRANK_RXDLY_PIPE_CG_IG_B0				   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[19:19]=1'h0								  
+	  R_RMRODTEN_CG_IG_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[20:20]=1'h0								  
+	  R_RMRX_TOPHY_CG_IG_B0 					   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) 				  
+	  R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 			   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[22:22]=1'h0								  
+	  R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 		   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[23:23]=1'h0								  
+	  R_DMRXDLY_CG_IG_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) 				  
+	  R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 			   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[26:26]=1'h0								  
+	  R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 			   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[27:27]=1'h0								  
+	  R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0			   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[28:28]=1'h0								  
+	  R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0		   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[29:29]=1'h0								  
+	  R_DMRANK_PIPE_CG_IG_B0					   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[30:30]=1'h0								  
+	  R_DMRANK_CHG_PIPE_CG_IG_B0				   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[31:31]=1'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0157, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+			P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+			P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+			P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+			P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+			P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+			P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+			P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B1_DQ8_0								   ral_reg_DDRPHY_blk_SHU_B1_DQ8_0							  - 	@9231														  
+	  R_DMRXDVS_UPD_FORCE_CYC_B1				   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[14:0]=15'h0157 (Mirror: 15'h0000)			  
+	  R_DMRXDVS_UPD_FORCE_EN_B1 				   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[15:15]=1'h0								  
+	  R_DMRANK_RXDLY_PIPE_CG_IG_B1				   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[19:19]=1'h0								  
+	  R_RMRODTEN_CG_IG_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[20:20]=1'h0								  
+	  R_RMRX_TOPHY_CG_IG_B1 					   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) 				  
+	  R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 			   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[22:22]=1'h0								  
+	  R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 		   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[23:23]=1'h0								  
+	  R_DMRXDLY_CG_IG_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) 				  
+	  R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 			   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[26:26]=1'h0								  
+	  R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 			   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[27:27]=1'h0								  
+	  R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1			   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[28:28]=1'h0								  
+	  R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1		   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[29:29]=1'h0								  
+	  R_DMRANK_PIPE_CG_IG_B1					   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[30:30]=1'h0								  
+	  R_DMRANK_CHG_PIPE_CG_IG_B1				   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[31:31]=1'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0157, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+			P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+			P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+			P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+			P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+			P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+			P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+			P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B0_DQ5_0								   ral_reg_DDRPHY_blk_SHU_B0_DQ5_0							  - 	@7728														  
+	  RG_RX_ARDQ_VREF_SEL_B0					   uvm_reg_field											  ...	 RW SHU_B0_DQ5_0[5:0]=6'h0e 								  
+	  RG_RX_ARDQ_VREF_BYPASS_B0 				   uvm_reg_field											  ...	 RW SHU_B0_DQ5_0[6:6]=1'h0									  
+	  RG_ARPI_FB_B0 							   uvm_reg_field											  ...	 RW SHU_B0_DQ5_0[13:8]=6'h00								  
+	  RG_RX_ARDQS0_DQSIEN_DLY_B0				   uvm_reg_field											  ...	 RW SHU_B0_DQ5_0[18:16]=3'h0								  
+	  RG_RX_ARDQS_DQSIEN_RB_DLY_B0				   uvm_reg_field											  ...	 RW SHU_B0_DQ5_0[19:19]=1'h0								  
+	  RG_RX_ARDQS0_DVS_DLY_B0					   uvm_reg_field											  ...	 RW SHU_B0_DQ5_0[23:20]=4'h2 (Mirror: 4'h0) 				  
+	  RG_RX_ARDQ_FIFO_DQSI_DLY_B0				   uvm_reg_field											  ...	 RW SHU_B0_DQ5_0[31:29]=3'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) |
+			P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) |
+			P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) |
+			P_Fld(0x2, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B1_DQ5_0								   ral_reg_DDRPHY_blk_SHU_B1_DQ5_0							  - 	@9131														  
+	  RG_RX_ARDQ_VREF_SEL_B1					   uvm_reg_field											  ...	 RW SHU_B1_DQ5_0[5:0]=6'h0e 								  
+	  RG_RX_ARDQ_VREF_BYPASS_B1 				   uvm_reg_field											  ...	 RW SHU_B1_DQ5_0[6:6]=1'h0									  
+	  RG_ARPI_FB_B1 							   uvm_reg_field											  ...	 RW SHU_B1_DQ5_0[13:8]=6'h00								  
+	  RG_RX_ARDQS0_DQSIEN_DLY_B1				   uvm_reg_field											  ...	 RW SHU_B1_DQ5_0[18:16]=3'h0								  
+	  RG_RX_ARDQS_DQSIEN_RB_DLY_B1				   uvm_reg_field											  ...	 RW SHU_B1_DQ5_0[19:19]=1'h0								  
+	  RG_RX_ARDQS0_DVS_DLY_B1					   uvm_reg_field											  ...	 RW SHU_B1_DQ5_0[23:20]=4'h2 (Mirror: 4'h0) 				  
+	  RG_RX_ARDQ_FIFO_DQSI_DLY_B1				   uvm_reg_field											  ...	 RW SHU_B1_DQ5_0[31:29]=3'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) |
+			P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) |
+			P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) |
+			P_Fld(0x2, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_RXDLY0_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0					  - 	@7490														  
+	  RX_ARDQ0_R_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h53 (Mirror: 8'h00) 		  
+	  RX_ARDQ0_F_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h53 (Mirror: 8'h00)		  
+	  RX_ARDQ1_R_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h53 (Mirror: 8'h00)		  
+	  RX_ARDQ1_F_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h53 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x53, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+			P_Fld(0x53, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x53, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
+			P_Fld(0x53, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_RXDLY1_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0					  - 	@7504														  
+	  RX_ARDQ2_R_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h53 (Mirror: 8'h00) 		  
+	  RX_ARDQ2_F_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h53 (Mirror: 8'h00)		  
+	  RX_ARDQ3_R_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h53 (Mirror: 8'h00)		  
+	  RX_ARDQ3_F_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h53 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x53, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+			P_Fld(0x53, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x53, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+			P_Fld(0x53, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_RXDLY2_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0					  - 	@7518														  
+	  RX_ARDQ4_R_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h53 (Mirror: 8'h00) 		  
+	  RX_ARDQ4_F_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h53 (Mirror: 8'h00)		  
+	  RX_ARDQ5_R_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h53 (Mirror: 8'h00)		  
+	  RX_ARDQ5_F_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h53 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x53, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+			P_Fld(0x53, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x53, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+			P_Fld(0x53, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_RXDLY3_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0					  - 	@7532														  
+	  RX_ARDQ6_R_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h53 (Mirror: 8'h00) 		  
+	  RX_ARDQ6_F_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h53 (Mirror: 8'h00)		  
+	  RX_ARDQ7_R_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h53 (Mirror: 8'h00)		  
+	  RX_ARDQ7_F_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h53 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x53, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+			P_Fld(0x53, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x53, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+			P_Fld(0x53, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_RXDLY4_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0					  - 	@7546														  
+	  RX_ARDQM0_R_DLY_B0						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h53 (Mirror: 8'h00) 		  
+	  RX_ARDQM0_F_DLY_B0						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h53 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x53, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+			P_Fld(0x53, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_RXDLY5_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0					  - 	@7556														  
+	  RX_ARDQS0_R_DLY_B0						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h00b (Mirror: 9'h000)		  
+	  RX_ARDQS0_F_DLY_B0						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h00b (Mirror: 9'h000) 	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x00b, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+			P_Fld(0x00b, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_RXDLY0_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1					  - 	@7497														  
+	  RX_ARDQ0_R_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h52 (Mirror: 8'h00) 		  
+	  RX_ARDQ0_F_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h52 (Mirror: 8'h00)		  
+	  RX_ARDQ1_R_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h52 (Mirror: 8'h00)		  
+	  RX_ARDQ1_F_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h52 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+			P_Fld(0x52, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x52, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
+			P_Fld(0x52, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_RXDLY1_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1					  - 	@7511														  
+	  RX_ARDQ2_R_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h52 (Mirror: 8'h00) 		  
+	  RX_ARDQ2_F_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h52 (Mirror: 8'h00)		  
+	  RX_ARDQ3_R_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h52 (Mirror: 8'h00)		  
+	  RX_ARDQ3_F_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h52 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
+			P_Fld(0x52, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x52, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
+			P_Fld(0x52, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_RXDLY2_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1					  - 	@7525														  
+	  RX_ARDQ4_R_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h52 (Mirror: 8'h00) 		  
+	  RX_ARDQ4_F_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h52 (Mirror: 8'h00)		  
+	  RX_ARDQ5_R_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h52 (Mirror: 8'h00)		  
+	  RX_ARDQ5_F_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h52 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
+			P_Fld(0x52, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x52, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
+			P_Fld(0x52, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_RXDLY3_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1					  - 	@7539														  
+	  RX_ARDQ6_R_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h52 (Mirror: 8'h00) 		  
+	  RX_ARDQ6_F_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h52 (Mirror: 8'h00)		  
+	  RX_ARDQ7_R_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h52 (Mirror: 8'h00)		  
+	  RX_ARDQ7_F_DLY_B0 						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h52 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
+			P_Fld(0x52, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x52, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
+			P_Fld(0x52, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_RXDLY4_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1					  - 	@7551														  
+	  RX_ARDQM0_R_DLY_B0						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h52 (Mirror: 8'h00) 		  
+	  RX_ARDQM0_F_DLY_B0						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h52 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+			P_Fld(0x52, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B0_RXDLY5_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1					  - 	@7561														  
+	  RX_ARDQS0_R_DLY_B0						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h00a (Mirror: 9'h000)		  
+	  RX_ARDQS0_F_DLY_B0						   uvm_reg_field											  ...	 RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h00a (Mirror: 9'h000) 	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x00a, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
+			P_Fld(0x00a, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_RXDLY0_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0					  - 	@8893														  
+	  RX_ARDQ0_R_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h53 (Mirror: 8'h00) 		  
+	  RX_ARDQ0_F_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h53 (Mirror: 8'h00)		  
+	  RX_ARDQ1_R_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h53 (Mirror: 8'h00)		  
+	  RX_ARDQ1_F_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h53 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x53, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+			P_Fld(0x53, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x53, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
+			P_Fld(0x53, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_RXDLY1_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0					  - 	@8907														  
+	  RX_ARDQ2_R_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h53 (Mirror: 8'h00) 		  
+	  RX_ARDQ2_F_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h53 (Mirror: 8'h00)		  
+	  RX_ARDQ3_R_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h53 (Mirror: 8'h00)		  
+	  RX_ARDQ3_F_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h53 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x53, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+			P_Fld(0x53, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x53, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+			P_Fld(0x53, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_RXDLY2_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0					  - 	@8921														  
+	  RX_ARDQ4_R_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h53 (Mirror: 8'h00) 		  
+	  RX_ARDQ4_F_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h53 (Mirror: 8'h00)		  
+	  RX_ARDQ5_R_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h53 (Mirror: 8'h00)		  
+	  RX_ARDQ5_F_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h53 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x53, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+			P_Fld(0x53, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x53, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+			P_Fld(0x53, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_RXDLY3_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0					  - 	@8935														  
+	  RX_ARDQ6_R_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h53 (Mirror: 8'h00) 		  
+	  RX_ARDQ6_F_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h53 (Mirror: 8'h00)		  
+	  RX_ARDQ7_R_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h53 (Mirror: 8'h00)		  
+	  RX_ARDQ7_F_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h53 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x53, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+			P_Fld(0x53, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x53, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+			P_Fld(0x53, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_RXDLY4_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0					  - 	@8949														  
+	  RX_ARDQM0_R_DLY_B1						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h53 (Mirror: 8'h00) 		  
+	  RX_ARDQM0_F_DLY_B1						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h53 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x53, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+			P_Fld(0x53, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_RXDLY5_0_0						   ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0					  - 	@8959														  
+	  RX_ARDQS0_R_DLY_B1						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h00b (Mirror: 9'h000)		  
+	  RX_ARDQS0_F_DLY_B1						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h00b (Mirror: 9'h000) 	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x00b, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+			P_Fld(0x00b, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_RXDLY0_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1					  - 	@8900														  
+	  RX_ARDQ0_R_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h52 (Mirror: 8'h00) 		  
+	  RX_ARDQ0_F_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h52 (Mirror: 8'h00)		  
+	  RX_ARDQ1_R_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h52 (Mirror: 8'h00)		  
+	  RX_ARDQ1_F_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h52 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+			P_Fld(0x52, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x52, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
+			P_Fld(0x52, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_RXDLY1_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1					  - 	@8914														  
+	  RX_ARDQ2_R_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h52 (Mirror: 8'h00) 		  
+	  RX_ARDQ2_F_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h52 (Mirror: 8'h00)		  
+	  RX_ARDQ3_R_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h52 (Mirror: 8'h00)		  
+	  RX_ARDQ3_F_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h52 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
+			P_Fld(0x52, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x52, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
+			P_Fld(0x52, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_RXDLY2_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1					  - 	@8928														  
+	  RX_ARDQ4_R_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h52 (Mirror: 8'h00) 		  
+	  RX_ARDQ4_F_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h52 (Mirror: 8'h00)		  
+	  RX_ARDQ5_R_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h52 (Mirror: 8'h00)		  
+	  RX_ARDQ5_F_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h52 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
+			P_Fld(0x52, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x52, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
+			P_Fld(0x52, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_RXDLY3_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1					  - 	@8942														  
+	  RX_ARDQ6_R_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h52 (Mirror: 8'h00) 		  
+	  RX_ARDQ6_F_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h52 (Mirror: 8'h00)		  
+	  RX_ARDQ7_R_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h52 (Mirror: 8'h00)		  
+	  RX_ARDQ7_F_DLY_B1 						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h52 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
+			P_Fld(0x52, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x52, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
+			P_Fld(0x52, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_RXDLY4_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1					  - 	@8954														  
+	  RX_ARDQM0_R_DLY_B1						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h52 (Mirror: 8'h00) 		  
+	  RX_ARDQM0_F_DLY_B1						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h52 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+			P_Fld(0x52, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_R0_B1_RXDLY5_0_1						   ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1					  - 	@8964														  
+	  RX_ARDQS0_R_DLY_B1						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h00a (Mirror: 9'h000)		  
+	  RX_ARDQS0_F_DLY_B1						   uvm_reg_field											  ...	 RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h00a (Mirror: 9'h000) 	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x00a, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
+			P_Fld(0x00a, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	B0_DQ9										   ral_reg_DDRPHY_blk_B0_DQ9								  - 	@7384														  
+	  RG_RX_ARDQ_STBEN_RESETB_B0				   uvm_reg_field											  ...	 RW B0_DQ9[0:0]=1'h0 (Mirror: 1'h1) 						  
+	  RG_RX_ARDQS0_STBEN_RESETB_B0				   uvm_reg_field											  ...	 RW B0_DQ9[4:4]=1'h1										  
+	  RG_RX_ARDQS0_DQSIENMODE_B0				   uvm_reg_field											  ...	 RW B0_DQ9[5:5]=1'h0										  
+	  R_DMRXDVS_R_F_DLY_RK_OPT_B0				   uvm_reg_field											  ...	 RW B0_DQ9[6:6]=1'h1										  
+	  R_DMRXFIFO_STBENCMP_EN_B0 				   uvm_reg_field											  ...	 RW B0_DQ9[7:7]=1'h0										  
+	  R_IN_GATE_EN_LOW_OPT_B0					   uvm_reg_field											  ...	 RW B0_DQ9[15:8]=8'h00										  
+	  R_DMDQSIEN_VALID_LAT_B0					   uvm_reg_field											  ...	 RW B0_DQ9[18:16]=3'h0										  
+	  R_DMDQSIEN_RDSEL_LAT_B0					   uvm_reg_field											  ...	 RW B0_DQ9[22:20]=3'h0										  
+	  R_DMRXDVS_VALID_LAT_B0					   uvm_reg_field											  ...	 RW B0_DQ9[26:24]=3'h0										  
+	  R_DMRXDVS_RDSEL_LAT_B0					   uvm_reg_field											  ...	 RW B0_DQ9[30:28]=3'h0										  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
+			P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
+			P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
+			P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
+			P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
+			P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	B1_DQ9										   ral_reg_DDRPHY_blk_B1_DQ9								  - 	@8787														  
+	  RG_RX_ARDQ_STBEN_RESETB_B1				   uvm_reg_field											  ...	 RW B1_DQ9[0:0]=1'h0 (Mirror: 1'h1) 						  
+	  RG_RX_ARDQS0_STBEN_RESETB_B1				   uvm_reg_field											  ...	 RW B1_DQ9[4:4]=1'h1										  
+	  RG_RX_ARDQS0_DQSIENMODE_B1				   uvm_reg_field											  ...	 RW B1_DQ9[5:5]=1'h0										  
+	  R_DMRXDVS_R_F_DLY_RK_OPT_B1				   uvm_reg_field											  ...	 RW B1_DQ9[6:6]=1'h1										  
+	  R_DMRXFIFO_STBENCMP_EN_B1 				   uvm_reg_field											  ...	 RW B1_DQ9[7:7]=1'h0										  
+	  R_IN_GATE_EN_LOW_OPT_B1					   uvm_reg_field											  ...	 RW B1_DQ9[15:8]=8'h00										  
+	  R_DMDQSIEN_VALID_LAT_B1					   uvm_reg_field											  ...	 RW B1_DQ9[18:16]=3'h0										  
+	  R_DMDQSIEN_RDSEL_LAT_B1					   uvm_reg_field											  ...	 RW B1_DQ9[22:20]=3'h0										  
+	  R_DMRXDVS_VALID_LAT_B1					   uvm_reg_field											  ...	 RW B1_DQ9[26:24]=3'h0										  
+	  R_DMRXDVS_RDSEL_LAT_B1					   uvm_reg_field											  ...	 RW B1_DQ9[30:28]=3'h0										  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
+			P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
+			P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
+			P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
+			P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
+			P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	B0_DQ9										   ral_reg_DDRPHY_blk_B0_DQ9								  - 	@7384														  
+	  RG_RX_ARDQ_STBEN_RESETB_B0				   uvm_reg_field											  ...	 RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) 						  
+	  RG_RX_ARDQS0_STBEN_RESETB_B0				   uvm_reg_field											  ...	 RW B0_DQ9[4:4]=1'h1										  
+	  RG_RX_ARDQS0_DQSIENMODE_B0				   uvm_reg_field											  ...	 RW B0_DQ9[5:5]=1'h0										  
+	  R_DMRXDVS_R_F_DLY_RK_OPT_B0				   uvm_reg_field											  ...	 RW B0_DQ9[6:6]=1'h1										  
+	  R_DMRXFIFO_STBENCMP_EN_B0 				   uvm_reg_field											  ...	 RW B0_DQ9[7:7]=1'h0										  
+	  R_IN_GATE_EN_LOW_OPT_B0					   uvm_reg_field											  ...	 RW B0_DQ9[15:8]=8'h00										  
+	  R_DMDQSIEN_VALID_LAT_B0					   uvm_reg_field											  ...	 RW B0_DQ9[18:16]=3'h0										  
+	  R_DMDQSIEN_RDSEL_LAT_B0					   uvm_reg_field											  ...	 RW B0_DQ9[22:20]=3'h0										  
+	  R_DMRXDVS_VALID_LAT_B0					   uvm_reg_field											  ...	 RW B0_DQ9[26:24]=3'h0										  
+	  R_DMRXDVS_RDSEL_LAT_B0					   uvm_reg_field											  ...	 RW B0_DQ9[30:28]=3'h0										  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
+			P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
+			P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
+			P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
+			P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
+			P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	B1_DQ9										   ral_reg_DDRPHY_blk_B1_DQ9								  - 	@8787														  
+	  RG_RX_ARDQ_STBEN_RESETB_B1				   uvm_reg_field											  ...	 RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) 						  
+	  RG_RX_ARDQS0_STBEN_RESETB_B1				   uvm_reg_field											  ...	 RW B1_DQ9[4:4]=1'h1										  
+	  RG_RX_ARDQS0_DQSIENMODE_B1				   uvm_reg_field											  ...	 RW B1_DQ9[5:5]=1'h0										  
+	  R_DMRXDVS_R_F_DLY_RK_OPT_B1				   uvm_reg_field											  ...	 RW B1_DQ9[6:6]=1'h1										  
+	  R_DMRXFIFO_STBENCMP_EN_B1 				   uvm_reg_field											  ...	 RW B1_DQ9[7:7]=1'h0										  
+	  R_IN_GATE_EN_LOW_OPT_B1					   uvm_reg_field											  ...	 RW B1_DQ9[15:8]=8'h00										  
+	  R_DMDQSIEN_VALID_LAT_B1					   uvm_reg_field											  ...	 RW B1_DQ9[18:16]=3'h0										  
+	  R_DMDQSIEN_RDSEL_LAT_B1					   uvm_reg_field											  ...	 RW B1_DQ9[22:20]=3'h0										  
+	  R_DMRXDVS_VALID_LAT_B1					   uvm_reg_field											  ...	 RW B1_DQ9[26:24]=3'h0										  
+	  R_DMRXDVS_RDSEL_LAT_B1					   uvm_reg_field											  ...	 RW B1_DQ9[30:28]=3'h0										  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
+			P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
+			P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
+			P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
+			P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
+			P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	B0_DQ4										   ral_reg_DDRPHY_blk_B0_DQ4								  - 	@7313														  
+	  RG_RX_ARDQS_EYE_R_DLY_B0					   uvm_reg_field											  ...	 RW B0_DQ4[6:0]=7'h57 (Mirror: 7'h00)						  
+	  RG_RX_ARDQS_EYE_F_DLY_B0					   uvm_reg_field											  ...	 RW B0_DQ4[14:8]=7'h57 (Mirror: 7'h00)						  
+	  RG_RX_ARDQ_EYE_R_DLY_B0					   uvm_reg_field											  ...	 RW B0_DQ4[21:16]=6'h13 (Mirror: 6'h00) 					  
+	  RG_RX_ARDQ_EYE_F_DLY_B0					   uvm_reg_field											  ...	 RW B0_DQ4[29:24]=6'h13 (Mirror: 6'h00) 					  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x57, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) |
+			P_Fld(0x57, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x13, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) |
+			P_Fld(0x13, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	B1_DQ4										   ral_reg_DDRPHY_blk_B1_DQ4								  - 	@8716														  
+	  RG_RX_ARDQS_EYE_R_DLY_B1					   uvm_reg_field											  ...	 RW B1_DQ4[6:0]=7'h57 (Mirror: 7'h00)						  
+	  RG_RX_ARDQS_EYE_F_DLY_B1					   uvm_reg_field											  ...	 RW B1_DQ4[14:8]=7'h57 (Mirror: 7'h00)						  
+	  RG_RX_ARDQ_EYE_R_DLY_B1					   uvm_reg_field											  ...	 RW B1_DQ4[21:16]=6'h13 (Mirror: 6'h00) 					  
+	  RG_RX_ARDQ_EYE_F_DLY_B1					   uvm_reg_field											  ...	 RW B1_DQ4[29:24]=6'h13 (Mirror: 6'h00) 					  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x57, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) |
+			P_Fld(0x57, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x13, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) |
+			P_Fld(0x13, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	B0_DQ5										   ral_reg_DDRPHY_blk_B0_DQ5								  - 	@7320														  
+	  RG_RX_ARDQ_EYE_VREF_SEL_B0				   uvm_reg_field											  ...	 RW B0_DQ5[13:8]=6'h10										  
+	  RG_RX_ARDQ_VREF_EN_B0 					   uvm_reg_field											  ...	 RW B0_DQ5[16:16]=1'h1										  
+	  RG_RX_ARDQ_EYE_VREF_EN_B0 				   uvm_reg_field											  ...	 RW B0_DQ5[17:17]=1'h1										  
+	  RG_RX_ARDQ_EYE_SEL_B0 					   uvm_reg_field											  ...	 RW B0_DQ5[23:20]=4'h0										  
+	  RG_RX_ARDQ_EYE_EN_B0						   uvm_reg_field											  ...	 RW B0_DQ5[24:24]=1'h1										  
+	  RG_RX_ARDQ_EYE_STBEN_RESETB_B0			   uvm_reg_field											  ...	 RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0)						  
+	  RG_RX_ARDQS0_DVS_EN_B0					   uvm_reg_field											  ...	 RW B0_DQ5[31:31]=1'h0										  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x10, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) |
+			P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) |
+			P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) |
+			P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	B1_DQ5										   ral_reg_DDRPHY_blk_B1_DQ5								  - 	@8723														  
+	  RG_RX_ARDQ_EYE_VREF_SEL_B1				   uvm_reg_field											  ...	 RW B1_DQ5[13:8]=6'h10										  
+	  RG_RX_ARDQ_VREF_EN_B1 					   uvm_reg_field											  ...	 RW B1_DQ5[16:16]=1'h1										  
+	  RG_RX_ARDQ_EYE_VREF_EN_B1 				   uvm_reg_field											  ...	 RW B1_DQ5[17:17]=1'h1										  
+	  RG_RX_ARDQ_EYE_SEL_B1 					   uvm_reg_field											  ...	 RW B1_DQ5[23:20]=4'h0										  
+	  RG_RX_ARDQ_EYE_EN_B1						   uvm_reg_field											  ...	 RW B1_DQ5[24:24]=1'h1										  
+	  RG_RX_ARDQ_EYE_STBEN_RESETB_B1			   uvm_reg_field											  ...	 RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0)						  
+	  RG_RX_ARDQS0_DVS_EN_B1					   uvm_reg_field											  ...	 RW B1_DQ5[31:31]=1'h0										  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x10, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) |
+			P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) |
+			P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) |
+			P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1));
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Enter
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_COMMON0_0								   ral_reg_DRAMC_blk_SHU_COMMON0_0							  - 	@5001														  
+	  FREQDIV4									   uvm_reg_field											  ...	 RW SHU_COMMON0_0[0:0]=1'h0 								  
+	  FDIV2 									   uvm_reg_field											  ...	 RW SHU_COMMON0_0[1:1]=1'h0 								  
+	  FREQDIV8									   uvm_reg_field											  ...	 RW SHU_COMMON0_0[2:2]=1'h1 (Mirror: 1'h0)					  
+	  DM64BITEN 								   uvm_reg_field											  ...	 RW SHU_COMMON0_0[4:4]=1'h0 								  
+	  DLE256EN									   uvm_reg_field											  ...	 RW SHU_COMMON0_0[5:5]=1'h1 (Mirror: 1'h0)					  
+	  LP5BGEN									   uvm_reg_field											  ...	 RW SHU_COMMON0_0[6:6]=1'h1 (Mirror: 1'h0)					  
+	  LP5WCKON									   uvm_reg_field											  ...	 RW SHU_COMMON0_0[7:7]=1'h1 (Mirror: 1'h0)					  
+	  CL2										   uvm_reg_field											  ...	 RW SHU_COMMON0_0[8:8]=1'h0 								  
+	  BL2										   uvm_reg_field											  ...	 RW SHU_COMMON0_0[9:9]=1'h0 								  
+	  BL4										   uvm_reg_field											  ...	 RW SHU_COMMON0_0[10:10]=1'h1 (Mirror: 1'h0)				  
+	  LP5BGOTF									   uvm_reg_field											  ...	 RW SHU_COMMON0_0[11:11]=1'h0								  
+	  BC4OTF									   uvm_reg_field											  ...	 RW SHU_COMMON0_0[12:12]=1'h1								  
+	  LP5HEFF_MODE								   uvm_reg_field											  ...	 RW SHU_COMMON0_0[13:13]=1'h1 (Mirror: 1'h0)				  
+	  SHU_COMMON0_RSV							   uvm_reg_field											  ...	 RW SHU_COMMON0_0[31:15]=17'h00000							  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0, P_Fld(0x0, SHU_COMMON0_FREQDIV4) |
+			P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x1, SHU_COMMON0_FREQDIV8) |
+			P_Fld(0x0, SHU_COMMON0_DM64BITEN) | P_Fld(0x1, SHU_COMMON0_DLE256EN) |
+			P_Fld(0x1, SHU_COMMON0_LP5BGEN) | P_Fld(0x1, SHU_COMMON0_LP5WCKON) |
+			P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) |
+			P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) |
+			P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x1, SHU_COMMON0_LP5HEFF_MODE) |
+			P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_ACTIMING_CONF_0 						   ral_reg_DRAMC_blk_SHU_ACTIMING_CONF_0					  - 	@5255														  
+	  SCINTV									   uvm_reg_field											  ...	 RW SHU_ACTIMING_CONF_0[5:0]=6'h26 (Mirror: 6'h2a)			  
+	  TRFCPBIG									   uvm_reg_field											  ...	 RW SHU_ACTIMING_CONF_0[8:8]=1'h0							  
+	  REFBW_FR									   uvm_reg_field											  ...	 RW SHU_ACTIMING_CONF_0[25:16]=10'h000						  
+	  TREFBWIG									   uvm_reg_field											  ...	 RW SHU_ACTIMING_CONF_0[31:31]=1'h1 (Mirror: 1'h0)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF, P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) |
+			P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) |
+			P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_DCM_CTRL0_0 							   ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0						  - 	@5027														  
+	  DDRPHY_CLK_EN_OPT 						   uvm_reg_field											  ...	 RW SHU_DCM_CTRL0_0[7:7]=1'h1								  
+	  DPHY_CMDDCM_EXTCNT						   uvm_reg_field											  ...	 RW SHU_DCM_CTRL0_0[11:8]=4'h4								  
+	  DDRPHY_CLK_DYN_GATING_SEL 				   uvm_reg_field											  ...	 RW SHU_DCM_CTRL0_0[15:12]=4'h5 							  
+	  CKE_EXTNONPD_CNT							   uvm_reg_field											  ...	 RW SHU_DCM_CTRL0_0[19:16]=4'h0 							  
+	  FASTWAKE2 								   uvm_reg_field											  ...	 RW SHU_DCM_CTRL0_0[29:29]=1'h1 (Mirror: 1'h0)				  
+	  FASTWAKE									   uvm_reg_field											  ...	 RW SHU_DCM_CTRL0_0[31:31]=1'h1 							  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
+			P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
+			P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) |
+			P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_CONF0_0 								   ral_reg_DRAMC_blk_SHU_CONF0_0							  - 	@5356														  
+	  DMPGTIM									   uvm_reg_field											  ...	 RW SHU_CONF0_0[5:0]=6'h3f (Mirror: 6'h08)					  
+	  ADVREFEN									   uvm_reg_field											  ...	 RW SHU_CONF0_0[6:6]=1'h0									  
+	  ADVPREEN									   uvm_reg_field											  ...	 RW SHU_CONF0_0[7:7]=1'h1 (Mirror: 1'h0)					  
+	  PBREFEN									   uvm_reg_field											  ...	 RW SHU_CONF0_0[8:8]=1'h1 (Mirror: 1'h0)					  
+	  REFTHD									   uvm_reg_field											  ...	 RW SHU_CONF0_0[15:12]=4'h1 (Mirror: 4'h0)					  
+	  REQQUE_DEPTH								   uvm_reg_field											  ...	 RW SHU_CONF0_0[19:16]=4'h8 								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x3f, SHU_CONF0_DMPGTIM) |
+			P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) |
+			P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) |
+			P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_MATYPE_0								   ral_reg_DRAMC_blk_SHU_MATYPE_0							  - 	@4996														  
+	  MATYPE									   uvm_reg_field											  ...	 RW SHU_MATYPE_0[1:0]=2'h2 (Mirror: 2'h0)					  
+	  NORMPOP_LEN								   uvm_reg_field											  ...	 RW SHU_MATYPE_0[6:4]=3'h1									  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE, P_Fld(0x2, SHU_MATYPE_MATYPE) |
+			P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_SCHEDULER_0 							   ral_reg_DRAMC_blk_SHU_SCHEDULER_0						  - 	@5023														  
+	  DUALSCHEN 								   uvm_reg_field											  ...	 RW SHU_SCHEDULER_0[2:2]=1'h1 (Mirror: 1'h0)				  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldAlign(DRAMC_REG_SHU_SCHEDULER, 0x1, SHU_SCHEDULER_DUALSCHEN);
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	TX_SET0 									   ral_reg_DRAMC_blk_TX_SET0								  - 	@3899														  
+	  TXRANK									   uvm_reg_field											  ...	 RW TX_SET0[1:0]=2'h0										  
+	  TXRANKFIX 								   uvm_reg_field											  ...	 RW TX_SET0[2:2]=1'h0										  
+	  DDRPHY_COMB_CG_SEL						   uvm_reg_field											  ...	 RW TX_SET0[3:3]=1'h0										  
+	  TX_DQM_DEFAULT							   uvm_reg_field											  ...	 RW TX_SET0[4:4]=1'h1										  
+	  DQBUS_X32 								   uvm_reg_field											  ...	 RW TX_SET0[5:5]=1'h0										  
+	  OE_DOWNGRADE								   uvm_reg_field											  ...	 RW TX_SET0[6:6]=1'h0										  
+	  DQ16COM1									   uvm_reg_field											  ...	 RW TX_SET0[21:21]=1'h0 									  
+	  WPRE2T									   uvm_reg_field											  ...	 RW TX_SET0[22:22]=1'h1 (Mirror: 1'h0)						  
+	  DRSCLR_EN 								   uvm_reg_field											  ...	 RW TX_SET0[24:24]=1'h0 									  
+	  DRSCLR_RK0_EN 							   uvm_reg_field											  ...	 RW TX_SET0[25:25]=1'h0 									  
+	  ARPI_CAL_E2OPT							   uvm_reg_field											  ...	 RW TX_SET0[26:26]=1'h0 									  
+	  TX_DLY_CAL_E2OPT							   uvm_reg_field											  ...	 RW TX_SET0[27:27]=1'h0 									  
+	  DQS_OE_OP1_DIS							   uvm_reg_field											  ...	 RW TX_SET0[28:28]=1'h0 									  
+	  DQS_OE_OP2_EN 							   uvm_reg_field											  ...	 RW TX_SET0[29:29]=1'h0 									  
+	  RK_SCINPUT_OPT							   uvm_reg_field											  ...	 RW TX_SET0[30:30]=1'h0 									  
+	  DRAMOEN									   uvm_reg_field											  ...	 RW TX_SET0[31:31]=1'h0 									  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_TX_SET0, P_Fld(0x0, TX_SET0_TXRANK) |
+			P_Fld(0x0, TX_SET0_TXRANKFIX) | P_Fld(0x0, TX_SET0_DDRPHY_COMB_CG_SEL) |
+			P_Fld(0x1, TX_SET0_TX_DQM_DEFAULT) | P_Fld(0x0, TX_SET0_DQBUS_X32) |
+			P_Fld(0x0, TX_SET0_OE_DOWNGRADE) | P_Fld(0x0, TX_SET0_DQ16COM1) |
+			P_Fld(0x1, TX_SET0_WPRE2T) | P_Fld(0x0, TX_SET0_DRSCLR_EN) |
+			P_Fld(0x0, TX_SET0_DRSCLR_RK0_EN) | P_Fld(0x0, TX_SET0_ARPI_CAL_E2OPT) |
+			P_Fld(0x0, TX_SET0_TX_DLY_CAL_E2OPT) | P_Fld(0x0, TX_SET0_DQS_OE_OP1_DIS) |
+			P_Fld(0x0, TX_SET0_DQS_OE_OP2_EN) | P_Fld(0x0, TX_SET0_RK_SCINPUT_OPT) |
+			P_Fld(0x0, TX_SET0_DRAMOEN));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_TX_SET0_0								   ral_reg_DRAMC_blk_SHU_TX_SET0_0							  - 	@5306														  
+	  DQOE_CNT									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[3:0]=4'h0 								  
+	  DQOE_OPT									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[4:4]=1'h0 								  
+	  TXUPD_SEL 								   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[7:6]=2'h0 								  
+	  TXUPD_W2R_SEL 							   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[10:8]=3'h2 (Mirror: 3'h0) 				  
+	  WECC_EN									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[11:11]=1'h0								  
+	  DBIWR 									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[12:12]=1'h0								  
+	  WDATRGO									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[13:13]=1'h0								  
+	  TWPSTEXT									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[14:14]=1'h0								  
+	  WPST1P5T									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[15:15]=1'h1 (Mirror: 1'h0)				  
+	  TXOEN_AUTOSET_OFFSET						   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[19:16]=4'h3								  
+	  TWCKPST									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[21:20]=2'h1								  
+	  OE_EXT2UI 								   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[24:22]=3'h1 (Mirror: 3'h0)				  
+	  DQS2DQ_FILT_PITHRD						   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[30:25]=6'h0e								  
+	  TXOEN_AUTOSET_EN							   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[31:31]=1'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+			P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+			P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+			P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+			P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
+			P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+			P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+			P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	MISC_SHU_STBCAL1_0							   ral_reg_DDRPHY_blk_MISC_SHU_STBCAL1_0					  - 	@12514														  
+	  DLLFRZRFCOPT								   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL1_0[1:0]=2'h0							  
+	  DLLFRZWROPT								   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL1_0[5:4]=2'h0							  
+	  r_rstbcnt_latch_opt						   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL1_0[10:8]=3'h0							  
+	  STB_UPDMASK_EN							   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL1_0[11:11]=1'h1 (Mirror: 1'h0)			  
+	  STB_UPDMASKCYC							   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL1_0[15:12]=4'h9 (Mirror: 4'h0)			  
+	  DQSINCTL_PRE_SEL							   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL1_0[16:16]=1'h1 (Mirror: 1'h0)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1, P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) |
+			P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) |
+			P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) |
+			P_Fld(0x1, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	MISC_SHU_STBCAL_0							   ral_reg_DDRPHY_blk_MISC_SHU_STBCAL_0 					  - 	@12499														  
+	  DMSTBLAT									   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL_0[3:0]=4'h2 (Mirror: 4'h0)				  
+	  PICGLAT									   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL_0[6:4]=3'h1 (Mirror: 3'h0)				  
+	  DQSG_MODE 								   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL_0[8:8]=1'h1 (Mirror: 1'h0)				  
+	  DQSIEN_PICG_MODE							   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL_0[9:9]=1'h1 (Mirror: 1'h0)				  
+	  DQSIEN_DQSSTB_MODE						   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL_0[13:12]=2'h3 (Mirror: 2'h1)			  
+	  DQSIEN_BURST_MODE 						   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL_0[14:14]=1'h1							  
+	  DQSIEN_SELPH_FRUN 						   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL_0[15:15]=1'h0							  
+	  STBCALEN									   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL_0[16:16]=1'h1 (Mirror: 1'h0)			  
+	  STB_SELPHCALEN							   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL_0[17:17]=1'h1 (Mirror: 1'h0)			  
+	  DQSIEN_4TO1_EN							   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL_0[20:20]=1'h0							  
+	  DQSIEN_8TO1_EN							   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL_0[21:21]=1'h0							  
+	  DQSIEN_16TO1_EN							   uvm_reg_field											  ...	 RW MISC_SHU_STBCAL_0[22:22]=1'h0							  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL, P_Fld(0x2, MISC_SHU_STBCAL_DMSTBLAT) |
+			P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) |
+			P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x3, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) |
+			P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) |
+			P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) |
+			P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) |
+			P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	MISC_SHU_RODTENSTB_0						   ral_reg_DDRPHY_blk_MISC_SHU_RODTENSTB_0					  - 	@12562														  
+	  RODTENSTB_TRACK_EN						   uvm_reg_field											  ...	 RW MISC_SHU_RODTENSTB_0[0:0]=1'h1 (Mirror: 1'h0)			  
+	  RODTEN_P1_ENABLE							   uvm_reg_field											  ...	 RW MISC_SHU_RODTENSTB_0[1:1]=1'h0							  
+	  RODTENSTB_4BYTE_EN						   uvm_reg_field											  ...	 RW MISC_SHU_RODTENSTB_0[2:2]=1'h0							  
+	  RODTENSTB_TRACK_UDFLWCTRL 				   uvm_reg_field											  ...	 RW MISC_SHU_RODTENSTB_0[3:3]=1'h1 (Mirror: 1'h0)			  
+	  RODTENSTB_SELPH_MODE						   uvm_reg_field											  ...	 RW MISC_SHU_RODTENSTB_0[4:4]=1'h1							  
+	  RODTENSTB_SELPH_BY_BITTIME				   uvm_reg_field											  ...	 RW MISC_SHU_RODTENSTB_0[5:5]=1'h0							  
+	  RODTENSTB__UI_OFFSET						   uvm_reg_field											  ...	 RW MISC_SHU_RODTENSTB_0[11:8]=4'h4 (Mirror: 4'h0)			  
+	  RODTENSTB_MCK_OFFSET						   uvm_reg_field											  ...	 RW MISC_SHU_RODTENSTB_0[15:12]=4'h0						  
+	  RODTENSTB_EXT 							   uvm_reg_field											  ...	 RW MISC_SHU_RODTENSTB_0[31:16]=16'h0008 (Mirror: 16'h0000)   
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) |
+			P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) |
+			P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) |
+			P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x4, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) |
+			P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	MISC_SHU_RX_SELPH_MODE_0					   ral_reg_DDRPHY_blk_MISC_SHU_RX_SELPH_MODE_0				  - 	@12751														  
+	  DQSIEN_SELPH_SERMODE						   uvm_reg_field											  ...	 RW MISC_SHU_RX_SELPH_MODE_0[1:0]=2'h3 (Mirror: 2'h0)		  
+	  RODT_SELPH_SERMODE						   uvm_reg_field											  ...	 RW MISC_SHU_RX_SELPH_MODE_0[5:4]=2'h2 (Mirror: 2'h0)		  
+	  RANK_SELPH_SERMODE						   uvm_reg_field											  ...	 RW MISC_SHU_RX_SELPH_MODE_0[7:6]=2'h2 (Mirror: 2'h0)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE, P_Fld(0x3, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) |
+			P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE));
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Exit
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Enter
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B0_DQ7_0								   ral_reg_DDRPHY_blk_SHU_B0_DQ7_0							  - 	@7808														  
+	  R_DMRANKRXDVS_B0							   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[3:0]=4'h0									  
+	  R_DMDQMDBI_EYE_SHU_B0 					   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[6:6]=1'h1 (Mirror: 1'h0)					  
+	  R_DMDQMDBI_SHU_B0 						   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[7:7]=1'h1 (Mirror: 1'h0)					  
+	  R_DMRXDVS_DQM_FLAGSEL_B0					   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[11:8]=4'h0 								  
+	  R_DMRXDVS_PBYTE_FLAG_OPT_B0				   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[12:12]=1'h0								  
+	  R_DMRXDVS_PBYTE_DQM_EN_B0 				   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[13:13]=1'h0								  
+	  R_DMRXTRACK_DQM_EN_B0 					   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[14:14]=1'h0								  
+	  R_DMRODTEN_B0 							   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[15:15]=1'h1								  
+	  R_DMARPI_CG_FB2DLL_DCM_EN_B0				   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[16:16]=1'h0								  
+	  R_DMTX_ARPI_CG_DQ_NEW_B0					   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[17:17]=1'h0								  
+	  R_DMTX_ARPI_CG_DQS_NEW_B0 				   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[18:18]=1'h0								  
+	  R_DMTX_ARPI_CG_DQM_NEW_B0 				   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[19:19]=1'h0								  
+	  R_LP4Y_SDN_MODE_DQS0						   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[20:20]=1'h0								  
+	  R_DMRXRANK_DQ_EN_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[24:24]=1'h1								  
+	  R_DMRXRANK_DQ_LAT_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[27:25]=3'h1								  
+	  R_DMRXRANK_DQS_EN_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[28:28]=1'h1								  
+	  R_DMRXRANK_DQS_LAT_B0 					   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[31:29]=3'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+			P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+			P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+			P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+			P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+			P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+			P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+			P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+			P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B1_DQ7_0								   ral_reg_DDRPHY_blk_SHU_B1_DQ7_0							  - 	@9211														  
+	  R_DMRANKRXDVS_B1							   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[3:0]=4'h0									  
+	  R_DMDQMDBI_EYE_SHU_B1 					   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[6:6]=1'h1 (Mirror: 1'h0)					  
+	  R_DMDQMDBI_SHU_B1 						   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[7:7]=1'h1 (Mirror: 1'h0)					  
+	  R_DMRXDVS_DQM_FLAGSEL_B1					   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[11:8]=4'h0 								  
+	  R_DMRXDVS_PBYTE_FLAG_OPT_B1				   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[12:12]=1'h0								  
+	  R_DMRXDVS_PBYTE_DQM_EN_B1 				   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[13:13]=1'h0								  
+	  R_DMRXTRACK_DQM_EN_B1 					   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[14:14]=1'h0								  
+	  R_DMRODTEN_B1 							   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[15:15]=1'h1								  
+	  R_DMARPI_CG_FB2DLL_DCM_EN_B1				   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[16:16]=1'h0								  
+	  R_DMTX_ARPI_CG_DQ_NEW_B1					   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[17:17]=1'h0								  
+	  R_DMTX_ARPI_CG_DQS_NEW_B1 				   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[18:18]=1'h0								  
+	  R_DMTX_ARPI_CG_DQM_NEW_B1 				   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[19:19]=1'h0								  
+	  R_LP4Y_SDN_MODE_DQS1						   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[20:20]=1'h0								  
+	  R_DMRXRANK_DQ_EN_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[24:24]=1'h1								  
+	  R_DMRXRANK_DQ_LAT_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[27:25]=3'h1								  
+	  R_DMRXRANK_DQS_EN_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[28:28]=1'h1								  
+	  R_DMRXRANK_DQS_LAT_B1 					   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[31:29]=3'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+			P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+			P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+			P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+			P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+			P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+			P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+			P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+			P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_TX_SET0_0								   ral_reg_DRAMC_blk_SHU_TX_SET0_0							  - 	@5306														  
+	  DQOE_CNT									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[3:0]=4'h0 								  
+	  DQOE_OPT									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[4:4]=1'h0 								  
+	  TXUPD_SEL 								   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[7:6]=2'h0 								  
+	  TXUPD_W2R_SEL 							   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[10:8]=3'h2								  
+	  WECC_EN									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[11:11]=1'h0								  
+	  DBIWR 									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[12:12]=1'h1 (Mirror: 1'h0)				  
+	  WDATRGO									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[13:13]=1'h0								  
+	  TWPSTEXT									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[14:14]=1'h0								  
+	  WPST1P5T									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[15:15]=1'h1								  
+	  TXOEN_AUTOSET_OFFSET						   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[19:16]=4'h3								  
+	  TWCKPST									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[21:20]=2'h1								  
+	  OE_EXT2UI 								   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[24:22]=3'h1								  
+	  DQS2DQ_FILT_PITHRD						   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[30:25]=6'h0e								  
+	  TXOEN_AUTOSET_EN							   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[31:31]=1'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+			P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+			P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+			P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+			P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
+			P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+			P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+			P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Exit
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Enter
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_HWSET_MR2_0 							   ral_reg_DRAMC_blk_SHU_HWSET_MR2_0						  - 	@5122														  
+	  HWSET_MR2_MRSMA							   uvm_reg_field											  ...	 RW SHU_HWSET_MR2_0[12:0]=13'h0002							  
+	  HWSET_MR2_OP								   uvm_reg_field											  ...	 RW SHU_HWSET_MR2_0[23:16]=8'h09 (Mirror: 8'h12)			  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR2, P_Fld(0x0002, SHU_HWSET_MR2_HWSET_MR2_MRSMA) |
+			P_Fld(0x09, SHU_HWSET_MR2_HWSET_MR2_OP));
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Exit
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Enter
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_FREQ_RATIO_SET0_0						   ral_reg_DRAMC_blk_SHU_FREQ_RATIO_SET0_0					  - 	@5384														  
+	  tDQSCK_JUMP_RATIO3						   uvm_reg_field											  ...	 RW SHU_FREQ_RATIO_SET0_0[7:0]=8'h20 (Mirror: 8'h00)		  
+	  tDQSCK_JUMP_RATIO2						   uvm_reg_field											  ...	 RW SHU_FREQ_RATIO_SET0_0[15:8]=8'h93 (Mirror: 8'h00)		  
+	  tDQSCK_JUMP_RATIO1						   uvm_reg_field											  ...	 RW SHU_FREQ_RATIO_SET0_0[23:16]=8'h07 (Mirror: 8'h00)		  
+	  tDQSCK_JUMP_RATIO0						   uvm_reg_field											  ...	 RW SHU_FREQ_RATIO_SET0_0[31:24]=8'h20 (Mirror: 8'h00)		  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) |
+			P_Fld(0x93, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x07, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) |
+			P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0));
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Exit
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Enter
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	MISC_SHU_DVFSDLL_0							   ral_reg_DDRPHY_blk_MISC_SHU_DVFSDLL_0					  - 	@12523														  
+	  r_bypass_1st_dll							   uvm_reg_field											  ...	 RW MISC_SHU_DVFSDLL_0[0:0]=1'h0							  
+	  r_bypass_2nd_dll							   uvm_reg_field											  ...	 RW MISC_SHU_DVFSDLL_0[1:1]=1'h0							  
+	  r_dll_idle								   uvm_reg_field											  ...	 RW MISC_SHU_DVFSDLL_0[10:4]=7'h5a (Mirror: 7'h46)			  
+	  r_2nd_dll_idle							   uvm_reg_field											  ...	 RW MISC_SHU_DVFSDLL_0[22:16]=7'h5a 						  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) |
+			P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) |
+			P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE));
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Exit
+		mcDELAY_US(1);
+	
+		mcDELAY_US(1);
+	
+	/*TINFO=---===BROADCAST OFF!===---*/
+		 broadcast_off();
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Enter
+		mcDELAY_US(1);
+	
+		mcDELAY_US(1);
+	
+	/*TINFO=---===BROADCAST ON!===---*/
+		 broadcast_on();
+	//	  ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Exit
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_DQSOSCR_0								   ral_reg_DRAMC_blk_SHU_DQSOSCR_0							  - 	@5338														  
+	  DQSOSCRCNT								   uvm_reg_field											  ...	 RW SHU_DQSOSCR_0[7:0]=8'h0e (Mirror: 8'h00)				  
+	  DQSOSC_ADV_SEL							   uvm_reg_field											  ...	 RW SHU_DQSOSCR_0[9:8]=2'h0 								  
+	  DQSOSC_DRS_ADV_SEL						   uvm_reg_field											  ...	 RW SHU_DQSOSCR_0[11:10]=2'h0								  
+	  DQSOSC_DELTA								   uvm_reg_field											  ...	 RW SHU_DQSOSCR_0[31:16]=16'hffff							  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR, P_Fld(0x0e, SHU_DQSOSCR_DQSOSCRCNT) |
+			P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) |
+			P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_DQSOSC_SET0_0							   ral_reg_DRAMC_blk_SHU_DQSOSC_SET0_0						  - 	@5332														  
+	  DQSOSCENDIS								   uvm_reg_field											  ...	 RW SHU_DQSOSC_SET0_0[0:0]=1'h1 							  
+	  DQSOSC_PRDCNT 							   uvm_reg_field											  ...	 RW SHU_DQSOSC_SET0_0[13:4]=10'h009 (Mirror: 10'h00f)		  
+	  DQSOSCENCNT								   uvm_reg_field											  ...	 RW SHU_DQSOSC_SET0_0[31:16]=16'h0002						  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0, P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) |
+			P_Fld(0x009, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_DQSOSC_0_0							   ral_reg_DRAMC_blk_SHURK_DQSOSC_0_0						  - 	@4906														  
+	  DQSOSC_BASE_RK0							   uvm_reg_field											  ...	 RW SHURK_DQSOSC_0_0[15:0]=16'h01ca (Mirror: 16'h0000)		  
+	  DQSOSC_BASE_RK0_B1						   uvm_reg_field											  ...	 RW SHURK_DQSOSC_0_0[31:16]=16'h01ca (Mirror: 16'h0000) 	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC, P_Fld(0x01ca, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
+			P_Fld(0x01ca, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_DQSOSC_0_1							   ral_reg_DRAMC_blk_SHURK_DQSOSC_0_1						  - 	@4911														  
+	  DQSOSC_BASE_RK0							   uvm_reg_field											  ...	 RW SHURK_DQSOSC_0_1[15:0]=16'h0106 (Mirror: 16'h0000)		  
+	  DQSOSC_BASE_RK0_B1						   uvm_reg_field											  ...	 RW SHURK_DQSOSC_0_1[31:16]=16'h0106 (Mirror: 16'h0000) 	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0106, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
+			P_Fld(0x0106, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_DQSOSC_THRD_0_0						   ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_0					  - 	@4916														  
+	  DQSOSCTHRD_INC							   uvm_reg_field											  ...	 RW SHURK_DQSOSC_THRD_0_0[11:0]=12'h007 (Mirror: 12'h001)	  
+	  DQSOSCTHRD_DEC							   uvm_reg_field											  ...	 RW SHURK_DQSOSC_THRD_0_0[27:16]=12'h005 (Mirror: 12'h001)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD, P_Fld(0x007, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
+			P_Fld(0x005, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHURK_DQSOSC_THRD_0_1						   ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_1					  - 	@4921														  
+	  DQSOSCTHRD_INC							   uvm_reg_field											  ...	 RW SHURK_DQSOSC_THRD_0_1[11:0]=12'h002 (Mirror: 12'h001)	  
+	  DQSOSCTHRD_DEC							   uvm_reg_field											  ...	 RW SHURK_DQSOSC_THRD_0_1[27:16]=12'h001					  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x002, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
+			P_Fld(0x001, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_TX_SET0_0								   ral_reg_DRAMC_blk_SHU_TX_SET0_0							  - 	@5306														  
+	  DQOE_CNT									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[3:0]=4'h0 								  
+	  DQOE_OPT									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[4:4]=1'h0 								  
+	  TXUPD_SEL 								   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[7:6]=2'h0 								  
+	  TXUPD_W2R_SEL 							   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[10:8]=3'h2								  
+	  WECC_EN									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[11:11]=1'h0								  
+	  DBIWR 									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[12:12]=1'h1								  
+	  WDATRGO									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[13:13]=1'h0								  
+	  TWPSTEXT									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[14:14]=1'h0								  
+	  WPST1P5T									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[15:15]=1'h1								  
+	  TXOEN_AUTOSET_OFFSET						   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[19:16]=4'h3								  
+	  TWCKPST									   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[21:20]=2'h1								  
+	  OE_EXT2UI 								   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[24:22]=3'h1								  
+	  DQS2DQ_FILT_PITHRD						   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[30:25]=6'h23 (Mirror: 6'h0e)				  
+	  TXOEN_AUTOSET_EN							   uvm_reg_field											  ...	 RW SHU_TX_SET0_0[31:31]=1'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
+			P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
+			P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
+			P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
+			P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
+			P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
+			P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x23, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
+			P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_ZQ_SET0_0								   ral_reg_DRAMC_blk_SHU_ZQ_SET0_0							  - 	@5351														  
+	  ZQCSCNT									   uvm_reg_field											  ...	 RW SHU_ZQ_SET0_0[15:0]=16'h0005 (Mirror: 16'h0000) 		  
+	  TZQLAT									   uvm_reg_field											  ...	 RW SHU_ZQ_SET0_0[31:27]=5'h1b								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) |
+			P_Fld(0x1b, SHU_ZQ_SET0_TZQLAT));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_HMR4_DVFS_CTRL0_0						   ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0					  - 	@5036														  
+	  FSPCHG_PRDCNT 							   uvm_reg_field											  ...	 RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h67						  
+	  REFRCNT									   uvm_reg_field											  ...	 RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h005 (Mirror: 12'h000)	  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x67, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
+			P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B0_DQ8_0								   ral_reg_DDRPHY_blk_SHU_B0_DQ8_0							  - 	@7828														  
+	  R_DMRXDVS_UPD_FORCE_CYC_B0				   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[14:0]=15'h0157 							  
+	  R_DMRXDVS_UPD_FORCE_EN_B0 				   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[15:15]=1'h1 (Mirror: 1'h0) 				  
+	  R_DMRANK_RXDLY_PIPE_CG_IG_B0				   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[19:19]=1'h0								  
+	  R_RMRODTEN_CG_IG_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[20:20]=1'h0								  
+	  R_RMRX_TOPHY_CG_IG_B0 					   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[21:21]=1'h1								  
+	  R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 			   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[22:22]=1'h0								  
+	  R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 		   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[23:23]=1'h0								  
+	  R_DMRXDLY_CG_IG_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[24:24]=1'h1								  
+	  R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 			   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[26:26]=1'h0								  
+	  R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 			   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[27:27]=1'h0								  
+	  R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0			   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[28:28]=1'h0								  
+	  R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0		   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[29:29]=1'h0								  
+	  R_DMRANK_PIPE_CG_IG_B0					   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[30:30]=1'h0								  
+	  R_DMRANK_CHG_PIPE_CG_IG_B0				   uvm_reg_field											  ...	 RW SHU_B0_DQ8_0[31:31]=1'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0157, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
+			P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+			P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
+			P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+			P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+			P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
+			P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+			P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B1_DQ8_0								   ral_reg_DDRPHY_blk_SHU_B1_DQ8_0							  - 	@9231														  
+	  R_DMRXDVS_UPD_FORCE_CYC_B1				   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[14:0]=15'h0157 							  
+	  R_DMRXDVS_UPD_FORCE_EN_B1 				   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[15:15]=1'h1 (Mirror: 1'h0) 				  
+	  R_DMRANK_RXDLY_PIPE_CG_IG_B1				   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[19:19]=1'h0								  
+	  R_RMRODTEN_CG_IG_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[20:20]=1'h0								  
+	  R_RMRX_TOPHY_CG_IG_B1 					   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[21:21]=1'h1								  
+	  R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 			   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[22:22]=1'h0								  
+	  R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 		   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[23:23]=1'h0								  
+	  R_DMRXDLY_CG_IG_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[24:24]=1'h1								  
+	  R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 			   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[26:26]=1'h0								  
+	  R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 			   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[27:27]=1'h0								  
+	  R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1			   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[28:28]=1'h0								  
+	  R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1		   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[29:29]=1'h0								  
+	  R_DMRANK_PIPE_CG_IG_B1					   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[30:30]=1'h0								  
+	  R_DMRANK_CHG_PIPE_CG_IG_B1				   uvm_reg_field											  ...	 RW SHU_B1_DQ8_0[31:31]=1'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0157, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
+			P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+			P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+			P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
+			P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+			P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+			P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+			P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B0_DQ7_0								   ral_reg_DDRPHY_blk_SHU_B0_DQ7_0							  - 	@7808														  
+	  R_DMRANKRXDVS_B0							   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[3:0]=4'h0									  
+	  R_DMDQMDBI_EYE_SHU_B0 					   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[6:6]=1'h1									  
+	  R_DMDQMDBI_SHU_B0 						   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[7:7]=1'h1									  
+	  R_DMRXDVS_DQM_FLAGSEL_B0					   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[11:8]=4'h8 (Mirror: 4'h0)					  
+	  R_DMRXDVS_PBYTE_FLAG_OPT_B0				   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[12:12]=1'h0								  
+	  R_DMRXDVS_PBYTE_DQM_EN_B0 				   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[13:13]=1'h0								  
+	  R_DMRXTRACK_DQM_EN_B0 					   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[14:14]=1'h0								  
+	  R_DMRODTEN_B0 							   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[15:15]=1'h1								  
+	  R_DMARPI_CG_FB2DLL_DCM_EN_B0				   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[16:16]=1'h0								  
+	  R_DMTX_ARPI_CG_DQ_NEW_B0					   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[17:17]=1'h0								  
+	  R_DMTX_ARPI_CG_DQS_NEW_B0 				   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[18:18]=1'h0								  
+	  R_DMTX_ARPI_CG_DQM_NEW_B0 				   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[19:19]=1'h0								  
+	  R_LP4Y_SDN_MODE_DQS0						   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[20:20]=1'h0								  
+	  R_DMRXRANK_DQ_EN_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[24:24]=1'h1								  
+	  R_DMRXRANK_DQ_LAT_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[27:25]=3'h1								  
+	  R_DMRXRANK_DQS_EN_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[28:28]=1'h1								  
+	  R_DMRXRANK_DQS_LAT_B0 					   uvm_reg_field											  ...	 RW SHU_B0_DQ7_0[31:29]=3'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
+			P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
+			P_Fld(0x8, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
+			P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
+			P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
+			P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
+			P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
+			P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
+			P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B1_DQ7_0								   ral_reg_DDRPHY_blk_SHU_B1_DQ7_0							  - 	@9211														  
+	  R_DMRANKRXDVS_B1							   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[3:0]=4'h0									  
+	  R_DMDQMDBI_EYE_SHU_B1 					   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[6:6]=1'h1									  
+	  R_DMDQMDBI_SHU_B1 						   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[7:7]=1'h1									  
+	  R_DMRXDVS_DQM_FLAGSEL_B1					   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[11:8]=4'h8 (Mirror: 4'h0)					  
+	  R_DMRXDVS_PBYTE_FLAG_OPT_B1				   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[12:12]=1'h0								  
+	  R_DMRXDVS_PBYTE_DQM_EN_B1 				   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[13:13]=1'h0								  
+	  R_DMRXTRACK_DQM_EN_B1 					   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[14:14]=1'h0								  
+	  R_DMRODTEN_B1 							   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[15:15]=1'h1								  
+	  R_DMARPI_CG_FB2DLL_DCM_EN_B1				   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[16:16]=1'h0								  
+	  R_DMTX_ARPI_CG_DQ_NEW_B1					   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[17:17]=1'h0								  
+	  R_DMTX_ARPI_CG_DQS_NEW_B1 				   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[18:18]=1'h0								  
+	  R_DMTX_ARPI_CG_DQM_NEW_B1 				   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[19:19]=1'h0								  
+	  R_LP4Y_SDN_MODE_DQS1						   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[20:20]=1'h0								  
+	  R_DMRXRANK_DQ_EN_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[24:24]=1'h1								  
+	  R_DMRXRANK_DQ_LAT_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[27:25]=3'h1								  
+	  R_DMRXRANK_DQS_EN_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[28:28]=1'h1								  
+	  R_DMRXRANK_DQS_LAT_B1 					   uvm_reg_field											  ...	 RW SHU_B1_DQ7_0[31:29]=3'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
+			P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
+			P_Fld(0x8, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
+			P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
+			P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
+			P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+			P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
+			P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
+			P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B0_DQ11_0								   ral_reg_DDRPHY_blk_SHU_B0_DQ11_0 						  - 	@7794														  
+	  RG_RX_ARDQ_RANK_SEL_SER_EN_B0 			   uvm_reg_field											  ...	 RW SHU_B0_DQ11_0[0:0]=1'h0 								  
+	  RG_RX_ARDQ_RANK_SEL_LAT_EN_B0 			   uvm_reg_field											  ...	 RW SHU_B0_DQ11_0[1:1]=1'h0 								  
+	  RG_RX_ARDQ_OFFSETC_LAT_EN_B0				   uvm_reg_field											  ...	 RW SHU_B0_DQ11_0[2:2]=1'h0 								  
+	  RG_RX_ARDQ_OFFSETC_EN_B0					   uvm_reg_field											  ...	 RW SHU_B0_DQ11_0[3:3]=1'h0 								  
+	  RG_RX_ARDQ_OFFSETC_BIAS_EN_B0 			   uvm_reg_field											  ...	 RW SHU_B0_DQ11_0[4:4]=1'h0 								  
+	  RG_RX_ARDQ_FRATE_EN_B0					   uvm_reg_field											  ...	 RW SHU_B0_DQ11_0[5:5]=1'h0 								  
+	  RG_RX_ARDQ_CDR_EN_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ11_0[6:6]=1'h0 								  
+	  RG_RX_ARDQ_DVS_EN_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ11_0[7:7]=1'h1 (Mirror: 1'h0)					  
+	  RG_RX_ARDQ_DVS_DLY_B0 					   uvm_reg_field											  ...	 RW SHU_B0_DQ11_0[11:8]=4'h0								  
+	  RG_RX_ARDQ_DES_MODE_B0					   uvm_reg_field											  ...	 RW SHU_B0_DQ11_0[17:16]=2'h3								  
+	  RG_RX_ARDQ_BW_SEL_B0						   uvm_reg_field											  ...	 RW SHU_B0_DQ11_0[19:18]=2'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11, P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) |
+			P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) |
+			P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) |
+			P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) |
+			P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) |
+			P_Fld(0x3, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0));
+	/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	Name										   Type 													  Size	Value														  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	SHU_B1_DQ11_0								   ral_reg_DDRPHY_blk_SHU_B1_DQ11_0 						  - 	@9197														  
+	  RG_RX_ARDQ_RANK_SEL_SER_EN_B1 			   uvm_reg_field											  ...	 RW SHU_B1_DQ11_0[0:0]=1'h0 								  
+	  RG_RX_ARDQ_RANK_SEL_LAT_EN_B1 			   uvm_reg_field											  ...	 RW SHU_B1_DQ11_0[1:1]=1'h0 								  
+	  RG_RX_ARDQ_OFFSETC_LAT_EN_B1				   uvm_reg_field											  ...	 RW SHU_B1_DQ11_0[2:2]=1'h0 								  
+	  RG_RX_ARDQ_OFFSETC_EN_B1					   uvm_reg_field											  ...	 RW SHU_B1_DQ11_0[3:3]=1'h0 								  
+	  RG_RX_ARDQ_OFFSETC_BIAS_EN_B1 			   uvm_reg_field											  ...	 RW SHU_B1_DQ11_0[4:4]=1'h0 								  
+	  RG_RX_ARDQ_FRATE_EN_B1					   uvm_reg_field											  ...	 RW SHU_B1_DQ11_0[5:5]=1'h0 								  
+	  RG_RX_ARDQ_CDR_EN_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ11_0[6:6]=1'h0 								  
+	  RG_RX_ARDQ_DVS_EN_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ11_0[7:7]=1'h1 (Mirror: 1'h0)					  
+	  RG_RX_ARDQ_DVS_DLY_B1 					   uvm_reg_field											  ...	 RW SHU_B1_DQ11_0[11:8]=4'h0								  
+	  RG_RX_ARDQ_DES_MODE_B1					   uvm_reg_field											  ...	 RW SHU_B1_DQ11_0[17:16]=2'h3								  
+	  RG_RX_ARDQ_BW_SEL_B1						   uvm_reg_field											  ...	 RW SHU_B1_DQ11_0[19:18]=2'h0								  
+	------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+	*/
+	vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11, P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) |
+			P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) |
+			P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) |
+			P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) |
+			P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) |
+			P_Fld(0x3, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1));
+	//	  Exit body
+}
+#endif
+
+
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c
new file mode 100644
index 000000000000..93c354ab319b
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c
@@ -0,0 +1,2445 @@
+/*----------------------------------------------------------------------------*
+ * Copyright Statement:                                                       *
+ *                                                                            *
+ *   This software/firmware and related documentation ("MediaTek Software")   *
+ * are protected under international and related jurisdictions'copyright laws *
+ * as unpublished works. The information contained herein is confidential and *
+ * proprietary to MediaTek Inc. Without the prior written permission of       *
+ * MediaTek Inc., any reproduction, modification, use or disclosure of        *
+ * MediaTek Software, and information contained herein, in whole or in part,  *
+ * shall be strictly prohibited.                                              *
+ * MediaTek Inc. Copyright (C) 2010. All rights reserved.                     *
+ *                                                                            *
+ *   BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND     *
+ * AGREES TO THE FOLLOWING:                                                   *
+ *                                                                            *
+ *   1)Any and all intellectual property rights (including without            *
+ * limitation, patent, copyright, and trade secrets) in and to this           *
+ * Software/firmware and related documentation ("MediaTek Software") shall    *
+ * remain the exclusive property of MediaTek Inc. Any and all intellectual    *
+ * property rights (including without limitation, patent, copyright, and      *
+ * trade secrets) in and to any modifications and derivatives to MediaTek     *
+ * Software, whoever made, shall also remain the exclusive property of        *
+ * MediaTek Inc.  Nothing herein shall be construed as any transfer of any    *
+ * title to any intellectual property right in MediaTek Software to Receiver. *
+ *                                                                            *
+ *   2)This MediaTek Software Receiver received from MediaTek Inc. and/or its *
+ * representatives is provided to Receiver on an "AS IS" basis only.          *
+ * MediaTek Inc. expressly disclaims all warranties, expressed or implied,    *
+ * including but not limited to any implied warranties of merchantability,    *
+ * non-infringement and fitness for a particular purpose and any warranties   *
+ * arising out of course of performance, course of dealing or usage of trade. *
+ * MediaTek Inc. does not provide any warranty whatsoever with respect to the *
+ * software of any third party which may be used by, incorporated in, or      *
+ * supplied with the MediaTek Software, and Receiver agrees to look only to   *
+ * such third parties for any warranty claim relating thereto.  Receiver      *
+ * expressly acknowledges that it is Receiver's sole responsibility to obtain *
+ * from any third party all proper licenses contained in or delivered with    *
+ * MediaTek Software.  MediaTek is not responsible for any MediaTek Software  *
+ * releases made to Receiver's specifications or to conform to a particular   *
+ * standard or open forum.                                                    *
+ *                                                                            *
+ *   3)Receiver further acknowledge that Receiver may, either presently       *
+ * and/or in the future, instruct MediaTek Inc. to assist it in the           *
+ * development and the implementation, in accordance with Receiver's designs, *
+ * of certain softwares relating to Receiver's product(s) (the "Services").   *
+ * Except as may be otherwise agreed to in writing, no warranties of any      *
+ * kind, whether express or implied, are given by MediaTek Inc. with respect  *
+ * to the Services provided, and the Services are provided on an "AS IS"      *
+ * basis. Receiver further acknowledges that the Services may contain errors  *
+ * that testing is important and it is solely responsible for fully testing   *
+ * the Services and/or derivatives thereof before they are used, sublicensed  *
+ * or distributed. Should there be any third party action brought against     *
+ * MediaTek Inc. arising out of or relating to the Services, Receiver agree   *
+ * to fully indemnify and hold MediaTek Inc. harmless.  If the parties        *
+ * mutually agree to enter into or continue a business relationship or other  *
+ * arrangement, the terms and conditions set forth herein shall remain        *
+ * effective and, unless explicitly stated otherwise, shall prevail in the    *
+ * event of a conflict in the terms in any agreements entered into between    *
+ * the parties.                                                               *
+ *                                                                            *
+ *   4)Receiver's sole and exclusive remedy and MediaTek Inc.'s entire and    *
+ * cumulative liability with respect to MediaTek Software released hereunder  *
+ * will be, at MediaTek Inc.'s sole discretion, to replace or revise the      *
+ * MediaTek Software at issue.                                                *
+ *                                                                            *
+ *   5)The transaction contemplated hereunder shall be construed in           *
+ * accordance with the laws of Singapore, excluding its conflict of laws      *
+ * principles.  Any disputes, controversies or claims arising thereof and     *
+ * related thereto shall be settled via arbitration in Singapore, under the   *
+ * then current rules of the International Chamber of Commerce (ICC).  The    *
+ * arbitration shall be conducted in English. The awards of the arbitration   *
+ * shall be final and binding upon both parties and shall be entered and      *
+ * enforceable in any court of competent jurisdiction.                        *
+ *---------------------------------------------------------------------------*/
+
+//-----------------------------------------------------------------------------
+// Include files
+//-----------------------------------------------------------------------------
+#include "dramc_common.h"
+#include "dramc_int_global.h"
+#include "x_hal_io.h"
+#include "dramc_top.h"
+
+#define SHUFFLE_GROUP   4               //SHU1~4
+
+//-----------------------------------------------------------------------------
+// Global variables
+//-----------------------------------------------------------------------------
+
+U8 _MappingFreqArray[DRAM_DFS_SRAM_MAX] = {0};
+
+U8 gDVFSCtrlSel = 0;
+U32 gu4Ddrphy0SPMCtrl0;
+U32 gu4Ddrphy1SPMCtrl0;
+U32 gu4Ddrphy0SPMCtrl2;
+U32 gu4Ddrphy1SPMCtrl2;
+
+
+void vSetDFSTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable)
+{
+    p->pDFSTable = pFreqTable;
+}
+
+void vSetDFSFreqSelByTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable)
+{
+    vSetDFSTable(p, pFreqTable);
+    DDRPhyFreqSel(p, p->pDFSTable->freq_sel);
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+    vSetVcoreByFreq(p);
+#endif
+
+#if DUMP_ALLSUH_RG
+    mcSHOW_DBG_MSG(("\n[dumpRG] vSetDFSFreqSelByTable Freq= %d, SRAM SHU%d\n", p->frequency, p->pDFSTable->SRAMIdx));
+    //mcSHOW_DBG_MSG3(("\n[dumpRG] vSetDFSFreqSelByTable Freq= %d, SRAM SHU%d\n", p->frequency, p->pDFSTable->shuffleIdx));
+#endif
+}
+
+DRAM_DFS_FREQUENCY_TABLE_T* get_FreqTbl_by_SRAMIndex(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T SRAMIdx)
+{
+    U8 u1ShuffleIdx = 0;
+    DRAM_DFS_FREQUENCY_TABLE_T *pFreqTbl;
+
+    pFreqTbl = gFreqTbl;
+
+    for (u1ShuffleIdx = 0; u1ShuffleIdx < DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
+    {
+        if (pFreqTbl[u1ShuffleIdx].SRAMIdx == SRAMIdx)
+            break;
+    }
+
+    if (u1ShuffleIdx == DRAM_DFS_SRAM_MAX)
+        {
+        mcSHOW_ERR_MSG(("\n get_FreqTbl_by_shuffleIndex is NULL \n"));
+        #if (__ETT__)
+            while(1);
+        #else
+        ASSERT(0);
+        #endif
+    }
+    return &pFreqTbl[u1ShuffleIdx];
+}
+
+#if 0 //@Darren, debug codes
+void DramcWriteShuffleSRAMRange(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr, u32 u4Data)
+{
+    U32 ii, u4tmp, u4Offset=0;
+
+    for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4)
+    {
+        vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0+u4Offset+SHU_GRP_DRAMC_OFFSET), u4Data);
+        u4Offset += 4;
+        mcDELAY_MS(1);
+    }
+}
+
+void DdrphyWriteShuffleSRAMRange(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr, u32 u4Data)
+{
+    U32 ii, u4tmp, u4Offset=0;
+
+    for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4)
+    {
+        vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL0+u4Offset+SHU_GRP_DDRPHY_OFFSET), u4Data);
+        u4Offset += 4;
+        mcDELAY_MS(1);
+    }
+}
+
+void FullRGDump(DRAMC_CTX_T *p, U8 step, U32 u4ShuOffset)
+{
+    U8 u1RankIdx=0;
+
+    mcSHOW_DBG_MSG(("[FullRGDump] STEP%d\n", step));
+    //Darren-DumpAoNonShuReg();
+    for (u1RankIdx=RANK_0; u1RankIdx<p->support_rank_num; u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+        mcSHOW_DBG_MSG(("[FullRGDump] RANK%d\n", u1RankIdx));
+        DumpAoShuReg(u4ShuOffset, u4ShuOffset);
+    }
+    //Darren-DumpNaoReg();
+}
+
+U32 SramDebugModeRead(DRAMC_CTX_T *p, U8 sram_shu_level, U32 u4Reg)
+{
+    U32 u4Value=0;
+    U32 u4RegBackupAddress[] =
+    {
+        (DDRPHY_REG_MISC_SRAM_DMA0),
+        (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHB_ADDR),
+        (DDRPHY_REG_MISC_SRAM_DMA1),
+        (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHB_ADDR),
+#if (CHANNEL_NUM==4)
+        (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHC_ADDR),
+        (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHD_ADDR),
+        (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHC_ADDR),
+        (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHD_ADDR),
+#endif
+    };
+
+    //Backup regs
+    DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+
+    //vIO32Write4B(DRAMC_REG_ADDR(u4Reg), u4Data); // SHU1
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, sram_shu_level, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL); // SHU8
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL);
+
+    p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1;
+    u4Value = u4IO32Read4B(DRAMC_REG_ADDR(u4Reg));// SHU1
+    DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+    p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
+    mcSHOW_DBG_MSG(("[SramDebugModeRead] RK%d Reg=0x%x, Value=0x%x\n", p->rank, u4Reg, u4Value));
+
+    //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);
+    //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x0, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS);
+
+    return u4Value;
+}
+
+void SramDebugModeWrite(DRAMC_CTX_T *p, U8 sram_shu_level, U32 u4Reg, U32 u4Data)
+{
+    U32 u4RegBackupAddress[] =
+    {
+        (DDRPHY_REG_MISC_SRAM_DMA0),
+        (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHB_ADDR),
+        (DDRPHY_REG_MISC_SRAM_DMA1),
+        (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHB_ADDR),
+#if (CHANNEL_NUM==4)
+        (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHC_ADDR),
+        (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHD_ADDR),
+        (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHC_ADDR),
+        (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHD_ADDR),
+#endif
+    };
+
+    //Backup regs
+    DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, sram_shu_level, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL); // SHU8
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL);
+
+    p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1;
+    vIO32Write4B(DRAMC_REG_ADDR(u4Reg), u4Data); // SHU1
+    DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+    p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
+    mcSHOW_DBG_MSG(("[SramDebugModeWrite] RK%d Reg=0x%x, Value=0x%x\n", p->rank, u4Reg, u4Data));
+
+    //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);
+    //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x0, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS);
+}
+
+void DramcCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr)
+{
+    U32 ii, u4tmp, u4Offset=0;
+    DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx; // SHU1 need use p->ShuRGAccessIdx=DRAM_DFS_REG_SHU1 for RK1
+
+    for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4)
+    {
+        u4tmp = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0+u4Offset));
+        mcDELAY_MS(1);
+        p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1;
+        vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0+u4Offset), u4tmp);
+        p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
+        u4Offset += 4;
+        mcDELAY_MS(1);
+    }
+
+    p->ShuRGAccessIdx = ShuRGAccessIdxBackup;
+}
+
+void DdrphyCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr)
+{
+    U32 ii, u4tmp, u4Offset=0;
+    DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx; // SHU1 need use p->ShuRGAccessIdx=DRAM_DFS_REG_SHU1 for RK1
+
+    for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4)
+    {
+        u4tmp = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL0+u4Offset));
+        mcDELAY_MS(1);
+        p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1;
+        vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL0+u4Offset), u4tmp);
+        p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
+        u4Offset += 4;
+        mcDELAY_MS(1);
+    }
+
+    p->ShuRGAccessIdx = ShuRGAccessIdxBackup;
+}
+#endif
+
+#if ENABLE_LP4Y_WA && LP4Y_BACKUP_SOLUTION
+static void ClkSingleEndRGEnable (DRAMC_CTX_T *p, U8 u1OnOff)
+{
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld( u1OnOff, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA) \
+                                                      | P_Fld( u1OnOff, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD7) , P_Fld( u1OnOff, SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK));
+}
+
+void CmdBusTrainingLP4YWA(DRAMC_CTX_T *p, U8 u1OnOff)
+{
+    U8 u1MR51 = 0;
+
+    if ((p->frequency > 800) && (p->dram_fsp==FSP_0)) // skip DDR1600 up
+        return;
+
+    if (p->dram_fsp==FSP_1) //for HIGH speed in FSP1, FSP0 SE setting will be mismatch
+    {
+        if (u1OnOff==DISABLE)
+        {
+            p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1;
+
+            //CLK to Diff end
+            ClkSingleEndRGEnable ( p, u1OnOff);
+
+            p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
+        }
+    }
+    else //for LOW speed under DDR1600
+    {
+        if (u1OnOff == DISABLE)
+            u1MR51Value[p->dram_fsp] = u1MR51Value[p->dram_fsp] & ~(1 << 3); // disable CLK SE mode
+        else
+            u1MR51Value[p->dram_fsp] = u1MR51Value[p->dram_fsp] | (1 << 3); // enable CLK SE mode
+
+        DramcModeRegWriteByRank(p, p->rank, 51, u1MR51Value[p->dram_fsp]);
+
+        //CLK to Diff end
+        ClkSingleEndRGEnable ( p, u1OnOff);
+    }
+}
+#endif
+
+#if ENABLE_DFS_RUNTIME_MRW
+void DFSRuntimeFspMRW(DRAMC_CTX_T *p)
+{
+    p->boot_fsp = p->dram_fsp;
+    vIO32WriteFldAlign_All(DRAMC_REG_SA_RESERVE, p->boot_fsp, SA_RESERVE_DFS_FSP_RTMRW);
+}
+
+void DFSRuntimeMRW_preset_BeforeK(DRAMC_CTX_T *p, U8 sram_shu_level)
+{
+    U8 u1ChIdx = 0, u1RankIdx = 0;
+    U8 u1MR51_Value = u1MR51Value[p->dram_fsp];
+    U32 u4DPMOffset = 0;
+    #if ENABLE_RTMRW_DEBUG_LOG
+    mcSHOW_DBG_MSG(("[DFSRuntimeMRW_preset_BeforeK] FSP%d\n", p->dram_fsp));
+    #endif
+
+#if ENABLE_LP4Y_DFS && (LP4Y_BACKUP_SOLUTION == 1) //Set SE before Calibration
+    if (p->frequency <=800)
+    {
+        u1MR51_Value = u1MR51Value[p->dram_fsp] | 0xe; // CLK[3]=1, WDQS[2]=1 and RDQS[1]=1 Single-End mode for LP4Y
+    }
+    else
+    {
+        u1MR51_Value = u1MR51Value[p->dram_fsp] & 0xf1;
+    }
+#endif
+
+    //! save shux mr1/mr2/mr3/mr11
+    vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (sram_shu_level << 4),
+        P_Fld(u1MR01Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_0) |
+        P_Fld(u1MR02Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_1) |
+        P_Fld(u1MR03Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_2) |
+        P_Fld(u1MR11Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_3));
+    #if ENABLE_RTMRW_DEBUG_LOG
+    mcSHOW_DBG_MSG(("\tMR01 = 0x%x, MR02 = 0x%x, MR03 = 0x%x, MR11 = 0x%x\n", u1MR01Value[p->dram_fsp], u1MR02Value[p->dram_fsp], u1MR03Value[p->dram_fsp], u1MR11Value[p->dram_fsp]));
+    #endif
+    //! save shux mr22/mr51
+    vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (sram_shu_level << 4),
+        P_Fld(u1MR21Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_5) |
+        P_Fld(u1MR22Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_6) |
+        P_Fld(u1MR51_Value, LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_7));
+    #if ENABLE_RTMRW_DEBUG_LOG
+    mcSHOW_DBG_MSG(("\tMR22 = 0x%x, MR51 = 0x%x\n", u1MR22Value[p->dram_fsp], u1MR51_Value));
+    #endif
+
+    for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx ++)
+    {
+#if CHANNEL_NUM > 2
+	if (channel_num_auxadc > 2) {
+        if (u1ChIdx >= CHANNEL_C)
+            u4DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM);  // for 4ch others DPM
+		}
+#endif
+        //! save shux mr12/mr14
+        vIO32WriteFldMulti(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 + ((u1ChIdx%2)*4) + u4DPMOffset + (sram_shu_level << 4),
+            P_Fld(u1MR12Value[u1ChIdx][RANK_0][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_8) |
+            P_Fld(u1MR12Value[u1ChIdx][RANK_1][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_9) |
+            P_Fld(u1MR14Value[u1ChIdx][RANK_0][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_10) |
+            P_Fld(u1MR14Value[u1ChIdx][RANK_1][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_11));
+    }
+
+#if ENABLE_RTMRW_DEBUG_LOG
+    for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++)
+    {
+        for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+        {
+            mcSHOW_DBG_MSG(("\tCH%d, RK%d, MR12 = 0x%x, MR14 = 0x%x\n", u1ChIdx, u1RankIdx,u1MR12Value[u1ChIdx][u1RankIdx][p->dram_fsp], u1MR14Value[u1ChIdx][u1RankIdx][p->dram_fsp]));
+        }
+    }
+#endif
+}
+
+void DFSRuntimeMRW_preset_AfterK(DRAMC_CTX_T *p, U8 sram_shu_level)
+{
+    U8 u1ChIdx = 0, u1RankIdx = 0;
+    U8 u1MR03_Value = u1MR03Value[p->dram_fsp], u1MR51_Value = u1MR51Value[p->dram_fsp];
+    U32 u4DPMOffset = 0;
+#if ENABLE_RTMRW_DEBUG_LOG
+    mcSHOW_DBG_MSG(("[DFSRuntimeMRW_preset_AfterK] FSP%d\n", p->dram_fsp));
+#endif
+
+#if ENABLE_READ_DBI
+    u1MR03_Value = ((u1MR03Value[p->dram_fsp] & 0xbf) | (p->DBI_R_onoff[p->dram_fsp] << 6));
+#endif
+
+#if ENABLE_WRITE_DBI
+    u1MR03_Value = ((u1MR03Value[p->dram_fsp] & 0x7F) | (p->DBI_W_onoff[p->dram_fsp] << 7));
+#endif
+
+#if ENABLE_LP4Y_DFS && (LP4Y_BACKUP_SOLUTION == 0) //Set SE after Calibration
+    if (p->frequency <=800)
+    {
+        u1MR51_Value = u1MR51Value[p->dram_fsp] | 0xe; // CLK[3]=1, WDQS[2]=1 and RDQS[1]=1 Single-End mode for LP4Y
+    }
+    else
+    {
+        u1MR51_Value = u1MR51Value[p->dram_fsp] & 0xf1;
+    }
+#endif
+
+    //! save shux mr1/mr2/mr3/mr11
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (sram_shu_level << 4),
+        u1MR03_Value, LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_2);
+    #if ENABLE_RTMRW_DEBUG_LOG
+    mcSHOW_DBG_MSG(("\tMR01 = 0x%x, MR02 = 0x%x, MR03 = 0x%x, MR11 = 0x%x\n", u1MR01Value[p->dram_fsp], u1MR02Value[p->dram_fsp], u1MR03_Value, u1MR11Value[p->dram_fsp]));
+    #endif
+    //! save shux mr22/mr51
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (sram_shu_level << 4),
+        u1MR51_Value, LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_7);
+    #if ENABLE_RTMRW_DEBUG_LOG
+    mcSHOW_DBG_MSG(("\tMR22 = 0x%x, MR51 = 0x%x\n", u1MR22Value[p->dram_fsp], u1MR51_Value));
+    #endif
+
+    for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx ++)
+    {
+#if CHANNEL_NUM > 2
+	if (channel_num_auxadc > 2) {
+        if (u1ChIdx >= CHANNEL_C)
+            u4DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM);  // for 4ch others DPM
+		}
+#endif
+        //! save shux mr12/mr14
+        vIO32WriteFldMulti(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 + ((u1ChIdx%2)*4) + u4DPMOffset + (sram_shu_level << 4),
+            P_Fld(u1MR12Value[u1ChIdx][RANK_0][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_8) |
+            P_Fld(u1MR12Value[u1ChIdx][RANK_1][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_9) |
+            P_Fld(u1MR14Value[u1ChIdx][RANK_0][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_10) |
+            P_Fld(u1MR14Value[u1ChIdx][RANK_1][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_11));
+    }
+
+#if ENABLE_RTMRW_DEBUG_LOG
+    for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++)
+    {
+        for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+        {
+            mcSHOW_DBG_MSG(("\tCH%d, RK%d, MR12 = 0x%x, MR14 = 0x%x\n", u1ChIdx, u1RankIdx,u1MR12Value[u1ChIdx][u1RankIdx][p->dram_fsp], u1MR14Value[u1ChIdx][u1RankIdx][p->dram_fsp]));
+        }
+    }
+#endif
+}
+
+static void TriggerRTMRW_SingleChannel(DRAMC_CTX_T *p, U8 rtmrw_rank_sel, U8 u1MR1, U8 u1MR2, U8 u1MR3, U8 u1MR11, U8 u1MR12, U8 u1MR13, U8 u1MR14, U8 u1MR21, U8 u1MR22, U8 u1MR51)
+{
+    U8 rt_response_ack = 1, rt_ack = 0;
+    U8 u1MRW_1ST_Num = 0x5; // MR13, MR1, MR2, MR3, MR11, MR12
+    U8 u1MRW_2ND_Num = 0x2; // MR14, 22, 51
+
+#if ENABLE_LP4Y_DFS
+    u1MRW_2ND_Num++; // for LP4Y MR21
+#endif
+
+#if 1
+    //! MR13, MR1, MR2, MR3, MR11, MR12
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL0),
+        P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW0_RK) |
+        P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW1_RK) |
+        P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW2_RK) |
+        P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW3_RK) |
+        P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW4_RK) |
+        P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW5_RK) |
+        P_Fld(u1MRW_1ST_Num, RTMRW_CTRL0_RTMRW_LEN) |
+        P_Fld(0x0, RTMRW_CTRL0_RTMRW_AGE) |
+        P_Fld(0x3, RTMRW_CTRL0_RTMRW_LAT));
+
+    //! MA = 13, 1, 2, 3
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL1),
+        P_Fld(13, RTMRW_CTRL1_RTMRW0_MA) |
+        P_Fld(1, RTMRW_CTRL1_RTMRW1_MA) |
+        P_Fld(2, RTMRW_CTRL1_RTMRW2_MA) |
+        P_Fld(3, RTMRW_CTRL1_RTMRW3_MA));
+
+    //! OP13, OP1, OP2, OP3
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL2),
+        P_Fld(u1MR13, RTMRW_CTRL2_RTMRW0_OP) |
+        P_Fld(u1MR1, RTMRW_CTRL2_RTMRW1_OP) |
+        P_Fld(u1MR2, RTMRW_CTRL2_RTMRW2_OP) |
+        P_Fld(u1MR3, RTMRW_CTRL2_RTMRW3_OP));
+
+    //! MR11/MR12
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL3),
+        P_Fld(11, RTMRW_CTRL3_RTMRW4_MA) |
+        P_Fld(12, RTMRW_CTRL3_RTMRW5_MA) |
+        P_Fld(u1MR11, RTMRW_CTRL3_RTMRW4_OP) |
+        P_Fld(u1MR12, RTMRW_CTRL3_RTMRW5_OP));
+
+    //!runtime MRW trigger
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x1, SWCMD_EN_RTMRWEN);
+
+    do {
+        rt_ack = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_RTMRW_RESPONSE);
+    } while(rt_response_ack != rt_ack);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x0, SWCMD_EN_RTMRWEN);
+#endif
+
+#if 1
+   //! MR14/22/51
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL0),
+        P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW0_RK) |
+        P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW1_RK) |
+        P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW2_RK) |
+#if ENABLE_LP4Y_DFS
+        P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW3_RK) |
+#endif
+        P_Fld(u1MRW_2ND_Num, RTMRW_CTRL0_RTMRW_LEN) |
+        P_Fld(0x0, RTMRW_CTRL0_RTMRW_AGE) |
+        P_Fld(0x3, RTMRW_CTRL0_RTMRW_LAT));
+
+    //! MA = 14, 22, 51
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL1),
+        P_Fld(14, RTMRW_CTRL1_RTMRW0_MA) |
+#if ENABLE_LP4Y_DFS
+        P_Fld(21, RTMRW_CTRL1_RTMRW3_MA) |
+#endif
+        P_Fld(22, RTMRW_CTRL1_RTMRW1_MA) |
+        P_Fld(51, RTMRW_CTRL1_RTMRW2_MA));
+
+    //! OP14, OP22, OP51
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL2),
+        P_Fld(u1MR14, RTMRW_CTRL2_RTMRW0_OP) |
+#if ENABLE_LP4Y_DFS
+        P_Fld(u1MR21, RTMRW_CTRL2_RTMRW3_OP) |
+#endif
+        P_Fld(u1MR22, RTMRW_CTRL2_RTMRW1_OP) |
+        P_Fld(u1MR51, RTMRW_CTRL2_RTMRW2_OP));
+
+    //!runtime MRW trigger
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x1, SWCMD_EN_RTMRWEN);
+
+    do {
+        rt_ack = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_RTMRW_RESPONSE);
+    } while(rt_response_ack != rt_ack);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x0, SWCMD_EN_RTMRWEN);
+#endif
+}
+
+static void DFSRTMRW_HwsetWA(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 pingpong_shu_level, U8 CH_num)
+{
+    U8 u1MR13_OP = 0, u1VRCG_OP = 0;
+    U8 u1ChIdx = 0;
+    U8 bc_bak = DRAMC_BROADCAST_OFF;
+    #if ENABLE_RTMRW_DEBUG_LOG
+    mcSHOW_DBG_MSG(("[DFSRTMRW_HwsetWA] \n"));
+    #endif
+
+        p->ShuRGAccessIdx = cur_shu_mux_index; // Currect
+        u1MR13_OP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), SHU_HWSET_MR13_HWSET_MR13_OP);
+        p->ShuRGAccessIdx = pingpong_shu_level; // Next
+        u1VRCG_OP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), SHU_HWSET_VRCG_HWSET_VRCG_OP);
+        p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
+
+        if(p->boot_fsp == FSP_1)
+        {
+            if (cur_shu_mux_index == PHYPLL_MODE)
+            {
+                u1MR13_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL
+                u1VRCG_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL
+            }
+            else
+            {
+                u1MR13_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL
+                u1VRCG_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL
+            }
+        }
+        else
+        {
+            if (cur_shu_mux_index == PHYPLL_MODE)
+            {
+                u1MR13_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL
+                u1VRCG_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL
+            }
+            else
+            {
+                u1MR13_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL
+                u1VRCG_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL
+            }
+        }
+
+    #if ENABLE_RTMRW_DEBUG_LOG
+    mcSHOW_DBG_MSG(("HWSET_MR13_OP = 0x%x\n", u1MR13_OP));
+    mcSHOW_DBG_MSG(("HWSET_VRCG_OP = 0x%x\n", u1VRCG_OP));
+    #endif
+
+    if (CH_num > CHANNEL_SINGLE)
+    {
+        bc_bak = GetDramcBroadcast();
+        DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+        p->ShuRGAccessIdx = cur_shu_mux_index; // Currect
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), u1MR13_OP, SHU_HWSET_MR13_HWSET_MR13_OP); // Current
+        p->ShuRGAccessIdx = pingpong_shu_level; // Next
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), u1VRCG_OP, SHU_HWSET_VRCG_HWSET_VRCG_OP); // Next
+        p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
+    if (CH_num > CHANNEL_SINGLE)
+        DramcBroadcastOnOff(bc_bak);
+
+}
+
+static void DFSRuntimeMRWEn(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_level)
+{
+    U8 rtmr13 = 0;
+    U8 rtmr1 = 0, rtmr2 = 0, rtmr3 = 0, rtmr11 = 0;
+    U8 rtmr12 = 0, rtmr14 = 0;
+    U8 rtmr21 = 0, rtmr22 = 0, rtmr51 = 0;
+    U8 dpm_rtmrw_hpri_en_bk = 0;
+    U32 bc_bak = 0, ch_bak = 0;
+    U8 u1ChIdx = 0, u1RankIdx = 0;
+    U32 DPMOffset;
+
+    bc_bak = GetDramcBroadcast();
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    ch_bak = vGetPHY2ChannelMapping(p);
+
+    //! get mr13
+    //rtmr13 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_0, LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_0);
+    //! get shux mr1/mr2/mr3/mr11
+    rtmr1 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_0);
+    rtmr2 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_1);
+    rtmr3 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_2);
+    rtmr11 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_3);
+    //! get shux mr21/mr22/mr51
+    rtmr21 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_5);
+    rtmr22 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_6);
+    rtmr51 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_7);
+
+    rtmr13 &= 0x3F;
+    if (p->boot_fsp== FSP_1)
+    {
+        if(cur_shu_mux_index == PHYPLL_MODE)
+            rtmr13 |= (0x1 << 7); //! MR13 OP7 = 1, OP6 = 0, from PHYPLL to CLRPLL
+        else
+            rtmr13 |= (0x1 << 6); //! MR13 OP7 = 0, OP6 = 1, from CLRPLL to PHYPLL
+    }
+    else
+    {
+        if(cur_shu_mux_index == PHYPLL_MODE)
+            rtmr13 |= (0x1 << 6); //! MR13 OP7 = 0, OP6 = 1, from CLRPLL to PHYPLL
+        else
+            rtmr13 |= (0x1 << 7); //! MR13 OP7 = 1, OP6 = 0, from PHYPLL to CLRPLL
+    }
+#if ENABLE_RTMRW_DEBUG_LOG
+    mcSHOW_DBG_MSG(("[DFSRuntimeMRWEn]\n"));
+#endif
+    for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1ChIdx);
+        dpm_rtmrw_hpri_en_bk = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), MPC_CTRL_RTMRW_HPRI_EN);
+        if (dpm_rtmrw_hpri_en_bk == 0)
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 0x1, MPC_CTRL_RTMRW_HPRI_EN);
+
+#if (CHANNEL_NUM > 2)
+	if (channel_num_auxadc > 2) {
+        if (u1ChIdx >= CHANNEL_C)
+            DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM);//SHIFT_TO_CHB_ADDR;
+        else
+		}
+#endif
+            DPMOffset = 0;
+
+        for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+        {
+            //! get shux mr12/mr14/
+            rtmr12 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 + ((u1ChIdx%2)*4) + DPMOffset + (nxt_shu_level << 4),  Fld(8, u1RankIdx*8));
+            rtmr14 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 + ((u1ChIdx%2)*4) + DPMOffset + (nxt_shu_level << 4),  Fld(8, (u1RankIdx*8)+16));
+            #if ENABLE_RTMRW_DEBUG_LOG
+            mcSHOW_DBG_MSG(("CH%d RK%d\n", u1ChIdx, u1RankIdx));
+            mcSHOW_DBG_MSG(("\tMR1=0x%x, MR2=0x%x, MR3=0x%x, MR11=0x%x\n", rtmr1, rtmr2, rtmr3, rtmr11));
+            mcSHOW_DBG_MSG(("\tMR12=0x%x, MR13=0x%x, MR14=0x%x, MR22=0x%x, MR51=0x%x\n", rtmr12, rtmr13, rtmr14, rtmr22, rtmr51));
+            #endif
+            TriggerRTMRW_SingleChannel(p, u1RankIdx, rtmr1, rtmr2, rtmr3, rtmr11, rtmr12, rtmr13, rtmr14, rtmr21, rtmr22, rtmr51);
+        }
+
+        if (dpm_rtmrw_hpri_en_bk == 0)
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), dpm_rtmrw_hpri_en_bk, MPC_CTRL_RTMRW_HPRI_EN);
+    }
+
+    vSetPHY2ChannelMapping(p, ch_bak);
+    DramcBroadcastOnOff(bc_bak);
+}
+#endif
+
+static void DFSHwSetWA(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_level, U8 CH_num)
+{
+    U8 u1MR13_OP = 0;
+    U8 bc_bak = DRAMC_BROADCAST_OFF;
+    #if ENABLE_RTMRW_DEBUG_LOG
+    mcSHOW_DBG_MSG(("[DFSHwSetWA] \n"));
+    #endif
+    p->ShuRGAccessIdx = cur_shu_mux_index; // NOTE: Currect shuffle
+    u1MR13_OP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), SHU_HWSET_MR13_HWSET_MR13_OP);
+
+    if ((nxt_shu_level == SRAM_SHU0) || (nxt_shu_level == SRAM_SHU1)) // for term shuffle level
+        u1MR13_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL
+    else
+        u1MR13_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL
+
+    if (CH_num > CHANNEL_SINGLE)
+    {
+        bc_bak = GetDramcBroadcast();
+        DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+
+    #if ENABLE_RTMRW_DEBUG_LOG
+    mcSHOW_DBG_MSG(("HWSET_MR13_OP = 0x%x\n", u1MR13_OP));
+    #endif
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), u1MR13_OP, SHU_HWSET_MR13_HWSET_MR13_OP); // Current
+    if (CH_num > CHANNEL_SINGLE)
+        DramcBroadcastOnOff(bc_bak);
+
+    p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
+}
+
+#if ENABLE_CONFIG_MCK_4TO1_MUX
+void ConfigMCK4To1MUX(DRAMC_CTX_T *p, CLK_MUX_T eClkMux)
+{
+    U8 u1DVFS_52M_104M_SEL, u1DVFS_104M_208M_SEL;
+
+    if (eClkMux == CLK_MUX_208M)
+    {
+        u1DVFS_52M_104M_SEL = 1;
+        u1DVFS_104M_208M_SEL = 1;
+    }
+    else if (eClkMux == CLK_MUX_104M)
+    {
+        u1DVFS_52M_104M_SEL = 1;
+        u1DVFS_104M_208M_SEL = 0;
+    }
+    else
+    {
+        u1DVFS_52M_104M_SEL = 0;
+        u1DVFS_104M_208M_SEL = 0;
+    }
+
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CKMUX_SEL, P_Fld(u1DVFS_52M_104M_SEL, MISC_CKMUX_SEL_RG_52M_104M_SEL)
+                        | P_Fld(u1DVFS_104M_208M_SEL, MISC_CKMUX_SEL_RG_104M_208M_SEL));
+
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0, P_Fld(0x3, MISC_CG_CTRL0_CLK_MEM_SEL)
+                        | P_Fld(0x1, MISC_CG_CTRL0_W_CHG_MEM));
+
+    mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK
+
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL0, 0x0, MISC_CG_CTRL0_W_CHG_MEM);
+}
+#endif
+
+#if ENABLE_DFS_DEBUG_MODE
+static void WaitDFSDebugSM(DRAMC_CTX_T *p, U8 u1HangStatus)
+{
+    U8 u1Status[CHANNEL_NUM] = {0}, u1DvfsState[CHANNEL_NUM] = {0}, u1ChIdx = 0;
+    DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p);
+    U32 u4While1Cnt = 100;
+
+    for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1ChIdx);
+        do {
+            u1Status[u1ChIdx] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_DVFS_STATUS), DVFS_STATUS_CUT_PHY_ST_SHU);
+            u1DvfsState[u1ChIdx] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS2), MRR_STATUS2_DVFS_STATE);
+            //mcSHOW_DBG_MSG(("[WaitDFSDebugSM] CH%d DFS debug mode state (0x%x, 0x%x), Dvfs State = 0x%x\n", u1ChIdx, u1Status[u1ChIdx], u1HangStatus, u1DvfsState[u1ChIdx]));
+            if (u1Status[u1ChIdx] == u1HangStatus)
+                break;
+
+            if (u4While1Cnt == 0)
+            {
+                DDRPhyFreqMeter(p);
+                while(1);
+            }
+            u4While1Cnt--;
+        } while(1);
+    }
+
+    vSetPHY2ChannelMapping(p, eOriChannel);
+}
+
+static void ExitDFSDebugMode(DRAMC_CTX_T *p, DFS_DBG_T eDbgMode)
+{
+    if ((eDbgMode == BEF_DFS_MODE) || (eDbgMode == AFT_DFS_MODE))
+    {
+        vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x0, MISC_DVFSCTL3_RG_DFS_AFT_PHY_SHU_DBG_EN)
+                            | P_Fld(0x0, MISC_DVFSCTL3_RG_DFS_BEF_PHY_SHU_DBG_EN));
+    }
+    else if (eDbgMode == CHG_CLK_MODE)
+    {
+        vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x0, MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_BCLK_BY_LPC_EN)
+                            | P_Fld(0x0, MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_MCLK_BY_LPC_EN));
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CLK_CTRL, 0x0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE); // HW mode
+    }
+    else
+    {
+        mcSHOW_ERR_MSG(("DFS debug mode err!\n"));
+        #if __ETT__
+        while (1);
+        #endif
+    }
+}
+
+static void ChkDFSDebugMode(DRAMC_CTX_T *p, DFS_DBG_T eDbgMode)
+{
+    if (eDbgMode == BEF_DFS_MODE)
+    {
+        WaitDFSDebugSM(p, 0x1);
+    }
+    else if (eDbgMode == AFT_DFS_MODE)
+    {
+        WaitDFSDebugSM(p, 0x1d);
+
+    }
+    else if (eDbgMode == CHG_CLK_MODE)
+    {
+        WaitDFSDebugSM(p, 0x1e);
+
+        // HW shuffle will switch clock to 208MHz and continue DFS
+        vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0xf, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL)
+                            | P_Fld(0x3, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE));
+        mcDELAY_US(1); // Wait 1T 26MHz
+        vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0xf, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL)
+                            | P_Fld(0x0, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE));
+
+        WaitDFSDebugSM(p, 0x1f);
+
+        // HW shuffle will switch clock to MCK and continue DFS
+        vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0x5, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL)
+                            | P_Fld(0x3, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE));
+        mcDELAY_US(1); // Wait 1T 26MHz
+        vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0x5, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL)
+                            | P_Fld(0x0, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE));
+
+    }
+    else
+    {
+        mcSHOW_ERR_MSG(("DFS debug mode err!\n"));
+        #if __ETT__
+        while (1);
+        #endif
+    }
+}
+
+static void EntryDFSDebugMode(DRAMC_CTX_T *p, DFS_DBG_T eDbgMode)
+{
+    if (eDbgMode == BEF_DFS_MODE)
+    {
+        vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x0, MISC_DVFSCTL3_RG_DFS_AFT_PHY_SHU_DBG_EN)
+                            | P_Fld(0x1, MISC_DVFSCTL3_RG_DFS_BEF_PHY_SHU_DBG_EN));
+    }
+    else if (eDbgMode == AFT_DFS_MODE)
+    {
+        vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x1, MISC_DVFSCTL3_RG_DFS_AFT_PHY_SHU_DBG_EN)
+                            | P_Fld(0x0, MISC_DVFSCTL3_RG_DFS_BEF_PHY_SHU_DBG_EN));
+    }
+    else if (eDbgMode == CHG_CLK_MODE)
+    {
+        vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x1, MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_BCLK_BY_LPC_EN)
+                            | P_Fld(0x1, MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_MCLK_BY_LPC_EN));
+        // for DPM RG mode
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CLK_CTRL, 0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE);
+        // for PHY RG mode (no support)
+        //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CLK_CTRL, 0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE);
+    }
+    else
+    {
+        mcSHOW_ERR_MSG(("DFS debug mode err!\n"));
+        #if __ETT__
+        while (1);
+        #endif
+    }
+
+}
+#endif
+
+#if DFS_NOQUEUE_FLUSH_ENABLE
+U32 u4PERFCTL0_backup=0;
+
+void EnableDFSNoQueueFlush(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti_All(DRAMC_REG_DVFS_CTRL0, P_Fld(0, DVFS_CTRL0_HWSET_WLRL)
+        | P_Fld(0, DVFS_CTRL0_DVFS_RXFIFOST_SKIP) // sync MP settings
+        | P_Fld(1, DVFS_CTRL0_DVFS_NOQUEFLUSH_EN)
+        | P_Fld(0, DVFS_CTRL0_R_DMDVFSMRW_EN));
+    vIO32WriteFldMulti_All(DRAMC_REG_SHUCTRL1, P_Fld(0, SHUCTRL1_FC_PRDCNT)
+#if ENABLE_LP4Y_WA
+        //@Berson, LP4Y tCKFSPE/X_SE violation at shuffle as DVFS noqueflush enable
+        // LP4Y tCKFSPE/X_SE violation at shuffle from 7.5ns to 15ns
+        | P_Fld(5, SHUCTRL1_CKFSPE_PRDCNT)
+        | P_Fld(5, SHUCTRL1_VRCGEN_PRDCNT)
+#else
+        | P_Fld(0, SHUCTRL1_CKFSPE_PRDCNT)
+        | P_Fld(0, SHUCTRL1_VRCGEN_PRDCNT)
+#endif
+        | P_Fld(0, SHUCTRL1_CKFSPX_PRDCNT));
+    vIO32WriteFldAlign_All(DRAMC_REG_BYPASS_FSPOP, 0, BYPASS_FSPOP_BPFSP_OPT); // sync MP settings
+
+#if ENABLE_DFS_RUNTIME_MRW // for Skip HW MR2
+    vIO32WriteFldMulti_All(DRAMC_REG_DVFS_TIMING_CTRL3, P_Fld(0, DVFS_TIMING_CTRL3_RTMRW_MRW1_SKIP) // OP CHG & VRCG High
+        | P_Fld(0, DVFS_TIMING_CTRL3_RTMRW_MRW2_SKIP) // VRCG Low
+        | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW3_SKIP)); // MR2 RL/WL (reduce 50ns)
+#endif
+
+#if ENABLE_DFS_NOQUEUE_FLUSH_DBG
+    // for debug mode only (skip HW MRW)
+    vIO32WriteFldMulti_All(DRAMC_REG_DVFS_TIMING_CTRL3, P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW1_PAUSE)
+        | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW2_PAUSE)
+        | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW3_PAUSE));
+#endif
+    //Fix wdle cnt fail issue
+    vIO32WriteFldAlign_All(DRAMC_REG_MISCTL0, 1, MISCTL0_GROUP_A_REV);
+}
+#if 0
+static void WaitNoQueueFlushComplete(DRAMC_CTX_T *p)
+{
+    // for debug mode only
+    U8 u1tCKFSPe_OK[CHANNEL_NUM] = {0};
+    U8 u1tVRCGDis_OK[CHANNEL_NUM] = {0};
+    U8 u1ChIdx = 0;
+    U16 u2Cnt = 0, u2PrintCnt = 1000;
+    DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p);
+
+    for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1ChIdx);
+        do {
+            u1tCKFSPe_OK[u1ChIdx] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS2), MRR_STATUS2_TCKFSPE_OK);
+            if ((u2Cnt++) == u2PrintCnt)
+            {
+                u2Cnt = 0;
+                mcSHOW_ERR_MSG(("MRW1_SKIP FAIL!\n"));
+                while(1);
+            }
+        } while(u1tCKFSPe_OK[u1ChIdx] != 0);
+
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DVFS_TIMING_CTRL3), 1, DVFS_TIMING_CTRL3_RTMRW_MRW1_SKIP);
+
+        do {
+            u1tCKFSPe_OK[u1ChIdx] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS2), MRR_STATUS2_TCKFSPE_OK);
+            u1tVRCGDis_OK[u1ChIdx] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS2), MRR_STATUS2_TVRCG_DIS_OK);
+            if ((u2Cnt++) == u2PrintCnt)
+            {
+                u2Cnt = 0;
+                mcSHOW_ERR_MSG(("MRW2_SKIP FAIL!\n"));
+                while(1);
+            }
+        } while((u1tCKFSPe_OK[u1ChIdx] != 1) && (u1tVRCGDis_OK[u1ChIdx] != 0));
+
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DVFS_TIMING_CTRL3), 1, DVFS_TIMING_CTRL3_RTMRW_MRW2_SKIP);
+
+        do {
+            u1tVRCGDis_OK[u1ChIdx] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS2), MRR_STATUS2_TVRCG_DIS_OK);
+            if ((u2Cnt++) == u2PrintCnt)
+            {
+                u2Cnt = 0;
+                mcSHOW_ERR_MSG(("MRW3_SKIP FAIL!\n"));
+                while(1);
+            }
+        } while(u1tVRCGDis_OK[u1ChIdx] != 1);
+
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DVFS_TIMING_CTRL3), 1, DVFS_TIMING_CTRL3_RTMRW_MRW3_SKIP);
+    }
+
+    vSetPHY2ChannelMapping(p, eOriChannel);
+}
+#endif
+#endif
+
+#if ENABLE_TIMING_TXSR_DFS_WA
+static void TimingTxsrWA(DRAMC_CTX_T *p, U32 next_shu_level)
+{
+    U32 onoff=0, bc_bak=0;
+
+    if (p->support_channel_num > CHANNEL_SINGLE) //for dual single
+    {
+        bc_bak = GetDramcBroadcast();
+        DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+
+    if ((next_shu_level == SRAM_SHU4) || (next_shu_level == SRAM_SHU5)
+        || (next_shu_level == SRAM_SHU6)
+#if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
+        || (next_shu_level == SRAM_SHU7))
+#else
+        )
+#endif
+    {
+        onoff = DISABLE;
+    }
+    else
+    {
+        onoff = ENABLE;
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_REFCTRL1, onoff, REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA);
+
+    if (p->support_channel_num > CHANNEL_SINGLE)
+        DramcBroadcastOnOff(bc_bak);
+}
+#endif
+
+#if ENABLE_TX_REBASE_ODT_WA
+void TxReadBaseODTWA(DRAMC_CTX_T *p, U8 next_shu_level)
+{
+    U32 termen_dis, bc_bak=0;
+
+    if (p->support_channel_num > CHANNEL_SINGLE) //for dual single
+    {
+        bc_bak = GetDramcBroadcast();
+        DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+
+    if ((next_shu_level == SRAM_SHU0) || (next_shu_level == SRAM_SHU1)) // for DDR4266/DDR3200
+        termen_dis = DISABLE; //term
+    else
+        termen_dis = ENABLE; // un-term
+
+    //mcSHOW_DBG_MSG(("[TxReadBaseODTWA] SRAM SHU%d, termen_dis = %d\n", next_shu_level, termen_dis));
+    vIO32WriteFldAlign(DDRPHY_REG_B0_DQ6, termen_dis, B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0);
+    vIO32WriteFldAlign(DDRPHY_REG_B1_DQ6, termen_dis, B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1);
+    vIO32WriteFldAlign(DDRPHY_REG_CA_CMD6, termen_dis, CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS);
+
+    if (p->support_channel_num > CHANNEL_SINGLE) //for dual single
+        DramcBroadcastOnOff(bc_bak);
+}
+#endif
+
+#if ENABLE_TX_REBASE_WDQS_DQS_PI_WA
+static void TxReBaseWDQSDqsPiWA(DRAMC_CTX_T *p, U8 pingpong_shu_level)
+{
+    U32 bc_bak=0;
+
+    if (p->support_channel_num > CHANNEL_SINGLE) //for dual single
+    {
+        bc_bak = GetDramcBroadcast();
+        DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+
+    p->ShuRGAccessIdx = pingpong_shu_level;
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13   , P_Fld(0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0           )
+                                                                | P_Fld(0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0          ) );
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13   , P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1           )
+                                                                | P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1          ) );
+    mcDELAY_US(1);
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13   , P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0           )
+                                                                | P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0          ) );
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13   , P_Fld(1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1           )
+                                                                | P_Fld(1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1          ) );
+    p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
+
+    if (p->support_channel_num > CHANNEL_SINGLE) //for dual single
+        DramcBroadcastOnOff(bc_bak);
+}
+#endif
+
+#if ENABLE_DDR800_SOPEN_DSC_WA
+static void DDR800_SOPEN_DSC_WA(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff)
+{
+    U8 MPDIV_CG, bc_bak = 0;
+
+    if (p->DRAMPinmux != PINMUX_DSC)
+        return;
+
+    if (p->support_channel_num> CHANNEL_SINGLE) //for dual single
+    {
+        bc_bak = GetDramcBroadcast();
+        DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    }
+
+    if ((next_shu_level == SRAM_SHU6) && (u1OnOff==DISABLE))// for DDR800
+    {
+        MPDIV_CG = DISABLE;
+        vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL4, MPDIV_CG, MISC_CTRL4_R_OPT2_MPDIV_CG);
+    }
+    else if ((next_shu_level != SRAM_SHU6) && (u1OnOff==ENABLE))
+    {
+        MPDIV_CG = ENABLE;
+        vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL4, MPDIV_CG, MISC_CTRL4_R_OPT2_MPDIV_CG);
+    }
+
+    if (p->support_channel_num > CHANNEL_SINGLE)
+        DramcBroadcastOnOff(bc_bak);
+}
+#endif
+
+void EnableDFSHwModeClk(DRAMC_CTX_T *p)
+{
+    //Shuffle HW mode for MCK/208M switch
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL3,
+                        P_Fld(0x3, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI) | // dvfs source clock selection when ddrphy shuffle
+                        P_Fld(0x1, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE)); // dvfs destination clock selection when ddrphy shuffle
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CLK_CTRL,
+                        P_Fld(0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN) | //M_CK clock mux selection update enable by shuffle
+                        P_Fld(0x1, MISC_CLK_CTRL_DVFS_CLK_MEM_SEL) | // by shuffle
+                        P_Fld(0x0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE) | // HW mode by shuffle
+                        P_Fld(0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL)); // 4-to-1 mux for PLLCK
+}
+#if 0
+static void DFSEnlargeTimingSettings(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x7f, MISC_SHU_DVFSDLL_R_DLL_IDLE)
+             | P_Fld(0x7f, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE)
+             | P_Fld(0, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL)
+        | P_Fld(0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL));
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL3, P_Fld(1, MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK)
+             | P_Fld(0xf, MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK)
+             | P_Fld(0xf, MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_MCLK)
+        | P_Fld(0x20, MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_MCLK));
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL, P_Fld(0xf, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW)
+             | P_Fld(0xf, MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW)
+             | P_Fld(0xf, MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW)
+             | P_Fld(0xf, MISC_DVFSCTL_R_DVFS_PICG_MARGIN4_NEW)
+        | P_Fld(0xf, MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN));
+}
+#endif
+void DVFSSettings(DRAMC_CTX_T *p)
+{
+    U8 u1DVFS_52M_104M_SEL = 1; // DVFS_SM freq: 0: 52Mhz 1:104Mhz
+    U8 u1Master_DLL_Idle = 0x2b; // Master from MCK
+    U8 u1Slave_DLL_Idle = 0x43; // Slave from MCK
+#if (fcFOR_CHIP_ID == fcA60868) // @Darren, for A60868 only
+    U8 u1ChClkIgnore[2] = {ENABLE, ENABLE}, u1Channel = 0; // 1=ignore
+#endif
+    U32 backup_broadcast = GetDramcBroadcast();
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+    if (vGet_Div_Mode(p) == DIV16_MODE)
+    {
+        u1Master_DLL_Idle = 0x37; // Master from MCK
+        u1Slave_DLL_Idle = 0x4D; // Slave from MCK
+    }
+
+    //DVFS debug enable - MRR_STATUS2_DVFS_STATE
+    //@Lynx, A60868 HW always enable shuffle debug. remove RG: DVFSDLL_R_DDRPHY_SHUFFLE_DEBUG_ENABLE
+    //vIO32WriteFldAlign_All(DRAMC_REG_DVFSDLL, 1, DVFSDLL_R_DDRPHY_SHUFFLE_DEBUG_ENABLE);
+
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, u1DVFS_52M_104M_SEL, MISC_CKMUX_SEL_RG_52M_104M_SEL); //Set DVFS_SM's clk
+#if ENABLE_DFS_208M_CLOCK
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, 0x1, MISC_CKMUX_SEL_RG_104M_208M_SEL); //Set DVFS_SM's clk to 208M
+#endif
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(u1Master_DLL_Idle, MISC_SHU_DVFSDLL_R_DLL_IDLE)
+        | P_Fld(u1Slave_DLL_Idle, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE));
+
+    // @Darren, set current SRAM SHU index for SPM mode DFS latch/restore
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, vGet_Current_SRAMIdx(p), MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM);
+    //mcSHOW_DBG_MSG(("[DVFSSettings] SHU_LEVEL_SRAM = %d\n", vGet_Current_SRAMIdx(p)));
+
+#if (fcFOR_CHIP_ID == fcA60868) // @Darren, for A60868 only
+    for (u1Channel = CHANNEL_A; u1Channel < p->support_channel_num; u1Channel++)
+        u1ChClkIgnore[u1Channel] = DISABLE;
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(u1ChClkIgnore[1], MISC_DVFSCTL2_RG_IGNORE_PHY_SH_CHG_CLK_RDY_CHB)
+        | P_Fld(u1ChClkIgnore[0], MISC_DVFSCTL2_RG_IGNORE_PHY_SH_CHG_CLK_RDY_CHA));
+#endif
+    // DFS trigger by DDRPHY RG
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); // DFS RG mode for calibration
+    //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_TX_TRACKING_DIS); // DFS RG mode for disable tx tracking
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 1, MISC_DVFSCTL2_RG_MRW_AFTER_DFS);
+
+    vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_FSM_CFG_1, P_Fld(1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL)
+        | P_Fld(1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND)
+        | P_Fld(1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR)
+        | P_Fld(1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND));
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_OPT, P_Fld(1, MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN)
+        | P_Fld(1, MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN));
+#if ENABLE_DFS_HW_SAVE_MASK
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 1, MISC_DVFSCTL2_DVFS_SYNC_MASK_FOR_PHY); // 0x1 = disable dfs hw save
+#endif
+
+#if 0 // @Darren, reserved from Mengru Dsim
+    U8 u1MarginNew = (u1DVFS_52M_104M_SEL == 1) ? 0x3 : 0x1;
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_OPT, 0x2, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN);
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL, P_Fld(u1MarginNew, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW)
+             | P_Fld(u1MarginNew, MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW)
+        | P_Fld(u1MarginNew, MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW));
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, 0x1, MISC_CKMUX_SEL_FMEM_CK_MUX);
+    vIO32WriteFldMulti_All(DRAMC_REG_DVFS_CTRL0, P_Fld(0x1, DVFS_CTRL0_R_DRAMC_CHA)
+             | P_Fld(0x0, DVFS_CTRL0_DVFS_CKE_OPT)
+             | P_Fld(0x1, DVFS_CTRL0_SCARB_PRI_OPT)
+        | P_Fld(0x0, DVFS_CTRL0_SHU_PHYRST_SEL));
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(0x1, MISC_DVFSCTL2_R_DVFS_PARK_N)
+        | P_Fld(0x1, MISC_DVFSCTL2_R_DVFS_OPTION));
+#endif
+
+#if ENABLE_BLOCK_APHY_CLOCK_DFS_OPTION
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL7, 1, MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL);
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL, P_Fld(1, MISC_DVFSCTL_R_DVFS_PICG_POSTPONE)
+        | P_Fld(1, MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT));
+#endif
+
+#if ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION // @Mazar
+    //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFS_EMI_CLK, 1, MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY);
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL, P_Fld(1, MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE)
+        | P_Fld(3, MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN)
+        | P_Fld(3, MISC_DVFSCTL_R_DVFS_PICG_MARGIN4_NEW));
+#endif
+
+#if (fcFOR_CHIP_ID == fc8195) // @Darren, for Mar_gaux New setting for ddrphy shuffle (sync mode)
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_DVFSCTL2, 0, MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL);
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_DVFSCTL2 + SHIFT_TO_CHB_ADDR, 1, MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL);
+#if CHANNEL_NUM > 2
+	if (channel_num_auxadc > 2) {
+	    vIO32WriteFldAlign(DDRPHY_REG_MISC_DVFSCTL2 + SHIFT_TO_CHC_ADDR, 0, MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL);
+    	vIO32WriteFldAlign(DDRPHY_REG_MISC_DVFSCTL2 + SHIFT_TO_CHD_ADDR, 1, MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL);
+		}
+#endif
+#endif
+
+    //DLL_SHUFFLE should be set enable before switch frequency
+    // @Darren, func is empty after IPM via @Mazar
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFS_EMI_CLK, 0, MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 0, MISC_DVFSCTL2_RG_DLL_SHUFFLE);
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(0, MISC_DVFSCTL2_R_DVFS_OPTION)
+        | P_Fld(0, MISC_DVFSCTL2_R_DVFS_PARK_N));
+
+#if 0
+    if (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE)
+    {
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_DVFSDLL, 1, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL);
+    }
+#endif
+
+#if ENABLE_DFS_TIMING_ENLARGE
+    DFSEnlargeTimingSettings(p);
+#endif
+
+    //EnableDFSHwModeClk(p); // @Darren, for DFS shuffle change
+
+    DramcBroadcastOnOff(backup_broadcast);
+}
+
+#if ENABLE_DFS_SSC_WA
+void DDRSSCSetting(DRAMC_CTX_T * p)
+{
+    U32 u4DELTA1 = 0;
+
+    if (p->frequency == 1866)
+    {
+        u4DELTA1 = 0xE14;
+    }
+    else if (p->frequency == 1600)
+    {
+        u4DELTA1 = 0xC1C;
+    }
+    else if (p->frequency == 1200)
+    {
+        u4DELTA1 = 0x90F;
+    }
+    else
+    {
+        return;
+    }
+
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL1, 0x1, SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL1, 0x1, SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN);
+
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL6, 0x1, SHU_PHYPLL6_RG_RPHYPLL_SDM_SSC_PH_INIT);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CLRPLL6, 0x1, SHU_CLRPLL6_RG_RCLRPLL_SDM_SSC_PH_INIT);
+
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL6, 0x0208, SHU_PHYPLL6_RG_RPHYPLL_SDM_SSC_PRD);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CLRPLL6, 0x0208, SHU_CLRPLL6_RG_RCLRPLL_SDM_SSC_PRD);
+
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL7, 0x0, SHU_PHYPLL7_RG_RPHYPLL_SDM_SSC_DELTA);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CLRPLL7, 0x0, SHU_CLRPLL7_RG_RCLRPLL_SDM_SSC_DELTA);
+
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL7, u4DELTA1, SHU_PHYPLL7_RG_RPHYPLL_SDM_SSC_DELTA1);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CLRPLL7, u4DELTA1, SHU_CLRPLL7_RG_RCLRPLL_SDM_SSC_DELTA1);
+
+    //vIO32WriteFldAlign_All(DDRPHY_PLL1, 0x1, PLL1_RG_RPHYPLL_SDM_SSC_EN);
+    //vIO32WriteFldAlign_All(DDRPHY_PLL2, 0x1, PLL2_RG_RCLRPLL_SDM_SSC_EN);
+}
+
+static void DramcSSCHoppingOnOff(DRAMC_CTX_T *p, U8 cur_shu_level, U8 u1OnOff)
+{
+    if ((cur_shu_level == 0x0) || (cur_shu_level == 0x8) || (cur_shu_level == 0x9) || (cur_shu_level == 0x6) || (cur_shu_level == 0x5))
+    {
+        if (!(p->u1PLLMode == PHYPLL_MODE))
+            vIO32WriteFldAlign(DDRPHY_REG_CLRPLL0, u1OnOff, CLRPLL0_RG_RCLRPLL_SDM_SSC_EN); // CLRPLL SSC
+        else
+            vIO32WriteFldAlign(DDRPHY_REG_PHYPLL0, u1OnOff, PHYPLL0_RG_RPHYPLL_SDM_SSC_EN); // PHYPLL SSC
+    }
+}
+#endif
+
+
+#if DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM || ENABLE_DFS_SSC_WA
+void DVS_DMY_RD_ENTR(DRAMC_CTX_T *p)
+{
+    /*TINFO="DRAM : SPM DVS DMY RD ENTR"*/
+
+    /*TINFO="DRAM : set sc_ddrphy_fb_ck_en = 1"*/
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 1, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
+
+
+    mcDELAY_US(1);
+
+    /*TINFO="DRAM : set sc_dmyrd_en_mod_sel = 1"*/
+    //! diff with WE
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL);
+
+    mcDELAY_US(1);
+
+    /*TINFO="DRAM : set sc_dmyrd_intv_sel = 1"*/
+    //! diff with WE
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL);
+
+    mcDELAY_US(1);
+
+    /*TINFO="DRAM : set sc_dmyrd_en = 1"*/
+    //! diff with WE
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DMYRD_EN);
+
+    mcDELAY_US(1);
+}
+
+void DVS_DMY_RD_EXIT(DRAMC_CTX_T *p)
+{
+    /*TINFO="DRAM : SPM DVS DMY RD EXIT"*/
+
+    /*TINFO="DRAM : set sc_dmyrd_en = 0"*/
+    //! diff with WE
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DMYRD_EN);
+
+    mcDELAY_US(1);
+
+    /*TINFO="DRAM : set sc_dmyrd_intv_sel = 0"*/
+    //! diff with WE
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL);
+
+    mcDELAY_US(1);
+
+    /*TINFO="DRAM : set sc_dmyrd_en_mod_sel = 0"*/
+    //! diff with WE
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL);
+
+    mcDELAY_US(1);
+
+    /*TINFO="DRAM : set sc_ddrphy_fb_ck_en = 0"*/
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
+
+    mcDELAY_US(1);
+
+
+    /*TINFO="DRAM : SPM DVS DMY RD EXIT end "*/
+}
+#endif
+
+
+#if 1//(FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
+static void EnableDramcTrackingByShuffle(DRAMC_CTX_T *p, U8 u1EnDPMCh, U8 u1OnOff)
+{
+    if (u1OnOff == ENABLE)
+    {
+    #if ENABLE_RX_TRACKING
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1EnDPMCh, LPIF_LOW_POWER_CFG_1_DPHY_RXDLY_TRACK_EN);
+        //RX delay cell use Vmddr in all freq, so rx tracking is not needed.
+    #endif
+    #if ENABLE_TX_TRACKING
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_TX_TRACKING_DIS);
+        //The LPDDR4 DRAM cannot be placed in power-down state during "Start DQS Interval Oscillator" operation.
+    #endif
+    }
+    else if (u1OnOff == DISABLE)
+    {
+    #if ENABLE_RX_TRACKING
+        mcSHOW_DBG_MSG4(("Disable RX-Tracking\n"));
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DPHY_RXDLY_TRACK_EN);
+    #endif
+    #if ENABLE_TX_TRACKING
+        mcSHOW_DBG_MSG4(("Disable TX-Tracking\n"));
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1EnDPMCh, LPIF_LOW_POWER_CFG_1_TX_TRACKING_DIS);
+    #endif
+    }
+}
+
+#if 0
+static void EnableDramcTrackingBySPMControl(DRAMC_CTX_T *p)
+{
+    if (p->frequency >= 1600)
+        vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DPHY_RXDLY_TRACK_EN);
+}
+
+static void TransferToRegControl(void)
+{
+    /* Chen-Hsiang@20160323: After leave preloader and low power scenario, conf is controller by RG*/
+}
+
+
+static void TransferToSPMControl(DRAMC_CTX_T *p)//Open all APHY controls from SPM path except PWR_ON && ISO (related to low power and DVFS)
+{
+#if ENABLE_TX_TRACKING //HW mode
+    vIO32WriteFldAlign_All(DRAMC_REG_TX_TRACKING_SET0, 0x0, TX_TRACKING_SET0_TX_TRACKING_OPT);//Set TX_TRACKING_OPT = 0 to let spm side band control HW TX tracking
+#endif
+#if 0 // Low power features remove to others RG: B0_LP_CTRL0/B1_LP_CTRL/CA_LP_CTRL/MISC_LP_CTRL
+    vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL0, 0xfbffefff, MISC_SPM_CTRL0_PHY_SPM_CTL0);
+    vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL2, 0xffffffef, MISC_SPM_CTRL2_PHY_SPM_CTL2);
+    vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL2 + SHIFT_TO_CHB_ADDR, 0x7fffffef, MISC_SPM_CTRL2_PHY_SPM_CTL2);//Lewis@20170627: Set CHB CA DLL type to slave mode
+#endif
+
+    return;
+}
+#endif
+void DPMEnableTracking(DRAMC_CTX_T *p, U32 u4Reg, U32 u4Field, U8 u1ShuIdx, U8 u1Enable)
+{
+    U32 val, fld;
+
+    fld = Fld(1, (Fld_shft(u4Field) + u1ShuIdx));
+
+    val = (u1Enable) ? 1 : 0;
+
+    vIO32WriteFldAlign_All(u4Reg, u1Enable, fld);
+}
+
+void DPMInit(DRAMC_CTX_T *p)
+{
+    U8 u1SetVal;
+    U8 u1Pll1Val, u1Pll2Val;
+    U8 u1ShuSramVal;
+    DRAM_DFS_SRAM_SHU_T u1CurrShuLevel = vGet_Current_SRAMIdx(p);
+
+    u1SetVal = (p->support_channel_num > 1) ? 0x3 : 0x1;
+
+    // pre-setting DPM to dramc low power interface setting
+    vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0,
+            P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_PHYPLL_EN) |	// both channel phy pll en
+            P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_DLL_EN) |	// both channel dpy pll en
+            P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN) | // both channel dpy 2nd pll en
+            P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN) |  // both channel dpy dll ck en
+            P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_VREF_EN)); // both channel dpy vref en
+
+    vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3,
+            P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_MCK8X_EN) |    // both channel mck8x en
+            P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_MIDPI_EN) |    // both channel midpi en
+            P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_PI_RESETB_EN));    // both channel dpy pi resetb en
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+    {
+        mcSHOW_DBG_MSG2(("PHYPLL\n"));
+        u1Pll1Val = u1SetVal;
+        u1Pll2Val = 0;
+    }
+    else
+    {
+        mcSHOW_DBG_MSG2(("CLRPLL\n"));
+        u1Pll1Val = 0;
+        u1Pll2Val = u1SetVal;
+    }
+
+    vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0,
+            P_Fld(u1Pll1Val, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN) |
+            P_Fld(u1Pll1Val, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW) |
+            P_Fld(u1Pll2Val, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN) |
+            P_Fld(u1Pll2Val, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW));
+
+    // all by lpif fw mode
+    vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_FSM_CFG_1,
+            /* TBA set control mux in DV initial */
+            P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) |                // 0: DPM, 1: SPM
+            P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND) |            // 0: DPM, 1: SPM
+            P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR) |        // 0: DPM, 1: SPM
+            P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND) |    // 0: DPM, 1: SPM
+            P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW) |           // 0: DPM SCU, 1: DPM CFG
+            P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND) |       // 0: DPM SCU, 1: DPM CFG
+            P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL) |             // 0: DPM SCU, 1: DPM CFG
+            P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL_2ND));         // 0: DPM SCU, 1: DPM CFG
+
+    vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_0,
+            P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_EN) |
+            P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_EN) |
+            P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_2ND_DLL_EN) |
+            P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_CK_EN) |
+            P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_VREF_EN) |
+            P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN) | // @Darren, fix dfs phypll init
+            P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_MODE_SW));
+
+    u1ShuSramVal = u1CurrShuLevel;
+
+    if (p->support_channel_num > 1)
+        u1ShuSramVal |= u1CurrShuLevel << 4;
+
+    // NOTE: DPM PST mode shuffle level = (LPIF_CTRL_CTRL1_LPIF_DRAMC_DR_SHU_LEVEL_SRAM | LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL)
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1ShuSramVal, LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL);
+
+#if __ETT__
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_SSPM_CFGREG_GPR0, 0xE7700E77, SSPM_CFGREG_GPR0_GPR0);
+#endif
+    // for DFS
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0x0, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL);
+    vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0x0, PHYPLL0_RG_RPHYPLL_EN);
+    vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0x0, CLRPLL0_RG_RCLRPLL_EN);
+
+    // enable DFD
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_DFD_DBUG_0 , 0x1, LPIF_DFD_DBUG_0_LPIF_DFD_DEBUG_ISO_EN);
+}
+#endif
+
+
+#if ENABLE_DVFS_BYPASS_MR13_FSP
+void DFSBypassMR13HwSet(DRAMC_CTX_T *p)
+{
+#if __A60868_TO_BE_PORTING__
+    U8 u1ShuffleIdx, BFSP = 0, u1SramShuIdx = 0;
+    REG_TRANSFER_T TransferReg;
+
+    TransferReg.u4Addr = DRAMC_REG_BYPASS_FSPOP;
+    TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU3;
+    for (u1ShuffleIdx = 0; u1ShuffleIdx < DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
+    {
+        u1SramShuIdx = gFreqTbl[u1ShuffleIdx].SRAMIdx;
+        switch (u1SramShuIdx)
+        {
+            case 0:
+                TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU0;
+                break;
+            case 1:
+                TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU1;
+                break;
+            case 2:
+                TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU2;
+                break;
+            case 3:
+                TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU3;
+                break;
+            case 4:
+                TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU4;
+                break;
+            case 5:
+                TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU5;
+                break;
+            case 6:
+                TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU6;
+                break;
+            case 7:
+                TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU7;
+                break;
+            case 8:
+                TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU8;
+                break;
+            case 9:
+                TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU9;
+                break;
+            default:
+                mcSHOW_ERR_MSG(("[DFSBypassMR13HwSet] fail at BPFSP_SHU%d incorrect !!!\n", u1SramShuIdx));
+                break;
+        }
+        BFSP = (gFreqTbl[u1ShuffleIdx].freq_sel <= LP4_DDR2667)? 0x1: 0x0; //0x1 (Bypass), 0x0 (Not bypass)
+        //mcSHOW_DBG_MSG(("[DFSBypassMR13HwSet] BPFSP_SHU%d = 0x%x\n", u1SramShuIdx, BFSP));
+        vIO32WriteFldAlign_All(TransferReg.u4Addr, BFSP, TransferReg.u4Fld);
+    }
+    vIO32WriteFldAlign_All(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0, 0x1, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT); // 1: shuffle level = 10, 0: shuffle level =4
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CDC_CTRL, 0x0, MISC_CDC_CTRL_REG_CDC_BYPASS_DBG);
+    vIO32WriteFldAlign_All(DRAMC_REG_BYPASS_FSPOP, 0x1, BYPASS_FSPOP_BPFSP_OPT);
+#endif
+}
+#endif
+
+#if FOR_DV_SIMULATION_USED
+void DFSSwitchtoRGMode(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL);
+}
+#endif
+#if 0
+static U8 vGet_Current_SRAMShuLevel(DRAMC_CTX_T *p)
+{
+    U8 curr_shu_level;
+
+    curr_shu_level = u4IO32ReadFldAlign(DDRPHY_REG_MISC_RG_DFS_CTRL, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM);
+
+    return curr_shu_level;
+}
+#endif
+void DramcSaveToShuffleSRAM(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T srcRG, DRAM_DFS_SRAM_SHU_T dstRG)
+{
+    U8 u1ChIdx;
+    U8 u1value;
+    DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p);
+
+    for (u1ChIdx = 0; u1ChIdx < p->support_channel_num; u1ChIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1ChIdx);
+
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_DMA_FIRE);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_APB_SLV_SEL);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_MODE);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_STEP_EN_MODE);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SRAM_WR_MODE);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_APB_WR_MODE);
+
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), srcRG, MISC_SRAM_DMA0_SW_SHU_LEVEL_APB);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), dstRG, MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_DMA_FIRE);
+        do {
+            u1value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DMA_DEBUG0), MISC_DMA_DEBUG0_SRAM_DONE);
+            u1value |= (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DMA_DEBUG0), MISC_DMA_DEBUG0_APB_DONE) << 1);
+            mcSHOW_DBG_MSG4(("\twait dramc to shuffle sram done.\n"));
+        } while (u1value != 0x3);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_DMA_FIRE);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_STEP_EN_MODE);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_MODE);
+    }
+
+    vSetPHY2ChannelMapping(p, eOriChannel);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0, MISC_SRAM_DMA0_SRAM_WR_MODE); //MP setting:should disable WR MDOE
+}
+
+void LoadShuffleSRAMtoDramc(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T srcRG, DRAM_DFS_REG_SHU_T dstRG)
+{
+    U8 u1ChIdx;
+    U8 u1value;
+    DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p);
+
+    for (u1ChIdx = 0; u1ChIdx < p->support_channel_num; u1ChIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1ChIdx);
+
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_DMA_FIRE);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_APB_SLV_SEL);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_MODE);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_STEP_EN_MODE);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SRAM_WR_MODE); //diff with DramcSaveToShuffleSRAM
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_APB_WR_MODE); // diff with DramcSaveToShuffleSRAM
+
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), dstRG, MISC_SRAM_DMA0_SW_SHU_LEVEL_APB);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), srcRG, MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_DMA_FIRE);
+        do {
+            u1value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DMA_DEBUG0), MISC_DMA_DEBUG0_SRAM_DONE);
+            u1value |= (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DMA_DEBUG0), MISC_DMA_DEBUG0_APB_DONE) << 1);
+            mcSHOW_DBG_MSG4(("\twait shuffle sram to dramc done.\n"));
+        } while (u1value != 0x3);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_DMA_FIRE);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_STEP_EN_MODE);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_MODE);
+    }
+
+    vSetPHY2ChannelMapping(p, eOriChannel);
+}
+
+static U8 WaitChShuEnAck(DRAMC_CTX_T *p, U32 u4Addr, U32 u4Fld, U8 u1Status)
+{
+    U8 u1WaitShuAckState = 0, u1ChIdx = 0, u1AckDone = 0;
+    DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p);
+
+    for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1ChIdx);
+
+        do {
+            u1WaitShuAckState = u4IO32ReadFldAlign(DRAMC_REG_ADDR(u4Addr), u4Fld);
+            //mcSHOW_DBG_MSG(("[WaitChShuEnAck] Wait Shu Ack State = 0x%x\n", u1WaitShuAckState));
+            if (u1WaitShuAckState == u1Status)
+                break;
+        } while(1);
+
+        u1AckDone |= (0x1 << u1ChIdx);
+    }
+    vSetPHY2ChannelMapping(p, eOriChannel);
+
+    return u1AckDone; // shu end
+}
+
+void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_level)
+{
+    U8 u1ShuAck = 0, u1SramAck = 0;
+    U8 i = 0;
+    U8 u1ChkComplete = 1;
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+    {
+        mcSHOW_DBG_MSG4(("Disable CLRPLL\n"));
+        vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN);
+    }
+    else
+    {
+        mcSHOW_DBG_MSG4(("Disable PHYPLL\n"));
+        vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN);
+    }
+
+    for (i = 0; i < p->support_channel_num; i++)
+    {
+        u1ShuAck |= (0x1 << i);
+    }
+
+    /* cc: Fix RG mode Hang. Since ACK is read from DPM and a DPM can only support up to 2 dram channels */
+    u1SramAck = u1ShuAck;
+    u1ShuAck &= 0x3;
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+    {
+        mcSHOW_DBG_MSG4(("DFSDirectJump to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
+    }
+    else
+    {
+        mcSHOW_DBG_MSG4(("DFSDirectJump to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
+    }
+
+    /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN);
+
+    // sram latch
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH);
+    mcDELAY_US(1);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH);
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+    {
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN);
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, !p->u1PLLMode, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL);
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN);
+        mcSHOW_DBG_MSG4(("Enable CLRPLL\n"));
+    }
+    else
+    {
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN);
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, !p->u1PLLMode, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL);
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN);
+        mcSHOW_DBG_MSG4(("Enable PHYPLL\n"));
+    }
+    mcDELAY_US(1);
+
+#if 1 //Darren-
+    //vIO32WriteFldMulti((DDRPHY_MISC_SPM_CTRL3), P_Fld(0, MISC_SPM_CTRL3_RG_DR_SHU_LEVEL_SRAM_CH1)
+    //                    | P_Fld(0, MISC_SPM_CTRL3_RG_DR_SHU_LEVEL_SRAM_CH0));
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, shu_level, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM);
+
+    //wait sram load ack.
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD);
+    //while (!u4IO32ReadFldAlign(DDRPHY_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_PLL_LOAD_ACK)); // wait SRAM PLL load ack
+    while (WaitChShuEnAck(p, DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK, u1ChkComplete) != u1SramAck)
+    //while (!u4IO32ReadFldAlign(DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK))
+    {
+        mcSHOW_DBG_MSG4(("\twait sram load ack.\n"));
+    }
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD);
+#endif
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+    {
+        //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW);
+        vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 1, CLRPLL0_RG_RCLRPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control
+    }
+    else
+    {
+        //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW);
+        vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 1, PHYPLL0_RG_RPHYPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control
+    }
+
+    #if 0//ENABLE_DFS_DEBUG_MODE
+    EntryDFSDebugMode(p, CHG_CLK_MODE);
+    #endif
+
+#if ENABLE_DDR800_SOPEN_DSC_WA
+    DDR800_SOPEN_DSC_WA(p, shu_level, DISABLE);
+#endif
+
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+    mcDELAY_US(20); // for SRAM shuffle DV sim spec > 20us
+#else
+    mcDELAY_XUS(20); // for SRAM shuffle DV sim spec > 20us
+#endif
+
+#if 0
+    mcSHOW_DBG_MSG3(("Enable SHORT-QUEUE\n"));
+    vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE);
+
+    mcSHOW_DBG_MSG3(("\twait 5us for short queue ack.\n"));
+    mcDELAY_US(5);
+#endif
+
+    //mcSHOW_DBG_MSG(("Disable RX-Tracking\n"));
+    //vIO32WriteFldAlign(SPM_SW_RSV_8, 0, SW_RSV_8_RX_TRACKING_EN);
+
+    mcSHOW_DBG_MSG4(("SHUFFLE Start\n"));
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_EN); // NOTE: from SHU_EN=1 to ACK, DV spec < 5.1us
+
+#if DFS_NOQUEUE_FLUSH_ENABLE && ENABLE_DFS_NOQUEUE_FLUSH_DBG
+    WaitNoQueueFlushComplete(p); // for debug mode MRW skip
+#endif
+
+    // Fixed DV sim spec for DFS shu_en=1 < 5.1us and shu_en=0 < 120ns
+#if 1//Darren-for test chip(FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+    //mcSHOW_DBG_MSG3(("\twait 5us for shu_en ack.\n"));
+    //mcDELAY_US(5);
+    #if 0//ENABLE_DFS_DEBUG_MODE
+    ChkDFSDebugMode(p, CHG_CLK_MODE);
+    #endif
+
+    //while (WaitChShuEnAck(p, DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE, u1ShuAckState) != u1ShuAck) // SHUFFLE_END
+    //@tg Fix RG mode can not recevie shuffle end ack.
+if (channel_num_auxadc <= 2) {
+    while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck)
+    {
+	mcSHOW_DBG_MSG4(("\twait shu_en ack.\n"));
+    }
+    }
+else {
+    while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck
+	    || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck)
+    {
+        mcSHOW_DBG_MSG4(("\twait shu_en ack.\n"));
+    }
+    }
+
+#else
+    while (u4IO32ReadFldAlign(DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE) != u1ShuAckState); // SHUFFLE_END
+#endif
+
+    #if 0//ENABLE_DFS_DEBUG_MODE
+    ExitDFSDebugMode(p, CHG_CLK_MODE);
+    #endif
+
+#if ENABLE_TX_REBASE_WDQS_DQS_PI_WA
+    TxReBaseWDQSDqsPiWA(p, !p->u1PLLMode);
+#endif
+
+#if ENABLE_TX_REBASE_ODT_WA
+    TxReadBaseODTWA(p, shu_level);
+#endif
+
+    //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_EN); // NOTE: from ACK to SHU_EN=0, DV spec < 120ns
+    mcSHOW_DBG_MSG4(("SHUFFLE End\n"));
+
+#if ENABLE_DDR800_SOPEN_DSC_WA
+    DDR800_SOPEN_DSC_WA(p, shu_level, ENABLE);
+#endif
+
+    //if(shu_level == 0)//LP4-2CH
+    //{
+        //mcSHOW_DBG_MSG(("Enable RX-Tracking for shuffle-0\n"));
+        //vIO32WriteFldAlign(SPM_SW_RSV_8, 3, SW_RSV_8_RX_TRACKING_EN);
+    //}
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+    {
+        /*TINFO="DRAM : set sc_phypll_mode_sw=0"*/
+        //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); // Disable PHYPLL
+        vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control
+    }
+    else
+    {
+        /*TINFO="DRAM : set sc_phypll2_mode_sw=0"*/
+        //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); // Disable CLRPLL
+        vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control
+    }
+
+#if 1 //Darren-
+    //wait sram restore ack.
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE);
+    while (WaitChShuEnAck(p, DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK, u1ChkComplete) != u1SramAck)
+    //while (!u4IO32ReadFldAlign(DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK))
+    {
+        mcSHOW_DBG_MSG4(("\twait sram restore ack.\n"));
+    }
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE);
+
+    /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN);
+#endif
+
+    #if ENABLE_TIMING_TXSR_DFS_WA
+    TimingTxsrWA(p, shu_level);
+    #endif
+
+    p->u1PLLMode = !p->u1PLLMode;
+
+    mcSHOW_DBG_MSG4(("Shuffle flow complete\n"));
+
+    return;
+}
+
+
+void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_level)
+{
+    U8 u1ShuAck = 0;
+    U8 i = 0;
+    U8 u1shu_level = 0;
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+    {
+        mcSHOW_DBG_MSG4(("Disable CLRPLL\n"));
+        vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN);
+    }
+    else
+    {
+        mcSHOW_DBG_MSG4(("Disable PHYPLL\n"));
+        vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN);
+    }
+
+    for (i = 0; i < p->support_channel_num; i++)
+    {
+        u1ShuAck |= (0x1 << i);
+    }
+
+    /* cc: Fix RGmode Hang. Since ACK is read from DPM and a DPM can only support up to 2 dram channels */
+    u1ShuAck &= 0x3;
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+    {
+        mcSHOW_DBG_MSG4(("DFSDirectJump_RGMode to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
+    }
+    else
+    {
+        mcSHOW_DBG_MSG4(("DFSDirectJump_RGMode to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
+    }
+
+    /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN);
+
+    if (shu_level == DRAM_DFS_REG_SHU0)
+        u1shu_level = shu_level; // Darren: shuffle to shu0 status (original calib flow.)
+    else
+        u1shu_level = 1; // Darren: Using shu1 for backup/restore, it diff with SPM mode
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+    {
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN);
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, u1shu_level, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL);
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN);
+        mcSHOW_DBG_MSG4(("Enable CLRPLL\n"));
+    }
+    else
+    {
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN);
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, u1shu_level, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL);
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN);
+        mcSHOW_DBG_MSG4(("Enable PHYPLL\n"));
+    }
+    mcDELAY_US(1);
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+    {
+        //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW);
+        vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 1, CLRPLL0_RG_RCLRPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control
+    }
+    else
+    {
+        //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW);
+        vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 1, PHYPLL0_RG_RPHYPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control
+    }
+
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+    mcDELAY_US(20); // for SRAM shuffle DV sim spec > 20us
+#else
+    mcDELAY_XUS(20); // for SRAM shuffle DV sim spec > 20us
+#endif
+
+#if 0
+    mcSHOW_DBG_MSG3(("Enable SHORT-QUEUE\n"));
+    vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE);
+
+    mcSHOW_DBG_MSG3(("\twait 5us for short queue ack.\n"));
+    mcDELAY_US(5);
+#endif
+
+    //mcSHOW_DBG_MSG(("Disable RX-Tracking\n"));
+    //vIO32WriteFldAlign(SPM_SW_RSV_8, 0, SW_RSV_8_RX_TRACKING_EN);
+
+
+    mcSHOW_DBG_MSG4(("SHUFFLE Start\n"));
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_EN);
+
+    //mcSHOW_DBG_MSG3(("\twait 5us for shu_en ack.\n"));
+    //mcDELAY_US(5);
+    //while (WaitChShuEnAck(p, DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE, u1ShuAckState) != u1ShuAck) // SHUFFLE_END
+    //@tg Fix RG mode can not recevie shuffle end ack.
+if (channel_num_auxadc <= 2) {
+    while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck)
+	{
+        mcSHOW_DBG_MSG4(("\twait shu_en ack.\n"));
+    }
+    }
+else {
+    while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck
+//#if CHANNEL_NUM > 2
+	    || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck)
+//#endif
+    {
+        mcSHOW_DBG_MSG4(("\twait shu_en ack.\n"));
+    }
+	}
+
+    //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_EN);
+    mcSHOW_DBG_MSG4(("SHUFFLE End\n"));
+
+    //if(shu_level == 0)//LP4-2CH
+    //{
+        //mcSHOW_DBG_MSG(("Enable RX-Tracking for shuffle-0\n"));
+        //vIO32WriteFldAlign(SPM_SW_RSV_8, 3, SW_RSV_8_RX_TRACKING_EN);
+    //}
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+    {
+        /*TINFO="DRAM : set sc_phypll_mode_sw=0"*/
+        //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); // Disable PHYPLL
+        vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control
+    }
+    else
+    {
+        /*TINFO="DRAM : set sc_phypll2_mode_sw=0"*/
+        //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); // Disable CLRPLL
+        vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control
+    }
+
+    /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN);
+
+    mcSHOW_DBG_MSG4(("Shuffle flow complete\n"));
+
+    p->u1PLLMode = !p->u1PLLMode;
+    return;
+}
+
+void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_level)
+{
+    U8 u1ShuAck = 0, u1EnDPMCh = 0;
+    U8 u1ChIdx = 0;
+    U8 u1ChNum_dpm = (p->support_channel_num==CHANNEL_SINGLE)?0x1:0x2;
+    U8 pingpong_shu_level = 0; // for shu0/1
+    U8 u1PingPong = 0;
+    U16 u2SramLevel = 0;
+
+    for (u1ChIdx = 0; u1ChIdx < u1ChNum_dpm; u1ChIdx++)
+    {
+        u1ShuAck |= (0x1 << u1ChIdx);
+        u1EnDPMCh |= (0x1 << u1ChIdx);
+    }
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+    {
+        mcSHOW_DBG_MSG4(("DramcDFSDirectJump_SPMMode to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
+    }
+    else
+    {
+        mcSHOW_DBG_MSG4(("DramcDFSDirectJump_SPMMode to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
+    }
+
+    //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x1, MISC_STBCAL2_STB_DBG_STATUS); // HJ Huang
+    /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, u1EnDPMCh, LPIF_LOW_POWER_CFG_2_DR_SHU_LEVEL_SRAM_LATCH);
+    mcDELAY_US(1);
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, 0, LPIF_LOW_POWER_CFG_2_DR_SHU_LEVEL_SRAM_LATCH);
+
+    //LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL[1:0] for CHA
+    //LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL[3:2] for CHB
+    pingpong_shu_level = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_10, LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL); // read shuffle level for dramc conf0/1
+    mcSHOW_DBG_MSG4(("Ping-pong CONF%d\n", (pingpong_shu_level & 0x1)));
+    for (u1ChIdx = 0; u1ChIdx < u1ChNum_dpm; u1ChIdx++)
+    {
+        u2SramLevel |= (shu_level << (u1ChIdx*4));
+        u1PingPong |= (!(pingpong_shu_level & 0x1)) << (u1ChIdx*2);
+    }
+    pingpong_shu_level = u1PingPong;
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+    {
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN);
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, pingpong_shu_level, LPIF_LOW_POWER_CFG_1_DR_SHU_LEVEL);
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN);
+        mcSHOW_DBG_MSG4(("Enable CLRPLL (0x%x 0x%x)\n", pingpong_shu_level, u2SramLevel));
+    }
+    else
+    {
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN);
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, pingpong_shu_level, LPIF_LOW_POWER_CFG_1_DR_SHU_LEVEL);
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN);
+        mcSHOW_DBG_MSG4(("Enable PHYPLL (0x%x 0x%x)\n", pingpong_shu_level, u2SramLevel));
+    }
+    mcDELAY_US(1);
+
+#if ENABLE_DFS_RUNTIME_MRW
+    DFSRuntimeMRWEn(p, p->u1PLLMode, shu_level);
+#endif
+
+#if 0 //Darren test+
+    vIO32WriteFldAlign(SPM_SPM_POWER_ON_VAL0, 0, SPM_POWER_ON_VAL0_SC_DR_SHU_LEVEL);
+    vIO32WriteFldAlign(SPM_SPM_POWER_ON_VAL0, shu_level, SPM_POWER_ON_VAL0_SC_DR_SHU_LEVEL);
+#else
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u2SramLevel, LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL);
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1EnDPMCh, LPIF_LOW_POWER_CFG_1_DR_SRAM_LOAD);
+
+if (channel_num_auxadc <= 2) {
+    while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SRAM_LOAD_ACK) & u1ShuAck) != u1ShuAck)
+    {
+        mcSHOW_DBG_MSG4(("\twait sram load ack.\n"));
+    }
+    }
+else {
+    while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SRAM_LOAD_ACK) & u1ShuAck) != u1ShuAck
+//#if CHANNEL_NUM > 2
+	    || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SRAM_LOAD_ACK) & u1ShuAck) != u1ShuAck)
+//#endif
+    {
+        mcSHOW_DBG_MSG4(("\twait sram load ack.\n"));
+    }
+    }
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DR_SRAM_LOAD);
+#endif
+
+    //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x2, MISC_STBCAL2_STB_DBG_STATUS);
+
+#if ENABLE_DFS_SSC_WA
+    DVS_DMY_RD_ENTR(p);
+#endif
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW);
+    else
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW);
+
+#if ENABLE_DFS_SSC_WA
+    DramcSSCHoppingOnOff(p, shu_level, ENABLE);
+#endif
+
+#if ENABLE_DFS_RUNTIME_MRW
+    DFSRTMRW_HwsetWA(p, p->u1PLLMode, !p->u1PLLMode, u1ChNum_dpm);
+#else
+    DFSHwSetWA(p, p->u1PLLMode, shu_level, u1ChNum_dpm);
+#endif
+
+    #if ENABLE_DFS_DEBUG_MODE
+    EntryDFSDebugMode(p, CHG_CLK_MODE);
+    #endif
+
+    EnableDramcTrackingByShuffle(p, u1EnDPMCh, DISABLE);
+
+#if ENABLE_DDR800_SOPEN_DSC_WA
+    DDR800_SOPEN_DSC_WA(p, shu_level, DISABLE);
+#endif
+
+    mcDELAY_US(20);
+
+    /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
+
+    /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
+
+    //func_imp_tracking_value_backup();
+    //func_imp_tracking_off();
+    //func_force_mm_ultra();
+
+#if ENABLE_DFS_SSC_WA
+    DVS_DMY_RD_EXIT(p);
+    //DramcSSCHoppingOnOff(p, cur_shu_level, ENABLE); // for waveform measure
+    //mcDELAY_US(10); // for waveform measure
+#endif
+
+#if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION
+    DDR800semiPowerSavingOn(p, shu_level, DISABLE);
+#endif
+
+#if (ENABLE_TX_TRACKING && TX_RETRY_ENABLE)
+    SPMTx_Track_Retry_OnOff(p, shu_level, ENABLE);
+#endif
+
+    mcSHOW_DBG_MSG4(("SHUFFLE Start\n"));
+    //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x3, MISC_STBCAL2_STB_DBG_STATUS);
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_DR_SHU_EN);
+
+    #if ENABLE_DFS_DEBUG_MODE
+    ChkDFSDebugMode(p, CHG_CLK_MODE);
+    // Add WA at here
+    ExitDFSDebugMode(p, CHG_CLK_MODE);
+    #endif
+
+if (channel_num_auxadc <= 2) {
+    while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck)
+	{
+		mcSHOW_DBG_MSG4(("\twait shu_en ack.\n"));
+	}
+    }
+else {
+    while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck
+//#if CHANNEL_NUM > 2
+	    || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck)
+//#endif
+    {
+        mcSHOW_DBG_MSG4(("\twait shu_en ack.\n"));
+    }
+    }
+#if DFS_NOQUEUE_FLUSH_LATENCY_CNT
+    U8 MaxCnt = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_RESERVED_6, LPIF_RESERVED_6_MAX_CNT_SHU_EN_HIGH_TO_ACK); // show chx max cnt
+    // cnt * 8 * 4.8ns (208M)
+    mcSHOW_DBG_MSG2(("\tMAX CNT = %d\n", MaxCnt));
+#endif
+
+#if ENABLE_TX_REBASE_WDQS_DQS_PI_WA
+    TxReBaseWDQSDqsPiWA(p, !p->u1PLLMode);
+#endif
+
+#if ENABLE_TX_REBASE_ODT_WA
+    TxReadBaseODTWA(p, shu_level);
+#endif
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DR_SHU_EN);
+    //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x4, MISC_STBCAL2_STB_DBG_STATUS);
+    mcSHOW_DBG_MSG4(("SHUFFLE End\n"));
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW); // PHYPLL off
+    else
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW); // CLRPLL off
+
+#if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION
+    DDR800semiPowerSavingOn(p, shu_level, ENABLE);
+#endif
+
+#if (ENABLE_TX_TRACKING && TX_RETRY_ENABLE)
+    SPMTx_Track_Retry_OnOff(p, shu_level, DISABLE);
+#endif
+
+#if ENABLE_DFS_SSC_WA
+    DramcSSCHoppingOnOff(p, shu_level, DISABLE);
+#endif
+
+#if ENABLE_DDR800_SOPEN_DSC_WA
+    DDR800_SOPEN_DSC_WA(p, shu_level, ENABLE);
+#endif
+
+    //func_imp_tracking_on();
+#if 1 //Darren test+
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, u1EnDPMCh, LPIF_LOW_POWER_CFG_2_DR_SRAM_RESTORE);
+
+if (channel_num_auxadc <= 2) {
+    while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SRAM_RESTORE_ACK) & u1ShuAck) != u1ShuAck)
+	{
+        mcSHOW_DBG_MSG4(("\twait sram restore ack.\n"));
+    }
+	}
+else {
+    while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SRAM_RESTORE_ACK) & u1ShuAck) != u1ShuAck
+//#if CHANNEL_NUM > 2
+	    || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SRAM_RESTORE_ACK) & u1ShuAck) != u1ShuAck)
+//#endif
+    {
+        mcSHOW_DBG_MSG4(("\twait sram restore ack.\n"));
+    }
+	}
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, 0, LPIF_LOW_POWER_CFG_2_DR_SRAM_RESTORE);
+#endif
+
+    /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
+    EnableDramcTrackingByShuffle(p, u1EnDPMCh, ENABLE);
+
+    //-----------------------------------
+    //     TRIGGER DRAM GATING ERROR
+    //-----------------------------------
+    //func_dram_dummy_read_on();
+    //mcDELAY_US(2);
+    //func_dram_dummy_read_off();
+
+    p->u1PLLMode = !p->u1PLLMode;
+
+    //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x5, MISC_STBCAL2_STB_DBG_STATUS);
+    mcSHOW_DBG_MSG4(("Shuffle flow complete\n"));
+
+    return;
+}
+
+void DramcDFSDirectJump_SPMMode_forK(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_level)
+{
+    U8 u1ShuAck = 0, u1EnDPMCh = 0;
+    U8 u1ChIdx = 0;
+    U8 u1ChNum_dpm = (p->support_channel_num==CHANNEL_SINGLE)?0x1:0x2;
+    U8 u1dpm_shu_level = 0; // for Conf0/1
+
+    for (u1ChIdx = 0; u1ChIdx < u1ChNum_dpm; u1ChIdx++)
+    {
+        u1ShuAck |= (0x1 << u1ChIdx);
+        u1EnDPMCh |= (0x1 << u1ChIdx);
+    }
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+    {
+        mcSHOW_DBG_MSG4(("DramcDFSDirectJump_SPMMode_forK to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
+    }
+    else
+    {
+        mcSHOW_DBG_MSG4(("DramcDFSDirectJump_SPMMode_forK to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
+    }
+
+    //LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL[1:0] for CHA
+    //LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL[3:2] for CHB
+    mcSHOW_DBG_MSG4(("Direct jump to CONF%d\n", shu_level));
+    for (u1ChIdx = 0; u1ChIdx < u1ChNum_dpm; u1ChIdx++)
+    {
+        u1dpm_shu_level |= (shu_level<< (u1ChIdx*2));
+    }
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+    {
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN);
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1dpm_shu_level, LPIF_LOW_POWER_CFG_1_DR_SHU_LEVEL);
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN);
+        mcSHOW_DBG_MSG4(("Enable CLRPLL\n"));
+    }
+    else
+    {
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN);
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1dpm_shu_level, LPIF_LOW_POWER_CFG_1_DR_SHU_LEVEL);
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN);
+        mcSHOW_DBG_MSG4(("Enable PHYPLL\n"));
+    }
+    mcDELAY_US(1);
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW);
+    else
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW);
+
+    mcDELAY_US(20);
+
+    /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
+
+    /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
+
+
+    mcSHOW_DBG_MSG4(("SHUFFLE Start\n"));
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_DR_SHU_EN);
+
+if (channel_num_auxadc <= 2) {
+    while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck)
+    {
+        mcSHOW_DBG_MSG4(("\twait shu_en ack.\n"));
+    }
+    }
+else {
+    while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck
+//#if CHANNEL_NUM > 2
+	    || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck)
+//#endif
+    {
+        mcSHOW_DBG_MSG4(("\twait shu_en ack.\n"));
+    }
+	}
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DR_SHU_EN);
+    mcSHOW_DBG_MSG4(("SHUFFLE End\n"));
+
+    if (p->u1PLLMode == PHYPLL_MODE)
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW); // PHYPLL off
+    else
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW); // CLRPLL off
+
+    /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
+
+    p->u1PLLMode = !p->u1PLLMode;
+
+    mcSHOW_DBG_MSG4(("Shuffle flow complete\n"));
+
+    return;
+}
+
+void DramcDFSDirectJump(DRAMC_CTX_T *p, U8 shu_level)
+{
+#if (DRAMC_DFS_MODE == 2)
+    gDVFSCtrlSel = 2; // SRAM RG mode
+#elif (DRAMC_DFS_MODE == 1)
+    gDVFSCtrlSel = 1; // DPM mode
+#elif (DRAMC_DFS_MODE == 0)
+    gDVFSCtrlSel = 0; // Legacy mode
+#endif
+
+    if (gDVFSCtrlSel == 0)
+    {
+        if (shu_level == SRAM_SHU0) // DDR4266
+            DramcDFSDirectJump_RGMode(p, 0); // Legacy mode for CONF0
+        else
+            DramcDFSDirectJump_RGMode(p, 1); // Legacy mode for CONF1
+    }
+    else if (gDVFSCtrlSel == 1)
+    {
+        DramcDFSDirectJump_SPMMode(p, shu_level);
+    }
+    else
+    {
+        DramcDFSDirectJump_SRAMShuRGMode(p, shu_level);
+    }
+}
+#if 0
+static void No_Parking_On_CLRPLL(DRAMC_CTX_T *p)
+{
+    if (p->u1PLLMode == PHYPLL_MODE) return; /* already parking on PHYPLL */
+
+    DramcDFSDirectJump_RGMode(p, DRAM_DFS_REG_SHU0); /* parking on PHYPLL */
+}
+#endif
+void ShuffleDfsToOriginalFSP(DRAMC_CTX_T *p)
+{
+    U8 operating_fsp = p->dram_fsp;
+    U8 u1RankIdx, backup_rank= u1GetRank(p);
+
+    // Support single rank and dual ranks
+    // Double confirm from CLRPLL to PHYPLL
+    if (operating_fsp == FSP_1)
+    {
+        cbt_dfs_mr13_global(p, CBT_HIGH_FREQ);
+        cbt_switch_freq(p, CBT_HIGH_FREQ);
+    }
+    else
+    {
+        for(u1RankIdx =0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+        {
+            vSetRank(p, u1RankIdx);
+            DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, TO_MR);
+        }
+        vSetRank(p, backup_rank);
+    }
+}
+
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_lowpower.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_lowpower.c
new file mode 100644
index 000000000000..5a42d7ac2b64
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_lowpower.c
@@ -0,0 +1,1105 @@
+/*----------------------------------------------------------------------------*
+ * Copyright Statement:                                                       *
+ *                                                                            *
+ *   This software/firmware and related documentation ("MediaTek Software")   *
+ * are protected under international and related jurisdictions'copyright laws *
+ * as unpublished works. The information contained herein is confidential and *
+ * proprietary to MediaTek Inc. Without the prior written permission of       *
+ * MediaTek Inc., any reproduction, modification, use or disclosure of        *
+ * MediaTek Software, and information contained herein, in whole or in part,  *
+ * shall be strictly prohibited.                                              *
+ * MediaTek Inc. Copyright (C) 2010. All rights reserved.                     *
+ *                                                                            *
+ *   BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND     *
+ * AGREES TO THE FOLLOWING:                                                   *
+ *                                                                            *
+ *   1)Any and all intellectual property rights (including without            *
+ * limitation, patent, copyright, and trade secrets) in and to this           *
+ * Software/firmware and related documentation ("MediaTek Software") shall    *
+ * remain the exclusive property of MediaTek Inc. Any and all intellectual    *
+ * property rights (including without limitation, patent, copyright, and      *
+ * trade secrets) in and to any modifications and derivatives to MediaTek     *
+ * Software, whoever made, shall also remain the exclusive property of        *
+ * MediaTek Inc.  Nothing herein shall be construed as any transfer of any    *
+ * title to any intellectual property right in MediaTek Software to Receiver. *
+ *                                                                            *
+ *   2)This MediaTek Software Receiver received from MediaTek Inc. and/or its *
+ * representatives is provided to Receiver on an "AS IS" basis only.          *
+ * MediaTek Inc. expressly disclaims all warranties, expressed or implied,    *
+ * including but not limited to any implied warranties of merchantability,    *
+ * non-infringement and fitness for a particular purpose and any warranties   *
+ * arising out of course of performance, course of dealing or usage of trade. *
+ * MediaTek Inc. does not provide any warranty whatsoever with respect to the *
+ * software of any third party which may be used by, incorporated in, or      *
+ * supplied with the MediaTek Software, and Receiver agrees to look only to   *
+ * such third parties for any warranty claim relating thereto.  Receiver      *
+ * expressly acknowledges that it is Receiver's sole responsibility to obtain *
+ * from any third party all proper licenses contained in or delivered with    *
+ * MediaTek Software.  MediaTek is not responsible for any MediaTek Software  *
+ * releases made to Receiver's specifications or to conform to a particular   *
+ * standard or open forum.                                                    *
+ *                                                                            *
+ *   3)Receiver further acknowledge that Receiver may, either presently       *
+ * and/or in the future, instruct MediaTek Inc. to assist it in the           *
+ * development and the implementation, in accordance with Receiver's designs, *
+ * of certain softwares relating to Receiver's product(s) (the "Services").   *
+ * Except as may be otherwise agreed to in writing, no warranties of any      *
+ * kind, whether express or implied, are given by MediaTek Inc. with respect  *
+ * to the Services provided, and the Services are provided on an "AS IS"      *
+ * basis. Receiver further acknowledges that the Services may contain errors  *
+ * that testing is important and it is solely responsible for fully testing   *
+ * the Services and/or derivatives thereof before they are used, sublicensed  *
+ * or distributed. Should there be any third party action brought against     *
+ * MediaTek Inc. arising out of or relating to the Services, Receiver agree   *
+ * to fully indemnify and hold MediaTek Inc. harmless.  If the parties        *
+ * mutually agree to enter into or continue a business relationship or other  *
+ * arrangement, the terms and conditions set forth herein shall remain        *
+ * effective and, unless explicitly stated otherwise, shall prevail in the    *
+ * event of a conflict in the terms in any agreements entered into between    *
+ * the parties.                                                               *
+ *                                                                            *
+ *   4)Receiver's sole and exclusive remedy and MediaTek Inc.'s entire and    *
+ * cumulative liability with respect to MediaTek Software released hereunder  *
+ * will be, at MediaTek Inc.'s sole discretion, to replace or revise the      *
+ * MediaTek Software at issue.                                                *
+ *                                                                            *
+ *   5)The transaction contemplated hereunder shall be construed in           *
+ * accordance with the laws of Singapore, excluding its conflict of laws      *
+ * principles.  Any disputes, controversies or claims arising thereof and     *
+ * related thereto shall be settled via arbitration in Singapore, under the   *
+ * then current rules of the International Chamber of Commerce (ICC).  The    *
+ * arbitration shall be conducted in English. The awards of the arbitration   *
+ * shall be final and binding upon both parties and shall be entered and      *
+ * enforceable in any court of competent jurisdiction.                        *
+ *---------------------------------------------------------------------------*/
+
+//-----------------------------------------------------------------------------
+// Include files
+//-----------------------------------------------------------------------------
+#include "dramc_common.h"
+#include "dramc_int_global.h"
+#include "x_hal_io.h"
+//-----------------------------------------------------------------------------
+// Global variables
+//-----------------------------------------------------------------------------
+U8 gDRSEnableSelfWakeup = 0;
+
+//----------------------------------------
+// Auto Gen Code -- START
+//----------------------------------------
+#if (CHECK_GOLDEN_SETTING == TRUE)
+typedef struct _GOLDEN_FIELD_T
+{
+    char fieldName[64]; //field name
+    U32 group;
+    U32 field;
+    U32 u4ChaValue;
+} GOLDEN_FIELD_T;
+GOLDEN_FIELD_T *golden_setting_anwer;
+
+#if APPLY_LOWPOWER_GOLDEN_SETTINGS
+// DCM On
+GOLDEN_FIELD_T shuf_golden_setting_anwer[] =
+{
+    {"SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0},
+    {"SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, 0x0},
+    {"MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL", DDRPHY_REG_MISC_SHU_CG_CTRL0, MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL, 0x334f3000},
+    {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0},
+    {"SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1},
+    {"SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0},
+    {"SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, 0x0},
+    {"SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0},
+    {"SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, 0x0},
+    {"SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW", DDRPHY_REG_SHU_CA_CMD7, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 0x0},
+    {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0},
+    {"SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0},
+    {"SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0},
+    {"SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0},
+    {"SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0},
+    {"SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, 0x0},
+    {"SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0},
+    {"SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0},
+    {"SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, 0x0},
+    {"SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0},
+    {"SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1},
+    {"SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0},
+    {"SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0},
+    {"SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, 0x0},
+    {"SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, 0x0},
+    {"SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1},
+    {"SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW", DDRPHY_REG_SHU_CA_CMD7, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 0x0},
+    {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0},
+    {"SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0},
+    {"SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0},
+    {"SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA", DDRPHY_REG_SHU_CA_CMD13, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA, 0x0},
+    {"SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0},
+    {"SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0},
+    {"SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0},
+    {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0},
+    {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0},
+    {"SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT", DRAMC_REG_SHU_APHY_TX_PICG_CTRL, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1},
+    {"SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0},
+    {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0},
+    {"SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1},
+};
+
+GOLDEN_FIELD_T nonshuf_golden_setting_anwer[] =
+{
+    {"SCSMCTRL_CG_SCARB_SM_CGAR", DRAMC_REG_SCSMCTRL_CG, SCSMCTRL_CG_SCARB_SM_CGAR, 0x0},
+    {"MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, 0x1},
+    {"MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, 0x0},
+    {"MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT, 0x0},
+    {"DUMMY_RD_DUMMY_RD_PA_OPT", DRAMC_REG_DUMMY_RD, DUMMY_RD_DUMMY_RD_PA_OPT, 0x1},
+    {"DVFS_CTRL0_DVFS_CG_OPT", DRAMC_REG_DVFS_CTRL0, DVFS_CTRL0_DVFS_CG_OPT, 0x0},
+    {"MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, 0x0},
+    {"MISC_CTRL3_ARPI_CG_MCTL_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCTL_CA_OPT, 0x0},
+    {"MISC_CTRL4_R_OPT2_CG_DQSIEN", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQSIEN, 0x1},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_FSEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FSEL, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, 0x0},
+    {"RX_CG_SET0_RDATCKAR", DRAMC_REG_RX_CG_SET0, RX_CG_SET0_RDATCKAR, 0x0},
+    {"MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, 0x0},
+    {"MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE, 0x0},
+    {"RX_CG_SET0_RDYCKAR", DRAMC_REG_RX_CG_SET0, RX_CG_SET0_RDYCKAR, 0x0},
+    {"DDRCOMMON0_DISSTOP26M", DRAMC_REG_DDRCOMMON0, DDRCOMMON0_DISSTOP26M, 0x0},
+    {"MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS", DRAMC_REG_MISCTL0, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 0x0},
+    {"DCM_CTRL0_BCLKAR", DRAMC_REG_DCM_CTRL0, DCM_CTRL0_BCLKAR, 0x0},
+    {"DRAMC_PD_CTRL_DCMEN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMEN, 0x1},
+    {"MISC_CG_CTRL5_R_CA_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_CA_DLY_DCM_EN, 0x1},
+    {"CLKAR_REQQUECLKRUN", DRAMC_REG_CLKAR, CLKAR_REQQUECLKRUN, 0x0},
+    {"CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT", DDRPHY_REG_CA_DLL_ARPI1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 0x0},
+    {"DRAMC_PD_CTRL_DCMENNOTRFC", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMENNOTRFC, 0x1},
+    {"MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN", DDRPHY_REG_MISC_DUTYSCAN1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 0x0},
+    {"TX_TRACKING_SET0_HMRRSEL_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_HMRRSEL_CGAR, 0x0},
+    {"ACTIMING_CTRL_SEQCLKRUN", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN, 0x0},
+    {"MISC_CTRL3_ARPI_CG_CLK_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_CLK_OPT, 0x0},
+    {"CMD_DEC_CTRL0_SELPH_CMD_CG_DIS", DRAMC_REG_CMD_DEC_CTRL0, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS, 0x0},
+    {"MISC_CTRL4_R_OPT2_CG_DQS", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQS, 0x1},
+    {"TX_TRACKING_SET0_RDDQSOSC_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_RDDQSOSC_CGAR, 0x0},
+    {"MISC_CTRL4_R_OPT2_CG_CMD", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CMD, 0x1},
+    {"DRAMC_PD_CTRL_PHYCLKDYNGEN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_PHYCLKDYNGEN, 0x1},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN, 0x1},
+    {"MISC_CTRL3_ARPI_CG_MCK_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCK_CA_OPT, 0x0},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE, 0x1},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0x0},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF, 0x0},
+    {"DRAMC_PD_CTRL_COMBPHY_CLKENSAME", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_COMBPHY_CLKENSAME, 0x0},
+    {"MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE, 0x0},
+    {"MISC_CTRL3_ARPI_CG_CMD_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_CMD_OPT, 0x0},
+    {"MISC_CTRL4_R_OPT2_CG_DQ", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQ, 0x1},
+    {"MISC_CTRL3_ARPI_CG_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_DQ_OPT, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, 0x0},
+    {"DRAMC_PD_CTRL_COMBCLKCTRL", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_COMBCLKCTRL, 0x1},
+    {"MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, 0x1},
+    {"MISC_CG_CTRL5_R_CA_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_CA_PI_DCM_EN, 0x1},
+    {"MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, 0x0},
+    {"MISC_CTRL3_ARPI_CG_DQS_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_DQS_OPT, 0x0},
+    {"TX_CG_SET0_TX_ATK_CLKRUN", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_TX_ATK_CLKRUN, 0x0},
+    {"ZQ_SET0_ZQCS_MASK_SEL_CGAR", DRAMC_REG_ZQ_SET0, ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0x0},
+    {"DRAMC_PD_CTRL_APHYCKCG_FIXOFF", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 0x0},
+    {"MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30, 0x0},
+    {"MISC_CTRL4_R_OPT2_CG_CS", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CS, 0x1},
+    {"MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE, 0x0},
+    {"MISC_CTRL3_R_DDRPHY_COMB_CG_IG", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_R_DDRPHY_COMB_CG_IG, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF, 0x0},
+    {"DRAMC_PD_CTRL_DCMEN2", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMEN2, 0x1},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN, 0x1},
+    {"MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, 0x0},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT, 0x5},
+    {"SCSMCTRL_CG_SCSM_CGAR", DRAMC_REG_SCSMCTRL_CG, SCSMCTRL_CG_SCSM_CGAR, 0x0},
+    {"DRAMC_PD_CTRL_MIOCKCTRLOFF", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_MIOCKCTRLOFF, 0x0},
+    {"MISC_CTRL4_R_OPT2_CG_CLK", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CLK, 0x1},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, 0x0},
+    {"ACTIMING_CTRL_SEQCLKRUN3", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN3, 0x1},
+    {"ACTIMING_CTRL_SEQCLKRUN2", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN2, 0x0},
+    {"MISC_CG_CTRL5_R_DQ0_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, 0x1},
+    {"MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN", DDRPHY_REG_MISC_RX_AUTOK_CFG0, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 0x0},
+    {"MISC_CTRL3_ARPI_CG_MCK_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, 0x0},
+    {"MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, 0x0},
+    {"TX_CG_SET0_DWCLKRUN", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_DWCLKRUN, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE, 0x1},
+    {"SREF_DPD_CTRL_SREF_CG_OPT", DRAMC_REG_SREF_DPD_CTRL, SREF_DPD_CTRL_SREF_CG_OPT, 0x0},
+    {"TX_TRACKING_SET0_TXUIPI_CAL_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 0x0},
+    {"MISC_CTRL4_R_OPT2_MPDIV_CG", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_MPDIV_CG, 0x1},
+    {"TX_CG_SET0_WDATA_CG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_WDATA_CG_DIS, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, 0x0},
+    {"MISC_CTRL4_R_OPT2_CG_MCK", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_MCK, 0x1},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 0x3},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 0x17},
+    {"TX_CG_SET0_SELPH_CG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_SELPH_CG_DIS, 0x0},
+    {"DRAMC_PD_CTRL_PHYGLUECLKRUN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_PHYGLUECLKRUN, 0x0},
+    {"MISC_CG_CTRL5_R_DQ1_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, 0x1},
+    {"CLKAR_REQQUE_PACG_DIS", DRAMC_REG_CLKAR, CLKAR_REQQUE_PACG_DIS, 0x0},
+    {"ZQ_SET0_ZQMASK_CGAR", DRAMC_REG_ZQ_SET0, ZQ_SET0_ZQMASK_CGAR, 0x0},
+    {"MISC_CTRL4_R_OPT2_CG_DQM", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQM, 0x1},
+};
+
+#else
+// DCM Off
+GOLDEN_FIELD_T shuf_golden_setting_anwer[] =
+{
+    {"SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x1},
+    {"SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, 0x1},
+    {"MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL", DDRPHY_REG_MISC_SHU_CG_CTRL0, MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL, 0x11400000},
+    {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0},
+    {"SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1},
+    {"SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x1},
+    {"SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, 0x1},
+    {"SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x1},
+    {"SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, 0x1},
+    {"SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW", DDRPHY_REG_SHU_CA_CMD7, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 0x0},
+    {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0},
+    {"SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x1},
+    {"SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x1},
+    {"SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x1},
+    {"SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x1},
+    {"SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, 0x1},
+    {"SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x1},
+    {"SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x1},
+    {"SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, 0x1},
+    {"SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x1},
+    {"SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1},
+    {"SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x1},
+    {"SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x1},
+    {"SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, 0x1},
+    {"SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, 0x1},
+    {"SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1},
+    {"SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW", DDRPHY_REG_SHU_CA_CMD7, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 0x0},
+    {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0},
+    {"SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x1},
+    {"SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x1},
+    {"SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA", DDRPHY_REG_SHU_CA_CMD13, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA, 0x0},
+    {"SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x1},
+    {"SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x1},
+    {"SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x1},
+    {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0},
+    {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0},
+    {"SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT", DRAMC_REG_SHU_APHY_TX_PICG_CTRL, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x0},
+    {"SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x1},
+    {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0},
+    {"SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1},
+};
+
+GOLDEN_FIELD_T nonshuf_golden_setting_anwer[] =
+{
+    {"SCSMCTRL_CG_SCARB_SM_CGAR", DRAMC_REG_SCSMCTRL_CG, SCSMCTRL_CG_SCARB_SM_CGAR, 0x1},
+    {"MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, 0x1},
+    {"MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT, 0x0},
+    {"DUMMY_RD_DUMMY_RD_PA_OPT", DRAMC_REG_DUMMY_RD, DUMMY_RD_DUMMY_RD_PA_OPT, 0x1},
+    {"DVFS_CTRL0_DVFS_CG_OPT", DRAMC_REG_DVFS_CTRL0, DVFS_CTRL0_DVFS_CG_OPT, 0x1},
+    {"MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, 0x0},
+    {"MISC_CTRL3_ARPI_CG_MCTL_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCTL_CA_OPT, 0x0},
+    {"MISC_CTRL4_R_OPT2_CG_DQSIEN", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQSIEN, 0x0},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_FSEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FSEL, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, 0x1},
+    {"RX_CG_SET0_RDATCKAR", DRAMC_REG_RX_CG_SET0, RX_CG_SET0_RDATCKAR, 0x1},
+    {"MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, 0x1},
+    {"MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, 0x1},
+    {"MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG, 0x1},
+    {"MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE, 0x1},
+    {"RX_CG_SET0_RDYCKAR", DRAMC_REG_RX_CG_SET0, RX_CG_SET0_RDYCKAR, 0x1},
+    {"DDRCOMMON0_DISSTOP26M", DRAMC_REG_DDRCOMMON0, DDRCOMMON0_DISSTOP26M, 0x1},
+    {"MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS", DRAMC_REG_MISCTL0, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 0x1},
+    {"DCM_CTRL0_BCLKAR", DRAMC_REG_DCM_CTRL0, DCM_CTRL0_BCLKAR, 0x1},
+    {"DRAMC_PD_CTRL_DCMEN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMEN, 0x0},
+    {"MISC_CG_CTRL5_R_CA_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_CA_DLY_DCM_EN, 0x0},
+    {"CLKAR_REQQUECLKRUN", DRAMC_REG_CLKAR, CLKAR_REQQUECLKRUN, 0x1},
+    {"CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT", DDRPHY_REG_CA_DLL_ARPI1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 0x0},
+    {"DRAMC_PD_CTRL_DCMENNOTRFC", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMENNOTRFC, 0x0},
+    {"MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN", DDRPHY_REG_MISC_DUTYSCAN1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 0x1},
+    {"TX_TRACKING_SET0_HMRRSEL_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_HMRRSEL_CGAR, 0x1},
+    {"ACTIMING_CTRL_SEQCLKRUN", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN, 0x1},
+    {"MISC_CTRL3_ARPI_CG_CLK_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_CLK_OPT, 0x0},
+    {"CMD_DEC_CTRL0_SELPH_CMD_CG_DIS", DRAMC_REG_CMD_DEC_CTRL0, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS, 0x1},
+    {"MISC_CTRL4_R_OPT2_CG_DQS", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQS, 0x0},
+    {"TX_TRACKING_SET0_RDDQSOSC_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_RDDQSOSC_CGAR, 0x1},
+    {"MISC_CTRL4_R_OPT2_CG_CMD", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CMD, 0x0},
+    {"DRAMC_PD_CTRL_PHYCLKDYNGEN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_PHYCLKDYNGEN, 0x0},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN, 0x0},
+    {"MISC_CTRL3_ARPI_CG_MCK_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCK_CA_OPT, 0x0},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE, 0x1},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0x0},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF, 0x0},
+    {"DRAMC_PD_CTRL_COMBPHY_CLKENSAME", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_COMBPHY_CLKENSAME, 0x1},
+    {"MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE, 0x0},
+    {"MISC_CTRL3_ARPI_CG_CMD_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_CMD_OPT, 0x0},
+    {"MISC_CTRL4_R_OPT2_CG_DQ", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQ, 0x0},
+    {"MISC_CTRL3_ARPI_CG_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_DQ_OPT, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, 0x1},
+    {"DRAMC_PD_CTRL_COMBCLKCTRL", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_COMBCLKCTRL, 0x0},
+    {"MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, 0x0},
+    {"MISC_CG_CTRL5_R_CA_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_CA_PI_DCM_EN, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, 0x1},
+    {"MISC_CTRL3_ARPI_CG_DQS_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_DQS_OPT, 0x0},
+    {"TX_CG_SET0_TX_ATK_CLKRUN", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_TX_ATK_CLKRUN, 0x1},
+    {"ZQ_SET0_ZQCS_MASK_SEL_CGAR", DRAMC_REG_ZQ_SET0, ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0x1},
+    {"DRAMC_PD_CTRL_APHYCKCG_FIXOFF", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 0x1},
+    {"MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30, 0x0},
+    {"MISC_CTRL4_R_OPT2_CG_CS", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CS, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE, 0x1},
+    {"MISC_CTRL3_R_DDRPHY_COMB_CG_IG", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_R_DDRPHY_COMB_CG_IG, 0x1},
+    {"MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF, 0x0},
+    {"DRAMC_PD_CTRL_DCMEN2", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMEN2, 0x0},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN, 0x1},
+    {"MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, 0x1},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT, 0x5},
+    {"SCSMCTRL_CG_SCSM_CGAR", DRAMC_REG_SCSMCTRL_CG, SCSMCTRL_CG_SCSM_CGAR, 0x1},
+    {"DRAMC_PD_CTRL_MIOCKCTRLOFF", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_MIOCKCTRLOFF, 0x1},
+    {"MISC_CTRL4_R_OPT2_CG_CLK", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CLK, 0x0},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON, 0x1},
+    {"MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, 0x1},
+    {"ACTIMING_CTRL_SEQCLKRUN3", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN3, 0x1},
+    {"ACTIMING_CTRL_SEQCLKRUN2", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN2, 0x1},
+    {"MISC_CG_CTRL5_R_DQ0_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, 0x0},
+    {"MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN", DDRPHY_REG_MISC_RX_AUTOK_CFG0, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 0x1},
+    {"MISC_CTRL3_ARPI_CG_MCK_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, 0x0},
+    {"MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE, 0x0},
+    {"MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, 0x1},
+    {"TX_CG_SET0_DWCLKRUN", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_DWCLKRUN, 0x1},
+    {"MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE, 0x1},
+    {"SREF_DPD_CTRL_SREF_CG_OPT", DRAMC_REG_SREF_DPD_CTRL, SREF_DPD_CTRL_SREF_CG_OPT, 0x1},
+    {"TX_TRACKING_SET0_TXUIPI_CAL_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 0x1},
+    {"MISC_CTRL4_R_OPT2_MPDIV_CG", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_MPDIV_CG, 0x0},
+    {"TX_CG_SET0_WDATA_CG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_WDATA_CG_DIS, 0x1},
+    {"MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, 0x1},
+    {"MISC_CTRL4_R_OPT2_CG_MCK", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_MCK, 0x0},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 0x3},
+    {"MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 0x17},
+    {"TX_CG_SET0_SELPH_CG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_SELPH_CG_DIS, 0x1},
+    {"DRAMC_PD_CTRL_PHYGLUECLKRUN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_PHYGLUECLKRUN, 0x1},
+    {"MISC_CG_CTRL5_R_DQ1_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, 0x0},
+    {"CLKAR_REQQUE_PACG_DIS", DRAMC_REG_CLKAR, CLKAR_REQQUE_PACG_DIS, 0x7fff},
+    {"ZQ_SET0_ZQMASK_CGAR", DRAMC_REG_ZQ_SET0, ZQ_SET0_ZQMASK_CGAR, 0x1},
+    {"MISC_CTRL4_R_OPT2_CG_DQM", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQM, 0x0},
+};
+
+#endif
+#endif
+
+static void EnableCommonDCMNonShuffle(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldAlign_All(DRAMC_REG_ACTIMING_CTRL, 0x1, ACTIMING_CTRL_SEQCLKRUN3);
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0,
+            P_Fld(0x1, MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE) |
+            P_Fld(0x0, MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN) |
+            P_Fld(0x0, MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF) |
+            P_Fld(0x0, MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF));
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL2,
+            P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE) |
+            P_Fld(0x17, MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL) |
+            P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_FSEL) |
+            P_Fld(0x0, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27) |
+            P_Fld(0x3, MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL) |
+            P_Fld(0x0, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30) |
+            P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF) |
+            P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN) |
+            P_Fld(0x0, MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE) |
+            P_Fld(0x0, MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE) |
+            P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG) |
+            P_Fld(0x5, MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT));
+    // RG group needs to be toggled!!
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
+    vIO32WriteFldAlign_All(DDRPHY_REG_CA_DLL_ARPI1, 0x0, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT);
+    vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DUMMY_RD_PA_OPT);
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL3,
+            P_Fld(0x0, MISC_CTRL3_ARPI_CG_DQS_OPT) |
+            P_Fld(0x0, MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT) |
+            P_Fld(0x0, MISC_CTRL3_ARPI_CG_DQ_OPT) |
+            P_Fld(0x0, MISC_CTRL3_ARPI_CG_MCK_DQ_OPT) |
+            P_Fld(0x0, MISC_CTRL3_ARPI_CG_CMD_OPT) |
+            P_Fld(0x0, MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT) |
+            P_Fld(0x0, MISC_CTRL3_ARPI_CG_MCTL_CA_OPT) |
+            P_Fld(0x0, MISC_CTRL3_ARPI_CG_CLK_OPT) |
+            P_Fld(0x0, MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT) |
+            P_Fld(0x0, MISC_CTRL3_ARPI_CG_MCK_CA_OPT));
+return;
+}
+
+static void EnableCommonDCMShuffle(DRAMC_CTX_T *p)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    if((vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) && (isLP4_DSC))
+    {
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ12, 0x1, SHU_B1_DQ12_DMY_DQ12_B1);  
+    }
+    else
+    {
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ12, 0, SHU_B1_DQ12_DMY_DQ12_B1);  
+    }
+
+    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ8,
+            P_Fld(!isLP4_DSC, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
+            P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1));
+    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD7,
+            P_Fld(0x0, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW) |
+            P_Fld(0x0, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW));
+    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ7,
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) |
+            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1));
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD13, 0x0, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA);
+    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ8,
+            P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) |
+            P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0));
+#if TX_PICG_NEW_MODE  
+    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ7,
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) |
+            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0));
+#endif
+return;
+}
+
+void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+    U8 MPDIV_CG = 1;
+    // Special case
+    EnableCommonDCMNonShuffle(p);
+
+    if(bEn)
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_SREF_DPD_CTRL, 0x0, SREF_DPD_CTRL_SREF_CG_OPT);
+        vIO32WriteFldMulti_All(DRAMC_REG_RX_CG_SET0,
+                P_Fld(0x0, RX_CG_SET0_RDYCKAR) |
+                P_Fld(0x0, RX_CG_SET0_RDATCKAR));
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL2,
+                P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON) |
+                P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN));
+        // RG group needs to be toggled!!
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
+        vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0,
+                P_Fld(0x0, TX_CG_SET0_DWCLKRUN) |
+                P_Fld(0x0, TX_CG_SET0_SELPH_CG_DIS) |
+                P_Fld(0x0, TX_CG_SET0_TX_ATK_CLKRUN) |
+                P_Fld(0x0, TX_CG_SET0_WDATA_CG_DIS));
+        vIO32WriteFldMulti_All(DRAMC_REG_ACTIMING_CTRL,
+                P_Fld(0x0, ACTIMING_CTRL_SEQCLKRUN2) |
+                P_Fld(0x0, ACTIMING_CTRL_SEQCLKRUN));
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0,
+                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE) |
+                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE) |
+                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE) |
+                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE) |
+                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE) |
+                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE) |
+                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE) |
+                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE) |
+                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE) |
+                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE) |
+                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE) |
+                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE));
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DUTYSCAN1, 0x0, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN);
+        vIO32WriteFldAlign_All(DRAMC_REG_DDRCOMMON0, 0x0, DDRCOMMON0_DISSTOP26M);
+        vIO32WriteFldMulti_All(DRAMC_REG_TX_TRACKING_SET0,
+                P_Fld(0x0, TX_TRACKING_SET0_TXUIPI_CAL_CGAR) |
+                P_Fld(0x0, TX_TRACKING_SET0_RDDQSOSC_CGAR) |
+                P_Fld(0x0, TX_TRACKING_SET0_HMRRSEL_CGAR));
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RX_AUTOK_CFG0, 0x0, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN);
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL5,
+                P_Fld(0x1, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN) |
+                P_Fld(0x1, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN) |
+                P_Fld(0x1, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN) |
+                P_Fld(0x1, MISC_CG_CTRL5_R_CA_PI_DCM_EN) |
+                P_Fld(0x1, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN) |
+                P_Fld(0x1, MISC_CG_CTRL5_R_CA_DLY_DCM_EN));
+        vIO32WriteFldMulti_All(DRAMC_REG_ZQ_SET0,
+                P_Fld(0x0, ZQ_SET0_ZQCS_MASK_SEL_CGAR) |
+                P_Fld(0x0, ZQ_SET0_ZQMASK_CGAR));
+        vIO32WriteFldAlign_All(DRAMC_REG_DVFS_CTRL0, 0x0, DVFS_CTRL0_DVFS_CG_OPT);
+        vIO32WriteFldAlign_All(DRAMC_REG_DCM_CTRL0, 0x0, DCM_CTRL0_BCLKAR);
+        vIO32WriteFldMulti_All(DRAMC_REG_SCSMCTRL_CG,
+                P_Fld(0x0, SCSMCTRL_CG_SCARB_SM_CGAR) |
+                P_Fld(0x0, SCSMCTRL_CG_SCSM_CGAR));
+        vIO32WriteFldMulti_All(DRAMC_REG_DRAMC_PD_CTRL,
+                P_Fld(0x1, DRAMC_PD_CTRL_PHYCLKDYNGEN) |
+                P_Fld(0x1, DRAMC_PD_CTRL_DCMEN2) |
+                P_Fld(0x1, DRAMC_PD_CTRL_DCMEN) |
+                P_Fld(0x0, DRAMC_PD_CTRL_PHYGLUECLKRUN) |
+                P_Fld(0x0, DRAMC_PD_CTRL_COMBPHY_CLKENSAME) |
+                P_Fld(0x0, DRAMC_PD_CTRL_APHYCKCG_FIXOFF) |
+                P_Fld(0x0, DRAMC_PD_CTRL_MIOCKCTRLOFF) |
+                P_Fld(0x1, DRAMC_PD_CTRL_DCMENNOTRFC) |
+                P_Fld(0x1, DRAMC_PD_CTRL_COMBCLKCTRL));
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL3,
+                P_Fld(0x0, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG) |
+                P_Fld(0x0, MISC_CTRL3_R_DDRPHY_COMB_CG_IG));
+        vIO32WriteFldAlign_All(DRAMC_REG_CMD_DEC_CTRL0, 0x0, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS);
+        vIO32WriteFldAlign_All(DRAMC_REG_MISCTL0, 0x0, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS);
+#if ENABLE_DDR800_SOPEN_DSC_WA
+        if (isLP4_DSC&&(vGet_DDR_Loop_Mode(p)==SEMI_OPEN_LOOP_MODE))
+            MPDIV_CG = 0;
+#endif
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL4,
+#if (RX_PICG_NEW_MODE || TX_PICG_NEW_MODE)
+                P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_MCK) |
+                P_Fld(MPDIV_CG, MISC_CTRL4_R_OPT2_MPDIV_CG) | //WA for DDR800 DSC DRAM, Need to check in Sim
+#endif
+#if RX_PICG_NEW_MODE     
+                P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQSIEN) |
+#endif
+#if TX_PICG_NEW_MODE   
+                P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQ)  |
+                P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQS) |
+                P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQM) |
+#endif
+                P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_CMD) |
+                P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_CLK) |
+                P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_CS));
+        vIO32WriteFldMulti_All(DRAMC_REG_CLKAR,
+                P_Fld(0x0, CLKAR_REQQUE_PACG_DIS) |
+                P_Fld(0x0, CLKAR_REQQUECLKRUN));
+    }
+    else
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_SREF_DPD_CTRL, 0x1, SREF_DPD_CTRL_SREF_CG_OPT);
+        vIO32WriteFldMulti_All(DRAMC_REG_RX_CG_SET0,
+                P_Fld(0x1, RX_CG_SET0_RDYCKAR) |
+                P_Fld(0x1, RX_CG_SET0_RDATCKAR));
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL2,
+                P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON) |
+                P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN));
+        // RG group needs to be toggled!!
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
+        vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0,
+                P_Fld(0x1, TX_CG_SET0_DWCLKRUN) |
+                P_Fld(0x1, TX_CG_SET0_SELPH_CG_DIS) |
+                P_Fld(0x1, TX_CG_SET0_TX_ATK_CLKRUN) |
+                P_Fld(0x1, TX_CG_SET0_WDATA_CG_DIS));
+        vIO32WriteFldMulti_All(DRAMC_REG_ACTIMING_CTRL,
+                P_Fld(0x1, ACTIMING_CTRL_SEQCLKRUN2) |
+                P_Fld(0x1, ACTIMING_CTRL_SEQCLKRUN));
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0,
+                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE) |
+                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE) |
+                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE) |
+                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE) |
+                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE) |
+                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE) |
+                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE) |
+                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE) |
+                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE) |
+                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE) |
+                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE) |
+                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE));
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DUTYSCAN1, 0x1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN);
+        vIO32WriteFldAlign_All(DRAMC_REG_DDRCOMMON0, 0x1, DDRCOMMON0_DISSTOP26M);
+        vIO32WriteFldMulti_All(DRAMC_REG_TX_TRACKING_SET0,
+                P_Fld(0x1, TX_TRACKING_SET0_TXUIPI_CAL_CGAR) |
+                P_Fld(0x1, TX_TRACKING_SET0_RDDQSOSC_CGAR) |
+                P_Fld(0x1, TX_TRACKING_SET0_HMRRSEL_CGAR));
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RX_AUTOK_CFG0, 0x1, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN);
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL5,
+                P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN) |
+                P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN) |
+                P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN) |
+                P_Fld(0x0, MISC_CG_CTRL5_R_CA_PI_DCM_EN) |
+                P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN) |
+                P_Fld(0x0, MISC_CG_CTRL5_R_CA_DLY_DCM_EN));
+        vIO32WriteFldMulti_All(DRAMC_REG_ZQ_SET0,
+                P_Fld(0x1, ZQ_SET0_ZQCS_MASK_SEL_CGAR) |
+                P_Fld(0x1, ZQ_SET0_ZQMASK_CGAR));
+        vIO32WriteFldAlign_All(DRAMC_REG_DVFS_CTRL0, 0x1, DVFS_CTRL0_DVFS_CG_OPT);
+        vIO32WriteFldAlign_All(DRAMC_REG_DCM_CTRL0, 0x1, DCM_CTRL0_BCLKAR);
+        vIO32WriteFldMulti_All(DRAMC_REG_SCSMCTRL_CG,
+                P_Fld(0x1, SCSMCTRL_CG_SCARB_SM_CGAR) |
+                P_Fld(0x1, SCSMCTRL_CG_SCSM_CGAR));
+        vIO32WriteFldMulti_All(DRAMC_REG_DRAMC_PD_CTRL,
+                P_Fld(0x0, DRAMC_PD_CTRL_PHYCLKDYNGEN) |
+                P_Fld(0x0, DRAMC_PD_CTRL_DCMEN2) |
+                P_Fld(0x0, DRAMC_PD_CTRL_DCMEN) |
+                P_Fld(0x1, DRAMC_PD_CTRL_PHYGLUECLKRUN) |
+                P_Fld(0x1, DRAMC_PD_CTRL_COMBPHY_CLKENSAME) |
+                P_Fld(0x1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF) |
+                P_Fld(0x1, DRAMC_PD_CTRL_MIOCKCTRLOFF) |
+                P_Fld(0x0, DRAMC_PD_CTRL_DCMENNOTRFC) |
+                P_Fld(0x0, DRAMC_PD_CTRL_COMBCLKCTRL));
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL3,
+                P_Fld(0x1, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG) |
+                P_Fld(0x1, MISC_CTRL3_R_DDRPHY_COMB_CG_IG));
+        vIO32WriteFldAlign_All(DRAMC_REG_CMD_DEC_CTRL0, 0x1, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS);
+        vIO32WriteFldAlign_All(DRAMC_REG_MISCTL0, 0x1, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS);
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL4,
+                P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_DQSIEN) |
+                P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_CLK) |
+                P_Fld(0x0, MISC_CTRL4_R_OPT2_MPDIV_CG) |
+                P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_DQM) |
+                P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_CMD) |
+                P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_DQS) |
+                P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_MCK) |
+                P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_CS) |
+                P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_DQ));
+        vIO32WriteFldMulti_All(DRAMC_REG_CLKAR,
+                P_Fld(0x7fff, CLKAR_REQQUE_PACG_DIS) |
+                P_Fld(0x1, CLKAR_REQQUECLKRUN));
+    }
+    return;
+}
+
+void EnableDramcPhyDCMShuffle(DRAMC_CTX_T *p, bool bEn)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+    // Special case
+    // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_READ_START_EXTEND3: Special case
+    // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_READ_START_EXTEND2: Special case
+    // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_READ_START_EXTEND1: Special case
+    // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_DLE_LAST_EXTEND1: Special case
+    // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_DLE_LAST_EXTEND2: Special case
+    // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_DLE_LAST_EXTEND3: Special case
+    EnableCommonDCMShuffle(p);
+
+    if(bEn)
+    {
+#if TX_PICG_NEW_MODE 
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, 0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT);
+#endif
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ8,
+                P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+                P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) |
+                P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+                P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) |
+                P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) |
+                P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+                P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+                P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1) |
+                P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1));
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD8,
+                P_Fld(0x0, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA) |
+                P_Fld(0x0, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA) |
+                P_Fld(0x0, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA) |
+                P_Fld(0x0, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA) |
+                P_Fld(0x0, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA) |
+                P_Fld(0x0, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA) |
+                P_Fld(isLP4_DSC, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA));
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_CG_CTRL0, 0x334f3000, MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL);
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ8,
+                P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) |
+                P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) |
+                P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+                P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+                P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+                P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) |
+                P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+                P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0) |
+                P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0));
+    }
+    else
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, 0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT);
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ8,
+                P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
+                P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) |
+                P_Fld(0x1, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
+                P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) |
+                P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) |
+                P_Fld(0x1, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
+                P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
+                P_Fld(0x1, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1) |
+                P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1));
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD8,
+                P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA) |
+                P_Fld(0x1, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA) |
+                P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA) |
+                P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA) |
+                P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA) |
+                P_Fld(0x1, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA) |
+                P_Fld(0x1, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA));
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_CG_CTRL0, 0x11400000, MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL);
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ8,
+                P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) |
+                P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) |
+                P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
+                P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
+                P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
+                P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) |
+                P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
+                P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0) |
+                P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0));
+    }
+    return;
+}
+
+//----------------------------------------
+// Auto Gen Code -- END
+//----------------------------------------
+
+void EnableDramcPhyDCM(DRAMC_CTX_T *p, bool bEn)
+{
+    U32 u4WbrBackup = GetDramcBroadcast();
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+    EnableDramcPhyDCMNonShuffle(p, bEn);
+    EnableDramcPhyDCMShuffle(p, bEn);//only need to set SHU0 RG while init, SHU0 will copy to others
+
+#if ((CHECK_GOLDEN_SETTING == TRUE) && (APPLY_LOWPOWER_GOLDEN_SETTINGS == 0))
+    DRAM_STATUS_T stResult = CheckGoldenSetting(p);
+    mcSHOW_DBG_MSG3(("Golden setting check: %s\n", (stResult == DRAM_OK)? ("OK") : ("NG")));
+#endif
+
+    DramcBroadcastOnOff(u4WbrBackup);
+    return;
+}
+
+
+#if RX_PICG_NEW_MODE
+#if 0
+DRAM_STATUS_T CheckRxPICGNewModeSetting(DRAMC_CTX_T *p)
+{
+    U8 channel_idx;
+    U8 u1RankIdx;
+    U32 u4Value;
+
+
+    for(channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
+    {
+        p->channel = channel_idx;
+        mcSHOW_DBG_MSG(("CH[%d] \n", channel_idx));        
+        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), MISC_CTRL4_R_OPT2_CG_MCK);
+        mcSHOW_DBG_MSG(("MISC_CTRL4_R_OPT2_CG_MCK:0x%x \n", u4Value));                                
+
+        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), MISC_CTRL4_R_OPT2_MPDIV_CG);
+        mcSHOW_DBG_MSG(("MISC_CTRL4_R_OPT2_MPDIV_CG:0x%x \n", u4Value));                                
+
+        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), MISC_CTRL4_R_OPT2_CG_DQSIEN);
+        mcSHOW_DBG_MSG(("MISC_CTRL4_R_OPT2_CG_DQSIEN:0x%x \n", u4Value));                                
+
+
+        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), MISC_STBCAL1_STBCNT_SHU_RST_EN);
+        mcSHOW_DBG_MSG(("MISC_STBCAL1_STBCNT_SHU_RST_EN:0x%x \n", u4Value));                                
+
+        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN);
+        mcSHOW_DBG_MSG(("MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN:0x%x \n", u4Value));                                
+
+        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), MISC_SHU_STBCAL_DQSIEN_PICG_MODE);
+        mcSHOW_DBG_MSG(("MISC_SHU_STBCAL_DQSIEN_PICG_MODE:0x%x \n", u4Value));                                
+        
+        
+        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT);
+        mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT:0x%x \n", u4Value));                                
+
+        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT);
+        mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT:0x%x \n", u4Value));                                
+
+        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN);
+        mcSHOW_DBG_MSG(("MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN:0x%x \n", u4Value));                                
+
+        for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)//Should set 2 rank
+        {
+            
+            vSetRank(p, u1RankIdx);
+            u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL), MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT);    
+            mcSHOW_DBG_MSG(("Rank[%d] MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT:0x%x \n", u1RankIdx, u4Value));                                
+            u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL), MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT);
+            mcSHOW_DBG_MSG(("Rank[%d] MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT:0x%x \n", u1RankIdx, u4Value));                                
+        }
+        vSetRank(p, RANK_0);        
+
+        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN);
+        mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN:0x%x \n", u4Value));                                
+
+        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN);
+        mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN:0x%x \n", u4Value));                                
+
+        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN);
+        mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN:0x%x \n", u4Value));                                
+        
+        
+        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN);
+        mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN:0x%x \n", u4Value));                                
+
+        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN);
+        mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN:0x%x \n", u4Value));                                
+
+        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN);
+        mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN:0x%x \n", u4Value));                                
+
+    }
+    p->channel = CHANNEL_A;
+}
+#endif
+#endif
+
+#if (CHECK_GOLDEN_SETTING == TRUE)
+static DRAM_STATUS_T CheckGoldenField(DRAMC_CTX_T *p, GOLDEN_FIELD_T *golden_setting_anwer, U16 array_size)
+{
+    DRAM_STATUS_T eStatus = DRAM_OK;
+    U8 channel_idx;
+    U32 u4Value = 0;
+    U32 u4Answer = 0;
+    U16 array_cnt = array_size / sizeof(golden_setting_anwer[0]);
+
+    U16 u2Idx = 0;
+    for(u2Idx = 0; u2Idx < array_cnt; u2Idx++)
+    {
+        for(channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)//comapre CHA && CHB
+        {
+            vSetPHY2ChannelMapping(p, channel_idx);
+            u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(golden_setting_anwer[u2Idx].group), golden_setting_anwer[u2Idx].field);
+            //mcSHOW_DBG_MSG(("%s: 0x%x\n", golden_setting_anwer[u2Idx].fieldName, u4Value));
+        
+            u4Answer = *(&golden_setting_anwer[u2Idx].u4ChaValue);//golden_setting_anwer only has CHA value
+
+            if(u4Answer != 0xffffffff)//0xffffffff: no need to compare
+            {
+                if(u4Answer == u4Value)
+                {
+                    //mcSHOW_DBG_MSG(("OK [%s] 0x%x\n", golden_setting_anwer[u2Idx].fieldName, u4Answer));
+                }
+                else
+                {
+                    mcSHOW_ERR_MSG(("*** fail ***[%s]CH[%d][0x%x][ANS:0x%x]****** fail\n", golden_setting_anwer[u2Idx].fieldName, channel_idx, u4Value, u4Answer));           
+                    eStatus |= DRAM_FAIL;
+                }
+            }
+        }
+    }
+    return eStatus;
+}
+
+DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p)
+{
+    U8 u1BkShuffleIdx = vGet_Current_SRAMIdx(p);
+    U8 u1SramShuffleIdx = 0;
+    U8 u1ShuffleIdx = 0;
+    U8 backup_channel = vGetPHY2ChannelMapping(p);
+    DRAM_STATUS_T eStatus = DRAM_OK;
+
+    mcSHOW_DBG_MSG3(("Golden setting check[Begin]\n"));
+    eStatus |= CheckGoldenField(p, nonshuf_golden_setting_anwer, sizeof(nonshuf_golden_setting_anwer));
+
+
+    if(gAndroid_DVFS_en)
+    {
+        for (u1ShuffleIdx = 0; u1ShuffleIdx <= DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
+        {
+            if (u1ShuffleIdx < DRAM_DFS_SRAM_MAX)
+            {
+                mcSHOW_DBG_MSG3(("SRAM SHU%d\n", u1ShuffleIdx));
+                u1SramShuffleIdx = u1ShuffleIdx;
+            }
+            else
+            {
+                mcSHOW_DBG_MSG3(("CONF SHU0, DDR[%d]\n", p->frequency * 2));
+                u1SramShuffleIdx = u1BkShuffleIdx; //Restore to original freq && check conf SHU0
+            }
+
+            //mcSHOW_DBG_MSG(("shuf_golden_setting_anwer:%d %d\n",  sizeof(shuf_golden_setting_anwer), sizeof(shuf_golden_setting_anwer[0])));
+            DramcDFSDirectJump(p, u1SramShuffleIdx); //fill conf SHU0 && SHU1 from SRAM SHU(0~9) while DVFS twice
+            DramcDFSDirectJump(p, u1SramShuffleIdx);
+
+            eStatus |= CheckGoldenField(p, shuf_golden_setting_anwer, sizeof(shuf_golden_setting_anwer));
+        }
+    }
+    else
+    {
+        mcSHOW_DBG_MSG3(("CONF SHU0, DDR[%d]\n", p->frequency * 2));
+        eStatus |= CheckGoldenField(p, shuf_golden_setting_anwer, sizeof(shuf_golden_setting_anwer));
+    }
+
+    mcSHOW_DBG_MSG3(("Golden setting check[End]\n"));
+
+    vSetPHY2ChannelMapping(p, backup_channel);
+    return eStatus;
+}
+#endif
+
+//#ifdef HW_SAVE_FOR_SR
+void HwSaveForSR(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti_All(DRAMC_REG_SREF_DPD_CTRL, P_Fld(0, SREF_DPD_CTRL_GT_SYNC_MASK)
+                | P_Fld(1, SREF_DPD_CTRL_SELFREF_AUTOSAVE_EN)
+                | P_Fld(1, SREF_DPD_CTRL_SREF2_OPTION)                        
+                | P_Fld(0, SREF_DPD_CTRL_SREF3_OPTION));
+
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 0x0, MISC_DVFSCTL2_GT_SYNC_MASK_FOR_PHY);//PIC: Robert
+}
+//#endif
+
+
+//#ifdef CLK_FREE_FUN_FOR_DRAMC_PSEL
+//If dramc enter SREF and power down, all configure need to sync 2T again after exit SREF.
+//If Psel is 1, clock will be free run at the periof of 2T to let conf be applied. 
+//If Psel is 0, Clock will be gated
+void ClkFreeRunForDramcPsel(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0, P_Fld(0, TX_CG_SET0_PSEL_OPT1)
+            | P_Fld(0, TX_CG_SET0_PSEL_OPT2)
+            | P_Fld(0, TX_CG_SET0_PSEL_OPT3)
+            | P_Fld(0, TX_CG_SET0_PSELAR));
+}
+//#endif
+
+#if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION
+#if 0
+static void EnableDllCg(DRAMC_CTX_T *p, U32 u4OnOff)
+{
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DLL_ARPI2, u4OnOff, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DLL_ARPI2, u4OnOff, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1);
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_DLL_ARPI2 + SHIFT_TO_CHB_ADDR, u4OnOff, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA);
+}
+#endif
+void DDR800semiPowerSavingOn(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff)
+{
+#if __Petrus_TO_BE_PORTING__
+    U8 u1ShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_MISC_DVFSCTL, MISC_DVFSCTL_R_OTHER_SHU_GP);
+    U8 u1IsDdr800Semi = u4IO32ReadFldAlign(DDRPHY_REG_SHU_PLL1 + (SHU_GRP_DDRPHY_OFFSET * u1ShuLevel), SHU_PLL1_RG_RPHYPLL_DDR400_EN);
+
+    if (u1IsDdr800Semi != 1) // close mode will return
+        return;
+
+    if ((next_shu_level != SRAM_SHU9) && (u1OnOff == DISABLE))
+    {
+        // for NORMAL_CLOSE_LOOP
+        EnableDllCg(p, DISABLE);
+    }
+    else if ((next_shu_level == SRAM_SHU9) && (u1OnOff == ENABLE))
+    {
+        // for DDR800_SEMI_LOOP power saving, clock gating
+        EnableDllCg(p, ENABLE);
+    }
+#endif
+}
+#endif
+#if 0 //Comment out unused code
+void DramcDRS(DRAMC_CTX_T *p, U8 bEnable)
+{
+    //R_DMDRS_CNTX[6:0](DVT set 0, HQA set 4 or 5)
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DRSCTRL), P_Fld(0, DRSCTRL_DRSPB2AB_OPT)
+                                                            | P_Fld(0, DRSCTRL_DRSMON_CLR)
+                                                            | P_Fld(8, DRSCTRL_DRSDLY)
+                                                            | P_Fld(0, DRSCTRL_DRSACKWAITREF)
+                                                            | P_Fld(!bEnable, DRSCTRL_DRSDIS)
+                                                            | P_Fld(1, DRSCTRL_DRSCLR_EN)
+                                                            | P_Fld(3, DRSCTRL_DRS_CNTX)
+                                                            | P_Fld(!gDRSEnableSelfWakeup, DRSCTRL_DRS_SELFWAKE_DMYRD_DIS)
+                                                            | P_Fld(0, DRSCTRL_DRSOPT2));
+}
+#endif
+
+#if 0 //Comment out unused code
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+void DramcEnterSelfRefresh(DRAMC_CTX_T *p, U8 op)
+{
+    U8 ucstatus = 0;
+    U32 uiTemp;
+    U32 u4TimeCnt;
+
+    u4TimeCnt = TIME_OUT_CNT;
+
+    mcSHOW_DBG_MSG(("[EnterSelfRefresh] %s\n", ((op == 1) ? "enter" : "exit")));
+
+    if (op == 1) // enter self refresh
+    {
+        // ONLY work for LP4, not LP3
+        // MISCA_SRFPD_DIS =1, self-refresh
+        // MISCA_SRFPD_DIS =0, self-refresh power down
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 1, SREFCTRL_SRFPD_DIS);
+
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 1, SREFCTRL_SELFREF);
+        mcDELAY_US(2);
+        uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
+        while ((uiTemp == 0) && (u4TimeCnt > 0))
+        {
+            mcSHOW_DBG_MSG2(("Still not enter self refresh(%d)\n", u4TimeCnt));
+            mcDELAY_US(1);
+            uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
+            u4TimeCnt --;
+        }
+    }
+    else // exit self refresh
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 0, SREFCTRL_SELFREF);
+
+        mcDELAY_US(2);
+        uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
+        while ((uiTemp != 0) && (u4TimeCnt > 0))
+        {
+            mcSHOW_DBG_MSG2(("Still not exit self refresh(%d)\n", u4TimeCnt));
+            mcDELAY_US(1);
+            uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
+            u4TimeCnt--;
+        }
+    }
+
+   if (u4TimeCnt == 0)
+   {
+        mcSHOW_DBG_MSG(("Self refresh fail\n"));
+   }
+   else
+   {
+        mcSHOW_DBG_MSG(("Self refresh done\n"));
+   }
+}
+#endif
+#endif //Comment out unused code
+
+//#if ENABLE_RX_DCM_DPHY
+void EnableRxDcmDPhy(DRAMC_CTX_T *p, U16 u2Freq)
+{
+    U8 u1PRECAL_CG_EN = 0;
+
+    //open loop mode and semi-open do not enable tracking
+    if (u1IsPhaseMode(p) == TRUE)
+        u1PRECAL_CG_EN = 1;
+    else
+        u1PRECAL_CG_EN = 0;
+
+    //power gain
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL,
+            P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DCM_OPT) |
+            P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT) |
+            P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_RODT_DCM_OPT) |
+            P_Fld(0x0, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_STBCAL_CG_EN) |
+            P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN) |     // if Rx gating Auto K, set 0, Runtime set 1
+            P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN) |
+            P_Fld(u1PRECAL_CG_EN, MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN) |
+            P_Fld(0x2, MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY) |
+            P_Fld(0x0, MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY));
+
+#if RDSEL_TRACKING_EN 
+    if(u2Freq >= RDSEL_TRACKING_TH)
+    {
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, 0x0, MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN);   // if K, set 1, at runtime if enable, set 0, else 1    
+    }
+    else
+    #endif
+    {
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, 0x1, MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN);
+    }
+
+}
+//#endif
+
+//#if CMD_PICG_NEW_MODE 
+void EnableCmdPicgEffImprove(DRAMC_CTX_T *p)
+{
+    U16 u2Clk_Dyn_Gating_Sel = 0x4;
+
+    if (vGet_Div_Mode(p) == DIV4_MODE)
+    {
+        u2Clk_Dyn_Gating_Sel = 0x6;
+    }
+    else //DIV8_MODE, DIV16_MODE
+    {
+        u2Clk_Dyn_Gating_Sel = 0x5;
+    }
+
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | P_Fld(u2Clk_Dyn_Gating_Sel, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL));
+}
+//#endif
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_basic_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_basic_api.c
new file mode 100644
index 000000000000..54b67d8d6363
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_basic_api.c
@@ -0,0 +1,9634 @@
+/*----------------------------------------------------------------------------*
+ * Copyright Statement:                                                       *
+ *                                                                            *
+ *   This software/firmware and related documentation ("MediaTek Software")   *
+ * are protected under international and related jurisdictions'copyright laws *
+ * as unpublished works. The information contained herein is confidential and *
+ * proprietary to MediaTek Inc. Without the prior written permission of       *
+ * MediaTek Inc., any reproduction, modification, use or disclosure of        *
+ * MediaTek Software, and information contained herein, in whole or in part,  *
+ * shall be strictly prohibited.                                              *
+ * MediaTek Inc. Copyright (C) 2010. All rights reserved.                     *
+ *                                                                            *
+ *   BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND     *
+ * AGREES TO THE FOLLOWING:                                                   *
+ *                                                                            *
+ *   1)Any and all intellectual property rights (including without            *
+ * limitation, patent, copyright, and trade secrets) in and to this           *
+ * Software/firmware and related documentation ("MediaTek Software") shall    *
+ * remain the exclusive property of MediaTek Inc. Any and all intellectual    *
+ * property rights (including without limitation, patent, copyright, and      *
+ * trade secrets) in and to any modifications and derivatives to MediaTek     *
+ * Software, whoever made, shall also remain the exclusive property of        *
+ * MediaTek Inc.  Nothing herein shall be construed as any transfer of any    *
+ * title to any intellectual property right in MediaTek Software to Receiver. *
+ *                                                                            *
+ *   2)This MediaTek Software Receiver received from MediaTek Inc. and/or its *
+ * representatives is provided to Receiver on an "AS IS" basis only.          *
+ * MediaTek Inc. expressly disclaims all warranties, expressed or implied,    *
+ * including but not limited to any implied warranties of merchantability,    *
+ * non-infringement and fitness for a particular purpose and any warranties   *
+ * arising out of course of performance, course of dealing or usage of trade. *
+ * MediaTek Inc. does not provide any warranty whatsoever with respect to the *
+ * software of any third party which may be used by, incorporated in, or      *
+ * supplied with the MediaTek Software, and Receiver agrees to look only to   *
+ * such third parties for any warranty claim relating thereto.  Receiver      *
+ * expressly acknowledges that it is Receiver's sole responsibility to obtain *
+ * from any third party all proper licenses contained in or delivered with    *
+ * MediaTek Software.  MediaTek is not responsible for any MediaTek Software  *
+ * releases made to Receiver's specifications or to conform to a particular   *
+ * standard or open forum.                                                    *
+ *                                                                            *
+ *   3)Receiver further acknowledge that Receiver may, either presently       *
+ * and/or in the future, instruct MediaTek Inc. to assist it in the           *
+ * development and the implementation, in accordance with Receiver's designs, *
+ * of certain softwares relating to Receiver's product(s) (the "Services").   *
+ * Except as may be otherwise agreed to in writing, no warranties of any      *
+ * kind, whether express or implied, are given by MediaTek Inc. with respect  *
+ * to the Services provided, and the Services are provided on an "AS IS"      *
+ * basis. Receiver further acknowledges that the Services may contain errors  *
+ * that testing is important and it is solely responsible for fully testing   *
+ * the Services and/or derivatives thereof before they are used, sublicensed  *
+ * or distributed. Should there be any third party action brought against     *
+ * MediaTek Inc. arising out of or relating to the Services, Receiver agree   *
+ * to fully indemnify and hold MediaTek Inc. harmless.  If the parties        *
+ * mutually agree to enter into or continue a business relationship or other  *
+ * arrangement, the terms and conditions set forth herein shall remain        *
+ * effective and, unless explicitly stated otherwise, shall prevail in the    *
+ * event of a conflict in the terms in any agreements entered into between    *
+ * the parties.                                                               *
+ *                                                                            *
+ *   4)Receiver's sole and exclusive remedy and MediaTek Inc.'s entire and    *
+ * cumulative liability with respect to MediaTek Software released hereunder  *
+ * will be, at MediaTek Inc.'s sole discretion, to replace or revise the      *
+ * MediaTek Software at issue.                                                *
+ *                                                                            *
+ *   5)The transaction contemplated hereunder shall be construed in           *
+ * accordance with the laws of Singapore, excluding its conflict of laws      *
+ * principles.  Any disputes, controversies or claims arising thereof and     *
+ * related thereto shall be settled via arbitration in Singapore, under the   *
+ * then current rules of the International Chamber of Commerce (ICC).  The    *
+ * arbitration shall be conducted in English. The awards of the arbitration   *
+ * shall be final and binding upon both parties and shall be entered and      *
+ * enforceable in any court of competent jurisdiction.                        *
+ *---------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------
+ *
+ * $Author: jc.wu $
+ * $Date: 2012/6/5 $
+ * $RCSfile: pi_basic_api.c,v $
+ * $Revision: #5 $
+ *
+ *---------------------------------------------------------------------------*/
+
+/** @file pi_basic_api.c
+ *  Basic DRAMC API implementation
+ */
+
+//-----------------------------------------------------------------------------
+// Include files
+//-----------------------------------------------------------------------------
+//#include "..\Common\pd_common.h"
+//#include "Register.h"
+#include "dramc_common.h"
+#include "dramc_dv_init.h"
+#include "dramc_int_global.h"
+#include "x_hal_io.h"
+#include "dramc_actiming.h"
+#if (FOR_DV_SIMULATION_USED==0)
+#include "dramc_top.h"
+#include "pll.h"
+//extern EMI_SETTINGS g_default_emi_setting;
+#endif
+
+//#include "DramC_reg.h"
+//#include "System_reg.h"
+//#include "string.h"
+
+//-----------------------------------------------------------------------------
+// Global variables
+//-----------------------------------------------------------------------------
+U8 u1PrintModeRegWrite = 0;
+
+#if ENABLE_RODT_TRACKING_SAVE_MCK
+// global variables for RODT tracking & ROEN
+U8 u1ODT_ON;        // infor of p->odt_onoff
+U8 u1WDQS_ON = 0;   // infor of WDQS on(ROEN=1)
+U8 u1RODT_TRACK = 0;  // infor of rodt tracking enable
+U8 u1ROEN, u1ModeSel;//status of ROEN, MODESEL setting
+#endif
+
+//MRR DRAM->DRAMC
+const U8 uiLPDDR4_MRR_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] =
+{
+    {
+        // for EMCP
+        //CH-A
+        {
+            0, 1, 2, 3, 5, 7, 6, 4,
+            9, 8, 13, 15, 10, 14, 11, 12
+        },
+#if (CHANNEL_NUM>1)
+        //CH-B
+        {
+            0, 1, 5, 4, 3, 7, 6, 2,
+            9, 8, 13, 14, 10, 15, 11, 12
+        },
+#endif
+#if (CHANNEL_NUM>2)
+        //CH-C
+        {
+            0, 1, 2, 3, 5, 7, 6, 4,
+            9, 8, 13, 15, 10, 14, 11, 12
+        },
+        //CH-D
+        {
+            0, 1, 5, 4, 3, 7, 6, 2,
+            9, 8, 13, 14, 10, 15, 11, 12
+        },
+#endif
+    },
+    {
+    // for DSC_2CH, HFID RESERVED
+        //CH-A
+        {
+            0, 1, 4, 3, 2, 5, 7, 6,
+            9, 8, 10, 11, 14, 13, 15, 12
+        },
+#if (CHANNEL_NUM>1)
+        //CH-B
+        {
+            0, 1, 2, 4, 5, 3, 7, 6,
+            8, 9, 10, 11, 15, 14, 13, 12
+        },
+#endif
+#if (CHANNEL_NUM>2)
+        //CH-C
+        {
+            0, 1, 2, 3, 4, 5, 6, 7,
+            8, 9, 10, 11, 12, 13, 14, 15
+        },
+        //CH-D
+        {
+            0, 1, 2, 3, 4, 5, 6, 7,
+            8, 9, 10, 11, 12, 13, 14, 15
+        },
+#endif
+    },
+    {
+        // for MCP
+        //CH-A
+        {
+            0, 1, 3, 6, 4, 7, 2, 5,
+            8, 9, 10, 13, 11, 12, 15, 14
+        },
+#if (CHANNEL_NUM>1)
+        //CH-B
+        {
+            0, 1, 4, 7, 3, 5, 6, 2,
+            9, 8, 10, 12, 11, 14, 13, 15
+        },
+#endif
+#if (CHANNEL_NUM>2)
+        //CH-C
+        {
+            1, 0, 3, 2, 4, 7, 6, 5,
+            8, 9, 10, 14, 11, 15, 13, 12
+        },
+        //CH-D
+        {
+            0, 1, 4, 7, 3, 5, 6, 2,
+            9, 8, 10, 12, 11, 14, 13, 15
+        },
+#endif
+    },
+    {
+    // for DSC_180
+        //CH-A
+        {
+            9, 8, 11, 10, 14, 15, 13, 12,
+            0, 1, 7, 6, 4, 5, 2, 3
+        },
+#if (CHANNEL_NUM>1)
+        //CH-B
+        {
+            8, 9, 11, 10, 12, 14, 13, 15,
+            1, 0, 5, 6, 3, 2, 7, 4
+        },
+#endif
+#if (CHANNEL_NUM>2)
+        //CH-C
+        {
+            0, 1, 7, 6, 4, 5, 2, 3,
+            9, 8, 11, 10, 14, 15, 13, 12
+        },
+        //CH-D
+        {
+            1, 0, 5, 6, 3, 2, 7, 4,
+            8, 9, 11, 10, 12, 14, 13, 15
+        },
+#endif
+    },
+};
+
+#if (__LP5_COMBO__)
+const U8 uiLPDDR5_MRR_Mapping_POP[CHANNEL_NUM][16] =
+{
+    {
+        8, 9, 10, 11, 12, 15, 14, 13,
+        0, 1, 2, 3, 4, 7, 6, 5,
+    },
+
+#if (CHANNEL_NUM>1)
+    {
+        8, 9, 10, 11, 12, 15, 14, 13,
+        0, 1, 2, 3, 4, 7, 6, 5,
+    },
+#endif
+};
+#endif
+
+//MRR DRAM->DRAMC
+U8 uiLPDDR4_MRR_Mapping_POP[CHANNEL_NUM][16] =
+{
+    //CH-A
+    {
+		0, 1, 2, 3, 7, 4, 6, 5,
+		9, 8, 12, 14, 15, 10, 13, 11
+    },
+#if (CHANNEL_NUM>1)
+    //CH-B
+    {
+		0, 1, 7, 4, 3, 2, 6, 5,
+		9, 8, 12, 14, 15, 10, 11, 13
+    },
+#endif
+#if (CHANNEL_NUM>2)
+    //CH-C
+    {
+		0, 1, 2, 3, 7, 4, 6, 5,
+		9, 8, 12, 14, 15, 10, 13, 11
+    },
+    //CH-D
+    {
+		0, 1, 7, 4, 3, 2, 6, 5,
+		9, 8, 12, 14, 15, 10, 11, 13
+    },
+#endif
+};
+
+#if (fcFOR_CHIP_ID == fc8195)
+static void Set_DRAM_Pinmux_Sel(DRAMC_CTX_T *p)
+{
+#if (__LP5_COMBO__)
+    if (is_lp5_family(p))
+        return;
+#endif
+
+#if !FOR_DV_SIMULATION_USED
+    if (is_discrete_lpddr4())
+        p->DRAMPinmux = PINMUX_DSC;
+    else
+#endif
+        p->DRAMPinmux = PINMUX_EMCP;
+
+    mcSHOW_DBG_MSG2(("[Set_DRAM_Pinmux_Sel] DRAMPinmux = %d\n", p->DRAMPinmux));
+
+    vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, p->DRAMPinmux, SA_RESERVE_DRM_DSC_DRAM);
+    memcpy(&uiLPDDR4_MRR_Mapping_POP, uiLPDDR4_MRR_DRAM_Pinmux[p->DRAMPinmux], sizeof(uiLPDDR4_MRR_Mapping_POP));
+    memcpy(&uiLPDDR4_O1_Mapping_POP, uiLPDDR4_O1_DRAM_Pinmux[p->DRAMPinmux], sizeof(uiLPDDR4_O1_Mapping_POP));
+    memcpy(&uiLPDDR4_CA_Mapping_POP, uiLPDDR4_CA_DRAM_Pinmux[p->DRAMPinmux], sizeof(uiLPDDR4_CA_Mapping_POP));
+}
+#endif
+
+static void Set_MRR_Pinmux_Mapping(DRAMC_CTX_T *p)
+{
+    U8 *uiLPDDR_MRR_Mapping = NULL;
+    U8 backup_channel;
+    U32 backup_broadcast;
+    DRAM_CHANNEL_T chIdx = CHANNEL_A;
+
+    //Backup channel & broadcast
+    backup_channel = vGetPHY2ChannelMapping(p);
+    backup_broadcast = GetDramcBroadcast();
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); //Disable broadcast
+
+    //LP4: Set each channel's pinmux individually, LP3: Only has 1 channel (support_channel_num == 1)
+    for (chIdx = CHANNEL_A; chIdx < (int)p->support_channel_num; chIdx++)
+    {
+        vSetPHY2ChannelMapping(p, chIdx);
+
+    #if (__LP5_COMBO__)
+        if (is_lp5_family(p))
+            uiLPDDR_MRR_Mapping = (U8 *)uiLPDDR5_MRR_Mapping_POP[chIdx];
+        else
+    #endif
+        uiLPDDR_MRR_Mapping = (U8 *)uiLPDDR4_MRR_Mapping_POP[chIdx];
+
+        //Set MRR pin mux
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX1), P_Fld(uiLPDDR_MRR_Mapping[0], MRR_BIT_MUX1_MRR_BIT0_SEL) | P_Fld(uiLPDDR_MRR_Mapping[1], MRR_BIT_MUX1_MRR_BIT1_SEL) |
+                                                                   P_Fld(uiLPDDR_MRR_Mapping[2], MRR_BIT_MUX1_MRR_BIT2_SEL) | P_Fld(uiLPDDR_MRR_Mapping[3], MRR_BIT_MUX1_MRR_BIT3_SEL));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX2), P_Fld(uiLPDDR_MRR_Mapping[4], MRR_BIT_MUX2_MRR_BIT4_SEL) | P_Fld(uiLPDDR_MRR_Mapping[5], MRR_BIT_MUX2_MRR_BIT5_SEL) |
+                                                                   P_Fld(uiLPDDR_MRR_Mapping[6], MRR_BIT_MUX2_MRR_BIT6_SEL) | P_Fld(uiLPDDR_MRR_Mapping[7], MRR_BIT_MUX2_MRR_BIT7_SEL));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX3), P_Fld(uiLPDDR_MRR_Mapping[8], MRR_BIT_MUX3_MRR_BIT8_SEL) | P_Fld(uiLPDDR_MRR_Mapping[9], MRR_BIT_MUX3_MRR_BIT9_SEL) |
+                                                                   P_Fld(uiLPDDR_MRR_Mapping[10], MRR_BIT_MUX3_MRR_BIT10_SEL) | P_Fld(uiLPDDR_MRR_Mapping[11], MRR_BIT_MUX3_MRR_BIT11_SEL));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX4), P_Fld(uiLPDDR_MRR_Mapping[12], MRR_BIT_MUX4_MRR_BIT12_SEL) | P_Fld(uiLPDDR_MRR_Mapping[13], MRR_BIT_MUX4_MRR_BIT13_SEL) |
+                                                                   P_Fld(uiLPDDR_MRR_Mapping[14], MRR_BIT_MUX4_MRR_BIT14_SEL) | P_Fld(uiLPDDR_MRR_Mapping[15], MRR_BIT_MUX4_MRR_BIT15_SEL));
+    }
+
+    //Recover channel & broadcast
+    vSetPHY2ChannelMapping(p, backup_channel);
+    DramcBroadcastOnOff(backup_broadcast);
+}
+
+
+static void Set_DQO1_Pinmux_Mapping(DRAMC_CTX_T *p)
+{
+    U8 *uiLPDDR_DQO1_Mapping = NULL;
+    U8 backup_channel;
+    U32 backup_broadcast;
+    DRAM_CHANNEL_T chIdx = CHANNEL_A;
+
+    //Backup channel & broadcast
+    backup_channel = vGetPHY2ChannelMapping(p);
+    backup_broadcast = GetDramcBroadcast();
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); //Disable broadcast
+
+    //LP4: Set each channel's pinmux individually, LP3: Only has 1 channel (support_channel_num == 1)
+    for (chIdx = CHANNEL_A; chIdx < (int)p->support_channel_num; chIdx++)
+    {
+        vSetPHY2ChannelMapping(p, chIdx);
+
+    #if (__LP5_COMBO__)
+        if (is_lp5_family(p))
+            uiLPDDR_DQO1_Mapping = (U8 *)uiLPDDR5_O1_Mapping_POP[chIdx];
+        else
+    #endif
+        uiLPDDR_DQO1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[chIdx];
+
+        //Set MRR pin mux
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL0), P_Fld(uiLPDDR_DQO1_Mapping[0], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0)
+                                                                            | P_Fld(uiLPDDR_DQO1_Mapping[1], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1)
+                                                                            | P_Fld(uiLPDDR_DQO1_Mapping[2], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2)
+                                                                            | P_Fld(uiLPDDR_DQO1_Mapping[3], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ3)
+                                                                            | P_Fld(uiLPDDR_DQO1_Mapping[4], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ4)
+                                                                            | P_Fld(uiLPDDR_DQO1_Mapping[5], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ5)
+                                                                            | P_Fld(uiLPDDR_DQO1_Mapping[6], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ6)
+                                                                            | P_Fld(uiLPDDR_DQO1_Mapping[7], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ7));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL1), P_Fld(uiLPDDR_DQO1_Mapping[8], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ8)
+                                                                            | P_Fld(uiLPDDR_DQO1_Mapping[9], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ9)
+                                                                            | P_Fld(uiLPDDR_DQO1_Mapping[10], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ10)
+                                                                            | P_Fld(uiLPDDR_DQO1_Mapping[11], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ11)
+                                                                            | P_Fld(uiLPDDR_DQO1_Mapping[12], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ12)
+                                                                            | P_Fld(uiLPDDR_DQO1_Mapping[13], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ13)
+                                                                            | P_Fld(uiLPDDR_DQO1_Mapping[14], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ14)
+                                                                            | P_Fld(uiLPDDR_DQO1_Mapping[15], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15));
+    }
+
+    //Recover channel & broadcast
+    vSetPHY2ChannelMapping(p, backup_channel);
+    DramcBroadcastOnOff(backup_broadcast);
+}
+
+
+static void SetRankInfoToConf(DRAMC_CTX_T *p)
+{
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+    EMI_SETTINGS *emi_set;
+    U32 u4value = 0;
+
+    emi_set = &g_default_emi_setting;
+
+    u4value = ((emi_set->EMI_CONA_VAL >> 17) & 0x1)? 0: 1;//CONA 17th bit 0: Disable dual rank mode 1: Enable dual rank mode
+
+    vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, u4value, SA_RESERVE_SINGLE_RANK);
+
+    mcSHOW_JV_LOG_MSG(("Rank info: %d, CONA[0x%x]\n", u4value, emi_set->EMI_CONA_VAL));
+#endif
+    return;
+}
+
+static void SetDramInfoToConf(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti_All(DRAMC_REG_SA_RESERVE,
+        P_Fld(p->dram_cbt_mode[RANK_0], SA_RESERVE_MODE_RK0) |
+        P_Fld(p->dram_cbt_mode[RANK_1], SA_RESERVE_MODE_RK1));
+
+    if(u2DFSGetHighestFreq(p) >= 2133)
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_SA_RESERVE, 1, SA_RESERVE_SUPPORT_4266);
+    }
+}
+#if 0
+static void UpdateHighestFreqInDFSTbl(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T new_freq_sel)
+{
+#if(FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
+    U16 u2HighestFreq = u2DFSGetHighestFreq(p);
+    DRAM_PLL_FREQ_SEL_T cur_freq_sel = 0;
+    U8 u1ShuffleIdx = 0;
+
+    // lookup table to find highest freq
+    cur_freq_sel = GetSelByFreq(p, u2HighestFreq);
+    if (cur_freq_sel == new_freq_sel)
+        return;
+
+    for (u1ShuffleIdx = 0; u1ShuffleIdx < DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
+        if (gFreqTbl[u1ShuffleIdx].freq_sel == cur_freq_sel)
+            break;
+
+    gFreqTbl[u1ShuffleIdx].freq_sel = new_freq_sel; // update
+
+    gUpdateHighestFreq = TRUE;
+    u2HighestFreq = u2DFSGetHighestFreq(p); // @Darren, Update u2FreqMax variables
+
+    #if __ETT__
+    UpdateEttDFVSTblHighest(p, cur_freq_sel, new_freq_sel); //@Darren, Update for ETT DVFS stress
+    #endif
+    mcSHOW_DBG_MSG2(("[UpdateHighestFreqInDFSTbl] Get Highest Freq is %d\n", u2HighestFreq));
+#endif
+}
+
+static void UpdateHighestFreqToDDR3733(DRAMC_CTX_T *p)
+{
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+    EMI_SETTINGS *emi_set;
+
+    emi_set = &g_default_emi_setting;
+
+    if (emi_set->highest_freq == 3733) {
+        UpdateHighestFreqInDFSTbl(p, LP4_DDR3733);
+    }
+#endif
+}
+#endif
+#ifdef SCRAMBLE_EN
+#endif
+#if 0
+static void TzCfgScramble(DRAMC_CTX_T *p, U32 u4RandmKey, U32 u4EncryptType)
+{
+    U32 u4ScrambleCFGAddr = DRAMC_REG_SCRAMBLE_CFG0;
+    U32 u4ScrambleCFGRGIdx = 0;
+
+    for(u4ScrambleCFGRGIdx = 0; u4ScrambleCFGRGIdx < 8; u4ScrambleCFGRGIdx++)
+    {
+        u4ScrambleCFGAddr += 4;
+        vIO32Write4B(DRAMC_REG_ADDR(u4ScrambleCFGAddr), u4RandmKey);
+    }
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SCRAMBLE_CFG8), P_Fld(1, SCRAMBLE_CFG8_SC_CMP_EN0) \
+                                                              | P_Fld(0, SCRAMBLE_CFG8_SC_CMP_TYPE0));
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SCRAMBLE_CFG9), 0xFFFF0000);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SCRAMBLE_CFG8), P_Fld(u4EncryptType, SCRAMBLE_CFG8_SC_RETRUN_HUSKY) \
+                                                              | P_Fld(1, SCRAMBLE_CFG8_SC_DDR_TYPE)
+                                                              | P_Fld(1, SCRAMBLE_CFG8_SC_EN));
+}
+#endif
+
+
+#if defined(DEVIATION) && !__ETT__
+#include "deviation.h"
+#define KEY_DEVIATION 0x4073
+static void vInitDeviationVariable(void)
+{
+    DEVIATION_INFO_T* deviation_info_ptr;
+
+    deviation_info_ptr = (DEVIATION_INFO_T *) get_dbg_info_base(KEY_DEVIATION);
+
+    if (deviation_info_ptr->magic == DEVIATION_MAGIC_PATTERN)
+    {
+        if (deviation_info_ptr->ca_enable == ENABLE)
+        {
+            gSetSpecificedVref_Enable[0] = ENABLE;
+
+            /*
+                CH_BA : (0: ch A + rank 0)
+                CH_BA : (1: ch A + rank 1)
+                CH_BA : (2: ch B + rank 0)
+                CH_BA : (3: ch B + rank 1)
+                CH_BA : (4: All Channel and All Rank)
+            */
+            if (deviation_info_ptr->ca_channel_bank == 4)
+            {
+                gSetSpecificedVref_All_ChRk[0] = ENABLE;
+            }
+            else
+            {
+                gSetSpecificedVref_Channel[0] = (deviation_info_ptr->ca_channel_bank >> 1) & 1;
+                gSetSpecificedVref_Rank[0] = deviation_info_ptr->ca_channel_bank & 1;
+            }
+            gSetSpecificedVref_Vref_Offset[0] = deviation_info_ptr->ca_offset;
+        }
+
+        if (deviation_info_ptr->rx_enable == ENABLE)
+        {
+            gSetSpecificedVref_Enable[1] = ENABLE;
+
+            if (deviation_info_ptr->rx_channel_bank == 4)
+            {
+                gSetSpecificedVref_All_ChRk[1] = ENABLE;
+            }
+            else
+            {
+                gSetSpecificedVref_Channel[1] = (deviation_info_ptr->rx_channel_bank >> 1) & 1;
+                gSetSpecificedVref_Rank[1] = deviation_info_ptr->rx_channel_bank & 1;
+            }
+            gSetSpecificedVref_Vref_Offset[1] = deviation_info_ptr->rx_offset;
+        }
+
+        if (deviation_info_ptr->tx_enable == ENABLE)
+        {
+            gSetSpecificedVref_Enable[2] = ENABLE;
+
+            if (deviation_info_ptr->tx_channel_bank == 4)
+            {
+                gSetSpecificedVref_All_ChRk[2] = ENABLE;
+            }
+            else
+            {
+                gSetSpecificedVref_Channel[2] = (deviation_info_ptr->tx_channel_bank >> 1) & 1;
+                gSetSpecificedVref_Rank[2] = deviation_info_ptr->tx_channel_bank & 1;
+            }
+            gSetSpecificedVref_Vref_Offset[2] = deviation_info_ptr->tx_offset;
+        }
+    }
+}
+
+void vSetDeviationVariable(void)
+{
+    DEVIATION_INFO_T* deviation_info_ptr;
+    U8 u1ChannelIdx, u1RankIdx, u1ByteIdx;
+
+    deviation_info_ptr = (DEVIATION_INFO_T *) get_dbg_info_base(KEY_DEVIATION);
+
+    for(u1ChannelIdx=0; u1ChannelIdx<2; u1ChannelIdx++)
+    {
+        for(u1RankIdx=0; u1RankIdx<2; u1RankIdx++)
+        {
+            deviation_info_ptr->dram_k_ca_vref_range[u1ChannelIdx][u1RankIdx] = (u1MR12Value[u1ChannelIdx][u1RankIdx][FSP_1]>>6) & 1;
+            deviation_info_ptr->dram_k_ca_vref_value[u1ChannelIdx][u1RankIdx] = u1MR12Value[u1ChannelIdx][u1RankIdx][FSP_1] & 0x3f;
+
+            deviation_info_ptr->dram_k_tx_vref_range[u1ChannelIdx][u1RankIdx] = (u1MR14Value[u1ChannelIdx][u1RankIdx][FSP_1]>>6)&1;
+            deviation_info_ptr->dram_k_tx_vref_value[u1ChannelIdx][u1RankIdx] = u1MR14Value[u1ChannelIdx][u1RankIdx][FSP_1] & 0x3f;
+
+            for(u1ByteIdx=0; u1ByteIdx<2; u1ByteIdx++)
+            {
+                deviation_info_ptr->dram_k_rx_vref_value[u1ChannelIdx][u1RankIdx][u1ByteIdx] = gFinalRXVrefDQ[u1ChannelIdx][u1RankIdx][u1ByteIdx];
+            }
+        }
+    }
+}
+#endif
+
+void Global_Option_Init(DRAMC_CTX_T *p)
+{
+    //SaveCurrDramCtx(p);
+    vSetChannelNumber(p);
+    SetRankInfoToConf(p);
+    vSetRankNumber(p);
+    vSetFSPNumber(p);
+#if (fcFOR_CHIP_ID == fc8195)
+    Set_DRAM_Pinmux_Sel(p);
+#endif
+    Set_MRR_Pinmux_Mapping(p);
+    Set_DQO1_Pinmux_Mapping(p);
+
+    vInitGlobalVariablesByCondition(p);
+
+#if ENABLE_TX_TRACKING
+    DramcDQSOSCInit();
+#endif
+
+#ifdef FOR_HQA_TEST_USED
+    HQA_measure_message_reset_all_data(p);
+#endif
+
+#if defined(DEVIATION) && !__ETT__
+    vInitDeviationVariable();
+#endif
+}
+
+/* RxDQSIsiPulseCG() - API for "RX DQS ISI pulse CG function" 0: disable, 1: enable
+ * 1. RG_*_RPRE_TOG_EN (16nm APHY): B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0, B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1
+ * 2. RG_RX_*RDQS*_DQSSTB_CG_EN*(10nm APHY): B0_DQ8_RG_RX_ARDQS_DQSSTB_CG_EN_B0, B1_DQ8_RG_RX_ARDQS_DQSSTB_CG_EN_B1
+ * Supports setting current channel only, add function to set "all channels" in the future
+ */
+#if 0
+static void RxDQSIsiPulseCG(DRAMC_CTX_T *p, U8 u1OnOff)
+{
+#if __A60868_TO_BE_PORTING__
+
+    mcSHOW_DBG_MSG4(("CH%u RX DQS ISI pulse CG: %u (0:disable, 1:enable)\n", u1OnOff));
+
+    /* LP4: Disable(set to 0) "RX DQS ISI pulse CG function" during the below senarios (must enable(set to 1) when done)
+     *      1. Gating window calibration
+     *      2. Duty related calibration (Justin: prevents DQSI from being kept high after READ burst)
+     * LP3: should always be set to 1
+     */
+#if (fcFOR_CHIP_ID == fcA60868)
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), u1OnOff, B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), u1OnOff, B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1);
+#else
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10), u1OnOff, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10), u1OnOff, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1);
+#endif
+
+    return;
+#endif
+}
+#endif
+#if 0
+static void OpenLoopModeSetting(DRAMC_CTX_T * p, DDR800_MODE_T eDDR800Mode)
+{
+#if __A60868_TO_BE_PORTING__
+
+    //Enable SHU option for MCK8X_EN and PHDET_EN
+    if (eDDR800Mode == DDR800_OPEN_LOOP)
+    {
+        vIO32WriteFldMulti_All(DDRPHY_MISC_CG_CTRL6, P_Fld(0x1, MISC_CG_CTRL6_RG_M_CK_OPENLOOP_MODE_EN)
+                    | P_Fld(0x1, MISC_CG_CTRL6_RG_MCK4X_I_OPENLOOP_MODE_EN)
+                    | P_Fld(0x1, MISC_CG_CTRL6_RG_CG_DDR400_MCK4X_I_OFF)
+                    | P_Fld(0x0, MISC_CG_CTRL6_RG_DDR400_MCK4X_I_FORCE_ON)
+                    | P_Fld(0x1, MISC_CG_CTRL6_RG_MCK4X_I_FB_CK_CG_OFF)
+                    | P_Fld(0x1, MISC_CG_CTRL6_RG_MCK4X_Q_OPENLOOP_MODE_EN)
+                    | P_Fld(0x1, MISC_CG_CTRL6_RG_CG_DDR400_MCK4X_Q_OFF)
+                    | P_Fld(0x0, MISC_CG_CTRL6_RG_DDR400_MCK4X_Q_FORCE_ON)
+                    | P_Fld(0x1, MISC_CG_CTRL6_RG_MCK4X_Q_FB_CK_CG_OFF)
+                    | P_Fld(0x1, MISC_CG_CTRL6_RG_MCK4X_O_OPENLOOP_MODE_EN)
+                    | P_Fld(0x1, MISC_CG_CTRL6_RG_CG_DDR400_MCK4X_O_OFF)
+                    | P_Fld(0x0, MISC_CG_CTRL6_RG_DDR400_MCK4X_O_FORCE_ON)
+                    | P_Fld(0x1, MISC_CG_CTRL6_RG_MCK4X_O_FB_CK_CG_OFF));
+
+        vIO32WriteFldAlign_All(DDRPHY_SHU_MISC2, 1, SHU_MISC2_M_CK_OPENLOOP_MODE_SEL);
+    }
+#endif
+}
+#endif
+#if __A60868_TO_BE_PORTING__
+#endif
+#if 0
+static void APhyModeSetting(DRAMC_CTX_T * p, DDR800_MODE_T eMode, U8 *uDLL1, U8 *uMode, U8 *uDLL0)
+{
+#if __A60868_TO_BE_PORTING__
+
+    DDR800Mode_T DDR800Mode;
+
+    OpenLoopModeSetting(p, eMode);
+
+    if ((eMode == DDR800_CLOSE_LOOP) || (eMode == NORMAL_CLOSE_LOOP))
+    {
+        DDR800Mode.phypll_ddr400_en = 0;
+        DDR800Mode.ddr400_en_b0 = 0;
+        DDR800Mode.ddr400_en_b1 = 0;
+        DDR800Mode.ddr400_en_ca = 0;
+        DDR800Mode.dll_phdet_en_b0 = 1;
+        DDR800Mode.dll_phdet_en_b1 = 1;
+        DDR800Mode.dll_phdet_en_ca_cha = 1;
+        DDR800Mode.dll_phdet_en_ca_chb = 1;
+        DDR800Mode.phypll_ada_mck8x_en = 1;
+        DDR800Mode.ddr400_dqs_ps_b0 = 0;
+        DDR800Mode.ddr400_dqs_ps_b1 = 0;
+        DDR800Mode.ddr400_dq_ps_b0 = 0;
+        DDR800Mode.ddr400_dq_ps_b1 = 0;
+        DDR800Mode.ddr400_dqs_ps_ca = 0;
+        DDR800Mode.ddr400_dq_ps_ca = 0;
+        DDR800Mode.ddr400_semi_en_b0 = 0;
+        DDR800Mode.ddr400_semi_en_b1 = 0;
+        DDR800Mode.ddr400_semi_en_ca = 0;
+        DDR800Mode.ddr400_semi_open_en = 0;
+        DDR800Mode.pll0_ada_mck8x_chb_en = 1;
+        DDR800Mode.pll0_ada_mck8x_cha_en = 1;
+
+        if (p->frequency <= 400) //DDR800 1:4 mode
+        {
+            *uDLL1 = 1;
+            *uMode = 0;
+            *uDLL0 = 2;
+        }
+        else if (p->frequency <= 800)
+        {
+            if (vGet_Div_Mode(p) == DIV8_MODE) // DDR1600 1:8 mode
+            {
+                *uDLL1 = 0;
+                *uMode = 0;
+                *uDLL0 = 2;
+            }
+            else // DDR1600 1:4 mode
+            {
+                *uDLL1 = 0;
+                *uMode = 1;
+                *uDLL0 = 0;
+            }
+        }
+        else // 1:8 mode
+        {
+            *uDLL1 = 0;
+            *uMode = 0;
+            *uDLL0 = 2;
+        }
+    }
+    else if (eMode == DDR800_OPEN_LOOP) // For DDR800
+    {
+        DDR800Mode.phypll_ddr400_en = 1;
+        DDR800Mode.ddr400_en_b0 = 1;
+        DDR800Mode.ddr400_en_b1 = 1;
+        DDR800Mode.ddr400_en_ca = 1;
+        DDR800Mode.dll_phdet_en_b0 = 0;
+        DDR800Mode.dll_phdet_en_b1 = 0;
+        DDR800Mode.dll_phdet_en_ca_cha = 0;
+        DDR800Mode.dll_phdet_en_ca_chb = 0;
+        DDR800Mode.phypll_ada_mck8x_en = 0;
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+        DDR800Mode.ddr400_dqs_ps_b0 = 0;  // 2'b00-0 degree, 2'b01-45 degree, 2'b10-90 degree
+        DDR800Mode.ddr400_dqs_ps_b1 = 0;
+        DDR800Mode.ddr400_dq_ps_b0 = 0;
+        DDR800Mode.ddr400_dq_ps_b1 = 0;
+        DDR800Mode.ddr400_dqs_ps_ca = 0; // clk
+        DDR800Mode.ddr400_dq_ps_ca = 0;  // ca
+#else
+        DDR800Mode.ddr400_dqs_ps_b0 = 1;
+        DDR800Mode.ddr400_dqs_ps_b1 = 1;
+        DDR800Mode.ddr400_dq_ps_b0 = 0;
+        DDR800Mode.ddr400_dq_ps_b1 = 0;
+        DDR800Mode.ddr400_dqs_ps_ca = 1;
+        DDR800Mode.ddr400_dq_ps_ca = 2;
+#endif
+        DDR800Mode.ddr400_semi_en_b0 = 0;
+        DDR800Mode.ddr400_semi_en_b1 = 0;
+        DDR800Mode.ddr400_semi_en_ca = 0;
+        DDR800Mode.ddr400_semi_open_en = 0;
+        DDR800Mode.pll0_ada_mck8x_chb_en = 0;
+        DDR800Mode.pll0_ada_mck8x_cha_en = 0;
+        *uDLL1 = 0;
+        *uMode = 1;
+        *uDLL0 = 0;
+    }
+    else if (eMode == DDR800_SEMI_LOOP) // For DDR800
+    {
+        DDR800Mode.phypll_ddr400_en = 1;
+        DDR800Mode.ddr400_en_b0 = 1;
+        DDR800Mode.ddr400_en_b1 = 1;
+        DDR800Mode.ddr400_en_ca = 1;
+        DDR800Mode.dll_phdet_en_b0 = 0;
+        DDR800Mode.dll_phdet_en_b1 = 0;
+        DDR800Mode.dll_phdet_en_ca_cha = 1;
+        DDR800Mode.dll_phdet_en_ca_chb = 0;
+        DDR800Mode.phypll_ada_mck8x_en = 1;
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+        DDR800Mode.ddr400_dqs_ps_b0 = 0;  // 2'b00-0 degree, 2'b01-45 degree, 2'b10-90 degree
+        DDR800Mode.ddr400_dqs_ps_b1 = 0;
+        DDR800Mode.ddr400_dq_ps_b0 = 0;
+        DDR800Mode.ddr400_dq_ps_b1 = 0;
+        DDR800Mode.ddr400_dqs_ps_ca = 0; // clk
+        DDR800Mode.ddr400_dq_ps_ca = 0;  // ca
+#else
+        DDR800Mode.ddr400_dqs_ps_b0 = 1;
+        DDR800Mode.ddr400_dqs_ps_b1 = 1;
+        DDR800Mode.ddr400_dq_ps_b0 = 0;
+        DDR800Mode.ddr400_dq_ps_b1 = 0;
+        DDR800Mode.ddr400_dqs_ps_ca = 1;
+        DDR800Mode.ddr400_dq_ps_ca = 2;
+#endif
+        DDR800Mode.ddr400_semi_en_b0 = 1;
+        DDR800Mode.ddr400_semi_en_b1 = 1;
+        DDR800Mode.ddr400_semi_en_ca = 1;
+        DDR800Mode.ddr400_semi_open_en = 1;
+        DDR800Mode.pll0_ada_mck8x_chb_en = 0;
+        DDR800Mode.pll0_ada_mck8x_cha_en = 1;
+        *uDLL1 = 0;
+        *uMode = 1;
+        *uDLL0 = 2;
+    }
+    else // Others
+    {
+        mcSHOW_ERR_MSG(("[FAIL] APhy mode incorrect !!!\n"));
+        #if __ETT__
+        while (1);
+        #endif
+    }
+
+    // Enable DDR800 RG
+    vIO32WriteFldAlign(DDRPHY_SHU_PLL1, DDR800Mode.phypll_ddr400_en, SHU_PLL1_RG_RPHYPLL_DDR400_EN); // CHA only
+    //vIO32WriteFldAlign_All(DDRPHY_PLL4, DDR800Mode.phypll_ada_mck8x_en, PLL4_RG_RPHYPLL_ADA_MCK8X_EN);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ6, DDR800Mode.ddr400_en_b0, SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ6, DDR800Mode.ddr400_en_b1, SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD6, DDR800Mode.ddr400_en_ca, SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA);
+
+    // DLL & Clock
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DLL0, DDR800Mode.dll_phdet_en_b0, SHU_B0_DLL0_RG_ARDLL_PHDET_EN_B0_SHU);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DLL0, DDR800Mode.dll_phdet_en_b1, SHU_B1_DLL0_RG_ARDLL_PHDET_EN_B1_SHU);
+    vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0, DDR800Mode.dll_phdet_en_ca_cha, SHU_CA_DLL0_RG_ARDLL_PHDET_EN_CA_SHU);
+    vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0 + SHIFT_TO_CHB_ADDR, DDR800Mode.dll_phdet_en_ca_chb, SHU_CA_DLL0_RG_ARDLL_PHDET_EN_CA_SHU);
+    vIO32WriteFldAlign(DDRPHY_SHU_PLL22, DDR800Mode.phypll_ada_mck8x_en, SHU_PLL22_RG_RPHYPLL_ADA_MCK8X_EN_SHU);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_PLL0, DDR800Mode.pll0_ada_mck8x_chb_en, SHU_PLL0_ADA_MCK8X_CHB_EN);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_PLL0, DDR800Mode.pll0_ada_mck8x_cha_en, SHU_PLL0_ADA_MCK8X_CHA_EN);
+
+    // CA/DQS/DQ position
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ9, DDR800Mode.ddr400_dqs_ps_b0, SHU_B0_DQ9_RG_DDR400_DQS_PS_B0);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ9, DDR800Mode.ddr400_dqs_ps_b1, SHU_B1_DQ9_RG_DDR400_DQS_PS_B1);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ9, DDR800Mode.ddr400_dq_ps_b0, SHU_B0_DQ9_RG_DDR400_DQ_PS_B0);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ9, DDR800Mode.ddr400_dq_ps_b1, SHU_B1_DQ9_RG_DDR400_DQ_PS_B1);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD9, DDR800Mode.ddr400_dqs_ps_ca, SHU_CA_CMD9_RG_DDR400_DQS_PS_CA);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD9, DDR800Mode.ddr400_dq_ps_ca, SHU_CA_CMD9_RG_DDR400_DQ_PS_CA);
+
+    // Semi Open Enable
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ9, DDR800Mode.ddr400_semi_en_b0, SHU_B0_DQ9_RG_DDR400_SEMI_EN_B0);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ9, DDR800Mode.ddr400_semi_en_b1, SHU_B1_DQ9_RG_DDR400_SEMI_EN_B1);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD9, DDR800Mode.ddr400_semi_en_ca, SHU_CA_CMD9_RG_DDR400_SEMI_EN_CA);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_PLL0, DDR800Mode.ddr400_semi_open_en, SHU_PLL0_RG_DDR400_SEMI_OPEN_EN);
+#endif
+}
+
+static void DDRDllModeSetting(DRAMC_CTX_T * p)
+{
+#if __A60868_TO_BE_PORTING__
+    U8 uDLL1 = 0, uMode = 0, uDLL0 = 2; // 1:8 mode for bring-up
+
+    APhyModeSetting(p, vGet_DDR800_Mode(p), &uDLL1, &uMode, &uDLL0);
+
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DLL1, uDLL1, SHU_B0_DLL1_FRATE_EN_B0);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DLL1, uDLL1, SHU_B1_DLL1_FRATE_EN_B1);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_CA_DLL2, uDLL1, SHU_CA_DLL2_FRATE_EN);
+
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ6, uMode, SHU_B0_DQ6_RG_TX_ARDQ_SER_MODE_B0);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ6, uMode, SHU_B1_DQ6_RG_TX_ARDQ_SER_MODE_B1);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD6, uMode, SHU_CA_CMD6_RG_TX_ARCMD_SER_MODE);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ6, uMode, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ6, uMode, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD6, uMode, SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE);
+
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DLL0, uDLL0, SHU_B0_DLL0_RG_ARDLL_DIV_MCTL_B0);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DLL0, uDLL0, SHU_B1_DLL0_RG_ARDLL_DIV_MCTL_B1);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_CA_DLL0, uDLL0, SHU_CA_DLL0_RG_ARDLL_DIV_MCTL_CA);
+#endif
+}
+
+static void DDRPhyPLLSetting(DRAMC_CTX_T *p)
+{
+#if __A60868_TO_BE_PORTING__
+
+    U8 u1CAP_SEL;
+    U8 u1MIDPICAP_SEL;
+    U8 u1VTH_SEL;
+    U16 u2SDM_PCW = 0;
+    U8 u1CA_DLL_Mode[2];
+    U8 iChannel = CHANNEL_A;
+    U8 u1BRPI_MCTL_EN_CA = 0;
+    U8 u1PCW_CHG = 0;
+#if ENABLE_TMRRI_NEW_MODE
+    U8 u1RankIdx;
+#endif
+    U8 u1Gain_Ca_ChA = 0, u1Gain_Ca_ChB = 0;
+    U8 u1CurrShuLevel = 0;
+
+    u1VTH_SEL = 0x2; /* RG_*RPI_MIDPI_VTH_SEL[1:0] is 2 for all freqs */
+
+#if (fcFOR_CHIP_ID == fcLafite)
+    if (p->frequency <= 400)
+    {
+        u1CAP_SEL = 0xb;
+    }
+    else if (p->frequency <= 600)
+    {
+        u1CAP_SEL = 0xf;
+    }
+    else if (p->frequency <= 800)
+    {
+        u1CAP_SEL = 0xb;
+    }
+    else if (p->frequency <= 1200)
+    {
+        u1CAP_SEL = 0x8;
+    }
+    else if (p->frequency <= 1333)
+    {
+        u1CAP_SEL = 0x8;
+    }
+    else if (p->frequency <= 1600)
+    {
+        u1CAP_SEL = 0x4;
+    }
+    else if (p->frequency <= 1866)
+    {
+        u1CAP_SEL = 0x2;
+    }
+    else//4266
+    {
+        u1CAP_SEL = 0x1;
+    }
+
+    if (p->frequency <= 933) //Lewis@20161129: Fix DDR1600 S-idle Vcore power is too big problem.
+    {
+        u1MIDPICAP_SEL = 0x2;
+    }
+    else if (p->frequency <= 1200)
+    {
+        u1MIDPICAP_SEL = 0x3;
+    }
+    else if (p->frequency <= 1333)
+    {
+        u1MIDPICAP_SEL = 0x3;
+    }
+    else if (p->frequency <= 1600)
+    {
+        u1MIDPICAP_SEL = 0x2;
+    }
+    else if (p->frequency <= 1866)
+    {
+        u1MIDPICAP_SEL = 0x1;
+    }
+    else//4266
+    {
+        u1MIDPICAP_SEL = 0x0;
+    }
+#if EMI_LPBK_USE_DDR_800
+    if (p->frequency == 800)
+    {
+        u1CAP_SEL = 0xf;    //Ying-Yu suggest setting for FT pattern
+    }
+#endif
+#endif
+
+    vIO32WriteFldAlign_All(DDRPHY_SHU_PLL4, 0x0, SHU_PLL4_RG_RPHYPLL_RESERVED);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_PLL6, 0x0, SHU_PLL6_RG_RCLRPLL_RESERVED);
+
+#if (fcFOR_CHIP_ID == fcLafite)
+    #if DLL_ASYNC_MODE
+    u1BRPI_MCTL_EN_CA = 1;
+    u1CA_DLL_Mode[CHANNEL_A] = u1CA_DLL_Mode[CHANNEL_B] = DLL_MASTER;
+    vIO32WriteFldAlign(DDRPHY_MISC_SHU_OPT + ((U32)CHANNEL_A << POS_BANK_NUM), 1, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN);
+    vIO32WriteFldAlign(DDRPHY_MISC_SHU_OPT + SHIFT_TO_CHB_ADDR, 1, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN);
+    vIO32WriteFldMulti(DDRPHY_CKMUX_SEL + ((U32)CHANNEL_A << POS_BANK_NUM), P_Fld(0, CKMUX_SEL_FMEM_CK_MUX) | P_Fld(0, CKMUX_SEL_FB_CK_MUX));
+    vIO32WriteFldMulti(DDRPHY_CKMUX_SEL + SHIFT_TO_CHB_ADDR, P_Fld(2, CKMUX_SEL_FMEM_CK_MUX) | P_Fld(2, CKMUX_SEL_FB_CK_MUX));
+    #else
+    u1CA_DLL_Mode[CHANNEL_A] = DLL_MASTER;
+    u1CA_DLL_Mode[CHANNEL_B] = DLL_SLAVE;
+    vIO32WriteFldAlign(DDRPHY_MISC_SHU_OPT + ((U32)CHANNEL_A << POS_BANK_NUM), 1, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN);
+    vIO32WriteFldAlign(DDRPHY_MISC_SHU_OPT + SHIFT_TO_CHB_ADDR, 2, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN);
+    vIO32WriteFldMulti(DDRPHY_CKMUX_SEL + ((U32)CHANNEL_A << POS_BANK_NUM), P_Fld(1, CKMUX_SEL_FMEM_CK_MUX) | P_Fld(1, CKMUX_SEL_FB_CK_MUX));
+    vIO32WriteFldMulti(DDRPHY_CKMUX_SEL + SHIFT_TO_CHB_ADDR, P_Fld(1, CKMUX_SEL_FMEM_CK_MUX) | P_Fld(1, CKMUX_SEL_FB_CK_MUX));
+    #endif
+
+    #if ENABLE_DLL_ALL_SLAVE_MODE
+    if ((p->frequency <= 933) && (vGet_DDR800_Mode(p) != DDR800_SEMI_LOOP))
+    {
+        u1CA_DLL_Mode[CHANNEL_A] = u1CA_DLL_Mode[CHANNEL_B] = DLL_SLAVE;
+    }
+    #endif
+
+    if (u1CA_DLL_Mode[CHANNEL_A] == DLL_SLAVE)//All slave mode
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_DVFSCTL, 1, SHU_DVFSCTL_R_BYPASS_1ST_DLL);
+    }
+    else
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_DVFSCTL, 0, SHU_DVFSCTL_R_BYPASS_1ST_DLL);
+    }
+
+    for (iChannel = CHANNEL_A; iChannel <= CHANNEL_B; iChannel++)
+    {
+        if (u1CA_DLL_Mode[iChannel] == DLL_MASTER)
+        {
+            vIO32WriteFldMulti(DDRPHY_SHU_CA_DLL0 + ((U32)iChannel << POS_BANK_NUM), P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_PHDET_OUT_SEL_CA)
+                        | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_PHDET_IN_SWAP_CA)
+                        | P_Fld(0x6, SHU_CA_DLL0_RG_ARDLL_GAIN_CA)
+                        | P_Fld(0x9, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA)
+                        | P_Fld(0x8, SHU_CA_DLL0_RG_ARDLL_P_GAIN_CA)
+                        | P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_PHJUMP_EN_CA)
+                        | P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_PHDIV_CA)
+                        | P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA));
+            vIO32WriteFldMulti(DDRPHY_SHU_CA_DLL1 + ((U32)iChannel << POS_BANK_NUM), P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA));
+            vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD9 + ((U32)iChannel << POS_BANK_NUM), 1, SHU_CA_CMD9_RG_DLL_FAST_PSJP_CA); // RG_*RPI_RESERVE_CA[1] 1'b1 tracking leaf(slave)
+        }
+        else
+        {
+            vIO32WriteFldMulti(DDRPHY_SHU_CA_DLL0 + ((U32)iChannel << POS_BANK_NUM), P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_PHDET_OUT_SEL_CA)
+                        | P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_PHDET_IN_SWAP_CA)
+                        | P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_GAIN_CA)
+                        | P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA)
+                        | P_Fld(0x8, SHU_CA_DLL0_RG_ARDLL_P_GAIN_CA)
+                        | P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_PHJUMP_EN_CA)
+                        | P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_PHDIV_CA)
+                        | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA));
+            vIO32WriteFldMulti(DDRPHY_SHU_CA_DLL1 + ((U32)iChannel << POS_BANK_NUM), P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA));
+            vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD9 + ((U32)iChannel << POS_BANK_NUM), 0, SHU_CA_CMD9_RG_DLL_FAST_PSJP_CA); // RG_*RPI_RESERVE_CA[1] 1'b1 tracking leaf(slave)
+        }
+    }
+#endif
+
+#if (fcFOR_CHIP_ID == fcLafite) // @Darren, enhance DLL Gain for 4S corner DDR2400/DDR1600 0.6125V DVS fail
+    u1CurrShuLevel = vGet_Current_SRAMIdx(p);
+    if ((u1CurrShuLevel == SRAM_SHU4) || (u1CurrShuLevel == SRAM_SHU6))
+    {
+        vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DLL0, 0x8, SHU_B0_DLL0_RG_ARDLL_GAIN_B0);
+        vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DLL0, 0x8, SHU_B1_DLL0_RG_ARDLL_GAIN_B1);
+        u1Gain_Ca_ChA = u4IO32ReadFldAlign(DDRPHY_SHU_CA_DLL0, SHU_CA_DLL0_RG_ARDLL_GAIN_CA);
+        u1Gain_Ca_ChB = u4IO32ReadFldAlign(DDRPHY_SHU_CA_DLL0 + SHIFT_TO_CHB_ADDR, SHU_CA_DLL0_RG_ARDLL_GAIN_CA);
+        u1Gain_Ca_ChA += 1;
+        u1Gain_Ca_ChB += 1;
+        vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0, u1Gain_Ca_ChA, SHU_CA_DLL0_RG_ARDLL_GAIN_CA);
+        vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0 + SHIFT_TO_CHB_ADDR, u1Gain_Ca_ChB, SHU_CA_DLL0_RG_ARDLL_GAIN_CA);
+    }
+#endif
+
+    U32 u4RegBackupAddress[] =
+    {
+        (DDRPHY_B0_DQ7),
+        (DDRPHY_B1_DQ7),
+        (DDRPHY_CA_CMD7),
+        (DDRPHY_B0_DQ7 + SHIFT_TO_CHB_ADDR),
+        (DDRPHY_B1_DQ7 + SHIFT_TO_CHB_ADDR),
+        (DDRPHY_CA_CMD7 + SHIFT_TO_CHB_ADDR),
+    };
+
+    //if(p->vendor_id==VENDOR_SAMSUNG && p->dram_type==TYPE_LPDDR3)
+    {
+#if 0
+        mcSHOW_DBG_MSG(("DDRPhyPLLSetting-DMSUS\n"));
+        vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL0, 0x0, MISC_SPM_CTRL0_PHY_SPM_CTL0);
+        vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL2, 0x0, MISC_SPM_CTRL2_PHY_SPM_CTL2);
+        vIO32WriteFldMulti_All(DDRPHY_MISC_SPM_CTRL1, P_Fld(0x1, MISC_SPM_CTRL1_RG_ARDMSUS_10) | P_Fld(0x1, MISC_SPM_CTRL1_RG_ARDMSUS_10_B0)
+                                                   | P_Fld(0x1, MISC_SPM_CTRL1_RG_ARDMSUS_10_B1) | P_Fld(0x1, MISC_SPM_CTRL1_RG_ARDMSUS_10_CA));
+#else
+        DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+        vIO32WriteFldMulti_All(DDRPHY_B0_DQ7, P_Fld(0x1, B0_DQ7_RG_TX_ARDQ_PULL_DN_B0) | P_Fld(0x1, B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0)
+                                                   | P_Fld(0x1, B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0) | P_Fld(0x1, B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0));
+        vIO32WriteFldMulti_All(DDRPHY_B1_DQ7, P_Fld(0x1, B1_DQ7_RG_TX_ARDQ_PULL_DN_B1) | P_Fld(0x1, B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1)
+                                                   | P_Fld(0x1, B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1) | P_Fld(0x1, B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1));
+        vIO32WriteFldMulti_All(DDRPHY_CA_CMD7, P_Fld(0x1, CA_CMD7_RG_TX_ARCMD_PULL_DN) | P_Fld(0x1, CA_CMD7_RG_TX_ARCS_PULL_DN)
+                                                   | P_Fld(0x1, CA_CMD7_RG_TX_ARCLK_PULL_DN) | P_Fld(0x1, CA_CMD7_RG_TX_ARCLKB_PULL_DN));
+
+        // DMSUS replaced by CA_CMD2_RG_TX_ARCMD_OE_DIS, CMD_OE_DIS(1) will prevent illegal command ouput
+        // And DRAM 1st reset_n pulse will disappear if use CA_CMD2_RG_TX_ARCMD_OE_DIS
+        vIO32WriteFldAlign_All(DDRPHY_CA_CMD2, 1, CA_CMD2_RG_TX_ARCMD_OE_DIS);
+#endif
+    }
+
+    //26M
+    vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0x0, MISC_CG_CTRL0_CLK_MEM_SEL);
+
+    #ifdef USE_CLK26M
+    vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0x1, MISC_CG_CTRL0_RG_DA_RREF_CK_SEL);
+    #endif
+
+    //PLL close sequence:
+    //DLL_PHDET_EN_* = 0
+    //==> CG = 1
+    //==> MIDPI_EN = 0(async)
+    //==> RG_ARPI_RESETB_* = 0
+    //==> MCK8X_EN(source of clk gating) = 0
+    //==> PLL_EN = 0 PIC: Ying-Yu
+
+    //DLL
+    vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI2, 0x0, CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA);
+    vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI2, 0x0, B0_DLL_ARPI2_RG_ARDLL_PHDET_EN_B0);
+    vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI2, 0x0, B1_DLL_ARPI2_RG_ARDLL_PHDET_EN_B1);
+
+    //CG
+    vIO32WriteFldMulti_All(DDRPHY_B0_DLL_ARPI2, P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
+                | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
+                | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
+                | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_FB_B0)
+                | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0)
+                | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0)
+                | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0)
+                | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0)
+                | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0));
+    vIO32WriteFldMulti_All(DDRPHY_B1_DLL_ARPI2, P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1)
+                | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1)
+                | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1)
+                | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_FB_B1)
+                | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1)
+                | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1)
+                | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1)
+                | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1)
+                | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1));
+    vIO32WriteFldMulti_All(DDRPHY_CA_DLL_ARPI2, P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA)
+                | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA)
+                | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA)
+                | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_FB_CA)
+                | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_CS)
+                | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_CLK)
+                | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_CMD)
+                | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN)
+                | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA));
+
+    //MIDPI_EN
+    vIO32WriteFldMulti_All(DDRPHY_SHU_B0_DQ6, P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0)
+                | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0));
+    vIO32WriteFldMulti_All(DDRPHY_SHU_B1_DQ6, P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_EN_B1)
+                | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1));
+    vIO32WriteFldMulti_All(DDRPHY_SHU_CA_CMD6, P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA)
+                | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA));
+
+    //RESETB
+    vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0x0, CA_DLL_ARPI0_RG_ARPI_RESETB_CA);
+    vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0x0, B0_DLL_ARPI0_RG_ARPI_RESETB_B0);
+    vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0x0, B1_DLL_ARPI0_RG_ARPI_RESETB_B1);
+    mcDELAY_US(1);
+
+    //MCK8X_EN
+    vIO32WriteFldMulti_All(DDRPHY_PLL4, P_Fld(0x0, PLL4_RG_RPHYPLL_ADA_MCK8X_EN)
+                | P_Fld(0x0, PLL4_RG_RPHYPLL_RESETB));
+
+    //PLL
+    vIO32WriteFldAlign_All(DDRPHY_PLL1, 0x0, PLL1_RG_RPHYPLL_EN);
+    vIO32WriteFldAlign_All(DDRPHY_PLL2, 0x0, PLL2_RG_RCLRPLL_EN);
+
+    ///TODO: PLL/MIDPI Settings
+    //Ref clock should be 20M~30M, if MPLL=52M, Pre-divider should be set to 1
+    #ifdef USE_CLK26M
+    vIO32WriteFldMulti_All(DDRPHY_SHU_PLL8, P_Fld(0x0, SHU_PLL8_RG_RPHYPLL_POSDIV) | P_Fld(0x0, SHU_PLL8_RG_RPHYPLL_PREDIV));
+    vIO32WriteFldMulti_All(DDRPHY_SHU_PLL10, P_Fld(0x0, SHU_PLL10_RG_RCLRPLL_POSDIV) | P_Fld(0x0, SHU_PLL10_RG_RCLRPLL_PREDIV));
+    #else //MPLL 52M
+    vIO32WriteFldMulti_All(DDRPHY_SHU_PLL8, P_Fld(0x0, SHU_PLL8_RG_RPHYPLL_POSDIV) | P_Fld(0x1, SHU_PLL8_RG_RPHYPLL_PREDIV));
+    vIO32WriteFldMulti_All(DDRPHY_SHU_PLL10, P_Fld(0x0, SHU_PLL10_RG_RCLRPLL_POSDIV) | P_Fld(0x1, SHU_PLL10_RG_RCLRPLL_PREDIV));
+    #endif
+
+    if (p->frequency == 2133)
+    {
+        u2SDM_PCW = 0xa400;
+    }
+    else if (p->frequency == 1866)
+    {   // 2722/26=143(0x8f)
+        #if ENABLE_FIX_SHORT_PLUSE
+        u2SDM_PCW = 0x7b00; // DDR3200
+        #else
+        u2SDM_PCW = 0x8f00;
+        #endif
+    }
+    else if (p->frequency == 1600 || p->frequency == 800 || p->frequency == 400)
+    {
+        #if ENABLE_FIX_SHORT_PLUSE
+        if (p->frequency == 1600)
+            u2SDM_PCW = 0x6c00; //DDR2800
+        #else
+        if (p->frequency == 1600)
+            u2SDM_PCW = 0x7700; //DDR3200(3094)
+        else if (p->frequency == 800)
+            u2SDM_PCW = 0x7600; //DDR1600(1534)
+        #endif
+        else if ((p->frequency == 400) && (vGet_DDR800_Mode(p) == DDR800_OPEN_LOOP))
+            u2SDM_PCW = 0x3c00; //DDR800 Open Loop Mode
+        else if (p->frequency == 400)
+            u2SDM_PCW = 0x7e00; //DDR826 for avoid GPS de-sense
+        else
+            u2SDM_PCW = 0x7b00; //DDR1600
+
+#if EMI_LPBK_USE_DDR_800 // For Ei_ger DDR800 no need
+        if (p->frequency == 800)
+        {
+            vIO32WriteFldAlign_All(DDRPHY_SHU_PLL8, 0x1, SHU_PLL8_RG_RPHYPLL_POSDIV);
+            vIO32WriteFldAlign_All(DDRPHY_SHU_PLL10, 0x1, SHU_PLL10_RG_RCLRPLL_POSDIV);
+        }
+#endif
+    }
+    else if (p->frequency == 1333 || p->frequency == 667)
+    {
+        u2SDM_PCW = 0x6600;
+    }
+    else if (p->frequency == 1200)
+    {
+        #if ENABLE_FIX_SHORT_PLUSE
+        u2SDM_PCW = 0x5100; //DDR2100
+        #else
+        u2SDM_PCW = 0x5c00;
+        #endif
+    }
+    else if (p->frequency == 1140)
+    {
+        u2SDM_PCW = 0x5700;
+    }
+    //LP3
+    else if (p->frequency == 933)
+    {
+        u2SDM_PCW = 0x8f00;
+    }
+    else if (p->frequency == 600)
+    {
+        u2SDM_PCW = 0x5c00;
+    }
+    else if (p->frequency == 467)
+    {
+        u2SDM_PCW = 0x4700;
+    }
+
+    /* SDM_PCW: Feedback divide ratio (8-bit integer + 8-bit fraction)
+     * PLL_SDM_FRA_EN: SDMPLL fractional mode enable (0:Integer mode, 1:Fractional mode)
+     */
+    vIO32WriteFldMulti_All(DDRPHY_SHU_PLL5, P_Fld(u2SDM_PCW, SHU_PLL5_RG_RPHYPLL_SDM_PCW)
+                                            | P_Fld(0x0, SHU_PLL5_RG_RPHYPLL_SDM_FRA_EN)); // Disable fractional mode
+    vIO32WriteFldMulti_All(DDRPHY_SHU_PLL7, P_Fld(u2SDM_PCW, SHU_PLL7_RG_RCLRPLL_SDM_PCW)
+                                            | P_Fld(0x0, SHU_PLL7_RG_RCLRPLL_SDM_FRA_EN)); // Disable fractional mode
+
+#if (fcFOR_CHIP_ID == fcLafite) // YH for LPDDR4 1:4 mode and 1:8 mode, Darren confirm with YH Cho
+    DDRDllModeSetting(p);
+#endif
+
+    vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0, CA_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_CA);
+    vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0, B0_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B0);
+    vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0, B1_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B1);
+    vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI1, 0, CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN);
+    vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI1, 0, B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0);
+    vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI1, 0, B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1);
+
+
+    vIO32WriteFldMulti_All(DDRPHY_SHU_B0_DQ6, P_Fld(u1VTH_SEL, SHU_B0_DQ6_RG_ARPI_MIDPI_VTH_SEL_B0)
+                | P_Fld(u1CAP_SEL, SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0)
+                | P_Fld(u1MIDPICAP_SEL, SHU_B0_DQ6_RG_ARPI_MIDPI_CAP_SEL_B0));
+    vIO32WriteFldMulti_All(DDRPHY_SHU_B1_DQ6, P_Fld(u1VTH_SEL, SHU_B1_DQ6_RG_ARPI_MIDPI_VTH_SEL_B1)
+                | P_Fld(u1CAP_SEL, SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1)
+                | P_Fld(u1MIDPICAP_SEL, SHU_B1_DQ6_RG_ARPI_MIDPI_CAP_SEL_B1));
+    vIO32WriteFldMulti_All(DDRPHY_SHU_CA_CMD6, P_Fld(u1VTH_SEL, SHU_CA_CMD6_RG_ARPI_MIDPI_VTH_SEL_CA)
+                | P_Fld(u1CAP_SEL, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA)
+                | P_Fld(u1MIDPICAP_SEL, SHU_CA_CMD6_RG_ARPI_MIDPI_CAP_SEL_CA));
+
+    //PLL open sequence
+    //PLL_EN = 1
+    //==> some of MIDPI*_EN = 1(async)
+    //==> RG_ARPI_RESETB_* = 1(async, open first)
+    //==> MCK8X_EN(source of clk gating) = 1
+    //==> CG = 0
+    //==> DLL_PHDET_EN_* = 1 PIC: Ying-Yu
+
+    //PLL
+    vIO32WriteFldAlign_All(DDRPHY_PLL1, 0x1, PLL1_RG_RPHYPLL_EN);
+    vIO32WriteFldAlign_All(DDRPHY_PLL2, 0x1, PLL2_RG_RCLRPLL_EN);
+    mcDELAY_US(100);
+
+    ///TODO: MIDPI Init 2
+    /* MIDPI Settings (Olymp_us): DA_*RPI_MIDPI_EN, DA_*RPI_MIDPI_CKDIV4_EN
+     * Justin suggests use frequency > 933 as boundary
+     */
+    if (p->frequency > 933)
+    {
+        vIO32WriteFldMulti_All(DDRPHY_SHU_B0_DQ6, P_Fld(0x1, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0)
+                    | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0));
+        vIO32WriteFldMulti_All(DDRPHY_SHU_B1_DQ6, P_Fld(0x1, SHU_B1_DQ6_RG_ARPI_MIDPI_EN_B1)
+                    | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1));
+        vIO32WriteFldMulti_All(DDRPHY_SHU_CA_CMD6, P_Fld(0x1, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA)
+                    | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA));
+    }
+    else
+    {
+        if ((p->frequency == 400) && (vGet_DDR800_Mode(p) != DDR800_CLOSE_LOOP)) // For *DDR800_OPEN_LOOP
+        {
+            vIO32WriteFldMulti_All(DDRPHY_SHU_B0_DQ6, P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0)
+                        | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0));
+            vIO32WriteFldMulti_All(DDRPHY_SHU_B1_DQ6, P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_EN_B1)
+                        | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1));
+            if (vGet_DDR800_Mode(p) == DDR800_SEMI_LOOP)
+            {
+                // DDR800_SEMI_LOOP from YY comment to DVT (1/0, CHA CA/other)
+                vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD6, 0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA);
+                vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD6, 0x1, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA);
+                vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD6 + SHIFT_TO_CHB_ADDR, 0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA);
+            }
+            else
+            {   //DDR800_OPEN_LOOP
+                vIO32WriteFldMulti_All(DDRPHY_SHU_CA_CMD6, P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA)
+                            | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA));
+            }
+        }
+        else
+        {
+            //MIDPI_EN
+            vIO32WriteFldMulti_All(DDRPHY_SHU_B0_DQ6, P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0)
+                        | P_Fld(0x1, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0));
+            vIO32WriteFldMulti_All(DDRPHY_SHU_B1_DQ6, P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_EN_B1)
+                        | P_Fld(0x1, SHU_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1));
+            vIO32WriteFldMulti_All(DDRPHY_SHU_CA_CMD6, P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA)
+                        | P_Fld(0x1, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA));
+        }
+    }
+    mcDELAY_US(1);
+
+    //RESETB
+    vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0x1, CA_DLL_ARPI0_RG_ARPI_RESETB_CA);
+    vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0x1, B0_DLL_ARPI0_RG_ARPI_RESETB_B0);
+    vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0x1, B1_DLL_ARPI0_RG_ARPI_RESETB_B1);
+    mcDELAY_US(1);
+
+    ///TODO: MIDPI Init 1
+    //MCK8X_EN
+    vIO32WriteFldMulti_All(DDRPHY_PLL4, P_Fld(0x1, PLL4_RG_RPHYPLL_ADA_MCK8X_EN)
+                | P_Fld(0x1, PLL4_RG_RPHYPLL_RESETB));
+    mcDELAY_US(1);
+
+    #if (fcFOR_CHIP_ID == fcLafite)
+    vIO32WriteFldMulti(DDRPHY_CA_DLL_ARPI3, P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA)
+                | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_FB_EN_CA)
+                | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CS_EN)
+                | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CLK_EN)
+                | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CMD_EN));
+    vIO32WriteFldMulti(DDRPHY_CA_DLL_ARPI3 + SHIFT_TO_CHB_ADDR, P_Fld(u1BRPI_MCTL_EN_CA, CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA) //CH_B CA slave
+                | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_FB_EN_CA)
+                | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CS_EN)
+                | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CLK_EN)
+                | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CMD_EN));
+    #endif
+    vIO32WriteFldMulti_All(DDRPHY_B0_DLL_ARPI3, P_Fld(0x1, B0_DLL_ARPI3_RG_ARPI_FB_EN_B0)
+                | P_Fld(0x1, B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0)
+                | P_Fld(0x1, B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0)
+                | P_Fld(0x1, B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0)
+                | P_Fld(0x1, B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0));
+    vIO32WriteFldMulti_All(DDRPHY_B1_DLL_ARPI3, P_Fld(0x1, B1_DLL_ARPI3_RG_ARPI_FB_EN_B1)
+                | P_Fld(0x1, B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1)
+                | P_Fld(0x1, B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1)
+                | P_Fld(0x1, B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1)
+                | P_Fld(0x1, B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1));
+   //CG
+    vIO32WriteFldMulti_All(DDRPHY_CA_DLL_ARPI2, P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA)
+                | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA)
+                | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA)
+                | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_FB_CA)
+                | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CS)
+                | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CLK)
+                | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CMD)
+                | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA));
+    vIO32WriteFldMulti_All(DDRPHY_B0_DLL_ARPI2, P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
+                | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
+                | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
+                | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_FB_B0)
+                | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0)
+                | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0)
+                | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0)
+                | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0));
+    vIO32WriteFldMulti_All(DDRPHY_B1_DLL_ARPI2, P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1)
+                | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1)
+                | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1)
+                | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_FB_B1)
+                | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1)
+                | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1)
+                | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1)
+                | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1));
+    #if (fcFOR_CHIP_ID == fcLafite)
+    vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI2, 1, CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN);
+    vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI2, 0, B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0);
+    vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI2, 0, B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1);
+    #endif
+
+    mcDELAY_US(2);
+
+    vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0x1, MISC_CG_CTRL0_CLK_MEM_SEL);
+    mcDELAY_US(1);
+
+#if ENABLE_APHY_DLL_IDLE_MODE_OPTION //Should before the PHDET_EN = 1
+    vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI5, 0x0, CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA);
+    vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI5 + SHIFT_TO_CHB_ADDR, 0x1, CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA);
+    vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI5, 0x1, B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0);
+    vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI5, 0x1, B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1);
+
+    vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI5, 0x3, B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0);//Zone1: 48ps Zone2: 96ps if(8ps/delay cell)
+    vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI5, 0x3, B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1);//Intrinsic 2 delay cell, setting: x
+    vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI5, 0x3, CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA);//Zone1 = 2 + 2x; Zone2 = 2 * Zone1
+
+    vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI5, 0xC, B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0);
+    vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI5, 0xC, B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1);
+    vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI5, 0xC, CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA);
+#endif
+
+    //DLL
+    vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI2, 0x1, CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA);
+    mcDELAY_US(1);
+    vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI2, 0x1, CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA);
+    mcDELAY_US(1);
+    vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI2, 0x1, B0_DLL_ARPI2_RG_ARDLL_PHDET_EN_B0);
+    mcDELAY_US(1);
+    vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI2, 0x1, B1_DLL_ARPI2_RG_ARDLL_PHDET_EN_B1);
+    mcDELAY_US(1);
+
+    //if(p->vendor_id==VENDOR_SAMSUNG && p->dram_type==TYPE_LPDDR3)
+    {
+#if 0
+        mcSHOW_DBG_MSG(("DDRPhyPLLSetting-DMSUS\n\n"));
+        vIO32WriteFldMulti_All(DDRPHY_MISC_SPM_CTRL1, P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10) | P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10_B0)
+                                                   | P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10_B1) | P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10_CA));
+        vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL0, 0xffffffff, MISC_SPM_CTRL0_PHY_SPM_CTL0);
+        vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL2, 0xffffffff, MISC_SPM_CTRL2_PHY_SPM_CTL2);
+#else
+        // DMSUS replaced by CA_CMD2_RG_TX_ARCMD_OE_DIS, CMD_OE_DIS(1) will prevent illegal command ouput
+        // And DRAM 1st reset_n pulse will disappear if use CA_CMD2_RG_TX_ARCMD_OE_DIS
+        vIO32WriteFldAlign_All(DDRPHY_CA_CMD2, 0, CA_CMD2_RG_TX_ARCMD_OE_DIS);
+        DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+#endif
+
+        mcSHOW_DBG_MSG2(("DDRPhyPLLSetting-CKEON\n\n"));
+
+        CKEFixOnOff(p, TO_ALL_RANK, CKE_DYNAMIC, TO_ALL_CHANNEL);
+    }
+
+#if ENABLE_DFS_SSC_WA
+    DDRSSCSetting(p);
+#endif
+
+    DDRPhyFreqMeter(p);
+#endif
+}
+#endif
+#if CBT_MOVE_CA_INSTEAD_OF_CLK
+void DramcCmdUIDelaySetting(DRAMC_CTX_T *p, U8 value)
+{
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7), P_Fld(value, SHU_SELPH_CA7_DLY_RA0) |
+                                                                P_Fld(value, SHU_SELPH_CA7_DLY_RA1) |
+                                                                P_Fld(value, SHU_SELPH_CA7_DLY_RA2) |
+                                                                P_Fld(value, SHU_SELPH_CA7_DLY_RA3) |
+                                                                P_Fld(value, SHU_SELPH_CA7_DLY_RA4) |
+                                                                P_Fld(value, SHU_SELPH_CA7_DLY_RA5) |
+                                                                P_Fld(value, SHU_SELPH_CA7_DLY_RA6));
+
+    // Note: CKE UI must sync CA UI (CA and CKE delay circuit are same) @Lin-Yi
+    // To avoid tXP timing margin issue
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), value, SHU_SELPH_CA5_DLY_CKE);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA6), value, SHU_SELPH_CA6_DLY_CKE1);
+
+    ///TODO: Yirong : new calibration flow : change CS UI to 0
+//  vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1));
+}
+#endif
+
+void cbt_dfs_mr13_global(DRAMC_CTX_T *p, U8 freq)
+{
+    U8 u1RankIdx;
+    U8 backup_rank;
+
+    backup_rank = u1GetRank(p);
+
+    for(u1RankIdx =0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+
+        if (freq == CBT_LOW_FREQ)
+        {
+            DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE);
+            DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_WR, JUST_TO_GLOBAL_VALUE);
+        }
+        else // CBT_HIGH_FREQ
+        {
+            DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE);
+            DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, JUST_TO_GLOBAL_VALUE);
+        }
+    }
+
+    vSetRank(p, backup_rank);
+}
+
+void cbt_switch_freq(DRAMC_CTX_T *p, U8 freq)
+{
+#if (FOR_DV_SIMULATION_USED == TRUE) // @Darren+ for DV sim
+    return;
+#endif
+
+    U8 u1backup_TCKFIXON[CHANNEL_NUM], ch, ch_bak;
+
+#if MR_CBT_SWITCH_FREQ
+#if (fcFOR_CHIP_ID == fc8195)
+    static U8 _CurFreq = CBT_UNKNOWN_FREQ;
+    if (_CurFreq == freq)
+    {
+        return; // Do nothing no meter the frequency is.
+    }
+    _CurFreq = freq;
+
+    /* @chengchun + Dynamic MIOCK to avoid CK stop state violation during DFS */
+    ch_bak = p->channel;
+    for (ch = CHANNEL_A; ch < p->support_channel_num; ch++) {
+        vSetPHY2ChannelMapping(p, ch);
+        u1backup_TCKFIXON[ch] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL),
+            DRAMC_PD_CTRL_TCKFIXON);
+    }
+    vSetPHY2ChannelMapping(p, ch_bak);
+    vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_PD_CTRL, 0x0, DRAMC_PD_CTRL_TCKFIXON);
+
+    EnableDFSHwModeClk(p);
+
+    if (freq == CBT_LOW_FREQ)
+    {
+        #if REPLACE_DFS_RG_MODE
+        DramcDFSDirectJump_SPMMode_forK(p, DRAM_DFS_REG_SHU1); //only use in Calibration (SCSM mode)
+        //DramcDFSDirectJump_SPMMode(p, SRAM_SHU3);// Darren NOTE: Dramc shu1 for MRW (DramcModeRegInit_LP4 and CBT)
+        //We use SRAM3(DDR1866-DIFF) instead of SRAM4(DDR1600-SE) because MRW is blocked and will cause SOC(SE) and DRAM(DIFF) mismatch.
+        #else
+        DramcDFSDirectJump_RGMode(p, DRAM_DFS_REG_SHU1); // Darren NOTE: Dramc shu1 for MRW (DramcModeRegInit_LP4 and CBT)
+        #endif
+    }
+    else
+    {
+        #if REPLACE_DFS_RG_MODE
+        DramcDFSDirectJump_SPMMode_forK(p, DRAM_DFS_REG_SHU0);
+        //DramcDFSDirectJump_SPMMode(p, vGet_Current_SRAMIdx(p));
+        #else
+        DramcDFSDirectJump_RGMode(p, DRAM_DFS_REG_SHU0);
+        #endif
+    }
+
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CLK_CTRL, P_Fld(0, MISC_CLK_CTRL_DVFS_CLK_MEM_SEL)
+                                                    | P_Fld(0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN));
+
+    for (ch = CHANNEL_A; ch < p->support_channel_num; ch++) {
+        vSetPHY2ChannelMapping(p, ch);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u1backup_TCKFIXON[ch],
+            DRAMC_PD_CTRL_TCKFIXON);
+    }
+    vSetPHY2ChannelMapping(p, ch_bak);
+
+    DDRPhyFreqMeter(p);
+#else
+    #error Need check of the DRAM_DFS_SHUFFLE_X for your chip !!!
+#endif
+#endif
+}
+
+
+void DramcPowerOnSequence(DRAMC_CTX_T *p)
+{
+#if ENABLE_TMRRI_NEW_MODE
+    //U8 u1RankIdx;
+#endif
+
+#ifdef DUMP_INIT_RG_LOG_TO_DE
+    //CKE high
+    CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ALL_CHANNEL);
+    return;
+#endif
+
+    #if APPLY_LP4_POWER_INIT_SEQUENCE
+    //static U8 u1PowerOn=0;
+    //if(u1PowerOn ==0)
+    {
+    //reset dram = low
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0x0, MISC_CTRL1_R_DMDA_RRESETB_I);
+
+    //vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0, RKCFG_CKE2RANK_OPT2);
+
+    //CKE low
+    CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXOFF, TO_ALL_CHANNEL);
+
+    // delay tINIT1=200us(min) & tINIT2=10ns(min)
+    mcDELAY_US(200);
+
+    //reset dram = low
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0x1, MISC_CTRL1_R_DMDA_RRESETB_I);
+
+    // Disable HW MIOCK control to make CLK always on
+    DramCLKAlwaysOnOff(p, ON, TO_ALL_CHANNEL);
+
+    //tINIT3=2ms(min)
+    mcDELAY_MS(2);
+
+    //CKE high
+    CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ALL_CHANNEL);
+
+    // tINIT5=2us(min)
+    mcDELAY_US(2);
+    //u1PowerOn=1;
+
+    //// Enable  HW MIOCK control to make CLK dynamic
+    DramCLKAlwaysOnOff(p, OFF, TO_ALL_CHANNEL);
+    mcSHOW_DBG_MSG5(("APPLY_LP4_POWER_INIT_SEQUENCE\n"));
+    }
+    #endif
+}
+
+DRAM_STATUS_T DramcModeRegInit_CATerm(DRAMC_CTX_T *p, U8 bWorkAround)
+{
+    static U8 CATermWA[CHANNEL_NUM] = {0};
+    U8 u1ChannelIdx, u1RankIdx, u1RankIdxBak;
+    U32 backup_broadcast;
+    //U8 operating_fsp = p->dram_fsp;
+    U8 u1MR11_Value;
+    U8 u1MR22_Value;
+
+    u1ChannelIdx = vGetPHY2ChannelMapping(p);
+
+    if (CATermWA[u1ChannelIdx] == bWorkAround)
+        return DRAM_OK;
+
+    CATermWA[u1ChannelIdx] = bWorkAround;
+
+    backup_broadcast = GetDramcBroadcast();
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+    u1RankIdxBak = u1GetRank(p);
+
+    for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+
+        mcSHOW_DBG_MSG2(("[DramcModeRegInit_CATerm] CH%u RK%u bWorkAround=%d\n", u1ChannelIdx, u1RankIdx, bWorkAround));
+        /* FSP_1: 1. For term freqs   2. Assumes "data rate >= DDR2667" are terminated */
+        #if MRW_CHECK_ONLY
+        mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+        #endif
+        DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, TO_MR); //@Darren, Fix high freq keep FSP0 for CA term workaround (PPR abnormal)
+        DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, TO_MR);
+
+        //MR12 use previous value
+
+        if (p->dram_type == TYPE_LPDDR4P)
+        {
+            u1MR11_Value = 0x0;                  //ODT disable
+        }
+        else
+        {
+#if ENABLE_SAMSUNG_NT_ODT
+            if ((p->vendor_id == VENDOR_SAMSUNG) && (p->revision_id == 0x7)) // 1ynm process for NT-ODT
+            {
+                u1MR11_Value = 0x2;              //@Darren, DQ ODT:120ohm -> parallel to 60ohm
+                u1MR11_Value |= (0x1 << 3);   //@Darren, MR11[3]=1 to enable NT-ODT for B707
+            }
+            else
+#endif
+                u1MR11_Value = 0x3;              //DQ ODT:80ohm
+
+        #if FSP1_CLKCA_TERM
+            if (p->dram_cbt_mode[u1RankIdx] == CBT_NORMAL_MODE)
+            {
+                u1MR11_Value |= 0x40;              //CA ODT:60ohm for byte mode
+            }
+            else
+            {
+                u1MR11_Value |= 0x20;              //CA ODT:120ohm for byte mode
+            }
+        #endif
+        }
+    #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
+        if (gDramcDqOdtRZQAdjust >= 0)
+            u1MR11_Value = gDramcDqOdtRZQAdjust;
+    #endif
+        u1MR11Value[p->dram_fsp] = u1MR11_Value;
+        DramcModeRegWriteByRank(p, u1RankIdx, 11, u1MR11Value[p->dram_fsp]); //ODT
+
+        if (p->dram_type == TYPE_LPDDR4)
+        {
+            u1MR22_Value = 0x24;     //SOC-ODT, ODTE-CK, ODTE-CS, Disable ODTD-CA
+        }
+        else  //TYPE_LPDDR4x, LP4P
+        {
+            u1MR22_Value = 0x3c;     //Disable CA-CS-CLK ODT, SOC ODT=RZQ/4
+        #if FSP1_CLKCA_TERM
+            if (bWorkAround)
+            {
+                u1MR22_Value = 0x4;
+            }
+            else
+            {
+                if (u1RankIdx == RANK_0)
+                {
+                    u1MR22_Value = 0x4;     //Enable CA-CS-CLK ODT, SOC ODT=RZQ/4
+                }
+                else
+                {
+                    u1MR22_Value = 0x2c;     //Enable CS ODT, SOC ODT=RZQ/4
+                }
+            }
+        #endif
+        }
+    #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
+        if (gDramcMR22SoCODTAdjust[u1MRFsp] >= 0)
+        {
+            u1MR22_Value = (u1MR22_Value & ~(0x7)) | gDramcMR22SoCODTAdjust[u1MRFsp];
+        }
+    #endif
+        u1MR22Value[p->dram_fsp] = u1MR22_Value;
+        DramcModeRegWriteByRank(p, u1RankIdx, 22, u1MR22_Value);
+    }
+
+    vSetRank(p, u1RankIdxBak);
+//  vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), RANK_0, MRS_MRSRK);
+
+    DramcBroadcastOnOff(backup_broadcast);
+
+    return DRAM_OK;
+}
+
+DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p)
+{
+    U32 u4RankIdx;//, u4CKE0Bak, u4CKE1Bak, u4MIOCKBak, u4AutoRefreshBak;
+    U8  u1MR2_RLWL;
+    //U16 u2MR3Value;
+    U8 u1MRFsp= FSP_0;
+    U8 u1ChannelIdx; //support_channel_num
+    U8 backup_channel, backup_rank;
+    U8 operating_fsp = p->dram_fsp;
+    U32 backup_broadcast;
+    U8 u1MR11_Value;
+    U8 u1MR22_Value;
+    U8 u1nWR=0;
+    U16 u2FreqMax = u2DFSGetHighestFreq(p);
+    U8 u1set_mrsrk=0;
+
+    backup_broadcast = GetDramcBroadcast();
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+
+    DramcPowerOnSequence(p);
+
+    backup_channel = p->channel;
+    backup_rank = p->rank;
+
+
+#if VENDER_JV_LOG
+    vPrintCalibrationBasicInfo_ForJV(p);
+#endif
+
+    /* Fix nWR value to 30 (MR01[6:4] = 101B) for DDR3200
+     * Fix nWR value to 34 (MR01[6:4] = 110B) for DDR3733
+     * Other vendors: Use default MR01 for each FSP (Set in vInitGlobalVariablesByCondition() )
+     */
+    {
+        /* Clear MR01 OP[6:4] */
+        u1MR01Value[FSP_0] &= 0x8F;
+        u1MR01Value[FSP_1] &= 0x8F;
+        if (u2FreqMax == 2133)
+        {
+            /* Set MR01 OP[6:4] to 111B = 7 */
+            u1MR01Value[FSP_0] |= (0x7 << 4);
+            u1MR01Value[FSP_1] |= (0x7 << 4);
+            u1nWR = 40;
+        }
+        else if (u2FreqMax == 1866)
+        {
+            /* Set MR01 OP[6:4] to 110B = 6 */
+            u1MR01Value[FSP_0] |= (0x6 << 4);
+            u1MR01Value[FSP_1] |= (0x6 << 4);
+            u1nWR = 34;
+        }
+        else // Freq <= 1600
+        {
+            /* Set MR01 OP[6:4] to 101B = 5 */
+            u1MR01Value[FSP_0] |= (0x5 << 4);
+            u1MR01Value[FSP_1] |= (0x5 << 4);
+            u1nWR = 30;
+        }
+
+        mcSHOW_DBG_MSG2(("nWR fixed to %d\n", u1nWR));
+        //mcDUMP_REG_MSG(("nWR fixed to %d\n", u1nWR));
+    }
+
+#ifndef DUMP_INIT_RG_LOG_TO_DE
+    if(p->dram_fsp == FSP_1)
+    {
+        // @Darren, VDDQ = 600mv + CaVref default is 301mV (no impact)
+        // Fix high freq keep FSP0 for CA term workaround (PPR abnormal)
+        CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ALL_CHANNEL);
+        cbt_switch_freq(p, CBT_LOW_FREQ);
+        CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ALL_CHANNEL);
+    }
+#endif
+
+    for(u1ChannelIdx=0; u1ChannelIdx<(p->support_channel_num); u1ChannelIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1ChannelIdx);
+
+        for(u4RankIdx =0; u4RankIdx < (U32)(p->support_rank_num); u4RankIdx++)
+        {
+            vSetRank(p, u4RankIdx);
+
+            mcSHOW_DBG_MSG2(("[ModeRegInit_LP4] CH%u RK%u\n", u1ChannelIdx, u4RankIdx));
+            //mcDUMP_REG_MSG(("[ModeRegInit_LP4] CH%u RK%u\n", u1ChannelIdx, u4RankIdx));
+        #if VENDER_JV_LOG
+            mcSHOW_JV_LOG_MSG(("\n[ModeRegInit_LP4] CH%u RK%d\n", u1ChannelIdx, u4RankIdx));
+        #endif
+        #if MRW_CHECK_ONLY
+            mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+        #endif
+
+            //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), u4RankIdx, MRS_MRSRK);
+
+            // Note : MR37 for LP4P should be set before any Mode register.
+            // MR37 is not shadow register, just need to set by channel and rank. No need to set by FSP
+            if(p->dram_type == TYPE_LPDDR4P)
+            {
+                //temp solution, need remove later
+            #ifndef MT6779_FPGA
+            #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
+                #if __Petrus_TO_BE_PORTING__
+                    dramc_set_vddq_voltage(p->dram_type, 600000);
+                #endif
+            #endif
+            #endif
+
+                DramcModeRegWriteByRank(p, u4RankIdx, 37, 0x1);
+
+                //temp solution, need remove later
+            #ifndef MT6779_FPGA
+            #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
+                #if __Petrus_TO_BE_PORTING__
+                    dramc_set_vddq_voltage(p->dram_type, 400000);
+                #endif
+            #endif
+            #endif
+            }
+
+
+           // if(p->frequency<=1200)
+            {
+                /* FSP_0: 1. For un-term freqs   2. Assumes "data rate < DDR2667" are un-term */
+                u1MRFsp = FSP_0;
+                mcSHOW_DBG_MSG2(("\tFsp%d\n", u1MRFsp));
+            #if VENDER_JV_LOG
+                mcSHOW_JV_LOG_MSG(("\tFsp%d\n", u1MRFsp));
+            #endif
+
+                u1MR13Value[u4RankIdx] = 0;
+                MRWriteFldMulti(p, 13, P_Fld(1, MR13_PRO) |
+                                       P_Fld(1, MR13_VRCG),
+                                       TO_MR);
+
+                //MR12 use previous value
+                DramcModeRegWriteByRank(p, u4RankIdx, 12, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]);
+                DramcModeRegWriteByRank(p, u4RankIdx, 1, u1MR01Value[u1MRFsp]);
+
+                //MR2 set Read/Write Latency
+                u1MR2_RLWL = LP4_DRAM_INIT_RLWL_MRfield_config(p->frequency << 1);
+                u1MR02Value[p->dram_fsp] = u1MR2_RLWL | (u1MR2_RLWL << 3); //@tg update 1:4 mode DDR400/800 WL/RL according to spec.
+
+                #if 0
+                if (p->freqGroup <= 400) // DDR800, DDR400
+                {
+                    u1MR02Value[u1MRFsp] = 0x12; // the minimum of WL is 8, and the minimum of RL is 14 (Jouling and HJ)
+                }
+                else if ((p->freqGroup == 800) || (p->freqGroup == 600)) // DDR1600, DDR1200
+                {
+                    u1MR02Value[u1MRFsp] = 0x12;
+                }
+                else if (p->freqGroup == 933) // DDR1866
+                {
+                    u1MR02Value[u1MRFsp] = 0x1b; //RL=20, WL=10
+                }
+                else if (p->freqGroup == 1200) // DDR2280, DDR2400 (DDR2667 uses FSP_1)
+                {
+                    u1MR02Value[u1MRFsp] = 0x24;
+                }
+                #endif
+                DramcModeRegWriteByRank(p, u4RankIdx, 2, u1MR02Value[u1MRFsp]);
+                //if(p->odt_onoff)
+                u1MR11Value[u1MRFsp] = 0x0;
+                DramcModeRegWriteByRank(p, u4RankIdx, 11, u1MR11Value[u1MRFsp]); //ODT disable
+
+#if ENABLE_LP4Y_DFS
+                // For LPDDR4Y <= DDR1600 un-term
+                if (p->freqGroup <= 800)
+                {
+                    u1MR21Value[u1MRFsp] |= (0x1 << 5); // Low Speed CA buffer for LP4Y
+                    #if LP4Y_BACKUP_SOLUTION
+                    u1MR51Value[u1MRFsp] |= (0x3 << 1); // CLK[3]=0, WDQS[2]=1 and RDQS[1]=1 Single-End mode for LP4Y
+                    #endif
+                }
+                else if ((p->freqGroup == 1200) || (p->freqGroup == 933))
+#endif
+                {
+                    u1MR21Value[u1MRFsp] = 0;
+                    u1MR51Value[u1MRFsp] = 0;
+                }
+                DramcModeRegWriteByRank(p, u4RankIdx, 21, u1MR21Value[u1MRFsp]);
+                DramcModeRegWriteByRank(p, u4RankIdx, 51, u1MR51Value[u1MRFsp]);
+
+                if(p->dram_type == TYPE_LPDDR4)
+                {
+                    u1MR22_Value = 0x20;     //SOC-ODT, ODTE-CK, ODTE-CS, Disable ODTD-CA
+                }
+                else  //TYPE_LPDDR4x, LP4P
+                {
+                    u1MR22_Value = 0x38;     //SOC-ODT, ODTE-CK, ODTE-CS, Disable ODTD-CA
+                }
+            #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
+                if (gDramcMR22SoCODTAdjust[u1MRFsp]>=0)
+                {
+                    u1MR22_Value = (u1MR22_Value&~(0x7))|gDramcMR22SoCODTAdjust[u1MRFsp];
+                }
+            #endif
+                u1MR22Value[u1MRFsp] = u1MR22_Value;
+                DramcModeRegWriteByRank(p, u4RankIdx, 22, u1MR22Value[u1MRFsp]);
+
+                //MR14 use previous value
+                DramcModeRegWriteByRank(p, u4RankIdx, 14, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]); //MR14 VREF-DQ
+
+            #if CALIBRATION_SPEED_UP_DEBUG
+                mcSHOW_DBG_MSG2(("CBT Vref Init: CH%d Rank%d FSP%d, Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f)));
+                mcSHOW_DBG_MSG2(("TX Vref Init: CH%d Rank%d FSP%d, TX Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp,u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f)));
+            #endif
+
+                //MR3 set write-DBI and read-DBI (Disabled during calibration, enabled after K)
+                u1MR03Value[u1MRFsp] = (u1MR03Value[u1MRFsp]&0x3F);
+
+                if(p->dram_type == TYPE_LPDDR4X || p->dram_type == TYPE_LPDDR4P)
+                {
+                    u1MR03Value[u1MRFsp] &= 0xfe;
+                }
+            #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
+                if (gDramcMR03PDDSAdjust[u1MRFsp]>=0)
+                {
+                    u1MR03Value[u1MRFsp] = (u1MR03Value[u1MRFsp]&~(0x7<<3))|(gDramcMR03PDDSAdjust[u1MRFsp]<<3);
+                }
+            #endif
+                // @Darren, Follow samsung PPR recommend flow
+                DramcModeRegWriteByRank(p, u4RankIdx, 3, u1MR03Value[u1MRFsp]);
+                DramcModeRegWriteByRank(p, u4RankIdx, 4, u1MR04Value[u4RankIdx]);
+                DramcModeRegWriteByRank(p, u4RankIdx, 3, u1MR03Value[u1MRFsp]);
+            }
+            //else
+            {
+                /* FSP_1: 1. For term freqs   2. Assumes "data rate >= DDR2667" are terminated */
+                u1MRFsp = FSP_1;
+                mcSHOW_DBG_MSG2(("\tFsp%d\n", u1MRFsp));
+            #if VENDER_JV_LOG
+                mcSHOW_JV_LOG_MSG(("\tFsp%d\n", u1MRFsp));
+            #endif
+
+                DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, TO_MR);
+
+                //MR12 use previous value
+                #if CBT_FSP1_MATCH_FSP0_UNTERM_WA
+                if (p->dram_fsp == FSP_0)
+                    DramcModeRegWriteByRank(p, u4RankIdx, 12, u1MR12Value[u1ChannelIdx][u4RankIdx][FSP_0]); //MR12 VREF-CA
+                else
+                #endif
+                DramcModeRegWriteByRank(p, u4RankIdx, 12, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]); //MR12 VREF-CA
+                DramcModeRegWriteByRank(p, u4RankIdx, 1, u1MR01Value[u1MRFsp]);
+                #if 0
+                //MR2 set Read/Write Latency
+                if (p->freqGroup == 2133)
+                {
+                    u1MR02Value[u1MRFsp] = 0x3f;
+                }
+                else if (p->freqGroup == 1866)
+                {
+                    u1MR02Value[u1MRFsp] = 0x36;
+                }
+                else if (p->freqGroup == 1600)
+                {
+                    u1MR02Value[u1MRFsp] = 0x2d;
+                }
+                else if (p->freqGroup == 1333)
+                {
+                    u1MR02Value[u1MRFsp] = 0x24;
+                }
+                #endif
+                DramcModeRegWriteByRank(p, u4RankIdx, 2, u1MR02Value[u1MRFsp]);
+
+                if(p->dram_type == TYPE_LPDDR4P)
+                    u1MR11_Value = 0x0;                  //ODT disable
+                else
+                {
+#if ENABLE_SAMSUNG_NT_ODT
+                    if ((p->vendor_id == VENDOR_SAMSUNG) && (p->revision_id == 0x7)) // 1ynm process for NT-ODT
+                    {
+                        u1MR11_Value = 0x2;              //@Darren, DQ ODT:120ohm -> parallel to 60ohm
+                        u1MR11_Value |= (0x1 << 3);   //@Darren, MR11[3]=1 to enable NT-ODT for B707
+                    }
+                    else
+#endif
+                        u1MR11_Value = 0x3;              //DQ ODT:80ohm
+
+                #if FSP1_CLKCA_TERM
+                #if CBT_FSP1_MATCH_FSP0_UNTERM_WA
+                if (p->dram_fsp == FSP_1)
+                #endif
+                {
+                    if(p->dram_cbt_mode[u4RankIdx]==CBT_NORMAL_MODE)
+                    {
+                        u1MR11_Value |= 0x40;              //CA ODT:60ohm for normal mode die
+                    }
+                    else
+                    {
+                        u1MR11_Value |= 0x20;              //CA ODT:120ohm for byte mode die
+                    }
+                }
+                #endif
+                }
+            #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
+                    if (gDramcDqOdtRZQAdjust>=0)
+                    {
+                        u1MR11_Value &= ~(0x7);
+                        u1MR11_Value = gDramcDqOdtRZQAdjust;
+                    }
+            #endif
+                    u1MR11Value[u1MRFsp] = u1MR11_Value;
+                    DramcModeRegWriteByRank(p, u4RankIdx, 11, u1MR11Value[u1MRFsp]); //ODT
+
+                u1MR21Value[u1MRFsp] = 0;
+                u1MR51Value[u1MRFsp] = 0;
+                DramcModeRegWriteByRank(p, u4RankIdx, 21, u1MR21Value[u1MRFsp]);
+                DramcModeRegWriteByRank(p, u4RankIdx, 51, u1MR51Value[u1MRFsp]);
+
+                if(p->dram_type == TYPE_LPDDR4)
+                {
+                    u1MR22_Value = 0x24;     //SOC-ODT, ODTE-CK, ODTE-CS, Disable ODTD-CA
+                }
+                else  //TYPE_LPDDR4x, LP4P
+                {
+                    u1MR22_Value = 0x3c;     //Disable CA-CS-CLK ODT, SOC ODT=RZQ/4
+                #if FSP1_CLKCA_TERM
+                #if CBT_FSP1_MATCH_FSP0_UNTERM_WA
+                if (p->dram_fsp == FSP_1)
+                #endif
+                {
+                    if(u4RankIdx==RANK_0)
+                    {
+                        u1MR22_Value = 0x4;     //Enable CA-CS-CLK ODT, SOC ODT=RZQ/4
+                    }
+                    else
+                    {
+                        u1MR22_Value = 0x2c;     //Enable CS ODT, SOC ODT=RZQ/4
+                    }
+                }
+                #endif
+                }
+            #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
+                if (gDramcMR22SoCODTAdjust[u1MRFsp]>=0)
+                {
+                    u1MR22_Value = (u1MR22_Value&~(0x7))|gDramcMR22SoCODTAdjust[u1MRFsp];
+                }
+            #endif
+                u1MR22Value[u1MRFsp] = u1MR22_Value;
+                DramcModeRegWriteByRank(p, u4RankIdx, 22, u1MR22Value[u1MRFsp]);
+
+                //MR14 use previous value
+                DramcModeRegWriteByRank(p, u4RankIdx, 14, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]); //MR14 VREF-DQ
+
+            #if CALIBRATION_SPEED_UP_DEBUG
+                mcSHOW_DBG_MSG2(("CBT Vref Init: CH%d Rank%d FSP%d, Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f)));
+                mcSHOW_DBG_MSG2(("TX Vref Init: CH%d Rank%d FSP%d, TX Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f)));
+            #endif
+
+                //MR3 set write-DBI and read-DBI (Disabled during calibration, enabled after K)
+                u1MR03Value[u1MRFsp] = (u1MR03Value[u1MRFsp]&0x3F);
+
+                if(p->dram_type == TYPE_LPDDR4X || p->dram_type == TYPE_LPDDR4P)
+                {
+                    u1MR03Value[u1MRFsp] &= 0xfe;
+                }
+            #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
+                if (gDramcMR03PDDSAdjust[u1MRFsp]>=0)
+                {
+                    u1MR03Value[u1MRFsp] = (u1MR03Value[u1MRFsp]&~(0x7<<3))|(gDramcMR03PDDSAdjust[u1MRFsp]<<3);
+                }
+            #endif
+                // @Darren, Follow samsung PPR recommend flow
+                DramcModeRegWriteByRank(p, u4RankIdx, 3, u1MR03Value[u1MRFsp]);
+                DramcModeRegWriteByRank(p, u4RankIdx, 4, u1MR04Value[u4RankIdx]);
+                DramcModeRegWriteByRank(p, u4RankIdx, 3, u1MR03Value[u1MRFsp]);
+            }
+
+#if ENABLE_LP4_ZQ_CAL
+            DramcZQCalibration(p, u4RankIdx); //ZQ calobration should be done before CBT calibration by switching to low frequency
+#endif
+
+            /* freq < 1333 is assumed to be odt_off -> uses FSP_0 */
+            //if (p->frequency < MRFSP_TERM_FREQ)
+            if(operating_fsp == FSP_0)
+            {
+                DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE);
+                DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_WR, JUST_TO_GLOBAL_VALUE);
+            }
+            else
+            {
+                DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE);
+                DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, JUST_TO_GLOBAL_VALUE);
+            }
+        }
+        vSetRank(p, backup_rank);
+
+#if 0
+        for(u4RankIdx =0; u4RankIdx < (U32)(p->support_rank_num); u4RankIdx++)
+        {
+            DramcModeRegWriteByRank(p, u4RankIdx, 13, u1MR13Value[RANK_0]);
+        }
+#else
+
+        /* MRS two ranks simutaniously */
+        if (p->support_rank_num == RANK_DUAL)
+            u1set_mrsrk = 0x3;
+        else
+            u1set_mrsrk = RANK_0;
+        DramcModeRegWriteByRank(p, u1set_mrsrk, 13, u1MR13Value[RANK_0]);
+#endif
+
+        /* Auto-MRW related register write (Used during HW DVFS frequency switch flow)
+         * VRCG seems to be enabled/disabled even when switching to same FSP(but different freq) to simplify HW DVFS flow
+         */
+        // 1. MR13 OP[3] = 1 : Enable "high current mode" to reduce the settling time when changing FSP(freq) during operation
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), P_Fld(u1MR13Value[RANK_0] | (0x1 << 3), SHU_HWSET_MR13_HWSET_MR13_OP)
+                                                                    | P_Fld(13, SHU_HWSET_MR13_HWSET_MR13_MRSMA));
+        // 2. MR13 OP[3] = 1 : Enable "high current mode" after FSP(freq) switch operation for calibration
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), P_Fld(u1MR13Value[RANK_0] | (0x1 << 3), SHU_HWSET_VRCG_HWSET_VRCG_OP)
+                                                                    | P_Fld(13, SHU_HWSET_VRCG_HWSET_VRCG_MRSMA));
+        // 3. MR2 : Set RL/WL after FSP(freq) switch
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR2), P_Fld(u1MR02Value[operating_fsp], SHU_HWSET_MR2_HWSET_MR2_OP)
+                                                                    | P_Fld(2, SHU_HWSET_MR2_HWSET_MR2_MRSMA));
+    }
+
+#ifndef DUMP_INIT_RG_LOG_TO_DE
+    //switch to high freq
+    if(p->dram_fsp == FSP_1)
+    {
+        // @Darren, no effect via DDR1600 (purpose to keep @FSP0)
+        // Fix high freq keep FSP0 for CA term workaround (PPR abnormal)
+        CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ALL_CHANNEL);
+        cbt_switch_freq(p, CBT_HIGH_FREQ);
+        CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ALL_CHANNEL);
+    }
+#endif
+    vSetPHY2ChannelMapping(p, backup_channel);
+
+#if ENABLE_DFS_RUNTIME_MRW
+    DFSRuntimeMRW_preset_BeforeK(p, vGet_Current_SRAMIdx(p));
+#endif
+
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), RANK_0, SWCMD_CTRL0_MRSRK);
+
+    DramcBroadcastOnOff(backup_broadcast);
+
+#if SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER
+    vApplyProgramSequence(p);
+#endif
+
+    return DRAM_OK;
+}
+
+
+void MPLLInit(void)
+{
+#if (FOR_DV_SIMULATION_USED==0)
+#if 0//__A60868_TO_BE_PORTING__
+
+#if (FOR_DV_SIMULATION_USED == 0)
+    unsigned int tmp;
+
+    DRV_WriteReg32(AP_PLL_CON0, 0x11); // CLKSQ Enable
+    mcDELAY_US(100);
+    DRV_WriteReg32(AP_PLL_CON0, 0x13); // CLKSQ LPF Enable
+    mcDELAY_MS(1);
+    DRV_WriteReg32(MPLL_PWR_CON0, 0x3); // power on MPLL
+    mcDELAY_US(30);
+    DRV_WriteReg32(MPLL_PWR_CON0, 0x1); // turn off ISO of  MPLL
+    mcDELAY_US(1);
+    tmp = DRV_Reg32(MPLL_CON1);
+    DRV_WriteReg32(MPLL_CON1, tmp | 0x80000000); // Config MPLL freq
+    DRV_WriteReg32(MPLL_CON0, 0x181); // enable MPLL
+    mcDELAY_US(20);
+#endif
+#else
+    unsigned int tmp;
+
+	tmp = DRV_Reg32(MPLL_CON4);
+	DRV_WriteReg32(MPLL_CON4, tmp | 0x1); // turn off ISO of  MPLL
+
+
+	tmp = DRV_Reg32(MPLL_CON4);
+	DRV_WriteReg32(MPLL_CON4, tmp & 0xfffffffd); // turn off ISO of  MPLL
+
+
+	tmp = DRV_Reg32(MPLL_CON0);
+	DRV_WriteReg32(MPLL_CON0, tmp & 0xffffefff); // turn off ISO of  MPLL
+
+
+	tmp = DRV_Reg32(MPLL_CON2);
+ 	DRV_WriteReg32(MPLL_CON2, 0x84200000); // turn off ISO of  MPLL
+
+
+	tmp = DRV_Reg32(MPLL_CON0);
+	DRV_WriteReg32(MPLL_CON0, tmp | 0x200); // turn off ISO of  MPLL
+
+#endif
+#endif
+}
+
+
+#if ENABLE_RODT_TRACKING_SAVE_MCK
+static void SetTxWDQSStatusOnOff(U8 u1OnOff)
+{
+      u1WDQS_ON = u1OnOff;
+}
+#endif
+
+
+#if XRTRTR_NEW_CROSS_RK_MODE
+void XRTRTR_SHU_Setting(DRAMC_CTX_T * p)
+{
+    U8 u1RkSelUIMinus = 0, u1RkSelMCKMinus = 0;
+    //U8 u1RankIdx = 0;
+    //U8 u1Rank_backup = u1GetRank(p);
+
+    if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) // DDR800semi
+        u1RkSelMCKMinus = 1;
+    else if (p->frequency >= 1600) //DDR3200 up
+        u1RkSelUIMinus = 2;
+
+    // DV codes is included
+    /*vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ6, u1ShuRkMode, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ6, u1ShuRkMode, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1);*/
+
+    //DRAMC setting - @Darren, DV no set (double confirm)
+    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(u1RkSelMCKMinus, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)
+                                       | P_Fld(u1RkSelUIMinus, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS)
+                                       | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS)
+                                       | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS)
+                                       | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN)
+                                       | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK)
+                                       | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK)
+                                       | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) // @HJ, no use
+                                       | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23)
+                                       | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN));
+    //Darren-vIO32WriteFldAlign_All(DRAMC_REG_SHU_STBCAL, 0x1, SHU_STBCAL_DQSIEN_RX_SELPH_OPT); //@HJ, internal wire assign to 1'b1
+
+    /*for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)
+                                           | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT)
+                                           | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN)
+                                           | P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT));
+    }
+    vSetRank(p, u1Rank_backup);*/
+}
+
+#if 0
+static void ENABLE_XRTRTR_Setting(DRAMC_CTX_T * p)
+{
+#if 0 // @Darren, DV codes is included
+    U8 u1ByteIdx = 0;
+    U32 u4ByteOffset = 0;
+
+    // DV codes is included
+    for(u1ByteIdx=0; u1ByteIdx<DQS_NUMBER_LP4; u1ByteIdx++)
+    {
+        u4ByteOffset = u1ByteIdx*DDRPHY_AO_B0_B1_OFFSET;
+        // PHY setting for B0/B1
+        vIO32WriteFldAlign_All(DDRPHY_REG_B0_DLL_ARPI1 + u4ByteOffset, 0x1, B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0);
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DLL_ARPI3 + u4ByteOffset, 0x1, SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0);
+
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ2 + u4ByteOffset, P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0)
+                                           | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0)
+                                           | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0));
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ10 + u4ByteOffset, P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0)
+                                           | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0));
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ11 + u4ByteOffset, P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0)
+                                           | P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0));
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ13 + u4ByteOffset, 0x1, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0);
+    }
+
+    // DV codes is included
+    vIO32WriteFldMulti_All(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0));
+    vIO32WriteFldMulti_All(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1));
+    //Darren-vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD9, P_Fld(0, CA_CMD9_R_IN_GATE_EN_LOW_OPT_CA) | P_Fld(0, CA_CMD9_R_DMRXDVS_R_F_DLY_RK_OPT));
+
+    // DV codes is included
+    vIO32WriteFldAlign_All(DDRPHY_REG_B0_DQ10, 0x1, B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0);
+    vIO32WriteFldAlign_All(DDRPHY_REG_B1_DQ10, 0x1, B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1);
+
+    // DV codes is included
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_STBCAL2, P_Fld(0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN)
+                                       | P_Fld(0x1, MISC_STBCAL2_STB_RST_BY_RANK)
+                                       | P_Fld(0x1, MISC_STBCAL2_STB_IG_XRANK_CG_RST));
+
+    //Extend 1T timing of FIFO mode rank switch
+    // DV codes is included
+    vIO32WriteFldAlign_All(DDRPHY_REG_B0_DQ9, 0x2, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0);
+    vIO32WriteFldAlign_All(DDRPHY_REG_B1_DQ9, 0x2, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1);
+    vIO32WriteFldAlign_All(DDRPHY_REG_B0_DQ9, 0x1, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0);
+    vIO32WriteFldAlign_All(DDRPHY_REG_B1_DQ9, 0x1, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1);
+#endif
+}
+#endif
+#endif
+
+#if XRTWTW_NEW_CROSS_RK_MODE
+void XRTWTW_SHU_Setting(DRAMC_CTX_T * p)
+{
+    U8 u1RankIdx, u1ByteIdx;
+    U8 u1Rank_bak = u1GetRank(p);
+    U16 u2TxDly_OEN_RK[2][2] = {0}, u2TxPI_UPD[2] = {0}, u2TxRankINCTL, u2TxDly_OEN_RK_max, u2TxPI_UPD_max;
+
+    for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+
+        u2TxDly_OEN_RK[u1RankIdx][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ0); //Byte0
+        u2TxDly_OEN_RK[u1RankIdx][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ1); //Byte1
+    }
+    vSetRank(p, u1Rank_bak);
+
+    for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+    {
+        u2TxDly_OEN_RK_max = (u2TxDly_OEN_RK[0][u1ByteIdx] > u2TxDly_OEN_RK[1][u1ByteIdx])? u2TxDly_OEN_RK[0][u1ByteIdx]: u2TxDly_OEN_RK[1][u1ByteIdx];
+        if (p->frequency >= 1200)
+            u2TxPI_UPD[u1ByteIdx] = (u2TxDly_OEN_RK_max > 2)? (u2TxDly_OEN_RK_max - 2): 0; //Byte0
+        else
+            u2TxPI_UPD[u1ByteIdx] = (u2TxDly_OEN_RK_max > 1)? (u2TxDly_OEN_RK_max - 1): 0; //Byte0
+    }
+
+    u2TxPI_UPD_max = (u2TxPI_UPD[0] > u2TxPI_UPD[1])? u2TxPI_UPD[0]: u2TxPI_UPD[1];
+    u2TxRankINCTL = (u2TxPI_UPD_max > 1)? (u2TxPI_UPD_max - 1): 0;
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_NEW_XRW2W_CTRL), P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)
+                                           | P_Fld(u2TxPI_UPD[0], SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0)
+                                           | P_Fld(u2TxPI_UPD[1], SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_RANKCTL), P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)
+                                            | P_Fld(u2TxRankINCTL, SHU_TX_RANKCTL_TXRANKINCTL)
+                                            | P_Fld(u2TxRankINCTL, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY));
+}
+#if 0
+static void ENABLE_XRTWTW_Setting(DRAMC_CTX_T * p)
+{
+#if 0 // @Darren, DV codes is included
+    // DV codes is included
+    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ2, P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0)
+                                       | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0));
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ13, 0x1, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0);
+
+    // DV codes is included
+    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ2, P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1)
+                                       | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1));
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ13, 0x1, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1);
+
+    // @Darren, CA don't care for xrank w2w
+    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD2, P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA)
+                                       | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA));
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD13, 0x1, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA);
+#endif
+}
+#endif
+#endif
+
+#if CMD_CKE_WORKAROUND_FIX
+static void CMD_CKE_Modified_txp_Setting(DRAMC_CTX_T * p)
+{
+#if __A60868_TO_BE_PORTING__
+
+    U8 u1CmdTxPipe = 0, u1CkTxPipe = 0, u1SrefPdSel = 0;
+
+    if (vGet_Div_Mode(p) == DIV4_MODE)
+    {
+        u1CkTxPipe = 1;
+        u1SrefPdSel = 1;
+    }
+    else if (p->frequency >= 1866)
+    {
+        u1CmdTxPipe = 1;
+        u1CkTxPipe = 1;
+    }
+
+    vIO32WriteFldAlign(DDRPHY_SHU_MISC0, u1CkTxPipe, SHU_MISC0_RG_CK_TXPIPE_BYPASS_EN);
+    vIO32WriteFldAlign(DDRPHY_SHU_MISC0, u1CmdTxPipe, SHU_MISC0_RG_CMD_TXPIPE_BYPASS_EN);
+    //vIO32WriteFldAlign(DRAMC_REG_SHU_CONF0, u1SrefPdSel, SHU_CONF0_SREF_PD_SEL);
+#endif //__A60868_TO_BE_PORTING__
+}
+#endif
+
+#if TX_OE_EXTEND
+static void UpdateTxOEN(DRAMC_CTX_T *p)
+{
+    U8 u1ByteIdx, backup_rank, ii;
+    U8 u1DQ_OE_CNT;
+
+    // For LP4
+    // 1. R_DMDQOE_OPT (dramc_conf 0x8C0[11])
+    //    set 1'b1: adjust DQSOE/DQOE length with R_DMDQOE_CNT
+    // 2. R_DMDQOE_CNT (dramc_conf 0x8C0[10:8])
+    //    set 3'h3
+    // 3. Initial TX setting OE/DATA
+    //    OE = DATA - 4 UI
+
+    // For LP3
+    // 1. R_DMDQOE_OPT (dramc_conf 0x8C0[11])
+    //    set 1'b1: adjust DQSOE/DQOE length with R_DMDQOE_CNT
+    // 2. R_DMDQOE_CNT (dramc_conf 0x8C0[10:8])
+    //    set 3'h2
+    // 3. Initial TX setting OE/DATA
+    //    OE = DATA - 2 UI
+
+    u1DQ_OE_CNT = 3;
+
+    vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(1, SHU_TX_SET0_DQOE_OPT) | P_Fld(u1DQ_OE_CNT, SHU_TX_SET0_DQOE_CNT));
+
+    backup_rank = u1GetRank(p);
+
+    LP4_ShiftDQS_OENUI(p, -1, ALL_BYTES);
+    ShiftDQ_OENUI_AllRK(p, -1, ALL_BYTES);
+
+}
+#endif
+#if 0
+static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p)
+{
+#if __A60868_TO_BE_PORTING__
+
+    U16 u2RXVrefDefault = 0x8;
+    U16 u1ChannelIdx, u1RankIdx, u1ByteIdx;
+    U16 u2Clk_Dyn_Gating_Sel = 0x4, u2CG_CK_SEL = 0xb;
+    #if CBT_MOVE_CA_INSTEAD_OF_CLK
+    U8 u1CaPI = 0, u1CaUI = 0;
+    U8 u1RankIdxBak;
+    #endif
+
+    if (p->odt_onoff == ODT_ON)
+    {
+        vIO32WriteFldAlign(DRAMC_REG_SHU_ODTCTRL, 1, SHU_ODTCTRL_ROEN);
+        vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x1, SHU_B0_DQ7_R_DMRODTEN_B0);
+        vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x1, SHU_B1_DQ7_R_DMRODTEN_B1);
+        vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD0, P_Fld(0x0, SHU_CA_CMD0_RG_TX_ARCMD_PRE_EN) // OE Suspend EN
+                | P_Fld(0x1, SHU_CA_CMD0_RG_TX_ARCLK_PRE_EN)); //ODT Suspend EN
+    }
+    else
+    {
+        vIO32WriteFldAlign(DRAMC_REG_SHU_ODTCTRL, 0, SHU_ODTCTRL_ROEN);
+        vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x0, SHU_B0_DQ7_R_DMRODTEN_B0);
+        vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x0, SHU_B1_DQ7_R_DMRODTEN_B1);
+        vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD0, P_Fld(0x0, SHU_CA_CMD0_RG_TX_ARCMD_PRE_EN) // OE Suspend EN
+                | P_Fld(0x0, SHU_CA_CMD0_RG_TX_ARCLK_PRE_EN)); //ODT Suspend EN
+    }
+
+    //close RX DQ/DQS tracking to save power
+    vIO32WriteFldMulti(DDRPHY_R0_B0_RXDVS2, P_Fld(0x0, R0_B0_RXDVS2_R_RK0_DVS_MODE_B0)
+                | P_Fld(0x0, R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0)
+                | P_Fld(0x0, R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0));
+    vIO32WriteFldMulti(DDRPHY_R1_B0_RXDVS2, P_Fld(0x0, R1_B0_RXDVS2_R_RK1_DVS_MODE_B0)
+                | P_Fld(0x0, R1_B0_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_B0)
+                | P_Fld(0x0, R1_B0_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_B0));
+    vIO32WriteFldMulti(DDRPHY_R0_B1_RXDVS2, P_Fld(0x0, R0_B1_RXDVS2_R_RK0_DVS_MODE_B1)
+                | P_Fld(0x0, R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1)
+                | P_Fld(0x0, R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1));
+    vIO32WriteFldMulti(DDRPHY_R1_B1_RXDVS2, P_Fld(0x0, R1_B1_RXDVS2_R_RK1_DVS_MODE_B1)
+                | P_Fld(0x0, R1_B1_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_B1)
+                | P_Fld(0x0, R1_B1_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_B1));
+    //wei-jen: RX rank_sel for CA is not used(), set it's dly to 0 to save power
+    vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD7, 0, SHU_CA_CMD7_R_DMRANKRXDVS_CA); //Move to DCM off setting
+
+
+    //DDRPhyTxRxInitialSettings_LP4
+    vIO32WriteFldAlign(DDRPHY_CA_CMD3, 0x1, CA_CMD3_RG_RX_ARCMD_STBENCMP_EN);
+
+    vIO32WriteFldAlign(DDRPHY_CA_CMD10, 0x1, CA_CMD10_RG_RX_ARCLK_DQSIENMODE);
+
+    vIO32WriteFldAlign(DDRPHY_CA_CMD6, 0x2, CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL);
+
+    vIO32WriteFldMulti(DDRPHY_B0_DQ3, P_Fld(0x1, B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0)
+                        | P_Fld(0x1, B0_DQ3_RG_RX_ARDQM0_IN_BUFF_EN_B0)
+                        | P_Fld(0x1, B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0));
+    vIO32WriteFldMulti(DDRPHY_B1_DQ3, P_Fld(0x1, B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1)
+                        | P_Fld(0x1, B1_DQ3_RG_RX_ARDQM0_IN_BUFF_EN_B1)
+                        | P_Fld(0x1, B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1));
+    vIO32WriteFldMulti(DDRPHY_CA_CMD3, P_Fld(0x1, CA_CMD3_RG_RX_ARCMD_IN_BUFF_EN)
+                            | P_Fld(0x1, CA_CMD3_RG_RX_ARCLK_IN_BUFF_EN));
+
+    vIO32WriteFldAlign(DDRPHY_B0_DQ3, 0x0, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ3, 0x0, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1);
+
+    vIO32WriteFldAlign(DDRPHY_B0_DQ5, 0x1, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ5, 0x1, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1);
+    vIO32WriteFldAlign(DDRPHY_CA_CMD5, 0x1, CA_CMD5_RG_RX_ARCLK_DVS_EN);
+
+    //LP4 no need, follow LP3 first.
+    //vIO32WriteFldAlign(DDRPHY_MISC_VREF_CTRL, P_Fld(0x1, MISC_VREF_CTRL_RG_RVREF_DDR3_SEL)
+    //                                        | P_Fld(0x0, MISC_VREF_CTRL_RG_RVREF_DDR4_SEL));
+
+
+    vIO32WriteFldMulti(DDRPHY_CA_CMD6, P_Fld(0x0, CA_CMD6_RG_TX_ARCMD_DDR3_SEL)
+                                    | P_Fld(0x1, CA_CMD6_RG_TX_ARCMD_DDR4_SEL)
+                                    | P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_DDR3_SEL)
+                                    | P_Fld(0x1, CA_CMD6_RG_RX_ARCMD_DDR4_SEL));
+    vIO32WriteFldMulti(DDRPHY_CA_CMD6, P_Fld(0x0, CA_CMD6_RG_TX_ARCMD_DDR3_SEL)
+                                    | P_Fld(0x1, CA_CMD6_RG_TX_ARCMD_DDR4_SEL)
+                                    | P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_DDR3_SEL)
+                                    | P_Fld(0x1, CA_CMD6_RG_RX_ARCMD_DDR4_SEL));
+    vIO32WriteFldMulti(DDRPHY_MISC_IMP_CTRL0, P_Fld(0x0, MISC_IMP_CTRL0_RG_RIMP_DDR3_SEL)
+                                    | P_Fld(0x1, MISC_IMP_CTRL0_RG_RIMP_DDR4_SEL));
+
+
+    vIO32WriteFldAlign(DDRPHY_B0_DQ6, 0x0, B0_DQ6_RG_RX_ARDQ_O1_SEL_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ6, 0x0, B1_DQ6_RG_RX_ARDQ_O1_SEL_B1);
+    vIO32WriteFldAlign(DDRPHY_CA_CMD6, 0x0, CA_CMD6_RG_RX_ARCMD_O1_SEL);
+
+    vIO32WriteFldAlign(DDRPHY_B0_DQ6, 0x1, B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ6, 0x1, B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1);
+    vIO32WriteFldAlign(DDRPHY_CA_CMD6, 0x1, CA_CMD6_RG_RX_ARCMD_BIAS_PS);
+    vIO32WriteFldAlign(DDRPHY_CA_CMD6, 0x1, CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN);
+
+    vIO32WriteFldAlign(DDRPHY_B0_DQ6, 0x0, B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ6, 0x0, B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1);
+    vIO32WriteFldAlign(DDRPHY_CA_CMD6, 0x0, CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS);
+
+    vIO32WriteFldAlign(DDRPHY_B0_DQ6, 0x1, B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ6, 0x1, B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1);
+    vIO32WriteFldAlign(DDRPHY_CA_CMD6, 0x1, CA_CMD6_RG_RX_ARCMD_RPRE_TOG_EN);
+
+    if (p->dram_type == TYPE_LPDDR4)
+    {
+        if (p->odt_onoff == ODT_ON)
+        {
+            u2RXVrefDefault = 0x17; // 0.6*VDDQ, 0x12=0.5*VDDQ
+        }
+        else
+        {
+            u2RXVrefDefault = 0x29;
+        }
+    }
+    else if (p->dram_type == TYPE_LPDDR4X)
+    {
+        if (p->odt_onoff == ODT_ON)
+        {
+            u2RXVrefDefault = 0x17; // 0.6*VDDQ, 0x12=0.5*VDDQ
+        }
+        else
+        {
+            u2RXVrefDefault = 0x29;
+        }
+    }
+    else //if(p->dram_type == TYPE_LPDDR4P)
+    {
+        u2RXVrefDefault = 0x10;
+    }
+
+    #if CALIBRATION_SPEED_UP_DEBUG
+    mcSHOW_DBG_MSG2(("\nInit Yulia RX Vref %d, apply to both rank0 and 1\n", u2RXVrefDefault));
+    #endif
+
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, u2RXVrefDefault, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0);
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ5, u2RXVrefDefault, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1);
+    vIO32WriteFldAlign(DDRPHY_B0_DQ5, u2RXVrefDefault, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ5, u2RXVrefDefault, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1);
+
+    for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < CHANNEL_NUM; u1ChannelIdx++)
+    {
+        for (u1RankIdx = RANK_0; u1RankIdx < RANK_MAX; u1RankIdx++)
+        {
+            for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+            {
+                gFinalRXVrefDQ[u1ChannelIdx][u1RankIdx][u1ByteIdx] = u2RXVrefDefault;
+            }
+        }
+    }
+
+    if ((p->dram_type == TYPE_LPDDR4X) || (p->dram_type == TYPE_LPDDR4P))
+    {
+        // LP4x eye fine-tune
+        // APHY Review by YY Hsu
+        vIO32WriteFldAlign(DDRPHY_B0_DQ8, 0x1, B0_DQ8_RG_TX_ARDQ_EN_LP4P_B0);
+        vIO32WriteFldAlign(DDRPHY_B1_DQ8, 0x1, B1_DQ8_RG_TX_ARDQ_EN_LP4P_B1);
+        vIO32WriteFldAlign(DDRPHY_CA_CMD9, 0x1, CA_CMD9_RG_TX_ARCMD_EN_LP4P);
+    }
+
+
+    /* Set initial default mode to "new burst mode (7UI or new 8UI)" */
+    DramcGatingMode(p, 1);
+
+    vIO32WriteFldAlign(DDRPHY_CA_CMD8, 0x1, CA_CMD8_RG_TX_RRESETB_DDR3_SEL);
+    vIO32WriteFldAlign(DDRPHY_CA_CMD8, 0x0, CA_CMD8_RG_TX_RRESETB_DDR4_SEL); //TODO: Remove if register default value is 0
+    //End of DDRPhyTxRxInitialSettings_LP4
+
+    //DFS workaround
+    vIO32WriteFldAlign(DRAMC_REG_SHU_MISC, 0x2, SHU_MISC_REQQUE_MAXCNT);
+
+    //should set 0x2a, otherwise AC-timing violation from Berson
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG, P_Fld(0x2a, SHU_DQSG_SCINTV) | P_Fld(0x1, SHU_DQSG_DQSINCTL_PRE_SEL));
+
+
+    //Update setting for
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, 0x0, SHU_B0_DQ5_RG_ARPI_FB_B0);
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ5, 0x0, SHU_B1_DQ5_RG_ARPI_FB_B1);
+    vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD5, 0x0, SHU_CA_CMD5_RG_ARPI_FB_CA);
+
+
+    //Reserved bits usage, check with PHY owners
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ6, 0x0, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ6, 0x0, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1);
+    vIO32WriteFldMulti_All(DDRPHY_SHU_CA_CMD6, P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OFFSET_CLKIEN)
+                                        | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA));
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+
+    //IMP Tracking Init Settings
+    //Write (DRAMC _BASE+ 0x219) [31:0] = 32'h80080020//DDR3200 default
+    //SHU_IMPCAL1_IMPCAL_CHKCYCLE should > 12.5/MCK, 1:4 mode will disable imp tracking -> don't care
+    vIO32WriteFldMulti(DRAMC_REG_SHU_IMPCAL1, P_Fld(8, SHU_IMPCAL1_IMPCAL_CALICNT) | P_Fld(0x10, SHU_IMPCAL1_IMPCALCNT)
+                                            | P_Fld(4, SHU_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(1, SHU_IMPCAL1_IMPCALCNT_OPT)
+                                            | P_Fld((p->frequency * 25 / 8000) + 1, SHU_IMPCAL1_IMPCAL_CHKCYCLE));
+
+    //for _K_
+    vIO32WriteFldMulti(DRAMC_REG_SREFCTRL, P_Fld(0x1, SREFCTRL_SCSM_CGAR)
+                                            | P_Fld(0x1, SREFCTRL_SCARB_SM_CGAR)
+                                            | P_Fld(0x1, SREFCTRL_RDDQSOSC_CGAR)
+                                            | P_Fld(0x1, SREFCTRL_HMRRSEL_CGAR));
+    vIO32WriteFldAlign(DRAMC_REG_PRE_TDQSCK1, 0x1, PRE_TDQSCK1_TXUIPI_CAL_CGAR);
+    /* DVFS related, PREA interval counter (After DVFS DVT, set to 0xf (originally was 0x1f)) */
+    vIO32WriteFldAlign(DRAMC_REG_SHU_MISC, 0xf, SHU_MISC_PREA_INTV);
+    vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ8, P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)
+                                        | P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0)
+                                        | P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0)
+                                        | P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0)
+                                        | P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0)
+                                        | P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0)
+                                        | P_Fld(0x1, SHU_B0_DQ8_R_DMSTBEN_SYNC_CG_IG_B0)
+                                        | P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0)
+                                        | P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0)
+                                        | P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0)
+                                        | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0)
+                                        | P_Fld(0x7fff, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ8, P_Fld(0x1, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)
+                                        | P_Fld(0x1, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1)
+                                        | P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1)
+                                        | P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1)
+                                        | P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1)
+                                        | P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1)
+                                        | P_Fld(0x1, SHU_B1_DQ8_R_DMSTBEN_SYNC_CG_IG_B1)
+                                        | P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1)
+                                        | P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1)
+                                        | P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1)
+                                        | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1)
+                                        | P_Fld(0x7fff, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD8, P_Fld(0x1, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA)
+                                        | P_Fld(0x1, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA)
+                                        | P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA)
+                                        | P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA)
+                                        | P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA)
+                                        | P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA)
+                                        | P_Fld(0x1, SHU_CA_CMD8_R_DMSTBEN_SYNC_CG_IG_CA)
+                                        | P_Fld(0x1, SHU_CA_CMD8_R_DMRXDLY_CG_IG_CA)
+                                        | P_Fld(0x1, SHU_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA)
+                                        | P_Fld(0x1, SHU_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA)
+                                        | P_Fld(0x0, SHU_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA)
+                                        | P_Fld(0x7fff, SHU_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA));
+    vIO32WriteFldAlign(DDRPHY_MISC_CTRL3, 0x1, MISC_CTRL3_R_DDRPHY_COMB_CG_IG);
+    /* HW design issue: run-time PBYTE (B0, B1) flags will lose it's function and become per-bit -> set to 0 */
+    vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0)
+                                        | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0)
+                                        | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1)
+                                        | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1)
+                                        | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1));
+
+    vIO32WriteFldMulti(DRAMC_REG_CLKAR, P_Fld(0x1, CLKAR_SELPH_CMD_CG_DIS) | P_Fld(0x7FFF, CLKAR_REQQUE_PACG_DIS));
+
+    vIO32WriteFldAlign(DRAMC_REG_SHU_DQSG_RETRY, 0x0, SHU_DQSG_RETRY_R_RETRY_PA_DSIABLE); //SH: Set to 0 -> save power
+    vIO32WriteFldAlign(DRAMC_REG_WRITE_LEV, 0x0, WRITE_LEV_DDRPHY_COMB_CG_SEL);
+    vIO32WriteFldAlign(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DUMMY_RD_PA_OPT);
+    vIO32WriteFldMulti(DRAMC_REG_STBCAL2, P_Fld(0x0, STBCAL2_STB_UIDLYCG_IG)
+                                            | P_Fld(0x0, STBCAL2_STB_PIDLYCG_IG));
+    vIO32WriteFldMulti(DRAMC_REG_EYESCAN, P_Fld(0x1, EYESCAN_EYESCAN_DQS_SYNC_EN)
+                                            | P_Fld(0x1, EYESCAN_EYESCAN_NEW_DQ_SYNC_EN)
+                                            | P_Fld(0x1, EYESCAN_EYESCAN_DQ_SYNC_EN));
+    //vIO32WriteFldMulti(DRAMC_REG_SHU_ODTCTRL, P_Fld(0x1, SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG)
+    //                                        | P_Fld(0x1, SHU_ODTCTRL_RODTEN_SELPH_CG_IG));
+
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DLL0, 0x1, SHU_B0_DLL0_RG_ARPISM_MCK_SEL_B0_SHU);//Move to DCM off setting
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DLL0, 0x1, SHU_B1_DLL0_RG_ARPISM_MCK_SEL_B1_SHU);//Move to DCM off setting
+    //vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0, 0x1, SHU_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU); move to DramcSetting_Olympus_LP4_ByteMode()
+
+    vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI1, 0x1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA);
+
+    //end _K_
+
+    //DE_UPDATE
+    #if (fcFOR_CHIP_ID == fcLafite)
+    // Must check with EMI owners -> Asynchronous EMI: Can't turn on RWSPLIT, Synchronous EMI: Can enable RWSPLIT (DE: JL Wu)
+    vIO32WriteFldMulti(DRAMC_REG_PERFCTL0, P_Fld(0x1, PERFCTL0_WRFIFO_OPT)
+                                        | P_Fld(0x0, PERFCTL0_REORDEREN) // from Unique  review (it will remove)
+                                        | P_Fld(0x1, PERFCTL0_RWSPLIT)); //synchronous EMI -> can turn on RWSPLIT
+    #endif
+    vIO32WriteFldAlign(DRAMC_REG_SREFCTRL, 0x1, SREFCTRL_SREF2_OPTION);
+    vIO32WriteFldAlign(DRAMC_REG_SHUCTRL1, 0x1a, SHUCTRL1_FC_PRDCNT);
+
+#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
+    vIO32WriteFldMulti(DDRPHY_B0_DQ6, P_Fld(0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0)
+                                | P_Fld(0x1, B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0));
+    vIO32WriteFldMulti(DDRPHY_B1_DQ6, P_Fld(0x1, B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1)
+                                | P_Fld(0x1, B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1));
+    vIO32WriteFldMulti(DDRPHY_CA_CMD6, P_Fld(0x1, CA_CMD6_RG_RX_ARCMD_OP_BIAS_SW_EN)
+                                    | P_Fld(0x1, CA_CMD6_RG_RX_ARCMD_BIAS_EN));
+    vIO32WriteFldAlign(DRAMC_REG_STBCAL2, 0x1, STBCAL2_STB_PICG_EARLY_1T_EN);
+    vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)
+                                    | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0)
+                                    | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0)
+                                    | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)
+                                    | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1)
+                                    | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1)
+                                    | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1));
+#else
+    vIO32WriteFldMulti(DDRPHY_B0_DQ6, P_Fld(0x0, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0)
+                                | P_Fld(0x0, B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0));
+    vIO32WriteFldMulti(DDRPHY_B1_DQ6, P_Fld(0x0, B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1)
+                                | P_Fld(0x0, B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1));
+    vIO32WriteFldMulti(DDRPHY_CA_CMD6, P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_OP_BIAS_SW_EN)
+                                    | P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_BIAS_EN));
+#endif
+
+    //end DE UPDATE
+
+    //Disable RODT tracking
+    //vIO32WriteFldAlign(DRAMC_REG_SHU_RODTENSTB, 0, SHU_RODTENSTB_RODTENSTB_TRACK_EN);
+
+    //Rx Gating tracking settings
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSG), \
+                                                P_Fld(9, SHU_DQSG_STB_UPDMASKCYC) | \
+                                                P_Fld(1, SHU_DQSG_STB_UPDMASK_EN));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSCAL, P_Fld(0, SHURK0_DQSCAL_R0DQSIENLLMTEN) | P_Fld(0, SHURK0_DQSCAL_R0DQSIENHLMTEN));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSCAL, P_Fld(0, SHURK1_DQSCAL_R1DQSIENLLMTEN) | P_Fld(0, SHURK1_DQSCAL_R1DQSIENHLMTEN));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_STBCAL, P_Fld(1, SHU_STBCAL_DQSG_MODE)
+                                        | P_Fld(1, SHU_STBCAL_PICGLAT));
+
+#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
+    vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x4, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x4, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1);
+#else
+    //Modify for corner IC failed at HQA test XTLV
+    vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x7, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x7, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1);
+#endif
+    vIO32WriteFldAlign(DDRPHY_CA_CMD10, 0x0, CA_CMD10_R_IN_GATE_EN_LOW_OPT_CA);
+
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ8, 0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0);
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ8, 0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1);
+
+#ifdef DUMMY_READ_FOR_DQS_GATING_RETRY
+    if (p->support_rank_num == RANK_SINGLE)
+    {
+        vIO32WriteFldAlign(DRAMC_REG_SHU_DQSG_RETRY, 1, SHU_DQSG_RETRY_R_RETRY_1RANK);
+    }
+#endif
+
+
+    #if ENABLE_TX_WDQS
+    mcSHOW_DBG_MSG2(("Enable WDQS\n"));
+    //Check reserved bits with PHY integrator
+    vIO32WriteFldMulti(DDRPHY_SHU_B0_DLL1, P_Fld(1, SHU_B0_DLL1_RG_READ_BASE_DQS_EN_B0) | P_Fld(1, SHU_B0_DLL1_RG_READ_BASE_DQSB_EN_B0)
+                                        | P_Fld(!p->odt_onoff, SHU_B0_DLL1_RG_ODT_DISABLE_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_B1_DLL1, P_Fld(1, SHU_B1_DLL1_RG_READ_BASE_DQS_EN_B1) | P_Fld(1, SHU_B1_DLL1_RG_READ_BASE_DQSB_EN_B1)
+                                        | P_Fld(!p->odt_onoff, SHU_B1_DLL1_RG_ODT_DISABLE_B1));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ODTCTRL, P_Fld(0x1, SHU_ODTCTRL_RODTE)
+            | P_Fld(0x1, SHU_ODTCTRL_RODTE2)
+            | P_Fld(0x1, SHU_ODTCTRL_ROEN));
+
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x1, SHU_B0_DQ7_R_DMRODTEN_B0);
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x1, SHU_B1_DQ7_R_DMRODTEN_B1);
+    #if ENABLE_RODT_TRACKING_SAVE_MCK
+    SetTxWDQSStatusOnOff(1);
+    #endif
+
+    #else //WDQS and reak pull are disable
+    //Check reserved bits with PHY integrator
+    vIO32WriteFldMulti(DDRPHY_SHU_B0_DLL1, P_Fld(0, SHU_B0_DLL1_RG_READ_BASE_DQS_EN_B0) | P_Fld(0, SHU_B0_DLL1_RG_READ_BASE_DQSB_EN_B0)
+                                        | P_Fld(0, SHU_B0_DLL1_RG_ODT_DISABLE_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_B1_DLL1, P_Fld(0, SHU_B1_DLL1_RG_READ_BASE_DQS_EN_B1) | P_Fld(0, SHU_B1_DLL1_RG_READ_BASE_DQSB_EN_B1)
+                                        | P_Fld(0, SHU_B1_DLL1_RG_ODT_DISABLE_B1));
+    #endif
+
+
+    //DE review WhitneyE2
+    vIO32WriteFldAlign(DRAMC_REG_DRSCTRL, 0x1, DRSCTRL_DRS_SELFWAKE_DMYRD_DIS);
+    vIO32WriteFldAlign(DRAMC_REG_REFCTRL0, 0x1, REFCTRL0_REFNA_OPT);
+    vIO32WriteFldAlign(DRAMC_REG_ZQCS, 0x1, ZQCS_ZQCS_MASK_SEL_CGAR);//Move to DCM off setting
+    vIO32WriteFldMulti(DRAMC_REG_DUMMY_RD, P_Fld(0x1, DUMMY_RD_DMYRD_REORDER_DIS) | P_Fld(0x0, DUMMY_RD_DMYRD_HPRI_DIS)); //La_fite MP setting = 0
+    vIO32WriteFldAlign(DRAMC_REG_SHUCTRL2, 0x1, SHUCTRL2_R_DVFS_SREF_OPT);
+    vIO32WriteFldAlign(DRAMC_REG_SHUCTRL3, 0xb, SHUCTRL3_VRCGDIS_PRDCNT);
+    vIO32WriteFldAlign(DDRPHY_MISC_CTRL3, 0x1, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG);
+    //End
+
+    //DE review
+    /* ARPISM_MCK_SEL_B0, B1 set to 1 (Joe): "Due to TX_PICG modify register is set to 1,
+     * ARPISM_MCK_SEL_Bx should be 1 to fulfill APHY TX OE spec for low freq (Ex: DDR1600)"
+     */
+    vIO32WriteFldMulti(DDRPHY_B0_DLL_ARPI1, P_Fld(0x1, B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT)
+                                        | P_Fld(0x1, B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0));
+    vIO32WriteFldMulti(DDRPHY_B1_DLL_ARPI1, P_Fld(0x1, B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT)
+                                        | P_Fld(0x1, B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1));
+    vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI1, 0x1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT);//Move to DCM off setting
+    vIO32WriteFldAlign(DDRPHY_MISC_CTRL0, 0, MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF);//Move to DCM off setting
+
+    vIO32WriteFldAlign(DDRPHY_MISC_RXDVS2, 1, MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG);
+    vIO32WriteFldAlign(DRAMC_REG_CLKCTRL, 0x1, CLKCTRL_SEQCLKRUN3);
+    vIO32WriteFldAlign(DRAMC_REG_REFCTRL1, 1, REFCTRL1_SREF_CG_OPT);
+    vIO32WriteFldMulti(DRAMC_REG_SHUCTRL, P_Fld(0x0, SHUCTRL_DVFS_CG_OPT) | P_Fld(0x3, SHUCTRL_R_DVFS_PICG_MARGIN2) | P_Fld(0x3, SHUCTRL_R_DVFS_PICG_MARGIN3));//Move to DCM off setting(SHUCTRL_DVFS_CG_OPT)
+    //vIO32WriteFldMulti(DRAMC_REG_SHUCTRL, P_Fld(0x3, SHUCTRL_R_DVFS_PICG_MARGIN2) | P_Fld(0x3, SHUCTRL_R_DVFS_PICG_MARGIN3));
+    vIO32WriteFldMulti(DRAMC_REG_SHUCTRL2, P_Fld(0x1, SHUCTRL2_SHORTQ_OPT) | P_Fld(0x3, SHUCTRL2_R_DVFS_PICG_MARGIN));
+    vIO32WriteFldAlign(DRAMC_REG_STBCAL2, 0x0, STBCAL2_STB_DBG_EN);
+    vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK1, P_Fld(0x0, PRE_TDQSCK1_APHY_CG_OPT1) | P_Fld(0x0, PRE_TDQSCK1_SHU_PRELOAD_TX_HW));
+
+    #ifndef FIRST_BRING_UP
+    if (u2DFSGetHighestFreq(p) >= 1866)
+    #endif
+    {
+        //if product supports 3733, CLKAR_SELPH_4LCG_DIS always 1 else o, but if 1, comsume more power
+        vIO32WriteFldAlign(DRAMC_REG_CLKAR, 1, CLKAR_SELPH_4LCG_DIS);
+    }
+
+    #if TX_OE_EXTEND
+    UpdateTxOEN(p);
+    #endif
+
+    vIO32WriteFldAlign(DRAMC_REG_CKECTRL, 0x1, CKECTRL_CKEPBDIS);
+
+    vIO32WriteFldMulti(DDRPHY_CA_TX_MCK, P_Fld(0x1, CA_TX_MCK_R_DMRESET_FRPHY_OPT) | P_Fld(0xa, CA_TX_MCK_R_DMRESETB_DRVP_FRPHY) | P_Fld(0xa, CA_TX_MCK_R_DMRESETB_DRVN_FRPHY));
+
+    //Syl_via MP setting should set CKECTRL_CKELCKFIX as 0 to rollback to M17
+    //Ei_ger review by CF Chang
+    vIO32WriteFldAlign(DRAMC_REG_CKECTRL, 0x0, CKECTRL_CKELCKFIX);
+
+    //Gating error problem happened in M17 has been solved by setting this RG as 0 (when RODT tracking on (), TX DLY of byte2,3 must not be zero)
+    vIO32WriteFldAlign(DRAMC_REG_SHU_RODTENSTB, 0x0, SHU_RODTENSTB_RODTENSTB_4BYTE_EN);
+
+    #if (fcFOR_CHIP_ID == fcLafite) //RODT old mode
+    // RODT old mode (it must set SHU_RODTENSTB_RODTENSTB_TRACK_EN=1) from HJ review
+    vIO32WriteFldAlign(DRAMC_REG_SHU_ODTCTRL, 0x1, SHU_ODTCTRL_RODTEN_OPT);
+    vIO32WriteFldMulti(DRAMC_REG_SHU_RODTENSTB, P_Fld(0, SHU_RODTENSTB_RODTEN_P1_ENABLE)
+                                        | P_Fld(1, SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL)
+                                        | P_Fld(1, SHU_RODTENSTB_RODTENSTB_SELPH_MODE));
+    vIO32WriteFldAlign(DRAMC_REG_SHU_STBCAL, 0x0, SHU_STBCAL_DQSIEN_PICG_MODE);
+    #if ENABLE_RODT_TRACKING // The SHU_RODTENSTB_RODTENSTB_TRACK_EN will depend on SHU_ODTCTRL_ROEN setting
+    if (vGet_Div_Mode(p) == DIV4_MODE)
+        vIO32WriteFldAlign(DRAMC_REG_SHU_RODTENSTB, 0x21, SHU_RODTENSTB_RODTENSTB_OFFSET);
+    else
+        vIO32WriteFldAlign(DRAMC_REG_SHU_RODTENSTB, 0x11, SHU_RODTENSTB_RODTENSTB_OFFSET);
+    #endif
+
+    //Enable RODT tracking at Init, because RODT position should be changed with Gating position simultaneously
+    U8 u1ReadROEN;
+    u1ReadROEN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), SHU_ODTCTRL_ROEN);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_RODTENSTB), P_Fld(0xff, SHU_RODTENSTB_RODTENSTB_EXT) | \
+                                                                P_Fld(u1ReadROEN, SHU_RODTENSTB_RODTENSTB_TRACK_EN));
+    #endif
+
+    #if (fcFOR_CHIP_ID == fcLafite) //DDRPHY settings review from YH Cho
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ3, 0x0, SHU_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0);
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ3, 0x0, SHU_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1);
+    #endif
+
+    #if ENABLE_FIX_PRE8_DVFS_AT_CKEPRD
+    vIO32WriteFldAlign(DRAMC_REG_MISCTL0, 0x1, MISCTL0_PG_WAKEUP_OPT);
+    #endif
+
+#if ENABLE_TMRRI_NEW_MODE
+    //[DVT](1)dram auto refersh rate by hardware mr4 for rank0 and rank1; (2)After suspend resume, HW MR4 will be fire autoly (Berson)
+    vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, (p->support_rank_num == RANK_DUAL)? (1): (0), SPCMDCTRL_HMR4_TOG_OPT);
+#else
+    vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x0, SPCMDCTRL_HMR4_TOG_OPT);
+#endif
+
+#if RX_PICG_NEW_MODE
+    RXPICGSetting(p);
+#endif
+
+    //[DVT]RX FIFO debug feature, MP setting should enable debug function
+    vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x1, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x1, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1);
+
+    // E2 - new -start =========================================================================
+    //Design Review Meeting dramc_stbcal_cross rank read to read for new APHY spec - HJ Huang
+    vIO32WriteFldMulti(DDRPHY_B0_DQ9, P_Fld(4, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0));
+    vIO32WriteFldMulti(DDRPHY_B1_DQ9, P_Fld(4, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1));
+    vIO32WriteFldMulti(DDRPHY_CA_CMD10, P_Fld(0, CA_CMD10_R_IN_GATE_EN_LOW_OPT_CA) | P_Fld(0, CA_CMD10_R_DMRXDVS_R_F_DLY_RK_OPT));
+    vIO32WriteFldAlign(DDRPHY_MISC_CTRL3, 0x0, MISC_CTRL3_ARPI_CG_RK1_SRC_SEL);
+    vIO32WriteFldAlign(DRAMC_REG_SHU_RANK_SEL_STB, 0x1, SHU_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK);
+    vIO32WriteFldAlign(DRAMC_REG_SHU_RANK_SEL_STB, 0x0, SHU_RANK_SEL_STB_RANK_SEL_STB_SERMODE); // for old rank mode settings - HJ Huang
+
+    // Update VREF1/VREF2 per bit select - Ying-Yu Hsu
+    // Note: The RG (SHU_B1_DQ3_RG_TX_ARDQS0_PDB_B1) need update when using VREF2 per bit select
+    vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ3, P_Fld(0, SHU_B0_DQ3_RG_TX_ARDQS0_PDB_B0) | P_Fld(0, SHU_B0_DQ3_RG_TX_ARDQ_PDB_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ3, P_Fld(0, SHU_B1_DQ3_RG_TX_ARDQS0_PDB_B1) | P_Fld(0, SHU_B1_DQ3_RG_TX_ARDQ_PDB_B1));
+
+    // DQSI DLY 3B in FIFO for adjustmen by YingMin
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, 0x4, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0);
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ5, 0x4, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1);
+
+#if ENABLE_REMOVE_MCK8X_UNCERT_LOWPOWER_OPTION
+    vIO32WriteFldAlign(DDRPHY_MISC_VREF_CTRL, 0x7F, MISC_VREF_CTRL_MISC_LP_8X_MUX); // @Mazar: MCK8X uncertainty remove
+    vIO32WriteFldAlign(DDRPHY_MISC_VREF_CTRL, 0x7F, MISC_VREF_CTRL_MISC_LP_DDR400_MUX); // @Mazar: open loop mode setting(found connection problem in CHB in DSIM)
+#endif
+
+#if ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION
+    vIO32WriteFldAlign(DDRPHY_DVFS_EMI_CLK, 1, DVFS_EMI_CLK_R_DDRPHY_SHUFFLE_MUX_ENABLE); // @Lynx
+    vIO32WriteFldAlign(DRAMC_REG_DVFSDLL2, 1, DVFSDLL2_R_SHUFFLE_PI_RESET_ENABLE); // @Lynx
+    vIO32WriteFldAlign(DRAMC_REG_DVFSDLL2, 3, DVFSDLL2_R_DVFS_MCK8X_MARGIN); // @Lynx
+
+    vIO32WriteFldAlign(DDRPHY_B0_DLL_ARPI0, 1, B0_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B0); // @YY
+    vIO32WriteFldAlign(DDRPHY_B1_DLL_ARPI0, 1, B1_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B1); // @YY
+    vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI0, 1, CA_DLL_ARPI0_RG_ARPI_MCK8X_SEL_CA); // @YY
+
+    vIO32WriteFldAlign(DRAMC_REG_DVFSDLL2, 3, DVFSDLL2_R_DVFS_PICG_MARGIN4_NEW); // @Lynx
+#endif
+
+    vIO32WriteFldAlign(DDRPHY_SHU_MISC1, 0x00000020, SHU_MISC1_DR_EMI_RESERVE); // @TK, For EMI slice timing
+
+    //@Ton, DQS retry off
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG_RETRY, P_Fld(0x0, SHU_DQSG_RETRY_R_RETRY_USE_BURST_MDOE)
+                | P_Fld(0x0, SHU_DQSG_RETRY_R_RDY_SEL_DLE)
+                | P_Fld(0x0, SHU_DQSG_RETRY_R_DQSIENLAT)
+                | P_Fld(0x0, SHU_DQSG_RETRY_R_RETRY_ROUND_NUM)
+                | P_Fld(0x0, SHU_DQSG_RETRY_R_RETRY_ONCE));
+
+    vIO32WriteFldAlign(DRAMC_REG_PRE_TDQSCK1, 0x1, PRE_TDQSCK1_TX_TRACKING_OPT); //@Jouling
+
+    //@Berson, NOTE: Please set to 1 when DVT is verified. SPMFW must updated by DVT owner.
+    vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_SPDR_MR4_OPT); //S0 from suspend to resume trigger HW MR4
+
+    //@YY, APHY init settings review
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ6, 0x0, SHU_B0_DQ6_RG_ARPI_OFFSET_MCTL_B0);
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ6, 0x0, SHU_B1_DQ6_RG_ARPI_OFFSET_MCTL_B1);
+    vIO32WriteFldAlign(DDRPHY_CA_CMD5, 0x29, CA_CMD5_RG_RX_ARCMD_EYE_VREF_SEL);
+    vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD5, 0x4, SHU_CA_CMD5_RG_RX_ARCMD_FIFO_DQSI_DLY);
+    // E2 - new -end =========================================================================
+
+    #if CMD_CKE_WORKAROUND_FIX
+    CMD_CKE_Modified_txp_Setting(p);
+    #endif
+
+    #if RX_PIPE_BYPASS_ENABLE
+    vIO32WriteFldAlign(DDRPHY_SHU_MISC0, 0x1, SHU_MISC0_R_RX_PIPE_BYPASS_EN);
+    #endif
+
+    #if CBT_MOVE_CA_INSTEAD_OF_CLK
+    if (u1IsPhaseMode(p) == FALSE)
+    {
+        u1CaUI = 0;
+        u1CaPI = 32;
+    }
+    else
+    {
+        u1CaUI = 0;
+        u1CaPI = 24;
+    }
+    // CA delay shift u1CaUI*UI
+    DramcCmdUIDelaySetting(p, u1CaUI);
+
+    // Rank0/1 u1CaPI*PI CA delay
+
+    u1RankIdxBak = u1GetRank(p);
+
+    for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+
+        CBTDelayCACLK(p, u1CaPI);
+    }
+
+    vSetRank(p, u1RankIdxBak);
+    #endif
+
+    //Reset XRTRTR related setting
+    #if XRTRTR_NEW_CROSS_RK_MODE
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ6, 0, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0);
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ6, 0, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1);
+    vIO32WriteFldAlign(DRAMC_REG_SHU_RANK_SEL_STB, 0, SHU_RANK_SEL_STB_RANK_SEL_STB_EN);
+    #endif
+
+
+    //Update MP setting
+    vIO32WriteFldAlign(DRAMC_REG_DRSCTRL, 0x1, DRSCTRL_DRSCLR_RK0_EN); //Jouling
+    vIO32WriteFldMulti(DRAMC_REG_STBCAL2, P_Fld(0x7, STBCAL2_STBCAL_UI_UPD_MASK_OPT)
+                                         |P_Fld(0x1, STBCAL2_STBCAL_UI_UPD_MASK_EN)); //HJ, Gating tracking
+    #if XRTRTR_NEW_CROSS_RK_MODE
+    vIO32WriteFldMulti(DRAMC_REG_SHU_PHY_RX_CTRL, P_Fld(0x2, SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET)
+                                         |P_Fld(0x2, SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET)
+                                         |P_Fld(0x1, SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN)); //HJ, R2R
+    #endif
+
+#endif// #if __A60868_TO_BE_PORTING__
+    return DRAM_OK;
+}
+#endif
+#if __A60868_TO_BE_PORTING__
+#if LEGACY_DELAY_CELL
+/* Legacy CA, TX DQ, TX DQM delay cell initial settings
+ * RK#_TX_ARCA#_DLY (RK0~2, CA0~5), RK#_TX_ARDQ#_DLY_B# (RK0~2, DQ0~8, B0~1), RK#_TX_ARDQM0_DLY_B# (RK0~2, B0~1)
+ */
+static void LegacyDlyCellInitLP4_DDR2667(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ0, P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0)
+                | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0)
+                | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0)
+                | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0)
+                | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0)
+                | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0)
+                | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0)
+                | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0));
+    vIO32WriteFldAlign(DDRPHY_SHU_R1_B0_DQ1, 0xa, SHU_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0);
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ0, P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1)
+                | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1)
+                | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1)
+                | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1)
+                | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1)
+                | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1)
+                | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1)
+                | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1));
+    vIO32WriteFldAlign(DDRPHY_SHU_R1_B1_DQ1, 0xa, SHU_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1);
+}
+
+static void LegacyDlyCellInitLP4_DDR1600(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ0, P_Fld(0xd, SHU_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0)
+                | P_Fld(0xd, SHU_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0)
+                | P_Fld(0xd, SHU_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0)
+                | P_Fld(0xd, SHU_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0)
+                | P_Fld(0xd, SHU_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0)
+                | P_Fld(0xd, SHU_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0)
+                | P_Fld(0xd, SHU_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0)
+                | P_Fld(0xd, SHU_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0));
+    vIO32WriteFldAlign(DDRPHY_SHU_R1_B0_DQ1, 0xd, SHU_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0);
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ0, P_Fld(0xd, SHU_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1)
+                | P_Fld(0xd, SHU_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1)
+                | P_Fld(0xd, SHU_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1)
+                | P_Fld(0xd, SHU_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1)
+                | P_Fld(0xd, SHU_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1)
+                | P_Fld(0xd, SHU_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1)
+                | P_Fld(0xd, SHU_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1)
+                | P_Fld(0xd, SHU_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1));
+    vIO32WriteFldAlign(DDRPHY_SHU_R1_B1_DQ1, 0xd, SHU_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1);
+}
+
+static void LegacyDlyCellInitLP4_DDR3200(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ0, P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0)
+                | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0)
+                | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0)
+                | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0)
+                | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0)
+                | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0)
+                | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0)
+                | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0));
+    vIO32WriteFldAlign(DDRPHY_SHU_R1_B0_DQ1, 0xa, SHU_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0);
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ0, P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1)
+                | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1)
+                | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1)
+                | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1)
+                | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1)
+                | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1)
+                | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1)
+                | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1));
+    vIO32WriteFldAlign(DDRPHY_SHU_R1_B1_DQ1, 0xa, SHU_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1);
+}
+#endif
+
+#if LEGACY_TX_TRACK
+/* Legacy tx tracking related initial settings (actual correct values are set during calibration steps)
+ * BOOT_ORIG_UI_RK#_DQ#, BOOT_TARG_UI_RK#_DQ#, BOOT_TARG_UI_RK#_DQM#, BOOT_TARG_UI_RK#_OEN_DQ#, BOOT_TARG_UI_RK#_OEN_DQM#
+ * DQSOSCTHRD_DEC, DQSOSCTHRD_INC, DQSOSC_PRDCNT
+ * DQSOSC_BASE_RK#, DQSOSCR_RK#_BYTE_MODE, DQSOSCR_DQSOSCRCNT
+ */
+static void LegacyTxTrackLP4_DDR2667(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCTHRD, P_Fld(0xc, SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0)
+                | P_Fld(0xc, SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0)
+                | P_Fld(0xc, SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_PRD, P_Fld(0xc, SHU_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1)
+                | P_Fld(0x0, SHU_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8)
+                | P_Fld(0x10, SHU_DQSOSC_PRD_DQSOSC_PRDCNT));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSOSC, P_Fld(0x1ae, SHURK0_DQSOSC_DQSOSC_BASE_RK0_B1)
+                | P_Fld(0x1ae, SHURK0_DQSOSC_DQSOSC_BASE_RK0));
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL1, P_Fld(0x354, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)
+                    | P_Fld(0x354, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL2, P_Fld(0x354, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)
+                    | P_Fld(0x354, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL1, P_Fld(0x254, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)
+                    | P_Fld(0x254, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL2, P_Fld(0x254, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)
+                    | P_Fld(0x254, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0));
+    }
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL3, P_Fld(0x14, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0)
+                | P_Fld(0x14, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0)
+                | P_Fld(0x18, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1)
+                | P_Fld(0x18, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL4, P_Fld(0x14, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0)
+                | P_Fld(0x14, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0)
+                | P_Fld(0x18, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1)
+                | P_Fld(0x18, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0));
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL5, P_Fld(0x354, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)
+                    | P_Fld(0x354, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL5, P_Fld(0x254, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)
+                    | P_Fld(0x254, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0));
+    }
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSOSC, P_Fld(0x160, SHURK1_DQSOSC_DQSOSC_BASE_RK1_B1)
+                | P_Fld(0x160, SHURK1_DQSOSC_DQSOSC_BASE_RK1));
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL1, P_Fld(0x354, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1)
+                    | P_Fld(0x354, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL2, P_Fld(0x354, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1)
+                    | P_Fld(0x354, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL1, P_Fld(0x254, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1)
+                    | P_Fld(0x254, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL2, P_Fld(0x254, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1)
+                    | P_Fld(0x254, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0));
+    }
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL3, P_Fld(0x14, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1_B4TO0)
+                | P_Fld(0x14, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0_B4TO0)
+                | P_Fld(0x18, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1)
+                | P_Fld(0x18, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL4, P_Fld(0x14, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1_B4TO0)
+                | P_Fld(0x14, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0_B4TO0)
+                | P_Fld(0x18, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1)
+                | P_Fld(0x18, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0));
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL5, P_Fld(0x354, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1)
+                    | P_Fld(0x354, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL5, P_Fld(0x254, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1)
+                    | P_Fld(0x254, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0));
+    }
+}
+
+static void LegacyTxTrackLP4_DDR1600(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCTHRD, P_Fld(0x14, SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0)
+                | P_Fld(0x14, SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0)
+                | P_Fld(0x14, SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_PRD, P_Fld(0x14, SHU_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1)
+                | P_Fld(0x0, SHU_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8)
+                | P_Fld(0xf, SHU_DQSOSC_PRD_DQSOSC_PRDCNT));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSOSC, P_Fld(0x2d0, SHURK0_DQSOSC_DQSOSC_BASE_RK0_B1)
+                | P_Fld(0x2d0, SHURK0_DQSOSC_DQSOSC_BASE_RK0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL1, P_Fld(0x23a, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)
+                | P_Fld(0x23a, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL2, P_Fld(0x23a, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)
+                | P_Fld(0x23a, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL3, P_Fld(0x1a, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0)
+                | P_Fld(0x1a, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0)
+                | P_Fld(0xf, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1)
+                | P_Fld(0xf, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL4, P_Fld(0x1a, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0)
+                | P_Fld(0x1a, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0)
+                | P_Fld(0xf, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1)
+                | P_Fld(0xf, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL5, P_Fld(0x23e, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)
+                | P_Fld(0x23e, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSOSC, P_Fld(0x24e, SHURK1_DQSOSC_DQSOSC_BASE_RK1_B1)
+                | P_Fld(0x24e, SHURK1_DQSOSC_DQSOSC_BASE_RK1));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL1, P_Fld(0x23e, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1)
+                | P_Fld(0x23e, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL2, P_Fld(0x23e, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1)
+                | P_Fld(0x23e, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL3, P_Fld(0x1e, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1_B4TO0)
+                | P_Fld(0x1e, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0_B4TO0)
+                | P_Fld(0xf, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1)
+                | P_Fld(0xf, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL4, P_Fld(0x1e, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1_B4TO0)
+                | P_Fld(0x1e, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0_B4TO0)
+                | P_Fld(0xf, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1)
+                | P_Fld(0xf, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL5, P_Fld(0x23e, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1)
+                | P_Fld(0x23e, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0));
+}
+
+static void LegacyTxTrackLP4_DDR3200(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCTHRD, P_Fld(0xa, SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0)
+                | P_Fld(0xa, SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0)
+                | P_Fld(0xa, SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_PRD, P_Fld(0xa, SHU_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1)
+                | P_Fld(0x0, SHU_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8)
+                | P_Fld(0x10, SHU_DQSOSC_PRD_DQSOSC_PRDCNT));
+    vIO32WriteFldAlign(DRAMC_REG_SHU_DQSOSCR, 0x10, SHU_DQSOSCR_DQSOSCRCNT);
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSOSC, P_Fld(0x168, SHURK0_DQSOSC_DQSOSC_BASE_RK0_B1)
+                | P_Fld(0x168, SHURK0_DQSOSC_DQSOSC_BASE_RK0));
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL1, P_Fld(0x3da, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)
+                        | P_Fld(0x3da, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL2, P_Fld(0x3da, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)
+                        | P_Fld(0x3da, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0));
+    }
+    else
+    {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL1, P_Fld(0x2da, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)
+                        | P_Fld(0x2da, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL2, P_Fld(0x2da, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)
+                        | P_Fld(0x2da, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0));
+    }
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL3, P_Fld(0x1a, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0)
+                | P_Fld(0x1a, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0)
+                | P_Fld(0x1c, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1)
+                | P_Fld(0x1c, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL4, P_Fld(0x1a, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0)
+                | P_Fld(0x1a, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0)
+                | P_Fld(0x1c, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1)
+                | P_Fld(0x1c, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0));
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL5, P_Fld(0x3da, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)
+                        | P_Fld(0x3da, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0));
+    }
+    else
+    {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL5, P_Fld(0x2da, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)
+                        | P_Fld(0x2da, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0));
+    }
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSOSC, P_Fld(0x127, SHURK1_DQSOSC_DQSOSC_BASE_RK1_B1)
+                | P_Fld(0x127, SHURK1_DQSOSC_DQSOSC_BASE_RK1));
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL1, P_Fld(0x3d4, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1)
+                        | P_Fld(0x3d4, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL2, P_Fld(0x3d4, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1)
+                        | P_Fld(0x3d4, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0));
+    }
+    else
+    {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL1, P_Fld(0x2d4, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1)
+                        | P_Fld(0x2d4, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL2, P_Fld(0x2d4, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1)
+                        | P_Fld(0x2d4, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0));
+    }
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL3, P_Fld(0x14, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1_B4TO0)
+                | P_Fld(0x14, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0_B4TO0)
+                | P_Fld(0x1c, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1)
+                | P_Fld(0x1c, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL4, P_Fld(0x14, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1_B4TO0)
+                | P_Fld(0x14, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0_B4TO0)
+                | P_Fld(0x1c, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1)
+                | P_Fld(0x1c, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0));
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL5, P_Fld(0x3d4, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1)
+                        | P_Fld(0x3d4, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0));
+    }
+    else
+    {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL5, P_Fld(0x2d4, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1)
+                        | P_Fld(0x2d4, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0));
+    }
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        vIO32WriteFldAlign(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_RK0_BYTE_MODE);
+        vIO32WriteFldAlign(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_RK1_BYTE_MODE);
+    }
+}
+#endif
+
+#if LEGACY_TDQSCK_PRECAL
+/* Legacy tDQSCK precal related initial settings (actual correct values are set during calibration)
+ * Ex: TDQSCK_JUMP_RATIO, TDQSCK_UIFREQ#, TDQSCK_PIFREQ#
+ */
+static void LegacyPreCalLP4_DDR2667(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK2, P_Fld(0x1a, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO0)
+                | P_Fld(0x10, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO1)
+                | P_Fld(0x0, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO2)
+                | P_Fld(0x26, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO3));
+    vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK3, P_Fld(0x13, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO4)
+                | P_Fld(0x0, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO5)
+                | P_Fld(0x40, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO6)
+                | P_Fld(0x35, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO7));
+    vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK4, P_Fld(0x0, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO8)
+                | P_Fld(0x0, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO9)
+                | P_Fld(0x0, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO10)
+                | P_Fld(0x0, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO11));
+    vIO32WriteFldAlign(DRAMC_REG_RK0_PRE_TDQSCK1, 0xa, RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0);
+    vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK2, P_Fld(0x0, RK0_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R0)
+                | P_Fld(0x0, RK0_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R0)
+                | P_Fld(0xb, RK0_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R0)
+                | P_Fld(0xd, RK0_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R0));
+    vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK3, P_Fld(0x0, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R0)
+                | P_Fld(0x11, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0)
+                | P_Fld(0xe, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0));
+    vIO32WriteFldAlign(DRAMC_REG_RK0_PRE_TDQSCK4, 0xa, RK0_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R0);
+    vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK5, P_Fld(0x0, RK0_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R0)
+                | P_Fld(0x0, RK0_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R0)
+                | P_Fld(0xb, RK0_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R0)
+                | P_Fld(0xd, RK0_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R0));
+    vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK6, P_Fld(0x0, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R0)
+                | P_Fld(0x11, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R0)
+                | P_Fld(0xe, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R0));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK1, P_Fld(0x8, RK1_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R1)
+                | P_Fld(0x10, RK1_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R1));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK2, P_Fld(0x0, RK1_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R1)
+                | P_Fld(0x0, RK1_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R1)
+                | P_Fld(0xe, RK1_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R1)
+                | P_Fld(0x10, RK1_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R1));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK3, P_Fld(0x0, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R1)
+                | P_Fld(0x14, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R1)
+                | P_Fld(0x14, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R1));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK4, P_Fld(0x8, RK1_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R1)
+                | P_Fld(0x10, RK1_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R1));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK5, P_Fld(0x0, RK1_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R1)
+                | P_Fld(0x0, RK1_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R1)
+                | P_Fld(0xe, RK1_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R1)
+                | P_Fld(0x10, RK1_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R1));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK6, P_Fld(0x0, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R1)
+                | P_Fld(0x14, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R1)
+                | P_Fld(0x14, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R1));
+}
+
+static void LegacyPreCalLP4_DDR1600(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK2, P_Fld(0x1a, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO0)
+                | P_Fld(0x10, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO1)
+                | P_Fld(0x0, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO2)
+                | P_Fld(0x26, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO3));
+    vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK3, P_Fld(0x13, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO4)
+                | P_Fld(0x0, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO5)
+                | P_Fld(0x40, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO6)
+                | P_Fld(0x35, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO7));
+    vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK4, P_Fld(0x0, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO8)
+                | P_Fld(0x0, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO9)
+                | P_Fld(0x0, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO10)
+                | P_Fld(0x0, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO11));
+    vIO32WriteFldAlign(DRAMC_REG_RK0_PRE_TDQSCK1, 0xa, RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0);
+    vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK2, P_Fld(0x0, RK0_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R0)
+                | P_Fld(0x0, RK0_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R0)
+                | P_Fld(0xb, RK0_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R0)
+                | P_Fld(0xd, RK0_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R0));
+    vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK3, P_Fld(0x0, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R0)
+                | P_Fld(0x11, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0)
+                | P_Fld(0xe, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0));
+    vIO32WriteFldAlign(DRAMC_REG_RK0_PRE_TDQSCK4, 0xa, RK0_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R0);
+    vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK5, P_Fld(0x0, RK0_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R0)
+                | P_Fld(0x0, RK0_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R0)
+                | P_Fld(0xb, RK0_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R0)
+                | P_Fld(0xd, RK0_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R0));
+    vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK6, P_Fld(0x0, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R0)
+                | P_Fld(0x11, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R0)
+                | P_Fld(0xe, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R0));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK1, P_Fld(0x8, RK1_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R1)
+                | P_Fld(0x10, RK1_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R1));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK2, P_Fld(0x0, RK1_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R1)
+                | P_Fld(0x0, RK1_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R1)
+                | P_Fld(0xe, RK1_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R1)
+                | P_Fld(0x10, RK1_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R1));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK3, P_Fld(0x0, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R1)
+                | P_Fld(0x14, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R1)
+                | P_Fld(0x14, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R1));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK4, P_Fld(0x8, RK1_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R1)
+                | P_Fld(0x10, RK1_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R1));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK5, P_Fld(0x0, RK1_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R1)
+                | P_Fld(0x0, RK1_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R1)
+                | P_Fld(0xe, RK1_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R1)
+                | P_Fld(0x10, RK1_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R1));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK6, P_Fld(0x0, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R1)
+                | P_Fld(0x14, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R1)
+                | P_Fld(0x14, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R1));
+}
+
+static void LegacyPreCalLP4_DDR3200(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK2, P_Fld(0x25, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO0)
+                | P_Fld(0x18, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO1)
+                | P_Fld(0x10, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO2)
+                | P_Fld(0x1b, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO3));
+    vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK3, P_Fld(0x14, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO4)
+                | P_Fld(0xd, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO5)
+                | P_Fld(0x2a, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO6)
+                | P_Fld(0x31, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO7));
+    vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK4, P_Fld(0x15, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO8)
+                | P_Fld(0x40, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO9)
+                | P_Fld(0x4a, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO10)
+                | P_Fld(0x30, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO11));
+    vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK1, P_Fld(0x1a, RK0_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R0)
+                | P_Fld(0x1c, RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0)
+                | P_Fld(0x14, RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0));
+    vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK2, P_Fld(0xb, RK0_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R0)
+                | P_Fld(0xd, RK0_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R0)
+                | P_Fld(0x10, RK0_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R0)
+                | P_Fld(0xa, RK0_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R0));
+    vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK3, P_Fld(0x11, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R0)
+                | P_Fld(0xe, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0)
+                | P_Fld(0x20, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0)
+                | P_Fld(0x18, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0));
+    vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK4, P_Fld(0x1a, RK0_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R0)
+                | P_Fld(0x1c, RK0_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R0)
+                | P_Fld(0x14, RK0_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R0));
+    vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK5, P_Fld(0xb, RK0_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R0)
+                | P_Fld(0xd, RK0_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R0)
+                | P_Fld(0x10, RK0_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R0)
+                | P_Fld(0xa, RK0_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R0));
+    vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK6, P_Fld(0x11, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R0)
+                | P_Fld(0xe, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R0)
+                | P_Fld(0x20, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R0)
+                | P_Fld(0x18, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R0));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK1, P_Fld(0xb, RK1_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R1)
+                | P_Fld(0x23, RK1_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R1)
+                | P_Fld(0xf, RK1_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R1)
+                | P_Fld(0x19, RK1_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R1));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK2, P_Fld(0xe, RK1_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R1)
+                | P_Fld(0x10, RK1_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R1)
+                | P_Fld(0x1f, RK1_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R1)
+                | P_Fld(0xe, RK1_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R1));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK3, P_Fld(0x14, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R1)
+                | P_Fld(0x12, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R1)
+                | P_Fld(0x27, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R1)
+                | P_Fld(0x1d, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R1));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK4, P_Fld(0xb, RK1_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R1)
+                | P_Fld(0x23, RK1_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R1)
+                | P_Fld(0xf, RK1_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R1)
+                | P_Fld(0x19, RK1_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R1));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK5, P_Fld(0xe, RK1_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R1)
+                | P_Fld(0x10, RK1_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R1)
+                | P_Fld(0x1f, RK1_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R1)
+                | P_Fld(0xe, RK1_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R1));
+    vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK6, P_Fld(0x14, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R1)
+                | P_Fld(0x12, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R1)
+                | P_Fld(0x27, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R1)
+                | P_Fld(0x1d, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R1));
+}
+#endif
+
+#if LEGACY_GATING_DLY
+/* Legacy initial settings (actual correct values are set during gating calibration)
+ * Ex: TX_DLY_DQS#_GATED, TX_DLY_DQS#_GATED_P1, REG_DLY_DQS#_GATED, REG_DLY_DQS#_GATED_P1
+ *     TXDLY_B#_RODTEN, TXDLY_B#_RODTEN_P1, DLY_B#_RODTEN, DLY_B#_RODTEN_P1
+ */
+static void LegacyGatingDlyLP3(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN0, P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN_P1)
+                | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN)
+                | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN_P1)
+                | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN)
+                | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1)
+                | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN)
+                | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1)
+                | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN1, P_Fld(0x4, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1)
+                | P_Fld(0x4, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN)
+                | P_Fld(0x4, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1)
+                | P_Fld(0x4, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN)
+                | P_Fld(0x4, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1)
+                | P_Fld(0x4, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN)
+                | P_Fld(0x4, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1)
+                | P_Fld(0x4, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN0, P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1)
+                | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN)
+                | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1)
+                | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN)
+                | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1)
+                | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN)
+                | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1)
+                | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN1, P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1)
+                | P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN)
+                | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1)
+                | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN)
+                | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1)
+                | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN)
+                | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1)
+                | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(0x4, SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1)
+                | P_Fld(0x2, SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED)
+                | P_Fld(0x4, SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1)
+                | P_Fld(0x2, SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED)
+                | P_Fld(0x4, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
+                | P_Fld(0x2, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
+                | P_Fld(0x4, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
+                | P_Fld(0x2, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(0x2, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED_P1)
+                | P_Fld(0x1, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED)
+                | P_Fld(0x2, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED_P1)
+                | P_Fld(0x1, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED)
+                | P_Fld(0x2, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
+                | P_Fld(0x1, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
+                | P_Fld(0x2, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
+                | P_Fld(0x1, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED_P1)
+                | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED)
+                | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED_P1)
+                | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED)
+                | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
+                | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
+                | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
+                | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0 + SHIFT_TO_CHB_ADDR, P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1 + SHIFT_TO_CHB_ADDR, P_Fld(0x3, SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED)
+                | P_Fld(0x3, SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED)
+                | P_Fld(0x3, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
+                | P_Fld(0x3, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
+                | P_Fld(0x1, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0 + SHIFT_TO_CHB_ADDR, P_Fld(0x2, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED_P1)
+                | P_Fld(0x1, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED)
+                | P_Fld(0x2, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED_P1)
+                | P_Fld(0x1, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED)
+                | P_Fld(0x2, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
+                | P_Fld(0x1, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
+                | P_Fld(0x2, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
+                | P_Fld(0x1, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1 + SHIFT_TO_CHB_ADDR, P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED_P1)
+                | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED)
+                | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED_P1)
+                | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED)
+                | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
+                | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
+                | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
+                | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
+}
+
+static void LegacyGatingDlyLP4_DDR800(DRAMC_CTX_T *p)
+{
+
+    U8 ucR0GatingMCK = 0, ucR0GatingB0UI = 0, ucR0GatingB1UI = 0;
+    U8 ucR0GatingP1MCK = 0, ucR0GatingB0P1UI = 0, ucR0GatingB1P1UI = 0;
+
+    U8 ucR1GatingMCK = 0, ucR1GatingB0UI = 0, ucR1GatingB1UI = 0;
+    U8 ucR1GatingP1MCK = 0, ucR1GatingB0P1UI = 0, ucR1GatingB1P1UI = 0;
+
+    U8 ucR0GatingB0PI = 0, ucR0GatingB1PI = 0;
+    U8 ucR1GatingB0PI = 0, ucR1GatingB1PI = 0;
+
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        // Byte mode don't use. need fine-tune for DV sim for DDR800
+        //RK0
+        ucR0GatingMCK = 0x2;
+        ucR0GatingP1MCK = 0x2;
+        ucR0GatingB0UI = 0x2;
+        ucR0GatingB1UI = 0x2;
+        ucR0GatingB0P1UI = 0x6;
+        ucR0GatingB1P1UI = 0x6;
+        //RK1
+        ucR1GatingMCK = 0x2;
+        ucR1GatingP1MCK = 0x3;
+        ucR1GatingB0UI = 0x5;
+        ucR1GatingB1UI = 0x5;
+        ucR1GatingB0P1UI = 0x1;
+        ucR1GatingB1P1UI = 0x1;
+    }
+    else
+    {
+        //RK0
+        ucR0GatingMCK = 0x1;
+        ucR0GatingP1MCK = 0x1;
+        ucR0GatingB0UI = 0x4;
+        ucR0GatingB1UI = 0x4;
+        ucR0GatingB0P1UI = 0x6;
+        ucR0GatingB1P1UI = 0x6;
+        //RK1
+        ucR1GatingMCK = 0x1;
+        ucR1GatingP1MCK = 0x1;
+        ucR1GatingB0UI = 0x5;
+        ucR1GatingB1UI = 0x5;
+        ucR1GatingB0P1UI = 0x7;
+        ucR1GatingB1P1UI = 0x7;
+    }
+
+    //Gating PI
+    if (vGet_DDR800_Mode(p) == DDR800_CLOSE_LOOP)
+    {
+        ucR0GatingB0PI = 0xc;
+        ucR0GatingB1PI = 0xe;
+        ucR1GatingB0PI = 0x1e;
+        ucR1GatingB1PI = 0x1e;
+    }
+    else
+    {
+        // DDR800_SEMI_LOOP and DDR800_OPEN_LOOP
+        ucR0GatingB0PI = 0x0;
+        ucR0GatingB1PI = 0x0;
+        ucR1GatingB0PI = 0x0;
+        ucR1GatingB1PI = 0x0;
+    }
+
+    //Gating RK0 MCK
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
+                | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
+                | P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
+                | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
+    //Gating RK0 UI
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(ucR0GatingB1P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
+                | P_Fld(ucR0GatingB1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
+                | P_Fld(ucR0GatingB0P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
+                | P_Fld(ucR0GatingB0UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
+
+    //Gating RK1 MCK
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
+                | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
+                | P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
+                | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
+    //Gating RK1 UI
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(ucR1GatingB1P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
+                | P_Fld(ucR1GatingB1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
+                | P_Fld(ucR1GatingB0P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
+                | P_Fld(ucR1GatingB0UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
+
+    //Gating RK0 PI
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSIEN, P_Fld(ucR0GatingB1PI, SHURK0_DQSIEN_R0DQS1IEN)
+                | P_Fld(ucR0GatingB0PI, SHURK0_DQSIEN_R0DQS0IEN));
+    //Gating RK1 PI
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(ucR1GatingB1PI, SHURK1_DQSIEN_R1DQS1IEN)
+                | P_Fld(ucR1GatingB0PI, SHURK1_DQSIEN_R1DQS0IEN));
+}
+
+
+static void LegacyGatingDlyLP4_DDR1600(DRAMC_CTX_T *p)
+{
+    U8 ucR0GatingMCK = 0, ucR0GatingB0UI = 0, ucR0GatingB1UI = 0;
+    U8 ucR0GatingP1MCK = 0, ucR0GatingB0P1UI = 0, ucR0GatingB1P1UI = 0;
+
+    U8 ucR1GatingMCK = 0, ucR1GatingB0UI = 0, ucR1GatingB1UI = 0;
+    U8 ucR1GatingP1MCK = 0, ucR1GatingB0P1UI = 0, ucR1GatingB1P1UI = 0;
+
+    U8 ucR0GatingB0PI = 0, ucR0GatingB1PI = 0;
+    U8 ucR1GatingB0PI = 0, ucR1GatingB1PI = 0;
+
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        // DV sim mix mode = RK0_BYTE and RK1_NORMAL
+        if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) // DV sim mixed mode
+        {
+            //RK0
+            ucR0GatingMCK = 0x2;
+            ucR0GatingP1MCK = 0x2;
+            ucR0GatingB0UI = 0x0;
+            ucR0GatingB1UI = 0x0;
+            ucR0GatingB0P1UI = 0x4;
+            ucR0GatingB1P1UI = 0x4;
+            //RK1
+            ucR1GatingMCK = 0x2;
+            ucR1GatingP1MCK = 0x2;
+            ucR1GatingB0UI = 0x3;
+            ucR1GatingB1UI = 0x2;
+            ucR1GatingB0P1UI = 0x7;
+            ucR1GatingB1P1UI = 0x6;
+        }
+        else
+        {
+            //RK0
+            ucR0GatingMCK = 0x2;
+            ucR0GatingP1MCK = 0x2;
+            ucR0GatingB0UI = 0x0;
+            ucR0GatingB1UI = 0x1;
+            ucR0GatingB0P1UI = 0x4;
+            ucR0GatingB1P1UI = 0x5;
+            //RK1
+            ucR1GatingMCK = 0x1;
+            ucR1GatingP1MCK = 0x2;
+            ucR1GatingB0UI = 0x7;
+            ucR1GatingB1UI = 0x7;
+            ucR1GatingB0P1UI = 0x3;
+            ucR1GatingB1P1UI = 0x3;
+        }
+    }
+    else
+    {
+        // Normal mode DRAM
+        //Normal mode dram, B0/1 tDQSCK = 1.5ns
+        //Byte/Mix mode dram, B0 tDQSCK = 1.5ns, B1 tDQSCK = 1.95ns
+        //RK1, tDQSCK=3.5ns
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+        {
+            //RK0
+            ucR0GatingMCK = 0x1;
+            ucR0GatingP1MCK = 0x1;
+            ucR0GatingB0UI = 0x4;
+            ucR0GatingB1UI = 0x4;
+            ucR0GatingB0P1UI = 0x6;
+            ucR0GatingB1P1UI = 0x6;
+            //RK1
+            ucR1GatingMCK = 0x1;
+            ucR1GatingP1MCK = 0x2;
+            ucR1GatingB0UI = 0x7;
+            ucR1GatingB1UI = 0x7;
+            ucR1GatingB0P1UI = 0x1;
+            ucR1GatingB1P1UI = 0x1;
+        }
+        else
+        {
+            //RK0
+            ucR0GatingMCK = 0x2;
+            ucR0GatingP1MCK = 0x3;
+            ucR0GatingB0UI = 0x4;
+            ucR0GatingB1UI = 0x4;
+            ucR0GatingB0P1UI = 0x0;
+            ucR0GatingB1P1UI = 0x0;
+            //RK1
+            ucR1GatingMCK = 0x2;
+            ucR1GatingP1MCK = 0x3;
+            ucR1GatingB0UI = 0x7;
+            ucR1GatingB1UI = 0x7;
+            ucR1GatingB0P1UI = 0x3;
+            ucR1GatingB1P1UI = 0x3;
+        }
+    }
+
+    //Gating PI
+    if (vGet_Div_Mode(p) == DIV4_MODE)
+    {
+        ucR0GatingB0PI = 0xb;
+        ucR0GatingB1PI = 0x0;
+        ucR1GatingB0PI = 0x1;
+        ucR1GatingB1PI = 0x1;
+    }
+    else
+    {
+        // for DDR1600 1:8 mode
+        if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+        {
+            if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_BYTE_MODE1)) // RK1 gating for byte mode
+            {
+                ucR0GatingB0PI = 0xa;
+                ucR0GatingB1PI = 0x0;
+                ucR1GatingB0PI = 0xc;
+                ucR1GatingB1PI = 0x16;
+            }
+            else if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) // DV sim mixed mode
+            {
+                ucR0GatingB0PI = 0xa;
+                ucR0GatingB1PI = 0x1e;
+                ucR1GatingB0PI = 0xc;
+                ucR1GatingB1PI = 0xc;
+            }
+            else //RK0: normal and RK1: byte
+            {
+                ucR0GatingB0PI = 0xa;
+                ucR0GatingB1PI = 0x0;
+                ucR1GatingB0PI = 0xc;
+                ucR1GatingB1PI = 0xc;
+
+            }
+        }
+        else
+        {
+            ucR0GatingB0PI = 0x0;
+            ucR0GatingB1PI = 0x0;
+            ucR1GatingB0PI = 0x0;
+            ucR1GatingB1PI = 0x0;
+        }
+    }
+
+    //Gating RK0 MCK
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
+                | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
+                | P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
+                | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
+    //Gating RK0 UI
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(ucR0GatingB1P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
+                | P_Fld(ucR0GatingB1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
+                | P_Fld(ucR0GatingB0P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
+                | P_Fld(ucR0GatingB0UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
+
+    //Gating RK1 MCK
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
+                | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
+                | P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
+                | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
+    //Gating RK1 UI
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(ucR1GatingB1P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
+                | P_Fld(ucR1GatingB1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
+                | P_Fld(ucR1GatingB0P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
+                | P_Fld(ucR1GatingB0UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
+
+    //Gating RK0 PI
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSIEN, P_Fld(ucR0GatingB1PI, SHURK0_DQSIEN_R0DQS1IEN)
+                | P_Fld(ucR0GatingB0PI, SHURK0_DQSIEN_R0DQS0IEN));
+    //Gating RK1 PI
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(ucR1GatingB1PI, SHURK1_DQSIEN_R1DQS1IEN)
+                | P_Fld(ucR1GatingB0PI, SHURK1_DQSIEN_R1DQS0IEN));
+}
+
+static void LegacyGatingDlyLP4_DDR2667(DRAMC_CTX_T *p)
+{
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+       vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN0, P_Fld(0x1, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1)
+                    | P_Fld(0x1, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN)
+                    | P_Fld(0x1, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1)
+                    | P_Fld(0x1, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN1, P_Fld(0x1, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1)
+                    | P_Fld(0x1, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN)
+                    | P_Fld(0x1, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1)
+                    | P_Fld(0x1, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(0x2, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
+                    | P_Fld(0x2, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
+                    | P_Fld(0x2, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
+                    | P_Fld(0x2, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(0x6, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
+                    | P_Fld(0x2, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
+                    | P_Fld(0x6, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
+                    | P_Fld(0x2, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN0, P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1)
+                    | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN)
+                    | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1)
+                    | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN1, P_Fld(0x1, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1)
+                    | P_Fld(0x1, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN)
+                    | P_Fld(0x1, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1)
+                    | P_Fld(0x1, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN));
+
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
+                    | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
+                    | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
+                    | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(0x4, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
+                    | P_Fld(0x0, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
+                    | P_Fld(0x4, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
+                    | P_Fld(0x0, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
+    }
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN0, P_Fld(0x1, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1)
+                    | P_Fld(0x1, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN)
+                    | P_Fld(0x1, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1)
+                    | P_Fld(0x1, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN1, P_Fld(0x6, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1)
+                    | P_Fld(0x6, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN)
+                    | P_Fld(0x6, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1)
+                    | P_Fld(0x6, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
+                    | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
+                    | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
+                    | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN0, P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN1, P_Fld(0x6, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1)
+                    | P_Fld(0x6, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN)
+                    | P_Fld(0x6, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1)
+                    | P_Fld(0x6, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
+                    | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
+                    | P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
+                    | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
+    }
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(0x2, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
+                | P_Fld(0x6, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
+                | P_Fld(0x2, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
+                | P_Fld(0x6, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
+}
+
+static void LegacyGatingDlyLP4_DDR3200(DRAMC_CTX_T *p)
+{
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN1, P_Fld(0x2, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1)
+                    | P_Fld(0x2, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN)
+                    | P_Fld(0x2, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1)
+                    | P_Fld(0x2, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN)
+                    | P_Fld(0x6, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1)
+                    | P_Fld(0x6, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN)
+                    | P_Fld(0x6, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1)
+                    | P_Fld(0x6, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN0, P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN1, P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1)
+                    | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN)
+                    | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1)
+                    | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN1, P_Fld(0x2, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1)
+                    | P_Fld(0x2, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN)
+                    | P_Fld(0x2, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1)
+                    | P_Fld(0x2, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN0, P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN1, P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1)
+                    | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN)
+                    | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1)
+                    | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN)
+                    | P_Fld(0x7, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1)
+                    | P_Fld(0x7, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN)
+                    | P_Fld(0x7, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1)
+                    | P_Fld(0x7, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN));
+    }
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(0x4, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
+                    | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
+                    | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
+                    | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(0x4, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
+                    | P_Fld(0x7, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
+                    | P_Fld(0x3, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
+                    | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
+                    | P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
+                    | P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(0x3, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
+                    | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
+                    | P_Fld(0x5, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
+                    | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(0x2, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
+                    | P_Fld(0x2, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
+                    | P_Fld(0x2, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
+                    | P_Fld(0x2, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(0x6, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
+                    | P_Fld(0x2, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
+                    | P_Fld(0x6, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
+                    | P_Fld(0x2, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
+                    | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
+                    | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
+                    | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(0x4, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
+                    | P_Fld(0x4, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1));
+    }
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
+                    | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
+                    | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
+                    | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
+                    | P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
+                    | P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
+                    | P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN0, P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN)
+                    | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN0, P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN)
+                    | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN));
+    }
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN0, P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN_P1)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN_P1)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN)
+                        | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1)
+                        | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN)
+                        | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1)
+                        | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN1, P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN));
+            vIO32WriteFldAlign(DRAMC_REG_SHURK0_SELPH_DQSG0, 0x4, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1);
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(0x1, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
+                        | P_Fld(0x5, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
+                        | P_Fld(0x0, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
+                        | P_Fld(0x4, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
+    }
+    else
+    {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN0, P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN_P1)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN_P1)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN)
+                        | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1)
+                        | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN1, P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1)
+                        | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(0x7, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
+                        | P_Fld(0x3, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
+                        | P_Fld(0x7, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
+                        | P_Fld(0x3, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
+    }
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN0, P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1)
+                        | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN)
+                        | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1)
+                        | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN));
+    }
+    else
+    {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN0, P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1)
+                        | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN)
+                        | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1)
+                        | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN)
+                        | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1)
+                        | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1));
+    }
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN1, P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1)
+                | P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN)
+                | P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1)
+                | P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN)
+                | P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1)
+                | P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN)
+                | P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1)
+                | P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN));
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+            vIO32WriteFldAlign(DRAMC_REG_SHURK1_SELPH_DQSG0, 0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED);
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(0x4, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
+                        | P_Fld(0x0, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
+                        | P_Fld(0x6, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
+                        | P_Fld(0x2, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
+    }
+    else
+    {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(0x5, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
+                        | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
+                        | P_Fld(0x5, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
+                        | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
+    }
+}
+
+static void LegacyGatingDlyLP4_DDR3733(DRAMC_CTX_T *p)
+{
+    U8 ucR0GatingMCK = 0, ucR0GatingB0UI = 0, ucR0GatingB1UI = 0;
+    U8 ucR1GatingMCK = 0, ucR1GatingB0UI = 0, ucR1GatingB1UI = 0;
+
+    U8 ucR0GatingP1MCK = 0, ucR0GatingB0P1UI = 0, ucR0GatingB1P1UI = 0;
+    U8 ucR1GatingP1MCK = 0, ucR1GatingB0P1UI = 0, ucR1GatingB1P1UI = 0;
+
+    U8 ucR0GatingB0PI = 0, ucR0GatingB1PI = 0;
+    U8 ucR1GatingB0PI = 0, ucR1GatingB1PI = 0;
+
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        // Byte mode don't use. need fine-tune for DV sim
+        //RK0
+        ucR0GatingMCK = 0x3;
+        ucR0GatingP1MCK = 0x3;
+        ucR0GatingB0UI = 0x3;
+        ucR0GatingB1UI = 0x3;
+        ucR0GatingB0P1UI = 0x7;
+        ucR0GatingB1P1UI = 0x7;
+        ucR0GatingB0PI = 0x14;
+        ucR0GatingB1PI = 0x14;
+        //RK1
+        ucR1GatingMCK = 0x4;
+        ucR1GatingP1MCK = 0x4;
+        ucR1GatingB0UI = 0x4;
+        ucR1GatingB1UI = 0x4;
+        ucR1GatingB0P1UI = 0x7;
+        ucR1GatingB1P1UI = 0x7;
+        ucR1GatingB0PI = 0x4;
+        ucR1GatingB1PI = 0x4;
+    }
+    else
+    {
+        //RK0
+        //Normal mode dram, B0/1 tDQSCK = 1.5ns
+        //Byte/Mix mode dram, B0 tDQSCK = 1.5ns, B1 tDQSCK = 1.95ns
+        ucR0GatingMCK = 0x2;
+        ucR0GatingP1MCK = 0x2;
+        ucR0GatingB0UI = 0x3;
+        ucR0GatingB1UI = 0x3;
+        ucR0GatingB0P1UI = 0x7;
+        ucR0GatingB1P1UI = 0x7;
+        ucR0GatingB0PI = 0x11;
+        ucR0GatingB1PI = 0x11;
+        //RK1, tDQSCK=3.5ns
+        ucR1GatingMCK = 0x3;
+        ucR1GatingP1MCK = 0x3;
+        ucR1GatingB0UI = 0x2;
+        ucR1GatingB1UI = 0x2;
+        ucR1GatingB0P1UI = 0x6;
+        ucR1GatingB1P1UI = 0x6;
+        ucR1GatingB0PI = 0x1f;
+        ucR1GatingB1PI = 0x1f;
+    }
+
+    #if ENABLE_READ_DBI
+    ucR0GatingMCK++;
+    ucR0GatingP1MCK++;
+    ucR1GatingMCK++;
+    ucR1GatingP1MCK++;
+    #endif
+
+    //Gating RK0 MCK
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
+                | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
+                | P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
+                | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
+    //Gating RK0 UI
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(ucR0GatingB1P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
+                | P_Fld(ucR0GatingB1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
+                | P_Fld(ucR0GatingB0P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
+                | P_Fld(ucR0GatingB0UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
+
+    //Gating RK1 MCK
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
+                | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
+                | P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
+                | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
+    //Gating RK1 UI
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(ucR1GatingB1P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
+                | P_Fld(ucR1GatingB1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
+                | P_Fld(ucR1GatingB0P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
+                | P_Fld(ucR1GatingB0UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
+
+    //Gating RK0 PI
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSIEN, P_Fld(0x0, SHURK0_DQSIEN_R0DQS3IEN)
+                | P_Fld(0x0, SHURK0_DQSIEN_R0DQS2IEN)
+                | P_Fld(ucR0GatingB1PI, SHURK0_DQSIEN_R0DQS1IEN)
+                | P_Fld(ucR0GatingB0PI, SHURK0_DQSIEN_R0DQS0IEN));
+
+    //Gating RK1 PI
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(0x0, SHURK1_DQSIEN_R1DQS3IEN)
+                | P_Fld(0x0, SHURK1_DQSIEN_R1DQS2IEN)
+                | P_Fld(ucR1GatingB1PI, SHURK1_DQSIEN_R1DQS1IEN)
+                | P_Fld(ucR1GatingB0PI, SHURK1_DQSIEN_R1DQS0IEN));
+}
+
+#endif //LEGACY_GATING_DLY
+
+#if LEGACY_RX_DLY
+/* Legacy RX related delay initial settings:
+ * RK#_RX_ARDQ#_F_DLY_B#, RK#_RX_ARDQ#_R_DLY_B# (DQ Rx per bit falling/rising edge delay line control)
+ * RK#_RX_ARDQS#_F_DLY_B#, RK#_RX_ARDQS#_R_DLY_B# (DQS RX per bit falling/rising edge delay line control)
+ * RK#_RX_ARDQM#_F_DLY_B#, RK#_RX_ARDQM#_R_DLY_B# (DQM RX per bit falling/rising edge delay line control)
+ * TODO: Channel B's PHY, seems to be all used for LP3's DQ, DQS, DQM -> LP3's Channel B RX CA, CKE etc.. delay should be regarded as RX_DLY?
+ */
+static void LegacyRxDly_LP4_DDR2667(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ2, P_Fld(0xa, SHU_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0)
+                | P_Fld(0xa, SHU_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ3, P_Fld(0xa, SHU_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0)
+                | P_Fld(0xa, SHU_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ4, P_Fld(0xa, SHU_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0)
+                | P_Fld(0xa, SHU_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ5, P_Fld(0xa, SHU_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0)
+                | P_Fld(0xa, SHU_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ6, P_Fld(0x15, SHU_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0)
+                | P_Fld(0xa, SHU_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ2, P_Fld(0xa, SHU_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1)
+                | P_Fld(0xa, SHU_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ3, P_Fld(0xa, SHU_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1)
+                | P_Fld(0xa, SHU_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ4, P_Fld(0xa, SHU_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1)
+                | P_Fld(0xa, SHU_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ5, P_Fld(0xa, SHU_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1)
+                | P_Fld(0xa, SHU_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ6, P_Fld(0x15, SHU_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1)
+                | P_Fld(0xa, SHU_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ2, P_Fld(0xb, SHU_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0)
+                | P_Fld(0xb, SHU_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ3, P_Fld(0xb, SHU_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0)
+                | P_Fld(0xb, SHU_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ4, P_Fld(0xb, SHU_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0)
+                | P_Fld(0xb, SHU_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ5, P_Fld(0xb, SHU_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0)
+                | P_Fld(0xb, SHU_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ6, P_Fld(0x16, SHU_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0)
+                | P_Fld(0xb, SHU_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ2, P_Fld(0xb, SHU_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1)
+                | P_Fld(0xb, SHU_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ3, P_Fld(0xb, SHU_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1)
+                | P_Fld(0xb, SHU_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ4, P_Fld(0xb, SHU_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1)
+                | P_Fld(0xb, SHU_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ5, P_Fld(0xb, SHU_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1)
+                | P_Fld(0xb, SHU_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ6, P_Fld(0x16, SHU_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1)
+                | P_Fld(0xb, SHU_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1));
+}
+
+static void LegacyRxDly_LP4_DDR800(DRAMC_CTX_T *p)
+{
+    U8 u1Dq = 0x0;
+    U8 u1Dqm = 0x0;
+    U8 u1Dqs = 0x26;
+
+    //RK0_B0
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ2, P_Fld(u1Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0)
+                | P_Fld(u1Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ3, P_Fld(u1Dq, SHU_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0)
+                | P_Fld(u1Dq, SHU_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ4, P_Fld(u1Dq, SHU_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0)
+                | P_Fld(u1Dq, SHU_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ5, P_Fld(u1Dq, SHU_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0)
+                | P_Fld(u1Dq, SHU_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ6, P_Fld(u1Dqs, SHU_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0)
+                | P_Fld(u1Dqm, SHU_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0));
+    //RK0_B1
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ2, P_Fld(u1Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1)
+                | P_Fld(u1Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ3, P_Fld(u1Dq, SHU_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1)
+                | P_Fld(u1Dq, SHU_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ4, P_Fld(u1Dq, SHU_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1)
+                | P_Fld(u1Dq, SHU_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ5, P_Fld(u1Dq, SHU_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1)
+                | P_Fld(u1Dq, SHU_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ6, P_Fld(u1Dqs, SHU_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1)
+                | P_Fld(u1Dqm, SHU_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1));
+    //RK1_B0
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ2, P_Fld(u1Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0)
+                | P_Fld(u1Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ3, P_Fld(u1Dq, SHU_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0)
+                | P_Fld(u1Dq, SHU_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ4, P_Fld(u1Dq, SHU_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0)
+                | P_Fld(u1Dq, SHU_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ5, P_Fld(u1Dq, SHU_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0)
+                | P_Fld(u1Dq, SHU_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ6, P_Fld(u1Dqs, SHU_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0)
+                | P_Fld(u1Dqm, SHU_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0));
+    //RK1_B1
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ2, P_Fld(u1Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1)
+                | P_Fld(u1Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ3, P_Fld(u1Dq, SHU_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1)
+                | P_Fld(u1Dq, SHU_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ4, P_Fld(u1Dq, SHU_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1)
+                | P_Fld(u1Dq, SHU_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ5, P_Fld(u1Dq, SHU_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1)
+                | P_Fld(u1Dq, SHU_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ6, P_Fld(u1Dqs, SHU_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1)
+                | P_Fld(u1Dqm, SHU_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1));
+}
+
+static void LegacyRxDly_LP4_DDR1600(DRAMC_CTX_T *p)
+{
+    U8 u1Rk0_Dq, u1Rk0_Dq5_6;
+    U8 u1Rk0_Dqm;
+    U8 u1Rk0_Dqs;
+    U8 u1Rk1_Dq;
+    U8 u1Rk1_Dqm;
+    U8 u1Rk1_Dqs;
+
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        u1Rk0_Dq = 0x0;
+        u1Rk0_Dq5_6 = 0x2;
+        u1Rk0_Dqm = 0x0;
+        u1Rk0_Dqs = 0x7;
+        u1Rk1_Dq = 0x0;
+        u1Rk1_Dqm = 0x0;
+        u1Rk1_Dqs = 0x5;
+    }
+    else
+    {
+        u1Rk0_Dq = 0x4;
+        u1Rk0_Dq5_6 = 0x4;
+        u1Rk0_Dqm = 0x4;
+        u1Rk0_Dqs = 0x15;
+        u1Rk1_Dq = 0x5;
+        u1Rk1_Dqm = 0x5;
+        u1Rk1_Dqs = 0x16;
+    }
+
+    //RK0_B0
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ2, P_Fld(u1Rk0_Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0)
+                | P_Fld(u1Rk0_Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ3, P_Fld(u1Rk0_Dq, SHU_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0)
+                | P_Fld(u1Rk0_Dq, SHU_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ4, P_Fld(u1Rk0_Dq5_6, SHU_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0)
+                | P_Fld(u1Rk0_Dq, SHU_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ5, P_Fld(u1Rk0_Dq, SHU_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0)
+                | P_Fld(u1Rk0_Dq5_6, SHU_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ6, P_Fld(u1Rk0_Dqs, SHU_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0)
+                | P_Fld(u1Rk0_Dqm, SHU_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0));
+    //RK0_B1
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ2, P_Fld(u1Rk0_Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1)
+                | P_Fld(u1Rk0_Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ3, P_Fld(u1Rk0_Dq, SHU_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1)
+                | P_Fld(u1Rk0_Dq, SHU_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ4, P_Fld(u1Rk0_Dq5_6, SHU_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1)
+                | P_Fld(u1Rk0_Dq, SHU_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ5, P_Fld(u1Rk0_Dq, SHU_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1)
+                | P_Fld(u1Rk0_Dq5_6, SHU_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ6, P_Fld(u1Rk0_Dqs, SHU_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1)
+                | P_Fld(u1Rk0_Dqm, SHU_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1));
+    //RK1_B0
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ2, P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0)
+                | P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ3, P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0)
+                | P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ4, P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0)
+                | P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ5, P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0)
+                | P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ6, P_Fld(u1Rk1_Dqs, SHU_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0)
+                | P_Fld(u1Rk1_Dqm, SHU_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0));
+    //RK1_B1
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ2, P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1)
+                | P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ3, P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1)
+                | P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ4, P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1)
+                | P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ5, P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1)
+                | P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ6, P_Fld(u1Rk1_Dqs, SHU_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1)
+                | P_Fld(u1Rk1_Dqm, SHU_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1));
+}
+
+static void LegacyRxDly_LP4_DDR3200(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ2, P_Fld(0xa, SHU_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0)
+                | P_Fld(0xa, SHU_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ3, P_Fld(0xa, SHU_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0)
+                | P_Fld(0xa, SHU_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ4, P_Fld(0xa, SHU_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0)
+                | P_Fld(0xa, SHU_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ5, P_Fld(0xa, SHU_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0)
+                | P_Fld(0xa, SHU_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ6, P_Fld(0xc, SHU_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0)
+                | P_Fld(0xa, SHU_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ2, P_Fld(0xb, SHU_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0)
+                | P_Fld(0xb, SHU_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ3, P_Fld(0xb, SHU_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0)
+                | P_Fld(0xb, SHU_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ4, P_Fld(0xb, SHU_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0)
+                | P_Fld(0xb, SHU_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ5, P_Fld(0xb, SHU_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0)
+                | P_Fld(0xb, SHU_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ6, P_Fld(0xd, SHU_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0)
+                | P_Fld(0xb, SHU_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ2, P_Fld(0xa, SHU_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1)
+                | P_Fld(0xa, SHU_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ3, P_Fld(0xa, SHU_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1)
+                | P_Fld(0xa, SHU_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ4, P_Fld(0xa, SHU_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1)
+                | P_Fld(0xa, SHU_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ5, P_Fld(0xa, SHU_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1)
+                | P_Fld(0xa, SHU_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ6, P_Fld(0xc, SHU_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1)
+                | P_Fld(0xa, SHU_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ2, P_Fld(0xb, SHU_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1)
+                | P_Fld(0xb, SHU_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ3, P_Fld(0xb, SHU_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1)
+                | P_Fld(0xb, SHU_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ4, P_Fld(0xb, SHU_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1)
+                | P_Fld(0xb, SHU_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ5, P_Fld(0xb, SHU_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1)
+                | P_Fld(0xb, SHU_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ6, P_Fld(0xd, SHU_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1)
+                | P_Fld(0xb, SHU_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1));
+}
+
+static void LegacyRxDly_LP4_DDR3733(DRAMC_CTX_T *p)
+{
+    U8 u1Dq = 0xf;
+    U8 u1Dqm = 0xf;
+    U8 u1Dqs = 0x0;
+
+    //RK0_B0
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ2, P_Fld(u1Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0)
+                | P_Fld(u1Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ3, P_Fld(u1Dq, SHU_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0)
+                | P_Fld(u1Dq, SHU_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ4, P_Fld(u1Dq, SHU_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0)
+                | P_Fld(u1Dq, SHU_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ5, P_Fld(u1Dq, SHU_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0)
+                | P_Fld(u1Dq, SHU_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ6, P_Fld(u1Dqs, SHU_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0)
+                | P_Fld(u1Dqm, SHU_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0));
+    //RK1_B0
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ2, P_Fld(u1Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0)
+                | P_Fld(u1Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ3, P_Fld(u1Dq, SHU_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0)
+                | P_Fld(u1Dq, SHU_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ4, P_Fld(u1Dq, SHU_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0)
+                | P_Fld(u1Dq, SHU_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ5, P_Fld(u1Dq, SHU_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0)
+                | P_Fld(u1Dq, SHU_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ6, P_Fld(u1Dqs, SHU_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0)
+                | P_Fld(u1Dqm, SHU_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0));
+    //RK0_B1
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ2, P_Fld(u1Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1)
+                | P_Fld(u1Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ3, P_Fld(u1Dq, SHU_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1)
+                | P_Fld(u1Dq, SHU_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ4, P_Fld(u1Dq, SHU_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1)
+                | P_Fld(u1Dq, SHU_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ5, P_Fld(u1Dq, SHU_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1)
+                | P_Fld(u1Dq, SHU_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ6, P_Fld(u1Dqs, SHU_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1)
+                | P_Fld(u1Dqm, SHU_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1));
+    //RK1_B1
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ2, P_Fld(u1Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1)
+                | P_Fld(u1Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ3, P_Fld(u1Dq, SHU_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1)
+                | P_Fld(u1Dq, SHU_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ4, P_Fld(u1Dq, SHU_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1)
+                | P_Fld(u1Dq, SHU_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ5, P_Fld(u1Dq, SHU_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1)
+                | P_Fld(u1Dq, SHU_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ6, P_Fld(u1Dqs, SHU_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1)
+                | P_Fld(u1Dqm, SHU_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1));
+}
+
+#endif //LEGACY_RX_DLY
+
+#if LEGACY_DAT_LAT
+static void LegacyDatlatLP4_DDR3733(DRAMC_CTX_T *p)
+{
+    // set by DramcRxdqsGatingPostProcess
+#if 0
+    vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x7, SHU_RANKCTL_RANKINCTL_PHY)
+                | P_Fld(0x5, SHU_RANKCTL_RANKINCTL_ROOT1)
+                | P_Fld(0x5, SHU_RANKCTL_RANKINCTL));
+#endif
+
+    // DATLAT init by AcTiming Table
+    /*vIO32WriteFldMulti(DRAMC_REG_SHU_CONF1, P_Fld(0x11, SHU_CONF1_DATLAT)
+                 | P_Fld(0xf, SHU_CONF1_DATLAT_DSEL)
+                 | P_Fld(0xf, SHU_CONF1_DATLAT_DSEL_PHY));*/
+
+    //DATLAT 1:8 mode DDR3733
+    vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_DIV2_OPT)
+                | P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_LOBYTE_OPT)
+                | P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_HIBYTE_OPT));
+
+    //RDATA PIPE from Ton
+    vIO32WriteFldMulti(DRAMC_REG_SHU_PIPE, P_Fld(0x1, SHU_PIPE_READ_START_EXTEND1)
+                | P_Fld(0x1, SHU_PIPE_DLE_LAST_EXTEND1)
+                | P_Fld(0x1, SHU_PIPE_READ_START_EXTEND2)
+                | P_Fld(0x1, SHU_PIPE_DLE_LAST_EXTEND2)
+                | P_Fld(0x0, SHU_PIPE_READ_START_EXTEND3)
+                | P_Fld(0x0, SHU_PIPE_DLE_LAST_EXTEND3));
+}
+#endif
+#endif  //__A60868_TO_BE_PORTING__
+
+#if __A60868_TO_BE_PORTING__
+static void DramcSetting_LP4_TX_Delay_DDR3733(DRAMC_CTX_T *p, DRAM_RANK_T eRank)
+{
+    U8 ucR0TxdlyOendq = 0, ucR0Txdlydq = 0;
+    U8 ucR1TxdlyOendq = 0, ucR1Txdlydq = 0;
+
+    if (eRank == RANK_0)
+    {
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+        {
+            ucR0TxdlyOendq = 0x3; // don't use
+            ucR0Txdlydq = 0x4; // don't use
+        }
+        else
+        {
+            ucR0TxdlyOendq = 0x3;
+            ucR0Txdlydq = 0x4;
+        }
+
+        if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+        {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ3)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ2)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ1)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM3)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM2)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM1)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM0));
+        }
+        else
+        {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ3)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ2)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ1)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM3)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM2)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM1)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM0));
+        }
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+        {
+            ucR0TxdlyOendq = 0x2; //don't use
+            ucR0Txdlydq = 0x1; //don't use
+        }
+        else
+        {
+            ucR0TxdlyOendq = 0x7; // TX OE -3UI
+            ucR0Txdlydq = 0x2;
+        }
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ3)
+                    | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ2)
+                    | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ1)
+                    | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ0)
+                    | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ2_DLY_DQ3)
+                    | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ2_DLY_DQ2)
+                    | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ2_DLY_DQ1)
+                    | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ2_DLY_DQ0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ3, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ3_DLY_OEN_DQM3)
+                    | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ3_DLY_OEN_DQM2)
+                    | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ3_DLY_OEN_DQM1)
+                    | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ3_DLY_OEN_DQM0)
+                    | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM3)
+                    | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM2)
+                    | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM1)
+                    | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM0));
+    }
+    else //RANK_1
+    {
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+        {
+            ucR1TxdlyOendq = 0x3; //don't use
+            ucR1Txdlydq = 0x4; //don't use
+        }
+        else
+        {
+            ucR1TxdlyOendq = 0x4;
+            ucR1Txdlydq = 0x4;
+        }
+        if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+        {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
+        }
+        else
+        {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
+        }
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+        {
+            ucR1TxdlyOendq = 0x3; //don't use
+            ucR1Txdlydq = 0x2; //don't use
+        }
+        else
+        {
+            ucR1TxdlyOendq = 0x0;
+            ucR1Txdlydq = 0x3;
+        }
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ2, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3)
+                    | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2)
+                    | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1)
+                    | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0)
+                    | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ2_DLY_R1DQ3)
+                    | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ2_DLY_R1DQ2)
+                    | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ2_DLY_R1DQ1)
+                    | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ2_DLY_R1DQ0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ3, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3)
+                    | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2)
+                    | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1)
+                    | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0)
+                    | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ3_DLY_R1DQM3)
+                    | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ3_DLY_R1DQM2)
+                    | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ3_DLY_R1DQM1)
+                    | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ3_DLY_R1DQM0));
+    }
+}
+
+static void DramcSetting_Olympus_LP4_ByteMode_DDR4266(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)
+                | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS2)
+                | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS1)
+                | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS0)
+                | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS3)
+                | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS2)
+                | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1)
+                | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS3)
+                | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS2)
+                | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS1)
+                | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS0)
+                | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS3)
+                | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS2)
+                | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS1)
+                | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS0));
+}
+
+static void DramcSetting_Olympus_LP4_ByteMode_DDR3733(DRAMC_CTX_T *p)
+{
+    DramcSetting_LP4_TX_Delay_DDR3733(p, RANK_0); // TX DQ/DQM MCK/UI
+    DramcSetting_LP4_TX_Delay_DDR3733(p, RANK_1); // TX DQ/DQM MCK/UI
+    // TX DQ/DQM PI
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(0xe, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0)
+                | P_Fld(0x13, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(0xe, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1)
+                | P_Fld(0x13, SHU_R0_B1_DQ7_RK0_ARPI_DQ_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ7, P_Fld(0x19, SHU_R1_B0_DQ7_RK1_ARPI_DQM_B0)
+                | P_Fld(0x22, SHU_R1_B0_DQ7_RK1_ARPI_DQ_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ7, P_Fld(0x19, SHU_R1_B1_DQ7_RK1_ARPI_DQM_B1)
+                | P_Fld(0x22, SHU_R1_B1_DQ7_RK1_ARPI_DQ_B1));
+
+    //TX DQS MCK by WriteLeveling
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)
+                | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS2)
+                | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS1)
+                | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS0)
+                | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS3)
+                | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS2)
+                | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1)
+                | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0));
+    //TX DQS UI by WriteLeveling
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS3)
+                | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS2)
+                | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS1)
+                | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS0)
+                | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3)
+                | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2)
+                | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS1)
+                | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS0));
+
+#if LEGACY_GATING_DLY
+    /*vIO32WriteFldMulti(DRAMC_REG_SHU_PHY_RX_CTRL, P_Fld(0x1, SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN)
+                | P_Fld(0x2, SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET)
+                | P_Fld(0x2, SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET)
+                | P_Fld(0x1, SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD)
+                | P_Fld(0x0, SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL)
+                | P_Fld(0x2, SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD)
+                | P_Fld(0x0, SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));*/
+
+    LegacyGatingDlyLP4_DDR3733(p);
+#endif
+
+#if LEGACY_RX_DLY
+    LegacyRxDly_LP4_DDR3733(p);
+#endif
+
+
+#if LEGACY_DAT_LAT // TODO: Darren
+    LegacyDatlatLP4_DDR3733(p);
+#endif
+}
+
+
+static void DramcSetting_Olympus_LP4_ByteMode_DDR2667(DRAMC_CTX_T *p)
+{
+    ////DRAMC0-SHU2
+#if LEGACY_TDQSCK_PRECAL
+    LegacyPreCalLP4_DDR2667(p);
+#endif
+    //vIO32WriteFldAlign(DRAMC_REG_SHU_CONF2, 0x54, SHU_CONF2_FSPCHG_PRDCNT);//ACTiming related -> set in UpdateACTiming_Reg()
+#if 0
+    vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x4, SHU_RANKCTL_RANKINCTL_PHY)
+                | P_Fld(0x2, SHU_RANKCTL_RANKINCTL_ROOT1)
+                | P_Fld(0x2, SHU_RANKCTL_RANKINCTL));
+#endif
+    vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x3, SHU_CKECTRL_TCKESRX));
+                //| P_Fld(0x3, SHU_CKECTRL_CKEPRD));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ODTCTRL, P_Fld(0x1, SHU_ODTCTRL_RODTE)
+                | P_Fld(0x1, SHU_ODTCTRL_RODTE2)
+                //| P_Fld(0x4, SHU_ODTCTRL_RODT) //Set in UpdateACTimingReg()
+                | P_Fld(0x1, SHU_ODTCTRL_ROEN));
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x1, SHU_B0_DQ7_R_DMRODTEN_B0);
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x1, SHU_B1_DQ7_R_DMRODTEN_B1);
+#if LEGACY_TX_TRACK
+    LegacyTxTrackLP4_DDR2667(p);
+#endif
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)
+                | P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_OEN_DQS2)
+                | P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_OEN_DQS1)
+                | P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_OEN_DQS0)
+                | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_DQS3)
+                | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_DQS2)
+                | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_DQS1)
+                | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_DQS0));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS3)
+                | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS2)
+                | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS1)
+                | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS0)
+                | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3)
+                | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2)
+                | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS1)
+                | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS0));
+
+    vIO32WriteFldAlign(DRAMC_REG_SHU_DQS2DQ_TX, 0x7, SHU_DQS2DQ_TX_OE2DQ_OFFSET);
+    //vIO32WriteFldAlign(DRAMC_REG_SHU_HWSET_MR2, 0x24, SHU_HWSET_MR2_HWSET_MR2_OP);
+    //vIO32WriteFldAlign(DRAMC_REG_SHU_HWSET_MR13, 0xc8, SHU_HWSET_MR13_HWSET_MR13_OP);
+    //vIO32WriteFldAlign(DRAMC_REG_SHU_HWSET_VRCG, 0xc0, SHU_HWSET_VRCG_HWSET_VRCG_OP);
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSIEN, P_Fld(0x19, SHURK0_DQSIEN_R0DQS1IEN)
+                | P_Fld(0x19, SHURK0_DQSIEN_R0DQS0IEN));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_PI, P_Fld(0x14, SHURK0_PI_RK0_ARPI_DQM_B1)
+                | P_Fld(0x14, SHURK0_PI_RK0_ARPI_DQM_B0)
+                | P_Fld(0x14, SHURK0_PI_RK0_ARPI_DQ_B1)
+                | P_Fld(0x14, SHURK0_PI_RK0_ARPI_DQ_B0));
+
+    #if LEGACY_GATING_DLY
+    LegacyGatingDlyLP4_DDR2667(p);
+    #endif
+
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
+                    | P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
+                    | P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
+                    | P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
+                    | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ3)
+                    | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ2)
+                    | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ1)
+                    | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
+                    | P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
+                    | P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
+                    | P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
+                    | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM3)
+                    | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM2)
+                    | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM1)
+                    | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM0));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
+                    | P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
+                    | P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
+                    | P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
+                    | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ3)
+                    | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ2)
+                    | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ1)
+                    | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
+                    | P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
+                    | P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
+                    | P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
+                    | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM3)
+                    | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM2)
+                    | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM1)
+                    | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM0));
+    }
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(0x6, SHURK0_SELPH_DQ2_DLY_OEN_DQ3)
+                | P_Fld(0x6, SHURK0_SELPH_DQ2_DLY_OEN_DQ2)
+                | P_Fld(0x6, SHURK0_SELPH_DQ2_DLY_OEN_DQ1)
+                | P_Fld(0x6, SHURK0_SELPH_DQ2_DLY_OEN_DQ0)
+                | P_Fld(0x1, SHURK0_SELPH_DQ2_DLY_DQ3)
+                | P_Fld(0x1, SHURK0_SELPH_DQ2_DLY_DQ2)
+                | P_Fld(0x1, SHURK0_SELPH_DQ2_DLY_DQ1)
+                | P_Fld(0x1, SHURK0_SELPH_DQ2_DLY_DQ0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ3, P_Fld(0x6, SHURK0_SELPH_DQ3_DLY_OEN_DQM3)
+                | P_Fld(0x6, SHURK0_SELPH_DQ3_DLY_OEN_DQM2)
+                | P_Fld(0x6, SHURK0_SELPH_DQ3_DLY_OEN_DQM1)
+                | P_Fld(0x6, SHURK0_SELPH_DQ3_DLY_OEN_DQM0)
+                | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM3)
+                | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM2)
+                | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM1)
+                | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM0));
+    //vIO32WriteFldAlign(DRAMC_REG_SHURK1_DQSCTL, 0x4, SHURK1_DQSCTL_R1DQSINCTL); //Set in UpdateACTimingReg()
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(0x1f, SHURK1_DQSIEN_R1DQS1IEN)
+                | P_Fld(0x1f, SHURK1_DQSIEN_R1DQS0IEN));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_PI, P_Fld(0x14, SHURK1_PI_RK1_ARPI_DQM_B1)
+                | P_Fld(0x14, SHURK1_PI_RK1_ARPI_DQM_B0)
+                | P_Fld(0x14, SHURK1_PI_RK1_ARPI_DQ_B1)
+                | P_Fld(0x14, SHURK1_PI_RK1_ARPI_DQ_B0));
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
+                    | P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
+                    | P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
+                    | P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
+                    | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
+                    | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
+                    | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
+                    | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
+                    | P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
+                    | P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
+                    | P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
+                    | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
+                    | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
+                    | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
+                    | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
+                    | P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
+                    | P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
+                    | P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
+                    | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
+                    | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
+                    | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
+                    | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
+                    | P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
+                    | P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
+                    | P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
+                    | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
+                    | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
+                    | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
+                    | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
+    }
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ2, P_Fld(0x7, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3)
+                | P_Fld(0x7, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2)
+                | P_Fld(0x7, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1)
+                | P_Fld(0x7, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0)
+                | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1DQ3)
+                | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1DQ2)
+                | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1DQ1)
+                | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1DQ0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ3, P_Fld(0x7, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3)
+                | P_Fld(0x7, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2)
+                | P_Fld(0x7, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1)
+                | P_Fld(0x7, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0)
+                | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1DQM3)
+                | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1DQM2)
+                | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1DQM1)
+                | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1DQM0));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG_RETRY, P_Fld(0x4, SHU_DQSG_RETRY_R_DQSIENLAT)
+                | P_Fld(0x1, SHU_DQSG_RETRY_R_DDR1866_PLUS));
+
+    ////DDRPHY0-SHU2
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, 0x3, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0);
+    //vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ6, P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0)
+    //            | P_Fld(0x1, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0));
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_MIDPI_DIV4_ENABLE)
+                    | P_Fld(0x1, SHU_B0_DQ7_MIDPI_ENABLE));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x1, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0)
+                    | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0)
+                    | P_Fld(0x0, SHU_B0_DQ7_MIDPI_DIV4_ENABLE)
+                    | P_Fld(0x1, SHU_B0_DQ7_MIDPI_ENABLE));
+    }
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ5, 0x3, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1);
+    //vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ6, P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1)
+    //            | P_Fld(0x1, SHU_B1_DQ6_RG_ARPI_MIDPI_EN_B1));
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+    }
+    else
+    {
+        vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ7, P_Fld(0x1, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1)
+                    | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1));
+    }
+    //DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    //vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD6, P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA)
+    //            | P_Fld(0x1, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA));
+    //vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD6+SHIFT_TO_CHB_ADDR, P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA)
+    //            | P_Fld(0x1, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA));
+    //DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    //vIO32WriteFldAlign(DDRPHY_SHU_PLL5, 0x3300, SHU_PLL5_RG_RPHYPLL_SDM_PCW);
+    //vIO32WriteFldAlign(DDRPHY_SHU_PLL7, 0x3300, SHU_PLL7_RG_RCLRPLL_SDM_PCW);
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(0x1e, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0)
+                | P_Fld(0x1e, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(0x1e, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1)
+                | P_Fld(0x1e, SHU_R0_B1_DQ7_RK0_ARPI_DQ_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ7, P_Fld(0x1e, SHU_R1_B0_DQ7_RK1_ARPI_DQM_B0)
+                | P_Fld(0x1e, SHU_R1_B0_DQ7_RK1_ARPI_DQ_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ7, P_Fld(0x1e, SHU_R1_B1_DQ7_RK1_ARPI_DQM_B1)
+                | P_Fld(0x1e, SHU_R1_B1_DQ7_RK1_ARPI_DQ_B1));
+#if LEGACY_RX_DLY
+    LegacyRxDly_LP4_DDR2667(p);
+#endif
+#if LEGACY_DELAY_CELL
+    LegacyDlyCellInitLP4_DDR2667(p);
+#endif
+
+}
+
+static void DramcSetting_LP4_TX_Delay_DDR1600(DRAMC_CTX_T *p, DRAM_RANK_T eRank)
+{
+    U8 ucR0TxdlyOendq = 0, ucR0Txdlydq = 0;
+    U8 ucR1TxdlyOendq = 0, ucR1Txdlydq = 0;
+    U8 u1R0B0Pi = 0, u1R0B1Pi = 0;
+    U8 u1R1B0Pi = 0, u1R1B1Pi = 0;
+
+    if (eRank == RANK_0)
+    {
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+        {
+            ucR0TxdlyOendq = 0x3;
+            ucR0Txdlydq = 0x4;
+        }
+        else
+        {
+            if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+            {
+                ucR0TxdlyOendq = 0x1;
+                ucR0Txdlydq = 0x2;
+            }
+            else
+            {
+                ucR0TxdlyOendq = 0x1;
+                ucR0Txdlydq = 0x2;
+            }
+        }
+
+        if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+        {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ3)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ2)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ1)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM3)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM2)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM1)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM0));
+        }
+        else
+        {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ3)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ2)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ1)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
+                        | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM3)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM2)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM1)
+                        | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM0));
+        }
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+        {
+            ucR0TxdlyOendq = 0x2;
+            ucR0Txdlydq = 0x1;
+        }
+        else
+        {
+            if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+            {
+                ucR0TxdlyOendq = 0x6;
+                ucR0Txdlydq = 0x1;
+            }
+            else
+            {
+                ucR0TxdlyOendq = 0x7;
+                ucR0Txdlydq = 0x1;
+            }
+        }
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ3)
+                    | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ2)
+                    | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ1)
+                    | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ0)
+                    | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ2_DLY_DQ3)
+                    | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ2_DLY_DQ2)
+                    | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ2_DLY_DQ1)
+                    | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ2_DLY_DQ0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ3, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ3_DLY_OEN_DQM3)
+                    | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ3_DLY_OEN_DQM2)
+                    | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ3_DLY_OEN_DQM1)
+                    | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ3_DLY_OEN_DQM0)
+                    | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM3)
+                    | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM2)
+                    | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM1)
+                    | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM0));
+    }
+    else //RANK_1
+    {
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+        {
+            ucR1TxdlyOendq = 0x3;
+            ucR1Txdlydq = 0x4;
+        }
+        else
+        {
+            if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+            {
+                ucR1TxdlyOendq = 0x1;
+                ucR1Txdlydq = 0x2;
+            }
+            else
+            {
+                ucR1TxdlyOendq = 0x1;
+                ucR1Txdlydq = 0x2;
+            }
+        }
+        if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+        {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
+        }
+        else
+        {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
+                        | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
+                        | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
+        }
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+        {
+            ucR1TxdlyOendq = 0x3;
+            ucR1Txdlydq = 0x2;
+        }
+        else
+        {
+            if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+            {
+                ucR1TxdlyOendq = 0x7;
+                ucR1Txdlydq = 0x2;
+            }
+            else
+            {
+                ucR1TxdlyOendq = 0x7;
+                ucR1Txdlydq = 0x1;
+            }
+        }
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ2, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3)
+                    | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2)
+                    | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1)
+                    | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0)
+                    | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ2_DLY_R1DQ3)
+                    | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ2_DLY_R1DQ2)
+                    | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ2_DLY_R1DQ1)
+                    | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ2_DLY_R1DQ0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ3, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3)
+                    | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2)
+                    | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1)
+                    | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0)
+                    | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ3_DLY_R1DQM3)
+                    | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ3_DLY_R1DQM2)
+                    | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ3_DLY_R1DQM1)
+                    | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ3_DLY_R1DQM0));
+    }
+
+    if (eRank == RANK_0)
+    {
+        if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+        {
+            // Byte mode For RK0 Tx PI
+            u1R0B0Pi = 0x1e;
+            u1R0B1Pi = 0x1e;
+        }
+        else
+        {
+            // For RK0 Tx PI
+            u1R0B0Pi = 0x1a;
+            u1R0B1Pi = 0x1a;
+        }
+        vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(u1R0B0Pi, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0)
+                    | P_Fld(u1R0B0Pi, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0));
+        vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(u1R0B1Pi, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1)
+                    | P_Fld(u1R0B1Pi, SHU_R0_B1_DQ7_RK0_ARPI_DQ_B1));
+    }
+    else
+    {
+        // For RK1 Tx PI
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+        {
+            // for DDR1600 1:4 mode
+            u1R1B0Pi = 0x1b;
+            u1R1B1Pi = 0x1b;
+        }
+        else
+        {
+            if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+            {
+                // Byte mode for DDR1600 1:8 mode
+                u1R1B0Pi = 0x13;
+                u1R1B1Pi = 0x12;
+            }
+            else
+            {
+                // for DDR1600 1:8 mode
+                u1R1B0Pi = 0x26;
+                u1R1B1Pi = 0x26;
+            }
+        }
+        vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ7, P_Fld(u1R1B0Pi, SHU_R1_B0_DQ7_RK1_ARPI_DQM_B0)
+                    | P_Fld(u1R1B0Pi, SHU_R1_B0_DQ7_RK1_ARPI_DQ_B0));
+        vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ7, P_Fld(u1R1B1Pi, SHU_R1_B1_DQ7_RK1_ARPI_DQM_B1)
+                    | P_Fld(u1R1B1Pi, SHU_R1_B1_DQ7_RK1_ARPI_DQ_B1));
+
+    }
+}
+
+static void DramcSetting_LP4_TX_Delay_DDR800(DRAMC_CTX_T *p, DRAM_RANK_T eRank)
+{
+    if (eRank == RANK_0)
+    {
+        if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+        {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
+                        | P_Fld(0x4, SHURK0_SELPH_DQ0_TXDLY_DQ3)
+                        | P_Fld(0x4, SHURK0_SELPH_DQ0_TXDLY_DQ2)
+                        | P_Fld(0x4, SHURK0_SELPH_DQ0_TXDLY_DQ1)
+                        | P_Fld(0x4, SHURK0_SELPH_DQ0_TXDLY_DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
+                        | P_Fld(0x4, SHURK0_SELPH_DQ1_TXDLY_DQM3)
+                        | P_Fld(0x4, SHURK0_SELPH_DQ1_TXDLY_DQM2)
+                        | P_Fld(0x4, SHURK0_SELPH_DQ1_TXDLY_DQM1)
+                        | P_Fld(0x4, SHURK0_SELPH_DQ1_TXDLY_DQM0));
+        }
+        else
+        {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
+                        | P_Fld(0x4, SHURK0_SELPH_DQ0_TXDLY_DQ3)
+                        | P_Fld(0x4, SHURK0_SELPH_DQ0_TXDLY_DQ2)
+                        | P_Fld(0x4, SHURK0_SELPH_DQ0_TXDLY_DQ1)
+                        | P_Fld(0x4, SHURK0_SELPH_DQ0_TXDLY_DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
+                        | P_Fld(0x4, SHURK0_SELPH_DQ1_TXDLY_DQM3)
+                        | P_Fld(0x4, SHURK0_SELPH_DQ1_TXDLY_DQM2)
+                        | P_Fld(0x4, SHURK0_SELPH_DQ1_TXDLY_DQM1)
+                        | P_Fld(0x4, SHURK0_SELPH_DQ1_TXDLY_DQM0));
+        }
+
+        if (vGet_DDR800_Mode(p) == DDR800_CLOSE_LOOP)
+        {
+            // TX OE -3*UI
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ3)
+                        | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ2)
+                        | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ1)
+                        | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ0)
+                        | P_Fld(0x1, SHURK0_SELPH_DQ2_DLY_DQ3)
+                        | P_Fld(0x1, SHURK0_SELPH_DQ2_DLY_DQ2)
+                        | P_Fld(0x1, SHURK0_SELPH_DQ2_DLY_DQ1)
+                        | P_Fld(0x1, SHURK0_SELPH_DQ2_DLY_DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ3, P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_OEN_DQM3)
+                        | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_OEN_DQM2)
+                        | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_OEN_DQM1)
+                        | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_OEN_DQM0)
+                        | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM3)
+                        | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM2)
+                        | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM1)
+                        | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM0));
+        }
+        else //if (vGet_DDR800_Mode(p) == DDR800_OPEN_LOOP)
+        {
+            // DDR800_OPEN_LOOP and DDR800_SEMI_LOOP
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(0x3, SHURK0_SELPH_DQ2_DLY_OEN_DQ3)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ2_DLY_OEN_DQ2)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ2_DLY_OEN_DQ1)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ2_DLY_OEN_DQ0)
+                        | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_DQ3)
+                        | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_DQ2)
+                        | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_DQ1)
+                        | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ3, P_Fld(0x3, SHURK0_SELPH_DQ3_DLY_OEN_DQM3)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ3_DLY_OEN_DQM2)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ3_DLY_OEN_DQM1)
+                        | P_Fld(0x3, SHURK0_SELPH_DQ3_DLY_OEN_DQM0)
+                        | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_DQM3)
+                        | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_DQM2)
+                        | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_DQM1)
+                        | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_DQM0));
+        }
+    }
+    else
+    {
+        if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+        {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
+                        | P_Fld(0x4, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
+                        | P_Fld(0x4, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
+                        | P_Fld(0x4, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
+                        | P_Fld(0x4, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
+                        | P_Fld(0x4, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
+                        | P_Fld(0x4, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
+                        | P_Fld(0x4, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
+                        | P_Fld(0x4, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
+        }
+        else
+        {
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
+                        | P_Fld(0x4, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
+                        | P_Fld(0x4, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
+                        | P_Fld(0x4, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
+                        | P_Fld(0x4, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
+                        | P_Fld(0x4, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
+                        | P_Fld(0x4, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
+                        | P_Fld(0x4, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
+                        | P_Fld(0x4, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
+        }
+
+        if (vGet_DDR800_Mode(p) == DDR800_CLOSE_LOOP)
+        {
+            // TX OE -3*UI
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ2, P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3)
+                        | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2)
+                        | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1)
+                        | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0)
+                        | P_Fld(0x1, SHURK1_SELPH_DQ2_DLY_R1DQ3)
+                        | P_Fld(0x1, SHURK1_SELPH_DQ2_DLY_R1DQ2)
+                        | P_Fld(0x1, SHURK1_SELPH_DQ2_DLY_R1DQ1)
+                        | P_Fld(0x1, SHURK1_SELPH_DQ2_DLY_R1DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ3, P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3)
+                        | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2)
+                        | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1)
+                        | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0)
+                        | P_Fld(0x1, SHURK1_SELPH_DQ3_DLY_R1DQM3)
+                        | P_Fld(0x1, SHURK1_SELPH_DQ3_DLY_R1DQM2)
+                        | P_Fld(0x1, SHURK1_SELPH_DQ3_DLY_R1DQM1)
+                        | P_Fld(0x1, SHURK1_SELPH_DQ3_DLY_R1DQM0));
+        }
+        else //if (vGet_DDR800_Mode(p) == DDR800_OPEN_LOOP)
+        {
+            // DDR800_OPEN_LOOP and DDR800_SEMI_LOOP
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ2, P_Fld(0x3, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0)
+                        | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1DQ3)
+                        | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1DQ2)
+                        | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1DQ1)
+                        | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ3, P_Fld(0x3, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1)
+                        | P_Fld(0x3, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0)
+                        | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1DQM3)
+                        | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1DQM2)
+                        | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1DQM1)
+                        | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1DQM0));
+        }
+    }
+
+    if (vGet_DDR800_Mode(p) == DDR800_CLOSE_LOOP)
+    {
+        // DDR800 1:4 mode TX PI
+        vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(0x1a, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0)
+                    | P_Fld(0x1a, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0));
+        vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(0x1a, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1)
+                    | P_Fld(0x1a, SHU_R0_B1_DQ7_RK0_ARPI_DQ_B1));
+        vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ7, P_Fld(0x25, SHU_R1_B0_DQ7_RK1_ARPI_DQM_B0)
+                    | P_Fld(0x25, SHU_R1_B0_DQ7_RK1_ARPI_DQ_B0));
+        vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ7, P_Fld(0x25, SHU_R1_B1_DQ7_RK1_ARPI_DQM_B1)
+                    | P_Fld(0x25, SHU_R1_B1_DQ7_RK1_ARPI_DQ_B1));
+    }
+    else
+    {
+        // DDR800_SEMI_LOOP and DDR800_OPEN_LOOP
+        // DDR800 1:4 mode TX PI
+        vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(0x0, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0)
+                    | P_Fld(0x0, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0));
+        vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(0x0, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1)
+                    | P_Fld(0x0, SHU_R0_B1_DQ7_RK0_ARPI_DQ_B1));
+        vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ7, P_Fld(0x0, SHU_R1_B0_DQ7_RK1_ARPI_DQM_B0)
+                    | P_Fld(0x0, SHU_R1_B0_DQ7_RK1_ARPI_DQ_B0));
+        vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ7, P_Fld(0x0, SHU_R1_B1_DQ7_RK1_ARPI_DQM_B1)
+                    | P_Fld(0x0, SHU_R1_B1_DQ7_RK1_ARPI_DQ_B1));
+    }
+}
+
+static void DramcSetting_Olympus_LP4_ByteMode_DDR1600(DRAMC_CTX_T *p)
+{
+    U8 ucMCKTxdlyOendqs = 0, ucMCKTxdlydqs = 0;
+    U8 ucUITxdlyOendqs = 0, ucUITxdlydqs = 0;
+
+    ////DRAMC0-SHU3
+#if LEGACY_TDQSCK_PRECAL
+    LegacyPreCalLP4_DDR1600(p);
+#endif
+#if LEGACY_TX_TRACK
+     LegacyTxTrackLP4_DDR1600(p);
+#endif
+
+    //vIO32WriteFldAlign(DRAMC_REG_SHU_CONF2, 0x32, SHU_CONF2_FSPCHG_PRDCNT); //ACTiming related -> set in UpdateACTiming_Reg()
+    //vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x0, SHU_CKECTRL_TCKESRX)); //from CF review, only work for DDR3/4 (Darren)
+                //| P_Fld(0x2, SHU_CKECTRL_CKEPRD));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ODTCTRL, P_Fld(0x0, SHU_ODTCTRL_RODTE)
+                | P_Fld(0x0, SHU_ODTCTRL_RODTE2)
+                //| P_Fld(0x2, SHU_ODTCTRL_RODT) //Set in UpdateACTimingReg()
+#ifdef LOOPBACK_TEST
+                | P_Fld(0x1, SHU_ODTCTRL_ROEN));
+#else
+                | P_Fld(0x0, SHU_ODTCTRL_ROEN));
+#endif
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x0, SHU_B0_DQ7_R_DMRODTEN_B0);
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x0, SHU_B1_DQ7_R_DMRODTEN_B1);
+
+    if (vGet_Div_Mode(p) == DIV4_MODE)
+    {
+        ucMCKTxdlyOendqs = 0x3;
+        ucMCKTxdlydqs = 0x4;
+        ucUITxdlyOendqs = 0x2;
+        ucUITxdlydqs = 0x1;
+    }
+    else
+    {
+        ucMCKTxdlyOendqs = 0x1;
+        ucMCKTxdlydqs = 0x2;
+        ucUITxdlyOendqs = 0x6;
+        ucUITxdlydqs = 0x1;
+    }
+
+    //MCK by Wleveling
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(ucMCKTxdlyOendqs, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)
+                | P_Fld(ucMCKTxdlyOendqs, SHU_SELPH_DQS0_TXDLY_OEN_DQS2)
+                | P_Fld(ucMCKTxdlyOendqs, SHU_SELPH_DQS0_TXDLY_OEN_DQS1)
+                | P_Fld(ucMCKTxdlyOendqs, SHU_SELPH_DQS0_TXDLY_OEN_DQS0)
+                | P_Fld(ucMCKTxdlydqs, SHU_SELPH_DQS0_TXDLY_DQS3)
+                | P_Fld(ucMCKTxdlydqs, SHU_SELPH_DQS0_TXDLY_DQS2)
+                | P_Fld(ucMCKTxdlydqs, SHU_SELPH_DQS0_TXDLY_DQS1)
+                | P_Fld(ucMCKTxdlydqs, SHU_SELPH_DQS0_TXDLY_DQS0));
+    //UI by Wleveling
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(ucUITxdlyOendqs, SHU_SELPH_DQS1_DLY_OEN_DQS3)
+                | P_Fld(ucUITxdlyOendqs, SHU_SELPH_DQS1_DLY_OEN_DQS2)
+                | P_Fld(ucUITxdlyOendqs, SHU_SELPH_DQS1_DLY_OEN_DQS1)
+                | P_Fld(ucUITxdlyOendqs, SHU_SELPH_DQS1_DLY_OEN_DQS0)
+                | P_Fld(ucUITxdlydqs, SHU_SELPH_DQS1_DLY_DQS3)
+                | P_Fld(ucUITxdlydqs, SHU_SELPH_DQS1_DLY_DQS2)
+                | P_Fld(ucUITxdlydqs, SHU_SELPH_DQS1_DLY_DQS1)
+                | P_Fld(ucUITxdlydqs, SHU_SELPH_DQS1_DLY_DQS0));
+
+    vIO32WriteFldAlign(DRAMC_REG_SHU_DQS2DQ_TX, 0x4, SHU_DQS2DQ_TX_OE2DQ_OFFSET);
+
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_PI, P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQM_B1)
+                | P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQM_B0)
+                | P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQ_B1)
+                | P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQ_B0));
+    //Rank0/1 TX Delay
+    if (p->freqGroup == 400)
+    {
+        DramcSetting_LP4_TX_Delay_DDR800(p, RANK_0);
+        DramcSetting_LP4_TX_Delay_DDR800(p, RANK_1);
+    }
+    else // for DDR1200 and DDR1600
+    {
+        DramcSetting_LP4_TX_Delay_DDR1600(p, RANK_0);
+        DramcSetting_LP4_TX_Delay_DDR1600(p, RANK_1);
+    }
+    // Tx tracking
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_PI, P_Fld(0x1e, SHURK1_PI_RK1_ARPI_DQM_B1)
+                | P_Fld(0x1e, SHURK1_PI_RK1_ARPI_DQM_B0)
+                | P_Fld(0x1e, SHURK1_PI_RK1_ARPI_DQ_B1)
+                | P_Fld(0x1e, SHURK1_PI_RK1_ARPI_DQ_B0));
+
+#if LEGACY_GATING_DLY
+    if (p->freqGroup == 400)
+        LegacyGatingDlyLP4_DDR800(p); // for 1:4 mode settings
+    else
+        LegacyGatingDlyLP4_DDR1600(p); // for 1:8 and 1:4 mode settings for DDR1200 and DDR1600
+#endif
+
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG_RETRY, P_Fld(0x3, SHU_DQSG_RETRY_R_DQSIENLAT)
+                | P_Fld(0x0, SHU_DQSG_RETRY_R_DDR1866_PLUS));
+
+    ////DDRPHY0-SHU3
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, 0x5, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0); // for Rx guard
+    //vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ6, P_Fld(0x1, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0)
+    //            | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0));
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x1, SHU_B0_DQ7_MIDPI_DIV4_ENABLE)
+                    | P_Fld(0x0, SHU_B0_DQ7_MIDPI_ENABLE));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0)
+                    | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0)
+                    | P_Fld(0x1, SHU_B0_DQ7_MIDPI_DIV4_ENABLE)
+                    | P_Fld(0x0, SHU_B0_DQ7_MIDPI_ENABLE));
+    }
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ5, 0x5, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1); // for Rx guard
+    //vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ6, P_Fld(0x1, SHU_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1)
+    //            | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_EN_B1));
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {}
+    else
+    {
+        vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1)
+                    | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1));
+    }
+
+#if LEGACY_RX_DLY
+    if (p->freqGroup == 400) // for DDR800 1:4 mode
+        LegacyRxDly_LP4_DDR800(p);
+    else
+        LegacyRxDly_LP4_DDR1600(p);
+#endif
+#if LEGACY_DELAY_CELL
+    LegacyDlyCellInitLP4_DDR1600(p);
+#endif
+
+    if (vGet_Div_Mode(p) == DIV4_MODE)
+    {
+#if 0
+        if (p->freqGroup == 400) // for DDR800 1:4 mode
+        {
+            vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x6, SHU_RANKCTL_RANKINCTL_PHY)
+                        | P_Fld(0x4, SHU_RANKCTL_RANKINCTL_ROOT1)
+                        | P_Fld(0x4, SHU_RANKCTL_RANKINCTL));
+        }
+        else // for DDR1600 1:4 mode
+        {
+            vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x6, SHU_RANKCTL_RANKINCTL_PHY)
+                        | P_Fld(0x4, SHU_RANKCTL_RANKINCTL_ROOT1)
+                        | P_Fld(0x4, SHU_RANKCTL_RANKINCTL));
+        }
+#endif
+        // 1:4 mode
+        vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x0, SHU_CONF0_DM64BITEN)
+                    | P_Fld(0x1, SHU_CONF0_FDIV2)
+                    | P_Fld(0x0, SHU_CONF0_FREQDIV4)
+                    | P_Fld(0x0, SHU_CONF0_DUALSCHEN)
+                    | P_Fld(0x1, SHU_CONF0_WDATRGO));
+#if 0 // 1:8 mode
+        vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x1, SHU_CONF0_DM64BITEN)
+                    | P_Fld(0x0, SHU_CONF0_FDIV2)
+                    | P_Fld(0x1, SHU_CONF0_FREQDIV4)
+                    | P_Fld(0x1, SHU_CONF0_DUALSCHEN)
+                    | P_Fld(0x0, SHU_CONF0_WDATRGO));
+#endif
+
+    #if (!CMD_CKE_WORKAROUND_FIX)
+        vIO32WriteFldAlign(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, 0x7, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_DYN_GATING_SEL);
+        vIO32WriteFldAlign(DRAMC_REG_SHU_SELPH_CA1, 0x1, SHU_SELPH_CA1_TXDLY_CKE);
+        vIO32WriteFldAlign(DRAMC_REG_SHU_SELPH_CA2, 0x1, SHU_SELPH_CA2_TXDLY_CKE1);
+    #endif
+        //DATLAT 1:4 mode from Ton
+        vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x1, SHU_B0_DQ7_R_DMRDSEL_DIV2_OPT)
+                    | P_Fld(0x1, SHU_B0_DQ7_R_DMRDSEL_LOBYTE_OPT)
+                    | P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_HIBYTE_OPT));
+        //RDATA PIPE from Ton
+        vIO32WriteFldMulti(DRAMC_REG_SHU_PIPE, P_Fld(0x1, SHU_PIPE_READ_START_EXTEND1)
+                    | P_Fld(0x1, SHU_PIPE_DLE_LAST_EXTEND1)
+                    | P_Fld(0x1, SHU_PIPE_READ_START_EXTEND2)
+                    | P_Fld(0x1, SHU_PIPE_DLE_LAST_EXTEND2)
+                    | P_Fld(0x0, SHU_PIPE_READ_START_EXTEND3)
+                    | P_Fld(0x0, SHU_PIPE_DLE_LAST_EXTEND3));
+    }
+#if 0
+    else
+    {
+        // for DDR1600 1:8 mode
+        vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x2, SHU_RANKCTL_RANKINCTL_PHY)
+                    | P_Fld(0x0, SHU_RANKCTL_RANKINCTL_ROOT1)
+                    | P_Fld(0x0, SHU_RANKCTL_RANKINCTL));
+    }
+#endif
+}
+
+/*
+CANNOT use DRAMC_WBR :
+DDRPHY_CA_DLL_ARPI0 -> DDRPHY_SHU_CA_DLL1
+DDRPHY_CA_DLL_ARPI3
+DDRPHY_CA_DLL_ARPI5 -> DDRPHY_SHU_CA_DLL0
+DDRPHY_SHU_CA_CMD6
+*/
+
+void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p)
+{
+
+    U8 u1CAP_SEL;
+    U8 u1MIDPICAP_SEL;
+    //U16 u2SDM_PCW = 0; // SDM_PCW are set in DDRPhyPLLSetting()
+    U8 u1TXDLY_CMD;
+    U8 u1TAIL_LAT;
+
+    AutoRefreshCKEOff(p);
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+                                                                             //before switch clock from 26M to PHY, need to init PHY clock first
+    vIO32WriteFldMulti_All(DDRPHY_CKMUX_SEL, P_Fld(0x1, CKMUX_SEL_R_PHYCTRLMUX)  //move CKMUX_SEL_R_PHYCTRLMUX to here (it was originally between MISC_CG_CTRL0_CLK_MEM_SEL and MISC_CTRL0_R_DMRDSEL_DIV2_OPT)
+                                        | P_Fld(0x1, CKMUX_SEL_R_PHYCTRLDCM)); // PHYCTRLDCM 1: follow DDRPHY_conf DCM settings, 0: follow infra DCM settings
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+
+    //chg_mem_en = 1
+    vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL0, 0x1, MISC_CG_CTRL0_W_CHG_MEM);
+    //26M
+    vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL0, 0x0, MISC_CG_CTRL0_CLK_MEM_SEL);
+
+    vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_DIV2_OPT)
+                | P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_LOBYTE_OPT)
+                | P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_HIBYTE_OPT));
+
+    //                   0 ===LP4_3200_intial_setting_shu1 begin===
+    #if APOLLO_SPECIFIC
+    vIO32WriteFldAlign(DRAMC_REG_RKCFG, 1, RKCFG_CS1FORCE0);
+    #endif
+    //Francis : pin mux issue, need to set CHD
+    // TODO: ARDMSUS_10 already set to 0 in SwimpedanceCal(), may be removed here?
+    vIO32WriteFldMulti(DDRPHY_MISC_SPM_CTRL1, P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10) | P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10_B0)
+                                           | P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10_B1) | P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10_CA));
+
+    vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL2, 0x0, MISC_SPM_CTRL2_PHY_SPM_CTL2);
+    vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL0, 0x0, MISC_SPM_CTRL0_PHY_SPM_CTL0);
+    vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL2, 0x6003bf, MISC_CG_CTRL2_RG_MEM_DCM_CTL);//Move to DCM off setting
+    vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL4, 0x333f3f00, MISC_CG_CTRL4_R_PHY_MCK_CG_CTRL);//Move to DCM off setting
+    vIO32WriteFldMulti(DDRPHY_SHU_PLL1, P_Fld(0x1, SHU_PLL1_R_SHU_AUTO_PLL_MUX)
+                | P_Fld(0x7, SHU_PLL1_SHU1_PLL1_RFU));
+    vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x1, SHU_B0_DQ7_MIDPI_ENABLE)
+                | P_Fld(0x0, SHU_B0_DQ7_MIDPI_DIV4_ENABLE)
+                | P_Fld(0, SHU_B0_DQ7_R_DMRANKRXDVS_B0));
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0, SHU_B1_DQ7_R_DMRANKRXDVS_B1);
+    //vIO32WriteFldAlign(DDRPHY_SHU_PLL4, 0xfe, SHU_PLL4_RG_RPHYPLL_RESERVED);
+    vIO32WriteFldMulti(DDRPHY_SHU_PLL4, P_Fld(0x1, SHU_PLL4_RG_RPHYPLL_IBIAS) | P_Fld(0x1, SHU_PLL4_RG_RPHYPLL_ICHP) | P_Fld(0x1, SHU_PLL4_RG_RPHYPLL_FS));
+    //vIO32WriteFldAlign(DDRPHY_SHU_PLL6, 0xfe, SHU_PLL6_RG_RCLRPLL_RESERVED);
+    vIO32WriteFldMulti(DDRPHY_SHU_PLL6, P_Fld(0x1, SHU_PLL6_RG_RCLRPLL_IBIAS) | P_Fld(0x1, SHU_PLL6_RG_RCLRPLL_ICHP) | P_Fld(0x1, SHU_PLL6_RG_RCLRPLL_FS));
+    vIO32WriteFldAlign(DDRPHY_SHU_PLL14, 0x0, SHU_PLL14_RG_RPHYPLL_SDM_SSC_PH_INIT);
+    vIO32WriteFldAlign(DDRPHY_SHU_PLL20, 0x0, SHU_PLL20_RG_RCLRPLL_SDM_SSC_PH_INIT);
+    vIO32WriteFldMulti(DDRPHY_CA_CMD2, P_Fld(0x0, CA_CMD2_RG_TX_ARCMD_OE_DIS)
+                | P_Fld(0x0, CA_CMD2_RG_TX_ARCMD_ODTEN_DIS)
+                | P_Fld(0x0, CA_CMD2_RG_TX_ARCLK_OE_DIS)
+                | P_Fld(0x0, CA_CMD2_RG_TX_ARCLK_ODTEN_DIS));
+    vIO32WriteFldMulti(DDRPHY_B0_DQ2, P_Fld(0x0, B0_DQ2_RG_TX_ARDQ_OE_DIS_B0)
+                | P_Fld(0x0, B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0)
+                | P_Fld(0x0, B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0)
+                | P_Fld(0x0, B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0));
+    vIO32WriteFldMulti(DDRPHY_B1_DQ2, P_Fld(0x0, B1_DQ2_RG_TX_ARDQ_OE_DIS_B1)
+                | P_Fld(0x0, B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1)
+                | P_Fld(0x0, B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1)
+                | P_Fld(0x0, B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1));
+    #if 0 //Correct settings are set in UpdateInitialSettings_LP4()
+    vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x0, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x7, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1);
+    vIO32WriteFldAlign(DDRPHY_CA_CMD10, 0x0, CA_CMD10_R_IN_GATE_EN_LOW_OPT_CA);
+    #endif
+    vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x1, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x1, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1);
+    vIO32WriteFldAlign(DDRPHY_CA_CMD10, 0x0, CA_CMD10_R_DMRXDVS_RDSEL_LAT_CA);
+
+    vIO32WriteFldAlign(DDRPHY_B0_RXDVS0, 0x1, B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_RXDVS0, 0x1, B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1);
+    vIO32WriteFldAlign(DDRPHY_B0_RXDVS0, 0x1, B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_RXDVS0, 0x1, B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1);
+    vIO32WriteFldAlign(DDRPHY_R0_B0_RXDVS2, 0x1, R0_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0);
+    vIO32WriteFldAlign(DDRPHY_R1_B0_RXDVS2, 0x1, R1_B0_RXDVS2_R_RK1_DVS_FDLY_MODE_B0);
+    vIO32WriteFldAlign(DDRPHY_R0_B1_RXDVS2, 0x1, R0_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1);
+    vIO32WriteFldAlign(DDRPHY_R1_B1_RXDVS2, 0x1, R1_B1_RXDVS2_R_RK1_DVS_FDLY_MODE_B1);
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, 0x3, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0);
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ5, 0x3, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1);
+#if LEGACY_RX_DLY
+    LegacyRxDly_LP4_DDR3200(p);
+#endif
+    vIO32WriteFldMulti(DDRPHY_R0_B0_RXDVS1, P_Fld(0x2, R0_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD)
+                | P_Fld(0x2, R0_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG));
+    vIO32WriteFldMulti(DDRPHY_R1_B0_RXDVS1, P_Fld(0x2, R1_B0_RXDVS1_R_RK1_B0_DVS_TH_LEAD)
+                | P_Fld(0x2, R1_B0_RXDVS1_R_RK1_B0_DVS_TH_LAG));
+    vIO32WriteFldMulti(DDRPHY_R0_B1_RXDVS1, P_Fld(0x2, R0_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD)
+                | P_Fld(0x2, R0_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG));
+    vIO32WriteFldMulti(DDRPHY_R1_B1_RXDVS1, P_Fld(0x2, R1_B1_RXDVS1_R_RK1_B1_DVS_TH_LEAD)
+                | P_Fld(0x2, R1_B1_RXDVS1_R_RK1_B1_DVS_TH_LAG));
+
+    vIO32WriteFldMulti(DDRPHY_R0_B0_RXDVS2, P_Fld(0x2, R0_B0_RXDVS2_R_RK0_DVS_MODE_B0)
+                | P_Fld(0x1, R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0)
+                | P_Fld(0x1, R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0));
+    vIO32WriteFldMulti(DDRPHY_R1_B0_RXDVS2, P_Fld(0x2, R1_B0_RXDVS2_R_RK1_DVS_MODE_B0)
+                | P_Fld(0x1, R1_B0_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_B0)
+                | P_Fld(0x1, R1_B0_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_B0));
+    vIO32WriteFldMulti(DDRPHY_R0_B1_RXDVS2, P_Fld(0x2, R0_B1_RXDVS2_R_RK0_DVS_MODE_B1)
+                | P_Fld(0x1, R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1)
+                | P_Fld(0x1, R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1));
+    vIO32WriteFldMulti(DDRPHY_R1_B1_RXDVS2, P_Fld(0x2, R1_B1_RXDVS2_R_RK1_DVS_MODE_B1)
+                | P_Fld(0x1, R1_B1_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_B1)
+                | P_Fld(0x1, R1_B1_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_B1));
+
+    vIO32WriteFldAlign(DDRPHY_B0_RXDVS0, 0x0, B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_RXDVS0, 0x0, B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1);
+    vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1);
+#if LEGACY_DELAY_CELL
+    LegacyDlyCellInitLP4_DDR3200(p);
+#endif
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(0x1f, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0)
+                | P_Fld(0x1f, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(0x1f, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1)
+                | P_Fld(0x1f, SHU_R0_B1_DQ7_RK0_ARPI_DQ_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ7, P_Fld(0x1f, SHU_R1_B0_DQ7_RK1_ARPI_DQM_B0)
+                | P_Fld(0x1f, SHU_R1_B0_DQ7_RK1_ARPI_DQ_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ7, P_Fld(0x1f, SHU_R1_B1_DQ7_RK1_ARPI_DQM_B1)
+                | P_Fld(0x1f, SHU_R1_B1_DQ7_RK1_ARPI_DQ_B1));
+    vIO32WriteFldMulti(DDRPHY_B0_DQ4, P_Fld(0x10, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0)
+                | P_Fld(0x10, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0));
+    vIO32WriteFldMulti(DDRPHY_B0_DQ5, P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0)
+                | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0)
+                | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0)
+                | P_Fld(0xe, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0)
+                | P_Fld(0x10, B0_DQ5_B0_DQ5_RFU));
+    vIO32WriteFldMulti(DDRPHY_B0_DQ6, P_Fld(0x1, B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0)
+                | P_Fld(0x0, B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0)
+                | P_Fld(0x0, B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0)
+                | P_Fld(0x1, B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0)
+                | P_Fld(0x1, B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0)
+                | P_Fld(0x0, B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0)
+                | P_Fld(0x1, B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0)
+                | P_Fld(0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0));
+    vIO32WriteFldMulti(DDRPHY_B0_DQ5, P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0)
+                | P_Fld(0x0, B0_DQ5_B0_DQ5_RFU));
+    vIO32WriteFldMulti(DDRPHY_B1_DQ4, P_Fld(0x10, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1)
+                | P_Fld(0x10, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1));
+    vIO32WriteFldMulti(DDRPHY_B1_DQ5, P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1)
+                | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1)
+                | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1)
+                | P_Fld(0xe, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1)
+                | P_Fld(0x10, B1_DQ5_B1_DQ5_RFU));
+    vIO32WriteFldMulti(DDRPHY_B1_DQ6, P_Fld(0x1, B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1)
+                | P_Fld(0x0, B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1)
+                | P_Fld(0x0, B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1)
+                | P_Fld(0x1, B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1)
+                | P_Fld(0x1, B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1)
+                | P_Fld(0x0, B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1)
+                | P_Fld(0x1, B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1)
+                | P_Fld(0x1, B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1));
+    vIO32WriteFldMulti(DDRPHY_B1_DQ5, P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1)
+                | P_Fld(0x0, B1_DQ5_B1_DQ5_RFU));
+    vIO32WriteFldMulti(DDRPHY_CA_CMD3, P_Fld(0x1, CA_CMD3_RG_RX_ARCMD_IN_BUFF_EN)
+                | P_Fld(0x1, CA_CMD3_RG_ARCMD_RESETB)
+                | P_Fld(0x1, CA_CMD3_RG_TX_ARCMD_EN));
+    vIO32WriteFldMulti(DDRPHY_CA_CMD6, P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_DDR4_SEL)
+                | P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL)
+                | P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN));
+    /* ARCMD_DRVP, DRVN , ARCLK_DRVP, DRVN not used anymore
+    vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD1, P_Fld(0x1, SHU_CA_CMD1_RG_TX_ARCMD_DRVN)
+                | P_Fld(0x1, SHU_CA_CMD1_RG_TX_ARCMD_DRVP));
+    vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD2, P_Fld(0x1, SHU_CA_CMD2_RG_TX_ARCLK_DRVN)
+                | P_Fld(0x1, SHU_CA_CMD2_RG_TX_ARCLK_DRVP));
+     */
+    //vIO32WriteFldMulti(DDRPHY_SHU2_CA_CMD1, P_Fld(0x1, SHU2_CA_CMD1_RG_TX_ARCMD_DRVN)
+    //            | P_Fld(0x1, SHU2_CA_CMD1_RG_TX_ARCMD_DRVP));
+    //vIO32WriteFldMulti(DDRPHY_SHU2_CA_CMD2, P_Fld(0x1, SHU2_CA_CMD2_RG_TX_ARCLK_DRVN)
+    //            | P_Fld(0x1, SHU2_CA_CMD2_RG_TX_ARCLK_DRVP));
+    vIO32WriteFldMulti(DDRPHY_PLL3, P_Fld(0x0, PLL3_RG_RPHYPLL_TSTOP_EN) | P_Fld(0x0, PLL3_RG_RPHYPLL_TST_EN));
+    vIO32WriteFldAlign(DDRPHY_MISC_VREF_CTRL, 0x0, MISC_VREF_CTRL_RG_RVREF_VREF_EN); //LP3 VREF
+
+    vIO32WriteFldAlign(DDRPHY_B0_DQ3, 0x1, B0_DQ3_RG_ARDQ_RESETB_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ3, 0x1, B1_DQ3_RG_ARDQ_RESETB_B1);
+
+    mcDELAY_US(1);
+
+    //Ref clock should be 20M~30M, if MPLL=52M, Pre-divider should be set to 1
+    vIO32WriteFldMulti(DDRPHY_SHU_PLL8, P_Fld(0x0, SHU_PLL8_RG_RPHYPLL_POSDIV) | P_Fld(0x1, SHU_PLL8_RG_RPHYPLL_PREDIV));
+    //vIO32WriteFldAlign(DDRPHY_SHU2_PLL8, 0x0, SHU2_PLL8_RG_RPHYPLL_POSDIV);
+    //vIO32WriteFldAlign(DDRPHY_SHU3_PLL8, 0x0, SHU3_PLL8_RG_RPHYPLL_POSDIV);
+    //vIO32WriteFldAlign(DDRPHY_SHU4_PLL8, 0x0, SHU4_PLL8_RG_RPHYPLL_POSDIV);
+
+    mcDELAY_US(1);
+
+    vIO32WriteFldMulti(DDRPHY_SHU_PLL9, P_Fld(0x0, SHU_PLL9_RG_RPHYPLL_MONCK_EN)
+                | P_Fld(0x0, SHU_PLL9_RG_RPHYPLL_MONVC_EN)
+                | P_Fld(0x0, SHU_PLL9_RG_RPHYPLL_LVROD_EN)
+                | P_Fld(0x1, SHU_PLL9_RG_RPHYPLL_RST_DLY));
+    vIO32WriteFldMulti(DDRPHY_SHU_PLL11, P_Fld(0x0, SHU_PLL11_RG_RCLRPLL_MONCK_EN)
+                | P_Fld(0x0, SHU_PLL11_RG_RCLRPLL_MONVC_EN)
+                | P_Fld(0x0, SHU_PLL11_RG_RCLRPLL_LVROD_EN)
+                | P_Fld(0x1, SHU_PLL11_RG_RCLRPLL_RST_DLY));
+
+    mcDELAY_US(1);
+
+    //Ref clock should be 20M~30M, if MPLL=52M, Pre-divider should be set to 1
+    vIO32WriteFldMulti(DDRPHY_SHU_PLL10, P_Fld(0x0, SHU_PLL10_RG_RCLRPLL_POSDIV) | P_Fld(0x1, SHU_PLL10_RG_RCLRPLL_PREDIV));
+    //vIO32WriteFldAlign(DDRPHY_SHU2_PLL10, 0x0, SHU2_PLL10_RG_RCLRPLL_POSDIV);
+    //vIO32WriteFldAlign(DDRPHY_SHU3_PLL10, 0x0, SHU3_PLL10_RG_RCLRPLL_POSDIV);
+    //vIO32WriteFldAlign(DDRPHY_SHU4_PLL10, 0x0, SHU4_PLL10_RG_RCLRPLL_POSDIV);
+
+    mcDELAY_US(1);
+
+
+    ///TODO: MIDPI Init 1
+    vIO32WriteFldMulti(DDRPHY_PLL4, P_Fld(0x0, PLL4_RG_RPHYPLL_AD_MCK8X_EN)
+                | P_Fld(0x1, PLL4_PLL4_RFU)
+                | P_Fld(0x1, PLL4_RG_RPHYPLL_MCK8X_SEL));
+
+
+    mcDELAY_US(1);
+
+    //@Darren-vIO32WriteFldAlign(DDRPHY_SHU_PLL0, 0x3, SHU_PLL0_RG_RPHYPLL_TOP_REV); // debug1111, org:3 -> mdf:0
+    vIO32WriteFldMulti(DDRPHY_SHU_PLL0, P_Fld(0x1, SHU_PLL0_ADA_MCK8X_CHB_EN)
+                | P_Fld(0x1, SHU_PLL0_ADA_MCK8X_CHA_EN)); //@Darren+
+    //vIO32WriteFldAlign(DDRPHY_SHU2_PLL0, 0x3, SHU2_PLL0_RG_RPHYPLL_TOP_REV);
+    //vIO32WriteFldAlign(DDRPHY_SHU3_PLL0, 0x3, SHU3_PLL0_RG_RPHYPLL_TOP_REV);
+    //vIO32WriteFldAlign(DDRPHY_SHU4_PLL0, 0x3, SHU4_PLL0_RG_RPHYPLL_TOP_REV);
+
+    mcDELAY_US(1);
+
+
+    vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI1, 0x1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA);
+    vIO32WriteFldMulti(DDRPHY_B0_DQ3, P_Fld(0x1, B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0)
+                | P_Fld(0x1, B0_DQ3_RG_TX_ARDQ_EN_B0)
+                | P_Fld(0x1, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0));
+    vIO32WriteFldMulti(DDRPHY_B1_DQ3, P_Fld(0x1, B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1)
+                | P_Fld(0x1, B1_DQ3_RG_TX_ARDQ_EN_B1)
+                | P_Fld(0x1, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1));
+
+
+
+#if (fcFOR_CHIP_ID == fcLafite)
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0, 0x1, SHU_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU);//Move to DCM off setting
+    vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0 + SHIFT_TO_CHB_ADDR, 0x1, SHU_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU);//Move to DCM off setting
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+#endif
+
+    vIO32WriteFldMulti(DDRPHY_SHU_B0_DLL0, P_Fld(0x1, SHU_B0_DLL0_RG_ARDLL_PHDET_IN_SWAP_B0)
+                | P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_GAIN_B0)
+                | P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0)
+                | P_Fld(0x8, SHU_B0_DLL0_RG_ARDLL_P_GAIN_B0)
+                | P_Fld(0x1, SHU_B0_DLL0_RG_ARDLL_PHJUMP_EN_B0)
+                | P_Fld(0x1, SHU_B0_DLL0_RG_ARDLL_PHDIV_B0)
+                | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_B1_DLL0, P_Fld(0x1, SHU_B1_DLL0_RG_ARDLL_PHDET_IN_SWAP_B1)
+                | P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_GAIN_B1)
+                | P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1)
+                | P_Fld(0x8, SHU_B1_DLL0_RG_ARDLL_P_GAIN_B1)
+                | P_Fld(0x1, SHU_B1_DLL0_RG_ARDLL_PHJUMP_EN_B1)
+                | P_Fld(0x1, SHU_B1_DLL0_RG_ARDLL_PHDIV_B1)
+                | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1));
+
+    vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD5, 0x29, SHU_CA_CMD5_RG_RX_ARCMD_VREF_SEL);
+    //vIO32WriteFldAlign(DDRPHY_SHU2_CA_CMD5, 0x0, SHU2_CA_CMD5_RG_RX_ARCMD_VREF_SEL);
+    //vIO32WriteFldAlign(DDRPHY_SHU3_CA_CMD5, 0x0, SHU3_CA_CMD5_RG_RX_ARCMD_VREF_SEL);
+    //vIO32WriteFldAlign(DDRPHY_SHU4_CA_CMD5, 0x0, SHU4_CA_CMD5_RG_RX_ARCMD_VREF_SEL);
+    vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD0, P_Fld(0x1, SHU_CA_CMD0_RG_TX_ARCMD_PRE_EN)
+                | P_Fld(0x4, SHU_CA_CMD0_RG_TX_ARCLK_DRVN_PRE)
+                | P_Fld(0x1, SHU_CA_CMD0_RG_TX_ARCLK_PRE_EN));
+    //vIO32WriteFldMulti(DDRPHY_SHU2_CA_CMD0, P_Fld(0x1, SHU2_CA_CMD0_RG_TX_ARCMD_PRE_EN)
+    //            | P_Fld(0x4, SHU2_CA_CMD0_RG_TX_ARCLK_DRVN_PRE)
+    //            | P_Fld(0x1, SHU2_CA_CMD0_RG_TX_ARCLK_PRE_EN));
+    //vIO32WriteFldMulti(DDRPHY_SHU3_CA_CMD0, P_Fld(0x1, SHU3_CA_CMD0_RG_TX_ARCMD_PRE_EN)
+    //            | P_Fld(0x4, SHU3_CA_CMD0_RG_TX_ARCLK_DRVN_PRE)
+    //            | P_Fld(0x1, SHU3_CA_CMD0_RG_TX_ARCLK_PRE_EN));
+    //vIO32WriteFldMulti(DDRPHY_SHU4_CA_CMD0, P_Fld(0x1, SHU4_CA_CMD0_RG_TX_ARCMD_PRE_EN)
+    //            | P_Fld(0x4, SHU4_CA_CMD0_RG_TX_ARCLK_DRVN_PRE)
+    //            | P_Fld(0x1, SHU4_CA_CMD0_RG_TX_ARCLK_PRE_EN));
+#if (fcFOR_CHIP_ID == fcLafite)
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD6, 0x0, SHU_CA_CMD6_RG_TX_ARCMD_SER_MODE);
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+#endif
+    //vIO32WriteFldAlign(DDRPHY_SHU2_CA_CMD6, 0x3, SHU2_CA_CMD6_RG_ARPI_RESERVE_CA);
+    //vIO32WriteFldAlign(DDRPHY_SHU3_CA_CMD6, 0x3, SHU3_CA_CMD6_RG_ARPI_RESERVE_CA);
+    //vIO32WriteFldAlign(DDRPHY_SHU4_CA_CMD6, 0x3, SHU4_CA_CMD6_RG_ARPI_RESERVE_CA);
+    //vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD3, 0x4e1, SHU_CA_CMD3_RG_ARCMD_REV);
+    //vIO32WriteFldAlign(DDRPHY_SHU2_CA_CMD7, 0x4e1, SHU2_CA_CMD7_RG_ARCMD_REV);
+    //vIO32WriteFldAlign(DDRPHY_SHU3_CA_CMD7, 0x4e1, SHU3_CA_CMD7_RG_ARCMD_REV);
+    //vIO32WriteFldAlign(DDRPHY_SHU4_CA_CMD7, 0x4e1, SHU4_CA_CMD7_RG_ARCMD_REV);
+    //vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x00, SHU_B0_DQ7_RG_ARDQ_REV_B0)
+    //            | P_Fld(0x0, SHU_B0_DQ7_DQ_REV_B0_BIT_05));
+    //vIO32WriteFldAlign(DDRPHY_SHU2_B0_DQ7, 0x20, SHU2_B0_DQ7_RG_ARDQ_REV_B0);
+    //vIO32WriteFldAlign(DDRPHY_SHU3_B0_DQ7, 0x20, SHU3_B0_DQ7_RG_ARDQ_REV_B0);
+    //vIO32WriteFldAlign(DDRPHY_SHU4_B0_DQ7, 0x20, SHU4_B0_DQ7_RG_ARDQ_REV_B0);
+    //vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ7, P_Fld(0x00, SHU_B1_DQ7_RG_ARDQ_REV_B1)
+    //            | P_Fld(0x0, SHU_B1_DQ7_DQ_REV_B1_BIT_05));
+
+ //lynx added
+    //vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x0, SHU_B0_DQ7_RG_ARDQ_REV_B0);
+    //vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x0, SHU_B1_DQ7_RG_ARDQ_REV_B1);
+ //
+    //vIO32WriteFldAlign(DDRPHY_SHU2_B1_DQ7, 0x20, SHU2_B1_DQ7_RG_ARDQ_REV_B1);
+    //vIO32WriteFldAlign(DDRPHY_SHU3_B1_DQ7, 0x20, SHU3_B1_DQ7_RG_ARDQ_REV_B1);
+    //vIO32WriteFldAlign(DDRPHY_SHU4_B1_DQ7, 0x20, SHU4_B1_DQ7_RG_ARDQ_REV_B1);
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ6, 0x0, SHU_B0_DQ6_RG_TX_ARDQ_SER_MODE_B0);
+    //vIO32WriteFldAlign(DDRPHY_SHU2_B0_DQ6, 0x1, SHU2_B0_DQ6_RG_ARPI_RESERVE_B0);
+    //vIO32WriteFldAlign(DDRPHY_SHU3_B0_DQ6, 0x1, SHU3_B0_DQ6_RG_ARPI_RESERVE_B0);
+    //vIO32WriteFldAlign(DDRPHY_SHU4_B0_DQ6, 0x1, SHU4_B0_DQ6_RG_ARPI_RESERVE_B0);
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ6, 0x0, SHU_B1_DQ6_RG_TX_ARDQ_SER_MODE_B1);
+    //vIO32WriteFldAlign(DDRPHY_SHU2_B1_DQ6, 0x1, SHU2_B1_DQ6_RG_ARPI_RESERVE_B1);
+    //vIO32WriteFldAlign(DDRPHY_SHU3_B1_DQ6, 0x1, SHU3_B1_DQ6_RG_ARPI_RESERVE_B1);
+    //vIO32WriteFldAlign(DDRPHY_SHU4_B1_DQ6, 0x1, SHU4_B1_DQ6_RG_ARPI_RESERVE_B1);
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    vIO32WriteFldMulti(DDRPHY_MISC_SHU_OPT, P_Fld(0x1, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN)
+                | P_Fld(0x1, MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN)
+                | P_Fld(0x2, MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN)
+                | P_Fld(0x1, MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN)
+                | P_Fld(0x2, MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN)
+                | P_Fld(0x1, MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN));
+    vIO32WriteFldMulti(DDRPHY_MISC_SHU_OPT + SHIFT_TO_CHB_ADDR, P_Fld(0x2, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN)
+                | P_Fld(0x1, MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN)
+                | P_Fld(0x2, MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN)
+                | P_Fld(0x1, MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN)
+                | P_Fld(0x2, MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN)
+                | P_Fld(0x1, MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN));
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+
+    mcDELAY_US(9);
+
+#if (fcFOR_CHIP_ID == fcLafite)
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    vIO32WriteFldMulti(DDRPHY_SHU_CA_DLL1, P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA));
+    vIO32WriteFldMulti(DDRPHY_SHU_CA_DLL1 + SHIFT_TO_CHB_ADDR, P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA)
+                | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA));//CH_B CA slave mode
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+#endif
+    vIO32WriteFldMulti(DDRPHY_SHU_B0_DLL1, P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_B1_DLL1, P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B1));
+
+    mcDELAY_US(1);
+
+    vIO32WriteFldAlign(DDRPHY_PLL2, 0x0, PLL2_RG_RCLRPLL_EN);
+    //vIO32WriteFldAlign(DDRPHY_SHU_PLL4, 0xff, SHU_PLL4_RG_RPHYPLL_RESERVED);
+    //vIO32WriteFldAlign(DDRPHY_SHU_PLL6, 0xff, SHU_PLL6_RG_RCLRPLL_RESERVED);
+    vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL0, 0xf, MISC_CG_CTRL0_CLK_MEM_DFS_CFG);
+
+    mcDELAY_US(1);
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    DDRPhyPLLSetting(p);
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+
+    //rollback tMRRI design change
+#if ENABLE_TMRRI_NEW_MODE
+    //fix rank at 0 to trigger new TMRRI setting
+    vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0, RKCFG_TXRANK);
+    vIO32WriteFldAlign(DRAMC_REG_RKCFG, 1, RKCFG_TXRANKFIX);
+    vIO32WriteFldAlign(DRAMC_REG_DRSCTRL, 0x0, DRSCTRL_RK_SCINPUT_OPT);// new mode, HW_MRR: R_DMMRRRK, SW_MRR: R_DMMRSRK
+    vIO32WriteFldMulti(DRAMC_REG_DRAMCTRL, P_Fld(0x0, DRAMCTRL_MRRIOPT) | P_Fld(0x0, DRAMCTRL_TMRRIBYRK_DIS) | P_Fld(0x1, DRAMCTRL_TMRRICHKDIS));
+    vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_SC_PG_UPD_OPT);
+    vIO32WriteFldMulti(DRAMC_REG_SPCMDCTRL, P_Fld(0x0, SPCMDCTRL_SC_PG_MPRW_DIS) | P_Fld(0x0, SPCMDCTRL_SC_PG_STCMD_AREF_DIS)
+                                             | P_Fld(0x0, SPCMDCTRL_SC_PG_OPT2_DIS) | P_Fld(0x0, SPCMDCTRL_SC_PG_MAN_DIS));
+    vIO32WriteFldMulti(DRAMC_REG_MPC_OPTION, P_Fld(0x1, MPC_OPTION_ZQ_BLOCKALE_OPT) | P_Fld(0x1, MPC_OPTION_MPC_BLOCKALE_OPT2) |
+                                               P_Fld(0x1, MPC_OPTION_MPC_BLOCKALE_OPT1) | P_Fld(0x1, MPC_OPTION_MPC_BLOCKALE_OPT));
+    //fix rank at 0 to trigger new TMRRI setting
+    vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0, RKCFG_TXRANK);
+    vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0, RKCFG_TXRANKFIX);
+#else
+    vIO32WriteFldAlign(DRAMC_REG_DRSCTRL, 0x1, DRSCTRL_RK_SCINPUT_OPT);// old mode, HW/SW MRR: R_DMMRRRK
+    vIO32WriteFldMulti(DRAMC_REG_DRAMCTRL, P_Fld(0x1, DRAMCTRL_MRRIOPT) | P_Fld(0x1, DRAMCTRL_TMRRIBYRK_DIS) | P_Fld(0x0, DRAMCTRL_TMRRICHKDIS));
+    vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x0, SPCMDCTRL_SC_PG_UPD_OPT);
+    vIO32WriteFldMulti(DRAMC_REG_SPCMDCTRL, P_Fld(0x1, SPCMDCTRL_SC_PG_MPRW_DIS) | P_Fld(0x1, SPCMDCTRL_SC_PG_STCMD_AREF_DIS)
+                                             | P_Fld(0x1, SPCMDCTRL_SC_PG_OPT2_DIS) | P_Fld(0x1, SPCMDCTRL_SC_PG_MAN_DIS));
+#endif
+    vIO32WriteFldAlign(DRAMC_REG_CKECTRL, 0x1, CKECTRL_RUNTIMEMRRCKEFIX);//Set Run time MRR CKE fix to 1 in tMRRI old mode to avoid no ACK from precharge all
+    vIO32WriteFldAlign(DRAMC_REG_CKECTRL, 0x0, CKECTRL_RUNTIMEMRRMIODIS);
+
+    vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1);
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(0xf, SHURK1_DQSIEN_R1DQS3IEN)
+                | P_Fld(0xf, SHURK1_DQSIEN_R1DQS2IEN)
+                | P_Fld(0xf, SHURK1_DQSIEN_R1DQS1IEN)
+                | P_Fld(0xf, SHURK1_DQSIEN_R1DQS0IEN));
+    vIO32WriteFldMulti(DRAMC_REG_STBCAL1, P_Fld(0x0, STBCAL1_DLLFRZ_MON_PBREF_OPT)
+                | P_Fld(0x1, STBCAL1_STB_FLAGCLR)
+                | P_Fld(0x1, STBCAL1_STBCNT_SHU_RST_EN) // from HJ review bring-up setting
+                | P_Fld(0x1, STBCAL1_STBCNT_MODESEL));
+    /* Darren-
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG_RETRY, P_Fld(0x1, SHU_DQSG_RETRY_R_RETRY_USE_BURST_MDOE)
+                | P_Fld(0x1, SHU_DQSG_RETRY_R_RDY_SEL_DLE)
+                | P_Fld(0x6, SHU_DQSG_RETRY_R_DQSIENLAT)
+                | P_Fld(0x1, SHU_DQSG_RETRY_R_RETRY_ONCE));
+    */
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DRVING1, P_Fld(0xa, SHU_DRVING1_DQSDRVP2) | P_Fld(0xa, SHU_DRVING1_DQSDRVN2)
+                | P_Fld(0xa, SHU_DRVING1_DQSDRVP1) | P_Fld(0xa, SHU_DRVING1_DQSDRVN1)
+                | P_Fld(0xa, SHU_DRVING1_DQDRVP2) | P_Fld(0xa, SHU_DRVING1_DQDRVN2));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DRVING2, P_Fld(0xa, SHU_DRVING2_DQDRVP1) | P_Fld(0xa, SHU_DRVING2_DQDRVN1)
+                | P_Fld(0xa, SHU_DRVING2_CMDDRVP2) | P_Fld(0xa, SHU_DRVING2_CMDDRVN2)
+                | P_Fld(0xa, SHU_DRVING2_CMDDRVP1) | P_Fld(0xa, SHU_DRVING2_CMDDRVN1));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DRVING3, P_Fld(0xa, SHU_DRVING3_DQSODTP2) | P_Fld(0xa, SHU_DRVING3_DQSODTN2)
+                | P_Fld(0xa, SHU_DRVING3_DQSODTP) | P_Fld(0xa, SHU_DRVING3_DQSODTN)
+                | P_Fld(0xa, SHU_DRVING3_DQODTP2) | P_Fld(0xa, SHU_DRVING3_DQODTN2));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DRVING4, P_Fld(0xa, SHU_DRVING4_DQODTP1) | P_Fld(0xa, SHU_DRVING4_DQODTN1)
+                | P_Fld(0xa, SHU_DRVING4_CMDODTP2) | P_Fld(0xa, SHU_DRVING4_CMDODTN2)
+                | P_Fld(0xa, SHU_DRVING4_CMDODTP1) | P_Fld(0xa, SHU_DRVING4_CMDODTN1));
+    /*
+    vIO32WriteFldMulti(DRAMC_REG_SHU2_DRVING1, P_Fld(0x14a, SHU2_DRVING1_DQSDRV2)
+                | P_Fld(0x14a, SHU2_DRVING1_DQSDRV1)
+                | P_Fld(0x14a, SHU2_DRVING1_DQDRV2));
+    vIO32WriteFldMulti(DRAMC_REG_SHU2_DRVING2, P_Fld(0x14a, SHU2_DRVING2_DQDRV1)
+                | P_Fld(0x14a, SHU2_DRVING2_CMDDRV2)
+                | P_Fld(0x14a, SHU2_DRVING2_CMDDRV1));
+    vIO32WriteFldMulti(DRAMC_REG_SHU2_DRVING3, P_Fld(0x14a, SHU2_DRVING3_DQSODT2)
+                | P_Fld(0x14a, SHU2_DRVING3_DQSODT1)
+                | P_Fld(0x14a, SHU2_DRVING3_DQODT2));
+    vIO32WriteFldMulti(DRAMC_REG_SHU2_DRVING4, P_Fld(0x14a, SHU2_DRVING4_DQODT1)
+                | P_Fld(0x14a, SHU2_DRVING4_CMDODT2)
+                | P_Fld(0x14a, SHU2_DRVING4_CMDODT1));
+    vIO32WriteFldMulti(DRAMC_REG_SHU3_DRVING1, P_Fld(0x14a, SHU3_DRVING1_DQSDRV2)
+                | P_Fld(0x14a, SHU3_DRVING1_DQSDRV1)
+                | P_Fld(0x14a, SHU3_DRVING1_DQDRV2));
+    vIO32WriteFldMulti(DRAMC_REG_SHU3_DRVING2, P_Fld(0x14a, SHU3_DRVING2_DQDRV1)
+                | P_Fld(0x14a, SHU3_DRVING2_CMDDRV2)
+                | P_Fld(0x14a, SHU3_DRVING2_CMDDRV1));
+    vIO32WriteFldMulti(DRAMC_REG_SHU3_DRVING3, P_Fld(0x14a, SHU3_DRVING3_DQSODT2)
+                | P_Fld(0x14a, SHU3_DRVING3_DQSODT1)
+                | P_Fld(0x14a, SHU3_DRVING3_DQODT2));
+    vIO32WriteFldMulti(DRAMC_REG_SHU3_DRVING4, P_Fld(0x14a, SHU3_DRVING4_DQODT1)
+                | P_Fld(0x14a, SHU3_DRVING4_CMDODT2)
+                | P_Fld(0x14a, SHU3_DRVING4_CMDODT1));
+    vIO32WriteFldMulti(DRAMC_REG_SHU4_DRVING1, P_Fld(0x14a, SHU4_DRVING1_DQSDRV2)
+                | P_Fld(0x14a, SHU4_DRVING1_DQSDRV1)
+                | P_Fld(0x14a, SHU4_DRVING1_DQDRV2));
+    vIO32WriteFldMulti(DRAMC_REG_SHU4_DRVING2, P_Fld(0x14a, SHU4_DRVING2_DQDRV1)
+                | P_Fld(0x14a, SHU4_DRVING2_CMDDRV2)
+                | P_Fld(0x14a, SHU4_DRVING2_CMDDRV1));
+    */
+    //  *((UINT32P)(DRAMC1_AO_BASE + 0x08a8)) = 0x14a5294a;
+    //  *((UINT32P)(DRAMC1_AO_BASE + 0x08ac)) = 0x14a5294a;
+    //  *((UINT32P)(DRAMC1_AO_BASE + 0x08b0)) = 0x14a5294a;
+    //  *((UINT32P)(DRAMC1_AO_BASE + 0x08b4)) = 0x14a5294a;
+    //  *((UINT32P)(DRAMC1_AO_BASE + 0x0ea8)) = 0x14a5294a;
+    //  *((UINT32P)(DRAMC1_AO_BASE + 0x0eac)) = 0x14a5294a;
+    //  *((UINT32P)(DRAMC1_AO_BASE + 0x0eb0)) = 0x14a5294a;
+    //  *((UINT32P)(DRAMC1_AO_BASE + 0x0eb4)) = 0x14a5294a;
+    //  *((UINT32P)(DRAMC1_AO_BASE + 0x14a8)) = 0x14a5294a;
+    //  *((UINT32P)(DRAMC1_AO_BASE + 0x14ac)) = 0x14a5294a;
+    //  *((UINT32P)(DRAMC1_AO_BASE + 0x14b0)) = 0x14a5294a;
+    //  *((UINT32P)(DRAMC1_AO_BASE + 0x14b4)) = 0x14a5294a;
+    //  *((UINT32P)(DRAMC1_AO_BASE + 0x1aa8)) = 0x14a5294a;
+    //  *((UINT32P)(DRAMC1_AO_BASE + 0x1aac)) = 0x14a5294a;
+    vIO32WriteFldMulti(DRAMC_REG_SHUCTRL2, P_Fld(0x0, SHUCTRL2_HWSET_WLRL)
+                | P_Fld(0x1, SHUCTRL2_SHU_PERIOD_GO_ZERO_CNT)
+                | P_Fld(0x1, SHUCTRL2_R_DVFS_OPTION)
+                | P_Fld(0x1, SHUCTRL2_R_DVFS_PARK_N)
+                | P_Fld(0x1, SHUCTRL2_R_DVFS_DLL_CHA)
+                | P_Fld(0xa, SHUCTRL2_R_DLL_IDLE));
+    vIO32WriteFldAlign(DRAMC_REG_DVFSDLL, 0x1, DVFSDLL_DLL_LOCK_SHU_EN);
+    vIO32WriteFldMulti(DRAMC_REG_DDRCONF0, P_Fld(0x1, DDRCONF0_LPDDR4EN)
+                | P_Fld(0x1, DDRCONF0_BC4OTF)
+                | P_Fld(0x1, DDRCONF0_BK8EN));
+    vIO32WriteFldMulti(DRAMC_REG_STBCAL2, P_Fld(0x1, STBCAL2_STB_GERR_B01)
+                | P_Fld(0x1, STBCAL2_STB_GERRSTOP)
+                | P_Fld(0x1, EYESCAN_EYESCAN_RD_SEL_OPT));
+    vIO32WriteFldAlign(DRAMC_REG_STBCAL2, 0x1, STBCAL2_STB_GERR_RST);
+    vIO32WriteFldAlign(DRAMC_REG_STBCAL2, 0x0, STBCAL2_STB_GERR_RST);
+    vIO32WriteFldAlign(DRAMC_REG_CLKAR, 0x1, CLKAR_PSELAR);
+    vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x1, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x1, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1);
+    vIO32WriteFldAlign(DDRPHY_CA_CMD10, 0x0, CA_CMD10_R_DMDQSIEN_RDSEL_LAT_CA);
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        vIO32WriteFldMulti(DDRPHY_MISC_CTRL0, P_Fld(0x1, MISC_CTRL0_R_STBENCMP_DIV4CK_EN)
+                    | P_Fld(0x1, MISC_CTRL0_R_DMDQSIEN_FIFO_EN)
+                    | P_Fld(0x1, MISC_CTRL0_R_DMSTBEN_OUTSEL)
+                    | P_Fld(0xf, MISC_CTRL0_R_DMDQSIEN_SYNCOPT));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DDRPHY_MISC_CTRL0, P_Fld(0x1, MISC_CTRL0_R_STBENCMP_DIV4CK_EN)
+                    | P_Fld(0x1, MISC_CTRL0_R_DMDQSIEN_FIFO_EN)
+                    | P_Fld(0x1, MISC_CTRL0_R_DMSTBEN_OUTSEL)
+                    | P_Fld(0xf, MISC_CTRL0_R_DMDQSIEN_SYNCOPT));
+    }
+    //vIO32WriteFldMulti(DDRPHY_MISC_CTRL1, P_Fld(0x1, MISC_CTRL1_R_DMDA_RRESETB_E) //Already set in vDramcInit_PreSettings()
+    vIO32WriteFldMulti(DDRPHY_MISC_CTRL1, P_Fld(0x1, MISC_CTRL1_R_DMDQSIENCG_EN)
+                | P_Fld(0x1, MISC_CTRL1_R_DM_TX_ARCMD_OE)
+#if ENABLE_PINMUX_FOR_RANK_SWAP
+                | P_Fld(0x1, MISC_CTRL1_R_RK_PINMUXSWAP_EN)
+#endif
+                | P_Fld(0x1, MISC_CTRL1_R_DM_TX_ARCLK_OE));
+    vIO32WriteFldAlign(DDRPHY_B0_RXDVS0, 1, B0_RXDVS0_R_HWSAVE_MODE_ENA_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_RXDVS0, 1, B1_RXDVS0_R_HWSAVE_MODE_ENA_B1);
+    vIO32WriteFldAlign(DDRPHY_CA_RXDVS0, 0, CA_RXDVS0_R_HWSAVE_MODE_ENA_CA);
+
+    vIO32WriteFldAlign(DDRPHY_CA_CMD7, 0x0, CA_CMD7_RG_TX_ARCMD_PULL_DN);
+    vIO32WriteFldAlign(DDRPHY_CA_CMD7, 0x0, CA_CMD7_RG_TX_ARCS_PULL_DN); // Added by Lingyun.Wu, 11-15
+    vIO32WriteFldAlign(DDRPHY_B0_DQ7, 0x0, B0_DQ7_RG_TX_ARDQ_PULL_DN_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ7, 0x0, B1_DQ7_RG_TX_ARDQ_PULL_DN_B1);
+    //vIO32WriteFldAlign(DDRPHY_CA_CMD8, 0x0, CA_CMD8_RG_TX_RRESETB_PULL_DN); //Already set in vDramcInit_PreSettings()
+
+    //For 1:8 mode start=================
+    // 1:8 mode
+    vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x1, SHU_CONF0_DM64BITEN)
+                | P_Fld(0x0, SHU_CONF0_FDIV2)
+                | P_Fld(0x1, SHU_CONF0_FREQDIV4)
+                | P_Fld(0x1, SHU_CONF0_DUALSCHEN)
+                | P_Fld(0x0, SHU_CONF0_WDATRGO)
+                | P_Fld(u1MaType, SHU_CONF0_MATYPE)
+                | P_Fld(0x1, SHU_CONF0_BL4)
+                | P_Fld(0x1, SHU_CONF0_REFTHD)
+                | P_Fld(0x1, SHU_CONF0_ADVPREEN)
+                | P_Fld(0x3f, SHU_CONF0_DMPGTIM));
+
+    vIO32WriteFldAlign(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, 0x5, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_DYN_GATING_SEL);
+    vIO32WriteFldAlign(DRAMC_REG_SHU_SELPH_CA1, 0x0, SHU_SELPH_CA1_TXDLY_CKE);
+    vIO32WriteFldAlign(DRAMC_REG_SHU_SELPH_CA2, 0x0, SHU_SELPH_CA2_TXDLY_CKE1);
+
+#if (fcFOR_CHIP_ID == fcLafite)
+    if (vGet_Div_Mode(p) == DIV4_MODE)
+    {
+        u1TAIL_LAT = 1;
+    }
+    else
+ //DIV8_MODE
+    {
+        u1TAIL_LAT = 0;
+    }
+
+    //PICG old mode
+    vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK0_SEL_P0)
+                | P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK0_SEL_P1)
+                | P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT));
+
+    //PICG_DQSIEN old/new project have same settings
+    vIO32WriteFldMulti(DRAMC_REG_SHU_STBCAL, P_Fld(u1TAIL_LAT, SHU_STBCAL_R1_DQSIEN_PICG_TAIL_EXT_LAT) //TAIL should be set as same value by old/new mode, no matter it is old or new mode
+                | P_Fld(u1TAIL_LAT, SHU_STBCAL_R0_DQSIEN_PICG_TAIL_EXT_LAT) //TAIL should be set as same value by old/new mode, no matter it is old or new mode
+                | P_Fld(u1TAIL_LAT, SHU_STBCAL_DQSIEN_RX_SELPH_OPT));
+
+    //RX_IN_GATE_EN old mode
+    vIO32WriteFldMulti(DRAMC_REG_SHU_PHY_RX_CTRL, P_Fld(0x0, SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL)
+                | P_Fld(0x0, SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD));
+#endif
+    //For 1:8 mode end=================
+
+    vIO32WriteFldMulti(DRAMC_REG_SHU_ODTCTRL, P_Fld(0x1, SHU_ODTCTRL_RODTE)
+                | P_Fld(0x1, SHU_ODTCTRL_RODTE2)
+                | P_Fld(0x1, SHU_ODTCTRL_TWODT)
+                //| P_Fld(0x5, SHU_ODTCTRL_RODT) //Set in UpdateACTimingReg()
+                | P_Fld(0x1, SHU_ODTCTRL_WOEN)
+                | P_Fld(0x1, SHU_ODTCTRL_ROEN));
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x1, SHU_B0_DQ7_R_DMRODTEN_B0);
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x1, SHU_B1_DQ7_R_DMRODTEN_B1);
+    vIO32WriteFldAlign(DRAMC_REG_REFCTRL0, 0x5, REFCTRL0_REF_PREGATE_CNT);
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1)
+                | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS)
+                | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS)
+                | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE)
+                | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET)
+                | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT)
+                | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS));
+
+    if (p->frequency < 1333)
+        u1TXDLY_CMD = 0x7;
+    else if (p->frequency < 1600)
+        u1TXDLY_CMD = 0x8;
+    else if (p->frequency < 1866)
+        u1TXDLY_CMD = 0x9;
+    else if (p->frequency < 2133)
+        u1TXDLY_CMD = 0xA;
+    else
+        u1TXDLY_CMD = 0xB;
+
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(u1TXDLY_CMD, SHU_SELPH_CA2_TXDLY_CMD)
+                | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2)
+                | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1)
+                | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7)
+                | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6)
+                | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5)
+                | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4)
+                | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3)
+                | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2)
+                | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1)
+                | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15)
+                | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14)
+                | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13)
+                | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12)
+                | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11)
+                | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10)
+                | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9)
+                | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8));
+    vIO32WriteFldAlign(DRAMC_REG_SHU_SELPH_CA5, 0x0, SHU_SELPH_CA5_DLY_ODT);
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)
+                | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS2)
+                | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS1)
+                | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS0)
+                | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_DQS3)
+                | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_DQS2)
+                | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_DQS1)
+                | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_DQS0));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS3)
+                | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS2)
+                | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS1)
+                | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS0)
+                | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS3)
+                | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS2)
+                | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS1)
+                | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
+                | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
+                | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
+                | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
+                | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ3)
+                | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ2)
+                | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ1)
+                | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
+                | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
+                | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
+                | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
+                | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM3)
+                | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM2)
+                | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM1)
+                | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ3)
+                | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ2)
+                | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ1)
+                | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ0)
+                | P_Fld(0x6, SHURK0_SELPH_DQ2_DLY_DQ3)
+                | P_Fld(0x6, SHURK0_SELPH_DQ2_DLY_DQ2)
+                | P_Fld(0x6, SHURK0_SELPH_DQ2_DLY_DQ1)
+                | P_Fld(0x6, SHURK0_SELPH_DQ2_DLY_DQ0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ3, P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_OEN_DQM3)
+                | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_OEN_DQM2)
+                | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_OEN_DQM1)
+                | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_OEN_DQM0)
+                | P_Fld(0x6, SHURK0_SELPH_DQ3_DLY_DQM3)
+                | P_Fld(0x6, SHURK0_SELPH_DQ3_DLY_DQM2)
+                | P_Fld(0x6, SHURK0_SELPH_DQ3_DLY_DQM1)
+                | P_Fld(0x6, SHURK0_SELPH_DQ3_DLY_DQM0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
+                | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
+                | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
+                | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
+                | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
+                | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
+                | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
+                | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
+                | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
+                | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
+                | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
+                | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
+                | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
+                | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
+                | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ2, P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3)
+                | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2)
+                | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1)
+                | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0)
+                | P_Fld(0x6, SHURK1_SELPH_DQ2_DLY_R1DQ3)
+                | P_Fld(0x6, SHURK1_SELPH_DQ2_DLY_R1DQ2)
+                | P_Fld(0x6, SHURK1_SELPH_DQ2_DLY_R1DQ1)
+                | P_Fld(0x6, SHURK1_SELPH_DQ2_DLY_R1DQ0));
+    vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ3, P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3)
+                | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2)
+                | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1)
+                | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0)
+                | P_Fld(0x6, SHURK1_SELPH_DQ3_DLY_R1DQM3)
+                | P_Fld(0x6, SHURK1_SELPH_DQ3_DLY_R1DQM2)
+                | P_Fld(0x6, SHURK1_SELPH_DQ3_DLY_R1DQM1)
+                | P_Fld(0x6, SHURK1_SELPH_DQ3_DLY_R1DQM0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(0x1a, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1)
+                | P_Fld(0x1a, SHU_R0_B1_DQ7_RK0_ARPI_DQ_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(0x1a, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0)
+                | P_Fld(0x1a, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ7, P_Fld(0x14, SHU_R1_B1_DQ7_RK1_ARPI_DQM_B1)
+                | P_Fld(0x14, SHU_R1_B1_DQ7_RK1_ARPI_DQ_B1));
+    vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ7, P_Fld(0x14, SHU_R1_B0_DQ7_RK1_ARPI_DQM_B0)
+                | P_Fld(0x14, SHU_R1_B0_DQ7_RK1_ARPI_DQ_B0));
+
+    mcDELAY_US(1);
+
+    vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x1, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1);
+    vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x1, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0);
+    vIO32WriteFldAlign(DDRPHY_B0_DQ6, 0x2, B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0);
+    vIO32WriteFldAlign(DDRPHY_B1_DQ6, 0x2, B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1);
+    vIO32WriteFldAlign(DRAMC_REG_STBCAL, 0x1, STBCAL_DQSIENMODE);
+    vIO32WriteFldMulti(DRAMC_REG_SREFCTRL, P_Fld(0x0, SREFCTRL_SREF_HW_EN)
+                | P_Fld(0x8, SREFCTRL_SREFDLY));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x3, SHU_CKECTRL_SREF_CK_DLY)
+                | P_Fld(0x3, SHU_CKECTRL_TCKESRX));
+                //| P_Fld(0x3, SHU_CKECTRL_CKEPRD));
+    vIO32WriteFldMulti(DRAMC_REG_SHU_PIPE, P_Fld(0x1, SHU_PIPE_READ_START_EXTEND1)
+                | P_Fld(0x1, SHU_PIPE_DLE_LAST_EXTEND1));
+    vIO32WriteFldMulti(DRAMC_REG_CKECTRL, P_Fld(0x1, CKECTRL_CKEON)
+                | P_Fld(0x1, CKECTRL_CKETIMER_SEL));
+    vIO32WriteFldMulti(DRAMC_REG_RKCFG, P_Fld(0x1, RKCFG_CKE2RANK)
+                | P_Fld(0x1, RKCFG_CKE2RANK_OPT2)); // Darren for CKE dependent
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHU_CONF2, P_Fld(0x1, SHU_CONF2_WPRE2T)
+                    | P_Fld(0x7, SHU_CONF2_DCMDLYREF));
+                    //| P_Fld(0x64, SHU_CONF2_FSPCHG_PRDCNT)); //ACTiming related -> set in UpdateACTiming_Reg()
+        vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_CLR_EN);
+        //vIO32WriteFldAlign(DRAMC_REG_SHU_SCINTV, 0xf, SHU_SCINTV_MRW_INTV); (Set in UpdateACTimingReg())
+        vIO32WriteFldAlign(DRAMC_REG_SHUCTRL1, 0x40, SHUCTRL1_FC_PRDCNT);
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHU_CONF2, P_Fld(0x1, SHU_CONF2_WPRE2T)
+                    | P_Fld(0x7, SHU_CONF2_DCMDLYREF));
+                    //| P_Fld(0x64, SHU_CONF2_FSPCHG_PRDCNT)); //ACTiming related -> set in UpdateACTiming_Reg()
+        vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_CLR_EN);
+        //vIO32WriteFldAlign(DRAMC_REG_SHU_SCINTV, 0xf, SHU_SCINTV_MRW_INTV); (Set in UpdateACTimingReg())
+        vIO32WriteFldAlign(DRAMC_REG_SHUCTRL1, 0x40, SHUCTRL1_FC_PRDCNT);
+    }
+    vIO32WriteFldAlign(DRAMC_REG_SHUCTRL, 0x1, SHUCTRL_LPSM_BYPASS_B);
+    vIO32WriteFldMulti(DRAMC_REG_REFCTRL1, P_Fld(0x0, REFCTRL1_SREF_PRD_OPT) | P_Fld(0x0, REFCTRL1_PSEL_OPT1) | P_Fld(0x0, REFCTRL1_PSEL_OPT2) | P_Fld(0x0, REFCTRL1_PSEL_OPT3));
+    //vIO32WriteFldAlign(DDRPHY_SHU_PLL4, 0xfe, SHU_PLL4_RG_RPHYPLL_RESERVED);
+    //vIO32WriteFldAlign(DDRPHY_SHU_PLL6, 0xfe, SHU_PLL6_RG_RCLRPLL_RESERVED);
+    vIO32WriteFldMulti(DRAMC_REG_REFRATRE_FILTER, P_Fld(0x1, REFRATRE_FILTER_PB2AB_OPT) | P_Fld(0x0, REFRATRE_FILTER_PB2AB_OPT1));
+
+#if !APPLY_LP4_POWER_INIT_SEQUENCE
+    vIO32WriteFldAlign(DDRPHY_MISC_CTRL1, 0x1, MISC_CTRL1_R_DMDA_RRESETB_I);
+#endif
+    vIO32WriteFldAlign(DRAMC_REG_DRAMCTRL, 0x0, DRAMCTRL_CLKWITRFC);
+    vIO32WriteFldMulti(DRAMC_REG_MISCTL0, P_Fld(0x1, MISCTL0_REFP_ARB_EN2)
+                | P_Fld(0x1, MISCTL0_PRE_DLE_VLD_OPT) // MISCTL0_PRE_DLE_VLD_OPT from Chris review
+                | P_Fld(0x1, MISCTL0_PBC_ARB_EN)
+                | P_Fld(0x1, MISCTL0_REFA_ARB_EN2));
+    vIO32WriteFldMulti(DRAMC_REG_PERFCTL0, P_Fld(0x1, PERFCTL0_MWHPRIEN)
+                //| P_Fld(0x1, PERFCTL0_RWSPLIT) //Set in UpdateInitialSettings_LP4()
+                | P_Fld(0x1, PERFCTL0_WFLUSHEN)
+                | P_Fld(0x1, PERFCTL0_EMILLATEN)
+                | P_Fld(0x1, PERFCTL0_RWAGEEN)
+                | P_Fld(0x1, PERFCTL0_RWLLATEN)
+                | P_Fld(0x1, PERFCTL0_RWHPRIEN)
+                | P_Fld(0x1, PERFCTL0_RWOFOEN)
+                | P_Fld(0x1, PERFCTL0_DISRDPHASE1));
+    vIO32WriteFldAlign(DRAMC_REG_ARBCTL, 0x80, ARBCTL_MAXPENDCNT);
+    vIO32WriteFldMulti(DRAMC_REG_PADCTRL, P_Fld(0x1, PADCTRL_DQIENLATEBEGIN)
+                | P_Fld(0x1, PADCTRL_DQIENQKEND));
+    vIO32WriteFldAlign(DRAMC_REG_DRAMC_PD_CTRL, 0x1, DRAMC_PD_CTRL_DCMREF_OPT);
+    vIO32WriteFldMulti(DRAMC_REG_CLKCTRL, P_Fld(0x1, CLKCTRL_CLK_EN_1)
+                | P_Fld(0x1, CLKCTRL_CLK_EN_0)); // CLK_EN_0 from Jouling review
+    vIO32WriteFldMulti(DRAMC_REG_REFCTRL0, P_Fld(0x4, REFCTRL0_DISBYREFNUM)
+                | P_Fld(0x1, REFCTRL0_DLLFRZ));
+#if 0 //CATRAIN_INTV, CATRAINLAT: Correct values are set in UpdateACTimingReg( )
+    vIO32WriteFldMulti(DRAMC_REG_CATRAINING1, P_Fld(0xff, CATRAINING1_CATRAIN_INTV)
+                | P_Fld(0x0, CATRAINING1_CATRAINLAT));
+#endif
+#if 0
+    vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x6, SHU_RANKCTL_RANKINCTL_PHY)
+                | P_Fld(0x4, SHU_RANKCTL_RANKINCTL_ROOT1)
+                | P_Fld(0x4, SHU_RANKCTL_RANKINCTL));
+#endif
+
+    //vIO32WriteFldAlign(DRAMC_REG_SHU_STBCAL, 0x1, SHU_STBCAL_DMSTBLAT);
+    //vIO32WriteFldAlign(DRAMC_REG_SHURK0_DQSCTL, 0x5, SHURK0_DQSCTL_DQSINCTL); //DQSINCTL: set in UpdateACTimingReg()
+    //vIO32WriteFldAlign(DRAMC_REG_SHURK1_DQSCTL, 0x5, SHURK1_DQSCTL_R1DQSINCTL); //Set in UpdateACTimingReg()
+
+    mcDELAY_US(2);
+    #if LEGACY_GATING_DLY
+    LegacyGatingDlyLP4_DDR3200(p);
+    #endif
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSIEN, P_Fld(0x19, SHURK0_DQSIEN_R0DQS1IEN)
+                    | P_Fld(0x19, SHURK0_DQSIEN_R0DQS0IEN));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(0x0, SHURK1_DQSIEN_R1DQS3IEN)
+                    | P_Fld(0x0, SHURK1_DQSIEN_R1DQS2IEN)
+                    | P_Fld(0x1b, SHURK1_DQSIEN_R1DQS1IEN)
+                    | P_Fld(0x1b, SHURK1_DQSIEN_R1DQS0IEN));
+    }
+    //               41536 === over_write_setting_begin ===
+    //               41536 === over_write_setting_end ===
+    vIO32WriteFldAlign(DRAMC_REG_DRAMCTRL, 0x1, DRAMCTRL_PREALL_OPTION);
+    vIO32WriteFldAlign(DRAMC_REG_ZQCS, 0x56, ZQCS_ZQCSOP);
+
+    mcDELAY_US(1);
+
+    vIO32WriteFldAlign(DRAMC_REG_SHU_CONF1, 0x1, SHU_CONF1_TREFBWIG);
+    vIO32WriteFldAlign(DRAMC_REG_SHU_CONF3, 0xff, SHU_CONF3_REFRCNT);
+    vIO32WriteFldAlign(DRAMC_REG_REFCTRL0, 0x1, REFCTRL0_REFFRERUN);
+    vIO32WriteFldAlign(DRAMC_REG_SREFCTRL, 0x1, SREFCTRL_SREF_HW_EN);
+    vIO32WriteFldAlign(DRAMC_REG_MPC_OPTION, 0x1, MPC_OPTION_MPCRKEN);
+    vIO32WriteFldAlign(DRAMC_REG_DRAMC_PD_CTRL, 0x1, DRAMC_PD_CTRL_PHYCLKDYNGEN);//Move to DCM off setting
+    vIO32WriteFldAlign(DRAMC_REG_DRAMC_PD_CTRL, 0x1, DRAMC_PD_CTRL_DCMEN);//Move to DCM off setting
+    vIO32WriteFldMulti(DRAMC_REG_EYESCAN, P_Fld(0x0, EYESCAN_RX_DQ_EYE_SEL)
+                | P_Fld(0x0, EYESCAN_RG_RX_EYE_SCAN_EN));
+    vIO32WriteFldMulti(DRAMC_REG_STBCAL1, P_Fld(0x1, STBCAL1_STBCNT_LATCH_EN)
+                | P_Fld(0x1, STBCAL1_STBENCMPEN));
+    vIO32WriteFldAlign(DRAMC_REG_TEST2_1, 0x10000, TEST2_1_TEST2_BASE);
+#if (FOR_DV_SIMULATION_USED == 1 || SW_CHANGE_FOR_SIMULATION == 1)
+    //because cmd_len=1 has bug with byte mode, so need to set cmd_len=0, then it will cost more time to do a pattern test
+    //workaround: reduce TEST2_OFF to make less test agent cmd. make lpddr4-1600 can finish in 60us (Mengru)
+    vIO32WriteFldAlign(DRAMC_REG_TEST2_2, 0x20, TEST2_2_TEST2_OFF);
+#else
+    vIO32WriteFldAlign(DRAMC_REG_TEST2_2, 0x400, TEST2_2_TEST2_OFF);
+#endif
+    vIO32WriteFldMulti(DRAMC_REG_TEST2_3, P_Fld(0x1, TEST2_3_TEST2WREN2_HW_EN)
+                | P_Fld(0x1, TEST2_3_TESTAUDPAT));
+    vIO32WriteFldAlign(DRAMC_REG_RSTMASK, 0x0, RSTMASK_DAT_SYNC_MASK);
+    vIO32WriteFldAlign(DRAMC_REG_RSTMASK, 0x0, RSTMASK_PHY_SYNC_MASK);
+
+    mcDELAY_US(1);
+
+    vIO32WriteFldMulti(DRAMC_REG_HW_MRR_FUN, P_Fld(0x0, HW_MRR_FUN_TRPMRR_EN)
+                    | P_Fld(0x0, HW_MRR_FUN_TRCDMRR_EN) | P_Fld(0x0, HW_MRR_FUN_TMRR_ENA)
+                    | P_Fld(0x0, HW_MRR_FUN_MANTMRR_EN)); // from YH Tsai review for samsung MRR/Read cmd issue
+    if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+    {
+        vIO32WriteFldAlign(DRAMC_REG_PERFCTL0, 0x1, PERFCTL0_WRFIO_MODE2);
+                    //| P_Fld(0x0, PERFCTL0_RWSPLIT)); //Set in UpdateInitialSettings_LP4()
+        vIO32WriteFldMulti(DRAMC_REG_PERFCTL0, P_Fld(0x1, PERFCTL0_REORDEREN)
+                    | P_Fld(0x0, PERFCTL0_REORDER_MODE));
+        vIO32WriteFldAlign(DRAMC_REG_RSTMASK, 0x0, RSTMASK_GT_SYNC_MASK);
+        vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0x1, RKCFG_DQSOSC2RK);
+        vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_REFR_BLOCKEN);
+        vIO32WriteFldAlign(DRAMC_REG_EYESCAN, 0x0, EYESCAN_RG_RX_MIOCK_JIT_EN);
+    }
+    else
+    {
+        vIO32WriteFldAlign(DRAMC_REG_DRAMCTRL, 0x0, DRAMCTRL_CTOREQ_HPRI_OPT);
+        vIO32WriteFldMulti(DRAMC_REG_PERFCTL0, P_Fld(0x1, PERFCTL0_REORDEREN)
+                    | P_Fld(0x0, PERFCTL0_REORDER_MODE));
+        vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_REFR_BLOCKEN);
+        vIO32WriteFldAlign(DRAMC_REG_RSTMASK, 0x0, RSTMASK_GT_SYNC_MASK);
+        vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0x1, RKCFG_DQSOSC2RK);
+        vIO32WriteFldAlign(DRAMC_REG_MPC_OPTION, 1, MPC_OPTION_MPCRKEN);
+        vIO32WriteFldAlign(DRAMC_REG_EYESCAN, 0x0, EYESCAN_RG_RX_MIOCK_JIT_EN);
+        vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0);
+        vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1);
+        vIO32WriteFldAlign(DRAMC_REG_SHU_RANKCTL, 0x4, SHU_RANKCTL_RANKINCTL);
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_DQ1)
+                    | P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_DQ0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_DQM1)
+                    | P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_DQM0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
+                    | P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
+                    | P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
+    }
+#if ENABLE_TMRRI_NEW_MODE
+    vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x0, SPCMDCTRL_REFR_BLOCKEN);
+    vIO32WriteFldAlign(DRAMC_REG_HW_MRR_FUN, 0x1, HW_MRR_FUN_TMRR_ENA);
+#endif
+    mcDELAY_US(5);
+
+    vIO32WriteFldAlign(DRAMC_REG_STBCAL1, 0x3, STBCAL1_STBCAL_FILTER);
+    vIO32WriteFldAlign(DRAMC_REG_STBCAL1, 0x1, STBCAL1_STBCAL_FILTER);
+    vIO32WriteFldMulti(DRAMC_REG_STBCAL, P_Fld(0x1, STBCAL_STB_DQIEN_IG)
+                | P_Fld(0x1, STBCAL_PICHGBLOCK_NORD)
+                | P_Fld(0x0, STBCAL_STBCALEN)
+                | P_Fld(0x0, STBCAL_STB_SELPHYCALEN)
+                | P_Fld(0x1, STBCAL_PIMASK_RKCHG_OPT));
+    vIO32WriteFldAlign(DRAMC_REG_STBCAL1, 0x1, STBCAL1_STB_SHIFT_DTCOUT_IG);
+    vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG, P_Fld(0x9, SHU_DQSG_STB_UPDMASKCYC)
+                | P_Fld(0x1, SHU_DQSG_STB_UPDMASK_EN));
+    vIO32WriteFldAlign(DDRPHY_MISC_CTRL0, 0x0, MISC_CTRL0_R_DMDQSIEN_SYNCOPT);
+    vIO32WriteFldAlign(DRAMC_REG_SHU_STBCAL, 0x1, SHU_STBCAL_DQSG_MODE);
+    vIO32WriteFldAlign(DRAMC_REG_STBCAL, 0x1, STBCAL_SREF_DQSGUPD);
+    //M17_Remap:vIO32WriteFldAlign(DDRPHY_MISC_CTRL1, 0x0, MISC_CTRL1_R_DMDQMDBI);
+    /* RX Tracking DQM SM enable (actual values are set in DramcRxInputDelayTrackingHW()) */
+#if ENABLE_RX_TRACKING
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, p->DBI_R_onoff[p->dram_fsp], SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0);
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, p->DBI_R_onoff[p->dram_fsp], SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1);
+#else
+    vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0);
+    vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1);
+#endif
+//Sylv_ia MP setting should set SHU_STBCAL_DMSTBLAT as 0x2 (review by HJ Huang)
+    vIO32WriteFldMulti(DRAMC_REG_SHU_STBCAL, P_Fld(0x1, SHU_STBCAL_PICGLAT)
+                | P_Fld(0x2, SHU_STBCAL_DMSTBLAT));
+    vIO32WriteFldMulti(DRAMC_REG_REFCTRL1, P_Fld(0x1, REFCTRL1_REF_QUE_AUTOSAVE_EN)
+                | P_Fld(0x1, REFCTRL1_SLEFREF_AUTOSAVE_EN));
+    vIO32WriteFldMulti(DRAMC_REG_DQSOSCR, P_Fld(0x1, DQSOSCR_SREF_TXPI_RELOAD_OPT)
+                | P_Fld(0x1, DQSOSCR_SREF_TXUI_RELOAD_OPT));
+    vIO32WriteFldMulti(DRAMC_REG_RSTMASK, P_Fld(0x0, RSTMASK_DVFS_SYNC_MASK)
+                | P_Fld(0x0, RSTMASK_GT_SYNC_MASK_FOR_PHY)
+                | P_Fld(0x0, RSTMASK_DVFS_SYNC_MASK_FOR_PHY));
+    vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0x1, RKCFG_RKMODE);
+
+#if !APPLY_LP4_POWER_INIT_SEQUENCE
+    vIO32WriteFldMulti(DRAMC_REG_CKECTRL, P_Fld(0x1, CKECTRL_CKEFIXON)
+                | P_Fld(0x1, CKECTRL_CKE1FIXON));
+#endif
+
+    mcDELAY_US(12);
+
+    ///TODO: DDR3200
+    //if(p->frequency==1600)
+    {
+#if 0
+        //               60826 ===dramc_shu1_lp4_3200 begin===
+        if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+        {
+                vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x5, SHU_RANKCTL_RANKINCTL_PHY)
+                            | P_Fld(0x3, SHU_RANKCTL_RANKINCTL_ROOT1)
+                            | P_Fld(0x3, SHU_RANKCTL_RANKINCTL));
+        }
+        else
+        {
+                vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x6, SHU_RANKCTL_RANKINCTL_PHY)
+                            | P_Fld(0x4, SHU_RANKCTL_RANKINCTL_ROOT1));
+        }
+#endif
+#if LEGACY_TX_TRACK
+        LegacyTxTrackLP4_DDR3200(p);
+#endif
+
+#if ENABLE_WRITE_POST_AMBLE_1_POINT_5_TCK
+        vIO32WriteFldAlign(DRAMC_REG_SHU_WODT, p->dram_fsp, SHU_WODT_WPST1P5T); //Set write post-amble by FSP with MR3
+#else
+        vIO32WriteFldAlign(DRAMC_REG_SHU_WODT, 0x0, SHU_WODT_WPST1P5T); //Set write post-amble by FSP with MR3
+#endif
+
+        //vIO32WriteFldAlign(DRAMC_REG_SHU_HWSET_MR2, 0x2d, SHU_HWSET_MR2_HWSET_MR2_OP);
+        if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+        {
+                vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSIEN, P_Fld(0x19, SHURK0_DQSIEN_R0DQS1IEN)
+                            | P_Fld(0x19, SHURK0_DQSIEN_R0DQS0IEN));
+        }
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_PI, P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQM_B1)
+                    | P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQM_B0)
+                    | P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQ_B1)
+                    | P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQ_B0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(0x4, SHURK0_SELPH_DQ2_DLY_OEN_DQ3)
+                    | P_Fld(0x4, SHURK0_SELPH_DQ2_DLY_OEN_DQ2)
+                    | P_Fld(0x4, SHURK0_SELPH_DQ2_DLY_OEN_DQ1)
+                    | P_Fld(0x4, SHURK0_SELPH_DQ2_DLY_OEN_DQ0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ3, P_Fld(0x4, SHURK0_SELPH_DQ3_DLY_OEN_DQM3)
+                    | P_Fld(0x4, SHURK0_SELPH_DQ3_DLY_OEN_DQM2)
+                    | P_Fld(0x4, SHURK0_SELPH_DQ3_DLY_OEN_DQM1)
+                    | P_Fld(0x4, SHURK0_SELPH_DQ3_DLY_OEN_DQM0));
+        if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+        {
+                vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(0x0, SHURK1_DQSIEN_R1DQS3IEN)
+                            | P_Fld(0x0, SHURK1_DQSIEN_R1DQS2IEN)
+                            | P_Fld(0x1b, SHURK1_DQSIEN_R1DQS1IEN)
+                            | P_Fld(0x1b, SHURK1_DQSIEN_R1DQS0IEN));
+        }
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_PI, P_Fld(0x14, SHURK1_PI_RK1_ARPI_DQM_B1)
+                    | P_Fld(0x14, SHURK1_PI_RK1_ARPI_DQM_B0)
+                    | P_Fld(0x14, SHURK1_PI_RK1_ARPI_DQ_B1)
+                    | P_Fld(0x14, SHURK1_PI_RK1_ARPI_DQ_B0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ2, P_Fld(0x4, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3)
+                    | P_Fld(0x4, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2)
+                    | P_Fld(0x4, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1)
+                    | P_Fld(0x4, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0));
+        vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ3, P_Fld(0x4, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3)
+                    | P_Fld(0x4, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2)
+                    | P_Fld(0x4, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1)
+                    | P_Fld(0x4, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0));
+        vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG_RETRY, P_Fld(0x0, SHU_DQSG_RETRY_R_XSR_RETRY_SPM_MODE)
+                    | P_Fld(0x0, SHU_DQSG_RETRY_R_DDR1866_PLUS)); //La_fite MP setting = 0
+#if LEGACY_TDQSCK_PRECAL
+        LegacyPreCalLP4_DDR3200(p);
+#endif
+        //               61832 ===dramc_shu1_lp4_3200 end===
+
+
+        //               66870 ===ddrphy_shu1_lp4_3200_CHA begin===
+        if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+        {
+                vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x1, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0);
+                vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x1, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1);
+        }
+        else
+        {
+                vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x1, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0)
+                            | P_Fld(0x1, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0));
+                vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ7, P_Fld(0x1, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1)
+                            | P_Fld(0x1, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1));
+//francis remove : it will make CLRPLL frequency wrong!
+//francis remove                vIO32WriteFldMulti(DDRPHY_SHU_PLL7, P_Fld(0x3d00, SHU_PLL7_RG_RCLRPLL_SDM_PCW)
+//francis remove                            | P_Fld(0x1, SHU_PLL7_RG_RCLRPLL_SDM_PCW_CHG));
+        }
+        //               67761 ===ddrphy_shu1_lp4_3200_CHA end===
+
+        //NOT included in parsing tool
+        vIO32WriteFldAlign(DRAMC_REG_SHU_DQS2DQ_TX, 0x0, SHU_DQS2DQ_TX_OE2DQ_OFFSET);
+    }
+    ///TODO: DDR3733
+    if (p->freqGroup == 2133)
+    {
+        DramcSetting_Olympus_LP4_ByteMode_DDR4266(p);
+    }
+    else if (p->freqGroup == 1866)
+    {
+        DramcSetting_Olympus_LP4_ByteMode_DDR3733(p);
+    }
+    ///TODO: DDR2667
+    else if (p->freqGroup == 1333 || p->freqGroup == 1200) // TODO: Initial settings for DDR2400?
+    {
+        DramcSetting_Olympus_LP4_ByteMode_DDR2667(p);
+    }
+    else if ((p->freqGroup == 800) || (p->freqGroup == 600) || (p->freqGroup == 400))
+    {
+        DramcSetting_Olympus_LP4_ByteMode_DDR1600(p);
+    }
+
+    UpdateInitialSettings_LP4(p);
+
+#if SIMULATION_SW_IMPED // Darren: Need porting by E2 IMP Calib DVT owner
+    #if FSP1_CLKCA_TERM
+    U8 u1CASwImpFreqRegion = (p->dram_fsp == FSP_0)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
+    #else
+    U8 u1CASwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
+    #endif
+    U8 u1DQSwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
+
+    if (p->dram_type == TYPE_LPDDR4X)
+        DramcSwImpedanceSaveRegister(p, u1CASwImpFreqRegion, u1DQSwImpFreqRegion, DRAM_DFS_REG_SHU0);
+#endif
+
+#ifndef LOOPBACK_TEST
+    DDRPhyFreqMeter(p);
+#endif
+
+#if 0
+    vIO32WriteFldMulti(DRAMC_REG_MRS, P_Fld(0x0, MRS_MRSRK)
+                | P_Fld(0x4, MRS_MRSMA)
+                | P_Fld(0x0, MRS_MRSOP));
+    mcDELAY_US(1);
+    vIO32WriteFldAlign(DRAMC_REG_SPCMD, 0x1, SPCMD_MRREN);
+    vIO32WriteFldAlign(DRAMC_REG_SPCMD, 0x0, SPCMD_MRREN);
+#endif
+
+    vIO32WriteFldAlign(DRAMC_REG_TEST2_4, 0x0, TEST2_4_TEST_REQ_LEN1);
+
+    vIO32WriteFldAlign(DRAMC_REG_SHU_CONF3, 0x5, SHU_CONF3_ZQCSCNT);
+
+    mcDELAY_US(1);
+
+#if !APPLY_LP4_POWER_INIT_SEQUENCE
+    vIO32WriteFldMulti(DRAMC_REG_CKECTRL, P_Fld(0x0, CKECTRL_CKEFIXON)
+                | P_Fld(0x0, CKECTRL_CKE1FIXON));
+#endif
+    vIO32WriteFldMulti(DRAMC_REG_REFCTRL0, P_Fld(0x1, REFCTRL0_PBREFEN)
+                | P_Fld(0x1, REFCTRL0_PBREF_DISBYRATE));
+    vIO32WriteFldMulti(DRAMC_REG_SHUCTRL2, P_Fld(0x1, SHUCTRL2_MR13_SHU_EN)
+                | P_Fld(0x1, SHUCTRL2_HWSET_WLRL));
+    vIO32WriteFldAlign(DRAMC_REG_REFCTRL0, 0x1, REFCTRL0_REFDIS);
+    //vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x0, SPCMDCTRL_REFRDIS);//Lewis@20160613: Fix refresh rate is wrong while diable MR4
+    vIO32WriteFldAlign(DRAMC_REG_DRAMCTRL, 0x1, DRAMCTRL_REQQUE_THD_EN);
+                //| P_Fld(0x1, DRAMCTRL_DPDRK_OPT)); //DPDRK_OPT doesn't exit for Sylv_ia
+    vIO32WriteFldMulti(DRAMC_REG_DUMMY_RD, P_Fld(0x1, DUMMY_RD_DQSG_DMYRD_EN)
+                | P_Fld(p->support_rank_num, DUMMY_RD_RANK_NUM)
+                | P_Fld(0x1, DUMMY_RD_DUMMY_RD_CNT6)
+                | P_Fld(0x1, DUMMY_RD_DUMMY_RD_CNT5)
+                | P_Fld(0x1, DUMMY_RD_DUMMY_RD_CNT3)
+                | P_Fld(0x1, DUMMY_RD_DUMMY_RD_SW));
+    vIO32WriteFldAlign(DRAMC_REG_TEST2_4, 0x4, TEST2_4_TESTAGENTRKSEL);
+    vIO32WriteFldAlign(DRAMC_REG_DRAMCTRL, 0x0, DRAMCTRL_CTOREQ_HPRI_OPT);
+    //               60759 === DE initial sequence done ===
+
+///TODO: DVFS_Enable
+
+    mcDELAY_US(1);
+
+      //*((UINT32P)(DDRPHY0AO_BASE + 0x0000)) = 0x00000000;
+
+    mcDELAY_US(1);
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    //CH-A
+    vIO32WriteFldMulti(DRAMC_REG_SHUCTRL, P_Fld(0x1, SHUCTRL_R_DRAMC_CHA) | P_Fld(0x0, SHUCTRL_SHU_PHYRST_SEL));
+    vIO32WriteFldAlign(DRAMC_REG_SHUCTRL2, 0x1, SHUCTRL2_R_DVFS_DLL_CHA);
+    //CH-B
+    vIO32WriteFldMulti(DRAMC_REG_SHUCTRL + SHIFT_TO_CHB_ADDR, P_Fld(0x0, SHUCTRL_R_DRAMC_CHA) | P_Fld(0x1, SHUCTRL_SHU_PHYRST_SEL));
+    vIO32WriteFldAlign(DRAMC_REG_SHUCTRL2 + SHIFT_TO_CHB_ADDR, 0x0, SHUCTRL2_R_DVFS_DLL_CHA);
+    //               60826 ===LP4_3200_intial_setting_shu1 end===
+
+#ifndef LOOPBACK_TEST
+    DDRPhyFMeter_Init(p);
+#endif
+
+    DVFSSettings(p);
+
+}
+#endif // __A60868_TO_BE_PORTING__
+
+#if 0
+void vApplyConfigAfterCalibration(DRAMC_CTX_T *p)
+{
+#if __A60868_TO_BE_PORTING__
+
+    U8 shu_index;
+#if ENABLE_TMRRI_NEW_MODE
+    U8 u1RankIdx;
+#endif
+
+/*================================
+    PHY RX Settings
+==================================*/
+    vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL4, 0x11400000, MISC_CG_CTRL4_R_PHY_MCK_CG_CTRL);
+    vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0x0, REFCTRL1_SREF_CG_OPT);
+    vIO32WriteFldAlign_All(DRAMC_REG_SHUCTRL, 0x0, SHUCTRL_DVFS_CG_OPT);//Move to DCM off setting
+
+    /* Burst mode settings are removed from here due to
+     *  1. Set in UpdateInitialSettings_LP4
+     *  2. DQS Gating ensures new burst mode is switched when to done
+     *     (or doesn't switch gatingMode at all, depending on "LP4_GATING_OLD_BURST_MODE")
+     */
+
+    vIO32WriteFldAlign_All(DDRPHY_CA_CMD6, 0x0, CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN);
+#if 0
+    vIO32WriteFldAlign_All(DDRPHY_B0_DQ6, 0x0, B0_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B0);
+    vIO32WriteFldAlign_All(DDRPHY_B1_DQ6, 0x0, B1_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B1);
+    vIO32WriteFldAlign_All(DDRPHY_CA_CMD6, 0x0, CA_CMD6_RG_TX_ARCMD_OE_EXT_DIS);
+#endif
+
+#if ENABLE_WRITE_DBI
+    EnableDRAMModeRegWriteDBIAfterCalibration(p);
+#endif
+
+#if ENABLE_READ_DBI
+    EnableDRAMModeRegReadDBIAfterCalibration(p);
+#endif
+
+    // Set VRCG{MR13[3]} to 0 both to DRAM and DVFS
+    SetMr13VrcgToNormalOperation(p);
+
+    //DA mode
+    vIO32WriteFldAlign_All(DDRPHY_B0_DQ6, 0x0, B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0);
+    vIO32WriteFldAlign_All(DDRPHY_B1_DQ6, 0x0, B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1);
+    vIO32WriteFldAlign_All(DDRPHY_CA_CMD6, 0x0, CA_CMD6_RG_RX_ARCMD_BIAS_PS);
+
+    vIO32WriteFldAlign_All(DDRPHY_B0_DQ6, 0x1, B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0);
+    vIO32WriteFldAlign_All(DDRPHY_B1_DQ6, 0x1, B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1);
+    vIO32WriteFldAlign_All(DDRPHY_CA_CMD6, 0x1, CA_CMD6_RG_RX_ARCMD_RPRE_TOG_EN);
+
+/*================================
+    IMPCAL Settings
+==================================*/
+    vIO32WriteFldMulti_All(DRAMC_REG_IMPCAL, P_Fld(0, IMPCAL_IMPCAL_IMPPDP) | P_Fld(0, IMPCAL_IMPCAL_IMPPDN));    //RG_RIMP_BIAS_EN and RG_RIMP_VREF_EN move to IMPPDP and IMPPDN
+    vIO32WriteFldAlign_All(DDRPHY_MISC_IMP_CTRL0, 0, MISC_IMP_CTRL0_RG_IMP_EN);
+
+/*================================
+    MR1
+==================================*/
+
+    //MR1 op[7]=0 already be setted at end of gating calibration, no need to set here again
+/*
+    u1MR01Value[p->dram_fsp] &= 0x7f;
+    DramcModeRegWrite(p, 1, u1MR01Value[p->dram_fsp]);
+*/
+    //Prevent M_CK OFF because of hardware auto-sync
+    vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, Fld(4, 0, AC_MSKB0));
+
+    //DFS- fix Gating Tracking settings
+    vIO32WriteFldAlign_All(DDRPHY_MISC_CTRL0, 0, MISC_CTRL0_R_STBENCMP_DIV4CK_EN);
+    vIO32WriteFldAlign_All(DDRPHY_MISC_CTRL1, 0, MISC_CTRL1_R_DMSTBENCMP_RK_OPT);
+
+    ///TODO: Disable MR4 MR18/MR19, TxHWTracking, Dummy RD - for DFS workaround
+    vIO32WriteFldAlign_All(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_REFRDIS);    //MR4 Disable
+    //vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS);  //MR18, MR19 Disable
+    //for(shu_index = SRAM_SHU0; shu_index < DRAM_DFS_SRAM_MAX; shu_index++)
+      //vIO32WriteFldAlign_All(DRAMC_REG_SHU_SCINTV + SHU_GRP_DRAMC_OFFSET*shu_index, 0x1, SHU_SCINTV_DQSOSCENDIS);
+    //vIO32WriteFldAlign_All(DRAMC_REG_SHU_SCINTV, 0x1, SHU_SCINTV_DQSOSCENDIS);
+    //vIO32WriteFldAlign_All(DRAMC_REG_SHU2_SCINTV, 0x1, SHU2_SCINTV_DQSOSCENDIS);
+    //vIO32WriteFldAlign_All(DRAMC_REG_SHU3_SCINTV, 0x1, SHU3_SCINTV_DQSOSCENDIS);
+    vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN)
+                                            | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN)
+                                            | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN)
+                                            | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG));
+
+#if APPLY_LP4_POWER_INIT_SEQUENCE
+    //CKE dynamic
+#if ENABLE_TMRRI_NEW_MODE
+    CKEFixOnOff(p, TO_ALL_RANK, CKE_DYNAMIC, TO_ALL_CHANNEL);
+#else
+    CKEFixOnOff(p, RANK_0, CKE_DYNAMIC, TO_ALL_CHANNEL);
+#endif
+
+    //// Enable  HW MIOCK control to make CLK dynamic
+    DramCLKAlwaysOnOff(p, OFF);
+#endif
+
+    //close eyescan to save power
+    vIO32WriteFldMulti_All(DRAMC_REG_EYESCAN, P_Fld(0x0, EYESCAN_EYESCAN_DQS_SYNC_EN)
+                                        | P_Fld(0x0, EYESCAN_EYESCAN_NEW_DQ_SYNC_EN)
+                                        | P_Fld(0x0, EYESCAN_EYESCAN_DQ_SYNC_EN));
+
+    /* TESTAGENT2 */
+    vIO32WriteFldAlign_All(DRAMC_REG_TEST2_4, 4, TEST2_4_TESTAGENTRKSEL); // Rank selection is controlled by Test Agent
+#endif
+}
+#endif
+
+static void vReplaceDVInit(DRAMC_CTX_T *p)
+{
+    U8 u1RandIdx, backup_rank = 0;
+
+    backup_rank = p->rank;
+
+    //Disable RX Tracking
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), P_Fld(0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), P_Fld(0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS0), P_Fld(0, B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0)
+                                                            | P_Fld(0, B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0 ));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_RXDVS0), P_Fld(0, B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1)
+                                                            | P_Fld(0, B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1 ));
+
+    for(u1RandIdx = RANK_0; u1RandIdx < p->support_rank_num; u1RandIdx++)
+    {
+        vSetRank(p, u1RandIdx);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS2), P_Fld(0, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0)
+                                                                    | P_Fld(0, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0)
+                                                                    | P_Fld(0, RK_B0_RXDVS2_R_RK0_DVS_MODE_B0));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS2), P_Fld(0, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1)
+                                                                    | P_Fld(0, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1)
+                                                                    | P_Fld(0, RK_B1_RXDVS2_R_RK0_DVS_MODE_B1));
+    }
+    vSetRank(p, backup_rank);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1), 0, CBT_WLEV_CTRL1_CATRAINLAT);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL1), 0, SWCMD_CTRL1_WRFIFO_MODE2);
+
+
+    //Bringup setting review
+    {
+        U32 backup_broadcast = GetDramcBroadcast();
+        DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+        U8 u1DQ_HYST_SEL=0x1, u1CA_HYST_SEL=0x1;
+        U8 u1DQ_CAP_SEL=0x1b, u1CA_CAP_SEL=0x1b;
+        //Critical
+        //APHY
+        if(p->frequency<=933)
+        {
+            u1DQ_HYST_SEL = 0x1;
+            u1CA_HYST_SEL = 0x1;
+        }
+        else
+        {
+            u1DQ_HYST_SEL = 0x0;
+            u1CA_HYST_SEL = 0x0;
+        }
+
+        if(p->frequency<=400)
+        {
+            u1DQ_CAP_SEL= 0xf;
+            u1CA_CAP_SEL= 0xf;
+        }
+        else if(p->frequency<=600)
+        {
+            u1DQ_CAP_SEL= 0x1b;
+            u1CA_CAP_SEL= 0x1b;
+        }
+        else if(p->frequency<=1200)
+        {
+            u1DQ_CAP_SEL= 0xf;
+            u1CA_CAP_SEL= 0xf;
+        }
+        else if(p->frequency<=1600)
+        {
+            u1DQ_CAP_SEL= 0xd;
+            u1CA_CAP_SEL= 0xd;
+        }
+        else if(p->frequency<=2133)
+        {
+            u1DQ_CAP_SEL= 0xb;
+            u1CA_CAP_SEL= 0xb;
+        }
+
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ6, P_Fld(u1DQ_HYST_SEL, SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0)
+                                                    | P_Fld(u1DQ_CAP_SEL, SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0));
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ6, P_Fld(u1DQ_HYST_SEL, SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1)
+                                                    | P_Fld(u1DQ_CAP_SEL, SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1));
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD6, P_Fld(u1CA_HYST_SEL, SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA)
+                                                    | P_Fld(u1CA_CAP_SEL, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA));
+
+        //Jeremy
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ2,P_Fld((p->frequency>=2133), SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0)
+                                                    | P_Fld((p->frequency>=2133), SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0)
+                                                    | P_Fld((p->frequency==1200), SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0) //Sync MP setting WL
+                                                    | P_Fld((p->frequency==1200), SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0)); //Sync MP setting WL
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ2,P_Fld((p->frequency>=2133), SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1)
+                                                    | P_Fld((p->frequency>=2133), SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1)
+                                                    | P_Fld((p->frequency==1200), SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1) //Sync MP setting WL
+                                                    | P_Fld((p->frequency==1200), SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1)); //Sync MP setting WL
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD2,P_Fld((p->frequency>=2133), SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA)
+                                                    | P_Fld((p->frequency>=2133), SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA)
+                                                    | P_Fld((p->frequency==1200), SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA) //Sync MP setting WL
+                                                    | P_Fld((p->frequency==1200), SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA)); //Sync MP setting WL
+
+        //disable RX PIPE for RX timing pass
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x0, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN);
+
+        //Disable DPM IRQ
+        vIO32Write4B_All(DDRPHY_REG_MISC_DBG_IRQ_CTRL1, 0x0);
+        vIO32Write4B_All(DDRPHY_REG_MISC_DBG_IRQ_CTRL4, 0x0);
+        vIO32Write4B_All(DDRPHY_REG_MISC_DBG_IRQ_CTRL7, 0x0);
+
+        //Disable NEW RX DCM mode
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY)
+                                                            | P_Fld(2, MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY)
+                                                            | P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT)
+                                                            | P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_DCM_OPT));
+
+        vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 0, HMR4_MR4INT_LIMITEN);
+        vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0, REFCTRL1_REFPEND_OPT1);
+        vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL3, 0, REFCTRL3_REF_DERATING_EN);
+
+        vIO32WriteFldMulti_All(DRAMC_REG_DRAMC_IRQ_EN, P_Fld(0x3fff, DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV)
+                                                    | P_Fld(0x0, DRAMC_IRQ_EN_MR4INT_EN));
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF0, 0, SHU_CONF0_PBREFEN);
+
+
+
+        vIO32WriteFldAlign_All(DDRPHY_REG_CA_TX_MCK, 0x1, CA_TX_MCK_R_DMRESET_FRPHY_OPT);
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 0x1, MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE);
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 0x1, MISC_IMPCAL_IMPBINARY);
+
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ10, P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0)
+                                                    | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0));
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ10, P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1)
+                                                    | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1));
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD10, P_Fld(0x1, SHU_CA_CMD10_RG_RX_ARCLK_DQSSTB_RPST_HS_EN_CA)
+                                                    | P_Fld(0x1, SHU_CA_CMD10_RG_RX_ARCLK_DQSSTB_CG_EN_CA));
+
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ8, P_Fld(1, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)
+                                                    | P_Fld(1, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0)
+                                                    | P_Fld(1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0)
+                                                    | P_Fld(1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0)
+                                                    | P_Fld(1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0)
+                                                    | P_Fld(1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0)
+                                                    | P_Fld(1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0)
+                                                    | P_Fld(1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0)
+                                                    | P_Fld(1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0)
+                                                    | P_Fld(1, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0)
+                                                    | P_Fld(1, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0));
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ8, P_Fld(1, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)
+                                                    | P_Fld(1, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1)
+                                                    | P_Fld(1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1)
+                                                    | P_Fld(1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1)
+                                                    | P_Fld(1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1)
+                                                    | P_Fld(1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1)
+                                                    | P_Fld(1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1)
+                                                    | P_Fld(1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1)
+                                                    | P_Fld(1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1)
+                                                    | P_Fld(1, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1)
+                                                    | P_Fld(1, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1));
+
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DLL2, 0x1, SHU_B0_DLL2_RG_ARDQ_REV_B0);
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DLL2, 0x1, SHU_B1_DLL2_RG_ARDQ_REV_B1);
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_DLL2, 0x1, SHU_CA_DLL2_RG_ARCMD_REV);    //Jeremy
+
+        #if 1
+        //Follow DE - DRAMC
+        //vIO32WriteFldAlign_All(DRAMC_REG_DDRCOMMON0, 1, DDRCOMMON0_DISSTOP26M);
+        //vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A3, 1, TEST2_A3_TEST_AID_EN);
+        //vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 0, TEST2_A4_TESTAGENTRKSEL);
+        vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0, DUMMY_RD_DQSG_DMYRD_EN);
+        vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_DBG_SEL1, 0x1e, DRAMC_DBG_SEL1_DEBUG_SEL_0);
+        vIO32WriteFldAlign_All(DRAMC_REG_SWCMD_CTRL2, 0x20, SWCMD_CTRL2_RTSWCMD_AGE);
+        vIO32WriteFldAlign_All(DRAMC_REG_RTMRW_CTRL0, 0x20, RTMRW_CTRL0_RTMRW_AGE);
+
+
+        vIO32WriteFldMulti_All(DRAMC_REG_DLLFRZ_CTRL, P_Fld(0, DLLFRZ_CTRL_DLLFRZ) | P_Fld(0, DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT));
+        vIO32WriteFldMulti_All(DRAMC_REG_MPC_CTRL, P_Fld(1, MPC_CTRL_RTSWCMD_HPRI_EN) | P_Fld(1, MPC_CTRL_RTMRW_HPRI_EN));
+        vIO32WriteFldMulti_All(DRAMC_REG_HW_MRR_FUN, P_Fld(0, HW_MRR_FUN_R2MRRHPRICTL) | P_Fld(0, HW_MRR_FUN_TR2MRR_ENA));
+        vIO32WriteFldMulti_All(DRAMC_REG_ACTIMING_CTRL, P_Fld(1, ACTIMING_CTRL_REFNA_OPT) | P_Fld(1, ACTIMING_CTRL_SEQCLKRUN3));
+        vIO32WriteFldAlign_All(DRAMC_REG_CKECTRL, 1, CKECTRL_RUNTIMEMRRCKEFIX);
+        vIO32WriteFldMulti_All(DRAMC_REG_DVFS_CTRL0, P_Fld(0, DVFS_CTRL0_DVFS_SYNC_MASK) | P_Fld(1, DVFS_CTRL0_R_DVFS_SREF_OPT));
+        vIO32WriteFldAlign_All(DRAMC_REG_DVFS_TIMING_CTRL1, 1, DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT);
+        vIO32WriteFldMulti_All(DRAMC_REG_HMR4, P_Fld(1, HMR4_REFRCNT_OPT)
+                                            | P_Fld(0, HMR4_REFR_PERIOD_OPT)
+                                            | P_Fld(1, HMR4_SPDR_MR4_OPT)//Resume from S0, trigger HW MR4
+                                            | P_Fld(0, HMR4_HMR4_TOG_OPT));
+        vIO32WriteFldAlign_All(DRAMC_REG_RX_SET0, 0, RX_SET0_SMRR_UPD_OLD);
+        vIO32WriteFldAlign_All(DRAMC_REG_DRAMCTRL, 1, DRAMCTRL_SHORTQ_OPT);
+        vIO32WriteFldAlign_All(DRAMC_REG_MISCTL0, 1, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS);
+#if ENABLE_EARLY_BG_CMD==0
+        vIO32WriteFldAlign_All(DRAMC_REG_PERFCTL0, 0, PERFCTL0_EBG_EN);
+#endif
+        vIO32WriteFldMulti_All(DRAMC_REG_CLKAR, P_Fld(1, CLKAR_REQQUECLKRUN) | P_Fld(0x7fff, CLKAR_REQQUE_PACG_DIS));
+        vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(0, REFCTRL0_PBREF_BK_REFA_ENA) | P_Fld(0, REFCTRL0_PBREF_BK_REFA_NUM));
+        vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0, REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA);
+        vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0, REFCTRL1_REFPB2AB_IGZQCS);
+        vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 1, REFCTRL1_REFPENDINGINT_OPT1); // @Darren, sync MP settings from Derping
+        vIO32WriteFldAlign_All(DRAMC_REG_REF_BOUNCE1,5, REF_BOUNCE1_REFRATE_DEBOUNCE_TH);
+        vIO32WriteFldAlign_All(DRAMC_REG_REFPEND2, 8, REFPEND2_MPENDREFCNT_TH8);
+        vIO32WriteFldAlign_All(DRAMC_REG_SCSMCTRL, 0, SCSMCTRL_SC_PG_MAN_DIS);
+        vIO32WriteFldMulti_All(DRAMC_REG_SCSMCTRL_CG, P_Fld(1, SCSMCTRL_CG_SCSM_CGAR)
+                                                    | P_Fld(1, SCSMCTRL_CG_SCARB_SM_CGAR));
+        vIO32WriteFldAlign_All(DRAMC_REG_RTSWCMD_CNT, 0x30, RTSWCMD_CNT_RTSWCMD_CNT);
+        vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_IRQ_EN, 0x3fff, DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV);
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_DCM_CTRL0, 1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT);
+        vIO32WriteFldMulti_All(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x1ff, SHU_HMR4_DVFS_CTRL0_REFRCNT) | P_Fld(0, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT));
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_VRCG, 11, SHU_HWSET_VRCG_VRCGDIS_PRDCNT);
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_MISC, 2, SHU_MISC_REQQUE_MAXCNT);
+        vIO32WriteFldAlign_All(DRAMC_REG_SREF_DPD_CTRL, 0, SREF_DPD_CTRL_DSM_HW_EN);//DSM only for LP5
+
+
+        //Follow DE - DDRPHY
+        vIO32WriteFldMulti_All(DDRPHY_REG_B0_DLL_ARPI4, P_Fld(1, B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B0) | P_Fld(1, B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B0));
+        vIO32WriteFldMulti_All(DDRPHY_REG_B1_DLL_ARPI4, P_Fld(1, B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B1) | P_Fld(1, B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B1));
+        vIO32WriteFldMulti_All(DDRPHY_REG_CA_DLL_ARPI4, P_Fld(1, CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CLK_CA) | P_Fld(1, CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CA_CA));
+        vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD11, P_Fld(0xa, CA_CMD11_RG_RRESETB_DRVN) | P_Fld(0xa, CA_CMD11_RG_RRESETB_DRVP));
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0x1f, MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL);
+
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQSIEN_CFG, 1, SHU_B0_DQSIEN_CFG_RG_RX_ARDQS_DQSIEN_GLITCH_FREE_EN_B0);//checked with WL
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQSIEN_CFG, 1, SHU_B1_DQSIEN_CFG_RG_RX_ARDQS_DQSIEN_GLITCH_FREE_EN_B1);//checked with WL
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_DQSIEN_CFG, 1, SHU_CA_DQSIEN_CFG_RG_RX_ARCLK_DQSIEN_GLITCH_FREE_EN_C0);//checked with WL
+
+
+#if (ENABLE_DDR400_OPEN_LOOP_MODE_OPTION == 0) // Darren- for DDR400 open loop mode disable
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL9, P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF)
+                                                        | P_Fld(0, MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF)
+                                                        | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN)
+                                                        | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF)
+                                                        | P_Fld(0, MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF)
+                                                        | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN)
+                                                        | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF)
+                                                        | P_Fld(0, MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF)
+                                                        | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN)
+                                                        | P_Fld(0, MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN));
+#endif
+        //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL, 1, MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE);
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(1, MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE)
+                                                        | P_Fld(0, MISC_DVFSCTL2_RG_DLL_SHUFFLE)); // Darren-
+
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL3, P_Fld(0x10, MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK)
+                                                        | P_Fld(1, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE)
+                                                        | P_Fld(3, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI)
+                                                        | P_Fld(1, MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK)
+                                                        | P_Fld(1, MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK));
+
+        //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL);
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DDR_RESERVE, 0xf, MISC_DDR_RESERVE_WDT_CONF_ISO_CNT);
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_IMP_CTRL1, P_Fld(1, MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT) | P_Fld(1, MISC_IMP_CTRL1_IMP_ABN_LAT_CLR));
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_IMPCAL, P_Fld(1, MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV)
+                                                    | P_Fld(1, MISC_IMPCAL_IMPCAL_DRVUPDOPT)
+                                                    | P_Fld(1, MISC_IMPCAL_IMPBINARY)
+                                                    | P_Fld(1, MISC_IMPCAL_DQDRVSWUPD)
+                                                    | P_Fld(0, MISC_IMPCAL_DRVCGWREF));
+
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DUTYSCAN1, P_Fld(1, MISC_DUTYSCAN1_EYESCAN_DQS_OPT) | P_Fld(1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN));
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFS_EMI_CLK, 0, MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY);
+        // @Darren, MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT is empty after IPM from Mao
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL0, P_Fld(0, MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT)
+                                                    | P_Fld(1, MISC_CTRL0_IMPCAL_CDC_ECO_OPT)
+                                                    | P_Fld(1, MISC_CTRL0_IMPCAL_LP_ECO_OPT));
+
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL4, P_Fld(0, MISC_CTRL4_R_OPT2_CG_CS)
+                                                    | P_Fld(0, MISC_CTRL4_R_OPT2_CG_CLK)
+                                                    | P_Fld(0, MISC_CTRL4_R_OPT2_CG_CMD)
+                                                    | P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQSIEN)
+                                                    | P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQ)
+                                                    | P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQS)
+                                                    | P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQM)
+                                                    | P_Fld(0, MISC_CTRL4_R_OPT2_CG_MCK)
+                                                    | P_Fld(0, MISC_CTRL4_R_OPT2_MPDIV_CG));
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL6, P_Fld(1, MISC_CTRL6_RG_ADA_MCK8X_EN_SHU_OPT) | P_Fld(1, MISC_CTRL6_RG_PHDET_EN_SHU_OPT));
+
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RX_AUTOK_CFG0, 1, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN);
+
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ1, P_Fld(1, SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0)
+                                                    | P_Fld(1, SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0)
+                                                    | P_Fld(1, SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0));
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ1, P_Fld(1, SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1)
+                                                    | P_Fld(1, SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1)
+                                                    | P_Fld(1, SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1));
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD1, P_Fld(1, SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA)
+                                                    | P_Fld(1, SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA)
+                                                    | P_Fld(1, SHU_CA_CMD1_RG_ARPI_8PHASE_XLATCH_FORCE_CA));
+
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ10, 1, SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0);
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ10, 1, SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1);
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10, 1, SHU_CA_CMD10_RG_RX_ARCLK_BW_SEL_CA); //sync MP settings by @WL review
+
+        // @Darren, sync MP settings by @WL review
+        {
+            U8 u1DQ_BW_SEL_B0=0, u1DQ_BW_SEL_B1=0, u1CA_BW_SEL_CA=0;
+
+            if (p->frequency >= 2133)
+            {
+                u1DQ_BW_SEL_B0 = 3;
+                u1DQ_BW_SEL_B1 = 3;
+                u1CA_BW_SEL_CA = 3;
+            }
+
+            vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ11, u1DQ_BW_SEL_B0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0);
+            vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ11, u1DQ_BW_SEL_B1, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1);
+            vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD11, u1CA_BW_SEL_CA, SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA);
+        }
+
+        //vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD1, P_Fld(1, SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA) | P_Fld(1, SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA));
+        //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10, 1, SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA);
+
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD12, 0, SHU_CA_CMD12_RG_RIMP_REV);
+
+
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1, P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_ODTN_UPD_DIS)
+                                                                    | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVN_UPD_DIS)
+                                                                    | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVP_UPD_DIS)
+                                                                    | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_ODTN_UPD_DIS)
+                                                                    | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVN_UPD_DIS)
+                                                                    | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVP_UPD_DIS));
+
+        //Darren-vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(67, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE) | P_Fld(43, MISC_SHU_DVFSDLL_R_DLL_IDLE));
+
+        //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_IMPCAL1, 0, SHU_MISC_IMPCAL1_IMPCALCNT);
+        //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING2, 0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN);
+        //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING6, 7, SHU_MISC_DRVING6_IMP_TXDLY_CMD);
+
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY)
+                                                            | P_Fld(2, MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY)
+                                                            | P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT)
+                                                            | P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_DCM_OPT));
+        #endif
+        DramcBroadcastOnOff(backup_broadcast);
+    }
+}
+
+
+void vApplyConfigBeforeCalibration(DRAMC_CTX_T *p)
+{
+#if __A60868_TO_BE_PORTING__
+
+    U8 read_xrtw2w, shu_index;
+    U8 u1RankIdx, u1RankIdxBak;
+    u1RankIdxBak = u1GetRank(p);
+
+    //Clk free run {Move to Init_DRAM() and only call once}
+#if (SW_CHANGE_FOR_SIMULATION == 0)
+    EnableDramcPhyDCM(p, 0);
+#endif
+
+    //Set LP3/LP4 Rank0/1 CA/TX delay chain to 0
+#if (FOR_DV_SIMULATION_USED == 0)
+    //CA0~9 per bit delay line -> CHA_CA0 CHA_CA3 CHA_B0_DQ6 CHA_B0_DQ7 CHA_B0_DQ2 CHA_B0_DQ5 CHA_B0_DQ4 CHA_B0_DQ1 CHA_B0_DQ0 CHA_B0_DQ3
+    vResetDelayChainBeforeCalibration(p);
+#endif
+
+    //MR4 refresh cnt set to 0x1ff (2ms update)
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF3, 0x1ff, SHU_CONF3_REFRCNT);
+
+    //The counter for Read MR4 cannot be reset after SREF if DRAMC no power down.
+    vIO32WriteFldAlign_All(DRAMC_REG_SPCMDCTRL, 1, SPCMDCTRL_SRFMR4_CNTKEEP_B);
+
+    //---- ZQ CS init --------
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_SCINTV, 0x1B, SHU_SCINTV_TZQLAT); //ZQ Calibration Time, unit: 38.46ns, tZQCAL min is 1 us. need to set larger than 0x1b
+    //for(shu_index = SRAM_SHU0; shu_index < DRAM_DFS_SRAM_MAX; shu_index++)
+        //vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF3 + SHU_GRP_DRAMC_OFFSET*shu_index, 0x1ff, SHU_CONF3_ZQCSCNT); //Every refresh number to issue ZQCS commands, only for DDR3/LPDDR2/LPDDR3/LPDDR4
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF3, 0x1ff, SHU_CONF3_ZQCSCNT); //Every refresh number to issue ZQCS commands, only for DDR3/LPDDR2/LPDDR3/LPDDR4
+    //vIO32WriteFldAlign_All(DRAMC_REG_SHU2_CONF3, 0x1ff, SHU_CONF3_ZQCSCNT); //Every refresh number to issue ZQCS commands, only for DDR3/LPDDR2/LPDDR3/LPDDR4
+    //vIO32WriteFldAlign_All(DRAMC_REG_SHU3_CONF3, 0x1ff, SHU_CONF3_ZQCSCNT); //Every refresh number to issue ZQCS commands, only for DDR3/LPDDR2/LPDDR3/LPDDR4
+    vIO32WriteFldAlign_All(DRAMC_REG_DRAMCTRL, 0, DRAMCTRL_ZQCALL);  // HW send ZQ command for both rank, disable it due to some dram only have 1 ZQ pin for two rank.
+
+    //Dual channel ZQCS interlace,  0: disable, 1: enable
+    if (p->support_channel_num == CHANNEL_SINGLE)
+    {
+        //single channel, ZQCSDUAL=0, ZQCSMASK=0
+        vIO32WriteFldMulti(DRAMC_REG_ZQCS, P_Fld(0, ZQCS_ZQCSDUAL) | P_Fld(0x0, ZQCS_ZQCSMASK));
+    }
+    else if (p->support_channel_num == CHANNEL_DUAL)
+    {
+        // HW ZQ command is channel interleaving since 2 channel share the same ZQ pin.
+        #ifdef ZQCS_ENABLE_LP4
+        // dual channel, ZQCSDUAL =1, and CHA ZQCSMASK=0, CHB ZQCSMASK=1
+
+        vIO32WriteFldMulti_All(DRAMC_REG_ZQCS, P_Fld(1, ZQCS_ZQCSDUAL) | \
+                                               P_Fld(0, ZQCS_ZQCSMASK_OPT) | \
+                                               P_Fld(0, ZQCS_ZQMASK_CGAR) | \
+                                               P_Fld(0, ZQCS_ZQCS_MASK_SEL_CGAR));
+        //Move to DCM off setting
+        //vIO32WriteFldMulti_All(DRAMC_REG_ZQCS, P_Fld(1, ZQCS_ZQCSDUAL) |
+        //                                       P_Fld(0, ZQCS_ZQCSMASK_OPT) |
+        //                                       P_Fld(0, ZQCS_ZQMASK_CGAR));
+
+        // DRAMC CHA(CHN0):ZQCSMASK=1, DRAMC CHB(CHN1):ZQCSMASK=0.
+        // ZQCSMASK setting: (Ch A, Ch B) = (1,0) or (0,1)
+        // if CHA.ZQCSMASK=1, and then set CHA.ZQCALDISB=1 first, else set CHB.ZQCALDISB=1 first
+        vIO32WriteFldAlign(DRAMC_REG_ZQCS + (CHANNEL_A << POS_BANK_NUM), 1, ZQCS_ZQCSMASK);
+        vIO32WriteFldAlign(DRAMC_REG_ZQCS + SHIFT_TO_CHB_ADDR, 0, ZQCS_ZQCSMASK);
+
+        // DRAMC CHA(CHN0):ZQCS_ZQCS_MASK_SEL=0, DRAMC CHB(CHN1):ZQCS_ZQCS_MASK_SEL=0.
+        vIO32WriteFldAlign_All(DRAMC_REG_ZQCS, 0, ZQCS_ZQCS_MASK_SEL);
+        #endif
+    }
+
+    // Disable LP3 HW ZQ
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL), 0, SPCMDCTRL_ZQCSDISB);   //LP3 ZQCSDISB=0
+    // Disable LP4 HW ZQ
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL), 0, SPCMDCTRL_ZQCALDISB);  //LP4 ZQCALDISB=0
+    // ---- End of ZQ CS init -----
+
+    //Disable write-DBI of DRAMC (Avoids pre-defined data pattern being modified)
+    DramcWriteDBIOnOff(p, DBI_OFF);
+    //Disable read-DBI of DRAMC (Avoids pre-defined data pattern being modified)
+    DramcReadDBIOnOff(p, DBI_OFF);
+    //disable MR4 read, REFRDIS=1
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL), 1, SPCMDCTRL_REFRDIS);
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0x1, DQSOSCR_DQSOSCRDIS);  //MR18, MR19 Disable
+    //for(shu_index = SRAM_SHU0; shu_index < DRAM_DFS_SRAM_MAX; shu_index++)
+        //vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCINTV) + SHU_GRP_DRAMC_OFFSET*shu_index, 0x1, SHU_SCINTV_DQSOSCENDIS);
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCINTV), 0x1, SHU_SCINTV_DQSOSCENDIS);
+    //vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SHU2_SCINTV), 0x1, SHU2_SCINTV_DQSOSCENDIS);
+    //vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SHU3_SCINTV), 0x1, SHU3_SCINTV_DQSOSCENDIS);
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN)
+                                            | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN)
+                                            | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN)
+                                            | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG));
+
+    // Disable HW gating tracking first, 0x1c0[31], need to disable both UI and PI tracking or the gating delay reg won't be valid.
+    DramcHWGatingOnOff(p, 0);
+
+    // Disable gating debug
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_STBCAL2), 0, STBCAL2_STB_GERRSTOP);
+
+    for (u1RankIdx = RANK_0; u1RankIdx < RANK_MAX; u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+
+        // Disable RX delay tracking
+        vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B0_RXDVS2), 0x0, R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0);
+        vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B1_RXDVS2), 0x0, R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1);
+
+        vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B0_RXDVS2), 0x0, R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0);
+        vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B1_RXDVS2), 0x0, R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1);
+
+        //RX delay mux, delay vlaue from reg.
+        vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B0_RXDVS2), 0x0, R0_B0_RXDVS2_R_RK0_DVS_MODE_B0);
+        vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B1_RXDVS2), 0x0, R0_B1_RXDVS2_R_RK0_DVS_MODE_B1);
+        vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_CA_RXDVS2), 0x0, R0_CA_RXDVS2_R_RK0_DVS_MODE_CA);
+    }
+    vSetRank(p, u1RankIdxBak);
+
+    // Set to all-bank refresh
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 0, REFCTRL0_PBREFEN);
+
+    // set MRSRK to 0, MPCRKEN always set 1 (Derping)
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_MRS), 0, MRS_MRSRK);
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION), 1, MPC_OPTION_MPCRKEN);
+
+    //RG mode
+    vIO32WriteFldAlign_All(DDRPHY_B0_DQ6, 0x1, B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0);
+    vIO32WriteFldAlign_All(DDRPHY_B1_DQ6, 0x1, B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1);
+    vIO32WriteFldAlign_All(DDRPHY_CA_CMD6, 0x1, CA_CMD6_RG_RX_ARCMD_BIAS_PS);
+
+#if ENABLE_RX_TRACKING
+    DramcRxInputDelayTrackingInit_byFreq(p);
+#endif
+
+#ifdef LOOPBACK_TEST
+#ifdef LPBK_INTERNAL_EN
+    DramcLoopbackTest_settings(p, 0);   //0: internal loopback test 1: external loopback test
+#else
+    DramcLoopbackTest_settings(p, 1);   //0: internal loopback test 1: external loopback test
+#endif
+#endif
+
+#if ENABLE_TMRRI_NEW_MODE
+    SetCKE2RankIndependent(p);
+#endif
+
+#ifdef DUMMY_READ_FOR_TRACKING
+    vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 1, DUMMY_RD_DMY_RD_RX_TRACK);
+#endif
+
+    vIO32WriteFldAlign_All(DRAMC_REG_DRSCTRL, 1, DRSCTRL_DRSDIS);
+
+#ifdef IMPEDANCE_TRACKING_ENABLE
+    // set correct setting to control IMPCAL HW Tracking in shuffle RG
+    // if p->freq >= 1333, enable IMP HW tracking(SHU_DRVING1_DIS_IMPCAL_HW=0), else SHU_DRVING1_DIS_IMPCAL_HW = 1
+    U8 u1DisImpHw;
+    U32 u4TermFreq;
+
+#if (__LP5_COMBO__ == TRUE)
+    if (TRUE == is_lp5_family(p))
+        u4TermFreq = LP5_MRFSP_TERM_FREQ;
+    else
+#endif
+        u4TermFreq = LP4_MRFSP_TERM_FREQ;
+
+    u1DisImpHw = (p->frequency >= u4TermFreq)? 0: 1;
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING1, u1DisImpHw, SHU_MISC_DRVING1_DIS_IMPCAL_HW);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING1, u1DisImpHw, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING2, u1DisImpHw, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD12, u1DisImpHw, SHU_CA_CMD12_RG_RIMP_UNTERM_EN);
+#endif
+
+
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION && RX_DELAY_PRE_CAL
+    s2RxDelayPreCal = PASS_RANGE_NA; // reset variable for fast k test
+#endif
+#endif
+}
+
+
+
+/* vDramcInit_PreSettings(): Initial register settings(which are required to be set before all calibration flow) */
+#if 0
+static void vDramcInit_PreSettings(DRAMC_CTX_T *p)
+{
+#if __A60868_TO_BE_PORTING__
+
+    /* PAD_RRESETB control sequence */
+    //remove twice dram reset pin pulse before dram power on sequence flow
+    vIO32WriteFldMulti(DDRPHY_CA_CMD8, P_Fld(0x0, CA_CMD8_RG_TX_RRESETB_PULL_UP) | P_Fld(0x0, CA_CMD8_RG_TX_RRESETB_PULL_DN)
+                                     | P_Fld(0x1, CA_CMD8_RG_TX_RRESETB_DDR3_SEL) | P_Fld(0x0, CA_CMD8_RG_TX_RRESETB_DDR4_SEL)
+                                     | P_Fld(0xa, CA_CMD8_RG_RRESETB_DRVP) | P_Fld(0xa, CA_CMD8_RG_RRESETB_DRVN));
+    vIO32WriteFldAlign(DDRPHY_MISC_CTRL1, 0x1, MISC_CTRL1_R_DMRRESETB_I_OPT); //Change to glitch-free path
+    //replace DDRCONF0_GDDR3RST with MISC_CTRL1_R_DMDA_RRESETB_I
+    vIO32WriteFldAlign(DDRPHY_MISC_CTRL1, 0x0, MISC_CTRL1_R_DMDA_RRESETB_I);
+    vIO32WriteFldAlign(DDRPHY_MISC_CTRL1, 0x1, MISC_CTRL1_R_DMDA_RRESETB_E);
+#if __ETT__
+    if (GetDramcBroadcast() == DRAMC_BROADCAST_OFF)
+    {   // In this function, broadcast is assumed to be ON(LP4) -> Show error if broadcast is OFF
+        mcSHOW_ERR_MSG(("Err! Broadcast is OFF!\n"));
+    }
+#endif
+    return;
+#endif
+}
+#endif
+static void DramcInit_DutyCalibration(DRAMC_CTX_T *p)
+{
+#if ENABLE_DUTY_SCAN_V2
+    U8 channel_idx, channel_backup = vGetPHY2ChannelMapping(p);
+    U32 u4backup_broadcast= GetDramcBroadcast();
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+#ifndef DUMP_INIT_RG_LOG_TO_DE
+    if (Get_MDL_Used_Flag()==NORMAL_USED)
+    {
+        for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
+        {
+            vSetPHY2ChannelMapping(p, channel_idx);
+            DramcNewDutyCalibration(p);
+        }
+        vSetPHY2ChannelMapping(p, channel_backup);
+    }
+#endif
+
+    DramcBroadcastOnOff(u4backup_broadcast);
+
+#endif
+}
+
+static void SV_BroadcastOn_DramcInit(DRAMC_CTX_T *p)
+{
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+
+    if(!is_lp5_family(p))
+    {
+        if(p->frequency>=2133)  //Term
+        {
+            mcSHOW_DBG_MSG2(("sv_algorithm_assistance_LP4_4266 \n"));
+            sv_algorithm_assistance_LP4_4266(p);
+        }
+        else if(p->frequency>=1333)  //Term
+        {
+            mcSHOW_DBG_MSG2(("sv_algorithm_assistance_LP4_3733 \n"));
+            sv_algorithm_assistance_LP4_3733(p);
+        }
+        else if(p->frequency>400) //Unterm
+        {
+            mcSHOW_DBG_MSG2(("sv_algorithm_assistance_LP4_1600 \n"));
+            sv_algorithm_assistance_LP4_1600(p);
+        }
+        else if(p->frequency==400)  //DDR800 Semi-Open
+        {
+            //mcSHOW_DBG_MSG(("CInit_golden_mini_freq_related_vseq_LP4_1600 \n"));
+            //CInit_golden_mini_freq_related_vseq_LP4_1600(p);
+            //CInit_golden_mini_freq_related_vseq_LP4_1600_SHU1(DramcConfig);
+            mcSHOW_DBG_MSG2(("sv_algorithm_assistance_LP4_800 \n"));
+            sv_algorithm_assistance_LP4_800(p);
+        }
+        else //DDR400 Open Loop
+        {
+            mcSHOW_DBG_MSG(("sv_algorithm_assistance_LP4_400 \n"));
+            sv_algorithm_assistance_LP4_400(p);
+        }
+    }
+    #if __LP5_COMBO__
+    else
+    {
+        if(p->freq_sel==LP5_DDR4266)
+        {
+            mcSHOW_DBG_MSG2(("CInit_golden_mini_freq_related_vseq_LP5_4266 \n"));
+            CInit_golden_mini_freq_related_vseq_LP5_4266(p);
+        }
+        else if(p->freq_sel==LP5_DDR5500)
+        {
+            mcSHOW_DBG_MSG2(("CInit_golden_mini_freq_related_vseq_LP5_5500 \n"));
+            CInit_golden_mini_freq_related_vseq_LP5_5500(p);
+        }
+        else
+        {
+            mcSHOW_DBG_MSG2(("CInit_golden_mini_freq_related_vseq_LP5_3200 \n"));
+            CInit_golden_mini_freq_related_vseq_LP5_3200(p);
+            CInit_golden_mini_freq_related_vseq_LP5_3200_SHU1(p);
+        }
+    }
+    #endif
+
+    RESETB_PULL_DN(p);
+    ANA_init(p);
+    DIG_STATIC_SETTING(p);
+    DIG_CONFIG_SHUF(p,0,0); //temp ch0 group 0
+
+#if __LP5_COMBO__
+    if(is_lp5_family(p))
+    {
+        LP5_UpdateInitialSettings(p);
+    }
+    else
+#endif
+    {
+        LP4_UpdateInitialSettings(p);
+    }
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+}
+
+static void GetRealFreq_at_Init(DRAMC_CTX_T *p){
+    gddrphyfmeter_value[vGet_Current_SRAMIdx(p)] = DDRPhyFreqMeter(p);
+}
+
+DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p)
+{
+
+#ifdef FOR_HQA_REPORT_USED
+    if (gHQALog_flag==1)
+    {
+        mcSHOW_DBG_MSG(("[HQA] Log parsing, "));
+        mcSHOW_DBG_MSG(("\tDram Data rate = ")); HQA_LOG_Print_Freq_String(p); mcSHOW_DBG_MSG(("\n"));
+    }
+#endif
+
+    //CInit_ConfigFromTBA();
+    mcSHOW_DBG_MSG(("MEM_TYPE=%d, freq_sel=%d\n", MEM_TYPE, p->freq_sel));
+
+    SV_BroadcastOn_DramcInit(p); // @Darren, Broadcast Off after SV_BroadcastOn_DramcInit done
+
+    #if PRINT_CALIBRATION_SUMMARY
+    //default set DRAM status = NO K
+    memset(p->aru4CalResultFlag, 0xffff, sizeof(p->aru4CalResultFlag));
+    memset(p->aru4CalExecuteFlag, 0, sizeof(p->aru4CalExecuteFlag));
+    #if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK
+    memset(p->FastKResultFlag, 0xffff, sizeof(p->FastKResultFlag));
+    memset(p->FastKExecuteFlag, 0, sizeof(p->FastKExecuteFlag));
+    #endif
+    #endif
+
+    EnableDramcPhyDCM(p, DCM_OFF); //Let CLK always free-run
+    vResetDelayChainBeforeCalibration(p);
+#if __LP5_COMBO__
+    if(!is_lp5_family(p))
+#endif
+        DVFSSettings(p);
+
+#if REPLACE_DFS_RG_MODE
+    DPMInit(p);
+    #if ENABLE_DFS_RUNTIME_MRW
+    DFSRuntimeFspMRW(p);
+    #endif
+    mcSHOW_DBG_MSG2(("DPMInit(p);done\n"));
+#endif
+
+    GetRealFreq_at_Init(p);
+
+    vSetRank(p, RANK_0);
+
+    // 8PhaseCal need executed before DutyCal
+#ifdef DDR_INIT_TIME_PROFILING
+    U32 CPU_Cycle;
+    TimeProfileBegin();
+#endif
+    Dramc8PhaseCal(p);
+#ifdef DDR_INIT_TIME_PROFILING
+    CPU_Cycle=TimeProfileEnd();
+    mcSHOW_TIME_MSG(("\t8PHaseCal takes %d us\n", CPU_Cycle));
+    TimeProfileBegin();
+#endif
+    DramcInit_DutyCalibration(p);
+#ifdef DDR_INIT_TIME_PROFILING
+    CPU_Cycle=TimeProfileEnd();
+    mcSHOW_TIME_MSG(("\tDutyCalibration takes %d us\n", CPU_Cycle));
+#endif
+
+#if __LP5_COMBO__
+    if(is_lp5_family(p))
+    {
+        LP5_DRAM_INIT(p); // Notice: LP5_DRAM_INIT is Broadcast On
+    }
+    else
+#endif
+    {
+        //LP4_DRAM_INIT(p);
+        DramcModeRegInit_LP4(p);
+    }
+
+    DdrUpdateACTiming(p);
+
+    memset(p->isWLevInitShift, FALSE, sizeof(p->isWLevInitShift));
+
+    #if BYPASS_CALIBRATION
+    if(p->freq_sel==LP4_DDR4266 || p->freq_sel==LP4_DDR3200)
+    {
+        Apply_LP4_4266_Calibraton_Result(p);
+    }
+
+    else if(p->freq_sel==LP4_DDR1600)
+    {
+        mcSHOW_DBG_MSG(("BYPASS CALIBRATION LP4 1600 \n"));
+        Apply_LP4_1600_Calibraton_Result(p);
+    }
+    #endif
+
+#if 0//__A60868_TO_BE_PORTING__
+
+    U32 save_ch, dram_t; //Darren
+    #if (!__ETT__ && !FOR_DV_SIMULATION_USED && SW_CHANGE_FOR_SIMULATION == 0)
+    EMI_SETTINGS *emi_set; //Darren
+    #endif
+    U8 dram_cbt_mode;
+
+    mcSHOW_DBG_MSG(("\n[DramcInit]\n"));
+
+    vSetPHY2ChannelMapping(p, CHANNEL_A);
+
+    //default set DRAM status = NO K
+    memset(p->aru4CalResultFlag, 0xffff, sizeof(p->aru4CalResultFlag));
+    memset(p->aru4CalExecuteFlag, 0, sizeof(p->aru4CalExecuteFlag));
+
+    DramcSetting_Olympus_LP4_ByteMode(p);
+
+    DramcInit_DutyCalibration(p);
+
+    DramcModeRegInit_LP4(p);
+
+    //DdrUpdateACTiming(p);
+
+#if 0  //update refresh rate
+    // for free-run clk 26MHz, 0x62 * (1/26) = 3.8ns
+    vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_PD_CTRL, 0x62, DRAMC_PD_CTRL_REFCNT_FR_CLK);
+    // for non-fre-run clk,  reg = 3.8 ns * f / 4 / 16;
+    u4RefreshRate = 38 * p->frequency / 640;
+    vIO32WriteFldAlign_All(DRAMC_REG_CONF2, u4RefreshRate, CONF2_REFCNT);
+#endif
+
+#if (fcFOR_CHIP_ID == fcLafite)
+    // For kernel api for check LPDDR3/4/4X (Darren), only for fcOlympus and fcElbrus.
+    // For Other chip, please confirm the register is free for SW use.
+    save_ch = vGetPHY2ChannelMapping(p);
+    vSetPHY2ChannelMapping(p, CHANNEL_A);
+
+    switch (p->dram_type)
+    {
+        case TYPE_LPDDR4:
+            dram_t = 2;
+            break;
+        case TYPE_LPDDR4X:
+            dram_t = 3;
+            break;
+        case TYPE_LPDDR4P:
+            dram_t = 4;
+            break;
+        default:
+            dram_t = 0;
+            mcSHOW_ERR_MSG(("Incorrect DRAM Type!\n"));
+            break;
+    }
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_ARBCTL), dram_t, ARBCTL_RSV_DRAM_TYPE);
+
+    // For DRAM normal, byte and mixed mode
+    if ((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE))
+        dram_cbt_mode = CBT_R0_R1_NORMAL;
+    else if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_BYTE_MODE1))
+        dram_cbt_mode = CBT_R0_R1_BYTE;
+    else if ((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_BYTE_MODE1))
+        dram_cbt_mode = CBT_R0_NORMAL_R1_BYTE;
+    else if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE))
+        dram_cbt_mode = CBT_R0_BYTE_R1_NORMAL;
+    else
+        dram_cbt_mode = CBT_R0_R1_NORMAL;
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RSTMASK), dram_cbt_mode, RSTMASK_RSV_DRAM_CBT_MIXED);
+
+    // Sagy: Keep original setting till OS kernel ready, if ready, remove it
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_ARBCTL), (p->dram_cbt_mode[RANK_0] | p->dram_cbt_mode[RANK_1]), ARBCTL_RSV_DRAM_CBT);
+
+    vSetPHY2ChannelMapping(p, save_ch);
+#endif
+
+    mcSHOW_DBG_MSG3(("[DramcInit] Done\n"));
+#endif//__A60868_TO_BE_PORTING__
+    return DRAM_OK;
+}
+
+#if 0
+static void Switch26MHzDisableDummyReadRefreshAllBank(DRAMC_CTX_T *p)
+{
+#if __A60868_TO_BE_PORTING__
+
+    vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_CLK_MEM_SEL);//Switch clk to 26MHz
+    vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 1, MISC_CG_CTRL0_W_CHG_MEM);
+    vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_W_CHG_MEM);
+
+    vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0, REFCTRL0_PBREFEN);//Switch to all bank refresh
+
+    vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DQSG_DMYWR_EN)//Disable Dummy Read
+                | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN) | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN)
+                | P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN) | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG)
+                | P_Fld(0x0, DUMMY_RD_DMY_WR_DBG));
+#endif
+    return;
+}
+#endif
+
+
+#if ENABLE_TMRRI_NEW_MODE
+void SetCKE2RankIndependent(DRAMC_CTX_T *p)
+{
+    #if ENABLE_TMRRI_NEW_MODE//Newly added CKE control mode API
+    mcSHOW_DBG_MSG2(("SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON\n"));
+    vCKERankCtrl(p, CKE_RANK_INDEPENDENT);
+    #else //Legacy individual CKE control register settings
+    mcSHOW_DBG_MSG2(("SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: OFF\n"));
+    vCKERankCtrl(p, CKE_RANK_DEPENDENT);
+    #endif
+}
+#endif
+
+
+#if ENABLE_WRITE_DBI
+void EnableDRAMModeRegWriteDBIAfterCalibration(DRAMC_CTX_T *p)
+{
+    U8 channel_idx, rank_idx;
+    U8 ch_backup, rank_backup, u1FSPIdx = 0;
+    //S8 u1ShuffleIdx;
+
+    ch_backup = p->channel;
+    rank_backup = p->rank;
+
+    for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
+    {
+        vSetPHY2ChannelMapping(p, channel_idx);
+        for (rank_idx = RANK_0; rank_idx < p->support_rank_num; rank_idx++)
+        {
+            vSetRank(p, rank_idx);
+            for (u1FSPIdx = FSP_0; u1FSPIdx < p->support_fsp_num; u1FSPIdx++)
+            {
+                DramcMRWriteFldAlign(p, 13, u1FSPIdx, MR13_FSP_WR, TO_MR);
+                SetDramModeRegForWriteDBIOnOff(p, u1FSPIdx, p->DBI_W_onoff[u1FSPIdx]);
+            }
+        }
+    }
+
+    vSetRank(p, rank_backup);
+    vSetPHY2ChannelMapping(p, ch_backup);
+}
+#endif
+
+#if ENABLE_READ_DBI
+void EnableDRAMModeRegReadDBIAfterCalibration(DRAMC_CTX_T *p)
+{
+    U8 channel_idx, rank_idx;
+    U8 ch_backup, rank_backup, u1FSPIdx = 0;
+    S8 u1ShuffleIdx;
+
+    ch_backup = p->channel;
+    rank_backup = p->rank;
+
+    for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
+    {
+        vSetPHY2ChannelMapping(p, channel_idx);
+        for (rank_idx = RANK_0; rank_idx < p->support_rank_num; rank_idx++)
+        {
+            vSetRank(p, rank_idx);
+            for (u1FSPIdx = FSP_0; u1FSPIdx < p->support_fsp_num; u1FSPIdx++)
+            {
+                DramcMRWriteFldAlign(p, 13, u1FSPIdx, MR13_FSP_WR, TO_MR);
+                SetDramModeRegForReadDBIOnOff(p, u1FSPIdx, p->DBI_R_onoff[u1FSPIdx]);
+            }
+        }
+    }
+
+    //[Ei_ger] DVT item RD2MRR & MRR2RD
+    vIO32WriteFldMulti_All(DRAMC_REG_HW_MRR_FUN, P_Fld(0x1, HW_MRR_FUN_TR2MRR_ENA)
+                                           | P_Fld(0x1, HW_MRR_FUN_R2MRRHPRICTL)
+                                           | P_Fld(0x1, HW_MRR_FUN_MANTMRR_EN));
+
+    vSetRank(p, rank_backup);
+    vSetPHY2ChannelMapping(p, ch_backup);
+}
+#endif
+
+
+static void SetMr13VrcgToNormalOperationShuffle(DRAMC_CTX_T *p)//Only set DRAM_DFS_SHUFFLE_1
+{
+    U32 u4Value = 0;
+
+    u4Value = u4IO32ReadFldAlign(DRAMC_REG_SHU_HWSET_VRCG, SHU_HWSET_VRCG_HWSET_VRCG_OP);
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_VRCG, u4Value & ~(0x1 << 3), SHU_HWSET_VRCG_HWSET_VRCG_OP);
+    return;
+}
+
+#if ENABLE_LP4Y_DFS
+void ENABLE_ClkSingleEndRG (DRAMC_CTX_T *p, U8 u1OnOff)
+{
+    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD13, P_Fld( u1OnOff, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA) \
+                                                      | P_Fld( u1OnOff, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA));
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD7, u1OnOff, SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK);
+}
+
+void ENABLE_WDQSSingleEndRG (DRAMC_CTX_T *p, U8 u1OnOff)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ13, P_Fld( !u1OnOff, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) \
+                                                                | P_Fld(!u1OnOff, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) \
+                                                                | P_Fld( u1OnOff, SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0) \
+                                                                | P_Fld( u1OnOff, SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0));
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ7, u1OnOff , SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0);
+
+    if (isLP4_DSC)
+    {
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD13, P_Fld(!u1OnOff, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_EN_CA) \
+                                                                    | P_Fld(!u1OnOff, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA) \
+                                                                    | P_Fld( u1OnOff, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA) \
+                                                                    | P_Fld( u1OnOff, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA));
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD7, u1OnOff , SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK);
+    }
+    else
+    {
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ13, P_Fld(!u1OnOff, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) \
+                                                                    | P_Fld(!u1OnOff, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) \
+                                                                    | P_Fld( u1OnOff, SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1) \
+                                                                    | P_Fld( u1OnOff, SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1));
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ7, u1OnOff , SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1);
+    }
+}
+
+void ENABLE_RDQSSingleEndRG (DRAMC_CTX_T *p, U8 u1OnOff)
+{
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ10, u1OnOff, SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0);
+    if (p->DRAMPinmux == PINMUX_DSC)
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10, u1OnOff, SHU_CA_CMD10_RG_RX_ARCLK_SE_EN_CA);
+    else
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ10, u1OnOff, SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1);
+}
+
+void ENABLE_SingleEndRGEnable (DRAMC_CTX_T *p, U16 u2Freq)
+{
+    if (u2Freq <= 800)
+    {
+        ENABLE_ClkSingleEndRG (p, ENABLE);
+        ENABLE_WDQSSingleEndRG (p, ENABLE);
+        ENABLE_RDQSSingleEndRG (p, ENABLE);
+    }
+}
+#endif
+
+void SetMr13VrcgToNormalOperation(DRAMC_CTX_T *p)
+{
+    DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p);
+    DRAM_RANK_T eOriRank = u1GetRank(p);
+    U8 u1ChIdx = CHANNEL_A;
+    U8 u1RankIdx = 0;
+
+#if MRW_CHECK_ONLY
+    mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+#endif
+
+    for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1ChIdx);
+        //To DRAM: MR13[3] = 0
+        for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+        {
+            vSetRank(p, u1RankIdx);
+            DramcModeRegWriteByRank(p, u1RankIdx, 13, u1MR13Value[u1RankIdx]);
+            DramcMRWriteFldAlign(p, 13, 0, MR13_VRCG, JUST_TO_GLOBAL_VALUE);
+        }
+    }
+    vSetPHY2ChannelMapping(p, (U8)eOriChannel);
+    vSetRank(p, (U8)eOriRank);
+    return;
+}
+
+
+static void DramcShuTrackingDcmSeEnBySRAM(DRAMC_CTX_T *p)
+{
+#if (fcFOR_CHIP_ID == fcA60868)
+    U8 u1ShuffleIdx, ShuRGAccessIdxBak;
+
+    ShuRGAccessIdxBak = p->ShuRGAccessIdx;
+    mcSHOW_DBG_MSG2(("\n==[DramcShuTrackingDcmEnBySRAM]==\n"));
+    for (u1ShuffleIdx = 0; u1ShuffleIdx <= 1; u1ShuffleIdx++) //fill SHU1 of conf while (u1ShuffleIdx==DRAM_DFS_SRAM_MAX)
+    {
+        //Aceess DMA SRAM by APB bus use debug mode by conf SHU3
+        p->ShuRGAccessIdx = u1ShuffleIdx;
+        #ifdef HW_GATING
+        //DramcHWGatingOnOff(p, 1, u4DramcShuOffset); // Enable HW gating tracking
+        #endif
+
+        #if ENABLE_TX_TRACKING
+        Enable_TX_Tracking(p);
+        #endif
+
+        #if RDSEL_TRACKING_EN
+        Enable_RDSEL_Tracking(p, u2Freq);
+        #endif
+
+        #ifdef HW_GATING
+        Enable_Gating_Tracking(p); // Enable HW gating tracking
+        #endif
+    }
+    p->ShuRGAccessIdx = ShuRGAccessIdxBak;
+#else
+    DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable = p->pDFSTable; // from dramc conf shu0
+    U8 u1ShuffleIdx;
+    U16 u2Freq = 0;
+
+    U32 u4RegBackupAddress[] =
+    {
+        (DDRPHY_REG_MISC_SRAM_DMA0),
+        (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHB_ADDR),
+        (DDRPHY_REG_MISC_SRAM_DMA1),
+        (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHB_ADDR),
+#if (CHANNEL_NUM==4)
+        (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHC_ADDR),
+        (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHD_ADDR),
+        (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHC_ADDR),
+        (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHD_ADDR),
+#endif
+    };
+
+    //Backup regs
+    DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+
+    #if (ENABLE_TX_TRACKING && TX_RETRY_ENABLE)
+    Enable_and_Trigger_TX_Retry(p);
+    #endif
+
+    //Aceess DMA SRAM by APB bus use debug mode by conf SHU3
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);//before setting
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS);
+
+    for (u1ShuffleIdx = 0; u1ShuffleIdx <= DRAM_DFS_SRAM_MAX; u1ShuffleIdx++) //fill SHU1 of conf while (u1ShuffleIdx==DRAM_DFS_SRAM_MAX)
+    {
+        if (u1ShuffleIdx == DRAM_DFS_SRAM_MAX)
+        {
+            //for SHU0 restore to SRAM
+            vSetDFSTable(p, pFreqTable);//Restore DFS table
+            u2Freq = GetFreqBySel(p, p->pDFSTable->freq_sel);
+            //Restore regs, or SHU0 RG cannot be set
+            DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+            p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;//Since access conf SHU0
+        }
+        else
+        {
+            //Aceess DMA SRAM by APB bus use debug mode by conf SHU1
+            vSetDFSTable(p, get_FreqTbl_by_SRAMIndex(p, u1ShuffleIdx));//Update DFS table
+            u2Freq = GetFreqBySel(p, p->pDFSTable->freq_sel);
+            vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);//before setting
+            vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, u1ShuffleIdx, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL);
+            //APB bus use debug mode by conf SHU1
+            vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL);//Trigger DEBUG MODE
+            p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1;
+        }
+        // add your function
+        // For example: EnableDramcPhyDCMShuffle(p, enable_dcm, u4DramcShuOffset, u4DDRPhyShuOffset, u1ShuffleIdx);
+#if ENABLE_TX_TRACKING
+        Enable_TX_Tracking(p);
+#endif
+#if RDSEL_TRACKING_EN
+        Enable_RDSEL_Tracking(p, u2Freq);
+#endif
+#ifdef HW_GATING
+        Enable_Gating_Tracking(p); // Enable HW gating tracking
+#endif
+
+#if ENABLE_PER_BANK_REFRESH && (!IMP_TRACKING_PB_TO_AB_REFRESH_WA)
+        Enable_PerBank_Refresh(p);
+#endif
+
+        EnableRxDcmDPhy(p, u2Freq);
+        EnableCmdPicgEffImprove(p);
+        Enable_ClkTxRxLatchEn(p); // for new xrank mode
+#if ENABLE_TX_WDQS // @Darren, To avoid unexpected DQS toggle during calibration
+        Enable_TxWDQS(p);
+#endif
+
+#if ENABLE_LP4Y_DFS && (LP4Y_BACKUP_SOLUTION == 0)
+        ENABLE_SingleEndRGEnable (p, u2Freq);
+#endif
+
+#if (SW_CHANGE_FOR_SIMULATION == 0)
+#if APPLY_LOWPOWER_GOLDEN_SETTINGS
+        int enable_dcm = (doe_get_config("dramc_dcm")) ? 0 : 1;
+        EnableDramcPhyDCMShuffle(p, enable_dcm);
+#else
+        EnableDramcPhyDCMShuffle(p, 0);
+#endif
+#endif
+        SetMr13VrcgToNormalOperationShuffle(p);
+
+        p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
+    }
+#endif
+}
+
+#if ENABLE_PER_BANK_REFRESH
+void DramcSetPerBankRefreshMode(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(1, REFCTRL0_PBREF_BK_REFA_ENA) | P_Fld(2, REFCTRL0_PBREF_BK_REFA_NUM));
+
+#if PER_BANK_REFRESH_USE_MODE==0
+        vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(0, REFCTRL0_KEEP_PBREF) | P_Fld(0, REFCTRL0_KEEP_PBREF_OPT)); //Original mode
+        mcSHOW_DBG_MSG(("\tPER_BANK_REFRESH: Original Mode\n"));
+#endif
+
+#if PER_BANK_REFRESH_USE_MODE==1
+        vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(0, REFCTRL0_KEEP_PBREF) | P_Fld(1, REFCTRL0_KEEP_PBREF_OPT)); //Hybrid mode
+        mcSHOW_DBG_MSG(("\tPER_BANK_REFRESH: Hybrid Mode\n"));
+#endif
+
+#if PER_BANK_REFRESH_USE_MODE==2
+        vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(1, REFCTRL0_KEEP_PBREF) | P_Fld(0, REFCTRL0_KEEP_PBREF_OPT)); //Always per-bank mode
+        mcSHOW_DBG_MSG(("\tPER_BANK_REFRESH: Always Per-Bank Mode\n"));
+#endif
+
+    vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 1, REFCTRL1_REFPB2AB_IGZQCS);
+
+}
+#endif
+
+#ifdef TEMP_SENSOR_ENABLE
+void DramcHMR4_Presetting(DRAMC_CTX_T *p)
+{
+    U8 backup_channel = p->channel;
+    U8 channelIdx;
+
+    for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++)
+    {
+        vSetPHY2ChannelMapping(p, channelIdx);
+    //    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), Refr_rate_manual_trigger, REFCTRL1_REFRATE_MANUAL_RATE_TRIG);
+    //    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), Refr_rate_manual, REFCTRL1_REFRATE_MANUAL);
+
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_REFR_PERIOD_OPT);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 0, HMR4_REFRCNT_OPT);    // 0: 3.9us * cnt, 1: 15.6us * cnt
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HMR4_DVFS_CTRL0), 0x80, SHU_HMR4_DVFS_CTRL0_REFRCNT);
+
+        // Support byte mode, default disable
+        // Support byte/normal mode
+        if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_HMR4_BYTEMODE_EN);
+        else
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 0, HMR4_HMR4_BYTEMODE_EN);
+
+        // Toggle to clear record
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), 0, REFCTRL1_REFRATE_MON_CLR);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), 1, REFCTRL1_REFRATE_MON_CLR);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), 0, REFCTRL1_REFRATE_MON_CLR);
+    }
+    vSetPHY2ChannelMapping(p, backup_channel);
+
+}
+#endif
+
+static void SwitchHMR4(DRAMC_CTX_T *p, bool en)
+{
+#ifdef __LP5_COMBO__
+    if (is_lp5_family(p))
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_REF_BOUNCE2, 9, REF_BOUNCE2_PRE_MR4INT_TH);
+
+        vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL2, 9, REFCTRL2_MR4INT_TH);
+
+    }
+    else
+#endif
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_REF_BOUNCE2, 5, REF_BOUNCE2_PRE_MR4INT_TH);
+
+        vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL2, 5, REFCTRL2_MR4INT_TH);
+    }
+
+    // TOG_OPT, 0: Read rank0 only, 1: read both rank0 and rank1
+    if (en && p->support_rank_num == RANK_DUAL)
+        vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 1, HMR4_HMR4_TOG_OPT);   // Read both rank0 and rank1
+    else
+        vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 0, HMR4_HMR4_TOG_OPT);   // Read rank0 only (need for manual/SW MRR)
+
+    vIO32WriteFldAlign_All(DRAMC_REG_HMR4, !en, HMR4_REFRDIS);
+
+#if 0   // Reading HMR4 repeatedly for debugging
+    while(1)
+    {
+        mcSHOW_DBG_MSG(("@@ --------------------\n"));
+        mcSHOW_DBG_MSG(("@@ MISC_STATUSA_REFRESH_RATE: %d\n",
+            u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_REFRESH_RATE)));
+        mcSHOW_DBG_MSG(("@@ MIN: %d, MAX: %d\n",
+            u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON), HW_REFRATE_MON_REFRESH_RATE_MIN_MON),
+            u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON), HW_REFRATE_MON_REFRESH_RATE_MAX_MON)));
+
+        // if HMR4_HMR4_TOG_OPT == 1
+        {
+            mcSHOW_DBG_MSG(("@@         MIN    MAX\n"));
+            mcSHOW_DBG_MSG(("@@ RK0_B0:  %d     %d\n",
+                u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MIN_MON_RK0_B0),
+                u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MAX_MON_RK0_B0)));
+            mcSHOW_DBG_MSG(("@@ RK1_B0:  %d     %d\n",
+                u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MIN_MON_RK1_B0),
+                u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MAX_MON_RK1_B0)));
+            mcSHOW_DBG_MSG(("@@ RK0_B1:  %d     %d\n",
+                u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MIN_MON_RK0_B1),
+                u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MAX_MON_RK0_B1)));
+            mcSHOW_DBG_MSG(("@@ RK1_B1:  %d     %d\n",
+                u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MIN_MON_RK1_B1),
+                u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MAX_MON_RK1_B1)));
+        }
+
+        mcSHOW_DBG_MSG(("@@ Wait to measure!!\n\n"));
+        Sleep(500);
+    }
+#endif
+}
+
+#if ENABLE_REFRESH_RATE_DEBOUNCE
+static void DramcRefreshRateDeBounceEnable(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti_All(DRAMC_REG_REF_BOUNCE1, P_Fld(0x4 , REF_BOUNCE1_REFRATE_DEBOUNCE_COUNT) | // when De-bounce counter >= this count, then dramc apply new dram's MR4 value
+                                                  P_Fld(5 , REF_BOUNCE1_REFRATE_DEBOUNCE_TH) |  // MR4 value >= 0.5X refresh rate, then de-bounce count active
+                                                  P_Fld(0 , REF_BOUNCE1_REFRATE_DEBOUNCE_OPT) |
+                                                  P_Fld(0xff1f , REF_BOUNCE1_REFRATE_DEBOUNCE_DIS) ); //all bits set 1 to disable debounce function
+}
+#endif
+
+#if DRAMC_MODIFIED_REFRESH_MODE
+void DramcModifiedRefreshMode(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti_All(DRAMC_REG_REFPEND1, P_Fld(2, REFPEND1_MPENDREFCNT_TH0)
+                                            | P_Fld(2, REFPEND1_MPENDREFCNT_TH1)
+                                            | P_Fld(4, REFPEND1_MPENDREFCNT_TH2)
+                                            | P_Fld(5, REFPEND1_MPENDREFCNT_TH3)
+                                            | P_Fld(5, REFPEND1_MPENDREFCNT_TH4)
+                                            | P_Fld(3, REFPEND1_MPENDREFCNT_TH5)
+                                            | P_Fld(3, REFPEND1_MPENDREFCNT_TH6)
+                                            | P_Fld(3, REFPEND1_MPENDREFCNT_TH7));
+    vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL1, P_Fld(1, REFCTRL1_REFPEND_OPT1) | P_Fld(1, REFCTRL1_REFPEND_OPT2));
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_REF0, 4, SHU_REF0_MPENDREF_CNT);
+}
+#endif
+
+#if DRAMC_CKE_DEBOUNCE
+void DramcCKEDebounce(DRAMC_CTX_T *p)
+{
+    U8 u1CKE_DBECnt = 15;
+    U8 rank_backup, u1RKIdx=0;
+    if(p->frequency>=1866)
+    {
+        rank_backup = p->rank;
+        for(u1RKIdx=0; u1RKIdx<p->support_rank_num; u1RKIdx++)
+        {
+            vSetRank(p, u1RKIdx);
+            vIO32WriteFldAlign_All(DRAMC_REG_SHURK_CKE_CTRL, u1CKE_DBECnt, SHURK_CKE_CTRL_CKE_DBE_CNT);
+            mcSHOW_DBG_MSG2(("CKE Debounce cnt = %d\n", u1CKE_DBECnt));
+        }
+        vSetRank(p, rank_backup);
+    }
+}
+#endif
+
+#if OPEN_LOOP_MODE_CLK_TOGGLE_WA
+static void ToggleOpenLoopModeClk(DRAMC_CTX_T *p)
+{
+        U8 u1ChannelMode = (p->support_channel_num == CHANNEL_DUAL)?3:1;
+
+    #if defined(DPM_CONTROL_AFTERK) && ((DRAMC_DFS_MODE%2) != 0)
+        mcSHOW_DBG_MSG(("[WARNING] DDR400 out (DPM RG/PST MODE) Toggle CLK WA\n"));
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1ChannelMode, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
+        mcDELAY_US(1);
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1ChannelMode, LPIF_LOW_POWER_CFG_1_DPY_BCLK_ENABLE);
+        mcDELAY_US(1);
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1ChannelMode, LPIF_LOW_POWER_CFG_1_SHU_RESTORE);
+        mcDELAY_US(1);
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_SHU_RESTORE);
+        mcDELAY_US(1);
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DPY_BCLK_ENABLE);
+        mcDELAY_US(1);
+        vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
+        mcDELAY_US(1);
+    #else //PHY_RG_MODE
+        mcSHOW_DBG_MSG(("[WARNING] DDR400 out (PHY RG MODE) Toggle CLK WA\n"));
+
+        //set SPM project code and enable clock enable
+        vIO32WriteFldMulti(SPM_POWERON_CONFIG_EN, P_Fld(0xB16, POWERON_CONFIG_EN_PROJECT_CODE) | P_Fld(1, POWERON_CONFIG_EN_BCLK_CG_EN));
+
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN);
+        mcDELAY_US(1);
+        vIO32WriteFldAlign(DRAMC_DPY_CLK_SW_CON_0, u1ChannelMode, DRAMC_DPY_CLK_SW_CON_0_SW_DPY_BCLK_ENABLE);
+        mcDELAY_US(1);
+        vIO32WriteFldAlign(DRAMC_DPY_CLK_SW_CON_1, u1ChannelMode, DRAMC_DPY_CLK_SW_CON_1_SW_SHU_RESTORE);
+        mcDELAY_US(1);
+        vIO32WriteFldAlign(DRAMC_DPY_CLK_SW_CON_1, 0, DRAMC_DPY_CLK_SW_CON_1_SW_SHU_RESTORE);
+        mcDELAY_US(1);
+        vIO32WriteFldAlign(DRAMC_DPY_CLK_SW_CON_0, 0, DRAMC_DPY_CLK_SW_CON_0_SW_DPY_BCLK_ENABLE);
+        mcDELAY_US(1);
+        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN);
+        mcDELAY_US(1);
+
+        //Other WA
+        //DramcDFSDirectJump_SRAMShuRGMode(p, SRAM_SHU7);
+        //DramcDFSDirectJump_SRAMShuRGMode(p, SRAM_SHU7);
+    #endif
+}
+#endif
+
+//1.Some RG setting will need to be DCM on, since not consider S0 2.ENABLE_RX_DCM_DPHY should be 1
+#if 0
+static void S0_DCMOffWA(DRAMC_CTX_T *p)//For S0 + DCM off
+{
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0,
+            P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE) |
+            P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE) |
+            P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE) |
+            P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE) |
+            P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE) |
+            P_Fld(0x0, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE) |
+            P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE) |
+            P_Fld(0x0, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE) |
+            P_Fld(0x0, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE));
+}
+#endif
+void DramcRunTimeConfig(DRAMC_CTX_T *p)
+{
+#if (fcFOR_CHIP_ID == fcA60868)
+    u1EnterRuntime = 1;
+#endif
+
+    mcSHOW_DBG_MSG(("[DramcRunTimeConfig]\n"));
+
+    SetDramInfoToConf(p);
+
+#if defined(DPM_CONTROL_AFTERK) && ((DRAMC_DFS_MODE%2) != 0) && (REPLACE_DFS_RG_MODE==0)// for DPM RG/PST mode
+    DPMInit(p);
+    mcSHOW_DBG_MSG(("DPM_CONTROL_AFTERK: ON\n"));
+#endif
+
+#if ENABLE_PER_BANK_REFRESH
+    #if IMP_TRACKING_PB_TO_AB_REFRESH_WA
+    // enable pb-ref for current shu
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF0, 0x1, SHU_CONF0_PBREFEN);
+    #endif
+    mcSHOW_DBG_MSG(("PER_BANK_REFRESH: ON\n"));
+#else
+    mcSHOW_DBG_MSG(("PER_BANK_REFRESH: OFF\n"));
+#endif
+
+///TODO:KIWI
+#if __A60868_TO_BE_PORTING__
+
+#if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION
+    if (vGet_DDR800_Mode(p) == DDR800_SEMI_LOOP)
+    {
+        EnableDllCg(p, ENABLE); //open CG to save power
+    }
+#endif
+
+#endif //__A60868_TO_BE_PORTING__
+
+#if REFRESH_OVERHEAD_REDUCTION
+    vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0x1, REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA);
+    mcSHOW_DBG_MSG(("REFRESH_OVERHEAD_REDUCTION: ON\n"));
+#else
+    mcSHOW_DBG_MSG(("REFRESH_OVERHEAD_REDUCTION: OFF\n"));
+#endif
+
+#if XRTWTW_NEW_CROSS_RK_MODE
+    if (p->support_rank_num == RANK_DUAL)
+    {
+        //ENABLE_XRTWTW_Setting(p); // @Darren, DV codes is included
+        mcSHOW_DBG_MSG(("XRTWTW_NEW_MODE: ON\n"));
+    }
+#else
+    mcSHOW_DBG_MSG(("XRTWTW_NEW_MODE: OFF\n"));
+#endif
+
+#if XRTRTR_NEW_CROSS_RK_MODE
+    if (p->support_rank_num == RANK_DUAL)
+    {
+        //ENABLE_XRTRTR_Setting(p); // @Darren, DV codes is included
+        mcSHOW_DBG_MSG(("XRTRTR_NEW_MODE: ON\n"));
+    }
+#else
+    mcSHOW_DBG_MSG(("XRTRTR_NEW_MODE: OFF\n"));
+#endif
+
+#if ENABLE_TX_TRACKING
+    mcSHOW_DBG_MSG(("TX_TRACKING: ON\n"));
+#else
+    mcSHOW_DBG_MSG(("TX_TRACKING: OFF\n"));
+#endif
+
+#if RDSEL_TRACKING_EN
+    mcSHOW_DBG_MSG(("RDSEL_TRACKING: ON\n"));
+#else
+    mcSHOW_DBG_MSG(("RDSEL_TRACKING: OFF\n"));
+#endif
+
+#if TDQSCK_PRECALCULATION_FOR_DVFS
+    mcSHOW_DBG_MSG(("DQS Precalculation for DVFS: "));
+    /* Maoauo: Enable DQS precalculation for LP4, disable for LP3(same as Kibo) */
+    DramcDQSPrecalculation_enable(p);
+    mcSHOW_DBG_MSG(("ON\n"));
+#else
+    mcSHOW_DBG_MSG(("DQS Precalculation for DVFS: OFF\n"));
+#endif
+
+#if ENABLE_RX_TRACKING
+    DramcRxInputDelayTrackingInit_Common(p);
+    DramcRxInputDelayTrackingHW(p);
+    mcSHOW_DBG_MSG(("RX_TRACKING: ON\n"));
+#else
+    mcSHOW_DBG_MSG(("RX_TRACKING: OFF\n"));
+#endif
+
+#if (ENABLE_RX_TRACKING && RX_DLY_TRACK_ONLY_FOR_DEBUG && defined(DUMMY_READ_FOR_TRACKING))
+    mcSHOW_DBG_MSG(("RX_DLY_TRACK_DBG: ON\n"));
+    DramcRxDlyTrackDebug(p);
+#endif
+
+/* HW gating - Disabled by default(in preloader) to save power (DE: HJ Huang) */
+#if (defined(HW_GATING))
+    mcSHOW_DBG_MSG(("HW_GATING DBG: ON\n"));
+    DramcHWGatingDebugOnOff(p, ENABLE);
+#else
+    mcSHOW_DBG_MSG(("HW_GATING DBG: OFF\n"));
+    DramcHWGatingDebugOnOff(p, DISABLE);
+#endif
+
+#ifdef ZQCS_ENABLE_LP4
+    // if CHA.ZQCSMASK=1, and then set CHA.ZQCALDISB=1 first, else set CHB.ZQCALDISB=1 first
+#if (fcFOR_CHIP_ID == fcPetrus)
+    vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_A << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB);
+    vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_D << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB);
+
+    mcDELAY_US(1);
+
+    vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_B << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB);
+    vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_C << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB);
+#elif (fcFOR_CHIP_ID == fc8195)
+    vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_A << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB);
+    vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_C << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB);
+
+    mcDELAY_US(1);
+
+    vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_B << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB);
+    vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_D << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB);
+#endif
+    mcSHOW_DBG_MSG(("ZQCS_ENABLE_LP4: ON\n"));
+#else
+    vIO32WriteFldAlign_All(DRAMC_REG_ZQ_SET1, 0, ZQ_SET1_ZQCALDISB);// LP3 and LP4 are different, be careful.
+    mcSHOW_DBG_MSG(("ZQCS_ENABLE_LP4: OFF\n"));
+    #if (!__ETT__) && ENABLE_LP4Y_DFS // for preloader
+    #error RTMRW DFS must support the SWZQ at DPM!!!
+    #endif
+#endif
+
+///TODO:JEREMY
+#if 0
+#ifdef DUMMY_READ_FOR_DQS_GATING_RETRY
+    DummyReadForDqsGatingRetryNonShuffle(p, 1);
+    mcSHOW_DBG_MSG(("DUMMY_READ_FOR_DQS_GATING_RETRY: ON\n"));
+#else
+    DummyReadForDqsGatingRetryNonShuffle(p, 0);
+    mcSHOW_DBG_MSG(("DUMMY_READ_FOR_DQS_GATING_RETRY: OFF\n"));
+#endif
+#endif
+
+#if RX_PICG_NEW_MODE
+    mcSHOW_DBG_MSG(("RX_PICG_NEW_MODE: ON\n"));
+#else
+    mcSHOW_DBG_MSG(("RX_PICG_NEW_MODE: OFF\n"));
+#endif
+
+#if TX_PICG_NEW_MODE
+    TXPICGNewModeEnable(p);
+    mcSHOW_DBG_MSG(("TX_PICG_NEW_MODE: ON\n"));
+#else
+    mcSHOW_DBG_MSG(("TX_PICG_NEW_MODE: OFF\n"));
+#endif
+
+#if ENABLE_LP4Y_DFS
+    mcSHOW_DBG_MSG(("ENABLE_LP4Y_DFS: ON\n"));
+#else
+    mcSHOW_DBG_MSG(("ENABLE_LP4Y_DFS: OFF\n"));
+#endif
+
+#if (SW_CHANGE_FOR_SIMULATION == 0)
+#if APPLY_LOWPOWER_GOLDEN_SETTINGS
+    int enable_dcm = (doe_get_config("dramc_dcm"))? 0: 1;
+    //const char *str = (enable_dcm == 1)? ("ON") : ("OFF");
+//    EnableDramcPhyDCM(p, enable_dcm);
+    EnableDramcPhyDCMNonShuffle(p, enable_dcm);
+    //mcSHOW_DBG_MSG(("LOWPOWER_GOLDEN_SETTINGS(DCM): %s\n", str));
+
+    if(enable_dcm == 0)
+    {
+        //S0_DCMOffWA(p);//For S0 + DCM off
+    }
+
+#else
+//    EnableDramcPhyDCM(p, DCM_OFF);
+    EnableDramcPhyDCMNonShuffle(p, 0);
+    mcSHOW_DBG_MSG(("LOWPOWER_GOLDEN_SETTINGS(DCM): OFF\n"));
+
+    //S0_DCMOffWA(p);//For S0 + DCM off
+#endif
+#endif
+
+//DumpShuRG(p);
+
+
+
+#if 1
+    DramcShuTrackingDcmSeEnBySRAM(p);
+#endif
+
+
+//Dummy read should NOT be enabled before gating tracking
+#ifdef DUMMY_READ_FOR_TRACKING
+    DramcDummyReadForTrackingEnable(p);
+#else
+    mcSHOW_DBG_MSG(("DUMMY_READ_FOR_TRACKING: OFF\n"));
+#endif
+
+
+#ifdef SPM_CONTROL_AFTERK
+    DVFS_PRE_config(p);
+    TransferToSPMControl(p);
+    mcSHOW_DBG_MSG(("SPM_CONTROL_AFTERK: ON\n"));
+#else
+    mcSHOW_DBG_MSG(("!!! SPM_CONTROL_AFTERK: OFF\n"));
+    mcSHOW_DBG_MSG(("!!! SPM could not control APHY\n"));
+#endif
+
+// when time profiling multi times, SW impedance tracking will fail when trakcing enable.
+// ignor SW impedance tracking when doing time profling
+#ifndef DDR_INIT_TIME_PROFILING
+#ifdef IMPEDANCE_TRACKING_ENABLE
+    if (p->dram_type == TYPE_LPDDR4 || p->dram_type == TYPE_LPDDR4X)
+    {
+        DramcImpedanceTrackingEnable(p);
+        mcSHOW_DBG_MSG(("IMPEDANCE_TRACKING: ON\n"));
+
+#ifdef IMPEDANCE_HW_SAVING
+        DramcImpedanceHWSaving(p);
+#endif
+    }
+#else
+    mcSHOW_DBG_MSG(("IMPEDANCE_TRACKING: OFF\n"));
+#endif
+#endif
+
+    //0x1c0[31]
+    //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSCAL0), 0, DQSCAL0_STBCALEN);
+
+#ifdef TEMP_SENSOR_ENABLE
+    SwitchHMR4(p, ON);
+    mcSHOW_DBG_MSG(("TEMP_SENSOR: ON\n"));
+#else
+    SwitchHMR4(p, OFF);
+    mcSHOW_DBG_MSG(("TEMP_SENSOR: OFF\n"));
+#endif
+
+    HwSaveForSR(p);
+
+    ClkFreeRunForDramcPsel(p);
+
+#if ENABLE_RODT_TRACKING
+    mcSHOW_DBG_MSG(("Read ODT Tracking: ON\n"));
+#else
+    mcSHOW_DBG_MSG(("Read ODT Tracking: OFF\n"));
+#endif
+
+#if ENABLE_REFRESH_RATE_DEBOUNCE
+    mcSHOW_DBG_MSG(("Refresh Rate DeBounce: ON\n"));
+    DramcRefreshRateDeBounceEnable(p);
+#endif
+
+#if ENABLE_DVFS_BYPASS_MR13_FSP
+    DFSBypassMR13HwSet(p);
+#endif
+
+#if (CHECK_GOLDEN_SETTING == TRUE)
+    DRAM_STATUS_T stResult = CheckGoldenSetting(p);
+    mcSHOW_DBG_MSG(("End of run time ==>Golden setting check: %s\n", (stResult == DRAM_OK)? ("OK") : ("NG")));
+#endif
+
+#if DFS_NOQUEUE_FLUSH_ENABLE
+    EnableDFSNoQueueFlush(p);
+    mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH: ON\n"));
+#else
+    mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH: OFF\n"));
+#endif
+
+#if DFS_NOQUEUE_FLUSH_LATENCY_CNT
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_FSM_CFG, 1, LPIF_FSM_CFG_DBG_LATENCY_CNT_EN);
+    // DPM clock is 208M
+    vIO32WriteFldMulti_All(DDRPHY_MD32_REG_SSPM_MCLK_DIV, P_Fld(0, SSPM_MCLK_DIV_MCLK_SRC)
+        | P_Fld(0, SSPM_MCLK_DIV_MCLK_DIV));
+    mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH_LATENCY_CNT: ON\n"));
+#else
+    mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF\n"));
+#endif
+
+#if ENABLE_DFS_RUNTIME_MRW
+    #if (REPLACE_DFS_RG_MODE==0)
+    DFSRuntimeFspMRW(p);
+    #endif
+    mcSHOW_DBG_MSG(("ENABLE_DFS_RUNTIME_MRW: ON\n"));
+#else
+    mcSHOW_DBG_MSG(("ENABLE_DFS_RUNTIME_MRW: OFF\n"));
+#endif
+
+    //CheckRxPICGNewModeSetting(p);
+    vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0x0, REFCTRL0_REFDIS); //After k, auto refresh should be enable
+
+#if DDR_RESERVE_NEW_MODE
+    mcSHOW_DBG_MSG(("DDR_RESERVE_NEW_MODE: ON\n"));
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DDR_RESERVE, P_Fld(1, MISC_DDR_RESERVE_WDT_LITE_EN) | P_Fld(0, MISC_DDR_RESERVE_WDT_SM_CLR));
+#else
+    mcSHOW_DBG_MSG(("DDR_RESERVE_NEW_MODE: OFF\n"));
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DDR_RESERVE, P_Fld(0, MISC_DDR_RESERVE_WDT_LITE_EN) | P_Fld(1, MISC_DDR_RESERVE_WDT_SM_CLR));
+#endif
+
+#if MR_CBT_SWITCH_FREQ
+    mcSHOW_DBG_MSG(("MR_CBT_SWITCH_FREQ: ON\n"));
+#else
+    mcSHOW_DBG_MSG(("MR_CBT_SWITCH_FREQ: OFF\n"));
+#endif
+
+#if OPEN_LOOP_MODE_CLK_TOGGLE_WA
+    if(vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE)
+    {
+        mcSHOW_DBG_MSG(("OPEN_LOOP_MODE_CLK_TOGGLE_WA: ON\n"));
+        ToggleOpenLoopModeClk(p);
+    }
+#endif
+
+    mcSHOW_DBG_MSG(("=========================\n"));
+}
+
+#if 0  //no use?
+void DramcTest_DualSch_stress(DRAMC_CTX_T *p)
+{
+    U32 count = 0;
+    U16 u2Value = 0;
+
+#if MRW_CHECK_ONLY
+    mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+#endif
+
+    //vIO32WriteFldAlign_All(DRAMC_REG_PERFCTL0, 1, PERFCTL0_DUALSCHEN);
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_SCHEDULER, 1, SHU_SCHEDULER_DUALSCHEN);
+
+    while (count < 10)
+    {
+        count++;
+
+        u1MR12Value[p->channel][p->rank][p->dram_fsp] = 0x14;
+        DramcModeRegWriteByRank(p, p->rank, 12, u1MR12Value[p->channel][p->rank][p->dram_fsp]);
+        DramcModeRegReadByRank(p, p->rank, 12, &u2Value);
+        //mcSHOW_DBG_MSG(("MR12 = 0x%0X\n", u1Value));
+    }
+}
+#endif
+
+#if (ENABLE_TX_TRACKING && TX_RETRY_ENABLE)
+void SPMTx_Track_Retry_OnOff(DRAMC_CTX_T *p, U8 shu_level, U8 onoff)
+{
+    static U8 gIsddr800TxRetry = 0;
+
+    // MCK still available for DRAMC RG access from Joe comment
+    if (shu_level == SRAM_SHU6)
+    {
+        gIsddr800TxRetry = 1;
+    }
+
+    //Need to do tx retry when DDR800 -> DDr1200
+    if ((gIsddr800TxRetry == 1) && (shu_level != SRAM_SHU6)
+#if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
+        && (shu_level != SRAM_SHU7))
+#else
+        )
+#endif
+    {
+        if (onoff == ENABLE)
+        {
+            mcSHOW_DBG_MSG2(("TX track retry: ENABLE! (DDR800 to DDR1200)\n"));
+            vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 1, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK);
+            mcDELAY_US(1);
+            #if TX_RETRY_CONTROL_BY_SPM
+            vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_TX_TRACKING_RETRY_EN);
+            #else //control by DRAMC
+            vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 1, TX_RETRY_SET0_XSR_TX_RETRY_EN);
+            #endif
+        }
+        else //DISABLE
+        {
+            mcSHOW_DBG_MSG2(("TX track retry: DISABLE! (DDR800 to DDR1200)\n"));
+            #if TX_RETRY_CONTROL_BY_SPM
+            vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_TX_TRACKING_RETRY_EN);
+            #else //control by DRAMC
+            vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 0, TX_RETRY_SET0_XSR_TX_RETRY_EN);
+            #endif
+            mcDELAY_US(1); //add 1us delay to wait emi and tx retry be done (because PPR_CTRL_TX_RETRY_SHU_RESP_OPT=1)
+            vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 0, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK); //enable block emi to let tx retry be finish
+            gIsddr800TxRetry = 0;
+        }
+    }
+}
+
+#if SW_TX_RETRY_ENABLE
+#define SW_TX_RETRY_ENABLE_WA 1 //To recieve response by disable CG
+void SWTx_Track_Retry_OnOff(DRAMC_CTX_T *p)
+{
+    U8 u4Response;
+    U8 u1RegBackup_DQSOSCENDIS;
+    U8 u1Shu_backup=p->ShuRGAccessIdx;
+    #if SW_TX_RETRY_ENABLE_WA
+    U8 u1RegBackup;
+
+    u1RegBackup=u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DCM_SUB_CTRL), DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DCM_SUB_CTRL), 0, DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING);
+    #endif
+    p->ShuRGAccessIdx = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_10,LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL)& 0x1;
+    u1RegBackup_DQSOSCENDIS = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0),SHU_DQSOSC_SET0_DQSOSCENDIS);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), 1, SHU_DQSOSC_SET0_DQSOSCENDIS);
+    mcSHOW_DBG_MSG2(("SW TX track retry!\n"));
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 0, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 1, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 1, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN);
+    do
+    {
+        u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_TX_RETRY_DONE_RESPONSE);
+        mcDELAY_US(1);  // Wait tZQCAL(min) 1us or wait next polling
+        mcSHOW_DBG_MSG4(("still wait tx retry be done\n", u4Response));
+    }while (u4Response == 0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 0, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 0, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), u1RegBackup_DQSOSCENDIS, SHU_DQSOSC_SET0_DQSOSCENDIS);
+    #if SW_TX_RETRY_ENABLE_WA
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DCM_SUB_CTRL), u1RegBackup, DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING);
+    #endif
+    p->ShuRGAccessIdx=u1Shu_backup;
+}
+#endif
+#endif
+
+// The "ENABLE_RANK_NUMBER_AUTO_DETECTION" use this API
+void DFSInitForCalibration(DRAMC_CTX_T *p)
+{
+#ifdef DDR_INIT_TIME_PROFILING
+    U32 CPU_Cycle;
+    mcSHOW_TIME_MSG(("*** Data rate %d ***\n\n", p->frequency << 1));
+
+    TimeProfileBegin();
+#endif
+
+    u1PrintModeRegWrite = 1;
+
+#if MRW_BACKUP
+    U8 u1RKIdx;
+
+    for(u1RKIdx=0; u1RKIdx<p->support_rank_num; u1RKIdx++)
+    {
+        gFSPWR_Flag[u1RKIdx]=p->dram_fsp;
+    }
+#endif
+
+    DramcInit(p);
+    u1PrintModeRegWrite = 0;
+    vBeforeCalibration(p);
+
+#ifdef DUMP_INIT_RG_LOG_TO_DE
+    while (1);
+#endif
+
+#ifdef DDR_INIT_TIME_PROFILING
+    CPU_Cycle = TimeProfileEnd();
+    mcSHOW_TIME_MSG(("  DFSInitForCalibration() take %d ms\n\n", CPU_Cycle / 1000));
+#endif
+
+#ifndef DUMP_INIT_RG_LOG_TO_DE
+    #ifdef ENABLE_MIOCK_JMETER
+    if ((Get_MDL_Used_Flag()==NORMAL_USED) && (p->frequency >= 800))
+    {
+        Get_RX_DelayCell(p);
+    }
+    #endif
+#endif
+
+#ifdef DDR_INIT_TIME_PROFILING
+    TimeProfileBegin();
+#endif
+
+#ifndef DUMP_INIT_RG_LOG_TO_DE
+    #ifdef ENABLE_MIOCK_JMETER
+    if (Get_MDL_Used_Flag()==NORMAL_USED)
+    {
+        p->u2DelayCellTimex100 = GetVcoreDelayCellTime(p);
+    }
+    #endif
+#endif
+
+#ifdef DDR_INIT_TIME_PROFILING
+    CPU_Cycle=TimeProfileEnd();
+    mcSHOW_TIME_MSG(("  (3) JMeter takes %d ms\n\r", CPU_Cycle / 1000));
+#endif
+}
+
+#if 0 /* cc mark to use DV initial setting */
+void DramcHWDQSGatingTracking_ModeSetting(DRAMC_CTX_T *p)
+{
+#ifdef HW_GATING
+#if DramcHWDQSGatingTracking_FIFO_MODE
+    //REFUICHG=0, STB_SHIFT_DTCOUT_IG=0, DQSG_MODE=1, NARROW_IG=0
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL),
+        P_Fld(1, MISC_STBCAL_STB_DQIEN_IG) |
+        P_Fld(1, MISC_STBCAL_PICHGBLOCK_NORD) |
+        P_Fld(0, MISC_STBCAL_REFUICHG) |
+        P_Fld(0, MISC_STBCAL_PHYVALID_IG) |
+        P_Fld(0, MISC_STBCAL_STBSTATE_OPT) |
+        P_Fld(0, MISC_STBCAL_STBDLELAST_FILTER) |
+        P_Fld(0, MISC_STBCAL_STBDLELAST_PULSE) |
+        P_Fld(0, MISC_STBCAL_STBDLELAST_OPT) |
+        P_Fld(1, MISC_STBCAL_PIMASK_RKCHG_OPT));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1),
+        P_Fld(1, MISC_STBCAL1_STBCAL_FILTER) |
+        //cc mark P_Fld(1, MISC_STBCAL1_STB_FLAGCLR) |
+        P_Fld(1, MISC_STBCAL1_STB_SHIFT_DTCOUT_IG));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0),
+        P_Fld(1, MISC_CTRL0_R_DMDQSIEN_FIFO_EN) |
+        P_Fld(0, MISC_CTRL0_R_DMVALID_DLY) |
+        P_Fld(0, MISC_CTRL0_R_DMVALID_DLY_OPT) |
+        P_Fld(0, MISC_CTRL0_R_DMVALID_NARROW_IG));
+        //cc mark P_Fld(0, MISC_CTRL0_R_DMDQSIEN_SYNCOPT));
+
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6),
+        0, B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0);
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6),
+        0, B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1);
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6),
+        0, CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL);
+
+#else
+    //REFUICHG=0, STB_SHIFT_DTCOUT_IG=0, DQSG_MODE=1, NARROW_IG=0
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL),
+        P_Fld(1, MISC_STBCAL_STB_DQIEN_IG) |
+        P_Fld(1, MISC_STBCAL_PICHGBLOCK_NORD) |
+        P_Fld(0, MISC_STBCAL_REFUICHG) |
+        P_Fld(0, MISC_STBCAL_PHYVALID_IG) |
+        P_Fld(0, MISC_STBCAL_STBSTATE_OPT) |
+        P_Fld(0, MISC_STBCAL_STBDLELAST_FILTER) |
+        P_Fld(0, MISC_STBCAL_STBDLELAST_PULSE) |
+        P_Fld(0, MISC_STBCAL_STBDLELAST_OPT) |
+        P_Fld(1, MISC_STBCAL_PIMASK_RKCHG_OPT));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1),
+        P_Fld(1, MISC_STBCAL1_STBCAL_FILTER) |
+        //cc mark P_Fld(1, MISC_STBCAL1_STB_FLAGCLR) |
+        P_Fld(0, MISC_STBCAL1_STB_SHIFT_DTCOUT_IG));
+
+
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0),
+        P_Fld(0, MISC_CTRL0_R_DMDQSIEN_FIFO_EN) |
+        P_Fld(3, MISC_CTRL0_R_DMVALID_DLY) |
+        P_Fld(1, MISC_CTRL0_R_DMVALID_DLY_OPT) |
+        P_Fld(0, MISC_CTRL0_R_DMVALID_NARROW_IG));
+        //cc mark P_Fld(0xf, MISC_CTRL0_R_DMDQSIEN_SYNCOPT));
+
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6),
+        1, B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0);
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6),
+        1, B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1);
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6),
+        1, CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL);
+#endif
+#endif
+}
+#endif
+
+#if TX_PICG_NEW_MODE
+#if 0
+void GetTXPICGSetting(DRAMC_CTX_T * p)
+{
+    U32 u4DQS_OEN_final, u4DQ_OEN_final;
+    U16 u2DQS_OEN_2T[2], u2DQS_OEN_05T[2], u2DQS_OEN_Delay[2];
+    U16 u2DQ_OEN_2T[2], u2DQ_OEN_05T[2], u2DQ_OEN_Delay[2];
+    U16 u2COMB_TX_SEL[2];
+    U16 u2Shift_Div[2];
+    U16 u2COMB_TX_PICG_CNT;
+    U8 u1CHIdx, u1RankIdx, u1Rank_bak = u1GetRank(p), u1backup_CH = vGetPHY2ChannelMapping(p), u1Div_ratio;
+
+    mcSHOW_DBG_MSG(("****** GetTXPICGSetting DDR[%d] @@@\n", p->frequency * 2));
+
+    for (u1CHIdx = 0; u1CHIdx < p->support_channel_num; u1CHIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1CHIdx);
+        //Set TX DQS PICG
+        //DQS0
+        u2DQS_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS0);//m
+        u2DQS_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS0);//n
+        //DQS1
+        u2DQS_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS1);//m
+        u2DQS_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS1);//n
+
+        mcSHOW_DBG_MSG(("CH%d\n", u1CHIdx));
+        mcSHOW_DBG_MSG(("DQS0 m=%d n=%d \n", u2DQS_OEN_2T[0], u2DQS_OEN_05T[0]));
+        mcSHOW_DBG_MSG(("DQS1 m=%d n=%d \n", u2DQS_OEN_2T[1], u2DQS_OEN_05T[1]));
+
+
+
+        u2COMB_TX_SEL[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_APHY_TX_PICG_CTRL), SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0);
+        u2COMB_TX_SEL[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_APHY_TX_PICG_CTRL), SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1);
+        u2COMB_TX_PICG_CNT = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_APHY_TX_PICG_CTRL), SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT);
+
+        mcSHOW_DBG_MSG(("TX_DQS_SEL_P0 %d \n", u2COMB_TX_SEL[0]));
+        mcSHOW_DBG_MSG(("TX_DQS_SEL_P1 %d \n", u2COMB_TX_SEL[1]));
+        mcSHOW_DBG_MSG(("COMB_TX_PICG_CNT %d \n", u2COMB_TX_PICG_CNT));
+
+        //Set TX RK0 and RK1 DQ PICG
+        for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+        {
+            mcSHOW_DBG_MSG(("Rank%d\n", u1RankIdx));
+
+            vSetRank(p, u1RankIdx);
+            //DQ0
+            u2DQ_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ0);//p
+            u2DQ_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ0);//q
+            //DQ1
+            u2DQ_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ1);//p
+            u2DQ_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ1);//q
+
+            mcSHOW_DBG_MSG(("DQ0 p=%d q=%d \n", u2DQ_OEN_2T[0], u2DQ_OEN_05T[0]));
+            mcSHOW_DBG_MSG(("DQ1 p=%d q=%d \n", u2DQ_OEN_2T[1], u2DQ_OEN_05T[1]));
+
+            u2COMB_TX_SEL[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0);
+            u2COMB_TX_SEL[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1);
+
+            mcSHOW_DBG_MSG(("TX_DQ_RK_SEL_P0 %d \n", u2COMB_TX_SEL[0]));
+            mcSHOW_DBG_MSG(("TX_DQ_RK_SEL_P1 %d \n", u2COMB_TX_SEL[1]));
+        }
+        vSetRank(p, u1Rank_bak);
+    }
+    vSetPHY2ChannelMapping(p, u1backup_CH);
+}
+#endif
+
+#define ADD_1UI_TO_APHY 1 //After A60-868/Pe-trus
+void TXPICGSetting(DRAMC_CTX_T * p)
+{
+    U32 u4DQS_OEN_final, u4DQ_OEN_final;
+    U16 u2DQS_OEN_2T[2], u2DQS_OEN_05T[2], u2DQS_OEN_Delay[2];
+    U16 u2DQ_OEN_2T[2], u2DQ_OEN_05T[2], u2DQ_OEN_Delay[2];
+    U16 u2COMB_TX_SEL[2];
+    U16 u2Shift_DQS_Div[2];
+    U16 u2Shift_DQ_Div[2];
+    U16 u2COMB_TX_PICG_CNT;
+    U8 u1CHIdx, u1RankIdx, u1Rank_bak = u1GetRank(p), u1backup_CH = vGetPHY2ChannelMapping(p), u1Div_ratio;
+
+    u2COMB_TX_PICG_CNT = 3;//After Pe-trus, could detect HW OE=1 -> 0 automatically, and prolong TX picg
+    if (vGet_Div_Mode(p) == DIV8_MODE)
+    {
+        u2Shift_DQS_Div[0] = 10;//phase 0
+        u2Shift_DQS_Div[1] = 6;//phase 1
+        u2Shift_DQ_Div[0] = 8;//phase 0
+        u2Shift_DQ_Div[1] = 4;//phase 1
+        u1Div_ratio = 3;
+    }
+    else //DIV4_MODE
+    {
+        u2Shift_DQS_Div[0] = 2;//phase 0
+        u2Shift_DQS_Div[1] = 0;//phase 1, no use
+        u2Shift_DQ_Div[0] = 0;//phase 0
+        u2Shift_DQ_Div[1] = 0;//phase 1, no use
+        u1Div_ratio = 2;
+    }
+
+    for (u1CHIdx = 0; u1CHIdx < p->support_channel_num; u1CHIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1CHIdx);
+        //Set TX DQS PICG
+        //DQS0
+        u2DQS_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS0);//m
+        u2DQS_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS0);//n
+        u2DQS_OEN_Delay[0] = (u2DQS_OEN_2T[0] << u1Div_ratio) + u2DQS_OEN_05T[0];
+        //DQS1
+        u2DQS_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS1);//m
+        u2DQS_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS1);//n
+        u2DQS_OEN_Delay[1] = (u2DQS_OEN_2T[1] << u1Div_ratio) + u2DQS_OEN_05T[1];
+
+        u4DQS_OEN_final = (u2DQS_OEN_Delay[0] > u2DQS_OEN_Delay[1])? u2DQS_OEN_Delay[1]: u2DQS_OEN_Delay[0]; //choose minimum value
+        u4DQS_OEN_final += ADD_1UI_TO_APHY;
+
+
+        u2COMB_TX_SEL[0] = (u4DQS_OEN_final > u2Shift_DQS_Div[0])? ((u4DQS_OEN_final - u2Shift_DQS_Div[0]) >> u1Div_ratio): 0;
+
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+            u2COMB_TX_SEL[1] = 0;
+        else
+            u2COMB_TX_SEL[1] = (u4DQS_OEN_final > u2Shift_DQS_Div[1])? ((u4DQS_OEN_final - u2Shift_DQS_Div[1]) >> u1Div_ratio): 0;
+
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_APHY_TX_PICG_CTRL), P_Fld(u2COMB_TX_SEL[0], SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0)
+                                             | P_Fld(u2COMB_TX_SEL[1], SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1)
+                                             | P_Fld(u2COMB_TX_PICG_CNT, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT));
+        //Set TX RK0 and RK1 DQ PICG
+        for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+        {
+            vSetRank(p, u1RankIdx);
+            //DQ0
+            u2DQ_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ0);
+            u2DQ_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ0);
+            u2DQ_OEN_Delay[0] = (u2DQ_OEN_2T[0] << u1Div_ratio) + u2DQ_OEN_05T[0];
+            //DQ1
+            u2DQ_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ1);
+            u2DQ_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ1);
+            u2DQ_OEN_Delay[1] = (u2DQ_OEN_2T[1] << u1Div_ratio) + u2DQ_OEN_05T[1];
+
+
+            u4DQ_OEN_final = (u2DQ_OEN_Delay[0] > u2DQ_OEN_Delay[1])? u2DQ_OEN_Delay[1]: u2DQ_OEN_Delay[0]; //choose minimum value
+            u4DQ_OEN_final += ADD_1UI_TO_APHY;
+
+            u2COMB_TX_SEL[0] = (u4DQ_OEN_final > u2Shift_DQ_Div[0])? ((u4DQ_OEN_final - u2Shift_DQ_Div[0]) >> u1Div_ratio): 0;
+
+            if (vGet_Div_Mode(p) == DIV4_MODE)
+               u2COMB_TX_SEL[1] = 0;
+            else
+               u2COMB_TX_SEL[1] = (u4DQ_OEN_final > u2Shift_DQ_Div[1])? ((u4DQ_OEN_final - u2Shift_DQ_Div[1]) >> u1Div_ratio): 0;
+
+               vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), P_Fld(u2COMB_TX_SEL[0], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)
+                                                 | P_Fld(u2COMB_TX_SEL[1], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1));
+        }
+        vSetRank(p, u1Rank_bak);
+    }
+    vSetPHY2ChannelMapping(p, u1backup_CH);
+}
+#endif
+
+
+#if RX_PICG_NEW_MODE
+static void RXPICGSetting(DRAMC_CTX_T * p)
+{
+    DRAM_RANK_T bkRank = u1GetRank(p);
+    U8 u1RankIdx = 0;
+
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_STBCAL, 0, MISC_SHU_STBCAL_STBCALEN);
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_STBCAL, 0, MISC_SHU_STBCAL_STB_SELPHCALEN);
+
+    //PI_CG_DQSIEN new mode
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL1, 1, MISC_STBCAL1_STBCNT_SHU_RST_EN);
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN);
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_STBCAL, 1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE);
+
+    //APHY control new mode
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL, 1, MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT);
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL, 1, MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT);
+
+    //Dummy code (based on DVT document Verification plan of RX PICG efficiency improvment.docx)
+    //No need to set since HW setting or setting in other place
+    //Pls. don't remove for the integrity
+    {
+        U8 u1TAIL_LAT = (vGet_Div_Mode(p) == DIV4_MODE) ? 1: 0;
+        vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0, MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN);
+
+        for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)//Should set 2 rank
+        {
+            vSetRank(p, u1RankIdx);
+            vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL, P_Fld(u1TAIL_LAT, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT)
+                    | P_Fld(0, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT));
+        }
+        vSetRank(p, bkRank);
+
+        vIO32WriteFldMulti(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL, P_Fld(0, MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN)
+                    | P_Fld(0, MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN)
+                    | P_Fld(0, MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN));
+
+        vIO32WriteFldMulti(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL, P_Fld(0, MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN)
+                    | P_Fld(0, MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN)
+                    | P_Fld(0, MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN));
+
+    }
+#if 0
+        vIO32WriteFldAlign(DRAMC_REG_STBCAL2, 0, STBCAL2_STB_STBENRST_EARLY_1T_EN);
+        vIO32WriteFldMulti(DRAMC_REG_SHU_STBCAL, P_Fld(u1TAIL_LAT, SHU_STBCAL_R1_DQSIEN_PICG_TAIL_EXT_LAT)
+                    | P_Fld(0, SHU_STBCAL_R1_DQSIEN_PICG_HEAD_EXT_LAT)
+                    | P_Fld(u1TAIL_LAT, SHU_STBCAL_R0_DQSIEN_PICG_TAIL_EXT_LAT)
+                    | P_Fld(0, SHU_STBCAL_R0_DQSIEN_PICG_HEAD_EXT_LAT));
+        vIO32WriteFldMulti(DRAMC_REG_PHY_RX_INCTL, P_Fld(0, PHY_RX_INCTL_DIS_IN_BUFF_EN)
+                    | P_Fld(0, PHY_RX_INCTL_FIX_IN_BUFF_EN)
+                    | P_Fld(0, PHY_RX_INCTL_RX_IN_BUFF_EN_4BYTE_EN)
+                    | P_Fld(0, PHY_RX_INCTL_DIS_IN_GATE_EN)
+                    | P_Fld(0, PHY_RX_INCTL_FIX_IN_GATE_EN)
+                    | P_Fld(0, PHY_RX_INCTL_RX_IN_GATE_EN_4BYTE_EN));
+#endif
+}
+#endif
+
+#ifndef DPM_CONTROL_AFTERK
+void dramc_exit_with_DFS_legacy_mode(DRAMC_CTX_T * p)
+{
+#if !__ETT__
+    //set for SPM DRAM self refresh
+    vIO32WriteFldAlign(SPM_POWERON_CONFIG_EN, 1, POWERON_CONFIG_EN_BCLK_CG_EN);
+    vIO32WriteFldAlign(SPM_DRAMC_DPY_CLK_SW_CON_2, 1, SPM_DRAMC_DPY_CLK_SW_CON_2_SW_PHYPLL_MODE_SW);
+    vIO32WriteFldAlign(SPM_POWER_ON_VAL0, 1, SPM_POWER_ON_VAL0_SC_PHYPLL_MODE_SW);
+#endif
+    //Preloader exit with legacy mode for CTP load used
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0x0, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL);
+    vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0x0, PHYPLL0_RG_RPHYPLL_EN);
+    vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0x0, CLRPLL0_RG_RCLRPLL_EN);
+}
+#endif
+
+#if TX_PICG_NEW_MODE
+void TXPICGNewModeEnable(DRAMC_CTX_T * p)
+{
+    //Switch TX PICG to new mode
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL3, P_Fld(0, MISC_CTRL3_ARPI_CG_MCK_DQ_OPT)
+                                         | P_Fld(0, MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT)
+                                         | P_Fld(0, MISC_CTRL3_ARPI_CG_DQS_OPT)
+                                         | P_Fld(0, MISC_CTRL3_ARPI_CG_DQ_OPT));
+}
+#endif
+
+#if ENABLE_WRITE_DBI_Protect
+void ApplyWriteDBIProtect(DRAMC_CTX_T *p, U8 onoff)
+{
+#if __A60868_TO_BE_PORTING__
+    U8 *uiLPDDR_O1_Mapping;
+    U16 Temp_PinMux_MaskWrite_WriteDBIOn = 0;
+    U8 B0_PinMux_MaskWrite_WriteDBIOn = 0, B1_PinMux_MaskWrite_WriteDBIOn = 0;
+    int DQ_index;
+
+    uiLPDDR_O1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[p->channel];
+
+    // Write DMI/DBI Protect Function
+    // Byte0 can not have bit swap between Group1(DQ0/1) and Group2(DQ02~DQ07).
+    // Byte1 can not have bit swap between Group1(DQ8/9) and Group2(DQ10~DQ15).
+    // DBIWR_IMP_EN=1 and DBIWR_PINMUX_EN=1
+    // set DBIWR_OPTB0[7:0] meet with Byte0 pin MUX table.
+    // set DBIWR_OPTB1[7:0] meet with Byte1 pin MUX table.
+
+    for (DQ_index = 0; DQ_index < 16; DQ_index++)
+    {
+        Temp_PinMux_MaskWrite_WriteDBIOn |= ((0x7C7C >> uiLPDDR_O1_Mapping[DQ_index]) & 0x1) << DQ_index;
+    }
+    B1_PinMux_MaskWrite_WriteDBIOn = (U8)(Temp_PinMux_MaskWrite_WriteDBIOn >> 8) & 0xff;
+    B0_PinMux_MaskWrite_WriteDBIOn = (U8) Temp_PinMux_MaskWrite_WriteDBIOn & 0xff;
+
+    vIO32WriteFldMulti_All(DRAMC_REG_ARBCTL, P_Fld(B1_PinMux_MaskWrite_WriteDBIOn, ARBCTL_DBIWR_OPT_B1)
+                                           | P_Fld(B0_PinMux_MaskWrite_WriteDBIOn, ARBCTL_DBIWR_OPT_B0)
+                                           | P_Fld(onoff, ARBCTL_DBIWR_PINMUX_EN)
+                                           | P_Fld(onoff, ARBCTL_DBIWR_IMP_EN));
+#endif
+}
+#endif
+
+#if ENABLE_WRITE_DBI
+void ApplyWriteDBIPowerImprove(DRAMC_CTX_T *p, U8 onoff)
+{
+
+    // set DBIWR_IMP_EN = 1
+    // DBIWR_OPTB0[1:0]=0, DBIWR_OPT_B0[7]=0
+    // DBIWR_OPTB1[1:0]=0, DBIWR_OPT_B1[7]=0
+    vIO32WriteFldMulti_All(DRAMC_REG_DBIWR_PROTECT, P_Fld(0, DBIWR_PROTECT_DBIWR_OPT_B1)
+                                       | P_Fld(0, DBIWR_PROTECT_DBIWR_OPT_B0)
+                                       | P_Fld(0, DBIWR_PROTECT_DBIWR_PINMUX_EN)
+                                       | P_Fld(onoff, DBIWR_PROTECT_DBIWR_IMP_EN));
+}
+/* DDR800 mode struct declaration (declared here due Fld_wid for each register type) */
+/*
+typedef struct _DDR800Mode_T
+{
+    U8 dll_phdet_en_b0: Fld_wid(SHU_B0_DLL0_RG_ARDLL_PHDET_EN_B0_SHU);
+    U8 dll_phdet_en_b1: Fld_wid(SHU_B1_DLL0_RG_ARDLL_PHDET_EN_B1_SHU);
+    U8 dll_phdet_en_ca_cha: Fld_wid(SHU_CA_DLL0_RG_ARDLL_PHDET_EN_CA_SHU);
+    U8 dll_phdet_en_ca_chb: Fld_wid(SHU_CA_DLL0_RG_ARDLL_PHDET_EN_CA_SHU);
+    U8 phypll_ada_mck8x_en: Fld_wid(SHU_PLL22_RG_RPHYPLL_ADA_MCK8X_EN_SHU);
+    U8 ddr400_en_b0: Fld_wid(SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0);
+    U8 ddr400_en_b1: Fld_wid(SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1);
+    U8 ddr400_en_ca: Fld_wid(SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA);
+    U8 phypll_ddr400_en: Fld_wid(SHU_PLL1_RG_RPHYPLL_DDR400_EN);
+    U8 ddr400_dqs_ps_b0: Fld_wid(SHU_B0_DQ9_RG_DDR400_DQS_PS_B0);
+    U8 ddr400_dqs_ps_b1: Fld_wid(SHU_B1_DQ9_RG_DDR400_DQS_PS_B1);
+    U8 ddr400_dq_ps_b0: Fld_wid(SHU_B0_DQ9_RG_DDR400_DQ_PS_B0);
+    U8 ddr400_dq_ps_b1: Fld_wid(SHU_B1_DQ9_RG_DDR400_DQ_PS_B1);
+    U8 ddr400_dqs_ps_ca: Fld_wid(SHU_CA_CMD9_RG_DDR400_DQS_PS_CA);
+    U8 ddr400_dq_ps_ca: Fld_wid(SHU_CA_CMD9_RG_DDR400_DQ_PS_CA);
+    U8 ddr400_semi_en_b0: Fld_wid(SHU_B0_DQ9_RG_DDR400_SEMI_EN_B0);
+    U8 ddr400_semi_en_b1: Fld_wid(SHU_B1_DQ9_RG_DDR400_SEMI_EN_B1);
+    U8 ddr400_semi_en_ca: Fld_wid(SHU_CA_CMD9_RG_DDR400_SEMI_EN_CA);
+    U8 ddr400_semi_open_en: Fld_wid(SHU_PLL0_RG_DDR400_SEMI_OPEN_EN);
+    U8 pll0_ada_mck8x_chb_en: Fld_wid(SHU_PLL0_ADA_MCK8X_CHB_EN);
+    U8 pll0_ada_mck8x_cha_en: Fld_wid(SHU_PLL0_ADA_MCK8X_CHA_EN);
+} DDR800Mode_T;
+*/
+#endif
+
+
+static void RODTSettings(DRAMC_CTX_T *p)
+{
+    U8 u1VrefSel;
+    U8 u1RankIdx, u1RankIdxBak;
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    //VREF_EN
+    vIO32WriteFldAlign(DDRPHY_REG_B0_DQ5, 1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0);
+    vIO32WriteFldAlign(DDRPHY_REG_B1_DQ5, !isLP4_DSC, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1);
+    vIO32WriteFldAlign(DDRPHY_REG_CA_CMD5, isLP4_DSC, CA_CMD5_RG_RX_ARCMD_VREF_EN);
+
+    //Update related setting of APHY RX and ODT
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_VREF, !(p->odt_onoff), SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0);
+    if (!isLP4_DSC)
+        vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_VREF, !(p->odt_onoff), SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1);
+    else
+        vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_VREF, !(p->odt_onoff), SHU_CA_VREF_RG_RX_ARCA_VREF_UNTERM_EN_CA);
+
+    if(p->odt_onoff==ODT_ON)
+    {
+        #if __LP5_COMBO__
+        if (p->dram_type==TYPE_LPDDR5)
+            u1VrefSel = 0x46;//term LP5
+        else
+        #endif
+            u1VrefSel = 0x2c;//term LP4
+    }
+    else
+    {
+        #if __LP5_COMBO__
+        if (p->dram_type==TYPE_LPDDR5)
+            u1VrefSel = 0x37;//unterm LP5
+        else
+        #endif
+            u1VrefSel = 0x37;//unterm LP4
+    }
+
+    u1RankIdxBak = u1GetRank(p);
+    for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+        vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_PHY_VREF_SEL,
+                    P_Fld(u1VrefSel, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0) |
+                    P_Fld(u1VrefSel, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0));
+        if (!isLP4_DSC){
+            vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_PHY_VREF_SEL,
+                        P_Fld(u1VrefSel, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1) |
+                        P_Fld(u1VrefSel, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B1));
+        }
+        else
+        {
+            vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_PHY_VREF_SEL,
+                        P_Fld(u1VrefSel, SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_LB) |
+                        P_Fld(u1VrefSel, SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_UB));
+        }
+    }
+    vSetRank(p, u1RankIdxBak);
+
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_VREF, 1, SHU_B0_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B0);
+    if (!isLP4_DSC)
+        vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_VREF, 1, SHU_B1_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B1);
+    else
+        vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_VREF, 1, SHU_CA_VREF_RG_RX_ARCA_VREF_RANK_SEL_EN_CA);
+
+#if ENABLE_TX_WDQS
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_ODTCTRL, 1, MISC_SHU_ODTCTRL_RODTEN);
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ7, 1, SHU_B0_DQ7_R_DMRODTEN_B0);
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ7, !isLP4_DSC, SHU_B1_DQ7_R_DMRODTEN_B1);
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD7, isLP4_DSC, SHU_CA_CMD7_R_DMRODTEN_CA);
+#else
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_ODTCTRL, p->odt_onoff, MISC_SHU_ODTCTRL_RODTEN);
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ7, p->odt_onoff, SHU_B0_DQ7_R_DMRODTEN_B0);
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ7, (p->odt_onoff & !isLP4_DSC), SHU_B1_DQ7_R_DMRODTEN_B1);
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD7, (p->odt_onoff & isLP4_DSC), SHU_CA_CMD7_R_DMRODTEN_CA);
+#endif
+
+#if ENABLE_RODT_TRACKING
+    //RODT tracking
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN)
+                                                                    | P_Fld(1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL)
+                                                                    | P_Fld(0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME));
+#endif
+
+    //Darren-vIO32WriteFldAlign(DDRPHY_REG_B0_DQ6, !(p->odt_onoff), B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0);
+    //Darren-vIO32WriteFldAlign(DDRPHY_REG_B1_DQ6, !(p->odt_onoff), B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1);
+    //Darren-vIO32WriteFldAlign(DDRPHY_REG_CA_CMD6, !(p->odt_onoff), CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS);
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ13, !(p->odt_onoff), SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0);
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ13, !(p->odt_onoff), SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1);
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD13, !(p->odt_onoff), SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA);
+
+    //APHY CG disable
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13, P_Fld(0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0)
+                                            | P_Fld(0, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0));
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ14, 0, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0);
+
+    if (!isLP4_DSC)
+    {
+        vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13, P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1)
+                                            | P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1));
+        vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ14, 0, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1);
+    }
+    else
+    {
+        vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD13, P_Fld(0, SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA)
+                                            | P_Fld(0, SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA));
+        vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD14, 0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA);
+    }
+}
+
+/* LP4 use 7UI mode (1)
+ * LP5 lower than 4266 use 7UI mode (1)
+ * LP5 higher than 4266 use 11UI mode (2)
+ * LP5 higher than 4266 with better SI use 11/24UI mode (3)
+ */
+static void DQSSTBSettings(DRAMC_CTX_T *p)
+{
+    unsigned int dqsien_mode = 1;
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+#if (__LP5_COMBO__)
+    U8 rpre_mode = LPDDR5_RPRE_4S_0T;
+
+    if (is_lp5_family(p))
+    {
+        if (p->frequency > 1600)
+            rpre_mode = LPDDR5_RPRE_2S_2T;
+    }
+
+    if (rpre_mode == LPDDR5_RPRE_2S_2T)
+        dqsien_mode = 2;
+    else if (rpre_mode == LPDDR5_RPRE_XS_4T)
+        dqsien_mode = 3;
+#endif
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
+        dqsien_mode, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10),
+        dqsien_mode, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0);
+    if(!isLP4_DSC)
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10),
+            dqsien_mode, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1);
+    else
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD10),
+            dqsien_mode, SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_MODE_CA);
+}
+
+static void SetMck8xLowPwrOption(DRAMC_CTX_T *p)
+{
+#if ENABLE_REMOVE_MCK8X_UNCERT_LOWPOWER_OPTION
+    U32 u4Mck8xMode = 1;
+#else
+    U32 u4Mck8xMode = 0;
+#endif
+
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_LP_CTRL,  P_Fld( u4Mck8xMode , MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL ) \
+                                                              | P_Fld( u4Mck8xMode , MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL      ) \
+                                                              | P_Fld( u4Mck8xMode, MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL       ) \
+                                                              | P_Fld( u4Mck8xMode , MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL       ) \
+                                                              | P_Fld( u4Mck8xMode , MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL) \
+                                                              | P_Fld( u4Mck8xMode, MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL          ) \
+                                                              | P_Fld( u4Mck8xMode , MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL      ));
+
+}
+
+void LP4_UpdateInitialSettings(DRAMC_CTX_T *p)
+{
+    U8 u1RankIdx, u1RankIdxBak;
+    ///TODO:
+    //BRINGUP-TEST
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL3, 0, MISC_CTRL3_ARPI_CG_CLK_OPT);
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL4, 0, MISC_CTRL4_R_OPT2_CG_CLK);
+
+    //vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld(1, CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA) | P_Fld(0, CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA));
+    //vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld(1, CA_CMD2_RG_TX_ARCLKB_OE_TIE_EN_CA) | P_Fld(0, CA_CMD2_RG_TX_ARCLKB_OE_TIE_SEL_CA));
+    //Set_MRR_Pinmux_Mapping(p); //Update MRR pinmux
+
+    vReplaceDVInit(p);
+
+    //Let CA and CS be independent
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD14, 0x0, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA); //@Jimmy, confirm with WL set EMCP/DSC = 0, from mt6833
+
+    //Disable perbyte option
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0)
+                                            | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0)
+                                            | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1)
+                                            | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1)
+                                            | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1));
+
+#if RX_PICG_NEW_MODE
+    RXPICGSetting(p);
+#endif
+
+#if SIMULATION_SW_IMPED // Darren: Need porting by E2 IMP Calib DVT owner
+    #if FSP1_CLKCA_TERM
+        U8 u1CASwImpFreqRegion = (p->dram_fsp == FSP_0)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
+    #else
+        U8 u1CASwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
+    #endif
+        U8 u1DQSwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
+
+    if (p->dram_type == TYPE_LPDDR4X)
+        DramcSwImpedanceSaveRegister(p, u1CASwImpFreqRegion, u1DQSwImpFreqRegion, DRAM_DFS_REG_SHU0);
+#endif
+
+    DQSSTBSettings(p);
+
+    RODTSettings(p);
+
+    //WDBI-OFF
+    vIO32WriteFldAlign(DRAMC_REG_SHU_TX_SET0, 0x0, SHU_TX_SET0_DBIWR);
+
+#if CBT_MOVE_CA_INSTEAD_OF_CLK
+    U8 u1CaPI = 0, u1CaUI = 0;
+
+    u1CaUI = 1;
+    u1CaPI = 0;
+
+    // CA delay shift u1CaUI*UI
+    DramcCmdUIDelaySetting(p, u1CaUI);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1));
+
+    // Rank0/1 u1CaPI*PI CA delay
+
+    u1RankIdxBak = u1GetRank(p);
+
+    for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+
+        CBTDelayCACLK(p, u1CaPI);
+    }
+
+    vSetRank(p, u1RankIdxBak);
+#endif
+
+#if ENABLE_TPBR2PBR_REFRESH_TIMING
+    vIO32WriteFldAlign(DRAMC_REG_REFCTRL1, 0x1, REFCTRL1_REF_OVERHEAD_PBR2PB_ENA); //@Derping
+    vIO32WriteFldAlign(DRAMC_REG_MISCTL0, 0x1, MISCTL0_REFP_ARBMASK_PBR2PBR_ENA); //@Unique
+    vIO32WriteFldAlign(DRAMC_REG_SCHEDULER_COM, 0x1, SCHEDULER_COM_PBR2PBR_OPT); //@YH
+#endif
+
+#if RDSEL_TRACKING_EN
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, 0, SHU_MISC_RDSEL_TRACK_DMDATLAT_I); //DMDATLAT_I should be set as 0 before set datlat k value, otherwise the status flag wil be set as 1
+#endif
+
+#if ENABLE_WRITE_POST_AMBLE_1_POINT_5_TCK
+    vIO32WriteFldAlign(DRAMC_REG_SHU_TX_SET0, p->dram_fsp, SHU_TX_SET0_WPST1P5T); //Set write post-amble by FSP with MR3
+#else
+    vIO32WriteFldAlign(DRAMC_REG_SHU_TX_SET0, 0x0, SHU_TX_SET0_WPST1P5T); //Set write post-amble by FSP with MR3
+#endif
+
+#if (!XRTRTR_NEW_CROSS_RK_MODE)
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, 0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN);
+#endif
+
+#if (fcFOR_CHIP_ID == fc8195)
+    if(p->support_rank_num== RANK_SINGLE)
+        vIO32WriteFldAlign(DRAMC_REG_CMD_DEC_CTRL0, 1, CMD_DEC_CTRL0_CS1FIXOFF);
+
+    //vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_EMI_CTRL, 0x26, SHU_MISC_EMI_CTRL_DR_EMI_RESERVE);//Alex-CH checked
+#endif
+
+    //MP Setting
+    vIO32WriteFldMulti(DRAMC_REG_DUMMY_RD, P_Fld(0x1, DUMMY_RD_DMYRD_REORDER_DIS) | P_Fld(0x1, DUMMY_RD_SREF_DMYRD_EN));
+    // @Unique, sync MP settings
+    vIO32WriteFldMulti(DRAMC_REG_DRAMCTRL, P_Fld(0x0, DRAMCTRL_ALL_BLOCK_CTO_ALE_DBG_EN)
+                                     | P_Fld(0x1, DRAMCTRL_DVFS_BLOCK_CTO_ALE_DBG_EN)
+                                     | P_Fld(0x1, DRAMCTRL_SELFREF_BLOCK_CTO_ALE_DBG_EN));
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 1, MISC_STBCAL2_DQSGCNT_BYP_REF);
+    //@Darren- enable bit11 via FMeter, vIO32WriteFldAlign(DDRPHY_REG_MISC_CG_CTRL7, 0, MISC_CG_CTRL7_CK_BFE_DCM_EN);
+
+    //1:8 --> data rate<=1600 set 0,  data rate<=3200 set 1, else 2
+    //1:4 --> data rate<= 800 set 0,  data rate<=1600 set 1, else 2
+    // @Darren, confirm w/ Chau-Wei Wang (Jason) sync MP settings
+    if(p->frequency<=800)
+        vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, 0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD);
+    else if(p->frequency<=1200)
+        vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, 1, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD);
+    else // for DDR4266/DDR3200
+        vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, 2, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD);
+
+    // @Darren, Fix DQ/DQM duty PI not work.
+    vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL1, 1, MISC_CTRL1_R_DMARPIDQ_SW);
+
+    // @Darren, sync MP from Mao
+    vIO32WriteFldMulti(DDRPHY_REG_CA_TX_MCK, P_Fld(0xa, CA_TX_MCK_R_DMRESETB_DRVP_FRPHY) | P_Fld(0xa, CA_TX_MCK_R_DMRESETB_DRVN_FRPHY));
+
+    // @Darren, Fix GE for new RANK_SEL design from HJ/WL Lee (B16/8 + APHY design skew = 3*MCK)
+    /*
+    DQSI_DIV latency:
+    100ps +    200ps     +    234ps*3    +    200ps      = 1202ps
+    (INB)      (gate dly)     (3UI@4266)     (LVSH+wire)
+
+    LEAD/LAG latency: (after retime with DQSI_DIV_INV) 200ps (LVSH+wire)
+    */
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x3, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
+            P_Fld(0x3, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x3, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
+
+    SetMck8xLowPwrOption(p);
+}
+
+#if __LP5_COMBO__
+void LP5_UpdateInitialSettings(DRAMC_CTX_T *p)
+{
+    U8 u1RankIdx, u1RankIdxBak;
+
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD14, 0x0, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA); //Let CA and CS be independent
+    //Set_MRR_Pinmux_Mapping(p); //Update MRR pinmux
+
+    //Disable perbyte option
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0)
+                                            | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0)
+                                            | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0));
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1)
+                                            | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1)
+                                            | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1));
+
+    ///TODO: Temp solution. May need to resolve in init flow
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL5, /* Will cause PI un-adjustable */
+        P_Fld(0x0, MISC_CG_CTRL5_R_CA_DLY_DCM_EN) |
+        P_Fld(0x0, MISC_CG_CTRL5_R_CA_PI_DCM_EN) |
+        P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN) |
+        P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN) |
+        P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN) |
+        P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN));
+
+    DQSSTBSettings(p);
+
+    RODTSettings(p);
+
+#if SIMULATION_SW_IMPED
+    #if FSP1_CLKCA_TERM
+        U8 u1CASwImpFreqRegion = (p->dram_fsp == FSP_0)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
+    #else
+        U8 u1CASwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
+    #endif
+        U8 u1DQSwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
+
+    if (p->dram_type == TYPE_LPDDR5)
+        DramcSwImpedanceSaveRegister(p, u1CASwImpFreqRegion, u1DQSwImpFreqRegion, DRAM_DFS_REG_SHU0);
+#endif
+
+#if RDSEL_TRACKING_EN
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, 0, SHU_MISC_RDSEL_TRACK_DMDATLAT_I); //DMDATLAT_I should be set as 0 before set datlat k value, otherwise the status flag wil be set as 1
+#endif
+
+#if (!XRTRTR_NEW_CROSS_RK_MODE)
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, 0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN);
+#endif
+    SetMck8xLowPwrOption(p);
+}
+#endif
+
+#define CKGEN_FMETER 0x0
+#define ABIST_FMETER 0x1
+/*
+1. Select meter clock input: CLK_DBG_CFG[1:0] = 0x0
+2. Select clock source from below table: CLK_DBG_CFG[21:16] = 0x39
+3. Setup meter div: CLK_MISC_CFG_0[31:24] = 0x0
+4. Enable frequency meter: CLK26CALI_0[12] = 0x1
+5. Trigger frequency meter: CLK26CALI_0[4] = 0x1
+6. Wait until CLK26CALI_0[4] = 0x0
+7. Read meter count: CLK26CALI_1[15:0]
+8. Calculate measured frequency: freq. = (26 * cal_cnt) / 1024
+
+DE: Mas Lin
+*/
+static unsigned int FMeter(unsigned char u1CLKMeterSel, unsigned char u1CLKMuxSel)
+{
+#if (FOR_DV_SIMULATION_USED==0)
+    unsigned int tmp, u4CalCnt;
+
+    // enable fmeter
+    DRV_WriteReg32(CLK26CALI_0, (0x1 << 7));
+
+    // select meter
+    tmp = DRV_Reg32(CLK_DBG_CFG);
+    tmp &= ~0x3;
+
+    if (u1CLKMeterSel == CKGEN_FMETER)
+        tmp |= 0x1;
+
+    DRV_WriteReg32(CLK_DBG_CFG, tmp);
+
+    // select fmeter's input clock
+    tmp = DRV_Reg32(CLK_DBG_CFG);
+
+    if (u1CLKMeterSel == CKGEN_FMETER) {
+        tmp &= ~(0xFF << 16);
+        tmp |=  u1CLKMuxSel << 16;
+    } else {
+        tmp &= ~(0x7F << 8);
+        tmp |=  u1CLKMuxSel << 8;
+    }
+
+    DRV_WriteReg32(CLK_DBG_CFG, tmp);
+
+    // setup fmeter div
+    tmp = DRV_Reg32(CLK_MISC_CFG_0);
+    tmp &= ~(0xFF << 24);
+    DRV_WriteReg32(CLK_MISC_CFG_0, tmp);
+
+    // set load_cnt to 0x3FF (1024 - 1)
+    tmp = DRV_Reg32(CLK26CALI_1);
+    tmp &= ~(0x3FF << 16);
+    tmp |= 0x3FF << 16;
+    DRV_WriteReg32(CLK26CALI_1, tmp);
+
+    // trigger fmeter
+    tmp = DRV_Reg32(CLK26CALI_0);
+    tmp |= (0x1 << 4);
+    DRV_WriteReg32(CLK26CALI_0, tmp);
+
+    // wait
+    while (DRV_Reg32(CLK26CALI_0) & (0x1 << 4)) {
+        mcDELAY_US(1);
+    }
+
+    // read
+    u4CalCnt = DRV_Reg32(CLK26CALI_1) & 0xFFFF;
+
+    // disable fmeter
+    tmp = DRV_Reg32(CLK26CALI_0);
+    tmp &= ~(0x1 << 7);
+    DRV_WriteReg32(CLK26CALI_0, tmp);
+
+    return ((u4CalCnt * 26) / 1024);
+#endif
+}
+
+unsigned int DDRPhyFreqMeter(DRAMC_CTX_T *p)
+{
+
+#if (FOR_DV_SIMULATION_USED == 0)
+
+    unsigned int reg0=0;//reg1=0
+    unsigned int backup_phypll = 0, backup_clrpll = 0;
+    unsigned int before_value=0, after_value=0;
+    unsigned int frq_result=0;
+    unsigned int meter_value=0;
+    U16 frqValue = 0;
+
+#if 1//def HJ_SIM
+    /*TINFO="\n[PhyFreqMeter]"*/
+
+    reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c) ;
+    backup_phypll = reg0;
+    DRV_WriteReg32  (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c  , reg0 | (1 << 16));
+    reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x72c) ;
+    backup_clrpll = reg0;
+    DRV_WriteReg32  (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x72c  , reg0 | (1 << 16));
+
+    mcDELAY_US(1);
+    // abist_clk22: AD_CLKSQ_FS26M_CK
+    frq_result = FMeter(ABIST_FMETER, 22);
+    mcSHOW_DBG_MSG4(("AD_CLKSQ_FS26M_CK=%d MHz\n", frq_result));
+
+    // abist_clk30: AD_MPLL_CK
+	frq_result = FMeter(ABIST_FMETER, 30);
+	mcSHOW_DBG_MSG4(("AD_MPLL_CK=%d MHz\n", frq_result));
+    /*TINFO="AD_MPLL_CK FREQ=%d\n", frq_result*/
+
+    #if 1
+    if((DRV_Reg32(Channel_A_DDRPHY_NAO_BASE_ADDRESS + 0x50c) & (1<<8))==0)
+    {
+        // abist_clk119: AD_RCLRPLL_DIV4_CK_ch01
+        //frq_result = FMeter(ABIST_FMETER, 119);
+        //mcSHOW_DBG_MSG4(("AD_RCLRPLL_DIV4_CK_ch01 FREQ=%d MHz\n", frq_result));
+        /*TINFO="AD_RCLRPLL_DIV4_CK_ch01 FREQ=%d\n", frq_result*/
+    }
+    else
+    {
+        // abist_clk120: AD_RPHYRPLL_DIV4_CK_ch01
+        //frq_result = FMeter(ABIST_FMETER, 120);
+        //mcSHOW_DBG_MSG4(("AD_RPHYRPLL_DIV4_CK_ch01 FREQ=%d\n", frq_result));
+        /*TINFO="AD_RPHYRPLL_DIV4_CK_ch01 FREQ=%d\n", frq_result*/
+    }
+    #endif
+    //! ch0
+    reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x504) ;
+    DRV_WriteReg32  (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x504  , reg0 | (1 << 11));
+
+    // abistgen_clk118: fmem_ck_bfe_dcm_ch0 (DRAMC CHA's clock before idle mask)
+	before_value = FMeter(ABIST_FMETER, 118);
+	mcSHOW_DBG_MSG4(("fmem_ck_bfe_dcm_ch0 FREQ=%d MHz\n", before_value));
+    /*TINFO="fmem_ck_bfe_dcm_ch0 FREQ=%d\n", before_value*/
+
+    // abistgen_clk117: fmem_ck_aft_dcm_ch0 (DRAMC CHA's clock after idle mask)
+	after_value = FMeter(ABIST_FMETER, 117);
+    mcSHOW_DBG_MSG4(("fmem_ck_aft_dcm_ch0 FREQ=%d MHz\n", after_value));
+    /*TINFO="fmem_ck_aft_dcm_ch0 FREQ=%d\n", after_value*/
+
+    //gddrphyfmeter_value = after_value << 2;
+
+    #if 0 // @ tg change for Open loop mode(0x70C need fix 1)
+    reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c) ;
+    DRV_WriteReg32  (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c  , reg0 & ~(1 << 16));
+    reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x72c) ;
+    DRV_WriteReg32  (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x72c  , reg0 & ~(1 << 16));
+    #else
+    DRV_WriteReg32  (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c  , backup_phypll);
+    DRV_WriteReg32  (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x72c  , backup_clrpll);
+    #endif
+
+    #if (CHANNEL_NUM>2)
+	    if (channel_num_auxadc > 2) {
+		    reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x70c) ;
+		    DRV_WriteReg32  (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x70c  , reg0 | (1 << 16));
+		    reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x72c) ;
+		    DRV_WriteReg32  (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x72c  , reg0 | (1 << 16));
+
+    #if 1
+    if((DRV_Reg32(Channel_C_DDRPHY_NAO_BASE_ADDRESS + 0x50c) & (1<<8))==0)
+    {
+        // abist_clk116: AD_RCLRPLL_DIV4_CK_ch23
+        //frq_result = FMeter(ABIST_FMETER, 116);
+        //mcSHOW_DBG_MSG4(("AD_RCLRPLL_DIV4_CK_ch23 FREQ=%d MHz\n", frq_result));
+        /*TINFO="AD_RCLRPLL_DIV4_CK_ch23 FREQ=%d\n", frq_result*/
+    }
+    else
+    {
+        // abist_clk115: AD_RPHYRPLL_DIV4_CK_ch23
+        //frq_result = FMeter(ABIST_FMETER, 115);
+        //mcSHOW_DBG_MSG4(("AD_RPHYRPLL_DIV4_CK_ch23 FREQ=%d\n", frq_result));
+        /*TINFO="AD_RPHYRPLL_DIV4_CK_ch23 FREQ=%d\n", frq_result*/
+    }
+    #endif
+
+    reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x504) ;
+    DRV_WriteReg32  (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x504  , reg0 | (1 << 11));
+    reg0 = DRV_Reg32(Channel_D_DDRPHY_AO_BASE_ADDRESS + 0x504) ;
+    DRV_WriteReg32  (Channel_D_DDRPHY_AO_BASE_ADDRESS + 0x504  , reg0 | (1 << 11));
+
+    // abistgen_clk114: fmem_ck_bfe_dcm_ch2 (DRAMC CHC's clock after idle mask)
+	before_value = FMeter(ABIST_FMETER, 114);
+    mcSHOW_DBG_MSG4(("fmem_ck_bfe_dcm_ch2 FREQ=%d MHz\n", before_value));
+    /*TINFO="fmem_ck_bfe_dcm_ch2 FREQ=%d\n", after_value*/
+
+    // abistgen_clk113: fmem_ck_aft_dcm_ch2 (DRAMC CHC's clock after idle mask)
+	after_value = FMeter(ABIST_FMETER, 113);
+    mcSHOW_DBG_MSG4(("fmem_ck_aft_dcm_ch2 FREQ=%d MHz\n", after_value));
+    /*TINFO="fmem_ck_aft_dcm_ch2 FREQ=%d\n", after_value*/
+
+    reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x70c) ;
+    DRV_WriteReg32  (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x70c  , reg0 & ~(1 << 16));
+    reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x72c) ;
+    DRV_WriteReg32  (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x72c  , reg0 & ~(1 << 16));
+	}
+    #endif
+
+    meter_value = (before_value<<16 | after_value);
+#else
+    mcSHOW_DBG_MSG3(("\n[PhyFreqMeter]\n"));
+    // abist_clk29: AD_MPLL_CK
+    mcSHOW_DBG_MSG(("AD_MPLL_CK FREQ=%d\n", FMeter(ABIST_FMETER, 29)));
+
+    // abist_clk31: AD_RCLRPLL_DIV4_CK_ch02
+    mcSHOW_DBG_MSG(("AD_RCLRPLL_DIV4_CK_ch02 FREQ=%d\n", FMeter(ABIST_FMETER, 31)));
+
+    // abist_clk32: AD_RCLRPLL_DIV4_CK_ch13
+    mcSHOW_DBG_MSG(("AD_RCLRPLL_DIV4_CK_ch13 FREQ=%d\n", FMeter(ABIST_FMETER, 32)));
+
+    // abist_clk33: AD_RPHYRPLL_DIV4_CK_ch02
+    mcSHOW_DBG_MSG(("AD_RPHYRPLL_DIV4_CK_ch02 FREQ=%d\n", FMeter(ABIST_FMETER, 33)));
+
+    // abist_clk34: AD_RPHYRPLL_DIV4_CK_ch13
+    mcSHOW_DBG_MSG(("AD_RPHYRPLL_DIV4_CK_ch13 FREQ=%d\n", FMeter(ABIST_FMETER, 34)));
+
+    // enable ck_bfe_dcm_en for freqmeter measure ddrphy clock, not needed for normal use
+    reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x504) ;
+    DRV_WriteReg32  (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x504  , reg0 | (1 << 11));
+
+    reg0 = DRV_Reg32(Channel_B_DDRPHY_AO_BASE_ADDRESS + 0x504) ;
+    DRV_WriteReg32  (Channel_B_DDRPHY_AO_BASE_ADDRESS + 0x504  , reg0 | (1 << 11));
+
+    reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x504) ;
+    DRV_WriteReg32  (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x504  , reg0 | (1 << 11));
+
+    reg0 = DRV_Reg32(Channel_D_DDRPHY_AO_BASE_ADDRESS + 0x504) ;
+    DRV_WriteReg32  (Channel_D_DDRPHY_AO_BASE_ADDRESS + 0x504  , reg0 | (1 << 11));
+
+    // abistgen_clk44: fmem_ck_bfe_dcm_ch0 (DRAMC CHA's clock before idle mask)
+    before_value = FMeter(ABIST_FMETER, 44);
+    mcSHOW_DBG_MSG(("fmem_ck_bfe_dcm_ch0 FREQ=%d\n", FMeter(ABIST_FMETER, 44)));
+
+    // abistgen_clk45: fmem_ck_bfe_dcm_ch1 (DRAMC CHB's clock before idle mask)
+    before_value = FMeter(ABIST_FMETER, 45);
+    mcSHOW_DBG_MSG(("fmem_ck_bfe_dcm_ch1 FREQ=%d\n", FMeter(ABIST_FMETER, 45)));
+
+    // abistgen_clk46: fmem_ck_bfe_dcm_ch2 (DRAMC CHC's clock before idle mask)
+    before_value = FMeter(ABIST_FMETER, 46);
+    mcSHOW_DBG_MSG(("fmem_ck_bfe_dcm_ch2 FREQ=%d\n", FMeter(ABIST_FMETER, 46)));
+
+    // abistgen_clk47: fmem_ck_bfe_dcm_ch3 (DRAMC CHC's clock before idle mask)
+    before_value = FMeter(ABIST_FMETER, 47);
+    mcSHOW_DBG_MSG(("fmem_ck_bfe_dcm_ch3 FREQ=%d\n", FMeter(ABIST_FMETER, 47)));
+
+    return 1;
+#if 0
+    DRV_WriteReg32(DRAMC_CH0_TOP0_BASE + 0x2a0, reg0);
+    DRV_WriteReg32(DRAMC_CH1_TOP0_BASE + 0x2a0, reg1);
+
+    return ((before_value<<16) | after_value);
+#endif
+
+#endif //! end DSIM
+
+        if(vGet_Div_Mode(p) == DIV8_MODE)
+        {
+        frqValue = (meter_value & 0xFFFF) << 2;
+        }
+        else if(vGet_Div_Mode(p) == DIV4_MODE)
+        {
+        frqValue = (meter_value & 0xFFFF) << 1;
+        }
+        else if(vGet_Div_Mode(p) == DIV16_MODE)
+        {
+        frqValue = (meter_value & 0xFFFF) << 4;
+        }
+        else
+        {
+            mcSHOW_ERR_MSG(("[DDRPhyFreqMeter] Get DIV mode error!\n"));
+        #if __ETT__
+            while (1);
+        #endif
+        }
+
+    return frqValue;
+
+#endif
+}
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
new file mode 100644
index 000000000000..72cdb11157e5
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
@@ -0,0 +1,14947 @@
+/*----------------------------------------------------------------------------*
+ * Copyright Statement:                                                       *
+ *                                                                            *
+ *   This software/firmware and related documentation ("MediaTek Software")   *
+ * are protected under international and related jurisdictions'copyright laws *
+ * as unpublished works. The information contained herein is confidential and *
+ * proprietary to MediaTek Inc. Without the prior written permission of       *
+ * MediaTek Inc., any reproduction, modification, use or disclosure of        *
+ * MediaTek Software, and information contained herein, in whole or in part,  *
+ * shall be strictly prohibited.                                              *
+ * MediaTek Inc. Copyright (C) 2010. All rights reserved.                     *
+ *                                                                            *
+ *   BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND     *
+ * AGREES TO THE FOLLOWING:                                                   *
+ *                                                                            *
+ *   1)Any and all intellectual property rights (including without            *
+ * limitation, patent, copyright, and trade secrets) in and to this           *
+ * Software/firmware and related documentation ("MediaTek Software") shall    *
+ * remain the exclusive property of MediaTek Inc. Any and all intellectual    *
+ * property rights (including without limitation, patent, copyright, and      *
+ * trade secrets) in and to any modifications and derivatives to MediaTek     *
+ * Software, whoever made, shall also remain the exclusive property of        *
+ * MediaTek Inc.  Nothing herein shall be construed as any transfer of any    *
+ * title to any intellectual property right in MediaTek Software to Receiver. *
+ *                                                                            *
+ *   2)This MediaTek Software Receiver received from MediaTek Inc. and/or its *
+ * representatives is provided to Receiver on an "AS IS" basis only.          *
+ * MediaTek Inc. expressly disclaims all warranties, expressed or implied,    *
+ * including but not limited to any implied warranties of merchantability,    *
+ * non-infringement and fitness for a particular purpose and any warranties   *
+ * arising out of course of performance, course of dealing or usage of trade. *
+ * MediaTek Inc. does not provide any warranty whatsoever with respect to the *
+ * software of any third party which may be used by, incorporated in, or      *
+ * supplied with the MediaTek Software, and Receiver agrees to look only to   *
+ * such third parties for any warranty claim relating thereto.  Receiver      *
+ * expressly acknowledges that it is Receiver's sole responsibility to obtain *
+ * from any third party all proper licenses contained in or delivered with    *
+ * MediaTek Software.  MediaTek is not responsible for any MediaTek Software  *
+ * releases made to Receiver's specifications or to conform to a particular   *
+ * standard or open forum.                                                    *
+ *                                                                            *
+ *   3)Receiver further acknowledge that Receiver may, either presently       *
+ * and/or in the future, instruct MediaTek Inc. to assist it in the           *
+ * development and the implementation, in accordance with Receiver's designs, *
+ * of certain softwares relating to Receiver's product(s) (the "Services").   *
+ * Except as may be otherwise agreed to in writing, no warranties of any      *
+ * kind, whether express or implied, are given by MediaTek Inc. with respect  *
+ * to the Services provided, and the Services are provided on an "AS IS"      *
+ * basis. Receiver further acknowledges that the Services may contain errors  *
+ * that testing is important and it is solely responsible for fully testing   *
+ * the Services and/or derivatives thereof before they are used, sublicensed  *
+ * or distributed. Should there be any third party action brought against     *
+ * MediaTek Inc. arising out of or relating to the Services, Receiver agree   *
+ * to fully indemnify and hold MediaTek Inc. harmless.  If the parties        *
+ * mutually agree to enter into or continue a business relationship or other  *
+ * arrangement, the terms and conditions set forth herein shall remain        *
+ * effective and, unless explicitly stated otherwise, shall prevail in the    *
+ * event of a conflict in the terms in any agreements entered into between    *
+ * the parties.                                                               *
+ *                                                                            *
+ *   4)Receiver's sole and exclusive remedy and MediaTek Inc.'s entire and    *
+ * cumulative liability with respect to MediaTek Software released hereunder  *
+ * will be, at MediaTek Inc.'s sole discretion, to replace or revise the      *
+ * MediaTek Software at issue.                                                *
+ *                                                                            *
+ *   5)The transaction contemplated hereunder shall be construed in           *
+ * accordance with the laws of Singapore, excluding its conflict of laws      *
+ * principles.  Any disputes, controversies or claims arising thereof and     *
+ * related thereto shall be settled via arbitration in Singapore, under the   *
+ * then current rules of the International Chamber of Commerce (ICC).  The    *
+ * arbitration shall be conducted in English. The awards of the arbitration   *
+ * shall be final and binding upon both parties and shall be entered and      *
+ * enforceable in any court of competent jurisdiction.                        *
+ *---------------------------------------------------------------------------*/
+
+//-----------------------------------------------------------------------------
+// Include files
+//-----------------------------------------------------------------------------
+#include "dramc_common.h"
+#include "dramc_int_global.h"
+#include "x_hal_io.h"
+#include "sv_c_data_traffic.h"
+#if (FOR_DV_SIMULATION_USED == 0)
+#include "dramc_top.h"
+#endif
+
+#define BITMAP_BITS_MAX         128
+
+#define MAX_CLK_PI_DELAY        31
+
+#define PASS_RANGE_NA   0x7fff
+
+#define DIE_NUM_MAX         1 //LP4 only
+static U8 fgwrlevel_done = 0;
+
+#if __ETT__
+U8 gETT_WHILE_1_flag = 1;
+#endif
+//#define CBT_NEW_PAT_DEBUG
+
+U8 u1MR01Value[FSP_MAX];
+U8 u1MR02Value[FSP_MAX];
+U8 u1MR03Value[FSP_MAX];
+U8 u1MR11Value[FSP_MAX];
+U8 u1MR18Value[FSP_MAX];
+U8 u1MR19Value[FSP_MAX];
+U8 u1MR20Value[FSP_MAX];
+U8 u1MR21Value[FSP_MAX];
+U8 u1MR22Value[FSP_MAX];
+U8 u1MR51Value[FSP_MAX];
+
+U8 u1MR04Value[RANK_MAX];
+U8 u1MR13Value[RANK_MAX];
+U8 u1MR26Value[RANK_MAX];
+U8 u1MR30Value[RANK_MAX];
+
+U8 u1MR12Value[CHANNEL_NUM][RANK_MAX][FSP_MAX];
+U8 u1MR14Value[CHANNEL_NUM][RANK_MAX][FSP_MAX];
+U16 gu2MR0_Value[RANK_MAX] = {0xffff, 0xffff};
+
+#if PINMUX_AUTO_TEST_PER_BIT_RX
+S16 gFinalRXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH];
+#endif
+#if PINMUX_AUTO_TEST_PER_BIT_TX
+S16 gFinalTXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH];
+#endif
+#if PINMUX_AUTO_TEST_PER_BIT_CA
+S16 gFinalCAPerbitFirstPass[CHANNEL_NUM][RANK_MAX][CATRAINING_NUM_LP4];
+#endif
+
+#ifdef FOR_HQA_TEST_USED
+U16 gFinalCBTVrefCA[CHANNEL_NUM][RANK_MAX];
+U16 gFinalCBTCA[CHANNEL_NUM][RANK_MAX][10];
+U16 gFinalRXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH];
+U16 gFinalTXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH];
+U16 gFinalTXPerbitWin_min_max[CHANNEL_NUM][RANK_MAX];
+U16 gFinalTXPerbitWin_min_margin[CHANNEL_NUM][RANK_MAX];
+U16 gFinalTXPerbitWin_min_margin_bit[CHANNEL_NUM][RANK_MAX];
+S8 gFinalClkDuty[CHANNEL_NUM];
+U32 gFinalClkDutyMinMax[CHANNEL_NUM][2];
+S8 gFinalDQSDuty[CHANNEL_NUM][DQS_BYTE_NUMBER];
+U32 gFinalDQSDutyMinMax[CHANNEL_NUM][DQS_BYTE_NUMBER][2];
+#endif
+
+U8 gFinalCBTVrefDQ[CHANNEL_NUM][RANK_MAX];
+U8 gFinalRXVrefDQ[CHANNEL_NUM][RANK_MAX][2];
+U8 gFinalTXVrefDQ[CHANNEL_NUM][RANK_MAX];
+
+#if defined(RELEASE)
+U8 gEye_Scan_color_flag = 0;
+U8 gCBT_EYE_Scan_flag = 0;
+U8 gCBT_EYE_Scan_only_higheset_freq_flag = 1;
+U8 gRX_EYE_Scan_flag = 0;
+U8 gRX_EYE_Scan_only_higheset_freq_flag = 1;
+U8 gTX_EYE_Scan_flag = 1;
+U8 gTX_EYE_Scan_only_higheset_freq_flag = 1;
+U8 gEye_Scan_unterm_highest_flag = 0;
+#elif  (CFG_DRAM_LOG_TO_STORAGE)
+U8 gEye_Scan_color_flag = 0;
+U8 gCBT_EYE_Scan_flag = 0;
+U8 gCBT_EYE_Scan_only_higheset_freq_flag = 1;
+U8 gRX_EYE_Scan_flag = 1;
+U8 gRX_EYE_Scan_only_higheset_freq_flag = 1;
+U8 gTX_EYE_Scan_flag = 1;
+U8 gTX_EYE_Scan_only_higheset_freq_flag = 1;
+U8 gEye_Scan_unterm_highest_flag = 0;
+#else
+U8 gEye_Scan_color_flag = 1;
+U8 gCBT_EYE_Scan_flag = 0;
+U8 gCBT_EYE_Scan_only_higheset_freq_flag = 1;
+U8 gRX_EYE_Scan_flag = 0;
+U8 gRX_EYE_Scan_only_higheset_freq_flag = 1;
+U8 gTX_EYE_Scan_flag = 0;
+U8 gTX_EYE_Scan_only_higheset_freq_flag = 1;
+U8 gEye_Scan_unterm_highest_flag = 0;
+#endif
+
+#ifdef DEVIATION
+U8 gSetSpecificedVref_Enable[3]={0};
+U8 gSetSpecificedVref_Type=0;
+U8 gSetSpecificedVref_All_ChRk[3]={0};
+U8 gSetSpecificedVref_Channel[3]={0};
+U8 gSetSpecificedVref_Rank[3]={0};
+S8 gSetSpecificedVref_Vref_Offset[3]={0};
+#endif
+
+#ifdef FOR_HQA_REPORT_USED
+#if CFG_DRAM_LOG_TO_STORAGE
+U8 gHQALog_flag = 1;
+#else
+U8 gHQALog_flag = 0;
+#endif
+U16 gHQALOG_RX_delay_cell_ps_075V = 0;
+U8 gHQALog_SLT_BIN[DRAM_DFS_SRAM_MAX] = {0};
+#endif
+
+#if (TX_AUTO_K_SUPPORT && TX_AUTO_K_WORKAROUND)
+U32 u4DQM_MCK_RK1_backup;
+U32 u4DQM_UI_RK1_backup;
+U32 u4DQM_PI_RK1_backup[2];
+U32 u4DQ_MCK_RK1_backup;
+U32 u4DQ_UI_RK1_backup;
+U32 u4DQ_PI_RK1_backup[2];
+#endif
+
+#if SIMULATION_RX_DVS
+U8 u1DVS_increase[RANK_MAX][DQS_BYTE_NUMBER];
+#endif
+
+//static U8 gu1DieNum[RANK_MAX]; // 2 rank may have different die number
+static S32 CATrain_CmdDelay[CHANNEL_NUM][RANK_MAX];
+static U32 CATrain_CsDelay[CHANNEL_NUM][RANK_MAX];
+//static S8 iFirstCAPass[RANK_MAX][DIE_NUM_MAX][CATRAINING_NUM];
+//static S8 iLastCAPass[RANK_MAX][DIE_NUM_MAX][CATRAINING_NUM];
+
+static S32 wrlevel_dqs_final_delay[RANK_MAX][DQS_BYTE_NUMBER]; // 3 is channel number
+//static U16 u2rx_window_sum;
+
+JMETER_DELAYCELL_T JMeter_DelayCell_Table[DRAM_DFS_SRAM_MAX]={0};
+
+U8 gFinalRXVrefDQForSpeedUp[CHANNEL_NUM][RANK_MAX][2/*ODT_onoff*/][2/*2bytes*/] = {0};
+U32 gDramcImpedanceResult[IMP_VREF_MAX][IMP_DRV_MAX] = {{0,0,0,0},{0,0,0,0},{0,0,0,0}};//ODT_ON/OFF x DRVP/DRVN/ODTP/ODTN
+
+S16 gu2RX_DQS_Duty_Offset[DQS_BYTE_NUMBER][2];
+
+#define RX_DELAY_PRE_CAL 1
+#if RX_DELAY_PRE_CAL
+S16 s2RxDelayPreCal=PASS_RANGE_NA;
+#endif
+
+#if MRW_CHECK_ONLY
+U16 u2MRRecord[CHANNEL_NUM][RANK_MAX][FSP_MAX][MR_NUM];
+#endif
+#if MRW_CHECK_ONLY || MRW_BACKUP
+U8 gFSPWR_Flag[RANK_MAX]={FSP_0};
+#endif
+
+#define IN_CBT  (0)
+#define OUT_CBT (1)
+
+#if PRINT_CALIBRATION_SUMMARY
+static void vSetCalibrationResult(DRAMC_CTX_T *p, U8 ucCalType, U8 ucResult)
+{
+    U32 *Pointer_CalExecute,*Pointer_CalResult;
+    if (ucCalType == DRAM_CALIBRATION_SW_IMPEDANCE)
+    {
+        Pointer_CalExecute = &p->SWImpCalExecute;
+        Pointer_CalResult = &p->SWImpCalResult;
+    }
+    else
+    {
+        Pointer_CalExecute = &p->aru4CalExecuteFlag[p->channel][p->rank];
+        Pointer_CalResult = &p->aru4CalResultFlag[p->channel][p->rank];
+    }
+
+    if (ucResult == DRAM_FAIL)  // Calibration FAIL
+    {
+        *Pointer_CalExecute |= (1<<ucCalType); // ececution done
+        *Pointer_CalResult |= (1<<ucCalType); // no result found
+    }
+    else if(ucResult == DRAM_OK)  // Calibration OK
+    {
+        *Pointer_CalExecute |= (1<<ucCalType); // ececution done
+        *Pointer_CalResult &= (~(1<<ucCalType)); // result found
+    }
+    else if(ucResult == DRAM_FAST_K)  // FAST K
+    {
+         *Pointer_CalExecute &= (~(1<<ucCalType)); // no ececution
+         *Pointer_CalResult &= (~(1<<ucCalType)); // result found
+    }
+    else  // NO K
+    {
+          *Pointer_CalExecute &= (~(1<<ucCalType)); // no ececution
+          *Pointer_CalResult |= (1<<ucCalType); // no result found
+    }
+}
+
+#if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK
+void Fast_K_CheckResult(DRAMC_CTX_T *p, U8 ucCalType)
+{
+    U32 CheckResult=0xFFFFFFFF;
+    U32 debug_cnt[2], u4all_result_R, u4all_result_F;
+    BOOL FastK_Check_flag=0;
+    U32 *Pointer_FastKExecute,*Pointer_FastKResult;
+
+    Pointer_FastKExecute = &p->FastKExecuteFlag[p->channel][p->rank];
+    Pointer_FastKResult = &p->FastKResultFlag[p->channel][p->rank];
+
+    if ((ucCalType==DRAM_CALIBRATION_TX_PERBIT)||(ucCalType==DRAM_CALIBRATION_DATLAT)||(ucCalType==DRAM_CALIBRATION_RX_PERBIT))
+    {
+        DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT);
+        CheckResult = DramcEngine2Run(p,TE_OP_WRITE_READ_CHECK , TEST_XTALK_PATTERN);
+        DramcEngine2End(p);
+        FastK_Check_flag=1;
+    }
+    else if (ucCalType==DRAM_CALIBRATION_RX_RDDQC)
+    {
+        DramcRxWinRDDQCInit(p);
+        CheckResult = DramcRxWinRDDQCRun(p);
+        DramcRxWinRDDQCEnd(p);
+        FastK_Check_flag=1;
+    }
+    else if (ucCalType==DRAM_CALIBRATION_GATING)
+    {
+        DramcEngine2Init(p, 0x55000000, 0xaa000000 |0x23, TEST_AUDIO_PATTERN, 0, TE_NO_UI_SHIFT);
+
+        //Gating Counter Reset
+        DramPhyReset(p);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1,
+                MISC_STBCAL2_DQSG_CNT_RST);
+        mcDELAY_US(1);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0,
+                MISC_STBCAL2_DQSG_CNT_RST);
+
+        DramcEngine2Run(p, TE_OP_READ_CHECK, TEST_AUDIO_PATTERN);
+
+        debug_cnt[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CAL_DQSG_CNT_B0));
+        debug_cnt[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CAL_DQSG_CNT_B1));
+
+        //mcSHOW_DBG_MSG((" 0x%X  ",u4DebugCnt))
+        if (debug_cnt[0]==0x4646 && debug_cnt[1]==0x4646)
+            CheckResult=0;
+
+        DramcEngine2End(p);
+        FastK_Check_flag=1;
+    }
+
+
+    if ((FastK_Check_flag==1)&&(CheckResult==0))
+    {
+        //mcSHOW_DBG_MSG((" [FAST K CHECK]->PASS\n"))
+        *Pointer_FastKResult &= (~(1<<ucCalType)); // result PASS
+        *Pointer_FastKExecute |= (1<<ucCalType);; // Excuted
+    }
+    else if ((FastK_Check_flag==1)&&(CheckResult !=0))
+    {
+        //mcSHOW_DBG_MSG((" [FAST K CHECK]->FAIL\n"))
+        *Pointer_FastKResult |= (1<<ucCalType); // result FAIL
+        *Pointer_FastKExecute |= (1<<ucCalType);; // Excuted
+    }
+}
+#endif
+
+const char *szCalibStatusName[DRAM_CALIBRATION_MAX]=
+{
+    "SW Impedance     ",
+    "DUTY Scan        ",
+    "ZQ Calibration   ",
+    "Jitter Meter     ",
+    "CBT Training     ",
+    "Write leveling   ",
+    "RX DQS gating    ",
+    "RX IN BUFF OFFC  ",
+    "RX DQ/DQS(RDDQC) ",
+    "TX DQ/DQS        ",
+    "RX DATLAT        ",
+    "RX DQ/DQS(Engine)",
+    "TX OE            ",
+};
+
+void vPrintCalibrationResult(DRAMC_CTX_T *p)
+{
+    U8 ucCHIdx, ucRankIdx, ucCalIdx;
+    U32 ucCalResult_All, ucCalExecute_All;
+    U8 ucCalResult, ucCalExecute;
+    U8 u1CalibrationFail;
+
+    mcSHOW_DBG_MSG(("\n\n[Calibration Summary] Freqency %d\n", p->frequency));
+
+    //for(ucFreqIdx=0; ucFreqIdx<DRAM_DFS_SRAM_MAX; ucFreqIdx++)
+    {
+        //mcSHOW_DBG_MSG(("==Freqency = %d==\n", get_FreqTbl_by_SRAMIndex(p,ucFreqIdx)->frequency));
+        for(ucCHIdx=0; ucCHIdx<p->support_channel_num; ucCHIdx++)
+        {
+            for(ucRankIdx=0; ucRankIdx<p->support_rank_num; ucRankIdx++)
+            {
+                u1CalibrationFail =0;
+                ucCalExecute_All = p->aru4CalExecuteFlag[ucCHIdx][ucRankIdx];
+                ucCalResult_All = p->aru4CalResultFlag[ucCHIdx][ucRankIdx];
+                mcSHOW_DBG_MSG(("CH %d, Rank %d\n", ucCHIdx, ucRankIdx));
+                //mcSHOW_DBG_MSG(("[vPrintCalibrationResult] Channel = %d, Rank= %d, Freq.= %d, (ucCalExecute_All 0x%x, ucCalResult_All 0x%x)\n", ucCHIdx, ucRankIdx, ucFreqIdx, ucCalExecute_All, ucCalResult_All));
+
+                for(ucCalIdx =0; ucCalIdx<DRAM_CALIBRATION_MAX; ucCalIdx++)
+                {
+                    if(ucCalIdx==0)
+                    {
+                        ucCalExecute = (U8)p->SWImpCalExecute; //for SW Impedence
+                        ucCalResult = (U8)p->SWImpCalResult; //for SW Impedence
+                    }
+                    else
+                    {
+                        ucCalExecute = (U8)((ucCalExecute_All >>ucCalIdx) & 0x1);
+                        ucCalResult =  (U8)((ucCalResult_All >>ucCalIdx) & 0x1);
+                    }
+
+                    #if PRINT_CALIBRATION_SUMMARY_DETAIL
+                    mcSHOW_DBG_MSG(("%s: ", szCalibStatusName[ucCalIdx]))
+                    if(ucCalExecute==1 && ucCalResult ==1) // excuted and fail
+                    {
+                        u1CalibrationFail =1;
+                        mcSHOW_DBG_MSG(("%s\n", "@_@FAIL@_@"))
+#if defined(SLT)
+                        mcSHOW_ERR_MSG(("[dramc] DRAM_FATAL_ERR_FLAG = 0x00000001, line: %d\n",__LINE__));
+                        while (1);
+#endif
+                    }
+                    else if (ucCalExecute==1 && ucCalResult ==0) // DRAM_OK
+                    {
+                    	mcSHOW_DBG_MSG(("%s\n", "PASS"))
+                    }
+                    else if (ucCalExecute==0 && ucCalResult ==0) // DRAM_FAST K
+                    {
+                    	mcSHOW_DBG_MSG(("%s\n", "FAST K"))
+                    }
+                    else //DRAM_NO K
+                    {
+                    	mcSHOW_DBG_MSG(("%s\n", "NO K"))
+                    }
+
+                    #else
+                    if(ucCalExecute==1 && ucCalResult ==1) // excuted and fail
+                    {
+                        u1CalibrationFail =1;
+                        mcSHOW_DBG_MSG(("%s: %s\n", szCalibStatusName[ucCalIdx],"@_@FAIL@_@"))
+#if defined(SLT)
+                        mcSHOW_ERR_MSG(("[dramc] DRAM_FATAL_ERR_FLAG = 0x00000001, line: %d\n",__LINE__));
+                        while (1);
+#endif
+                    }
+                    #endif
+                }
+
+                if(u1CalibrationFail ==0)
+                {
+                	mcSHOW_DBG_MSG(("All Pass.\n"));
+                }
+                mcSHOW_DBG_MSG(("\n"));
+            }
+        }
+    }
+
+}
+#endif
+
+#ifdef DEVIATION
+static void DeviationAddVrefOffset(U8 k_type, U16 *u2FinalRange, U16 *u2FinalVref, S8 Vref_Offset)
+{
+    S16 temp_vref_value;
+
+    if (k_type==Deviation_RX)
+    {
+        temp_vref_value = *u2FinalVref + Vref_Offset;
+        if (temp_vref_value < 0)
+        {
+            *u2FinalVref = 0;
+        }
+        else if (temp_vref_value < RX_VREF_RANGE_END)
+        {
+            *u2FinalVref = temp_vref_value;
+        }
+        else
+        {
+            *u2FinalVref = RX_VREF_RANGE_END;
+        }
+    }
+    else
+    {
+        temp_vref_value = (*u2FinalRange*30) + *u2FinalVref + Vref_Offset;
+        if (temp_vref_value < 0)
+        {
+            *u2FinalRange = 0;
+            *u2FinalVref = 0;
+        }
+        else if (temp_vref_value <=50)
+        {
+            *u2FinalRange = 0;
+            *u2FinalVref = temp_vref_value;
+        }
+        else if (temp_vref_value < 81)
+        {
+            *u2FinalRange = 1;
+            *u2FinalVref = temp_vref_value - 30;
+        }
+        else
+        {
+            *u2FinalRange = 1;
+            *u2FinalVref = 50;
+        }
+    }
+}
+void SetDeviationVref(DRAMC_CTX_T *p)
+{
+    U8 u1ChannelIdx, u1RankIdx;
+    U16 deviation_Vref, deviation_Vref_Range;
+    U16 temp_Vref;
+    U8 backup_channel, backup_rank;
+
+    backup_channel = vGetPHY2ChannelMapping(p);
+    backup_rank = u1GetRank(p);
+
+    mcSHOW_DBG_MSG2(("[SetDeviationVref]\n"));
+    for(u1ChannelIdx=0; u1ChannelIdx<p->support_channel_num; u1ChannelIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1ChannelIdx);
+        for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++)
+        {
+            vSetRank(p, u1RankIdx);
+            //CBT
+            if (gSetSpecificedVref_Enable[Deviation_CA]==ENABLE && ((p->channel==gSetSpecificedVref_Channel[Deviation_CA] && p->rank==gSetSpecificedVref_Rank[Deviation_CA]) || gSetSpecificedVref_All_ChRk[Deviation_CA]==ENABLE))
+            {
+                deviation_Vref = u1MR12Value[p->channel][p->rank][p->dram_fsp]& 0x3f;
+                deviation_Vref_Range = (u1MR12Value[p->channel][p->rank][p->dram_fsp]>>6)&0x1;
+                DeviationAddVrefOffset(Deviation_CA, &deviation_Vref_Range, &deviation_Vref, gSetSpecificedVref_Vref_Offset[Deviation_CA]);
+                temp_Vref= ((deviation_Vref & 0x3f)|((deviation_Vref_Range & 0x1) <<6));
+                DramcModeRegWriteByRank(p, p->rank, 12,  temp_Vref);
+                u1MR12Value[p->channel][p->rank][p->dram_fsp]=temp_Vref;
+                mcSHOW_DBG_MSG2(("CBT Channel%d, Rank%d,  u1MR12Value = 0x%x\n", p->channel, p->rank, u1MR12Value[p->channel][p->rank][p->dram_fsp]));
+            }
+            //TX
+            if (gSetSpecificedVref_Enable[Deviation_TX]==ENABLE && ((p->channel==gSetSpecificedVref_Channel[Deviation_TX] && p->rank==gSetSpecificedVref_Rank[Deviation_TX]) || gSetSpecificedVref_All_ChRk[Deviation_TX]==ENABLE))
+            {
+                deviation_Vref = u1MR14Value[p->channel][p->rank][p->dram_fsp]& 0x3f;
+                deviation_Vref_Range = (u1MR14Value[p->channel][p->rank][p->dram_fsp]>>6)&0x1;
+                DeviationAddVrefOffset(Deviation_TX, &deviation_Vref_Range, &deviation_Vref, gSetSpecificedVref_Vref_Offset[Deviation_TX]);
+                temp_Vref= ((deviation_Vref & 0x3f)|((deviation_Vref_Range & 0x1) <<6));
+                DramcModeRegWriteByRank(p, p->rank, 14,  temp_Vref);
+                u1MR14Value[p->channel][p->rank][p->dram_fsp]=temp_Vref;
+                mcSHOW_DBG_MSG2(("TX Channel%d, Rank%d,  u1MR14Value = 0x%x\n", p->channel, p->rank, u1MR14Value[p->channel][p->rank][p->dram_fsp]));
+            }
+
+            //RX
+            if (gSetSpecificedVref_Enable[Deviation_RX]==ENABLE && ((p->channel==gSetSpecificedVref_Channel[Deviation_RX] && p->rank==gSetSpecificedVref_Rank[Deviation_RX]) || gSetSpecificedVref_All_ChRk[Deviation_RX]==ENABLE))
+            {
+                    //BYTE_0
+                    deviation_Vref = gFinalRXVrefDQ[p->channel][p->rank][BYTE_0];
+                    DeviationAddVrefOffset(Deviation_RX, NULL, &deviation_Vref, gSetSpecificedVref_Vref_Offset[Deviation_RX]);
+                    gFinalRXVrefDQ[p->channel][p->rank][BYTE_0] = deviation_Vref;
+                    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL),
+                            P_Fld(deviation_Vref, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0) |
+                            P_Fld(deviation_Vref, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0));
+                    mcSHOW_DBG_MSG2(("RX Channel%d, Rank%d,  RX Vref B0 = 0x%x\n", p->channel, p->rank, gFinalRXVrefDQ[p->channel][p->rank][BYTE_0]));
+
+                    //BYTE_1
+                    deviation_Vref = gFinalRXVrefDQ[p->channel][p->rank][BYTE_1];
+                    DeviationAddVrefOffset(Deviation_RX, NULL, &deviation_Vref, gSetSpecificedVref_Vref_Offset[Deviation_RX]);
+                    gFinalRXVrefDQ[p->channel][p->rank][BYTE_1] = deviation_Vref;
+                    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL),
+                            P_Fld(deviation_Vref, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1) |
+                            P_Fld(deviation_Vref, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B1));
+                    mcSHOW_DBG_MSG2(("RX Channel%d, Rank%d,  RX Vref B1 = 0x%x\n", p->channel, p->rank, gFinalRXVrefDQ[p->channel][p->rank][BYTE_1]));
+            }
+        }
+    }
+    vSetRank(p, backup_rank);
+    vSetPHY2ChannelMapping(p, backup_channel);
+}
+#endif
+
+void vInitGlobalVariablesByCondition(DRAMC_CTX_T *p)
+{
+    U8 u1CHIdx, u1RankIdx, u1FSPIdx;
+
+    u1MR01Value[FSP_0] = 0x26;
+    u1MR01Value[FSP_1] = 0x56;
+
+    u1MR03Value[FSP_0] = 0x31; //Set write post-amble as 0.5 tck
+    u1MR03Value[FSP_1] = 0x31; //Set write post-amble as 0.5 tck
+#ifndef ENABLE_POST_PACKAGE_REPAIR
+    u1MR03Value[FSP_0] |= 0x4; //MR3 OP[2]=1 for PPR protection enabled
+    u1MR03Value[FSP_1] |= 0x4; //MR3 OP[2]=1 for PPR protection enabled
+#endif
+#if ENABLE_WRITE_POST_AMBLE_1_POINT_5_TCK
+    u1MR03Value[FSP_1] |= 0x2; //MR3 OP[1]=1 for Set write post-amble as 1.5 tck, support after Eig_er E2
+#endif
+    // @Darren, Follow samsung PPR recommend flow
+    u1MR04Value[RANK_0] = 0x3;
+    u1MR04Value[RANK_1] = 0x3;
+
+    // @Darren, for LP4Y single-end mode
+    u1MR21Value[FSP_0] = 0x0;
+    u1MR21Value[FSP_1] = 0x0;
+    u1MR51Value[FSP_0] = 0x0;
+    u1MR51Value[FSP_1] = 0x0;
+
+    for (u1FSPIdx = 0; u1FSPIdx < p->support_fsp_num; u1FSPIdx++)
+    {
+        u1MR02Value[u1FSPIdx] = 0x1a;
+    }
+
+    for (u1CHIdx = 0; u1CHIdx < CHANNEL_NUM; u1CHIdx++)
+        for (u1RankIdx = 0; u1RankIdx < RANK_MAX; u1RankIdx++)
+            for (u1FSPIdx = 0; u1FSPIdx < p->support_fsp_num; u1FSPIdx++)
+            {
+                // MR14 default value, LP4 default 0x4d, LP4X 0x5d
+                u1MR14Value[u1CHIdx][u1RankIdx][u1FSPIdx] = (u1FSPIdx == FSP_0)? 0x5d: 0x18;  //0x18: customize for Eig_er
+                #if FSP1_CLKCA_TERM
+                u1MR12Value[u1CHIdx][u1RankIdx][u1FSPIdx] = (u1FSPIdx == FSP_0)? 0x5d: 0x1b;
+                #else
+                u1MR12Value[u1CHIdx][u1RankIdx][u1FSPIdx] = 0x5d;
+                #endif
+                #if MRW_CHECK_ONLY
+                for (u1MRIdx = 0; u1MRIdx < MR_NUM; u1MRIdx++)
+                    u2MRRecord[u1CHIdx][u1RankIdx][u1FSPIdx][u1MRIdx] = 0xffff;
+                #endif
+            }
+
+    memset(gu2RX_DQS_Duty_Offset, 0, sizeof(gu2RX_DQS_Duty_Offset));
+}
+
+const U8 uiLPDDR4_CA_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][6] =
+{
+    {
+        // for EMCP
+        //CH-A
+        {
+			3, 1, 0, 5, 7, 4
+        },
+
+    #if (CHANNEL_NUM>1)
+        //CH-B
+        {
+			3, 2, 4, 0, 5, 1
+        },
+    #endif
+    #if (CHANNEL_NUM>2)
+        //CH-C
+        {
+			3, 1, 0, 5, 7, 4
+        },
+        //CH-D
+        {
+			3, 2, 4, 0, 5, 1
+        },
+    #endif
+    },
+    {
+    // for DSC_2CH, HFID RESERVED
+        //CH-A
+        {
+            5, 2, 1, 3, 4, 0
+        },
+
+    #if (CHANNEL_NUM>1)
+        //CH-B
+        {
+            0, 2, 1, 3, 4, 5
+        },
+    #endif
+    #if (CHANNEL_NUM>2)
+        //CH-C
+        {
+            0, 1, 2, 3, 4, 5
+        },
+        //CH-D
+        {
+            0, 1, 2, 3, 4, 5
+        },
+    #endif
+    },
+    {
+        // for MCP
+        //CH-A
+        {
+            5, 4, 3, 2, 1, 0
+        },
+
+    #if (CHANNEL_NUM>1)
+        //CH-B
+        {
+            4, 5, 2, 0, 3, 1
+        },
+    #endif
+    #if (CHANNEL_NUM>2)
+        //CH-C
+        {
+            5, 4, 0, 2, 1, 3
+        },
+        //CH-D
+        {
+            3, 5, 2, 4, 0, 1
+        },
+    #endif
+    },
+    {
+    // for DSC_2CH, HFID RESERVED
+        //CH-A
+        {
+            3, 0, 2, 4, 1, 5
+        },
+
+    #if (CHANNEL_NUM>1)
+        //CH-B
+        {
+            4, 1, 0, 2, 3, 5
+        },
+    #endif
+    #if (CHANNEL_NUM>2)
+        //CH-C
+        {
+            5, 0, 4, 3, 1, 2
+        },
+        //CH-D
+        {
+            2, 5, 3, 0, 4, 1
+        },
+    #endif
+    },
+};
+
+//O1 DRAM->APHY
+const U8 uiLPDDR4_O1_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] =
+{
+    {
+        // for EMCP
+        //CH-A
+        {
+            0, 1, 2, 3, 5, 7, 6, 4,
+            9, 8, 13, 15, 10, 14, 11, 12
+        },
+        #if (CHANNEL_NUM>1)
+        //CH-B
+        {
+            0, 1, 5, 4, 3, 7, 6, 2,
+            9, 8, 13, 14, 10, 15, 11, 12
+        },
+        #endif
+        #if (CHANNEL_NUM>2)
+        //CH-C
+        {
+            0, 1, 2, 3, 5, 7, 6, 4,
+            9, 8, 13, 15, 10, 14, 11, 12
+        },
+        //CH-D
+        {
+			0, 1, 5, 4, 3, 7, 6, 2,
+			9, 8, 13, 14, 10, 15, 11, 12
+        },
+        #endif
+    },
+    {
+    // for DSC_2CH, HFID RESERVED
+        //CH-A
+        {
+            0, 1, 4, 3, 2, 5, 7, 6,
+            9, 8, 10, 11, 14, 13, 15, 12
+        },
+        #if (CHANNEL_NUM>1)
+        //CH-B
+        {
+            0, 1, 2, 4, 5, 3, 7, 6,
+            8, 9, 10, 11, 15, 14, 13, 12
+        },
+        #endif
+        #if (CHANNEL_NUM>2)
+        //CH-C
+        {
+            0, 1, 2, 3, 4, 5, 6, 7,
+            8, 9, 10, 11, 12, 13, 14, 15
+        },
+        //CH-D
+        {
+            0, 1, 2, 3, 4, 5, 6, 7,
+            8, 9, 10, 11, 12, 13, 14, 15
+        },
+        #endif
+    },
+    {
+        // for MCP
+        //CH-A
+        {
+            0, 1, 3, 6, 4, 7, 2, 5,
+            8, 9, 10, 13, 11, 12, 15, 14
+        },
+        #if (CHANNEL_NUM>1)
+        //CH-B
+        {
+            0, 1, 4, 7, 3, 5, 6, 2,
+            9, 8, 10, 12, 11, 14, 13, 15
+        },
+        #endif
+        #if (CHANNEL_NUM>2)
+        //CH-C
+        {
+            1, 0, 3, 2, 4, 7, 6, 5,
+            8, 9, 10, 14, 11, 15, 13, 12
+        },
+        //CH-D
+        {
+            0, 1, 4, 7, 3, 5, 6, 2,
+            9, 8, 10, 12, 11, 14, 13, 15
+        },
+        #endif
+    },
+    {
+    // for DSC_180
+        //CH-A
+        {
+            9, 8, 11, 10, 14, 15, 13, 12,
+            0, 1, 7, 6, 4, 5, 2, 3
+        },
+        #if (CHANNEL_NUM>1)
+        //CH-B
+        {
+            8, 9, 11, 10, 12, 14, 13, 15,
+            1, 0, 5, 6, 3, 2, 7, 4
+        },
+        #endif
+        #if (CHANNEL_NUM>2)
+        //CH-C
+        {
+            0, 1, 7, 6, 4, 5, 2, 3,
+            9, 8, 11, 10, 14, 15, 13, 12
+        },
+        //CH-D
+        {
+            1, 0, 5, 6, 3, 2, 7, 4,
+            8, 9, 11, 10, 12, 14, 13, 15
+        },
+        #endif
+    },
+};
+
+//CA DRAM->APHY
+#if (CA_PER_BIT_DELAY_CELL || PINMUX_AUTO_TEST_PER_BIT_CA)
+#if __LP5_COMBO__
+const U8 uiLPDDR5_CA_Mapping_POP[CHANNEL_NUM][7] =
+{
+    //CH-A
+    {
+        0, 1, 2, 3, 4, 5, 6
+    },
+
+#if (CHANNEL_NUM>1)
+    //CH-B
+    {
+        0, 4, 2, 3, 1, 5, 6
+    }
+#endif
+};
+#endif
+
+U8 uiLPDDR4_CA_Mapping_POP[CHANNEL_NUM][6] =
+{
+    //CH-A
+    {
+		2, 1, 0, 5, 3, 4
+    },
+
+#if (CHANNEL_NUM>1)
+    //CH-B
+    {
+	3, 5, 1, 0, 2, 4
+    },
+#endif
+#if (CHANNEL_NUM>2)
+    //CH-C
+    {
+	2, 1, 0, 5, 3, 4
+    },
+    //CH-D
+    {
+	3, 5, 1, 0, 2, 4
+    },
+#endif
+};
+#endif
+
+#if (__LP5_COMBO__)
+const U8 uiLPDDR5_O1_Mapping_POP[CHANNEL_NUM][16] =
+{
+    {
+        8, 9, 10, 11, 12, 15, 14, 13,
+        0, 1, 2, 3, 4, 7, 6, 5,
+    },
+
+    #if (CHANNEL_NUM>1)
+    {
+        8, 9, 10, 11, 12, 15, 14, 13,
+        0, 1, 2, 3, 4, 7, 6, 5,
+    },
+    #endif
+};
+#endif
+
+//O1 DRAM->APHY
+U8 uiLPDDR4_O1_Mapping_POP[CHANNEL_NUM][16] =
+{
+    //CH-A
+    {
+	0, 1, 2, 3, 5, 7, 6, 4,
+	9, 8, 13, 15, 10, 14, 11, 12
+    },
+    #if (CHANNEL_NUM>1)
+    //CH-B
+    {
+	0, 1, 5, 4, 3, 7, 6, 2,
+	9, 8, 13, 14, 10, 15, 11, 12
+    },
+    #endif
+    #if (CHANNEL_NUM>2)
+    //CH-C
+    {
+	0, 1, 2, 3, 5, 7, 6, 4,
+	9, 8, 13, 15, 10, 14, 11, 12
+    },
+    //CH-D
+    {
+	0, 1, 5, 4, 3, 7, 6, 2,
+	9, 8, 13, 14, 10, 15, 11, 12
+    },
+    #endif
+};
+
+#if 0
+static DRAM_STATUS_T DramcMRInit_LP4(DRAMC_CTX_T *p)
+{
+    mcSHOW_DBG_MSG2(("=== LP4 MR Init ===\n"));
+
+    U32 u4RankIdx;
+    U8 u1MRFsp = FSP_0;
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+    // LP4_HIGHEST_FREQ == 1866
+    /* Set MR01 OP[6:4] to 110B = 6 */
+    u1MR01Value[FSP_0] |= (0x6 << 4);
+    u1MR01Value[FSP_1] |= (0x6 << 4);
+    mcSHOW_DBG_MSG2(("(FSP0)MR#1 = 0x%x\n", u1MR01Value[FSP_0]));
+
+//    for (u1ChannelIdx = 0; u1ChannelIdx < (p->support_channel_num); u1ChannelIdx++)
+    {
+        for (u4RankIdx = 0; u4RankIdx < (U32)(p->support_rank_num); u4RankIdx++)
+        {
+            // FSP_0
+            u1MRFsp = FSP_0;
+//            DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_WR, TO_MR);
+
+            //MR2 set Read/Write Latency
+            if ((p->frequency == 800) || (p->frequency == 600) || (p->frequency == 400)) // DDR1600, DDR1200, DDR800
+            {
+                u1MR02Value[u1MRFsp] = 0x12;
+            }
+            else if (p->frequency <= 1200) // DDR2280, DDR2400 (DDR2667 uses FSP_1)
+            {
+                u1MR02Value[u1MRFsp] = 0x24;
+            }
+            else if (p->frequency <= 1333)
+            {
+                u1MR02Value[u1MRFsp] = 0x24;
+            }
+            else if (p->frequency <= 1600)
+            {
+                u1MR02Value[u1MRFsp] = 0x2d;
+            }
+            else if (p->frequency <= 1866)
+            {
+                u1MR02Value[u1MRFsp] = 0x36;
+            }
+            else // if (p->frequency > 1866)
+            {
+                u1MR02Value[u1MRFsp] = 0x3f;
+            }
+            DramcModeRegWriteByRank(p, u4RankIdx, 2, u1MR02Value[u1MRFsp]);
+            mcSHOW_DBG_MSG2(("(FSP0)MR#2 = 0x%x\n", u1MR02Value[u1MRFsp]));
+
+            // FSP_1
+            u1MRFsp = FSP_1;
+
+            //MR2 set Read/Write Latency
+            if ((p->frequency == 800) || (p->frequency == 600) || (p->frequency == 400)) // DDR1600, DDR1200, DDR800
+            {
+                u1MR02Value[u1MRFsp] = 0x12;
+            }
+            else if (p->frequency <= 1200) // DDR2280, DDR2400 (DDR2667 uses FSP_1)
+            {
+                u1MR02Value[u1MRFsp] = 0x24;
+            }
+            else if (p->frequency <= 1333)
+            {
+                u1MR02Value[u1MRFsp] = 0x24;
+            }
+            else if (p->frequency <= 1600)
+            {
+                u1MR02Value[u1MRFsp] = 0x2d;
+            }
+            else if (p->frequency <= 1866)
+            {
+                u1MR02Value[u1MRFsp] = 0x36;
+            }
+            else // if (p->frequency > 1866)
+            {
+                u1MR02Value[u1MRFsp] = 0x3f;
+            }
+            DramcModeRegWriteByRank(p, u4RankIdx, 2, u1MR02Value[u1MRFsp]);
+            mcSHOW_DBG_MSG2(("(FSP1)MR#2 = 0x%x\n", u1MR02Value[u1MRFsp]));
+
+            // To do...
+
+#if FOR_DV_SIMULATION_USED == 1
+           cal_sv_rand_args_t *psra = get_psra(); ;
+
+           if (psra) {
+               u1MR02Value[p->dram_fsp] = psra->mr2_value & 0x7F;
+               DramcModeRegWriteByRank(p, p->rank, 2, u1MR02Value[p->dram_fsp]);
+           }
+#endif /* FOR_DV_SIMULATION_USED */
+        }
+    }
+
+    return DRAM_OK;
+}
+#endif
+#if __LP5_COMBO__
+DRAM_STATUS_T DramcMRInit_LP5(DRAMC_CTX_T *p)
+{
+    mcSHOW_DBG_MSG2(("=== LP5 MR Init ===\n"));
+
+    U32 u4RankIdx;
+    U8 u1MRFsp = FSP_0;
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+//    for (u1ChannelIdx = 0; u1ChannelIdx < (p->support_channel_num); u1ChannelIdx++)
+    {
+        for (u4RankIdx = 0; u4RankIdx < (U32)(p->support_rank_num); u4RankIdx++)
+        {
+            // FSP_0
+            u1MRFsp = FSP_0;
+
+//            if ((p->frequency == 2133) || (p->frequency == 3200))
+            // DV SIM fix DDR6400 <=> Freq 3200
+            {
+               // u1MR18Value[u1MRFsp] = 0x03;
+               // u1MR20Value[u1MRFsp] = 0x02;
+            }
+            mcSHOW_DBG_MSG2(("(FSP0)MR#18 = 0x%x\n", u1MR18Value[u1MRFsp]));
+            mcSHOW_DBG_MSG2(("(FSP0)MR#20 = 0x%x\n", u1MR20Value[u1MRFsp]));
+
+            // FSP_1
+            u1MRFsp = FSP_1;
+            // To do...
+
+
+        }
+    }
+
+#if FOR_DV_SIMULATION_USED == 1
+    cal_sv_rand_args_t *psra = get_psra();
+
+    if (psra) {
+        u1MR18Value[p->dram_fsp] = psra->mr18_value;
+        u1MR20Value[p->dram_fsp] = psra->mr20_value;
+    }
+#endif
+
+    return DRAM_OK;
+}
+#endif
+
+#ifdef IMPEDANCE_TRACKING_ENABLE
+static void ImpedanceTracking_DisImpHw_Setting(DRAMC_CTX_T *p, U8 u1DisImpHw)
+{
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1, P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_ODTN_UPD_DIS)
+                                                                    | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVN_UPD_DIS)
+                                                                    | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVP_UPD_DIS)
+                                                                    | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS)
+                                                                    | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS)
+                                                                    | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS)
+                                                                    | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_ODTN_UPD_DIS)
+                                                                    | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVN_UPD_DIS)
+                                                                    | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVP_UPD_DIS)
+                                                                    | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_ODTN_UPD_DIS)
+                                                                    | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVN_UPD_DIS)
+                                                                    | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVP_UPD_DIS)
+                                                                    | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS)
+                                                                    | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS)
+                                                                    | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS));
+
+#if (fcFOR_CHIP_ID == fc8195)
+    //WCK_ODTN_UPD_DIS is used as the swith of mux for B1/CA swap here.
+        if (p->DRAMPinmux == PINMUX_DSC){
+            vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1, 1, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS);
+        }else{
+            vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1, 0, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS);
+        }
+#endif
+
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_IMPCAL1, (u1DisImpHw? 0x0:0x40), SHU_MISC_IMPCAL1_IMPCALCNT);
+    vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(u1DisImpHw, SHU_MISC_DRVING1_DIS_IMPCAL_HW)
+                                                   | P_Fld(u1DisImpHw, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK));
+
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_DRVING2, u1DisImpHw, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN);
+    vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD12, u1DisImpHw, SHU_CA_CMD12_RG_RIMP_UNTERM_EN);
+
+}
+#endif
+
+void vBeforeCalibration(DRAMC_CTX_T *p)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+#if (__LP5_COMBO__ == TRUE)
+    if (TRUE == is_lp5_family(p))
+    {
+        DramcMRInit_LP5(p);
+    }
+    else
+#endif
+    {
+        //DramcMRInit_LP4(p);
+    }
+
+#if SIMULATION_RX_DVS || ENABLE_RX_TRACKING
+    DramcRxInputDelayTrackingInit_byFreq(p);
+#endif
+
+    DramcHWGatingOnOff(p, 0); //disable gating tracking
+
+    CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ALL_CHANNEL); //Let CLK always on during calibration
+
+#if ENABLE_TMRRI_NEW_MODE
+    SetCKE2RankIndependent(p); //CKE should be controlled independently
+#endif
+
+    //WDBI-OFF
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_TX_SET0, 0x0, SHU_TX_SET0_DBIWR);
+
+#ifdef IMPEDANCE_TRACKING_ENABLE
+    // set correct setting to control IMPCAL HW Tracking in shuffle RG
+    // if p->freq >= 1333, enable IMP HW tracking(SHU_DRVING1_DIS_IMPCAL_HW=0), else SHU_DRVING1_DIS_IMPCAL_HW = 1
+    U8 u1DisImpHw;
+    U32 u4TermFreq, u4WbrBackup;
+
+#if (__LP5_COMBO__ == TRUE)
+    if (TRUE == is_lp5_family(p))
+        u4TermFreq = LP5_MRFSP_TERM_FREQ;
+    else
+#endif
+        u4TermFreq = LP4_MRFSP_TERM_FREQ;
+
+    u1DisImpHw = (p->frequency >= u4TermFreq)? 0: 1;
+
+    u4WbrBackup = GetDramcBroadcast();
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+    ImpedanceTracking_DisImpHw_Setting(p, u1DisImpHw);
+    DramcBroadcastOnOff(u4WbrBackup);
+
+#endif
+
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CLK_CTRL, P_Fld(0, MISC_CLK_CTRL_DVFS_CLK_MEM_SEL)
+                                                    | P_Fld(0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN));
+
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_ZQ_SET0,
+            P_Fld(0x1ff, SHU_ZQ_SET0_ZQCSCNT) | //Every refresh number to issue ZQCS commands, only for DDR3/LPDDR2/LPDDR3/LPDDR4
+            P_Fld(0x1b, SHU_ZQ_SET0_TZQLAT));
+
+    if (p->support_channel_num == CHANNEL_SINGLE)
+    {
+        //single channel, ZQCSDUAL=0, ZQCSMASK=0
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ZQ_SET0), P_Fld(0, ZQ_SET0_ZQCSDUAL) | P_Fld(0x0, ZQ_SET0_ZQCSMASK));
+    }
+    else if (p->support_channel_num == CHANNEL_DUAL)
+    {
+        // HW ZQ command is channel interleaving since 2 channel share the same ZQ pin.
+        #ifdef ZQCS_ENABLE_LP4
+        // dual channel, ZQCSDUAL =1, and CHA ZQCSMASK=0, CHB ZQCSMASK=1
+
+        vIO32WriteFldMulti_All(DRAMC_REG_ZQ_SET0, P_Fld(1, ZQ_SET0_ZQCSDUAL) |
+                                               P_Fld(0, ZQ_SET0_ZQCSMASK_OPT) |
+                                               P_Fld(0, ZQ_SET0_ZQMASK_CGAR) |
+                                               P_Fld(0, ZQ_SET0_ZQCS_MASK_SEL_CGAR));
+
+        // DRAMC CHA(CHN0):ZQCSMASK=1, DRAMC CHB(CHN1):ZQCSMASK=0.
+        // ZQCSMASK setting: (Ch A, Ch B) = (1,0) or (0,1)
+        // if CHA.ZQCSMASK=1, and then set CHA.ZQCALDISB=1 first, else set CHB.ZQCALDISB=1 first
+        vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_A << POS_BANK_NUM), 1, ZQ_SET0_ZQCSMASK);
+        vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + SHIFT_TO_CHB_ADDR, 0, ZQ_SET0_ZQCSMASK);
+
+        // DRAMC CHA(CHN0):ZQ_SET0_ZQCS_MASK_SEL=0, DRAMC CHB(CHN1):ZQ_SET0_ZQCS_MASK_SEL=0.
+        vIO32WriteFldAlign_All(DRAMC_REG_ZQ_SET0, 0, ZQ_SET0_ZQCS_MASK_SEL);
+        #endif
+    }
+#if (CHANNEL_NUM > 2)
+    else if (p->support_channel_num == CHANNEL_FOURTH)
+    {
+        // HW ZQ command is channel interleaving since 2 channel share the same ZQ pin.
+        #ifdef ZQCS_ENABLE_LP4
+        // dual channel, ZQCSDUAL =1, and CHA ZQCSMASK=0, CHB ZQCSMASK=1
+
+        vIO32WriteFldMulti_All(DRAMC_REG_ZQ_SET0, P_Fld(1, ZQ_SET0_ZQCSDUAL) |
+                                               P_Fld(0, ZQ_SET0_ZQCALL) |
+                                               P_Fld(0, ZQ_SET0_ZQ_SRF_OPT) |
+                                               P_Fld(0, ZQ_SET0_ZQCSMASK_OPT) |
+                                               P_Fld(0, ZQ_SET0_ZQMASK_CGAR) |
+                                               P_Fld(0, ZQ_SET0_ZQCS_MASK_SEL_CGAR));
+
+        // DRAMC CHA(CHN0):ZQCSMASK=1, DRAMC CHB(CHN1):ZQCSMASK=0.
+        // ZQCSMASK setting: (Ch A, Ch C) = (1,0) or (0,1), (Ch B, Ch D) = (1,0) or (0,1)
+        // if CHA.ZQCSMASK=1, and then set CHA.ZQCALDISB=1 first, else set CHB.ZQCALDISB=1 first
+    #if fcFOR_CHIP_ID == fcPetrus
+        vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_A << POS_BANK_NUM), 1, ZQ_SET0_ZQCSMASK);
+        vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_B << POS_BANK_NUM), 0, ZQ_SET0_ZQCSMASK);
+        vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_C << POS_BANK_NUM), 0, ZQ_SET0_ZQCSMASK);
+        vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_D << POS_BANK_NUM), 1, ZQ_SET0_ZQCSMASK);
+    #elif (fcFOR_CHIP_ID == fc8195)
+        vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_A << POS_BANK_NUM), 1, ZQ_SET0_ZQCSMASK);
+        vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_B << POS_BANK_NUM), 0, ZQ_SET0_ZQCSMASK);
+        vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_C << POS_BANK_NUM), 1, ZQ_SET0_ZQCSMASK);
+        vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_D << POS_BANK_NUM), 0, ZQ_SET0_ZQCSMASK);
+    #endif
+
+        // DRAMC CHA(CHN0):ZQ_SET0_ZQCS_MASK_SEL=0, DRAMC CHB(CHN1):ZQ_SET0_ZQCS_MASK_SEL=0.
+        vIO32WriteFldAlign_All(DRAMC_REG_ZQ_SET0, 0, ZQ_SET0_ZQCS_MASK_SEL);
+        #endif
+    }
+#endif
+
+    // Set 0 to be able to adjust TX DQS/DQ/DQM PI during calibration, for new cross rank mode.
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ2, 0, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0);
+    if (!isLP4_DSC)
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ2, 0, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1);
+    else
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD2, 0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA);
+
+#if ENABLE_PA_IMPRO_FOR_TX_AUTOK
+    vIO32WriteFldAlign_All(DRAMC_REG_DCM_SUB_CTRL, 0x0, DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK);
+#endif
+    // ARPI_DQ SW mode mux, TX DQ use 1: PHY Reg 0: DRAMC Reg
+    #if ENABLE_PA_IMPRO_FOR_TX_TRACKING
+    vIO32WriteFldAlign_All(DRAMC_REG_DCM_SUB_CTRL, 0, DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING);
+    #endif
+    //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL1, 1, MISC_CTRL1_R_DMARPIDQ_SW); @Darren, remove to LP4_UpdateInitialSettings
+    //Disable HW MR18/19 to prevent fail case when doing SW MR18/19 in DQSOSCAuto
+    vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS);
+
+    vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0x1, REFCTRL0_REFDIS); //disable refresh
+
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_MATYPE, u1MaType, SHU_MATYPE_MATYPE);
+
+    TX_Path_Algorithm(p);
+}
+
+void vAfterCalibration(DRAMC_CTX_T *p)
+{
+
+#if ENABLE_READ_DBI
+    EnableDRAMModeRegReadDBIAfterCalibration(p);
+#endif
+
+#if ENABLE_WRITE_DBI
+    EnableDRAMModeRegWriteDBIAfterCalibration(p);
+#endif
+
+    SetMr13VrcgToNormalOperation(p);// Set VRCG{MR13[3]} to 0
+
+
+    CKEFixOnOff(p, TO_ALL_RANK, CKE_DYNAMIC, TO_ALL_CHANNEL); //After CKE FIX on/off, CKE should be returned to dynamic (control by HW)
+
+    vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, p->support_rank_num, DUMMY_RD_RANK_NUM);
+
+#if ENABLE_PER_BANK_REFRESH
+    DramcSetPerBankRefreshMode(p);
+#endif
+
+#if FOR_DV_SIMULATION_USED == 1
+    cal_sv_rand_args_t *psra = get_psra();
+
+    if (psra) {
+        u1MR03Value[p->dram_fsp] = psra->mr3_value;
+    }
+#endif
+
+    //@Darren, KaiHsin sync MP setting
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL7, 0, MISC_CG_CTRL7_CK_BFE_DCM_EN);
+
+    /* TESTAGENT2 for @Chris sync MP settings*/
+    vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL); // Rank selection is controlled by Test Agent
+    vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A2, 0x20, TEST2_A2_TEST2_OFF); //@Chris, MP setting for runtime TA2 Length
+
+    //@Darren, CW sync MP setting
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DUTYSCAN1, 0, MISC_DUTYSCAN1_DQSERRCNT_DIS);
+
+    //@Darren, HJ sync MP setting
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL1, 0, MISC_CTRL1_R_DMSTBENCMP_RK_OPT);
+}
+
+static void O1PathOnOff(DRAMC_CTX_T *p, U8 u1OnOff)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+    #if 0//O1_SETTING_RESTORE
+    const U32 u4O1RegBackupAddress[] =
+    {
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5))
+    };
+    #endif
+
+    U8 u1VrefSel;
+
+    if (u1OnOff == ON)
+    {
+        // These RG will be restored when leaving each calibration flow
+        // -------------------------------------------------------
+        // VREF_UNTERM_EN
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF), 1, SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0);
+        if (!isLP4_DSC)
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF), 1, SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1);
+        else
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_VREF), 1, SHU_CA_VREF_RG_RX_ARCA_VREF_UNTERM_EN_CA);
+
+        #if (__LP5_COMBO__ == TRUE)
+        if (p->dram_type==TYPE_LPDDR5)
+            u1VrefSel = 0x37;//unterm LP5
+        else
+        #endif
+            u1VrefSel = 0x37;//unterm LP4
+
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL),
+                    P_Fld(u1VrefSel, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0) |
+                    P_Fld(u1VrefSel, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0));
+        if (!isLP4_DSC)
+        {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL),
+                    P_Fld(u1VrefSel, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1) |
+                    P_Fld(u1VrefSel, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B1));
+        }
+        else
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_PHY_VREF_SEL),
+                        P_Fld(u1VrefSel, SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_LB) |
+                        P_Fld(u1VrefSel, SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_UB));
+        }
+    }
+
+    // DQ_O1 enable/release
+    // -------------------------------------------------------
+    // Actually this RG naming is O1_EN in APHY
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), u1OnOff, B0_DQ6_RG_RX_ARDQ_O1_SEL_B0);
+    if (!isLP4_DSC)
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), u1OnOff, B1_DQ6_RG_RX_ARDQ_O1_SEL_B1);
+    else
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6), u1OnOff, CA_CMD6_RG_RX_ARCMD_O1_SEL);
+
+
+    // DQ_IN_BUFF_EN
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3),
+                        P_Fld(u1OnOff, B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0) |
+                        P_Fld(u1OnOff, B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0));
+    if (!isLP4_DSC)
+    {
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3),
+                        P_Fld(u1OnOff, B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1) |
+                        P_Fld(u1OnOff, B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD3),
+                            P_Fld(u1OnOff, CA_CMD3_RG_RX_ARCMD_IN_BUFF_EN) |
+                            P_Fld(u1OnOff, CA_CMD3_RG_RX_ARCLK_IN_BUFF_EN));
+    }
+
+    // DQ_BUFF_EN_SEL
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), u1OnOff, B0_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B0);
+    if (!isLP4_DSC)
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3), u1OnOff, B1_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B1);
+    else
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3), u1OnOff, CA_PHY3_RG_RX_ARCA_BUFF_EN_SEL_CA);
+
+    // Gating always ON
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL),(u1OnOff << 1) | u1OnOff, MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN);
+
+    mcDELAY_US(1);
+}
+
+static inline u8 get_ca_pi_per_ui(DRAMC_CTX_T *p)
+{
+#if __LP5_COMBO__
+    if (p->freq_sel == LP5_DDR4266)
+        return 64;
+    else
+#endif
+        return 32;
+}
+
+static int get_capi_max(DRAMC_CTX_T *p)
+{
+    if (u1IsPhaseMode(p) == TRUE)
+    {
+        return 32;
+    }
+
+    return 64;
+}
+#if 0
+static u8 get_autok_sweep_max_cnt(u8 lenpi, u8 respi)
+{
+    u8 max;
+
+    lenpi += 1;
+    max = 64 / (1 << (respi & 0x3));
+    return lenpi > max? max: lenpi;
+}
+
+/*
+ * cbt_wlev_train_autok -- ca/cs/dqs autok
+ * @mode: ca or cs select, 0 for ca, 1 for cs
+ * @initpi: init pi select
+ * @lenpi: sweep how many pi step, 0 ~ 63
+ * @respi: sweep pi resolution, 00 for 1 pi, 01 for 2 pi, 10 for 4 pi, 11 for 8 pi
+ *
+ * autok result store to @cmp0 and @cmp1.
+ */
+
+static int cbt_wlev_train_autok(DRAMC_CTX_T *p, ATUOK_MODE_T autok_mode,
+        u8 initpi, u8 lenpi, u8 respi,
+        u32 *cmp0_array,
+        u32 *cmp1_array,
+        u8 pin_num)
+{
+    u8 sweep_max_cnt, i;
+    u32 cnt, ready;
+
+    /*
+    * it's takes 3.6us for one step.
+    * max times is 64, about 3.6 * 64 = 231us
+    */
+    cnt = TIME_OUT_CNT * 3;
+
+    switch (autok_mode){
+    case AUTOK_CS:
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0),
+                P_Fld(0, CBT_WLEV_ATK_CTRL0_ARPICS_SW));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL1),
+                P_Fld(0, CBT_WLEV_ATK_CTRL1_UICS_SW));
+        break;
+    case AUTOK_CA:
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0),
+                P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
+                P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CS));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0),
+                P_Fld(0, CBT_WLEV_ATK_CTRL0_ARPICA_SW));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL1),
+                P_Fld(0, CBT_WLEV_ATK_CTRL1_UICA_SW));
+        break;
+    case AUTOK_DQS:
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0),
+                P_Fld(0, CBT_WLEV_ATK_CTRL0_ARPIDQS_SW));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL1),
+                P_Fld(0, CBT_WLEV_ATK_CTRL1_UIDQS_SW));
+        break;
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL1),
+            (get_ca_pi_per_ui(p) == 64) ? 0x1 : 0x0, CBT_WLEV_ATK_CTRL1_CBT_ATK_CA1UI64PI);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0),
+            0x3, CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_INTV);
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0),
+            P_Fld(lenpi, CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_LENPI) |
+            P_Fld(respi, CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_RESPI) |
+            P_Fld(initpi, CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_INITPI));
+
+    switch (autok_mode){
+    case AUTOK_CS:
+        if (p->new_cbt_mode)
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0),
+                    P_Fld(1, CBT_WLEV_ATK_CTRL0_CATRAIN_ATKEN));
+        }
+        else
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0),
+                    P_Fld(1, CBT_WLEV_ATK_CTRL0_CSTRAIN_ATKEN));
+        }
+        break;
+    case AUTOK_CA:
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0),
+                P_Fld(1, CBT_WLEV_ATK_CTRL0_CATRAIN_ATKEN));
+        break;
+    case AUTOK_DQS:
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0),
+                P_Fld(1, CBT_WLEV_ATK_CTRL0_WLEV_ATKEN));
+        break;
+    }
+
+    do {
+        ready = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS),
+                CBT_WLEV_STATUS_CBT_WLEV_ATK_RESPONSE);
+        cnt--;
+        mcDELAY_US(1);
+    }
+    #if FOR_DV_SIMULATION_USED
+    while (ready == 0);
+    #else
+    while ((ready == 0) && (cnt > 0));
+    #endif
+
+    if (cnt == 0){
+        mcSHOW_ERR_MSG(("[cbt_autok] Resp fail (time out) for "))
+        switch (autok_mode) {
+        case AUTOK_CS:
+            mcSHOW_ERR_MSG(("CSTrain\n"));
+            break;
+        case AUTOK_CA:
+            mcSHOW_ERR_MSG(("CATrain\n"));
+            break;
+        case AUTOK_DQS:
+            mcSHOW_ERR_MSG(("DQSTrain\n"));
+            break;
+        }
+    }
+
+    sweep_max_cnt = get_autok_sweep_max_cnt(lenpi, respi);
+    for (i = 0; i < pin_num; i++) {
+        cmp0_array[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_RESULT0 + i * 8));
+
+        if (sweep_max_cnt > 32) {
+            cmp1_array[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_RESULT1 + i * 8));
+        } else {
+            cmp1_array[i] = 0xFFFFFFFF;
+        }
+    }
+
+    for (i = 0; i < pin_num; i++) {
+        mcSHOW_DBG_MSG4(("cmp0[%d]=0x%x, cmp1[%d]=0x%x\n",
+                i, cmp0_array[i],
+                i, cmp1_array[i]));
+    }
+
+    switch (autok_mode){
+    case AUTOK_CS:
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0),
+                P_Fld(1, CBT_WLEV_ATK_CTRL0_ARPICS_SW));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL1),
+                P_Fld(0x3, CBT_WLEV_ATK_CTRL1_UICS_SW));
+        if (p->new_cbt_mode)
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0),
+                    P_Fld(0, CBT_WLEV_ATK_CTRL0_CATRAIN_ATKEN));
+        }
+        else
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0),
+                    P_Fld(0, CBT_WLEV_ATK_CTRL0_CSTRAIN_ATKEN));
+        }
+        break;
+    case AUTOK_CA:
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0),
+                P_Fld(1, CBT_WLEV_ATK_CTRL0_ARPICA_SW));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL1),
+                P_Fld(0x7F, CBT_WLEV_ATK_CTRL1_UICA_SW));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0),
+                P_Fld(0, CBT_WLEV_ATK_CTRL0_CATRAIN_ATKEN));
+        break;
+    case AUTOK_DQS:
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0),
+                P_Fld(1, CBT_WLEV_ATK_CTRL0_ARPIDQS_SW));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL1),
+                P_Fld(0xF, CBT_WLEV_ATK_CTRL1_UIDQS_SW));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0),
+                P_Fld(0, CBT_WLEV_ATK_CTRL0_WLEV_ATKEN));
+        break;
+    }
+
+    return 0;
+}
+#endif
+/*
+ * set_cbt_intv -- set interval related rg according to speed.
+ *
+ * TODO, move these to ACTimingTable ????!!!
+ */
+
+struct cbt_intv {
+    DRAM_PLL_FREQ_SEL_T freq_sel;
+    DIV_MODE_T divmode;
+    u8 tcmdo1lat;
+    u8 catrain_intv;
+    u8 new_cbt_pat_intv;
+    u8 wlev_dqspat_lat;
+};
+
+static void set_cbt_intv_rg(DRAMC_CTX_T *p, struct cbt_intv *pintv)
+{
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1),
+        P_Fld(pintv->tcmdo1lat, CBT_WLEV_CTRL1_TCMDO1LAT) |
+        P_Fld(pintv->catrain_intv, CBT_WLEV_CTRL1_CATRAIN_INTV));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5),
+        P_Fld(pintv->new_cbt_pat_intv, CBT_WLEV_CTRL5_NEW_CBT_PAT_INTV));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
+        P_Fld(pintv->wlev_dqspat_lat, CBT_WLEV_CTRL0_WLEV_DQSPAT_LAT));
+}
+
+static struct cbt_intv *lookup_cbt_intv(struct cbt_intv *intv, int cnt,
+        DRAM_PLL_FREQ_SEL_T fsel, DIV_MODE_T dmode)
+{
+    struct cbt_intv *pintv = NULL;
+    int i;
+
+    for (i = 0; i < cnt; i++) {
+        if (intv[i].freq_sel == fsel && intv[i].divmode == dmode) {
+            pintv = &intv[i];
+            break;
+        }
+    }
+
+    return pintv;
+}
+
+static void set_cbt_wlev_intv_lp4(DRAMC_CTX_T *p)
+{
+    struct cbt_intv intv[] = {
+        {
+            LP4_DDR4266,
+            DIV8_MODE,
+            17, /*tcmdo1lat*/
+            14, /* catrain_intv */
+            19, /* new_cbt_pat_intv */
+            19, /* wlev_dqspat_lat */
+        }, {
+            LP4_DDR3733,
+            DIV8_MODE,
+            16, /*tcmdo1lat*/
+            13, /* catrain_intv */
+            18, /* new_cbt_pat_intv */
+            18, /* wlev_dqspat_lat */
+        }, {
+            LP4_DDR3200,
+            DIV8_MODE,
+            14, /*tcmdo1lat*/
+            11, /* catrain_intv */
+            16, /* new_cbt_pat_intv */
+            16, /* wlev_dqspat_lat */
+        }, {
+            LP4_DDR2667,
+            DIV8_MODE,
+            13, /*tcmdo1lat*/
+            10, /* catrain_intv */
+            15, /* new_cbt_pat_intv */
+            15, /* wlev_dqspat_lat */
+        }, {
+            LP4_DDR2400,
+            DIV8_MODE,
+            12, /*tcmdo1lat*/
+            9, /* catrain_intv */
+            14, /* new_cbt_pat_intv */
+            14, /* wlev_dqspat_lat */
+        }, {
+            LP4_DDR1866,
+            DIV8_MODE,
+            11, /*tcmdo1lat*/
+            9, /* catrain_intv */
+            13, /* new_cbt_pat_intv */
+            13, /* wlev_dqspat_lat */
+        }, {
+            LP4_DDR1600,
+            DIV8_MODE,
+            10, /*tcmdo1lat*/
+            8, /* catrain_intv */
+            12, /* new_cbt_pat_intv */
+            12, /* wlev_dqspat_lat */
+        }, {
+            LP4_DDR1200,
+            DIV8_MODE,
+            9, /*tcmdo1lat*/
+            8, /* catrain_intv */
+            11, /* new_cbt_pat_intv */
+            11, /* wlev_dqspat_lat */
+        }, {
+            LP4_DDR800,
+            DIV8_MODE,
+            8, /*tcmdo1lat*/
+            8, /* catrain_intv */
+            10, /* new_cbt_pat_intv */
+            10, /* wlev_dqspat_lat */
+        }, {
+            LP4_DDR1600,
+            DIV4_MODE,
+            16, /*tcmdo1lat*/
+            13, /* catrain_intv */
+            16, /* new_cbt_pat_intv */
+            16, /* wlev_dqspat_lat */
+        }, {
+            LP4_DDR1200,
+            DIV4_MODE,
+            14, /*tcmdo1lat*/
+            13, /* catrain_intv */
+            14, /* new_cbt_pat_intv */
+            14, /* wlev_dqspat_lat */
+        }, {
+            LP4_DDR800,
+            DIV4_MODE,
+            12, /*tcmdo1lat*/
+            13, /* catrain_intv */
+            12, /* new_cbt_pat_intv */
+            12, /* wlev_dqspat_lat */
+        }, {
+            LP4_DDR400,
+            DIV4_MODE,
+            12, /*tcmdo1lat*/
+            13, /* catrain_intv */
+            12, /* new_cbt_pat_intv */
+            12, /* wlev_dqspat_lat */
+        },
+    };
+
+    struct cbt_intv *pintv;
+
+    pintv = lookup_cbt_intv(intv, ARRAY_SIZE(intv),
+            p->freq_sel, vGet_Div_Mode(p));
+    if (!pintv) {
+        mcSHOW_ERR_MSG(("not found entry!\n"));
+        return;
+    }
+
+    set_cbt_intv_rg(p, pintv);
+}
+
+#if __LP5_COMBO__
+static void set_cbt_wlev_intv_lp5(DRAMC_CTX_T *p)
+{
+    struct cbt_intv intv[] = {
+        {
+            LP5_DDR6400,
+            UNKNOWN_MODE,
+            15, /*tcmdo1lat*/
+            15, /* catrain_intv */
+            17, /* new_cbt_pat_intv */
+            17, /* wlev_dqspat_lat */
+        }, {
+            LP5_DDR6000,
+            UNKNOWN_MODE,
+            15, /*tcmdo1lat*/
+            15, /* catrain_intv */
+            17, /* new_cbt_pat_intv */
+            17, /* wlev_dqspat_lat */
+        }, {
+            LP5_DDR5500,
+            UNKNOWN_MODE,
+            14, /*tcmdo1lat*/
+            14, /* catrain_intv */
+            16, /* new_cbt_pat_intv */
+            16, /* wlev_dqspat_lat */
+        }, {
+            LP5_DDR4800,
+            UNKNOWN_MODE,
+            13, /*tcmdo1lat*/
+            13, /* catrain_intv */
+            15, /* new_cbt_pat_intv */
+            15, /* wlev_dqspat_lat */
+        }, {
+            LP5_DDR4266,
+            UNKNOWN_MODE,
+            20, /*tcmdo1lat*/
+            20, /* catrain_intv */
+            22, /* new_cbt_pat_intv */
+            20, /* wlev_dqspat_lat */
+        }, {
+            LP5_DDR3733,
+            UNKNOWN_MODE,
+            19, /*tcmdo1lat*/
+            19, /* catrain_intv */
+            21, /* new_cbt_pat_intv */
+            19, /* wlev_dqspat_lat */
+        }, {
+            LP5_DDR3200,
+            UNKNOWN_MODE,
+            15, /*tcmdo1lat*/
+            15, /* catrain_intv */
+            17, /* new_cbt_pat_intv */
+            17, /* wlev_dqspat_lat */
+        }, {
+            LP5_DDR2400,
+            UNKNOWN_MODE,
+            13, /*tcmdo1lat*/
+            13, /* catrain_intv */
+            15, /* new_cbt_pat_intv */
+            15, /* wlev_dqspat_lat */
+        }, {
+            LP5_DDR1600,
+            UNKNOWN_MODE,
+            17, /*tcmdo1lat*/
+            17, /* catrain_intv */
+            19, /* new_cbt_pat_intv */
+            17, /* wlev_dqspat_lat */
+        }, {
+            LP5_DDR1200,
+            UNKNOWN_MODE,
+            15, /*tcmdo1lat*/
+            15, /* catrain_intv */
+            17, /* new_cbt_pat_intv */
+            15, /* wlev_dqspat_lat */
+        }, {
+            LP5_DDR800,
+            UNKNOWN_MODE,
+            13, /*tcmdo1lat*/
+            13, /* catrain_intv */
+            15, /* new_cbt_pat_intv */
+            13, /* wlev_dqspat_lat */
+        },
+    };
+
+    struct cbt_intv *pintv;
+
+    pintv = lookup_cbt_intv(intv, ARRAY_SIZE(intv), p->freq_sel, UNKNOWN_MODE);
+    if (!pintv) {
+        mcSHOW_ERR_MSG(("not found entry!\n"));
+        return;
+    }
+
+    set_cbt_intv_rg(p, pintv);
+}
+#endif /* __LP5_COMBO__ */
+
+static void set_cbt_wlev_intv(DRAMC_CTX_T *p)
+{
+#if __LP5_COMBO__
+    if (is_lp5_family(p))
+        set_cbt_wlev_intv_lp5(p);
+    else
+#endif
+        set_cbt_wlev_intv_lp4(p);
+}
+
+#if SIMUILATION_CBT == 1
+/* To process LPDDR5 Pinmux */
+struct cbt_pinmux {
+    u8 dram_dq_b0; /* EMI_B0 is mapped to which DRAMC byte ?? */
+    u8 dram_dq_b1;
+    u8 dram_dmi_b0; /* EMI_DMI0 is mapped to which DRAMC DMI ?? */
+    u8 dram_dmi_b1;
+
+    u8 dram_dq7_b0; /* EMI_DQ7 is mapped to which DRAMC DQ ?? */
+    u8 dram_dq7_b1; /* EMI_DQ15 is mapped to which DRAMC DQ ?? */
+};
+
+/* Per-project definition */
+static struct cbt_pinmux lp4_cp[CHANNEL_NUM] = {
+    {
+        /* CHA */
+        .dram_dq_b0 = 0,
+        .dram_dq_b1 = 1,
+
+        .dram_dmi_b0 = 0,
+        .dram_dmi_b1 = 1,
+    },
+    #if (CHANNEL_NUM>1)
+    {
+        /* CHB */
+        .dram_dq_b0 = 0,
+        .dram_dq_b1 = 1,
+
+        .dram_dmi_b0 = 0,
+        .dram_dmi_b1 = 1,
+    },
+    #endif
+    #if (CHANNEL_NUM>2)
+    {
+        /* CHC */
+        .dram_dq_b0 = 0,
+        .dram_dq_b1 = 1,
+
+        .dram_dmi_b0 = 0,
+        .dram_dmi_b1 = 1,
+    },
+    {
+        /* CHD */
+        .dram_dq_b0 = 0,
+        .dram_dq_b1 = 1,
+
+        .dram_dmi_b0 = 0,
+        .dram_dmi_b1 = 1,
+    },
+    #endif
+};
+#if 0
+static struct cbt_pinmux lp5_cp[CHANNEL_NUM] = {
+    {
+        /* CHA */
+        .dram_dq_b0 = 1,
+        .dram_dq_b1 = 0,
+
+        .dram_dmi_b0 = 1,
+        .dram_dmi_b1 = 0,
+
+        .dram_dq7_b0 = 13,
+        .dram_dq7_b1 = 5,
+    },
+#if (CHANNEL_NUM > 1)
+    {
+        /* CHB */
+        .dram_dq_b0 = 1,
+        .dram_dq_b1 = 0,
+
+        .dram_dmi_b0 = 1,
+        .dram_dmi_b1 = 0,
+
+        .dram_dq7_b0 = 13,
+        .dram_dq7_b1 = 5,
+    },
+#endif
+};
+#endif
+static inline u8 is_byte_mode(DRAMC_CTX_T *p)
+{
+    return p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1? 1: 0;
+}
+
+static void vSetDramMRCBTOnOff(DRAMC_CTX_T *p, U8 u1OnOff, U8 operating_fsp)
+{
+    if (u1OnOff)
+    {
+        // op[7] = !(p->dram_fsp), dram will switch to another FSP_OP automatically
+        if (operating_fsp)
+        {
+            MRWriteFldMulti(p, 13, P_Fld(0, MR13_FSP_OP) |
+                                   P_Fld(1, MR13_FSP_WR) |
+                                   P_Fld(1, MR13_CBT),
+                                   TO_MR);
+        }
+        else
+        {
+            MRWriteFldMulti(p, 13, P_Fld(1, MR13_FSP_OP) |
+                                   P_Fld(0, MR13_FSP_WR) |
+                                   P_Fld(1, MR13_CBT),
+                                   TO_MR);
+        }
+
+        if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1)
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), P_Fld(1, CBT_WLEV_CTRL0_BYTEMODECBTEN) |
+				P_Fld(1, CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE));    //BYTEMODECBTEN=1
+        }
+    }
+    else
+    {
+        if (operating_fsp)
+        {
+            // !! Remain MR13_FSP_OP = 0, because of system is at low frequency now.
+            // @Darren, Fix high freq keep FSP0 for CA term workaround (PPR abnormal)
+            MRWriteFldMulti(p, 13, P_Fld(0, MR13_FSP_OP) |
+                                   P_Fld(1, MR13_FSP_WR) |
+                                   P_Fld(0, MR13_CBT),
+                                   TO_MR);
+        }
+        else
+        {
+            MRWriteFldMulti(p, 13, P_Fld(1, MR13_FSP_OP) |
+                                   P_Fld(0, MR13_FSP_WR) |
+                                   P_Fld(0, MR13_CBT),
+                                   TO_MR);
+        }
+    }
+
+}
+
+static void CBTEntryLP4(DRAMC_CTX_T *p, U8 operating_fsp, U16 operation_frequency)
+{
+    struct cbt_pinmux *cp = &lp4_cp[p->channel];
+
+    #if MR_CBT_SWITCH_FREQ
+    if (p->dram_fsp == FSP_1)
+        DramcModeRegInit_CATerm(p, 1);
+    #endif
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL),
+            0, MISC_STBCAL_DQSIENCG_NORMAL_EN);
+
+    CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL);
+
+    // yr: CA train old mode and CS traing need to check MRSRK at this point
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1GetRank(p), SWCMD_CTRL0_MRSRK);
+
+    //Step 0: MRW MR13 OP[0]=1 to enable CBT
+    vSetDramMRCBTOnOff(p, ENABLE, operating_fsp);
+
+    //Step 0.1: before CKE low, Let DQS=0 by R_DMwrite_level_en=1, spec: DQS_t has to retain a low level during tDQSCKE period
+    if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE)
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
+                1, CBT_WLEV_CTRL0_WRITE_LEVEL_EN);
+
+        //TODO, pinmux
+        //force byte0 tx
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
+            0x1, CBT_WLEV_CTRL0_DQSOEAOEN);
+
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
+            (1 << cp->dram_dq_b0), CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN);
+    }
+
+    mcDELAY_US(1);
+
+    //Step 1.0: let CKE go low
+    CKEFixOnOff(p, p->rank, CKE_FIXOFF, TO_ONE_CHANNEL);
+
+    // Adjust u1MR13Value
+    (operating_fsp == FSP_1)?
+            DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE):
+            DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE);
+
+    // Step 1.1 : let IO to O1 path valid
+    if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE)
+    {
+        // Let R_DMFIXDQIEN1=1 (byte1), 0xd8[13]  ==> Note: Do not enable again.
+        //Currently set in O1PathOnOff
+        //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_PADCTRL), 0x3, PADCTRL_FIXDQIEN);
+
+        // Let DDRPHY RG_RX_ARDQ_SMT_EN_B1=1 (byte1)
+        //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_B1_DQ3), 1, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1);
+        O1PathOnOff(p, ON);
+    }
+
+    if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1)
+    {
+        // let IO to O1 path valid by DDRPHY RG_RX_ARDQ_SMT_EN_B0=1
+        //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_B0_DQ3), 1, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0);
+        O1PathOnOff(p, ON);
+    }
+
+    // Wait tCAENT
+    mcDELAY_US(1);
+}
+
+static void CBTExitLP4(DRAMC_CTX_T *p, U8 operating_fsp, U8 operation_frequency)
+{
+    //U8 u1MROP;
+
+    if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE || p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1)
+    {
+        //Step 1: CKE go high (Release R_DMCKEFIXOFF, R_DMCKEFIXON=1)
+        CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL);
+
+        //Step 2:wait tCATX, wait tFC
+        mcDELAY_US(1);
+
+        //Step 3: MRW to command bus training exit (MR13 OP[0]=0 to disable CBT)
+        vSetDramMRCBTOnOff(p, DISABLE, operating_fsp);
+
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
+                 0, CBT_WLEV_CTRL0_WRITE_LEVEL_EN);
+    }
+
+    //Step 4:
+    //Disable O1 path output
+    if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE)
+    {
+        //Let DDRPHY RG_RX_ARDQ_SMT_EN_B1=0
+        //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_B1_DQ3), 0, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1);
+        O1PathOnOff(p, OFF);
+        //Let FIXDQIEN1=0 ==> Note: Do not enable again.
+        //Moved into O1PathOnOff
+        //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_PADCTRL), 0, PADCTRL_FIXDQIEN);
+    }
+
+    if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1)
+    {
+        //Let DDRPHY RG_RX_ARDQ_SMT_EN_B0=0
+        //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_B0_DQ3), 0, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0);
+        O1PathOnOff(p, OFF);
+
+        //Disable Byte mode CBT enable bit
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), P_Fld(0, CBT_WLEV_CTRL0_BYTEMODECBTEN) |
+			P_Fld(0, CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE));    //BYTEMODECBTEN=1
+    }
+
+    // Wait tCAENT
+    mcDELAY_US(1);
+}
+
+/*
+ * get_mck_ck_ratio -- get ratio of mck:ck
+ *
+ * TODO, remove later, get the ratio from dram ctx dfs table!!!!
+ *
+ *
+ * return 1 means 1:1
+ * return 0 means 1:2
+ */
+static u8 get_mck_ck_ratio(DRAMC_CTX_T *p)
+{
+    /*
+    * as per DE's comments, LP5 mck:ck has only 1:1 and 1:2.
+    * read SHU_LP5_CMD.LP5_CMD1TO2EN to decide which one.
+    */
+    u32 ratio;
+    //u32 ui_max;
+
+    ratio = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_LP5_CMD),
+        SHU_LP5_CMD_LP5_CMD1TO2EN);
+
+    mcSHOW_DBG_MSG5(("LP5 MCK:CK=%s\n", ratio == 1 ? "1:1" : "1:2"));
+
+    return ratio;
+}
+
+static u8 get_cbtui_adjustable_maxvalue(DRAMC_CTX_T *p)
+{
+    u8 ratio;
+
+    /*
+    * MCK:CK=1:1,
+    * ther are only 0~1 for ui adjust, if ui value is larger than 1, adjust MCK.
+    *
+    * MCK:CK=1:2,
+    * ther are only 0~3 for ui adjust, if ui value is larger than 3, adjust MCK.
+    *
+    * MCK:CK=1:4, (for LP4)
+    * ther are only 0~7 for ui adjust, if ui value is larger than 7, adjust MCK.
+    *
+    */
+#if __LP5_COMBO__
+	if (is_lp5_family(p))
+		ratio = (get_mck_ck_ratio(p) == 1) ? 1 : 3;
+	else
+#endif
+		ratio = (vGet_Div_Mode(p) == DIV4_MODE) ? 3 : 7;
+
+    return ratio;
+}
+
+static inline u32 get_ca_mck(DRAMC_CTX_T *p)
+{
+    u32 dly;
+
+    dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3));
+    return dly & 0x0FFFFFFFU;
+}
+
+static inline void put_ca_mck(DRAMC_CTX_T *p, u32 ca_mck)
+{
+    u32 dly;
+
+    dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3));
+    dly &= 0xF0000000U;
+    ca_mck &= 0x0FFFFFFFU;
+    dly |= ca_mck;
+
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3), dly);
+}
+
+static inline u32 get_ca_ui(DRAMC_CTX_T *p)
+{
+    u32 dly;
+
+    dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7));
+    return dly & 0x0FFFFFFFU;
+}
+
+static inline void put_ca_ui(DRAMC_CTX_T *p, u32 ca_ui)
+{
+    u32 dly;
+
+    dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7));
+    dly &= 0xF0000000U;
+    ca_ui &= 0x0FFFFFFFU;
+    dly |= ca_ui;
+
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7), dly);
+
+    // Note: CKE UI must sync CA UI (CA and CKE delay circuit are same) @Lin-Yi
+    // To avoid tXP timing margin issue
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), ca_ui & 0xF, SHU_SELPH_CA5_DLY_CKE);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA6), ca_ui & 0xF, SHU_SELPH_CA6_DLY_CKE1);
+}
+
+static void xlate_ca_mck_ui(DRAMC_CTX_T *p, u32 ui_delta,
+        u32 mck_old, u32 ui_old, u32 *mck_new, u32 *ui_new)
+{
+    u8 i;
+    u32 mask, max;
+    u32 bit_ui, bit_mck;
+    u32 ui_tmp = 0, mck_tmp = 0;
+
+    max = get_cbtui_adjustable_maxvalue(p);
+    mask = max;
+
+    for (i = 0; i < CATRAINING_NUM_LP5; i++) {
+        bit_mck = 0;
+        bit_ui = ((ui_old >> (i * 4)) & mask) + ui_delta;
+        if (bit_ui > max) {
+            bit_mck = bit_ui / (max + 1);
+            bit_ui = bit_ui % (max + 1);
+        }
+
+        mck_tmp += (bit_mck << (i * 4));
+        ui_tmp += (bit_ui << (i * 4));
+    }
+
+    if (ui_new)
+        *ui_new = ui_tmp;
+
+    if (mck_new)
+        *mck_new = mck_old + mck_tmp;
+}
+
+static S16 adjust_ca_ui(DRAMC_CTX_T *p, U32 ca_mck,
+        U32 ca_ui, S16 pi_dly)
+{
+    S16 p2u;
+    S16 ui, pi;
+    U32 ui_new = 0, mck_new = 0;
+
+    if (pi_dly < get_capi_max(p))
+    {
+        return pi_dly;
+    }
+
+    p2u = get_ca_pi_per_ui(p);
+
+    ui = pi_dly / p2u;
+    pi = pi_dly % p2u;
+
+    xlate_ca_mck_ui(p, ui, ca_mck, ca_ui, &mck_new, &ui_new);
+
+    put_ca_ui(p, ui_new);
+    put_ca_mck(p, mck_new);
+    mcSHOW_DBG_MSG5(("mck_new: 0x%x, ui_new: 0x%x, pi:%d\n",
+        mck_new, ui_new, pi));
+
+    return pi;
+}
+
+static inline u32 get_cs_mck(DRAMC_CTX_T *p)
+{
+    if (p->rank == RANK_1)
+        return u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA1),
+            SHU_SELPH_CA1_TXDLY_CS1);
+    else
+        return u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA1),
+            SHU_SELPH_CA1_TXDLY_CS);
+}
+
+static inline void put_cs_mck(DRAMC_CTX_T *p, u32 cs_ui)
+{
+    if (p->rank == RANK_1)
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA1),
+            cs_ui, SHU_SELPH_CA1_TXDLY_CS1);
+    else
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA1),
+            cs_ui, SHU_SELPH_CA1_TXDLY_CS);
+}
+
+static inline u32 get_cs_ui(DRAMC_CTX_T *p)
+{
+    if (p->rank == RANK_1)
+        return u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5),
+            SHU_SELPH_CA5_DLY_CS1);
+    else
+        return u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5),
+            SHU_SELPH_CA5_DLY_CS);
+}
+
+static inline void put_cs_ui(DRAMC_CTX_T *p, u32 cs_ui)
+{
+    if (p->rank == RANK_1)
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5),
+            cs_ui, SHU_SELPH_CA5_DLY_CS1);
+    else
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5),
+            cs_ui, SHU_SELPH_CA5_DLY_CS);
+}
+
+//void LP5_ShiftCSUI(DRAMC_CTX_T *p, S8 iShiftUI)
+//{
+//  REG_TRANSFER_T TransferUIRegs  = {DRAMC_REG_SHU_SELPH_CA5, SHU_SELPH_CA5_DLY_CS};
+//  REG_TRANSFER_T TransferMCKRegs = {DRAMC_REG_SHU_SELPH_CA1, SHU_SELPH_CA1_TXDLY_CS};
+//
+//  ExecuteMoveDramCDelay(p, TransferUIRegs[i], TransferMCKRegs[i], iShiftUI);
+//}
+
+static S16 adjust_cs_ui(DRAMC_CTX_T *p, u32 cs_mck, u32 cs_ui, S16 pi_dly)
+{
+    S16 p2u;
+    S16 ui = 0, pi = 0;
+    u8 ratio;
+    u32 ui_max;
+    u32 cs_bit_mask, cs_ui_tmp, cs_mck_tmp;
+
+    if (pi_dly < get_capi_max(p))
+    {
+        return pi_dly;
+    }
+
+    p2u = get_ca_pi_per_ui(p);
+
+    ui = pi_dly / p2u;
+    pi = pi_dly % p2u;
+
+    ratio = get_mck_ck_ratio(p);
+    if (ratio) {
+        /* 1:1 */
+        cs_bit_mask = 1;
+    } else {
+        /* 1:2 */
+        cs_bit_mask = 3;
+    }
+
+    ui_max = get_cbtui_adjustable_maxvalue(p);
+    cs_ui_tmp = (cs_ui & cs_bit_mask) + ui;
+    cs_mck_tmp = 0;
+    if (cs_ui_tmp > ui_max) {
+        cs_mck_tmp = cs_ui_tmp / (ui_max + 1);
+        cs_ui_tmp = cs_ui_tmp % (ui_max + 1);
+    }
+
+    cs_mck_tmp += cs_mck;
+    put_cs_ui(p, cs_ui_tmp);
+    put_cs_mck(p, cs_mck_tmp);
+
+    mcSHOW_DBG_MSG5(("csmck:%d, csui: %d, pi:%d before\n",
+            cs_mck, cs_ui, 0));
+    mcSHOW_DBG_MSG5(("csmck:%d, csui: %d, pi:%d after\n",
+            cs_mck_tmp, cs_ui_tmp, pi));
+
+    return pi;
+}
+
+static u32 get_capi_step(DRAMC_CTX_T *p, int autok)
+{
+    u32 step;
+
+#if FOR_DV_SIMULATION_USED
+    step = 8;
+#else
+    switch (p->freq_sel) {
+    case LP5_DDR800:
+    case LP5_DDR1200:
+    case LP5_DDR1600:
+    case LP5_DDR3733:
+        step = 8;
+        break;
+    default:
+        if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE)
+            step = 8;
+        else if (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE)
+            step = 16;
+        else
+            step = 1;
+
+        break;
+    }
+#endif
+
+    if (step > 8 && autok)
+        step = 8;
+
+    return step;
+}
+#if 0
+static int find_next_bit(u32 *bitmap, u8 bitval, u8 start, u8 end,
+        u8 *bit_pos)
+{
+    u8 i, base, ofst;
+    u32 map;
+    int res = 0;
+
+    for (i = start; i < end + 1; i++) {
+        base = (i >> 5); /* i / 32  */
+        ofst = i & 0x1F; /* i % 32 */
+        map = bitmap[base];
+
+        if ((bitval == 0) && ((map & (1UL << ofst)) == 0UL)) {
+            *bit_pos = i;
+            res = 1;
+            break;
+        } else if (bitval && (map & (1UL << ofst))) {
+            *bit_pos = i;
+            res = 1;
+            break;
+        }
+    }
+
+    return res;
+}
+
+static int find_next_zero_bit(u32 *bitmap, u8 start, u8 end, u8 *bit_pos)
+{
+    return find_next_bit(bitmap, 0, start, end, bit_pos);
+}
+
+static int find_next_one_bit(u32 *bitmap, u8 start, u8 end, u8 *bit_pos)
+{
+    return find_next_bit(bitmap, 1, start, end, bit_pos);
+}
+
+static int find_zero_window(u32 *bitmap, u8 start, u8 end,
+        u8 *win_start, u8 *win_end)
+{
+    int res;
+    u8 win_lsb, win_msb;
+
+    if (start > end)
+        return 0;
+
+    res = find_next_zero_bit(bitmap, start, end, &win_lsb);
+    if (!res)
+        return 0;
+
+    res = find_next_one_bit(bitmap, win_lsb + 1, end, &win_msb);
+    if (!res)
+        win_msb = end + 1;
+
+    *win_start = win_lsb;
+    *win_end = win_msb - 1;
+
+    return 1;
+}
+#endif
+#if 0
+static int get_new_cbt_pat_cfg(DRAMC_CTX_T *p,
+        new_cbt_pat_cfg_t *pncm, U8 u1CATrain)
+{
+#if __LP5_COMBO__
+    if (is_lp5_family(p)) {
+        /* lp5 */
+        pncm->pat_v[0] = 0x04;
+        pncm->pat_v[1] = 0x0B;
+        pncm->pat_v[2] = 0x0B;
+        pncm->pat_v[3] = 0x04;
+        pncm->pat_v[4] = 0x04;
+        pncm->pat_v[5] = 0x0B;
+        pncm->pat_v[6] = 0x0A;
+        pncm->pat_v[7] = 0x05;
+
+        pncm->pat_a[0] = 0x00;
+        pncm->pat_a[1] = 0x0F;
+        pncm->pat_a[2] = 0x04;
+        pncm->pat_a[3] = 0x0B;
+        pncm->pat_a[4] = 0x04;
+        pncm->pat_a[5] = 0x0B;
+        pncm->pat_a[6] = 0x0A;
+        pncm->pat_a[7] = 0x05;
+
+        pncm->pat_dmv = 0x55;
+        pncm->pat_dma = 0xAA;
+
+        pncm->pat_cs0 = 0x0C;
+        pncm->pat_cs1 = 0x0C;
+        pncm->ca_golden_sel = 0x2;
+        pncm->pat_num = 7;
+        pncm->ca_num = 6;
+    } else
+#endif
+    {
+        /* lp4 */
+        pncm->pat_v[0] = 0x30;
+        pncm->pat_v[1] = 0xCF;
+        pncm->pat_v[2] = 0xCF;
+        pncm->pat_v[3] = 0x30;
+        pncm->pat_v[4] = 0x30;
+        pncm->pat_v[5] = 0xCF;
+        pncm->pat_v[6] = 0xCC;
+        pncm->pat_v[7] = 0x33;
+
+        pncm->pat_a[0] = 0x00;
+        pncm->pat_a[1] = 0xFF;
+        pncm->pat_a[2] = 0x30;
+        pncm->pat_a[3] = 0xCF;
+        pncm->pat_a[4] = 0x30;
+        pncm->pat_a[5] = 0xCF;
+        pncm->pat_a[6] = 0xCC;
+        pncm->pat_a[7] = 0x33;
+
+        pncm->pat_dmv = 0x55;
+        pncm->pat_dma = 0xAA;
+
+        pncm->pat_cs0 = 0x30;
+        pncm->pat_cs1 = 0x30;
+        pncm->ca_golden_sel = 0x4;
+        pncm->pat_num = 7;
+        pncm->ca_num = 5;
+    }
+
+    pncm->invert_num = 1;
+
+#if FOR_DV_SIMULATION_USED == 1
+    cal_sv_rand_args_t *psra = get_psra();
+
+    if (psra) {
+        /*
+         * DV's regression
+         */
+        int i;
+
+        for (i = 0; i < 8; i++) {
+            pncm->pat_v[i] = psra->pat_v[i] & 0xFF;
+            pncm->pat_a[i] = psra->pat_a[i] & 0xFF;
+        }
+        pncm->pat_dmv = psra->pat_dmv & 0xFF;
+        pncm->pat_dma = psra->pat_dma & 0xFF;
+        pncm->pat_cs0 = psra->pat_cs & 0xFF;
+        pncm->pat_cs1 = pncm->pat_cs0;
+        pncm->ca_golden_sel = psra->cagolden_sel & 0xFF;
+        pncm->invert_num = psra->invert_num & 0xFF;
+    }
+#endif
+
+    if (!u1CATrain) {
+        pncm->pat_a[0] = pncm->pat_v[0] ^ 0xFF;
+        pncm->pat_dmv = 0x00;
+        pncm->pat_dma = 0x00;
+        pncm->pat_num = 1;
+        pncm->ca_num = 0;
+        pncm->invert_num = 0;
+    }
+
+    return 0;
+}
+
+static void cfg_new_cbt_pat(DRAMC_CTX_T *p,
+        new_cbt_pat_cfg_t *pncm)
+{
+    u32 tmp;
+
+    tmp = (pncm->pat_v[3] << 24) | (pncm->pat_v[2] << 16) |
+            (pncm->pat_v[1] << 8) | pncm->pat_v[0];
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_INITK_PAT0),
+            tmp, INITK_PAT0_INITK_PAT0);
+
+    tmp = (pncm->pat_v[7] << 24) | (pncm->pat_v[6] << 16) |
+            (pncm->pat_v[5] << 8) | pncm->pat_v[4];
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_INITK_PAT1),
+            tmp, INITK_PAT1_INITK_PAT1);
+
+    tmp = (pncm->pat_a[3] << 24) | (pncm->pat_a[2] << 16) |
+            (pncm->pat_a[1] << 8) | pncm->pat_a[0];
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_INITK_PAT2),
+            tmp, INITK_PAT2_INITK_PAT2);
+
+    tmp = (pncm->pat_a[7] << 24) | (pncm->pat_a[6] << 16) |
+            (pncm->pat_a[5] << 8) | pncm->pat_a[4];
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_INITK_PAT3),
+            tmp, INITK_PAT3_INITK_PAT3);
+
+    tmp = (pncm->pat_cs1 << 24) | (pncm->pat_cs0 << 16) |
+            (pncm->pat_dma << 8) | pncm->pat_dmv;
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_INITK_PAT4),
+            tmp, INITK_PAT4_INITK_PAT4);
+
+#ifdef CBT_NEW_PAT_DEBUG
+    mcSHOW_DBG_MSG(("CBT NEW PAT:\n"));
+    mcSHOW_DBG_MSG(("PAT0_V=0x%x, PAT0_A=0x%x\n", pncm->pat_v[0], pncm->pat_a[0]));
+    mcSHOW_DBG_MSG(("PAT_DMV=0x%x, PAT_DMA=0x%x\n", pncm->pat_dmv, pncm->pat_dma));
+    mcSHOW_DBG_MSG(("PAT_CS0=0x%x, PAT_CS1=0x%x\n", pncm->pat_cs0, pncm->pat_cs1));
+#endif
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5),
+            P_Fld(1, CBT_WLEV_CTRL5_CBT_NEW_MODE) |
+            P_Fld(p->rank, CBT_WLEV_CTRL5_NEW_CBT_PAT_RKSEL) |
+            P_Fld(pncm->ca_num, CBT_WLEV_CTRL5_NEW_CBT_CA_NUM) |
+            P_Fld(pncm->pat_num, CBT_WLEV_CTRL5_NEW_CBT_PAT_NUM) |
+            P_Fld(pncm->invert_num, CBT_WLEV_CTRL5_NEW_CBT_INVERT_NUM) |
+            P_Fld(pncm->ca_golden_sel, CBT_WLEV_CTRL5_NEW_CBT_CAGOLDEN_SEL));
+}
+#endif
+#if CBT_O1_PINMUX_WORKAROUND
+static u32 CBTCompareWordaroundDecodeO1Pinmux(DRAMC_CTX_T *p, u32 o1_value, U8 *uiLPDDR_O1_Mapping)
+{
+    U8 u1Idx;
+    U32 u4Result;
+
+    u4Result = 0;
+
+    for (u1Idx = 0;u1Idx < p->data_width;u1Idx++)
+        u4Result |= ((o1_value >> uiLPDDR_O1_Mapping[u1Idx]) & 0x1) << u1Idx;
+
+    return u4Result;
+}
+
+#if CBT_OLDMODE_SUPPORT
+static u32 CBTDelayCACLKCompareWorkaround(DRAMC_CTX_T *p)
+{
+    u8 u1pattern_index, u1ca_index, u1dq_index, u1dq_start, u1dq_end, u1ca_number_per_bit, u1bit_num_per_byte, u1pattern_choose;
+    U8 *uiLPDDR_O1_Mapping = NULL;
+    u32 u4TimeCnt, rdy, u4dq_o1, u4data_receive, u4ca_pattern, u4Result, u4Ready;
+    u8 u1pattern_num;
+
+    const U8 u1LP5CBT_Pattern_Mapping[2][7] =
+    {
+        {
+            1, 2, 4, 8, 16, 32, 64
+        },
+
+        {
+            126, 125, 123, 119, 111, 95, 63
+        },
+    };
+    const U8 u1LP4CBT_Pattern_Mapping[2][6] =
+    {
+        {
+            1, 2, 4, 8, 16, 32
+        },
+
+        {
+            62, 61, 59, 55, 47, 31
+        },
+    };
+
+    u4Result = 0;
+    u1bit_num_per_byte = 8;
+
+#if (__LP5_COMBO__)
+    if (is_lp5_family(p))
+    {
+        uiLPDDR_O1_Mapping = (U8 *)uiLPDDR5_O1_Mapping_POP[p->channel];
+        u1pattern_num = 8;
+        u1ca_number_per_bit = CATRAINING_NUM_LP5;
+        if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE)
+        {
+            u1dq_start = 0;
+            u1dq_end = 6;
+        }
+        else
+        {
+            u1dq_start = 0;
+            u1dq_end = 14;
+        }
+    }
+    else
+#endif
+    {
+        uiLPDDR_O1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[p->channel];
+        u1pattern_num = 4;
+        u1ca_number_per_bit = CATRAINING_NUM_LP4;
+        if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE)
+        {
+            u1dq_start = 8;
+            u1dq_end = 13;
+        }
+        else
+        {
+            u1dq_start = 0;
+            u1dq_end = 13;
+        }
+    }
+
+    vIO32WriteFldMulti(DRAMC_REG_CBT_WLEV_CTRL3, P_Fld(0x1, CBT_WLEV_CTRL3_CATRAIN_PAT_STOP0)
+        | P_Fld(0x1, CBT_WLEV_CTRL3_CATRAIN_PAT_STOP1));
+
+    for (u1pattern_index = 0; u1pattern_index < u1pattern_num; u1pattern_index++)
+    {
+        u1pattern_choose = (u1pattern_index > 3) ? (u1pattern_index % 2) : /* LP5 mapping */
+            ((u1pattern_index > 1)? (3 - u1pattern_index) : u1pattern_index); /* LP5 & LP4 mapping */
+        for (u1ca_index = 0; u1ca_index < u1ca_number_per_bit; u1ca_index++)
+        {
+        #if (__LP5_COMBO__)
+            if (is_lp5_family(p))
+            {
+                u4ca_pattern = u1LP5CBT_Pattern_Mapping[u1pattern_choose][u1ca_index];
+            }
+            else
+        #endif
+            {
+                u4ca_pattern = u1LP4CBT_Pattern_Mapping[u1pattern_choose][u1ca_index];
+            }
+
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3), P_Fld((u1pattern_index+1), CBT_WLEV_CTRL3_CATRAIN_1PAT_SEL0)
+                                                       | P_Fld((u1ca_index+1), CBT_WLEV_CTRL3_CATRAIN_1PAT_SEL1));
+
+            u4TimeCnt = TIME_OUT_CNT;
+
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 1, CBT_WLEV_CTRL0_CBT_CAPATEN);
+
+            //Check CA training compare ready (dramc_conf_nao 0x3fc , CATRAIN_CMP_CPT)
+            do
+            {
+                u4Ready = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS1), CBT_WLEV_STATUS1_CATRAIN_CMP_CPT);
+                u4TimeCnt --;
+                mcDELAY_US(1);
+            }while ((u4Ready == 0) && (u4TimeCnt > 0));
+
+            if (u4TimeCnt == 0)//time out
+            {
+                mcSHOW_ERR_MSG(("[CBTDelayCACLKCompare] Resp fail (time out)\n"));
+                mcFPRINTF((fp_A60868, "[CBTDelayCACLKCompare] Resp fail (time out)\n"));//Eddie Test
+                //return DRAM_FAIL;
+            }
+
+            u4dq_o1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQO1), MISC_DQO1_DQO1_RO);
+
+            u4dq_o1 = CBTCompareWordaroundDecodeO1Pinmux(p, u4dq_o1, uiLPDDR_O1_Mapping);
+
+            if (u1dq_end >= u1ca_number_per_bit)
+                u4ca_pattern |= u4ca_pattern << u1bit_num_per_byte;
+
+            u4dq_o1 ^= u4ca_pattern;
+
+            for(u1dq_index=u1dq_start; u1dq_index<=u1dq_end; u1dq_index++)
+            {
+                if ((p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) && (u1dq_index == u1ca_number_per_bit))
+                    u1dq_index = u1bit_num_per_byte;
+
+                u4data_receive = (u4dq_o1 >> u1dq_index) & 0x1;
+
+                if (u1dq_index < u1bit_num_per_byte)
+                    u4Result |= u4data_receive << u1dq_index;
+                else
+                    u4Result |= u4data_receive << u1dq_index - u1bit_num_per_byte;
+            }
+
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0, CBT_WLEV_CTRL0_CBT_CAPATEN);
+
+        }
+        if (u4Result == ((0x1 << u1ca_number_per_bit) - 1))
+            break;
+    }
+    return u4Result;
+}
+#endif
+
+static u32 new_cbt_pat_compare_workaround(DRAMC_CTX_T *p, new_cbt_pat_cfg_t *ncm)
+{
+    u8 u1pattern_index, u1ca_index, u1dq_index, u1dq_start, u1dq_end, u1ca_number_per_bit, u1bit_num_per_byte;
+    U8 *uiLPDDR_O1_Mapping = NULL;
+    u32 u4TimeCnt, rdy, u4dq_o1, u4data_receive, u4ca_pattern_a, u4ca_pattern, u4Result, u4Ready;
+    u8 u1pattern_num;
+
+    u4Result = 0;
+    u1bit_num_per_byte = 8;
+
+#if (__LP5_COMBO__)
+    if (is_lp5_family(p))
+    {
+        uiLPDDR_O1_Mapping = (U8 *)uiLPDDR5_O1_Mapping_POP[p->channel];
+        u1pattern_num = 8;
+        u1ca_number_per_bit = 7;
+        if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE)
+        {
+            u1dq_start = 0;
+            u1dq_end = 6;
+        }
+        else
+        {
+            u1dq_start = 0;
+            u1dq_end = 14;
+        }
+    }
+    else
+#endif
+    {
+        uiLPDDR_O1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[p->channel];
+        u1pattern_num = 4;
+        u1ca_number_per_bit = 6;
+        if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE)
+        {
+            u1dq_start = 8;
+            u1dq_end = 13;
+        }
+        else
+        {
+            u1dq_start = 0;
+            u1dq_end = 13;
+        }
+    }
+
+    for (u1pattern_index = 0; u1pattern_index < u1pattern_num; u1pattern_index++)
+    {
+        u4ca_pattern_a = ((ncm->pat_a[u1pattern_index] >> ncm->ca_golden_sel) & 0x1) ? ((0x1 << u1ca_number_per_bit) - 1) : 0x0;
+
+        for (u1ca_index = 0; u1ca_index < u1ca_number_per_bit; u1ca_index++)
+        {
+            u4ca_pattern = u4ca_pattern_a & ~(0x1 << u1ca_index);
+
+            if ((ncm->pat_v[u1pattern_index] >> ncm->ca_golden_sel) & 0x1)
+                u4ca_pattern |= 0x1 << u1ca_index;
+
+            if (ncm->invert_num)
+                u4ca_pattern ^= (0x1 << u1ca_number_per_bit) - 1;
+
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), P_Fld(u1pattern_index, CBT_WLEV_CTRL5_NEW_CBT_PAT_NUM)
+                                                       | P_Fld(u1ca_index, CBT_WLEV_CTRL5_NEW_CBT_CA_NUM));
+
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), 1, CBT_WLEV_CTRL5_NEW_CBT_CAPATEN);
+
+            //Check CA training compare ready (dramc_conf_nao 0x3fc , CATRAIN_CMP_CPT)
+            do
+            {
+                u4Ready = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS2), CBT_WLEV_STATUS2_CBT_PAT_CMP_CPT);
+                u4TimeCnt --;
+                mcDELAY_US(1);
+            }while ((u4Ready == 0) && (u4TimeCnt > 0));
+
+            if (u4TimeCnt == 0)//time out
+            {
+                mcSHOW_ERR_MSG(("[CBTDelayCACLKCompare] Resp fail (time out)\n"));
+                mcFPRINTF((fp_A60868, "[CBTDelayCACLKCompare] Resp fail (time out)\n"));//Eddie Test
+                //return DRAM_FAIL;
+            }
+
+            u4dq_o1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQO1), MISC_DQO1_DQO1_RO);
+
+            u4dq_o1 = CBTCompareWordaroundDecodeO1Pinmux(p, u4dq_o1, uiLPDDR_O1_Mapping);
+
+            if (u1dq_end >= u1ca_number_per_bit)
+                u4ca_pattern |= u4ca_pattern << u1bit_num_per_byte;
+
+            u4dq_o1 ^= u4ca_pattern;
+
+            for(u1dq_index=u1dq_start; u1dq_index<=u1dq_end; u1dq_index++)
+            {
+                if ((p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) && (u1dq_index == u1ca_number_per_bit))
+                    u1dq_index = u1bit_num_per_byte;
+
+                u4data_receive = (u4dq_o1 >> u1dq_index) & 0x1;
+
+                if (u1dq_index < u1bit_num_per_byte)
+                    u4Result |= u4data_receive << u1dq_index;
+                else
+                    u4Result |= u4data_receive << u1dq_index - u1bit_num_per_byte;
+            }
+
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), 0, CBT_WLEV_CTRL5_NEW_CBT_CAPATEN);
+        }
+        if (u4Result == ((0x1 << u1ca_number_per_bit) - 1))
+            break;
+    }
+    return u4Result;
+}
+#endif
+
+void CmdOEOnOff(DRAMC_CTX_T *p, U8 u1OnOff, CMDOE_DIS_CHANNEL CmdOeDisChannelNUM)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    if (CmdOeDisChannelNUM ==CMDOE_DIS_TO_ALL_CHANNEL)
+    {
+        if (!isLP4_DSC)
+        {
+            vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld(!u1OnOff, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA)
+                                                    | P_Fld(u1OnOff, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA)
+                                                    | P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA));
+        }
+        else
+        {
+            vIO32WriteFldMulti_All(DDRPHY_REG_B1_DQ2, P_Fld(!u1OnOff, B1_DQ2_RG_TX_ARDQ_OE_DIS_B1)
+                                                    | P_Fld(u1OnOff, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1)
+                                                    | P_Fld(0xff, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1));
+        }
+    }
+    else//(CmdOeDisChannelNUM ==CMDOE_DIS_TO_ONE_CHANNEL)
+    {
+        if (!isLP4_DSC)
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld(!u1OnOff, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA)
+                                                    | P_Fld(u1OnOff, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA)
+                                                    | P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA));
+        }
+        else
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), P_Fld(!u1OnOff, B1_DQ2_RG_TX_ARDQ_OE_DIS_B1)
+                                                    | P_Fld(u1OnOff, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1)
+                                                    | P_Fld(0xff, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1));
+        }
+    }
+
+
+}
+
+void CBTDelayCACLK(DRAMC_CTX_T *p, S32 iDelay)
+{
+    if (iDelay < 0)
+    {   /* Set CLK delay */
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0),
+            P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CMD) |
+            P_Fld(-iDelay, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
+            P_Fld(-iDelay, SHU_R0_CA_CMD0_RG_ARPI_CS));
+    }
+/*
+    else if (iDelay >= 64)
+    {
+        DramcCmdUIDelaySetting(p, 2);
+
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0),
+            P_Fld(iDelay - 64, SHU_R0_CA_CMD0_RG_ARPI_CMD) |
+            P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
+            P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CS));
+    }
+*/
+    else
+    {   /* Set CA output delay */
+//      DramcCmdUIDelaySetting(p, 0);
+
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0),
+            P_Fld(iDelay, SHU_R0_CA_CMD0_RG_ARPI_CMD) |
+            P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
+            P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CS));
+    }
+}
+#if 0
+static void CATrainingPosCal(DRAMC_CTX_T *p, U8* pu1DieNum, S8* ps1CAMacroDelay, S16 *ps1CACenterDiff, U8 u1CABitNum)
+{
+    U8 u1RankIdx, u1DieIdx, u1CAIdx;
+    S8 s1Intersect_min, s1Intersect_max;
+    S8 s1Intersect_min_byBit[CATRAINING_NUM], s1Intersect_max_byBit[CATRAINING_NUM], s1CACenter_min;//, s1CACenter[CATRAINING_NUM];
+    S8 s1TempFirstPass, s1TempLastPass;
+    U8 u1PerBitDelayCellEnable =0;
+    S8 s1CACenter[CATRAINING_NUM];
+
+#if CA_PER_BIT_DELAY_CELL
+    u1PerBitDelayCellEnable = 1;
+#endif
+
+    mcSHOW_DBG_MSG(("\n[CATrainingPosCal] consider %d rank data\n", p->rank +1));
+
+    s1Intersect_min = -127; // 127
+    s1Intersect_max = 127; //-127
+    s1CACenter_min = 0x7f;
+
+    for(u1CAIdx=0; u1CAIdx < u1CABitNum; u1CAIdx++)
+    {
+        s1Intersect_min_byBit[u1CAIdx] = -127; // 127
+        s1Intersect_max_byBit[u1CAIdx] = 127; //-127
+
+        for (u1RankIdx = RANK_0; u1RankIdx <= p->rank; u1RankIdx++)
+        {
+            for (u1DieIdx = 0; u1DieIdx < pu1DieNum[u1RankIdx]; u1DieIdx++)
+            {
+                s1TempFirstPass = iFirstCAPass[u1RankIdx][u1DieIdx][u1CAIdx];
+                s1TempLastPass = iLastCAPass[u1RankIdx][u1DieIdx][u1CAIdx];
+                //mcSHOW_DBG_MSG(("RK%d, Die%d ,CA%d,iFirstCAPass = %d, iLastCAPass=%d \n",u1RankIdx, u1DieIdx, u1CAIdx, s1TempFirstPass, s1TempLastPass));
+
+                // Intersection by Macro
+                if(s1TempFirstPass > s1Intersect_min)
+                    s1Intersect_min = s1TempFirstPass;
+
+                if(s1TempLastPass < s1Intersect_max)
+                    s1Intersect_max = s1TempLastPass;
+
+                // intersection by CA bit
+                if(s1TempFirstPass > s1Intersect_min_byBit[u1CAIdx])
+                    s1Intersect_min_byBit[u1CAIdx] = s1TempFirstPass;
+
+                if(s1TempLastPass < s1Intersect_max_byBit[u1CAIdx])
+                    s1Intersect_max_byBit[u1CAIdx] = s1TempLastPass;
+            }
+        }
+
+        s1CACenter[u1CAIdx] = s1Intersect_min_byBit[u1CAIdx] + (s1Intersect_max_byBit[u1CAIdx] - s1Intersect_min_byBit[u1CAIdx])/2;
+
+        if(s1CACenter[u1CAIdx] < s1CACenter_min)
+            s1CACenter_min = s1CACenter[u1CAIdx];
+    }
+
+    // If CA perbit, choose min CA PI of all bits.
+    // If CA perbyte, choose middle position of intersenction range of all bits.
+
+    // CA perbit enable
+    if(u1PerBitDelayCellEnable && (p->u2DelayCellTimex100 !=0))
+    {
+        if(s1CACenter_min <0) //don't move clk
+        {
+            //mcSHOW_DBG_MSG(("warning : Minimum CA PI delay is %d(<0) and changed to 0\n", s1CACenter_min));
+            s1CACenter_min =0;
+        }
+
+        *ps1CAMacroDelay = s1CACenter_min;
+
+        mcSHOW_DBG_MSG(("u2DelayCellTimex100 = %d/100 ps\n", p->u2DelayCellTimex100));
+
+        for(u1CAIdx=0; u1CAIdx < u1CABitNum; u1CAIdx++)
+        {
+            if(s1CACenter[u1CAIdx] <0) //don't move clk
+            {
+                s1CACenter[u1CAIdx] =0;
+                ps1CACenterDiff[u1CAIdx]=0;
+            }
+            else
+            {
+                ps1CACenterDiff[u1CAIdx] = s1CACenter[u1CAIdx] - s1CACenter_min;
+            }
+
+            mcSHOW_DBG_MSG(("CA%d delay=%d (%d~%d),", u1CAIdx, s1CACenter[u1CAIdx], s1Intersect_min_byBit[u1CAIdx], s1Intersect_max_byBit[u1CAIdx]));
+            mcSHOW_DBG_MSG(("Diff = %d PI ", ps1CACenterDiff[u1CAIdx]));
+            ps1CACenterDiff[u1CAIdx] = (ps1CACenterDiff[u1CAIdx]*100000000/(DDRPhyGetRealFreq(p)<<6))/p->u2DelayCellTimex100;
+            mcSHOW_DBG_MSG(("(%d cell)", ps1CACenterDiff[u1CAIdx]));
+
+            //mcDUMP_REG_MSG(("CA%d delay=%d (%d~%d),", u1CAIdx, s1CACenter[u1CAIdx], s1Intersect_min_byBit[u1CAIdx], s1Intersect_max_byBit[u1CAIdx]));
+            //mcDUMP_REG_MSG(("Diff = %d PI ", ps1CACenterDiff[u1CAIdx]));
+            //mcDUMP_REG_MSG(("(%d cell)\n", ps1CACenterDiff[u1CAIdx]));
+
+            if(ps1CACenterDiff[u1CAIdx]>0x7f)
+            {
+                mcSHOW_DBG_MSG(("[WARNING] CA%d delay cell %d >15, adjust to 15 cell", u1CAIdx, ps1CACenterDiff[u1CAIdx]));
+                //mcDUMP_REG_MSG(("[WARNING] CA%d delay cell %d >15, adjust to 15 cell\n", u1CAIdx, ps1CACenterDiff[u1CAIdx]));
+                ps1CACenterDiff[u1CAIdx] =0x7f;
+            }
+
+            mcSHOW_DBG_MSG(("\n"));
+
+#ifdef FOR_HQA_REPORT_USED
+            if (gHQALog_flag == 1)
+            {
+                HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_2, "CA_PosCal_Cell", " ", u1CAIdx, ps1CACenterDiff[u1CAIdx], NULL);
+            }
+#endif
+        }
+
+        mcSHOW_DBG_MSG(("\nCA PerBit enable=%d, CA PI delay=%d\n", u1PerBitDelayCellEnable, *ps1CAMacroDelay));
+    }
+    else //CA perbyte
+    {
+        *ps1CAMacroDelay = s1Intersect_min + (s1Intersect_max - s1Intersect_min)/2;
+
+        if(*ps1CAMacroDelay <0)//don't move clk
+        {
+            //mcSHOW_DBG_MSG(("warning : CA PI delay is %d(<0) and changed to 0\n", *ps1CAMacroDelay));
+            *ps1CAMacroDelay =0;
+        }
+        mcSHOW_DBG_MSG(("CA PerBit enable=%d, CA PI delay=%d (%d~%d)\n", u1PerBitDelayCellEnable, *ps1CAMacroDelay, s1Intersect_min, s1Intersect_max));
+    }
+}
+#endif
+#if 0
+static u32 new_cbt_pat_result(DRAMC_CTX_T *p)
+{
+	u32 res = 0, res0 = 0, res_final = 0;
+	u32 fld;
+
+	if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) {
+#if __LP5_COMBO__
+		if (is_lp5_family(p))
+			fld = CBT_WLEV_STATUS2_CBT_PAT_CMP_ERR_B0;
+		else
+#endif
+			fld = CBT_WLEV_STATUS2_CBT_PAT_CMP_ERR_B1;
+
+		res = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS2), fld);
+	} else {
+		res0 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS2),
+				CBT_WLEV_STATUS2_CBT_PAT_CMP_ERR_B0);
+		res = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS2),
+				CBT_WLEV_STATUS2_CBT_PAT_CMP_ERR_B1);
+	}
+
+	res_final = res | res0;
+
+	return res_final;
+}
+#endif
+#if 0
+static u32 new_cbt_pat_compare(DRAMC_CTX_T *p)
+{
+    u32 res_final = 0;
+    u32 time_cnt, rdy;
+
+    time_cnt = TIME_OUT_CNT;
+
+#if CBT_O1_PINMUX_WORKAROUND
+    res_final = new_cbt_pat_compare_workaround(p, &ncm);
+#else
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), 1, CBT_WLEV_CTRL5_NEW_CBT_CAPATEN);
+
+
+    do {
+        rdy = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS2),
+                CBT_WLEV_STATUS2_CBT_PAT_CMP_CPT);
+        time_cnt--;
+        mcDELAY_US(1);
+    } while ((rdy == 0) && (time_cnt > 0));
+
+    if (time_cnt == 0) {
+        mcSHOW_DBG_MSG(("[new_cbt_pat_compare] Resp fail (time out)\n"));
+        //return DRAM_FAIL;
+    }
+
+    res_final = new_cbt_pat_result(p);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), 0, CBT_WLEV_CTRL5_NEW_CBT_CAPATEN);
+#endif
+
+    return res_final; // return pattern compre result
+}
+#endif
+#if 0
+static u32 new_cs_pat_compare(DRAMC_CTX_T *p)
+{
+	u32 res_final = 0;
+	u32 time_cnt, rdy;
+
+	time_cnt = TIME_OUT_CNT;
+
+	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), 1, CBT_WLEV_CTRL5_NEW_CBT_CAPATEN);
+
+	do {
+		rdy = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS2),
+				CBT_WLEV_STATUS2_CBT_PAT_CMP_CPT);
+		time_cnt--;
+		mcDELAY_US(1);
+	} while ((rdy == 0) && (time_cnt > 0));
+
+	if (time_cnt == 0) {
+		mcSHOW_ERR_MSG(("[new_cs_pat_compare] Resp fail (time out)\n"));
+		//return DRAM_FAIL;
+	}
+
+	res_final = new_cbt_pat_result(p);
+
+	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), 0, CBT_WLEV_CTRL5_NEW_CBT_CAPATEN);
+
+	return res_final; // return pattern compre result
+}
+#endif
+#if CBT_OLDMODE_SUPPORT
+#if 0
+static U32 CBTDelayCACLKCompare(DRAMC_CTX_T *p)
+{
+    U32 u4Result = 0, u4Result0 = 0, u4Ready, res_final = 0;
+    U32 u4Fld, u4TimeCnt;
+
+    u4TimeCnt = TIME_OUT_CNT;
+
+#if CBT_O1_PINMUX_WORKAROUND
+    res_final = CBTDelayCACLKCompareWorkaround(p);
+#else /* Without WA */
+    //Let R_DMTESTCATRAIN=1 to enable HW CAPAT Generator
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 1, CBT_WLEV_CTRL0_CBT_CAPATEN);
+
+    //Check CA training compare ready (dramc_conf_nao 0x3fc , CATRAIN_CMP_CPT)
+    do
+    {
+        u4Ready = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS1), CBT_WLEV_STATUS1_CATRAIN_CMP_CPT);
+        u4TimeCnt --;
+        mcDELAY_US(1);
+    }while ((u4Ready == 0) && (u4TimeCnt > 0));
+
+    if (u4TimeCnt == 0)//time out
+    {
+        mcSHOW_ERR_MSG(("[CBTDelayCACLKCompare] Resp fail (time out)\n"));
+
+        mcFPRINTF((fp_A60868, "[CBTDelayCACLKCompare] Resp fail (time out)\n"));//Eddie Test
+
+        //return DRAM_FAIL;
+    }
+
+    //Get CA training compare result (dramc_conf_nao 0x3fc , CATRAIN_CMP_ERR)
+        if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE)
+        {
+#if __LP5_COMBO__
+            if (is_lp5_family(p))
+                u4Fld = CBT_WLEV_STATUS1_CATRAIN_CMP_ERR_B0;
+            else
+#endif
+                u4Fld = CBT_WLEV_STATUS1_CATRAIN_CMP_ERR_B1;
+
+            u4Result = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS1), u4Fld);
+        }
+        else
+        {
+            u4Result0 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS1), CBT_WLEV_STATUS1_CATRAIN_CMP_ERR_B0);
+//            mcSHOW_DBG_MSG(("[Francis] TCMDO1LAT_CATRAIN_CMP_ERR0=0x%x\n", u4Result0));
+            u4Result = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS1), CBT_WLEV_STATUS1_CATRAIN_CMP_ERR_B1);
+//            mcSHOW_DBG_MSG(("[Francis] TCMDO1LAT_CATRAIN_CMP_ERR=0x%x\n", u4Result));
+        }
+
+    res_final = (u4Result | u4Result0);
+
+    //Let R_DMTESTCATRAIN=0 to disable HW CAPAT Generator
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0, CBT_WLEV_CTRL0_CBT_CAPATEN);
+#endif
+
+    return res_final; // return pattern compre result
+}
+#endif
+#endif
+#if 0
+static U32 CBTDelayCSCompare(DRAMC_CTX_T *p, U32 uiDelay)
+{
+    U32 u4Result, u4Golden, u4Ready;
+    U32 u4TimeCnt;
+    U32 u4dq_o1;
+#if (fcFOR_CHIP_ID==fcA60868)
+    U8 *uiLPDDR_O1_Mapping = NULL;
+    U32 u4byte_index;
+#endif
+
+    u4TimeCnt = TIME_OUT_CNT;
+
+#if (fcFOR_CHIP_ID==fcA60868)
+#if (__LP5_COMBO__)
+    if (is_lp5_family(p)) {
+        uiLPDDR_O1_Mapping = (U8 *)uiLPDDR5_O1_Mapping_POP[p->channel];
+    } else
+#endif
+    {
+        uiLPDDR_O1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[p->channel];
+    }
+#endif
+
+    //Step 5: toggle CS/CA for CS training by R_DMTCMDEN (wait dramc_nao tcmd_response=1, disable R_DMTCMDEN), 0x1e4[5]
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 1, CBT_WLEV_CTRL0_TCMDEN);
+    do
+    {
+        u4Ready = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_TCMD_RESPONSE);
+        u4TimeCnt --;
+        mcDELAY_US(1);
+    }while ((u4Ready == 0) && (u4TimeCnt > 0));
+
+
+    if (u4TimeCnt == 0)//time out
+    {
+        mcSHOW_ERR_MSG(("[CBTDelayCSCompare] Resp fail (time out)\n"));
+        //return DRAM_FAIL;
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0, CBT_WLEV_CTRL0_TCMDEN);
+
+    //Step 6: check CS training result on DQ[13:8] by O1, DDRPHYCFG 0xF80
+    //Expected CA value is h2a (CA pulse width is 6UI, CS pulse is 1UI)
+    u4dq_o1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQO1), MISC_DQO1_DQO1_RO);
+    u4Golden = 0x2a;
+    u4Result = 0;
+
+#if (fcFOR_CHIP_ID==fcA60868)
+#if __LP5_COMBO__
+    if (is_lp5_family(p)) {
+        for (u4byte_index = 0; u4byte_index <= 6; u4byte_index++)
+        {
+            u4Result |= (((u4dq_o1 & (1 << uiLPDDR_O1_Mapping[u4byte_index])) >> (uiLPDDR_O1_Mapping[u4byte_index])) << (u4byte_index));
+        }
+    }
+    else
+#endif
+    {
+        for (u4byte_index = 8; u4byte_index <= 13; u4byte_index++) {
+            u4Result |= (((u4dq_o1 & (1 << uiLPDDR_O1_Mapping[u4byte_index])) >> (uiLPDDR_O1_Mapping[u4byte_index])) << (u4byte_index - 8));
+        }
+    }
+#else
+#if __LP5_COMBO__
+        if (is_lp5_family(p)) {
+            u4Result = (u4dq_o1& 0x7F);		// ignore DQ7
+        }
+        else
+#endif
+        {
+            u4Result = (u4dq_o1& 0xFF00)>>8;
+        }
+#endif
+
+    return u4Result ^ u4Golden; // return pattern compre result
+}
+#endif
+
+#if CBT_AUTO_K_SUPPORT
+/*
+ * cbt_catrain_autok -- ca autok
+ * @initpi: init pi select
+ * @steps: sweep how many pi step, 1 ~ 64
+ * @respi: step resolution, 0,1,2,3. that means 1, 2, 4, 8 pis
+ *
+ */
+#if 0
+static int cbt_catrain_autok(DRAMC_CTX_T *p,
+        u8 initpi, u8 steps, u8 respi,
+        u32 *cmp0_array, u32 *cmp1_array,
+        u8 n)
+{
+    u8 lenpi;
+    int res;
+
+    if (steps == 0)
+        steps = 1;
+
+    lenpi = steps - 1;
+
+    return cbt_wlev_train_autok(p, AUTOK_CA, initpi, lenpi, respi,
+            cmp0_array, cmp1_array, n);
+}
+
+static int cbt_cstrain_autok(DRAMC_CTX_T *p,
+        u8 initpi, u8 steps, u8 respi,
+        u32 *cmp0, u32 *cmp1)
+{
+    u8 lenpi;
+
+    if (steps == 0)
+        steps = 1;
+
+    lenpi = steps - 1;
+
+    return cbt_wlev_train_autok(p, AUTOK_CS,
+            initpi, lenpi, respi, cmp0, cmp1, 1);
+}
+
+/*
+ * cbt_catrain_autok_next_window -- find next zero window
+ * @bitmap: window map
+ * @start_pos: start position to find
+ * @initpi: init pi select
+ * @steps: sweep how many pi step, 1 ~ 64
+ * @respi: step resolution, 0, 1, 2, 3
+ * @pwin: window boundary to store
+ *
+ * return 1 if found window, 0 otherwise.
+ */
+static int cbt_catrain_autok_next_window(DRAMC_CTX_T *p,
+        u32 *bitmap, u8 start_pos,
+        u8 initpi, u8 steps, u8 respi,
+        PASS_WIN_DATA_T *pwin)
+{
+    u8 lenpi;
+    u8 sweep_max_cnt, win_left, win_right;
+    int res;
+
+    if (steps == 0)
+        steps = 1;
+
+    lenpi = steps - 1;
+
+    sweep_max_cnt = get_autok_sweep_max_cnt(lenpi, respi);
+    res = find_zero_window(bitmap, start_pos, sweep_max_cnt - 1,
+                &win_left, &win_right);
+
+    if (!res) {
+        mcSHOW_DBG_MSG4(("can't find zero window.\n"));
+        return 0;
+    } else {
+        mcSHOW_DBG_MSG4(("find max zero window [%d, %d]\n",
+            win_left, win_right));
+        pwin->first_pass = initpi + win_left * (1 << respi);
+        pwin->last_pass = initpi + win_right * (1 << respi);
+        return 1;
+    }
+}
+static void cbt_autok_maxwindow(DRAMC_CTX_T *p,
+    u32 *bitmap, u8 uiDelay, u8 pi_step, u8 steps, u8 respi,
+    S32 *iFirstPass, S32 *iLastPass)
+{
+    int res;
+    u8 start_pos;
+    PASS_WIN_DATA_T win;
+
+    start_pos = 0;
+
+    while (1)
+    {
+        res = cbt_catrain_autok_next_window(p,
+                bitmap, start_pos,
+                uiDelay, steps, respi, &win);
+
+        if (!res)
+        {
+            /*
+             * autok not find pass window
+             */
+            mcSHOW_DBG_MSG2(("no window @pi [%d, %d]\n",
+                        uiDelay + start_pos,
+                        uiDelay + pi_step - 1));
+
+            if ((*iFirstPass != PASS_RANGE_NA) &&
+                    (*iLastPass == PASS_RANGE_NA))
+            {
+                /* window has left boundary */
+                if ((uiDelay - *iFirstPass) < 5) /* prevent glitch */
+                {
+                    *iFirstPass = PASS_RANGE_NA;
+                }
+                else
+                {
+                    *iLastPass = uiDelay - pi_step;
+                }
+            }
+
+            /* ca no pass window yet, break while-1 loop */
+            break;
+        }
+        else
+        {
+            /*
+             * autok find pass window
+             */
+            mcSHOW_DBG_MSG2(("find pi pass window [%d, %d] in [%d, %d]\n",
+                        win.first_pass, win.last_pass,
+                        uiDelay, uiDelay + pi_step - 1));
+
+            /* adjust start_pos to find next pass window */
+            start_pos = win.last_pass - uiDelay + 1;
+
+            if (*iFirstPass == PASS_RANGE_NA)
+            {
+                *iFirstPass = win.first_pass;
+            }
+            else if (*iLastPass != PASS_RANGE_NA)
+            {
+                /* have pass window yet */
+                if (*iLastPass + (1 << respi) >= win.first_pass)
+                {
+                    *iLastPass = win.last_pass;
+                }
+                else
+                {
+                    /* wind is NOT continuous  and larger size */
+                    if (win.last_pass - win.first_pass >= *iLastPass - *iFirstPass)
+                    {
+                        *iFirstPass = win.first_pass;
+                        *iLastPass = win.last_pass;
+                    }
+                }
+                continue; /* find next window */
+            }
+
+            if (*iLastPass == PASS_RANGE_NA)
+            {
+                if ((win.last_pass - *iFirstPass) < 5) /* prevent glitch */
+                {
+                    *iFirstPass = PASS_RANGE_NA;
+                    continue;
+                }
+
+                *iLastPass = win.last_pass;
+            }
+        }
+    } /* while (1) */
+}
+#endif
+#endif
+#if 0
+static void DramcCmdBusTrainingPostProcess(DRAMC_CTX_T *p)
+{
+    S32 iCSFinalClkDelay=0, iCSFinalCmdDelay, iCSFinalCSDelay;
+    U8 backup_rank, irank;
+
+    // CBT Rank0/1 must set Clk/CA/CS the same from Wei-Jen
+
+    mcSHOW_DBG_MSG(("[DramcCmdBusTrainingPostProcess] p->frequency=%d\n", p->frequency));
+
+    backup_rank = u1GetRank(p);
+
+    iCSFinalCmdDelay = (CATrain_CmdDelay[p->channel][RANK_0] + CATrain_CmdDelay[p->channel][RANK_1]) / 2;
+    CATrain_CmdDelay[p->channel][RANK_0] = iCSFinalCmdDelay;
+    CATrain_CmdDelay[p->channel][RANK_1] = iCSFinalCmdDelay;
+
+    iCSFinalCSDelay = (CATrain_CsDelay[p->channel][RANK_0] + CATrain_CsDelay[p->channel][RANK_1]) / 2;
+    CATrain_CsDelay[p->channel][RANK_0] = iCSFinalCSDelay;
+    CATrain_CsDelay[p->channel][RANK_1] = iCSFinalCSDelay;
+
+    for (irank = RANK_0; irank < RANK_MAX; irank++)
+    {
+        vSetRank(p, irank);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), P_Fld(iCSFinalClkDelay, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
+                                                                  P_Fld(iCSFinalCmdDelay, SHU_R0_CA_CMD0_RG_ARPI_CMD) |
+                                                                  P_Fld(iCSFinalCSDelay, SHU_R0_CA_CMD0_RG_ARPI_CS));
+    }
+
+    mcSHOW_DBG_MSG(("Clk Dly = %d\nCmd Dly = %d\nCS Dly = %d\n", iCSFinalClkDelay, iCSFinalCmdDelay, iCSFinalCSDelay));
+
+    vSetRank(p, backup_rank);
+
+}
+#endif
+static void CBTAdjustCS(DRAMC_CTX_T *p, int autok)
+{
+    S32 iCSFinalDelay = 0;//iFirstCSPass = 0, iLastCSPass = 0, iCSCenter
+    //U32 uiDelay, u4ValueReadBack, u4CSWinSize;
+    U8 backup_rank, ii;
+    //u32 pi_start, pi_end, pi_step;
+    u32 pi_dly;
+    u32 cs_ui, cs_mck;
+    //u16 u2HalfCSWin;
+    //u8 idx = 0;
+    //u8 step_respi = AUTOK_RESPI_1;
+    //u32 capi_max;
+
+    backup_rank = u1GetRank(p);
+
+    cs_ui = get_cs_ui(p);
+    cs_mck = get_cs_mck(p);
+
+#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_CBT)
+    if (p->femmc_Ready == 1)
+    {
+        CATrain_CsDelay[p->channel][p->rank] = p->pSavetimeData->u1CBTCsDelay_Save[p->channel][p->rank];
+    }
+#endif
+
+    // if dual rank, use average position of both rank
+    if(backup_rank == RANK_1)
+    {
+        iCSFinalDelay = (CATrain_CsDelay[p->channel][RANK_0] + CATrain_CsDelay[p->channel][RANK_1]) >> 1;
+    }
+    else
+    {
+        iCSFinalDelay = CATrain_CsDelay[p->channel][p->rank];
+    }
+
+    //Set CS output delay after training
+    /* p->rank = RANK_0, save to Reg Rank0 and Rank1, p->rank = RANK_1, save to Reg Rank1 */
+    for (ii = RANK_0; ii <= backup_rank; ii++)
+    {
+        vSetRank(p, ii);
+
+        pi_dly = adjust_cs_ui(p, cs_mck, cs_ui, iCSFinalDelay);
+
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), pi_dly, SHU_R0_CA_CMD0_RG_ARPI_CS);
+
+#ifdef FOR_HQA_REPORT_USED
+        if (gHQALog_flag == 1)
+        {
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, "CS_Center", " ", 0, pi_dly, NULL);
+        }
+#endif
+    }
+
+    vSetRank(p, backup_rank);
+
+    //Also for Dump_Reg
+    //mcSHOW_DBG_MSG(("CS delay=%d (%d~%d)\n", iCSFinalDelay, iFirstCSPass, iLastCSPass));
+    //mcDUMP_REG_MSG(("CS delay=%d (%d~%d)\n", iCSFinalDelay, iFirstCSPass, iLastCSPass));
+}
+
+#if CA_PER_BIT_DELAY_CELL
+static void CATrainingSetPerBitDelayCell(DRAMC_CTX_T *p, S16 *iCAFinalCenter, U8 ca_pin_num)
+{
+    U8 *uiLPDDR_CA_Mapping = NULL;
+    U8 u1CA;
+    S8 iCA_PerBit_DelayLine[8] = {0};
+
+#if __LP5_COMBO__
+    if (is_lp5_family(p))
+    {
+        uiLPDDR_CA_Mapping = (U8 *)uiLPDDR5_CA_Mapping_POP[p->channel];
+    }
+    else
+#endif
+    {
+        uiLPDDR_CA_Mapping = (U8 *)uiLPDDR4_CA_Mapping_POP[p->channel];
+    }
+
+    for (u1CA = 0;u1CA < ca_pin_num;u1CA++)
+    {
+        iCA_PerBit_DelayLine[uiLPDDR_CA_Mapping[u1CA]] = iCAFinalCenter[u1CA];
+    }
+
+    // Set CA perbit delay line calibration results
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_TXDLY0),
+            P_Fld(iCA_PerBit_DelayLine[0], SHU_R0_CA_TXDLY0_TX_ARCA0_DLY) |
+            P_Fld(iCA_PerBit_DelayLine[1], SHU_R0_CA_TXDLY0_TX_ARCA1_DLY) |
+            P_Fld(iCA_PerBit_DelayLine[2], SHU_R0_CA_TXDLY0_TX_ARCA2_DLY) |
+            P_Fld(iCA_PerBit_DelayLine[3], SHU_R0_CA_TXDLY0_TX_ARCA3_DLY));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_TXDLY1),
+            P_Fld(iCA_PerBit_DelayLine[4], SHU_R0_CA_TXDLY1_TX_ARCA4_DLY) |
+            P_Fld(iCA_PerBit_DelayLine[5], SHU_R0_CA_TXDLY1_TX_ARCA5_DLY) |
+            P_Fld(iCA_PerBit_DelayLine[6], SHU_R0_CA_TXDLY1_TX_ARCA6_DLY) |
+            P_Fld(iCA_PerBit_DelayLine[7], SHU_R0_CA_TXDLY1_TX_ARCA7_DLY));
+}
+#endif// end of CA_PER_BIT_DELAY_CELL
+
+static void CBTSetCACLKResult(DRAMC_CTX_T *p, U32 u4MCK, U32 u4UI, U8 ca_pin_num)
+{
+    S8 iFinalCACLK;
+    U8 backup_rank, rank_i, uiCA;
+    S16 iCAFinalCenter[CATRAINING_NUM]={0}; //for CA_PER_BIT
+
+#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_CBT)
+    if (p->femmc_Ready == 1)
+    {
+        CATrain_CmdDelay[p->channel][p->rank] = p->pSavetimeData->s1CBTCmdDelay_Save[p->channel][p->rank];
+        vSetCalibrationResult(p, DRAM_CALIBRATION_CA_TRAIN, DRAM_FAST_K);
+    #if CA_PER_BIT_DELAY_CELL
+        for (uiCA = 0; uiCA < ca_pin_num; uiCA++)
+            iCAFinalCenter[uiCA] = p->pSavetimeData->u1CBTCA_PerBit_DelayLine_Save[p->channel][p->rank][uiCA];
+    #endif
+    }
+#endif
+
+    iFinalCACLK = CATrain_CmdDelay[p->channel][p->rank];
+
+    mcSHOW_DBG_MSG(("\n[CBTSetCACLKResult] CA Dly = %d\n", iFinalCACLK));
+
+    iFinalCACLK = adjust_ca_ui(p, u4MCK, u4UI, iFinalCACLK);
+
+    backup_rank = u1GetRank(p);
+
+    for (rank_i = RANK_0; rank_i <=  p->support_rank_num;rank_i++)
+    {
+        vSetRank(p, rank_i);
+
+        CBTDelayCACLK(p, iFinalCACLK);
+
+#if CA_PER_BIT_DELAY_CELL
+        CATrainingSetPerBitDelayCell(p, iCAFinalCenter, ca_pin_num);
+#endif
+    }
+
+    vSetRank(p, backup_rank);
+}
+
+#if (__LP5_COMBO__)
+/* Return (Vref_B0 | (Vref_B1 << 8) to support Byte mode */
+static U8 GetCBTVrefPinMuxValue_lp5(DRAMC_CTX_T *p, U8 u1VrefLevel)
+{
+    U8 u2VrefBit, u2Vref_org;
+    U16 u2Vref_new;
+
+    u2Vref_org = u1VrefLevel & 0x7f;
+
+    u2Vref_new = 0;
+
+    for (u2VrefBit = 0; u2VrefBit < 8; u2VrefBit++)
+    {
+        //mcSHOW_DBG_MSG(("=== u2VrefBit: %d, %d\n",u2VrefBit,uiLPDDR4_O1_Mapping_POP[p->channel][u2VrefBit]));
+        if (u2Vref_org & (1 << u2VrefBit))
+        {
+            u2Vref_new |= (1 << uiLPDDR5_O1_Mapping_POP[p->channel][u2VrefBit]);
+        }
+    }
+
+    mcSHOW_DBG_MSG4(("=== u2Vref_new: 0x%x --> 0x%x\n", u2Vref_org, u2Vref_new));
+
+    if (lp5_cp[p->channel].dram_dq_b0)
+        u2Vref_new >>= 8;
+
+    return u2Vref_new;
+}
+
+#endif
+
+static U8 GetCBTVrefPinMuxValue(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel)
+{
+    U8 u2VrefBit, u2Vref_org;
+    U16 u2Vref_new;
+
+    if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1)
+        return ((u1VrefRange & 0x1) << 6) | (u1VrefLevel & 0x3f);
+
+    u2Vref_org = ((u1VrefRange & 0x1) << 6) | (u1VrefLevel & 0x3f);
+
+    u2Vref_new = 0;
+    for (u2VrefBit = 0; u2VrefBit < 8; u2VrefBit++)
+    {
+        //mcSHOW_DBG_MSG(("=== u2VrefBit: %d, %d\n",u2VrefBit,uiLPDDR4_O1_Mapping_POP[p->channel][u2VrefBit]));
+        if (u2Vref_org & (1 << u2VrefBit))
+        {
+            u2Vref_new |= (1 << uiLPDDR4_O1_Mapping_POP[p->channel][u2VrefBit]);
+        }
+    }
+
+    mcSHOW_DBG_MSG4(("=== u2Vref_new: 0x%x --> 0x%x\n", u2Vref_org, u2Vref_new));
+
+    if (lp4_cp[p->channel].dram_dq_b0)
+        u2Vref_new >>= 8;
+
+    return u2Vref_new;
+}
+
+#if 0
+static U8 GetCBTVrefPinMuxRevertValue(DRAMC_CTX_T *p, U8 u1VrefLevel)
+{
+    U8 u2VrefBit, u2Vref_new, u2Vref_org;
+
+    if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1)
+        return u1VrefLevel;
+
+    u2Vref_new = 0;
+    u2Vref_org = u1VrefLevel;
+    for (u2VrefBit = 0; u2VrefBit < 8; u2VrefBit++)
+    {
+#if (__LP5_COMBO__)
+        if (is_lp5_family(p)) {
+            u2Vref_new |= ((u2Vref_org >> uiLPDDR5_O1_Mapping_POP[p->channel][u2VrefBit]) & 1) << u2VrefBit;
+        } else
+#endif
+        u2Vref_new |= ((u2Vref_org >> uiLPDDR4_O1_Mapping_POP[p->channel][u2VrefBit]) & 1) << u2VrefBit;
+    }
+
+    mcSHOW_DBG_MSG4(("=== Revert u2Vref_new: 0x%x --> 0x%x\n", u2Vref_org, u2Vref_new));
+
+    return u2Vref_new;
+}
+#endif
+static void CBTSetVrefLP4(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel, U8 operating_fsp, U8 stateFlag)
+{
+    U32 fld;
+    U8 u4DbgValue;
+    U8 u1VrefValue_pinmux;
+    struct cbt_pinmux *cp = &lp4_cp[p->channel];
+
+    if ((p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) &&
+        (stateFlag == IN_CBT))
+    {
+        u1VrefValue_pinmux = GetCBTVrefPinMuxValue(p, u1VrefRange, u1VrefLevel);
+
+#if !REDUCE_LOG_FOR_PRELOADER
+        mcSHOW_DBG_MSG(("\nCH_%d, RK_%d, Range=%d, VrefValue_pinmux = 0x%x\n", p->channel, p->rank, u1VrefRange, u1VrefValue_pinmux));
+#endif
+        u1MR12Value[p->channel][p->rank][operating_fsp] = ((u1VrefRange & 0x1) << 6) | u1VrefLevel;
+
+        fld = (cp->dram_dq_b0) ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0;
+
+        //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_WRITE_LEV), ((u1VrefRange&0x1) <<6) | (u1VrefLevel & 0x3f), WRITE_LEV_DMVREFCA);  //MR12, bit[25:20]=OP[5:0]  bit 26=OP[6]
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
+            u1VrefValue_pinmux, fld);  //MR12, bit[25:20]=OP[5:0]  bit 26=OP[6]
+
+         //DQS_SEL=1, DQS_B1_G=1, Toggle R_DMDQS_WLEV (1 to 0)
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), (0x1 << cp->dram_dq_b0), CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3), 0xa, CBT_WLEV_CTRL3_DQSBX_G);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 1, CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG);
+        mcDELAY_US(1);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0, CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG);
+
+    }
+    else
+    {
+        if (operating_fsp == FSP_1)
+        {
+            DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, TO_MR);
+        }
+
+        u4DbgValue = (((u1VrefRange & 0x1) << 6) | (u1VrefLevel & 0x3f));
+        u1MR12Value[p->channel][p->rank][operating_fsp] = u4DbgValue;
+        mcSHOW_DBG_MSG5(("u4DbgValue = 0x%x\n", u4DbgValue));
+
+        DramcModeRegWriteByRank(p, p->rank, 12, u4DbgValue);
+    }
+
+    //wait tVREF_LONG
+    mcDELAY_US(1);
+}
+
+
+#if __LP5_COMBO__
+static inline u8 is_training_mode1(DRAMC_CTX_T *p)
+{
+    return is_lp5_family(p) && p->lp5_training_mode == TRAINING_MODE1? 1: 0;
+}
+
+static inline u8 is_training_mode2(DRAMC_CTX_T *p)
+{
+    return is_lp5_family(p) && p->lp5_training_mode == TRAINING_MODE2? 1: 0;
+}
+
+static inline u8 is_phase_falling(DRAMC_CTX_T *p)
+{
+    return is_lp5_family(p) && p->lp5_cbt_phase == CBT_PHASE_FALLING? 1: 0;
+}
+
+static void force_dq7(DRAMC_CTX_T *p, u8 level)
+{
+    u32 fld_b0, fld_b1;
+    u8 dq;
+    u8 dramc_byte;
+    struct cbt_pinmux *cp = &lp5_cp[p->channel];
+    /*
+     * TODO
+     *
+     * pinmux to selec dq7
+     *
+     */
+
+    fld_b0 = (cp->dram_dq_b0) ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0;
+    fld_b1 = (cp->dram_dq_b1) ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0;
+
+    dq = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
+        fld_b0);
+    dq &= ~(1 << (cp->dram_dq7_b0 % 8));
+    dq |= ((level & 1) << (cp->dram_dq7_b0 % 8));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
+        P_Fld(dq, fld_b0));
+
+    if (is_byte_mode(p)) {
+        dq = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
+            fld_b1);
+        dq &= ~(1 << (cp->dram_dq7_b1 % 8));
+        dq |= ((level & 1) << (cp->dram_dq7_b1 % 8));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
+            P_Fld(dq, fld_b1));
+    }
+}
+
+static inline void force_dmi(DRAMC_CTX_T *p, u8 level)
+{
+    struct cbt_pinmux *cp = &lp5_cp[p->channel];
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
+        P_Fld(level, (cp->dram_dmi_b0) ? CBT_WLEV_CTRL0_CBT_SW_DQM_B1_LP5 : CBT_WLEV_CTRL0_CBT_SW_DQM_B0_LP5));
+
+    if (is_byte_mode(p)) {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
+        P_Fld(level, (cp->dram_dmi_b1 ? CBT_WLEV_CTRL0_CBT_SW_DQM_B1_LP5 : CBT_WLEV_CTRL0_CBT_SW_DQM_B0_LP5)));
+    }
+}
+
+static void toggle_wck(DRAMC_CTX_T *p, u8 toggle)
+{
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
+        P_Fld(toggle, CBT_WLEV_CTRL0_CBT_WLEV_WCKAO));
+}
+
+static void set_vref_by_mrw(DRAMC_CTX_T *p, u8 vref)
+{
+    DramcModeRegWriteByRank(p, p->rank, 12, vref);
+}
+
+static void set_vref_by_dq(DRAMC_CTX_T *p, u16 vref)
+{
+    u8 dq;
+    struct cbt_pinmux *cp = &lp5_cp[p->channel];
+
+    force_dmi(p, 0);
+    /* wait tCBTRTW */
+    mcDELAY_US(1);
+
+    if (is_byte_mode(p)) {
+        /* DRAMC B0/B1 as TX */
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
+            3, CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN);
+
+        /* Set DRAM Byte 1 */
+        dq = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
+            (cp->dram_dq_b1 ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0));
+
+        /* Shall be carefully processed in case DQ[7] is changed */
+        dq &= (1 << (cp->dram_dq7_b1 % 8));
+        dq |= ((vref >> 8) & 0xff);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
+            P_Fld(dq, (cp->dram_dq_b1 ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0)));
+    } else {
+        /* DRAMC B0 as TX */
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
+            (1 << cp->dram_dq_b0), CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN);
+    }
+
+    /* Set DRAM Byte 0 */
+    dq = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
+        (cp->dram_dq_b0 ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0));
+    dq &= (1 << (cp->dram_dq7_b0 % 8));
+    dq |= (vref & 0xff);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
+        P_Fld(dq, (cp->dram_dq_b0 ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0)));
+
+    /* wait tDQStrain */
+    mcDELAY_US(1);
+    force_dmi(p, 1);
+    mcDELAY_US(1);
+    /* DRAMC B0/B1 as RX */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
+        0, CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN);
+    mcDELAY_US(1);
+}
+
+static void switch_oe_tie(DRAMC_CTX_T *p, u8 sw)
+{
+    u8 dq_oe;
+    struct cbt_pinmux *cp = &lp5_cp[p->channel];
+
+    if (sw) {
+        /* Set DRAM Byte 0 */
+        if (cp->dram_dq_b0) {
+            dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
+                B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1);
+            dq_oe |= (1 << (cp->dram_dq7_b0 % 8));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
+                P_Fld(dq_oe, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1) |
+                P_Fld(1, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1));
+
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
+                P_Fld(1, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) |
+                P_Fld(1, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1));
+        } else {
+            dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
+                B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0);
+            dq_oe |= (1 << (cp->dram_dq7_b0 % 8));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
+                P_Fld(dq_oe, B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0) |
+                P_Fld(1, B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0));
+
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
+                P_Fld(1, B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0) |
+                P_Fld(1, B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0));
+        }
+
+        /* Set DRAM Byte 1 */
+        if (is_byte_mode(p)) {
+            /* Set DRAM Byte 0 */
+            if (cp->dram_dq_b1) {
+                dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
+                    B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1);
+                dq_oe |= (1 << (cp->dram_dq7_b1 % 8));
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
+                    P_Fld(dq_oe, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1) |
+                    P_Fld(1, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1));
+
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
+                    P_Fld(1, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) |
+                    P_Fld(1, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1));
+            } else {
+                dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
+                    B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0);
+                dq_oe |= (1 << (cp->dram_dq7_b1 % 8));
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
+                    P_Fld(dq_oe, B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0) |
+                    P_Fld(1, B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0));
+
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
+                    P_Fld(1, B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0) |
+                    P_Fld(1, B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0));
+            }
+        }
+    } else {
+        /* Set DRAM Byte 0 */
+        if (cp->dram_dq_b0) {
+            dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
+                B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1);
+            dq_oe &= ~(1 << (cp->dram_dq7_b0 % 8));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
+                P_Fld(dq_oe, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1) |
+                P_Fld(0, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1));
+
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
+                P_Fld(0, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) |
+                P_Fld(0, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1));
+        } else {
+            dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
+                B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0);
+            dq_oe &= ~(1 << (cp->dram_dq7_b0 % 8));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
+                P_Fld(dq_oe, B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0) |
+                P_Fld(0, B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0));
+
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
+                P_Fld(0, B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0) |
+                P_Fld(0, B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0));
+        }
+
+        /* Set DRAM Byte 1 */
+        if (is_byte_mode(p)) {
+            /* Set DRAM Byte 0 */
+            if (cp->dram_dq_b1) {
+                dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
+                    B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1);
+                dq_oe &= ~(1 << (cp->dram_dq7_b1 % 8));
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
+                    P_Fld(dq_oe, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1) |
+                    P_Fld(0, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1));
+
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
+                    P_Fld(0, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) |
+                    P_Fld(0, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1));
+            } else {
+                dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
+                    B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0);
+                dq_oe &= ~(0 << (cp->dram_dq7_b1 % 8));
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
+                    P_Fld(dq_oe, B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0) |
+                    P_Fld(0, B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0));
+
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
+                    P_Fld(0, B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0) |
+                    P_Fld(0, B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0));
+            }
+        }
+    }
+}
+
+static void lp5_cbt_entry(DRAMC_CTX_T *p, u8 operating_fsp,
+        u16 operation_frequency)
+{
+    lp5heff_save_disable(p);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL),
+        0, MISC_STBCAL_DQSIENCG_NORMAL_EN);
+
+    /* TCMDEN and CATRAINEN use MRSRK */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0),
+        p->rank, SWCMD_CTRL0_MRSRK);
+
+    #if 0
+    if (p->rank == RANK_0) {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
+            P_Fld(0, CKECTRL_CKEFIXOFF) |
+            P_Fld(1, CKECTRL_CKEFIXON));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
+            P_Fld(1, CKECTRL_CKE1FIXOFF) |
+            P_Fld(0, CKECTRL_CKE1FIXON));
+    } else if (p->rank == RANK_1) {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
+            P_Fld(0, CKECTRL_CKE1FIXOFF) |
+            P_Fld(1, CKECTRL_CKE1FIXON));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
+            P_Fld(1, CKECTRL_CKEFIXOFF) |
+            P_Fld(0, CKECTRL_CKEFIXON));
+    }
+    #else
+    if (p->rank == RANK_0) {
+        CKEFixOnOff(p, RANK_0, CKE_FIXON, TO_ONE_CHANNEL);
+        CKEFixOnOff(p, RANK_1, CKE_FIXOFF, TO_ONE_CHANNEL);
+    } else if (p->rank == RANK_1){
+        CKEFixOnOff(p, RANK_1, CKE_FIXON, TO_ONE_CHANNEL);
+        CKEFixOnOff(p, RANK_0, CKE_FIXOFF, TO_ONE_CHANNEL);
+    }
+    #endif
+
+    /*
+    * APHY TX PI Spec mode option
+    * for K RK1, if RK0/1 DQ UI setting is not the same, it will fail
+    */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_NEW_XRW2W_CTRL),
+        1, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE);
+
+    /*
+    * APHY TX PI Spec mode option
+    * for K RK1, if RK0/1 DQ UI setting is not the same, it will fail
+    */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_NEW_XRW2W_CTRL),
+        1, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE);
+
+    /*
+    * APHY TX PI Spec mode option
+    * for K RK1, if RK0/1 DQ UI setting is not the same, it will fail
+    */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_NEW_XRW2W_CTRL),
+        1, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE);
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
+        P_Fld(0x1, CBT_WLEV_CTRL0_WRITE_LEVEL_EN));
+
+    /*
+     * TODO
+     * BYTEMODE, PINMUX
+     */
+    if (is_training_mode1(p)) {
+        /* DRAMC B0 as RX */
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
+            0, CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN);
+    }
+
+    switch_oe_tie(p, 1);
+
+    /*
+     * MR13 OP[6], cbt mode
+     * 0, training mode 1
+     * 1, training mode 2
+     *
+     * TODO
+     * MR13 values??
+     */
+    DramcModeRegWriteByRank(p, p->rank, 13, p->lp5_training_mode << 6);
+
+    if (operating_fsp == FSP_2) {
+        /*
+         * dram will switch to another FSP_OP automatically
+         */
+        DramcModeRegWriteByRank(p, p->rank, 16,
+            (2 << MR16_FSP_WR_SHIFT) |
+            (2 << MR16_FSP_OP_SHIFT) |
+            (p->lp5_cbt_phase << MR16_CBT_PHASE) |
+            /* CBT enabled fsp[2] */
+            (3 << MR16_FSP_CBT) |
+            (1 << MR16_VRCG));
+    } else if (operating_fsp == FSP_1) {
+        /*
+         * dram will switch to another FSP_OP automatically
+         */
+        DramcModeRegWriteByRank(p, p->rank, 16,
+            (1 << MR16_FSP_WR_SHIFT) |
+            (1<< MR16_FSP_OP_SHIFT) |
+            (p->lp5_cbt_phase << MR16_CBT_PHASE) |
+            /* CBT enabled fsp[1] */
+            (2 << MR16_FSP_CBT) |
+            (1 << MR16_VRCG));
+    } else {
+        /* FSP_0 */
+        DramcModeRegWriteByRank(p, p->rank, 16,
+            (0 << MR16_FSP_WR_SHIFT) |
+            (0 << MR16_FSP_OP_SHIFT) |
+            (p->lp5_cbt_phase << MR16_CBT_PHASE) |
+            /* CBT enabled fsp[0] */
+            (1 << MR16_FSP_CBT) |
+            (1 << MR16_VRCG));
+    }
+
+    /* wait tCBTWCKPRE_static */
+    mcDELAY_US(1);
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3),
+        P_Fld(0x5, CBT_WLEV_CTRL3_DQSBX_G) |
+        P_Fld(0x5, CBT_WLEV_CTRL3_DQSBY_G) |
+        P_Fld(0x5, CBT_WLEV_CTRL3_DQSBX1_G) |
+        P_Fld(0x5, CBT_WLEV_CTRL3_DQSBY1_G));
+
+    if (is_byte_mode(p)) {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 3, CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), P_Fld(1, CBT_WLEV_CTRL0_BYTEMODECBTEN) |
+			P_Fld(1, CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE));    //BYTEMODECBTEN=1
+    } else {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), (1 << lp5_cp[p->channel].dram_dq_b0),
+            CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL);
+    }
+
+    /* toggle WCK */
+    toggle_wck(p, 1);
+
+    /* wait tWCK2DQ7H */
+    mcDELAY_US(1);
+
+    /* DQ[7] = High */
+    force_dq7(p, 1);
+
+    /* wait tDQ7HWCK to switch FSP */
+    mcDELAY_US(1);
+
+    /* stop toggle WCK */
+    toggle_wck(p, 0);
+
+    /* wait tDQ72DQ */
+    mcDELAY_US(1);
+
+    O1PathOnOff(p, 1);
+
+    /* start toggle WCK */
+    toggle_wck(p, 1);
+
+    /* Wait tCAENT */
+    mcDELAY_US(1);
+}
+
+static void lp5_cbt_exit(DRAMC_CTX_T *p, u8 operating_fsp,
+        u8 operation_frequency)
+{
+    /* drive dq7 low */
+    force_dq7(p, 0);
+
+    /* wait tDQ7WCK */
+    mcDELAY_US(1);
+
+    /* stop wck toggle */
+    toggle_wck(p, 0);
+
+    /* wait tVREFCA_LOGNG */
+    mcDELAY_US(1);
+
+    if (operating_fsp == FSP_2) {
+        DramcModeRegWriteByRank(p, p->rank, 16,
+            (2 << MR16_FSP_WR_SHIFT) |
+            (2 << MR16_FSP_OP_SHIFT) |
+            (0 << MR16_CBT_PHASE) |
+            /* normal operation */
+            (0 << MR16_FSP_CBT) |
+            (1 << MR16_VRCG));
+    } else if (operating_fsp == FSP_1) {
+        DramcModeRegWriteByRank(p, p->rank, 16,
+            (1 << MR16_FSP_WR_SHIFT) |
+            (1 << MR16_FSP_OP_SHIFT) |
+            (0 << MR16_CBT_PHASE) |
+            /* normal operation */
+            (0 << MR16_FSP_CBT) |
+            (1 << MR16_VRCG));
+    } else {
+        DramcModeRegWriteByRank(p, p->rank, 16,
+            (0 << MR16_FSP_WR_SHIFT) |
+            (0 << MR16_FSP_OP_SHIFT) |
+            (0 << MR16_CBT_PHASE) |
+            /* normal operation */
+            (0 << MR16_FSP_CBT) |
+            (1 << MR16_VRCG));
+    }
+
+    /* wait tMRD */
+    mcDELAY_US(1);
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
+        P_Fld(0x0, CBT_WLEV_CTRL0_WRITE_LEVEL_EN));
+    switch_oe_tie(p, 0);
+
+    /*
+    * APHY TX PI Spec mode option
+    * for K RK1, if RK0/1 DQ UI setting is not the same, it will fail
+    */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_NEW_XRW2W_CTRL),
+        0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE);
+
+    /* Disable O1 path output */
+    O1PathOnOff(p, 0);
+
+    if (is_byte_mode(p)) {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), P_Fld(0, CBT_WLEV_CTRL0_BYTEMODECBTEN) |
+			P_Fld(0, CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE));    //BYTEMODECBTEN=1
+    }
+
+    #if 0
+    if (p->rank == RANK_0) {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
+            P_Fld(0, CKECTRL_CKEFIXOFF) |
+            P_Fld(0, CKECTRL_CKEFIXON));
+    } else if (p->rank == RANK_1) {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
+            P_Fld(0, CKECTRL_CKE1FIXOFF) |
+            P_Fld(0, CKECTRL_CKE1FIXON));
+    }
+    #else
+    CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ONE_CHANNEL);
+    #endif
+
+    lp5heff_restore(p);
+}
+#endif
+
+static void CBTEntryLP45(DRAMC_CTX_T *p, U8 u1FSP, U16 u2Freq)
+{
+#if __LP5_COMBO__
+    if (is_lp5_family(p))
+    {
+        lp5_cbt_entry(p, u1FSP, u2Freq);
+    }
+    else
+#endif
+    {
+        if(p->dram_fsp == FSP_1)
+        {
+            //@Darren, Risk here!!!VDDQ term region between 300mv and 360mv. (CaVref_0x20 is 204mv)
+            CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ONE_CHANNEL);
+            cbt_switch_freq(p, CBT_LOW_FREQ);
+            CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ONE_CHANNEL);
+        }
+#if ENABLE_LP4Y_WA && LP4Y_BACKUP_SOLUTION //@Darren, debugging for DFS stress
+        CmdBusTrainingLP4YWA(p, DISABLE);
+#endif
+        CBTEntryLP4(p, u1FSP, u2Freq); // @Darren, after CBT entry will not any CMD output (CKE low)
+        if(p->dram_fsp == FSP_1)
+        {
+            cbt_switch_freq(p, CBT_HIGH_FREQ);
+        }
+    }
+}
+
+static void CBTExitLP45(DRAMC_CTX_T *p, U8 u1FSP, U8 u2Freq, U8 stateFlag)
+{
+    /* by yirong.wang
+     * if stateFlag == OUT_CBT, it means we finished CBT, exit CBT
+     * if stateFlag == IN_CBT, it means we are trying to setup vref by MRW
+     *   IN_CBT case, only for LP5 mode 1 and LP4 byte mode
+     */
+#if __LP5_COMBO__
+    if (is_lp5_family(p))
+    {
+        if (stateFlag == OUT_CBT || is_training_mode1(p))
+        {
+            lp5_cbt_exit(p, u1FSP, u2Freq);
+        }
+    }
+    else
+#endif
+    {
+        if (stateFlag == OUT_CBT || p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1)
+        {
+            (p->dram_fsp == FSP_1)? cbt_switch_freq(p, CBT_LOW_FREQ): NULL;
+            CBTExitLP4(p, u1FSP, u2Freq);
+#if ENABLE_LP4Y_WA && LP4Y_BACKUP_SOLUTION //@Darren, debugging for DFS stress
+            CmdBusTrainingLP4YWA(p, ENABLE);
+#endif
+        }
+    }
+}
+
+static void CBTSetVrefLP45(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel, U8 u1FSP, U16 u2Freq, U8 stateFlag)
+{
+    /* by yirong.wang
+     * if stateFlag == OUT_CBT, it means we are not in CBT, setup vref by MRW
+     * if stateFlag == IN_CBT, it means we are doing CBT
+     *   LP5 training mode 1 and LP4 byte mode, exit CBT and setup vref by MRW, then re-enter CBT
+     *   LP5 training mode 2 and LP4 normal mode, setup vref by DQ
+     */
+#if __LP5_COMBO__
+    if (is_lp5_family(p))
+    {
+        if (stateFlag == IN_CBT && is_training_mode2(p))
+        {
+            /*
+             * training mode2
+             * TODO, according to pinmux to adjust u1VrefLevel
+             */
+            set_vref_by_dq(p, GetCBTVrefPinMuxValue_lp5(p, u1VrefLevel));
+        }
+        else
+        {
+            if (stateFlag == IN_CBT && is_training_mode1(p))
+            {
+                lp5_cbt_exit(p, u1FSP, u2Freq);
+            }
+
+            set_vref_by_mrw(p, u1VrefLevel);
+
+            if (stateFlag == IN_CBT && is_training_mode1(p))
+            {
+                lp5_cbt_entry(p, u1FSP, u2Freq);
+            }
+        }
+    }
+    else
+#endif
+    {
+        if (stateFlag == IN_CBT && p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1)
+        {
+            // BYTE MODE: We are not in CBT now, set Vref & enter CBT
+            (p->dram_fsp == FSP_1)? cbt_switch_freq(p, CBT_LOW_FREQ): NULL;
+            CBTExitLP4(p, u1FSP, u2Freq);
+
+            CBTSetVrefLP4(p, u1VrefRange, u1VrefLevel, u1FSP, stateFlag);
+
+            CBTEntryLP4(p, u1FSP, u2Freq);
+            if(p->dram_fsp == FSP_1)
+            {
+                cbt_switch_freq(p, CBT_HIGH_FREQ);
+            }
+        }
+        else
+        {
+            CBTSetVrefLP4(p, u1VrefRange, u1VrefLevel, u1FSP, stateFlag);
+        }
+    }
+}
+
+static void CBTScanPI(DRAMC_CTX_T *p, S16 *s2PIStart, S16 *s2PIEnd, S16 *s2PIStep, int autok)
+{
+	u16 p2u;
+
+	p2u = get_ca_pi_per_ui(p);
+
+    if (is_discrete_lpddr4())
+	*s2PIStart = -16; /* improve high frequency CA left boundary */
+	else
+	*s2PIStart = 0;
+	*s2PIEnd = p2u * 3 - 1;
+
+#if __LP5_COMBO__
+	if (!is_lp5_family(p))
+#endif
+	{
+		/* LPDDR4 */
+#if !CBT_MOVE_CA_INSTEAD_OF_CLK
+		if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE)
+		{
+			*s2PIStart = -24;
+		}
+		else if (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE)
+		{
+			*s2PIStart = -16;
+		}
+		else
+		{
+			*s2PIStart = -MAX_CLK_PI_DELAY;
+		}
+		*s2PIEnd = p2u * 2 - 1;
+#endif
+	}
+
+	*s2PIStep = get_capi_step(p, autok);
+}
+
+DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type)
+{
+    U8 u1FinalVref, u1FinalRange=0; //u1VrefLevel, u1VrefRange,
+    //U32 u1vrefidx, u1BitIdx, ii;
+    //U8 u1VRangeStart, u1VRangeEnd;
+    //U8 u1VrefStart, u1VrefEnd, u1VrefStep;
+    //U8 u1VrefScanStart, u1VrefScanEnd;
+    //U8 u1CBTError_flag=0;
+    //U32 u4CompareResult;
+    //PASS_WIN_DATA_T FinalWinPerCA[CATRAINING_NUM] = {{0,0,0,0,0}};
+    //U32 uiCA, uiFinishCount, uiTemp;
+    //S16 iDelay, pi_dly;
+    //S32 iFirstPass_tmp[CATRAINING_NUM], iLastPass_tmp[CATRAINING_NUM];
+    U32 uiCAWinSumMax; //uiCAWinSum,
+    U8 operating_fsp;
+    U16 operation_frequency;
+    //S32 iCA_PerBit_DelayLine[CATRAINING_NUM] = {0}, iCK_MIN = 1000
+#if CA_PER_BIT_DELAY_CELL
+    S16 iCAFinalCenter[CATRAINING_NUM] = {0}; //for CA_PER_BIT
+#endif
+    U8 u1CBTEyeScanEnable=(K_Type==NORMAL_K ? DISABLE : ENABLE);
+    U8 backup_MR12Value=0;
+    S32 backup_CATrain_CmdDelay=0;
+    U32 backup_CATrain_CsDelay=0;
+    S32 backup_CATrain_ClkDelay=0;
+    U32 backup_CATrain_CmdUIDelay=0;
+    U32 backup_CATrain_CmdCKEUIDelay=0;
+    U32 backup_CATrain_CmdCKE1UIDelay=0;
+    U32 backup_CATrain_CmdMCKDelay=0;
+
+#if ENABLE_EYESCAN_GRAPH
+    U8 EyeScan_index[CATRAINING_NUM];
+#endif
+
+    S16 pi_step; //, pi_step_bk;
+    S16 pi_start, pi_end;
+    u32 ca_ui, ca_ui_default; //, ca_ui_tmp
+    u32 ca_mck; //Vca_mck_tmp, a_mck_default
+    u32 ca_cmd0;
+    u8 ca_pin_num;
+    u8 step_respi = AUTOK_RESPI_1;
+    //u32 capi_max;
+
+    U32 u4RegBackupAddress[] =
+    {
+        (DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL)),
+        (DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2)),
+        (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0)),
+        (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1)),
+        (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL2)),
+        (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3)),
+        (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4)),
+        (DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0)),
+        (DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0)),
+
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF)),           //in O1PathOnOff()
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF)),           //in O1PathOnOff()
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_VREF)),           //in O1PathOnOff()
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL)),   //in O1PathOnOff()
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL)),   //in O1PathOnOff()
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_PHY_VREF_SEL)),   //in O1PathOnOff()
+    };
+
+    CBTScanPI(p, &pi_start, &pi_end, &pi_step, autok);
+    while (((1 << step_respi) < pi_step) && autok)
+        step_respi++;
+
+#if MRW_CHECK_ONLY
+    mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+#endif
+
+#if __LP5_COMBO__
+    if (is_lp5_family(p))
+    {
+        u1FinalVref = u1MR12Value[p->channel][p->rank][p->dram_fsp];
+        ca_pin_num = CATRAINING_NUM_LP5;
+    }
+    else
+#endif
+    {
+        u1FinalRange = u1MR12Value[p->channel][p->rank][p->dram_fsp] >> 6;
+        u1FinalVref = u1MR12Value[p->channel][p->rank][p->dram_fsp] & 0x3f;
+        ca_pin_num = CATRAINING_NUM_LP4;
+    }
+
+#if ENABLE_EYESCAN_GRAPH
+    if (u1CBTEyeScanEnable)
+    {
+        backup_MR12Value = u1MR12Value[p->channel][p->rank][p->dram_fsp];
+
+        backup_CATrain_CmdDelay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), SHU_R0_CA_CMD0_RG_ARPI_CMD);
+        backup_CATrain_CsDelay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), SHU_R0_CA_CMD0_RG_ARPI_CS);
+        backup_CATrain_ClkDelay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), SHU_R0_CA_CMD0_RG_ARPI_CLK);
+
+        backup_CATrain_CmdUIDelay = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7));
+        backup_CATrain_CmdCKEUIDelay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), SHU_SELPH_CA5_DLY_CKE);
+        backup_CATrain_CmdCKE1UIDelay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA6), SHU_SELPH_CA6_DLY_CKE1);
+
+        backup_CATrain_CmdMCKDelay = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3));
+
+        for (u1vrefidx = 0; u1vrefidx < VREF_VOLTAGE_TABLE_NUM_LP5-1; u1vrefidx++)
+        {
+            for (uiCA = 0; uiCA < ca_pin_num; uiCA++)
+            {
+                for (ii = 0; ii < EYESCAN_BROKEN_NUM; ii++)
+                {
+                    gEyeScan_Min[u1vrefidx][uiCA][ii] = EYESCAN_DATA_INVALID;
+                    gEyeScan_Max[u1vrefidx][uiCA][ii] = EYESCAN_DATA_INVALID;
+                }
+            }
+        }
+    }
+#endif
+
+    //DUMP_REG_MSG(("\n[dumpRG] CmdBusTraining \n"));
+
+    vPrintCalibrationBasicInfo(p);
+    mcSHOW_DBG_MSG(("[CmdBusTrainingLP45] new_cbt_mode=%d, autok=%d\n", p->new_cbt_mode, autok));
+    mcSHOW_DBG_MSG2(("pi_start=%d, pi_end=%d, pi_step=%d\n", pi_start, pi_end, pi_step));
+
+#if __LP5_COMBO__
+    if (is_lp5_family(p))
+    {
+        mcSHOW_DBG_MSG2(("lp5_training_mode=%d, lp5_cbt_phase=%d\n", p->lp5_training_mode, p->lp5_cbt_phase));
+    }
+#endif
+
+    //Back up dramC register
+    DramcBackupRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress));
+
+    //default set FAIL
+    if (u1CBTEyeScanEnable == DISABLE)
+    {
+        vSetCalibrationResult(p, DRAM_CALIBRATION_CA_TRAIN, DRAM_FAIL);
+#if CA_PER_BIT_DELAY_CELL
+        CATrainingSetPerBitDelayCell(p, iCAFinalCenter, ca_pin_num);
+#endif
+
+    }
+
+#if CBT_MOVE_CA_INSTEAD_OF_CLK
+    if (u1IsLP4Family(p->dram_type))
+    {
+        U8 u1CaPI = 0, u1CaUI = 0;
+
+        u1CaUI = 1;
+        u1CaPI = 0;
+
+        DramcCmdUIDelaySetting(p, u1CaUI);
+
+        CBTDelayCACLK(p, u1CaPI);
+    }
+#endif
+
+    /* read ca ui and mck */
+    ca_ui_default = ca_ui = get_ca_ui(p);
+    ca_mck = get_ca_mck(p);
+    ca_cmd0 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0));
+
+    vAutoRefreshSwitch(p, DISABLE); //When doing CA training, should make sure that auto refresh is disable
+
+    /*
+     * TOOD
+     *
+     * here just pass simulation,
+     * remove after ACTiming OK(ACTiming Table includes CATRAIN_INTV)
+     */
+    //vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1),
+    //      P_Fld(0x1F, CBT_WLEV_CTRL1_CATRAIN_INTV));
+    set_cbt_wlev_intv(p);
+
+    /*
+     * tx_rank_sel is selected by SW
+     * Lewis@20180509: tx_rank_sel is selected by SW in CBT if TMRRI design has changed.
+     */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0),
+        p->rank, TX_SET0_TXRANK);
+    /* TXRANKFIX should be write after TXRANK or the rank will be fix at rank 1 */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0),
+        1, TX_SET0_TXRANKFIX);
+
+    //SW variable initialization
+    uiCAWinSumMax = 0;
+
+    operating_fsp = p->dram_fsp;
+    operation_frequency = p->frequency;
+
+    // free-run dramc/ddrphy clk (DCMEN2=0, MIOCKCTRLOFF=1, PHYCLKDYNGEN=0, COMBCLKCTRL=0)
+    // free-run dram clk(APHYCKCG_FIXOFF =1, TCKFIXON=1)
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL),
+        P_Fld(0, DRAMC_PD_CTRL_DCMEN2) |
+        P_Fld(1, DRAMC_PD_CTRL_MIOCKCTRLOFF) |
+        P_Fld(0, DRAMC_PD_CTRL_PHYCLKDYNGEN) |
+        P_Fld(0, DRAMC_PD_CTRL_COMBCLKCTRL) |
+        P_Fld(1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF) |
+        P_Fld(1, DRAMC_PD_CTRL_TCKFIXON));
+
+    //Note : Assume that there is a default CS value that can apply for CA.
+    CBTEntryLP45(p, operating_fsp, operation_frequency);
+
+#if PINMUX_AUTO_TEST_PER_BIT_CA
+    CheckCADelayCell(p);
+#endif
+
+    //Step 3: set vref range and step by ddr type
+
+#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && (BYPASS_VREF_CAL || BYPASS_CBT))
+    if (p->femmc_Ready == 1)
+    {
+        u1FinalVref = p->pSavetimeData->u1CBTVref_Save[p->channel][p->rank];
+    }
+#endif
+
+    if (u1CBTEyeScanEnable)
+    {
+        u1FinalVref = backup_MR12Value & 0x3f;
+        u1FinalRange = (backup_MR12Value>>6) & 1;
+    }
+
+    mcSHOW_DBG_MSG(("\n[CmdBusTrainingLP45] Vref(ca) range %d: %d\n", u1FinalRange, u1FinalVref));
+    //DUMP_REG_MSG(("\n[CmdBusTrainingLP45] Vref(ca) range %d: %d\n", u1FinalRange, u1FinalVref));
+
+#ifdef FOR_HQA_TEST_USED
+    gFinalCBTVrefCA[p->channel][p->rank] = u1FinalVref;
+#endif
+
+    //Set Vref after training
+    // BYTE MODE: Set Vref & enter CBT
+    CBTSetVrefLP45(p, u1FinalRange, u1FinalVref, operating_fsp, operation_frequency, IN_CBT);
+#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_CBT)
+    #if CBT_MOVE_CA_INSTEAD_OF_CLK
+    // scan UI from 0, not from the UI we used to enter CBT
+    DramcCmdUIDelaySetting(p, 0);
+    ca_ui = get_ca_ui(p);
+    #endif
+#endif
+    put_ca_ui(p, ca_ui);
+    //Set CA_PI_Delay after training
+    if (u1CBTEyeScanEnable == DISABLE)
+    {
+        CBTSetCACLKResult(p, ca_mck, ca_ui, ca_pin_num);
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0),
+            P_Fld(backup_CATrain_CmdDelay, SHU_R0_CA_CMD0_RG_ARPI_CMD) |
+            P_Fld(backup_CATrain_ClkDelay, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
+            P_Fld(backup_CATrain_CsDelay, SHU_R0_CA_CMD0_RG_ARPI_CS));
+
+        vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7), backup_CATrain_CmdUIDelay);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), backup_CATrain_CmdCKEUIDelay, SHU_SELPH_CA5_DLY_CKE);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA6), backup_CATrain_CmdCKE1UIDelay, SHU_SELPH_CA6_DLY_CKE1);
+
+        vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3), backup_CATrain_CmdMCKDelay);
+    }
+
+#if ENABLE_EYESCAN_GRAPH
+    gEyeScan_CaliDelay[0] = CATrain_CmdDelay[p->channel][p->rank] -pi_start;
+#endif
+
+    /* -------------  CS and CLK ---------- */
+    /* delay ca 1UI before K CS */
+#if __LP5_COMBO__
+    if (is_phase_falling(p)) {
+        ca_mck = get_ca_mck(p);
+        ca_ui = get_ca_ui(p);
+        xlate_ca_mck_ui(p, 1,
+                ca_mck, ca_ui,
+                &ca_mck_tmp, &ca_ui_tmp);
+        put_ca_mck(p, ca_mck_tmp);
+        put_ca_ui(p, ca_ui_tmp);
+    }
+#endif
+
+    if (u1CBTEyeScanEnable == DISABLE)
+    {
+        CBTAdjustCS(p, autok);
+    }
+
+    /* restore ca mck and ui */
+#if __LP5_COMBO__
+    if (is_phase_falling(p)) {
+        put_ca_mck(p, ca_mck);
+        put_ca_ui(p, ca_ui);
+    }
+#endif
+
+//-------  Going to exit Command bus training(CBT) mode.-------------
+    CBTExitLP45(p, operating_fsp, operation_frequency, OUT_CBT);
+    CBTSetVrefLP45(p, u1FinalRange, u1FinalVref, operating_fsp, operation_frequency, OUT_CBT);
+
+#if __LP5_COMBO__
+    if (!is_lp5_family(p))
+#endif
+    {
+        if (p->dram_fsp == FSP_1)
+        {
+            #if MR_CBT_SWITCH_FREQ
+            DramcModeRegInit_CATerm(p, 0);
+            #else
+            DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_OP, TO_MR);
+            #endif
+        }
+    }
+
+#if EYESCAN_LOG || defined(FOR_HQA_TEST_USED)
+    gFinalCBTVrefDQ[p->channel][p->rank] = u1FinalVref;
+#endif
+
+    mcSHOW_DBG_MSG4(("\n[CmdBusTrainingLP45] Done\n"));
+
+    //tx_rank_sel is selected by HW //Lewis@20180509: tx_rank_sel is selected by SW in CBT if TMRRI design has changed.
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANK);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANKFIX); //TXRANKFIX should be write after TXRANK or the rank will be fix at rank 1
+
+    //Restore setting registers
+    DramcRestoreRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress));
+
+    return DRAM_OK;
+}
+#endif /* SIMUILATION_CBT */
+
+//-------------------------------------------------------------------------
+/** DramcWriteLeveling
+ *  start Write Leveling Calibration.
+ *  @param p                Pointer of context created by DramcCtxCreate.
+ *  @param  apply           (U8): 0 don't apply the register we set  1 apply the register we set ,default don't apply.
+ *  @retval status          (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL
+ */
+//-------------------------------------------------------------------------
+#define WRITE_LEVELING_MOVD_DQS 1//UI
+
+U8 u1MCK2UI_DivShift(DRAMC_CTX_T *p)
+{
+#if (__LP5_COMBO__ == TRUE)
+    if (TRUE == is_lp5_family(p))
+    {
+        //in LP4 1:8 mode, 8 small UI =  1 large UI
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+        {
+            return MCK_TO_4UI_SHIFT;
+        }
+        else if (vGet_Div_Mode(p) == DIV16_MODE)
+        {
+            return MCK_TO_16UI_SHIFT;
+        }
+        else
+        {
+            return MCK_TO_8UI_SHIFT;
+        }
+    }
+    else
+#endif
+    {
+        //in LP4 1:8 mode, 8 small UI =  1 large UI
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+        {
+            return MCK_TO_4UI_SHIFT;
+        }
+        else
+        {
+            return MCK_TO_8UI_SHIFT;
+        }
+    }
+}
+
+static DRAM_STATUS_T ExecuteMoveDramCDelay(DRAMC_CTX_T *p,
+                                                    REG_TRANSFER_T ui_reg,
+                                                    REG_TRANSFER_T mck_reg,
+                                                    S8 iShiftUI)
+{
+    S32 s4HighLevelDelay, s4DelaySum;
+    U32 u4TmpUI, u4TmpMCK;
+    U8 ucDataRateDivShift = 0;
+    DRAM_STATUS_T MoveResult;
+
+    ucDataRateDivShift = u1MCK2UI_DivShift(p);
+
+    u4TmpUI = u4IO32ReadFldAlign(DRAMC_REG_ADDR(ui_reg.u4Addr), ui_reg.u4Fld) & (~(1 << ucDataRateDivShift));
+    u4TmpMCK = u4IO32ReadFldAlign(DRAMC_REG_ADDR(mck_reg.u4Addr), mck_reg.u4Fld);
+    //mcSHOW_DBG_MSG(("Base:  u4TmpMCK:%d,  u4TmpUI: %d,\n", u4TmpMCK, u4TmpUI));
+
+    s4HighLevelDelay = (u4TmpMCK << ucDataRateDivShift) + u4TmpUI;
+    s4DelaySum = (s4HighLevelDelay + iShiftUI);
+
+    if (s4DelaySum < 0)
+    {
+        u4TmpUI = 0;
+        u4TmpMCK = 0;
+        MoveResult = DRAM_FAIL;
+    }
+    else
+    {
+        u4TmpMCK = s4DelaySum >> ucDataRateDivShift;
+        u4TmpUI = s4DelaySum - (u4TmpMCK << ucDataRateDivShift);
+        MoveResult = DRAM_OK;
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(ui_reg.u4Addr), u4TmpUI, ui_reg.u4Fld);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(mck_reg.u4Addr), u4TmpMCK, mck_reg.u4Fld);
+    //mcSHOW_DBG_MSG(("[%d]  Final ==> u4TmpMCK:%d,  u4TmpUI: %d,\n", iShiftUI, u4TmpMCK, u4TmpUI));
+
+    return MoveResult;
+}
+
+static void _LoopAryToDelay(DRAMC_CTX_T *p,
+                                  REG_TRANSFER_T *ui_reg,
+                                  REG_TRANSFER_T *mck_reg,
+                                  U8 u8RG_num,
+                                  S8 iShiftUI,
+                                  BYTES_T eByteIdx)
+{
+    U8 idx = 0, step = 1;
+    if (eByteIdx == BYTE_0)
+    {
+        idx = 0;
+        step = 2;
+    }
+    else if (eByteIdx == BYTE_1)
+    {
+        idx = 1;
+        step = 2;
+    }
+
+    for (; idx < u8RG_num; idx += step)
+    {
+        ExecuteMoveDramCDelay(p, ui_reg[idx], mck_reg[idx], iShiftUI);
+    }
+}
+
+static void LP4_ShiftDQSUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx)
+{
+    // DQS / DQS_OEN
+    REG_TRANSFER_T TransferUIRegs[]  = {{DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_DQS0},        // Byte0
+                                        {DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_DQS1}};       // Byte1
+    REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHU_SELPH_DQS0, SHU_SELPH_DQS0_TXDLY_DQS0},
+                                        {DRAMC_REG_SHU_SELPH_DQS0, SHU_SELPH_DQS0_TXDLY_DQS1}};
+
+    _LoopAryToDelay(p, TransferUIRegs, TransferMCKRegs,
+                       sizeof(TransferUIRegs) / sizeof(REG_TRANSFER_T),
+                       iShiftUI, eByteIdx);
+}
+
+void LP4_ShiftDQS_OENUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx)
+{
+    // DQS / DQS_OEN
+    REG_TRANSFER_T TransferUIRegs[]  = {{DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_OEN_DQS0},    // Byte0
+                                        {DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_OEN_DQS1}};   // Byte1
+    REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHU_SELPH_DQS0, SHU_SELPH_DQS0_TXDLY_OEN_DQS0},
+                                        {DRAMC_REG_SHU_SELPH_DQS0, SHU_SELPH_DQS0_TXDLY_OEN_DQS1}};
+
+    _LoopAryToDelay(p, TransferUIRegs, TransferMCKRegs,
+                       sizeof(TransferUIRegs) / sizeof(REG_TRANSFER_T),
+                       iShiftUI, eByteIdx);
+}
+
+static void ShiftDQUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx)
+{
+    // Shift DQ / DQM / DQ_OEN / DQM_OEN
+    REG_TRANSFER_T TransferUIRegs[]  = {{DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_DQM0},      // Byte0
+                                        {DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_DQM1},      // Byte1
+                                        {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_DQ0},       // Byte0
+                                        {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_DQ1}};  // Byte1
+    REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHURK_SELPH_DQ1, SHURK_SELPH_DQ1_TXDLY_DQM0},
+                                        {DRAMC_REG_SHURK_SELPH_DQ1, SHURK_SELPH_DQ1_TXDLY_DQM1},
+                                        {DRAMC_REG_SHURK_SELPH_DQ0, SHURK_SELPH_DQ0_TXDLY_DQ0},
+                                        {DRAMC_REG_SHURK_SELPH_DQ0, SHURK_SELPH_DQ0_TXDLY_DQ1}};
+
+    _LoopAryToDelay(p, TransferUIRegs, TransferMCKRegs,
+                    sizeof(TransferUIRegs) / sizeof(REG_TRANSFER_T),
+                    iShiftUI, eByteIdx);
+}
+
+static void ShiftDQUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx)
+{
+    U8 backup_rank, rk_i;
+    backup_rank = u1GetRank(p);
+
+    // Shift DQ / DQM / DQ_OEN / DQM_OEN
+    for (rk_i = RANK_0; rk_i < p->support_rank_num; rk_i++)
+    {
+        vSetRank(p, rk_i);
+        ShiftDQUI(p, iShiftUI, eByteIdx);
+    }
+    vSetRank(p, backup_rank);
+}
+
+static void ShiftDQ_OENUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx)
+{
+    REG_TRANSFER_T TransferUIRegs[]  = {{DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_OEN_DQM0},  // Byte0
+                                        {DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_OEN_DQM1},  // Byte1
+                                        {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_OEN_DQ0},   // Byte0
+                                        {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_OEN_DQ1}};  // Byte1
+    REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHURK_SELPH_DQ1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0},
+                                        {DRAMC_REG_SHURK_SELPH_DQ1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1},
+                                        {DRAMC_REG_SHURK_SELPH_DQ0, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0},
+                                        {DRAMC_REG_SHURK_SELPH_DQ0, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1}};
+
+    _LoopAryToDelay(p, TransferUIRegs, TransferMCKRegs,
+                    sizeof(TransferUIRegs) / sizeof(REG_TRANSFER_T),
+                    iShiftUI, eByteIdx);
+}
+
+void ShiftDQ_OENUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx)
+{
+    U8 backup_rank, rk_i;
+    backup_rank = u1GetRank(p);
+
+    // Shift DQ / DQM / DQ_OEN / DQM_OEN
+    for (rk_i = RANK_0; rk_i < p->support_rank_num; rk_i++)
+    {
+        vSetRank(p, rk_i);
+        ShiftDQ_OENUI(p, iShiftUI, eByteIdx);
+    }
+    vSetRank(p, backup_rank);
+}
+
+//void WriteLevelingMoveDQSInsteadOfCLK(DRAMC_CTX_T *p, S8 iShiftUI)
+//{
+//    LP4_ShiftDQSUI(p, iShiftUI, ALL_BYTES);
+//    LP4_ShiftDQUI(p, iShiftUI, ALL_BYTES);
+//}
+
+#if __LP5_COMBO__
+static void LP5_ShiftWCKUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx)
+{
+    REG_TRANSFER_T TransferUIRegs[]  = {{DRAMC_REG_SHURK_WCK_WR_UI, SHURK_WCK_WR_UI_WCK_WR_B0_UI},      // Byte0
+                                        {DRAMC_REG_SHURK_WCK_WR_UI, SHURK_WCK_WR_UI_WCK_WR_B1_UI},      // Byte1
+                                        {DRAMC_REG_SHURK_WCK_RD_UI, SHURK_WCK_RD_UI_WCK_RD_B0_UI},      // Byte0
+                                        {DRAMC_REG_SHURK_WCK_RD_UI, SHURK_WCK_RD_UI_WCK_RD_B1_UI},      // Byte1
+                                        {DRAMC_REG_SHURK_WCK_FS_UI, SHURK_WCK_FS_UI_WCK_FS_B0_UI},      // Byte0
+                                        {DRAMC_REG_SHURK_WCK_FS_UI, SHURK_WCK_FS_UI_WCK_FS_B1_UI}};     // Byte1
+    REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHURK_WCK_WR_MCK, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK},
+                                        {DRAMC_REG_SHURK_WCK_WR_MCK, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK},
+                                        {DRAMC_REG_SHURK_WCK_RD_MCK, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK},
+                                        {DRAMC_REG_SHURK_WCK_RD_MCK, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK},
+                                        {DRAMC_REG_SHURK_WCK_FS_MCK, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK},
+                                        {DRAMC_REG_SHURK_WCK_FS_MCK, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK}};
+
+    _LoopAryToDelay(p, TransferUIRegs, TransferMCKRegs,
+                       sizeof(TransferUIRegs) / sizeof(REG_TRANSFER_T),
+                       iShiftUI, eByteIdx);
+}
+#endif
+
+static void ShiftDQSWCK_UI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx)
+{
+#if (__LP5_COMBO__ == TRUE)
+        if (TRUE == is_lp5_family(p))
+            LP5_ShiftWCKUI(p, iShiftUI, eByteIdx);
+        else
+#endif
+        {
+            LP4_ShiftDQSUI(p, iShiftUI, eByteIdx);
+            LP4_ShiftDQS_OENUI(p, iShiftUI, eByteIdx);
+        }
+}
+
+U8 u1IsLP4Div4DDR800(DRAMC_CTX_T *p)
+{
+    if ((vGet_Div_Mode(p) == DIV4_MODE) && (p->frequency == 400))
+        return TRUE;
+    else
+        return FALSE;
+}
+
+//static void vSetDramMRWriteLevelingOnOff(DRAMC_CTX_T *p, U8 u1OnOff)
+static void vSetDramMRWriteLevelingOnOff(DRAMC_CTX_T *p, U8 u1OnOff)
+{
+    // MR2 OP[7] to enable/disable write leveling
+    if (u1OnOff)
+        u1MR02Value[p->dram_fsp] |= 0x80;  // OP[7] WR LEV =1
+    else
+        u1MR02Value[p->dram_fsp] &= 0x7f;  // OP[7] WR LEV =0
+
+    DramcModeRegWriteByRank(p, p->rank, 2, u1MR02Value[p->dram_fsp]);
+}
+
+U8 u1IsPhaseMode(DRAMC_CTX_T *p)
+{
+    if ((vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE) || (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE))
+        return TRUE;
+    else // DDR800_CLOSE_LOOP and NORMAL_CLOSE_LOOP
+        return FALSE;
+}
+#if __LP5_COMBO__
+static void vSetLP5Dram_WCK2CK_WlevOnOff(DRAMC_CTX_T *p, U8 u1OnOff)
+{
+    // MR18 OP[6] to enable/disable WCK2CK leveling
+    if (u1OnOff)
+        u1MR18Value[p->dram_fsp] |= 0x40;  // OP[6] WCK2CK Leveling = 1
+    else
+        u1MR18Value[p->dram_fsp] &= 0xBF;  // OP[6] WCK2CK Leveling = 0
+
+    DramcModeRegWriteByRank(p, p->rank, 18, u1MR18Value[p->dram_fsp]);
+}
+#endif
+#if 0
+static DRAM_STATUS_T DramcTriggerAndWait(DRAMC_CTX_T *p, REG_TRANSFER_T TriggerReg, REG_TRANSFER_T RepondsReg)
+{
+//    U32 u4TimeCnt = TIME_OUT_CNT;
+    // @Darren, Rx HW AutoK simulation time
+    // RX delay all range -511~255, step:4,DDR800semi + TEST2_OFF=0x100 => 8661us/per rank
+    // RX delay all range -327~252, step:8,DDR800semi, TEST2_OFF=0x100 => 3276us/per rank
+    U32 u4TimeCnt = DDR_HW_AUTOK_POLLING_CNT;
+    DRAM_STATUS_T u4RespFlag = 0;
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 0, TriggerReg.u4Fld); // Init EN status
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 1, TriggerReg.u4Fld);
+    do
+    {
+        u4RespFlag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(RepondsReg.u4Addr), RepondsReg.u4Fld);
+        u4TimeCnt --;
+        mcDELAY_US(1);
+    }while ((u4RespFlag == 0) && (u4TimeCnt > 0));
+
+    if (u4TimeCnt == 0)//time out
+    {
+        mcSHOW_ERR_MSG(("[DramcTriggerAndWait] Wait 0x%x respond fail (time out)\n", RepondsReg.u4Addr));
+        return DRAM_FAIL;
+    }
+
+    return DRAM_OK;
+}
+
+static DRAM_STATUS_T DramcTriggerAndWait_For_RX_AutoK_WorkAround(DRAMC_CTX_T *p, REG_TRANSFER_T TriggerReg, REG_TRANSFER_T RepondsReg, U16 u16DelayStep)
+{
+    // Set step = 0 to let autoK non-stop
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_AUTOK_CFG0), 0, MISC_RX_AUTOK_CFG0_RX_CAL_STEP);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 0, TriggerReg.u4Fld); // Init EN status
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 1, TriggerReg.u4Fld);
+
+    // Trigger and then stop immediately
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 0, TriggerReg.u4Fld);
+
+    // PHY reset
+    DramPhyReset(p);
+
+    // Restor the original step
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_AUTOK_CFG0), u16DelayStep, MISC_RX_AUTOK_CFG0_RX_CAL_STEP);
+
+    return DramcTriggerAndWait(p, TriggerReg, RepondsReg);
+}
+#endif
+#if (SIMULATION_WRITE_LEVELING == 1)
+#define DQPI_PER_UI (32)
+#define STORAGED_DLY_UNIT (24)
+static void WriteLevelingScanRange_PI(DRAMC_CTX_T *p, S32 *ps4DlyBegin, S32 *ps4DlyEnd, U8 *pu1PIStep, S16 *pPI_bound, WLEV_DELAY_BASED_T stDelayBase)
+{
+    S32 s4DlyBegin = 0, s4DlyEnd;
+    U8 u1PIStep;
+    S16 PI_bound;
+
+    if (stDelayBase == PI_BASED)
+    {
+        // Giving PI scan range
+        s4DlyBegin = WRITE_LEVELING_MOVD_DQS * 32 - MAX_CLK_PI_DELAY - 1;
+        s4DlyEnd = s4DlyBegin + 64 - 1;
+
+        if ((vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE))
+        {
+            u1PIStep = 16;
+            PI_bound = 32;
+        }
+        else if ((vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE))
+        {
+            u1PIStep = 8;
+            PI_bound = 32;
+        }
+        else
+        {
+            u1PIStep = 1;
+            PI_bound = 64;
+        }
+    }
+    else // stDelayBase == DLY_BASED
+    {
+        // Giving delay cell scan range
+        s4DlyBegin = 0;
+        s4DlyEnd = 2 * STORAGED_DLY_UNIT;
+
+        u1PIStep = 1;    // One step is 1/4 delay cell
+        PI_bound = 1024; // No bounadary as delay cell based
+    }
+    mcSHOW_DBG_MSG2(("Delay: %d->%d, Step: %d, Bound: %d\n", s4DlyBegin, s4DlyEnd, u1PIStep, PI_bound));
+
+    *ps4DlyBegin = s4DlyBegin;
+    *ps4DlyEnd = s4DlyEnd;
+    *pu1PIStep = u1PIStep;
+    *pPI_bound = PI_bound;
+
+}
+
+#if ENABLE_WDQS_MODE_2
+void WriteLevelingPosCal(DRAMC_CTX_T *p, WLEV_DELAY_BASED_T stDelayBase)
+{
+    DRAM_RANK_T backup_rank = u1GetRank(p);
+    U8 wrlevel_dqs_delay[DQS_BYTE_NUMBER] = {0};
+    U8 rank_i = 0;
+
+    if((wrlevel_dqs_final_delay[RANK_0][0] - wrlevel_dqs_final_delay[RANK_1][0])>=9 ||
+        (wrlevel_dqs_final_delay[RANK_0][0] - wrlevel_dqs_final_delay[RANK_1][0])<=-9 ||
+        (wrlevel_dqs_final_delay[RANK_0][1] - wrlevel_dqs_final_delay[RANK_1][1])>=9 ||
+        (wrlevel_dqs_final_delay[RANK_0][1] - wrlevel_dqs_final_delay[RANK_1][1])<=-9 )
+    {
+        mcSHOW_ERR_MSG(("[WARNING] Larger WL R2R !!\n"));
+        #if CHECK_HQA_CRITERIA
+        while(1);
+        #endif
+    }
+
+    wrlevel_dqs_delay[0] = (wrlevel_dqs_final_delay[RANK_0][0] + wrlevel_dqs_final_delay[RANK_1][0]) >> 1;
+    wrlevel_dqs_delay[1] = (wrlevel_dqs_final_delay[RANK_0][1] + wrlevel_dqs_final_delay[RANK_1][1]) >> 1;
+
+    wrlevel_dqs_final_delay[RANK_0][0] = wrlevel_dqs_final_delay[RANK_1][0] = wrlevel_dqs_delay[0];
+    wrlevel_dqs_final_delay[RANK_0][1] = wrlevel_dqs_final_delay[RANK_1][1] = wrlevel_dqs_delay[1];
+
+    for (rank_i = p->rank; rank_i < p->support_rank_num; rank_i++)
+    {
+        vSetRank(p, rank_i);
+
+        // set to best values for  DQS
+        if (stDelayBase == PI_BASED)
+        {
+            // Adjust DQS output delay.
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), wrlevel_dqs_delay[0], SHU_R0_B0_DQ0_ARPI_PBYTE_B0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), wrlevel_dqs_delay[1], SHU_R0_B1_DQ0_ARPI_PBYTE_B1);
+        }
+        else // stDelayBase == DLY_BASED
+        {
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), wrlevel_dqs_delay[0], SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), wrlevel_dqs_delay[1], SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), wrlevel_dqs_delay[0], SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), wrlevel_dqs_delay[1], SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1);
+        }
+    }
+
+    vSetRank(p, backup_rank);
+
+    mcSHOW_DBG_MSG(("[WriteLevelingPosCal] DQS PI B0/B1 = %d/%d\n", wrlevel_dqs_delay[0], wrlevel_dqs_delay[1]));
+}
+#endif
+
+#define SET_PATTERN_MANUALLY_FOR_DEBUG 1
+DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T stDelayBase)
+{
+// Note that below procedure is based on "ODT off"
+    DRAM_STATUS_T KResult = DRAM_FAIL;
+
+    //U8 *uiLPDDR_O1_Mapping = NULL;
+    //U32 u4value = 0, u4dq_o1 = 0 u4value1 = 0,  u4dq_o1_tmp[DQS_BYTE_NUMBER];
+    U8 byte_i, rank_i, ucDoneFlg;
+    //S32 iDelay, ClockDelayMax;
+    //U8 ucStatus[DQS_BYTE_NUMBER], ucdq_o1[DQS_BYTE_NUMBER], ucdq_o1_shift[DQS_BYTE_NUMBER]
+    //U8 ucHW_cmp_raw_data, uccmp_result[DQS_BYTE_NUMBER];
+    DRAM_RANK_T backup_rank;
+
+    //S32 wrlevel_dq_delay[DQS_BYTE_NUMBER]; // 3 is channel number
+    S32 wrlevel_dqs_delay[DQS_BYTE_NUMBER]; // 3 is channel number
+
+    //u32 bitmap31_0[DQS_BYTE_NUMBER] = {0};
+    //u32 bitmap63_32[DQS_BYTE_NUMBER] = {0};
+    //u8 idx = 0;
+    //U16 _bitmap_stored_num = 0;
+
+    S32 s4DlyBegin, s4DlyEnd;
+    U8 u1PIStep;
+    U8 u1OverBoundCnt = 0; //jj = 0
+    S16 PI_bound = 64;
+
+    //When doing WriteLeveling, should make sure that auto refresh is disable
+    vAutoRefreshSwitch(p, DISABLE);
+
+    // error handling
+    if (!p)
+    {
+        mcSHOW_ERR_MSG(("context NULL\n"));
+        return DRAM_FAIL;
+    }
+    //DUMP_REG_MSG(("\n[dumpRG] DramcWriteLeveling \n"));
+#if VENDER_JV_LOG
+        vPrintCalibrationBasicInfo_ForJV(p);
+#else
+        vPrintCalibrationBasicInfo(p);
+#endif
+    mcSHOW_DBG_MSG(("[Write Leveling] autok: %d\n", isAutoK));
+
+    fgwrlevel_done = 0;
+    backup_rank = u1GetRank(p);
+
+    //DramcRankSwap(p, p->rank);
+    //tx_rank_sel is selected by SW //Lewis@20180604: tx_rank_sel is selected by SW in WL if TMRRI design has changed.
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), p->rank, TX_SET0_TXRANK);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 1, TX_SET0_TXRANKFIX); //TXRANKFIX should be write after TXRANK
+
+    // backup mode settings
+    U32 u4RegBackupAddress[] =
+    {
+        (DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)),
+        (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0)),
+        (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1)),
+        (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3)),
+        (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF)),           //in O1PathOnOff()
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF)),           //in O1PathOnOff()
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_VREF)),           //in O1PathOnOff()
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL)),   //in O1PathOnOff()
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL)),   //in O1PathOnOff()
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_PHY_VREF_SEL)),   //in O1PathOnOff()
+        (DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL))
+    };
+    DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+
+
+    //default set DRAM FAIL
+    vSetCalibrationResult(p, DRAM_CALIBRATION_WRITE_LEVEL, DRAM_FAIL);
+
+#if MRW_CHECK_ONLY
+    mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+#endif
+
+    if (p->isWLevInitShift[p->channel] == FALSE)
+    {
+        // It must be PI_BASED or FAIL!!
+#if __ETT__
+		while (stDelayBase != PI_BASED);
+#else
+        ASSERT(stDelayBase == PI_BASED);
+#endif
+
+        p->isWLevInitShift[p->channel] = TRUE;
+
+        // This flow would be excuted just one time, so all ranks(maybe rank0/1) should be adjusted at once.
+        ShiftDQUI_AllRK(p, -WRITE_LEVELING_MOVD_DQS, ALL_BYTES);
+        ShiftDQ_OENUI_AllRK(p, -WRITE_LEVELING_MOVD_DQS, ALL_BYTES);
+        ShiftDQSWCK_UI(p, -WRITE_LEVELING_MOVD_DQS, ALL_BYTES);
+
+#if (__LP5_COMBO__ == TRUE)
+        if (TRUE == is_lp5_family(p))
+        {
+            // For DLY based WCK leveling
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13), 0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), 0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1);
+
+            // Set DQS DLY-based delay to 16
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), STORAGED_DLY_UNIT, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), STORAGED_DLY_UNIT, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), STORAGED_DLY_UNIT, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), STORAGED_DLY_UNIT, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1);
+        }
+#endif
+        // Set DQS PI-based delay to 0
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), 0, SHU_R0_B0_DQ0_ARPI_PBYTE_B0);  //rank0, byte0, DQS delay
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), 0, SHU_R0_B1_DQ0_ARPI_PBYTE_B1);  //rank0, byte1, DQS delay
+
+    }
+
+    // decide algorithm parameters according to freq.(PI mode/ phase mode)
+    WriteLevelingScanRange_PI(p, &s4DlyBegin, &s4DlyEnd, &u1PIStep, &PI_bound, stDelayBase);
+
+    // Not support autok to delay cell based mode.
+    if (stDelayBase == DLY_BASED)
+        isAutoK = FALSE;
+
+
+#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_WRITELEVELING)
+    if (p->femmc_Ready == 1)
+    {
+        wrlevel_dqs_final_delay[p->rank][0] = p->pSavetimeData->u1WriteLeveling_bypass_Save[p->channel][p->rank][0];
+        wrlevel_dqs_final_delay[p->rank][1] = p->pSavetimeData->u1WriteLeveling_bypass_Save[p->channel][p->rank][1];
+
+        ucDoneFlg = 0xff;
+        KResult = DRAM_OK;
+        vSetCalibrationResult(p, DRAM_CALIBRATION_WRITE_LEVEL, DRAM_FAST_K);
+    }
+#endif
+
+    if (u1OverBoundCnt > 0)
+        ShiftDQSWCK_UI(p, -u1OverBoundCnt * (PI_bound / DQPI_PER_UI), ALL_BYTES);
+
+    if (ucDoneFlg == 0xff)
+    {
+        // all bytes are done
+        fgwrlevel_done = 1;
+        KResult = DRAM_OK;
+    }
+    else
+    {
+        KResult = DRAM_FAIL;
+        #if PIN_CHECK_TOOL
+        PINInfo_flashtool.WL_ERR_FLAG|=(0x1<<(p->channel*2+p->rank));
+        #endif
+    }
+    vSetCalibrationResult(p, DRAM_CALIBRATION_WRITE_LEVEL, KResult);
+    mcSHOW_DBG_MSG2(("pass bytecount = 0x%x (0xff: all bytes pass) \n\n", ucDoneFlg));
+
+#if defined(FOR_HQA_TEST_USED) && defined(FOR_HQA_REPORT_USED)
+    if (gHQALog_flag == 1)
+    {
+        for (byte_i = 0; byte_i < DQS_BYTE_NUMBER; byte_i++)
+        {
+            if (byte_i==0)
+            {
+                HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "", "WriteLeveling_MCK_DQS", byte_i, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_DQS0), NULL);
+                HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "", "WriteLeveling_UI_DQS", byte_i, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_DQS0), NULL);
+            }
+            else
+            {
+                HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "", "WriteLeveling_MCK_DQS", byte_i, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_DQS1), NULL);
+                HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "", "WriteLeveling_UI_DQS", byte_i, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_DQS1), NULL);
+            }
+
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "", "WriteLeveling_DQS", byte_i, wrlevel_dqs_final_delay[p->rank][byte_i], NULL);
+        }
+    }
+#endif
+
+
+#if (__LP5_COMBO__ == TRUE)
+    if (TRUE == is_lp5_family(p))
+
+        vSetLP5Dram_WCK2CK_WlevOnOff(p, DISABLE);
+    else
+#endif
+        vSetDramMRWriteLevelingOnOff(p, DISABLE); // Disable DDR write leveling mode:  issue MR2[7] to enable write leveling
+
+
+    // Write leveling enable OFF
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0, CBT_WLEV_CTRL0_WRITE_LEVEL_EN);
+
+    //Disable DQ_O1, SELO1ASO=0 for power saving
+    O1PathOnOff(p, OFF);
+
+    //tx_rank_sel is selected by HW
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANK);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANKFIX); //TXRANKFIX should be write after TXRANK
+
+    //restore registers.
+    DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+
+    // Calculate DQS "PI" delay, nothing to do with delay cell
+    for (byte_i = 0; byte_i < DQS_BYTE_NUMBER; byte_i++)
+    {
+        //Also for Dump_Reg
+        mcSHOW_DBG_MSG(("Write leveling (Byte %d): %d", byte_i, wrlevel_dqs_final_delay[p->rank][byte_i]));
+        //DUMP_REG_MSG(("Write leveling (Byte %d): %d", byte_i, wrlevel_dqs_final_delay[p->rank][byte_i]));
+        if (wrlevel_dqs_final_delay[p->rank][byte_i] >= PI_bound)
+        {
+            ShiftDQSWCK_UI(p, (wrlevel_dqs_final_delay[p->rank][byte_i] / PI_bound) * (PI_bound / DQPI_PER_UI), byte_i);
+
+            wrlevel_dqs_final_delay[p->rank][byte_i] %= PI_bound;
+        }
+
+        wrlevel_dqs_delay[byte_i] = wrlevel_dqs_final_delay[p->rank][byte_i];
+        mcSHOW_DBG_MSG((" => %d\n", wrlevel_dqs_delay[byte_i]));
+        //DUMP_REG_MSG((" => %d\n", wrlevel_dqs_delay[byte_i]));
+    }
+
+    for (rank_i = p->rank; rank_i < RANK_MAX; rank_i++)
+    {
+        vSetRank(p, rank_i);
+
+        // set to best values for  DQS
+        if (stDelayBase == PI_BASED)
+        {
+            // Adjust DQS output delay.
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), wrlevel_dqs_delay[0], SHU_R0_B0_DQ0_ARPI_PBYTE_B0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), wrlevel_dqs_delay[1], SHU_R0_B1_DQ0_ARPI_PBYTE_B1);
+        }
+        else // stDelayBase == DLY_BASED
+        {
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), wrlevel_dqs_delay[0], SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), wrlevel_dqs_delay[1], SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), wrlevel_dqs_delay[0], SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), wrlevel_dqs_delay[1], SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1);
+        }
+    }
+
+    vSetRank(p, backup_rank);
+
+    mcSHOW_DBG_MSG4(("[DramcWriteLeveling] Done\n\n"));
+
+    return KResult;
+}
+#endif //SIMULATION_WRITE_LEVELING
+
+#if (fcFOR_CHIP_ID == fcA60868) // Just work around for 868 test chip
+// Set OPT6 = 1 after trigger, and OPT6 = 0 before release
+// When WCKDUAL == 1, CAS-FS command, RTSWCMD_RK must be 2'b11
+// When WCKDUAL == 1, CAS-OFF command must be issue 2 times, RTSWCMD_RK must be 2'b00 and 2'b01 for each
+static void RunTime_SW_Cmd(DRAMC_CTX_T *p, RUNTIME_SWCMD_SEL_T runtime_SW_cmd_sel)
+{
+    U32 u4Response = 0;
+    U32 u4TimeCnt = TIME_OUT_CNT;
+    U32 u4BackupCKECTRL;
+
+    // Backup rank, CKE fix on/off, HW MIOCK control settings
+    u4BackupCKECTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL));
+
+    // Work around case, set both rank CKE_FIXON for CAS-OFF
+    CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ALL_CHANNEL);
+
+    // Select a RT SW command
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), runtime_SW_cmd_sel, SWCMD_EN_RTSWCMD_SEL);
+
+    // Set _CNT, _AGE, _RANK
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT), 0x30, RTSWCMD_CNT_RTSWCMD_CNT);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2),
+            P_Fld(0, SWCMD_CTRL2_RTSWCMD_AGE) |
+            P_Fld(p->rank, SWCMD_CTRL2_RTSWCMD_RK));
+
+    U8 _rank_idx_CAS_OFF = 0;
+    U8 _is_differential_mode = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL), SHU_WCKCTRL_WCKDUAL);
+    while (1)
+    {
+        // Work around case, set specific rank value.
+        if (runtime_SW_cmd_sel == RUNTIME_SWCMD_CAS_OFF)
+        {
+            if ( _is_differential_mode == 0)
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), _rank_idx_CAS_OFF, SWCMD_CTRL2_RTSWCMD_RK);
+        }
+        else if (runtime_SW_cmd_sel == RUNTIME_SWCMD_CAS_FS)
+        {
+            if (_is_differential_mode == 0)
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), 0x3, SWCMD_CTRL2_RTSWCMD_RK);
+        }
+
+        // Trigger RT SW command
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_RTSWCMDEN);
+
+        do
+        {
+            u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_RTSWCMD_RESPONSE);
+            u4TimeCnt --;
+            mcDELAY_US(1);
+        }while ((u4Response == 0) && (u4TimeCnt > 0));
+
+        if (u4TimeCnt == 0)//time out
+        {
+            mcSHOW_ERR_MSG(("[LP5 RT SW Cmd ] Resp fail (time out)\n"));
+        }
+
+        // Release RT SW command
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RTSWCMDEN);
+
+        // Work around case, loop again sending CAS-OFF command for RK1.
+        if (runtime_SW_cmd_sel == RUNTIME_SWCMD_CAS_OFF)
+        {
+            if (_is_differential_mode == 0)
+                if (++_rank_idx_CAS_OFF <= 1)
+                    continue;
+        }
+
+        break;
+    }
+    // Restore rank, CKE fix on
+    vIO32Write4B_All(DRAMC_REG_CKECTRL, u4BackupCKECTRL);
+}
+#else // Single end mode
+#if 0
+static void RunTime_SW_Cmd(DRAMC_CTX_T *p, RUNTIME_SWCMD_SEL_T runtime_SW_cmd_sel)
+{
+    U32 u4Response = 0;
+    U32 u4TimeCnt = TIME_OUT_CNT;
+
+    // Select a RT SW command
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), runtime_SW_cmd_sel, SWCMD_EN_RTSWCMD_SEL);
+
+    // Set _CNT, _AGE, _RANK
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT), 0x30, RTSWCMD_CNT_RTSWCMD_CNT);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2),
+            P_Fld(0, SWCMD_CTRL2_RTSWCMD_AGE) |
+            P_Fld(p->rank, SWCMD_CTRL2_RTSWCMD_RK));
+
+    // If command is CAS_FS/CAS_OFF, replace RTSWCMD_RK = 2'b11.
+    // Avoid this RK value at CAS_FS/CAS_OFF no match.
+    if ((runtime_SW_cmd_sel == RUNTIME_SWCMD_CAS_FS) || (runtime_SW_cmd_sel == RUNTIME_SWCMD_CAS_OFF))
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), 0x3, SWCMD_CTRL2_RTSWCMD_RK);
+
+    // Trigger RT SW command
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_RTSWCMDEN);
+
+    do
+    {
+        u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_RTSWCMD_RESPONSE);
+        u4TimeCnt --;
+        mcDELAY_US(1);
+    }while ((u4Response == 0) && (u4TimeCnt > 0));
+
+    if (u4TimeCnt == 0)//time out
+    {
+        mcSHOW_ERR_MSG(("[LP5 RT SW Cmd ] Resp fail (time out)\n"));
+    }
+
+    // Release RT SW command
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RTSWCMDEN);
+
+}
+#endif
+#endif
+
+#if (SIMULATION_DUTY_CYC_MONITOR == 1)
+static U8 FetchRGSettingVal(int step_val)
+{
+    if (step_val <= 0)
+        return (U8)(-step_val);
+    else
+        return ((U8)step_val | 0x08);
+}
+
+DRAM_STATUS_T DramcDutyCycleMonitor(DRAMC_CTX_T *p)
+{
+    U8 backup_rank;
+//    U8 u8ResultDutyCycMonitor[WHOLE_STEPS_NUM] = {0};
+
+    // error handling
+    if (!p)
+    {
+        mcSHOW_ERR_MSG(("context NULL\n"));
+        return DRAM_FAIL;
+    }
+
+    vAutoRefreshSwitch(p, DISABLE);
+    //CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL);
+
+    backup_rank = u1GetRank(p);
+
+    RunTime_SW_Cmd(p, RUNTIME_SWCMD_CAS_FS);
+
+    int i = -7;
+    for (i = -7; i <= 7; i++)
+    {
+        // MRW MR30 OP[7:4] = i(Set DCAU) and OP[3:0] = i(Set DCAL)
+        U8 u8RGSettingVal = FetchRGSettingVal(i);
+        mcSHOW_ERR_MSG(("Set value %d into MR30\n", u8RGSettingVal));
+        MRWriteFldMulti(p, 30, P_Fld(u8RGSettingVal, MR30_DCAU) |
+                               P_Fld(u8RGSettingVal, MR30_DCAL),
+                               TO_MR);
+
+        // Start duty cycle monitor
+        DramcMRWriteFldAlign(p, 26, 1, MR26_DCM_START_STOP, TO_MR);
+
+        // Delay tDCMM(2us)
+        mcDELAY_US(2);
+
+        // Duty cycle monitor Flip 0 -> 1, and store result of flip = 0
+        DramcMRWriteFldAlign(p, 26, 1, MR26_DCM_FLIP, TO_MR);
+
+        // Delay tDCMM(2us)
+        mcDELAY_US(2);
+
+        // Duty cycle monitor Flip 1 -> 0, and store result of flip = 1
+        DramcMRWriteFldAlign(p, 26, 0, MR26_DCM_FLIP, TO_MR);
+
+        // Delay tDCMM(2us)
+        mcDELAY_US(2);
+
+        // Stop Duty cycle monitor
+        DramcMRWriteFldAlign(p, 26, 0, MR26_DCM_START_STOP, TO_MR);
+
+        // Delay tMRD
+        mcDELAY_US(2);
+
+        mcSHOW_ERR_MSG(("Wait tMRD and MRR MR26\n"));
+
+        ///TODO:  Read back result MR25[5:2]
+        // Store result into u8ResultDutyCycMonitor[]
+
+    }
+    ///TODO:  Find and set a best MR30 variables
+
+    RunTime_SW_Cmd(p, RUNTIME_SWCMD_CAS_OFF);
+
+    vAutoRefreshSwitch(p, ENABLE);
+    //CKEFixOnOff(p, p->rank, CKE_DYNAMIC, TO_ONE_CHANNEL);
+
+    vSetRank(p, backup_rank);
+}
+#endif // SIMULATION_DUTY_CYC_MONITOR
+
+
+void vResetDelayChainBeforeCalibration(DRAMC_CTX_T *p)
+{
+    U8 u1RankIdx, u1RankIdxBak;
+    U32 u4WbrBackup = GetDramcBroadcast();
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    u1RankIdxBak = u1GetRank(p);
+
+    for(u1RankIdx=RANK_0; u1RankIdx<RANK_MAX; u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_CA_TXDLY0,
+            P_Fld(0, SHU_R0_CA_TXDLY0_TX_ARCA0_DLY) |
+            P_Fld(0, SHU_R0_CA_TXDLY0_TX_ARCA1_DLY) |
+            P_Fld(0, SHU_R0_CA_TXDLY0_TX_ARCA2_DLY) |
+            P_Fld(0, SHU_R0_CA_TXDLY0_TX_ARCA3_DLY));
+
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_CA_TXDLY1,
+            P_Fld(0, SHU_R0_CA_TXDLY1_TX_ARCA4_DLY) |
+            P_Fld(0, SHU_R0_CA_TXDLY1_TX_ARCA5_DLY) |
+            P_Fld(0, SHU_R0_CA_TXDLY1_TX_ARCA6_DLY) |
+            P_Fld(0, SHU_R0_CA_TXDLY1_TX_ARCA7_DLY));
+
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0)
+            | P_Fld(0, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0)
+            | P_Fld(0, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0)
+            | P_Fld(0, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0)
+            | P_Fld(0, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0)
+            | P_Fld(0, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0)
+            | P_Fld(0, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
+
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1)
+            | P_Fld(0, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1)
+            | P_Fld(0, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1)
+            | P_Fld(0, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1)
+            | P_Fld(0, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1)
+            | P_Fld(0, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1)
+            | P_Fld(0, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_R0_B0_TXDLY3, 0x0, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0);
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_R0_B1_TXDLY3, 0x0, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1);
+    }
+
+    vSetRank(p, u1RankIdxBak);
+    DramcBroadcastOnOff(u4WbrBackup);
+}
+
+
+//Reset PHY to prevent glitch when change DQS gating delay or RX DQS input delay
+// [Lynx] Evere_st : cannot reset single channel. All DramC and All Phy have to reset together.
+void DramPhyReset(DRAMC_CTX_T *p)
+{
+    // Evere_st change reset order : reset DQS before DQ, move PHY reset to final.
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0), 1, RX_SET0_RDATRST);// read data counter reset
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 1, MISC_CTRL1_R_DMPHYRST);
+
+    //RG_ARCMD_RESETB & RG_ARDQ_RESETB_B0/1 only reset once at init, Justin Chan.
+    ///TODO: need to confirm RG_ARCMD_RESETB & RG_ARDQ_RESETB_B0/1 is reset at mem.c
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9),
+            P_Fld(0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) |
+            P_Fld(0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9),
+            P_Fld(0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) |
+            P_Fld(0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1));
+    mcDELAY_US(1);//delay 10ns
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9),
+            P_Fld(1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) |
+            P_Fld(1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9),
+            P_Fld(1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) |
+            P_Fld(1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0));
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMPHYRST);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0), 0, RX_SET0_RDATRST);// read data counter reset
+}
+
+#if SIMULATION_LP4_ZQ
+//-------------------------------------------------------------------------
+/** DramcZQCalibration
+ *  start Dram ZQ calibration.
+ *  @param p                Pointer of context created by DramcCtxCreate.
+ *  @retval status          (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL
+ */
+//-------------------------------------------------------------------------
+#if ZQ_SWCMD_MODE
+static DRAM_STATUS_T ZQ_SWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
+{
+    U32 u4Response;
+    U32 u4TimeCnt = TIME_OUT_CNT;
+    U32 u4SWCMDEN, u4SWCMDCTRL, u4SPDCTRL, u4CKECTRL;
+
+    // Backup rank, CKE fix on/off, HW MIOCK control settings
+    u4SWCMDEN = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN));
+    u4SWCMDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0));
+    u4SPDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL));
+    u4CKECTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL));
+
+    mcSHOW_DBG_MSG4(("[ZQCalibration]\n"));
+    //mcFPRINTF((fp_A60501, "[ZQCalibration]\n"));
+
+    // Disable HW MIOCK control to make CLK always on
+    DramCLKAlwaysOnOff(p, ON, TO_ONE_CHANNEL);
+    mcDELAY_US(1);
+
+    //if CKE2RANK=1, only need to set CKEFIXON, it will apply to both rank.
+    CKEFixOnOff(p, rank, CKE_FIXON, TO_ONE_CHANNEL);
+
+    //select rank
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), rank, SWCMD_CTRL0_SWTRIG_ZQ_RK);
+
+    //ZQCAL Start
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_ZQCEN_SWTRIG);
+
+    do
+    {
+        u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_ZQC_SWTRIG_RESPONSE);
+        u4TimeCnt --;
+        mcDELAY_US(1);  // Wait tZQCAL(min) 1us or wait next polling
+
+        mcSHOW_DBG_MSG4(("%d- ", u4TimeCnt));
+        //mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt));
+    }while((u4Response==0) &&(u4TimeCnt>0));
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQCEN_SWTRIG);
+
+    if(u4TimeCnt==0)//time out
+    {
+        vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL);
+        mcSHOW_ERR_MSG(("ZQCAL Start fail (time out)\n"));
+        //mcFPRINTF((fp_A60501, "ZQCAL Start fail (time out)\n"));
+        return DRAM_FAIL;
+    }
+
+    // [JC] delay tZQCAL
+    mcDELAY_US(1);
+    u4TimeCnt = TIME_OUT_CNT;
+
+    //ZQCAL Latch
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_ZQLATEN_SWTRIG);
+    do
+    {
+        u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_ZQLAT_SWTRIG_RESPONSE);
+        u4TimeCnt --;
+        mcDELAY_US(1);// Wait tZQLAT 30ns or wait next polling
+
+        mcSHOW_DBG_MSG4(("%d=\n\n", u4TimeCnt));
+        //mcFPRINTF((fp_A60501, "%d= ", u4TimeCnt));
+    }while((u4Response==0) &&(u4TimeCnt>0));
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQLATEN_SWTRIG);
+
+    if(u4TimeCnt==0)//time out
+    {
+        vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL);
+        mcSHOW_ERR_MSG(("ZQCAL Latch fail (time out)\n"));
+        //mcFPRINTF((fp_A60501, "ZQCAL Latch fail (time out)\n"));
+        return DRAM_FAIL;
+    }
+
+    // [JC] delay tZQLAT
+    mcDELAY_US(1);
+
+    // Restore rank, CKE fix on, HW MIOCK control settings
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), u4SWCMDEN);
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u4SWCMDCTRL);
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4SPDCTRL);
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4CKECTRL);
+
+    vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_OK);
+    mcSHOW_DBG_MSG4(("[DramcZQCalibration] Done\n\n"));
+    //mcFPRINTF((fp_A60501, "\n[DramcZQCalibration] Done\n\n"));
+
+    return DRAM_OK;
+}
+#endif
+#if ZQ_RTSWCMD_MODE
+static DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
+{
+    U32 u4Response;
+    U32 u4TimeCnt = TIME_OUT_CNT;
+    U32 u4SWCMDEN, u4SWCMDCTRL, u4MPCCTRL, u4RTSWCMD, u4SPDCTRL, u4CKECTRL;
+
+    // Backup rank, CKE fix on/off, HW MIOCK control settings
+    u4SWCMDEN = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN));
+    u4SWCMDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2));
+    u4MPCCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL));
+    u4RTSWCMD = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT));
+    u4SPDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL));
+    u4CKECTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL));
+
+    mcSHOW_DBG_MSG4(("[ZQCalibration]\n"));
+    //mcFPRINTF((fp_A60501, "[ZQCalibration]\n"));
+
+    // Disable HW MIOCK control to make CLK always on
+    //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF);
+    //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_TCKFIXON);
+    mcDELAY_US(1);
+
+    //if CKE2RANK=1, only need to set CKEFIXON, it will apply to both rank.
+    //CKEFixOnOff(p, rank, CKE_FIXON, TO_ONE_CHANNEL);
+
+    //select rank
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2),
+        P_Fld(rank, SWCMD_CTRL2_RTSWCMD_RK) |
+        P_Fld(0x20, SWCMD_CTRL2_RTSWCMD_AGE));
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 0x1, MPC_CTRL_RTSWCMD_HPRI_EN);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT), 0x2a, RTSWCMD_CNT_RTSWCMD_CNT);
+
+    //ZQCAL Start
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x5, SWCMD_EN_RTSWCMD_SEL);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_RTSWCMDEN);
+
+    do
+    {
+        u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_RTSWCMD_RESPONSE);
+        u4TimeCnt --;
+        mcDELAY_US(1);  // Wait tZQCAL(min) 1us or wait next polling
+
+        mcSHOW_DBG_MSG4(("%d- ", u4TimeCnt));
+        //mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt));
+    }while((u4Response==0) &&(u4TimeCnt>0));
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RTSWCMDEN);
+
+    if(u4TimeCnt==0)//time out
+    {
+        vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL);
+        mcSHOW_ERR_MSG(("ZQCAL Start fail (time out)\n"));
+        //mcFPRINTF((fp_A60501, "ZQCAL Start fail (time out)\n"));
+        return DRAM_FAIL;
+    }
+
+    // [JC] delay tZQCAL
+    mcDELAY_US(1);
+    u4TimeCnt = TIME_OUT_CNT;
+
+    //ZQCAL Latch
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x6, SWCMD_EN_RTSWCMD_SEL);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_RTSWCMDEN);
+
+    do
+    {
+        u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_RTSWCMD_RESPONSE);
+        u4TimeCnt --;
+        mcDELAY_US(1);// Wait tZQLAT 30ns or wait next polling
+
+        mcSHOW_DBG_MSG4(("%d=", u4TimeCnt));
+        //mcFPRINTF((fp_A60501, "%d= ", u4TimeCnt));
+    }while((u4Response==0) &&(u4TimeCnt>0));
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RTSWCMDEN);
+
+    if(u4TimeCnt==0)//time out
+    {
+        vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL);
+        mcSHOW_ERR_MSG(("ZQCAL Latch fail (time out)\n"));
+        //mcFPRINTF((fp_A60501, "ZQCAL Latch fail (time out)\n"));
+        return DRAM_FAIL;
+    }
+
+    // [JC] delay tZQLAT
+    mcDELAY_US(1);
+
+    // Restore rank, CKE fix on, HW MIOCK control settings
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), u4SWCMDEN);
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), u4SWCMDCTRL);
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), u4MPCCTRL);
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT), u4RTSWCMD);
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4SPDCTRL);
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4CKECTRL);
+
+    vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_OK);
+    mcSHOW_DBG_MSG4(("\n[DramcZQCalibration] Done\n\n"));
+    //mcFPRINTF((fp_A60501, "\n[DramcZQCalibration] Done\n\n"));
+
+    return DRAM_OK;
+}
+#endif
+#if ZQ_SCSM_MODE
+static DRAM_STATUS_T ZQ_SCSM_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
+{
+    U32 u4Response;
+    U32 u4TimeCnt = TIME_OUT_CNT;
+    U32 u4SWCMDEN, u4MPCCTRL, u4SWCMDCTRL, u4SPDCTRL, u4CKECTRL;
+
+    // Backup rank, CKE fix on/off, HW MIOCK control settings
+    u4SWCMDEN = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN));
+    u4SWCMDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0));
+    u4MPCCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION));
+    u4SPDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL));
+    u4CKECTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL));
+
+    mcSHOW_DBG_MSG4(("[ZQCalibration]\n"));
+    //mcFPRINTF((fp_A60501, "[ZQCalibration]\n"));
+
+    // Disable HW MIOCK control to make CLK always on
+    DramCLKAlwaysOnOff(p, ON, TO_ONE_CHANNEL);
+    mcDELAY_US(1);
+
+    //if CKE2RANK=1, only need to set CKEFIXON, it will apply to both rank.
+    CKEFixOnOff(p, rank, CKE_FIXON, TO_ONE_CHANNEL);
+
+    //Use rank swap or MRSRK to select rank
+    //DramcRankSwap(p, p->rank);
+    //!!R_DMMRSRK(R_DMMPCRKEN=1) specify rank0 or rank1
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), rank, SWCMD_CTRL0_MRSRK);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION), 1, MPC_OPTION_MPCRKEN);
+
+    //ZQCAL Start
+    //R_DMZQCEN, 0x1E4[4]=1 for ZQCal Start
+    //Wait zqc_response=1 (dramc_conf_nao, 0x3b8[4])
+    //R_DMZQCEN, 0x1E4[4]=0
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_ZQCEN);
+    do
+    {
+        u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_ZQC_RESPONSE);
+        u4TimeCnt --;
+        mcDELAY_US(1);  // Wait tZQCAL(min) 1us or wait next polling
+
+        mcSHOW_DBG_MSG4(("%d- ", u4TimeCnt));
+        //mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt));
+    }while((u4Response==0) &&(u4TimeCnt>0));
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQCEN);
+
+    if(u4TimeCnt==0)//time out
+    {
+        vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL);
+        mcSHOW_ERR_MSG(("ZQCAL Start fail (time out)\n"));
+        //mcFPRINTF((fp_A60501, "ZQCAL Start fail (time out)\n"));
+        return DRAM_FAIL;
+    }
+
+    // [JC] delay tZQCAL
+    mcDELAY_US(1);
+    u4TimeCnt = TIME_OUT_CNT;
+
+    //ZQCAL Latch
+    //R_DMZQLATEN, 0x1E4[6]=1 for ZQCal latch
+    //Wait zqlat_response=1 (dramc_conf_nao, 0x3b8[28])
+    //R_DMZQLATEN, 0x1E4[6]=0
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_ZQLATEN);
+    do
+    {
+        u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_ZQLAT_RESPONSE);
+        u4TimeCnt --;
+        mcDELAY_US(1);// Wait tZQLAT 30ns or wait next polling
+
+        mcSHOW_DBG_MSG4(("%d=", u4TimeCnt));
+        //mcFPRINTF((fp_A60501, "%d= ", u4TimeCnt));
+    }while((u4Response==0) &&(u4TimeCnt>0));
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQLATEN);
+
+    if(u4TimeCnt==0)//time out
+    {
+        vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL);
+        mcSHOW_ERR_MSG(("ZQCAL Latch fail (time out)\n"));
+        //mcFPRINTF((fp_A60501, "ZQCAL Latch fail (time out)\n"));
+        return DRAM_FAIL;
+    }
+
+    // [JC] delay tZQLAT
+    mcDELAY_US(1);
+
+    // Restore rank, CKE fix on, HW MIOCK control settings
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), u4SWCMDEN);
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), u4SWCMDCTRL);
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), u4MPCCTRL);
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4SPDCTRL);
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4CKECTRL);
+
+    vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_OK);
+    mcSHOW_DBG_MSG4(("\n[DramcZQCalibration] Done\n\n"));
+    //mcFPRINTF((fp_A60501, "\n[DramcZQCalibration] Done\n\n"));
+
+    return DRAM_OK;
+}
+#endif
+
+DRAM_STATUS_T DramcZQCalibration(DRAMC_CTX_T *p, U8 rank)
+{
+    #if ZQ_SWCMD_MODE
+    return ZQ_SWCMD_MODE_Cal(p, rank);
+    #elif ZQ_RTSWCMD_MODE
+    return ZQ_RTSWCMD_MODE_Cal(p, rank);
+    #else //ZQ_SCSM_MODE
+    return ZQ_SCSM_MODE_Cal(p, rank);
+    #endif
+}
+#endif
+
+#if ENABLE_RX_INPUT_BUFF_OFF_K
+static U8 RXInputBuf_DelayExchange(S8 iOfst)
+{
+    U8 u1Value;
+
+    if(iOfst <0)
+    {
+        u1Value = 0x8 | (-iOfst);
+    }
+    else
+    {
+        u1Value = iOfst;
+    }
+
+    return u1Value;
+}
+
+// cannot be simulated in DV or DSim, it's analog feature.
+DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p)
+{
+	S8 iOffset, s1begin, s1end;
+	S8 s1DQFinalFlagChange[DQ_DATA_WIDTH], s1DQMFinalFlagChange[DQM_BYTE_NUM];
+	U8 u1BitIdx, u1ByteIdx, u1FinishCount, u1step, u1DQFinal_rg_offset[DQ_DATA_WIDTH], u1DQMFinal_rg_offset[DQM_BYTE_NUM];
+	//U8 *uiLPDDR_O1_Mapping = NULL;
+	U8 ii, read_val_b0 = u1GetRank(p); //u1rank_backup
+	U8 u1Offc_RgValue, u1O1_value;
+	U32 u4RestltDQ, u4RestltDQ_B0, u4RestltDQ_B1, u4RestltDQM[DQM_BYTE_NUM];
+	BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+	U32 u4RegBackupAddress[] =
+	{
+		(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5)),
+		(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5)),
+		(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD5)),
+		(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)),
+		(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)),
+		(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6)),
+		(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3)),
+		(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3)),
+		(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD3)),
+		(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3)),
+		(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3)),
+		(DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3)),
+		(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL)),
+	};
+
+	vSetCalibrationResult(p, DRAM_CALIBRATION_RX_INPUT_BUFF_OFFC, DRAM_FAIL);
+	mcSHOW_DBG_MSG2(("\n[DramcRXInputBufferOffsetCal] \n"));
+#if VENDER_JV_LOG
+	vPrintCalibrationBasicInfo_ForJV(p);
+#else
+	vPrintCalibrationBasicInfo(p);
+#endif
+
+	DramcBackupRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress));
+
+    //Swith RX from Rank1 to Rank0
+	DramcEngine2Run(p, TE_OP_READ_CHECK, TEST_AUDIO_PATTERN);
+
+	vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), 0xf, MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN);
+
+	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6),
+					P_Fld(1, B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0) |
+					P_Fld(1, B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0) |
+					P_Fld(0, B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0) |
+					P_Fld(1, B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0));
+	if (!isLP4_DSC)
+	{
+	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6),
+					P_Fld(1, B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1) |
+					P_Fld(1, B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1)  |
+					P_Fld(0, B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1) |
+					P_Fld(1, B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1));
+	}
+	else
+	{
+	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6),
+					P_Fld(1, CA_CMD6_RG_RX_ARCMD_BIAS_PS) |
+					P_Fld(1, CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN)  |
+					P_Fld(0, CA_CMD6_RG_TX_ARCMD_DDR3_SEL) |
+					P_Fld(1, CA_CMD6_RG_TX_ARCMD_DDR4_SEL));
+	}
+
+	//Enable VREF, (RG_RX_*DQ_VREF_EN_* =1)
+	vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), 1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0);
+	if (!isLP4_DSC)
+		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), 1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1);
+	else
+		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD5), 1, CA_CMD5_RG_RX_ARCMD_VREF_EN);
+
+	// Wait 1us.
+	mcDELAY_US(1);
+
+	//Enable RX input buffer (RG_RX_*DQ_IN_BUFF_EN_* =1, DA_RX_*DQ_IN_GATE_EN_* =1)
+	//Enable RX input buffer offset calibration (RG_RX_*DQ_OFFC_EN_*=1)
+	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3), P_Fld(1, B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0) | P_Fld(1, B0_DQ3_RG_RX_ARDQ_OFFC_EN_B0));
+	if (!isLP4_DSC)
+	{
+	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3), P_Fld(1, B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1) | P_Fld(1, B1_DQ3_RG_RX_ARDQ_OFFC_EN_B1));
+	}
+	else
+	{
+		vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD3), P_Fld(1, CA_CMD3_RG_RX_ARCMD_IN_BUFF_EN) | P_Fld(1, CA_CMD3_RG_RX_ARCLK_IN_BUFF_EN));
+	}
+
+	// DQ_BUFF_EN_SEL
+	vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), 1, B0_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B0);
+	if (!isLP4_DSC)
+	{
+	vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3), 1, B1_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B1);
+	}
+	else
+	{
+		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3), 1, CA_PHY3_RG_RX_ARCA_BUFF_EN_SEL_CA);
+	}
+
+	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11),
+            P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) |
+            P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0));
+	if (!isLP4_DSC)
+	{
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11),
+            P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) |
+            P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1));
+	}
+	else
+	{
+		vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11),
+			P_Fld(0x1, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA) |
+			P_Fld(0x1, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA));
+	}
+
+	vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), 1, B0_DQ6_RG_RX_ARDQ_O1_SEL_B0);
+	if (!isLP4_DSC)
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), 1, B1_DQ6_RG_RX_ARDQ_O1_SEL_B1);
+	else
+		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6), 1, CA_CMD6_RG_RX_ARCMD_O1_SEL);
+
+	// SW parameter initialization
+	u1FinishCount =0;
+    s1begin = -7;
+	s1end = 8;
+	u1step = 1;
+
+	memset(s1DQFinalFlagChange, 0x7f, sizeof(s1DQFinalFlagChange));
+	memset(s1DQMFinalFlagChange, 0x7f, sizeof(s1DQMFinalFlagChange));
+
+	//Sweep RX offset calibration code (RG_RX_*DQ*_OFFC<3:0>), the MSB is sign bit, sweep the code from -7(1111) to +7(0111)
+	for(iOffset = s1begin; iOffset < s1end; iOffset+=u1step)
+	{
+		u1Offc_RgValue = RXInputBuf_DelayExchange(iOffset);
+
+		mcSHOW_DBG_MSG2(("iOffset= %2d, set %2d,", iOffset, u1Offc_RgValue));
+
+		//Delay of B0/B1 DQ0~DQ7.
+		vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQ0),
+            P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ0_OFFC_B0) |
+            P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ1_OFFC_B0) |
+            P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ2_OFFC_B0) |
+            P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ3_OFFC_B0) |
+            P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ4_OFFC_B0) |
+            P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ5_OFFC_B0) |
+            P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ6_OFFC_B0) |
+            P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ7_OFFC_B0));
+		if (!isLP4_DSC)
+		{
+		vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQ0),
+            P_Fld(u1Offc_RgValue, SHU_RK_B1_DQ0_RG_RX_ARDQ0_OFFC_B1) |
+            P_Fld(u1Offc_RgValue, SHU_RK_B1_DQ0_RG_RX_ARDQ1_OFFC_B1) |
+            P_Fld(u1Offc_RgValue, SHU_RK_B1_DQ0_RG_RX_ARDQ2_OFFC_B1) |
+            P_Fld(u1Offc_RgValue, SHU_RK_B1_DQ0_RG_RX_ARDQ3_OFFC_B1) |
+            P_Fld(u1Offc_RgValue, SHU_RK_B1_DQ0_RG_RX_ARDQ4_OFFC_B1) |
+            P_Fld(u1Offc_RgValue, SHU_RK_B1_DQ0_RG_RX_ARDQ5_OFFC_B1) |
+            P_Fld(u1Offc_RgValue, SHU_RK_B1_DQ0_RG_RX_ARDQ6_OFFC_B1) |
+            P_Fld(u1Offc_RgValue, SHU_RK_B1_DQ0_RG_RX_ARDQ7_OFFC_B1));
+		}
+		else
+		{
+			vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_CA_CMD0),
+				P_Fld(u1Offc_RgValue, SHU_RK_CA_CMD0_RG_RX_ARCA0_OFFC) |
+				P_Fld(u1Offc_RgValue, SHU_RK_CA_CMD0_RG_RX_ARCA1_OFFC) |
+				P_Fld(u1Offc_RgValue, SHU_RK_CA_CMD0_RG_RX_ARCA2_OFFC) |
+				P_Fld(u1Offc_RgValue, SHU_RK_CA_CMD0_RG_RX_ARCA3_OFFC) |
+				P_Fld(u1Offc_RgValue, SHU_RK_CA_CMD0_RG_RX_ARCA4_OFFC) |
+				P_Fld(u1Offc_RgValue, SHU_RK_CA_CMD0_RG_RX_ARCA5_OFFC));
+			vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_CA_DQ_OFFSET),
+				P_Fld(u1Offc_RgValue, SHU_RK_CA_DQ_OFFSET_RG_RX_ARDQ6_OFFSETC_C0) |
+				P_Fld(u1Offc_RgValue, SHU_RK_CA_DQ_OFFSET_RG_RX_ARDQ7_OFFSETC_C0));
+		}
+
+		//Delay of B0/B1 DQM0
+		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQ1), u1Offc_RgValue, SHU_RK_B0_DQ1_RG_RX_ARDQM0_OFFC_B0);
+		if (!isLP4_DSC)
+		{
+		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQ1), u1Offc_RgValue, SHU_RK_B1_DQ1_RG_RX_ARDQM0_OFFC_B1);
+		}
+		else
+		{
+		    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_CA_CMD1), u1Offc_RgValue, SHU_RK_CA_CMD1_RG_RX_ARCS0_OFFC);
+		}
+
+		//For each code sweep, wait 0.1us to check the flag.
+		mcDELAY_US(1);
+
+		//Check offset flag of DQ (RGS_*DQ*_OFFSET_FLAG_*), the value will be from 1(-7) to 0(+7). Record the value when the flag becomes "0".
+		//Flag bit0 is for DQ0,  Flag bit15 for DQ15
+		u4RestltDQ_B0 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_DQ_O1), MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B0);
+		if (!isLP4_DSC)
+		{
+			u4RestltDQ_B1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_DQ_O1), MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B1);
+		}
+		else
+		{
+			u4RestltDQ_B1 = ((u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_CMD_O1)))&0x3f)\
+							|(u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_DQ_O1), MISC_AD_RX_DQ_O1_AD_RX_ARDQ6_O1_C0)<<0x6)\
+							|(u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_DQ_O1), MISC_AD_RX_DQ_O1_AD_RX_ARDQ7_O1_C0)<<0x7);
+		}
+             u4RestltDQ = u4RestltDQ_B0|(u4RestltDQ_B1<<8);
+             mcSHOW_DBG_MSG2((" DQ O1 = 0x%x, ", u4RestltDQ));
+
+		for(u1BitIdx= 0; u1BitIdx < DQ_DATA_WIDTH ; u1BitIdx++)
+		{
+			if(s1DQFinalFlagChange[u1BitIdx] == 0x7f) //invalid
+			{
+				u1O1_value = (u4RestltDQ >> u1BitIdx) & 0x1;
+
+				if(u1O1_value ==0) // 1 -> 0
+				{
+					s1DQFinalFlagChange[u1BitIdx] = iOffset;
+					u1FinishCount ++;
+#if __ETT__
+					if(iOffset == s1begin)
+					{
+					    mcSHOW_ERR_MSG(("Error! didn't find trainsition point\n"));
+					}
+#endif
+				}
+				else if(iOffset >= (s1end - u1step))
+				{
+				    s1DQFinalFlagChange[u1BitIdx] = iOffset;
+					u1FinishCount ++;
+
+					mcSHOW_ERR_MSG(("Error! didn't find trainsition point\n"));
+				}
+			}
+		}
+
+		//Check offset flag of DQM (RGS_*DQ*_OFFSET_FLAG_*), the value will be from 1(-7) to 0(+7). Record the value when the flag becomes "0".
+		u4RestltDQM[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_DQ_O1), MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B0);
+		if (!isLP4_DSC)
+		{
+		u4RestltDQM[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_DQ_O1), MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B1);
+		}
+		else
+		{
+			u4RestltDQM[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_CMD_O1), MISC_AD_RX_CMD_O1_AD_RX_ARCS0_O1);
+		}
+
+		mcSHOW_DBG_MSG2(("DQM O1 (B1)= 0x%2x, (B0)= 0x%2x\n", u4RestltDQM[1], u4RestltDQM[0]));
+
+		for(u1ByteIdx= 0; u1ByteIdx < DQM_BYTE_NUM; u1ByteIdx++)
+		{
+			if(s1DQMFinalFlagChange[u1ByteIdx]== 0x7f) //invalid
+			{
+				if(u4RestltDQM[u1ByteIdx]==0)// 1 -> 0
+				{
+					s1DQMFinalFlagChange[u1ByteIdx]= iOffset;
+					u1FinishCount++;
+#if __ETT__
+					if(iOffset == s1begin)
+					{
+					    mcSHOW_ERR_MSG(("Error! didn't find trainsition point\n"));
+					}
+#endif
+				}
+				else if(iOffset == (s1end - u1step))
+				{
+				    s1DQMFinalFlagChange[u1ByteIdx] = iOffset;
+					u1FinishCount ++;
+
+					mcSHOW_ERR_MSG(("Error! didn't find trainsition point\n"));
+				}
+			}
+		}
+
+		if(u1FinishCount==(DQM_BYTE_NUM+DQ_DATA_WIDTH)) // (DQ8 bits, DQM 1bit, total 9 bits.) x2 bytes
+		{
+		    vSetCalibrationResult(p, DRAM_CALIBRATION_RX_INPUT_BUFF_OFFC, DRAM_OK);
+		    mcSHOW_DBG_MSG2(("All bits find pass window, early break!\n"));
+			break; //all bits done, early break
+		}
+	}
+
+	mcSHOW_DBG_MSG2(("O1 Result DQ : [00]%3d [01]%3d [02]%3d [03]%3d [04]%3d [05]%3d [06]%3d [07]%3d\n",
+					s1DQFinalFlagChange[0], s1DQFinalFlagChange[1], s1DQFinalFlagChange[2], s1DQFinalFlagChange[3],
+					s1DQFinalFlagChange[4], s1DQFinalFlagChange[5], s1DQFinalFlagChange[6], s1DQFinalFlagChange[7]));
+	mcSHOW_DBG_MSG2(("O1 Result DQ : [08]%3d [09]%3d [10]%3d [11]%3d [12]%3d [13]%3d [14]%3d [15]%3d\n",
+					s1DQFinalFlagChange[8], s1DQFinalFlagChange[9], s1DQFinalFlagChange[10], s1DQFinalFlagChange[11],
+					s1DQFinalFlagChange[12], s1DQFinalFlagChange[13], s1DQFinalFlagChange[14],s1DQFinalFlagChange[15]));
+	mcSHOW_DBG_MSG2(("O1 Result DQM0 %2d Result DQM1 %2d,\n", s1DQMFinalFlagChange[0], s1DQMFinalFlagChange[1]));
+
+	for(u1BitIdx= 0; u1BitIdx <DQ_DATA_WIDTH; u1BitIdx++)
+	{
+	    u1DQFinal_rg_offset[u1BitIdx] = RXInputBuf_DelayExchange(s1DQFinalFlagChange[u1BitIdx]);
+#ifdef FOR_HQA_REPORT_USED
+            if (gHQALog_flag == 1)
+            {
+                HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_1, "RX_Input_Offset", " ", u1BitIdx, s1DQFinalFlagChange[u1BitIdx], NULL);
+            }
+#endif
+	}
+	u1DQMFinal_rg_offset[0]= RXInputBuf_DelayExchange(s1DQMFinalFlagChange[0]);
+	u1DQMFinal_rg_offset[1]= RXInputBuf_DelayExchange(s1DQMFinalFlagChange[1]);
+#ifdef FOR_HQA_REPORT_USED
+    if (gHQALog_flag == 1)
+    {
+        HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("RX_Input_Offset  Channel%d Rank%d DQM0 %d\n", p->channel, p->rank, s1DQMFinalFlagChange[0]));
+        HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("RX_Input_Offset  Channel%d Rank%d DQM1 %d\n", p->channel, p->rank, s1DQMFinalFlagChange[1]));
+    }
+#endif
+
+    for (ii = RANK_0; ii < p->support_rank_num; ii++)
+    {
+        vSetRank(p, ii);
+
+	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQ0),
+            P_Fld(u1DQFinal_rg_offset[0], SHU_RK_B0_DQ0_RG_RX_ARDQ0_OFFC_B0) |
+            P_Fld(u1DQFinal_rg_offset[1], SHU_RK_B0_DQ0_RG_RX_ARDQ1_OFFC_B0) |
+            P_Fld(u1DQFinal_rg_offset[2], SHU_RK_B0_DQ0_RG_RX_ARDQ2_OFFC_B0) |
+            P_Fld(u1DQFinal_rg_offset[3], SHU_RK_B0_DQ0_RG_RX_ARDQ3_OFFC_B0) |
+            P_Fld(u1DQFinal_rg_offset[4], SHU_RK_B0_DQ0_RG_RX_ARDQ4_OFFC_B0) |
+            P_Fld(u1DQFinal_rg_offset[5], SHU_RK_B0_DQ0_RG_RX_ARDQ5_OFFC_B0) |
+            P_Fld(u1DQFinal_rg_offset[6], SHU_RK_B0_DQ0_RG_RX_ARDQ6_OFFC_B0) |
+            P_Fld(u1DQFinal_rg_offset[7], SHU_RK_B0_DQ0_RG_RX_ARDQ7_OFFC_B0));
+		if (!isLP4_DSC)
+		{
+			vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQ0),
+				P_Fld(u1DQFinal_rg_offset[8], SHU_RK_B1_DQ0_RG_RX_ARDQ0_OFFC_B1) |
+				P_Fld(u1DQFinal_rg_offset[9], SHU_RK_B1_DQ0_RG_RX_ARDQ1_OFFC_B1) |
+				P_Fld(u1DQFinal_rg_offset[10], SHU_RK_B1_DQ0_RG_RX_ARDQ2_OFFC_B1) |
+				P_Fld(u1DQFinal_rg_offset[11], SHU_RK_B1_DQ0_RG_RX_ARDQ3_OFFC_B1) |
+				P_Fld(u1DQFinal_rg_offset[12], SHU_RK_B1_DQ0_RG_RX_ARDQ4_OFFC_B1) |
+				P_Fld(u1DQFinal_rg_offset[13], SHU_RK_B1_DQ0_RG_RX_ARDQ5_OFFC_B1) |
+				P_Fld(u1DQFinal_rg_offset[14], SHU_RK_B1_DQ0_RG_RX_ARDQ6_OFFC_B1) |
+				P_Fld(u1DQFinal_rg_offset[15], SHU_RK_B1_DQ0_RG_RX_ARDQ7_OFFC_B1));
+		}
+		else
+		{
+			vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_CA_CMD0),
+				P_Fld(u1DQFinal_rg_offset[8], SHU_RK_CA_CMD0_RG_RX_ARCA0_OFFC) |
+				P_Fld(u1DQFinal_rg_offset[9], SHU_RK_CA_CMD0_RG_RX_ARCA1_OFFC) |
+				P_Fld(u1DQFinal_rg_offset[10], SHU_RK_CA_CMD0_RG_RX_ARCA2_OFFC) |
+				P_Fld(u1DQFinal_rg_offset[11], SHU_RK_CA_CMD0_RG_RX_ARCA3_OFFC) |
+				P_Fld(u1DQFinal_rg_offset[12], SHU_RK_CA_CMD0_RG_RX_ARCA4_OFFC) |
+				P_Fld(u1DQFinal_rg_offset[13], SHU_RK_CA_CMD0_RG_RX_ARCA5_OFFC));
+			vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_CA_DQ_OFFSET),
+				P_Fld(u1DQFinal_rg_offset[14], SHU_RK_CA_DQ_OFFSET_RG_RX_ARDQ6_OFFSETC_C0) |
+				P_Fld(u1DQFinal_rg_offset[15], SHU_RK_CA_DQ_OFFSET_RG_RX_ARDQ7_OFFSETC_C0));
+		}
+
+		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQ1), u1DQMFinal_rg_offset[0], SHU_RK_B0_DQ1_RG_RX_ARDQM0_OFFC_B0);
+		if (!isLP4_DSC)
+		{
+		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQ1), u1DQMFinal_rg_offset[1], SHU_RK_B1_DQ1_RG_RX_ARDQM0_OFFC_B1);
+		}
+		else
+		{
+		    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_CA_CMD1), u1DQMFinal_rg_offset[1], SHU_RK_CA_CMD1_RG_RX_ARCS0_OFFC);
+		}
+    }
+	vSetRank(p, read_val_b0);
+
+	//need to set 0 after DramcRXInputBufferOffsetCal
+	//vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), 0x0, MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN);
+	//vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), 0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0);
+	//vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), 0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1);
+
+	DramcRestoreRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress));
+
+	//after K, must set OFFSET_BIAS_EN as1 and OFFSET_EN as 0
+	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11),
+            P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) |
+            P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0));
+	if (!isLP4_DSC)
+	{
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11),
+            P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) |
+            P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1));
+	}
+	else
+	{
+		vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11),
+			P_Fld(0x1, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA) |
+			P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA));
+	}
+
+	mcSHOW_DBG_MSG2(("[DramcRXInputBufferOffsetCal] ====Done====\n"));
+
+	return DRAM_OK;
+}
+#endif
+
+#if (SIMULATION_GATING == 1)
+#define GATING_PATTERN_NUM_LP5      0x23
+#define GATING_GOLDEND_DQSCNT_LP5   0x4646
+#define RXDQS_GATING_AUTO_DBG_REG_NUM       6
+/* Preamble & Postamble setting. Currently use macro to define.
+ * Later may use speed or MR setting to decide
+ * !!! REVIEW !!!
+ */
+
+#if GATING_ADJUST_TXDLY_FOR_TRACKING
+U8 u1TXDLY_Cal_min =0xff, u1TXDLY_Cal_max=0;
+U8 ucbest_coarse_mck_backup[RANK_MAX][DQS_BYTE_NUMBER];
+U8 ucbest_coarse_ui_backup[RANK_MAX][DQS_BYTE_NUMBER];
+U8 ucbest_coarse_mck_P1_backup[RANK_MAX][DQS_BYTE_NUMBER];
+U8 ucbest_coarse_ui_P1_backup[RANK_MAX][DQS_BYTE_NUMBER];
+#endif
+
+
+struct rxdqs_gating_cal {
+    U8 dqsien_dly_mck;
+    U8 dqsien_dly_ui;
+    U8 dqsien_dly_pi;
+
+    U8 dqsien_dly_mck_p1;
+    U8 dqsien_dly_ui_p1;
+
+    U8 dqsien_pi_adj_step;
+
+    U8 dqsien_pi_per_ui;
+    U8 dqsien_ui_per_mck;
+    U8 dqsien_freq_div;
+};
+
+struct rxdqs_gating_trans {
+    U8 dqs_lead[DQS_BYTE_NUMBER];
+    U8 dqs_lag[DQS_BYTE_NUMBER];
+    U8 dqs_high[DQS_BYTE_NUMBER];
+#if GATING_LEADLAG_LOW_LEVEL_CHECK
+    U8 dqs_low[DQS_BYTE_NUMBER];
+#endif
+    U8 dqs_transition[DQS_BYTE_NUMBER];
+    U8 dqs_transitioned[DQS_BYTE_NUMBER];
+    U8 dqsien_dly_mck_leadlag[DQS_BYTE_NUMBER];
+    U8 dqsien_dly_ui_leadlag[DQS_BYTE_NUMBER];
+    U8 dqsien_dly_pi_leadlag[DQS_BYTE_NUMBER];
+};
+
+struct rxdqs_gating_best_win {
+    U8 best_dqsien_dly_mck[DQS_BYTE_NUMBER];
+    U8 best_dqsien_dly_ui[DQS_BYTE_NUMBER];
+    U8 best_dqsien_dly_pi[DQS_BYTE_NUMBER];
+    U8 best_dqsien_dly_mck_p1[DQS_BYTE_NUMBER];
+    U8 best_dqsien_dly_ui_p1[DQS_BYTE_NUMBER];
+    U8 best_dqsien_dly_pi_p1[DQS_BYTE_NUMBER];
+};
+
+struct rxdqs_gating_auto_param {
+    U8 early_break;
+    U8 dbg_mode;
+
+    U8 init_mck;
+    U8 init_ui;
+    U8 end_mck;
+    U8 end_ui;
+    U8 pi_offset;
+
+    U8 burst_len;
+};
+
+#if ENABLE_GATING_AUTOK_WA
+U8 __wa__gating_swk_for_autok = 0;
+U8 __wa__gating_autok_init_ui[RANK_MAX] = { 0 };
+#endif
+
+#if (__LP5_COMBO__)
+static U8 u1GetLp5ReadLatency(DRAMC_CTX_T *p)
+{
+    U8 read_latency;
+    U8 rl, ckr, dvfsc;
+
+    const U8 au1MR2MappingToRL_wo_dvfsc[2][12] = {
+        {3, 4, 5, 6, 8, 9, 10, 12, 13, 14, 15, 17}, /* CKR = 4:1 */
+        {6, 8, 10, 12, 16, 18}, /* CKR = 2:1 */
+    };
+
+    ///TODO: Spec has not specify these values
+    const U8 au1MR2MappingToRL_wi_dvfsc[2][6] = {
+        {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, /* CKR = 4:1 */
+        {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, /* CKR = 2:1 */
+    };
+
+    ckr = (u1MR18Value[p->dram_fsp] >> 7) & 0x1;
+    dvfsc = !!(u1MR19Value[p->dram_fsp] & 0x3);
+    rl = (u1MR02Value[p->dram_fsp] & 0xf);
+
+    if (dvfsc)
+        read_latency = au1MR2MappingToRL_wi_dvfsc[ckr][rl];
+    else
+        read_latency = au1MR2MappingToRL_wo_dvfsc[ckr][rl];
+
+    /* note that the uint of RL is nCK, convert to nWCK */
+    if (ckr == 0)
+        read_latency *= 4;
+    else
+        read_latency *= 2;
+
+    mcSHOW_DBG_MSG2(("ckr = %d, dvfsc = %d, rl = %d, read_latency = %d\n",
+        ckr, dvfsc, rl, read_latency));
+
+    return read_latency;
+}
+#endif
+
+static U8 u1GetGatingStartPos(DRAMC_CTX_T *p, U8 u1AutoK)
+{
+    const U8 au1MR2MappingToRL[2][8] = {{6, 10, 14, 20, 24, 28, 32, 36},   //normal mode
+                                        {6, 10, 16, 22, 26, 32, 36, 40}};  //byte mode
+    //U8 u1CK2WCK, u1DVFSCEn;
+    U8 u1MR0_LatencyMode;
+    U8 u1MR2RLValue;
+
+    u1MR2RLValue = u1MR02Value[p->dram_fsp] & 0x7; //MR2 Op[2:0]
+    U8 u1RX_Path_delay_UI, u1RealRL,u1StartUI, u1ExtraMCKfor1_4mode;
+    U8 u1MCK2CK_UI, u1ReadDQSINCTL, u1DQSINCTL_UI;
+    U8 u4TDQSCK_UI_min;
+    U8 u1GatingAheadDQS_UI;
+
+    /* LPDDR5 uses same bit */
+    if(gu2MR0_Value[p->rank] == 0xffff)  //MR0 is not ready
+    {
+        u1MR0_LatencyMode = CBT_NORMAL_MODE;
+    }
+    else
+    {
+        u1MR0_LatencyMode = (gu2MR0_Value[p->rank]>>1) & 0x1; //MR0 OP[1],  0:normal mode,  1:byte mode
+    }
+
+#if (__LP5_COMBO__)
+    if (is_lp5_family(p)) {
+        u4TDQSCK_UI_min = 500 * DDRPhyGetRealFreq(p) *2/ 1000000;
+        u1RealRL = u1GetLp5ReadLatency(p);
+    } else
+#endif
+    {
+        u4TDQSCK_UI_min = 1500 * DDRPhyGetRealFreq(p) *2/ 1000000;
+        u1RealRL = au1MR2MappingToRL[u1MR0_LatencyMode][u1MR2RLValue];
+    }
+
+    ///TODO: A60868 does not support LP5 DIV4, current setting is not provided for LP5
+    if(vGet_Div_Mode(p) == DIV4_MODE)
+    {
+        u1MCK2CK_UI = 4;
+        u1ExtraMCKfor1_4mode = 1;
+        u1GatingAheadDQS_UI = 3;
+    }
+    else if (vGet_Div_Mode(p) == DIV8_MODE)
+    {
+        u1MCK2CK_UI = 8;
+        u1ExtraMCKfor1_4mode = 0;
+#if (__LP5_COMBO__)
+    if (is_lp5_family(p)) {
+        if (p->frequency <= 1600)
+            u1GatingAheadDQS_UI = 1 * u1MCK2CK_UI;
+        else if (p->frequency == 1866)
+            u1GatingAheadDQS_UI = 4;
+        else
+            u1GatingAheadDQS_UI = 8;
+    } else
+#endif
+        u1GatingAheadDQS_UI = 5;
+    }
+    else
+    {
+        /* DIV16, only for LP5 */
+        u1MCK2CK_UI = 16;
+        u1ExtraMCKfor1_4mode = 0;
+        u1GatingAheadDQS_UI = 8;
+    }
+
+    // RX_Path_delay_UI = RL*2 + tDQSCK_UI<1500~3500ps> - PHY_interanl<skip 30ps> - GatingAheadDQS<2UI> + if(1:4 mod)+1MCK
+    u1RX_Path_delay_UI = (u1RealRL<<1) + u4TDQSCK_UI_min - u1GatingAheadDQS_UI + (u1MCK2CK_UI*u1ExtraMCKfor1_4mode);
+
+    u1ReadDQSINCTL = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL), MISC_SHU_RK_DQSCTL_DQSINCTL);
+    u1DQSINCTL_UI = u1ReadDQSINCTL * u1MCK2CK_UI;
+
+    if(u1AutoK)
+        u1RX_Path_delay_UI += 0; //HW K start position =  gating min position(1500ns)
+    else
+        u1RX_Path_delay_UI -= 3; //SW K start position = gating min position(1500ns) -3UI
+
+    if(u1RX_Path_delay_UI >= u1DQSINCTL_UI)
+        u1StartUI = u1RX_Path_delay_UI - u1DQSINCTL_UI;
+    else
+    {
+        u1StartUI =0;
+        mcSHOW_ERR_MSG(("GatingStartPos err! Need to fine-tune default DQSINCTL value.\n(RX_Path_delay_UI %d) < DQSINCTL_UI %d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI));
+        #if __ETT__
+        while(1);
+        #endif
+    }
+
+    mcSHOW_DBG_MSG2(("[DUMPLOG] %d GatingStartPos_MR0_LatencyMode %d, u1RealRL %d , u4TDQSCK_UI_min %d, 1:4ExtraMCK %d\n", p->frequency * 2, u1MR0_LatencyMode, u1RealRL, u4TDQSCK_UI_min, u1ExtraMCKfor1_4mode));
+
+    if(u1AutoK)
+    {
+        mcSHOW_DBG_MSG2(("RX_Path_delay_UI(%d) - DQSINCTL_UI(%d) = u1StartUI(%d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI, u1StartUI));
+    }
+    else
+    {
+        mcSHOW_DBG_MSG2(("RX_Path_delay_UI(%d) -3 - DQSINCTL_UI(%d) = u1StartUI(%d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI, u1StartUI));
+    }
+
+    return u1StartUI;
+}
+
+#if GATING_RODT_LATANCY_EN
+static U8 get_rodt_mck2ui(DRAMC_CTX_T *p)
+{
+    if (vGet_Div_Mode(p) == DIV16_MODE)
+        return 8;
+    else if (vGet_Div_Mode(p) == DIV8_MODE)
+        return 4;
+    else
+        return 2;
+}
+#endif
+
+static u8 rxdqs_gating_bypass(DRAMC_CTX_T *p)
+{
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_GatingCal
+        if (p->femmc_Ready == 1) {
+            mcSHOW_DBG_MSG(("[FAST_K] Bypass Gating Calibration\n"));
+            return 1;
+        }
+#endif
+
+    return 0;
+}
+
+static void rxdqs_gating_fastk_save_restore(DRAMC_CTX_T *p,
+    struct rxdqs_gating_best_win *best_win,
+    struct rxdqs_gating_cal *gating_cal)
+{
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+        u8 ui_per_mck = gating_cal->dqsien_ui_per_mck;
+        u8 freq_div = gating_cal->dqsien_freq_div;
+        u8 ch = p->channel;
+        u8 rk = p->rank;
+        u8 dqs_i;
+
+        if (p->femmc_Ready == 1) {
+            for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) {
+                best_win->best_dqsien_dly_mck[dqs_i] =
+                    p->pSavetimeData->u1Gating_MCK_Save[ch][rk][dqs_i];
+                best_win->best_dqsien_dly_ui[dqs_i] =
+                    p->pSavetimeData->u1Gating_UI_Save[ch][rk][dqs_i];
+                best_win->best_dqsien_dly_pi[dqs_i] =
+                    p->pSavetimeData->u1Gating_PI_Save[ch][rk][dqs_i];
+
+                /* Calculate P1 */
+                best_win->best_dqsien_dly_ui_p1[dqs_i] =
+                    best_win->best_dqsien_dly_mck[dqs_i] * ui_per_mck +
+                    best_win->best_dqsien_dly_ui[dqs_i] + freq_div; /* Total UI for Phase1 */
+                best_win->best_dqsien_dly_mck_p1[dqs_i] =
+                    best_win->best_dqsien_dly_ui_p1[dqs_i] / ui_per_mck;
+                best_win->best_dqsien_dly_ui_p1[dqs_i] =
+                    best_win->best_dqsien_dly_ui_p1[dqs_i] % ui_per_mck;
+
+                vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_FAST_K);
+
+                mcSHOW_DBG_MSG(("[FAST_K] CH%d RK%d best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n",
+                    ch, rk, dqs_i, best_win->best_dqsien_dly_mck[dqs_i],
+                    best_win->best_dqsien_dly_ui[dqs_i],
+                    best_win->best_dqsien_dly_pi[dqs_i]));
+                mcSHOW_DBG_MSG(("[FAST_K] CH%d RK%d best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n",
+                    ch, rk, dqs_i, best_win->best_dqsien_dly_mck_p1[dqs_i],
+                    best_win->best_dqsien_dly_ui_p1[dqs_i],
+                    best_win->best_dqsien_dly_pi_p1[dqs_i]));
+
+            }
+        }
+#endif
+}
+
+static void rxdqs_gating_misc_process(DRAMC_CTX_T *p,
+    struct rxdqs_gating_best_win *rxdqs_best_win)
+{
+#if GATING_ADJUST_TXDLY_FOR_TRACKING
+    U8 u1TX_dly_DQSgated = 0;
+#endif
+    U8 dqs_i;
+
+    for (dqs_i=0; dqs_i<DQS_BYTE_NUMBER; dqs_i++) {
+#ifdef FOR_HQA_REPORT_USED
+        HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT6, "DQSINCTL ", "", 0,
+            u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL), MISC_SHU_RK_DQSCTL_DQSINCTL), NULL);
+        HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0,
+            "Gating_Center_", "2T", dqs_i, rxdqs_best_win->best_dqsien_dly_mck[dqs_i], NULL);
+        HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0,
+            "Gating_Center_", "05T", dqs_i, rxdqs_best_win->best_dqsien_dly_ui[dqs_i], NULL);
+        HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0,
+            "Gating_Center_", "PI", dqs_i, rxdqs_best_win->best_dqsien_dly_pi[dqs_i], NULL);
+#endif
+
+        /*TINFO="best DQS%d delay(2T, 0.5T, PI) = (%d, %d, %d)\n", dqs_i, rxdqs_best_win.best_dqsien_dly_mck[dqs_i], rxdqs_best_win.best_dqsien_dly_ui[dqs_i], rxdqs_best_win.best_dqsien_dly_pi[dqs_i])); */
+        mcSHOW_DBG_MSG(("best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i,
+            rxdqs_best_win->best_dqsien_dly_mck[dqs_i],
+            rxdqs_best_win->best_dqsien_dly_ui[dqs_i],
+            rxdqs_best_win->best_dqsien_dly_pi[dqs_i]));
+        /*mcDUMP_REG_MSG(("best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i,
+            rxdqs_best_win->best_dqsien_dly_mck[dqs_i],
+            rxdqs_best_win->best_dqsien_dly_ui[dqs_i],
+            rxdqs_best_win->best_dqsien_dly_pi[dqs_i]));*/
+        /* cc mark mcFPRINTF((fp_A60501,"best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i,
+            rxdqs_best_win.best_dqsien_dly_mck[dqs_i],
+            rxdqs_best_win.best_dqsien_dly_ui[dqs_i],
+            rxdqs_best_win.best_dqsien_dly_pi[dqs_i]));
+        */
+
+#if GATING_ADJUST_TXDLY_FOR_TRACKING
+    u1TX_dly_DQSgated = (rxdqs_best_win->best_dqsien_dly_mck[dqs_i] << 4) +
+        rxdqs_best_win->best_dqsien_dly_ui[dqs_i];
+
+    if (vGet_Div_Mode(p) == DIV16_MODE)
+        u1TX_dly_DQSgated >>= 4;
+    else if (vGet_Div_Mode(p) == DIV8_MODE)
+        u1TX_dly_DQSgated >>= 3;
+    else
+        u1TX_dly_DQSgated >>= 2;
+
+    if (u1TX_dly_DQSgated < u1TXDLY_Cal_min)
+        u1TXDLY_Cal_min = u1TX_dly_DQSgated;
+
+    ucbest_coarse_ui_backup[p->rank][dqs_i] = rxdqs_best_win->best_dqsien_dly_ui[dqs_i];
+    ucbest_coarse_mck_backup[p->rank][dqs_i] = rxdqs_best_win->best_dqsien_dly_mck[dqs_i];
+#endif
+    }
+
+    mcSHOW_DBG_MSG(("\n"));
+    //cc mark mcFPRINTF((fp_A60501,"\n"));
+
+    for (dqs_i=0; dqs_i<DQS_BYTE_NUMBER; dqs_i++) {
+        /*TINFO="best DQS%d P1 delay(2T, 0.5T, PI) = (%d, %d, %d)\n", dqs_i, rxdqs_best_win.best_dqsien_dly_mck_p1[dqs_i], rxdqs_best_win.best_dqsien_dly_ui_p1[dqs_i], rxdqs_best_win.best_dqsien_dly_pi_p1[dqs_i]*/
+        mcSHOW_DBG_MSG(("best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i,
+            rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i],
+            rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i],
+            rxdqs_best_win->best_dqsien_dly_pi_p1[dqs_i]));
+        /*mcDUMP_REG_MSG(("best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i,
+            rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i],
+            rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i],
+            rxdqs_best_win->best_dqsien_dly_pi_p1[dqs_i]));*/
+        /* cc mark mcFPRINTF((fp_A60501,"best DQS%d P1 dly(2T, 0.5T, PI) = (%d, %d, %d)\n", dqs_i,
+            rxdqs_best_win.best_dqsien_dly_mck_p1[dqs_i],
+            rxdqs_best_win.best_dqsien_dly_ui_p1[dqs_i],
+            rxdqs_best_win.best_dqsien_dly_pi_p1[dqs_i]));
+        */
+
+#if GATING_ADJUST_TXDLY_FOR_TRACKING
+        // find max gating TXDLY (should be in P1)
+        u1TX_dly_DQSgated = (rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i] << 4) +
+            rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i];
+
+        if (vGet_Div_Mode(p) == DIV16_MODE)
+            u1TX_dly_DQSgated >>= 4;
+        else if (vGet_Div_Mode(p) == DIV8_MODE)
+            u1TX_dly_DQSgated >>= 3;
+        else
+            u1TX_dly_DQSgated >>= 2;
+
+        if(u1TX_dly_DQSgated > u1TXDLY_Cal_max)
+            u1TXDLY_Cal_max = u1TX_dly_DQSgated;
+
+        ucbest_coarse_ui_P1_backup[p->rank][dqs_i] = rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i];
+        ucbest_coarse_mck_P1_backup[p->rank][dqs_i] = rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i];
+#endif
+    }
+
+#if RDSEL_TRACKING_EN
+    if(p->frequency >= RDSEL_TRACKING_TH)
+    {
+
+        //Byte 0
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI),
+            (ucbest_coarse_mck_backup[p->rank][0] << 4) | (ucbest_coarse_ui_backup[p->rank][0]),
+            SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0);//UI
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI), rxdqs_best_win->best_dqsien_dly_pi[0],
+            SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0); //PI
+        //Byte 1
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI),
+            (ucbest_coarse_mck_backup[p->rank][1] << 4) | (ucbest_coarse_ui_backup[p->rank][1]),
+            SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1);//UI
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI),
+            rxdqs_best_win->best_dqsien_dly_pi[1], SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1); //PI
+    }
+#endif
+
+}
+
+#if GATING_AUTO_K_SUPPORT
+static void rxdqs_gating_auto_cal_reset(DRAMC_CTX_T *p)
+{
+    /* Reset internal autok status and logic */
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0),
+        P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK0_SW_RST) |
+        P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK1_SW_RST) |
+        P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_SW_RST));
+
+    mcDELAY_US(1);
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0),
+        P_Fld(0x0, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK0_SW_RST) |
+        P_Fld(0x0, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK1_SW_RST) |
+        P_Fld(0x0, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_SW_RST));
+}
+static void rxdqs_gating_auto_cal_cfg(DRAMC_CTX_T *p,
+    struct rxdqs_gating_auto_param *auto_param)
+{
+    /* Before start calibration, reset all state machine and all rank's state */
+    rxdqs_gating_auto_cal_reset(p);
+
+
+    /*-----------
+     * Normal Setting, Same as SW calibration
+     *---------------*/
+    if (p->frequency == 800) {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1),
+            0x1, MISC_STBCAL1_STBCNT_SW_RST);
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1),
+        0x1, MISC_STBCAL1_STBCNT_SHU_RST_EN);
+
+    /* SELPH_MODE = BY RANK */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2),
+        0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN);
+
+    if (p->dram_type == TYPE_LPDDR5) {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2),
+            0x1, MISC_STBCAL2_STB_PICG_EARLY_1T_EN);
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1),
+        0x1, MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD);
+
+    /* PICG_EARLY_EN */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6),
+        0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6),
+        0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2),
+        0x1, MISC_STBCAL2_STB_PICG_EARLY_1T_EN);
+
+    /* BURST_MODE */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
+        0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE);
+
+#if (__LP5_COMBO__)
+    if (is_lp5_family(p)) {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9),
+            0x1, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9),
+            0x1, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1);
+    } else
+#endif
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9),
+            0x1, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9),
+            0x1, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1);
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6),
+        0x2, B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6),
+        0x2, B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL),
+        0x1, MISC_STBCAL_DQSIENMODE);
+
+    /* New Rank Mode */
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2),
+        P_Fld(0x1, MISC_STBCAL2_STB_IG_XRANK_CG_RST) |
+        P_Fld(0x1, MISC_STBCAL2_STB_RST_BY_RANK) |
+        P_Fld(0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN));
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2),
+        0x1, B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2),
+        0x1, B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1);
+
+    /* dummy read */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD),
+        0x1, DUMMY_RD_DUMMY_RD_PA_OPT);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0),
+        0x1, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE);
+
+    //Yulia add workaround for auto K pattern length. : Apply for all project before IPM_V2
+    //Dummy read BL should be controlled by DQSIEN_AUTOK_BURST_LENGTH, but now we can only use dummy read length(DMY_RD_LEN)
+    //DMY_RD_LEN (0 for BL8, 1 for BL16, 3 for BL32)
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR), 3/*auto_param->burst_len*/, RK_DUMMY_RD_ADR_DMY_RD_LEN);
+
+    /* Decide by HW  Although Dummy read used, but TA2 has higher priority */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
+        0x4, TEST2_A4_TESTAGENTRKSEL);
+
+    //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1,
+    //  MISC_STBCAL2_STBENCMPEN);
+
+    /*-----------
+     * Auto calibration setting
+     *-------------------*/
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0),
+        P_Fld(auto_param->init_mck, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_INI_MCK) |
+        P_Fld(auto_param->init_ui, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_INI__UI) |
+        P_Fld(auto_param->end_mck, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_END_MCK) |
+        P_Fld(auto_param->end_ui, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_END__UI) |
+        P_Fld(auto_param->pi_offset, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_PI_OFFSET) |
+        P_Fld(p->rank, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_CUR_RANK) |
+        P_Fld(auto_param->burst_len, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_BURST_LENGTH) |
+        P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_B0_EN) |
+        P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_B1_EN));
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0),
+        auto_param->dbg_mode, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_DEBUG_MODE_EN);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0),
+        auto_param->early_break, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_EARLY_BREAK_EN);
+
+    /*---------
+     * DV settings
+     *-------------------*/
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL),
+        0x0, MISC_STBCAL_PICGEN);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
+        P_Fld(0x0, MISC_SHU_STBCAL_STBCALEN) |
+        P_Fld(0x0, MISC_SHU_STBCAL_STB_SELPHCALEN));
+
+    mcSHOW_DBG_MSG(("[Gating] AUTO K with param:\n"));
+    mcSHOW_DBG_MSG(("\tinit_mck: %d, init_ui: %d, end_mck: %d, end_ui: %d\n",
+        auto_param->init_mck, auto_param->init_ui,
+        auto_param->end_mck, auto_param->end_ui));
+    mcSHOW_DBG_MSG(("\tpi_offset: %d, early_break: %s\n", auto_param->pi_offset,
+        (auto_param->early_break)? "ENABLE" : "DISABLE"));
+}
+
+static void rxdqs_gating_auto_cal_trigger(DRAMC_CTX_T *p)
+{
+    mcSHOW_DBG_MSG(("[Gating] AUTO K start...\n"));
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0),
+        0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_GO);
+}
+
+static void rxdqs_gating_auto_cal_stop(DRAMC_CTX_T *p)
+{
+    mcSHOW_DBG_MSG(("[Gating] AUTO K stop...\n"));
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0),
+        0x0, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_GO);
+
+    rxdqs_gating_auto_cal_reset(p);
+}
+#endif
+
+static void rxdqs_gating_set_final_result(DRAMC_CTX_T *p, U8 mck2ui,
+    struct rxdqs_gating_best_win *best_win)
+{
+    //U8 reg_mck, reg_ui;
+    //U8 value;
+    //U8 reg_mck_rodt[DQS_BYTE_NUMBER], reg_ui_rodt[DQS_BYTE_NUMBER];
+    //U8 reg_mck_rodt_p1[DQS_BYTE_NUMBER], reg_ui_rodt_p1[DQS_BYTE_NUMBER];
+    //U8 dqs_i;
+
+#if GATING_RODT_LATANCY_EN
+    for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) {
+        reg_mck = best_win->best_dqsien_dly_mck[dqs_i];
+        reg_ui = best_win->best_dqsien_dly_ui[dqs_i];
+
+        value = (reg_mck * mck2ui) + reg_ui;
+
+        if (value >= 11) {
+            U8 rodt_mck2ui = get_rodt_mck2ui(p);
+
+            value -= 11;
+            reg_mck_rodt[dqs_i] = value / rodt_mck2ui;
+            reg_ui_rodt[dqs_i] = value % rodt_mck2ui;
+
+            reg_mck_rodt_p1[dqs_i] = reg_mck_rodt[dqs_i];
+            reg_ui_rodt_p1[dqs_i] = reg_ui_rodt[dqs_i];
+        } else {
+
+            reg_mck_rodt[dqs_i] = 0;
+            reg_ui_rodt[dqs_i] = 0;
+            reg_mck_rodt_p1[dqs_i] = 4;
+            reg_ui_rodt_p1[dqs_i] = 4;
+            mcSHOW_DBG_MSG(("[Warning] RODT cannot be -11UI for B%d\n",
+                dqs_i));
+        }
+
+        mcSHOW_DBG_MSG(("DQS%d Final RODTEN: (%2d, %2d)\n",
+            dqs_i, reg_mck_rodt[dqs_i], reg_ui_rodt[dqs_i]));
+        mcSHOW_DBG_MSG(("DQS%d Final RODTEN_P1: (%2d, %2d)\n",
+            dqs_i, reg_mck_rodt_p1[dqs_i], reg_ui_rodt_p1[dqs_i]));
+    }
+#endif
+
+    /* Set DQSIEN delay in MCK and UI */
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
+        P_Fld(best_win->best_dqsien_dly_mck[0],
+        SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+        P_Fld(best_win->best_dqsien_dly_ui[0],
+        SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+        P_Fld(best_win->best_dqsien_dly_mck_p1[0],
+        SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) |
+        P_Fld(best_win->best_dqsien_dly_ui_p1[0],
+        SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
+        P_Fld(best_win->best_dqsien_dly_mck[1],
+        SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+        P_Fld(best_win->best_dqsien_dly_ui[1],
+        SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+        P_Fld(best_win->best_dqsien_dly_mck_p1[1],
+        SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) |
+        P_Fld(best_win->best_dqsien_dly_ui_p1[1],
+        SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1));
+
+#if GATING_RODT_LATANCY_EN
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY),
+        P_Fld(reg_mck_rodt[0],
+        SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+        P_Fld(reg_ui_rodt[0],
+        SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+        P_Fld(reg_mck_rodt_p1[0],
+        SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) |
+        P_Fld(reg_ui_rodt_p1[0],
+        SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY),
+        P_Fld(reg_mck_rodt[1],
+        SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+        P_Fld(reg_ui_rodt[1],
+        SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+        P_Fld(reg_mck_rodt_p1[1],
+        SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) |
+        P_Fld(reg_ui_rodt_p1[1],
+        SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1));
+#endif
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY),
+        best_win->best_dqsien_dly_pi[0],
+        SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY),
+        best_win->best_dqsien_dly_pi[1],
+        SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+
+}
+
+#if GATING_AUTO_K_SUPPORT
+/* By autoK: Set the result calibrated by HW to RG */
+static void rxdqs_gating_auto_xlate(DRAMC_CTX_T *p,
+    struct rxdqs_gating_best_win *best_win,
+    struct rxdqs_gating_cal *rxdqs_cal)
+{
+    u8 mck, ui, pi;
+    U8 mck_p1, ui_p1;
+    u8 mck2ui, freq_div;
+    U8 total_ui;
+#if GATING_RODT_LATANCY_EN
+    U8 mck_rodt, ui_rodt;
+    U8 mck_rodt_p1, ui_rodt_p1;
+#endif
+    U16 value;
+    u8 dqs_i;
+
+    /* Transfer HW unit to RG unit */
+    for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) {
+        mck = best_win->best_dqsien_dly_mck[dqs_i];
+        ui = best_win->best_dqsien_dly_ui[dqs_i];
+        pi = best_win->best_dqsien_dly_pi[dqs_i];
+        mck2ui = rxdqs_cal->dqsien_ui_per_mck;
+        freq_div = rxdqs_cal->dqsien_freq_div;
+
+        if (vGet_Div_Mode(p) == DIV16_MODE)
+            total_ui = (mck << 4) + ui; /* 1:16 mode */
+        else if (vGet_Div_Mode(p) == DIV8_MODE)
+            total_ui = (mck << 3) + ui; /* 1: 8 mode */
+        else
+            total_ui = (mck << 2) + ui; /* 1: 4 mode */
+
+        /* RG is always 1:16 mode */
+        mck = (total_ui >> 4);
+        ui = (total_ui & 0xf);
+
+        value = mck * mck2ui + ui; /* Total UI number */
+        mck_p1 = (value + freq_div) / mck2ui;
+        ui_p1 = (value + freq_div) % mck2ui;
+
+        mcSHOW_DBG_MSG(("[Gating][RG] DQS%d Final result: (%d, %d, %d)\n", dqs_i, mck, ui, pi));
+        mcSHOW_DBG_MSG(("[Gating][RG] DQS%d Final result P1: (%d, %d)\n", dqs_i, mck_p1, ui_p1));
+
+        best_win->best_dqsien_dly_mck[dqs_i] = mck;
+        best_win->best_dqsien_dly_ui[dqs_i] = ui;
+        best_win->best_dqsien_dly_pi[dqs_i] = pi;
+
+        best_win->best_dqsien_dly_mck_p1[dqs_i] = mck_p1;
+        best_win->best_dqsien_dly_ui_p1[dqs_i] = ui_p1;
+        best_win->best_dqsien_dly_pi_p1[dqs_i] = pi;
+    }
+}
+
+#define RXDQS_GATING_AUTO_CAL_STATUS_BYTE_OFFSET        0x40
+
+static DRAM_STATUS_T rxdqs_gating_auto_cal_status(DRAMC_CTX_T *p,
+    struct rxdqs_gating_auto_param *auto_param,
+    struct rxdqs_gating_best_win *best_win)
+{
+    U8 mck_center[DQS_BYTE_NUMBER], ui_center[DQS_BYTE_NUMBER], pi_center[DQS_BYTE_NUMBER];
+    U8 mck_left[DQS_BYTE_NUMBER], ui_left[DQS_BYTE_NUMBER], pi_left[DQS_BYTE_NUMBER];
+    U8 mck_right[DQS_BYTE_NUMBER], ui_right[DQS_BYTE_NUMBER], pi_right[DQS_BYTE_NUMBER];
+    U8 done[DQS_BYTE_NUMBER] = { 0 }, error[DQS_BYTE_NUMBER] = { 0 };
+    DRAM_STATUS_T ret;
+    U8 done_bytes, total_bytes;
+    U8 byte_ofst;
+    U8 dqs_i;
+    //U8 div_mode;
+
+    total_bytes = DQS_BYTE_NUMBER;
+    done_bytes = 0;
+    ret = DRAM_OK;
+
+    while (done_bytes < total_bytes) {
+        for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) {
+            /* If already done, skip this byte */
+            if (done[dqs_i])
+                continue;
+
+            byte_ofst = dqs_i * RXDQS_GATING_AUTO_CAL_STATUS_BYTE_OFFSET;
+
+            done[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(
+                DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst),
+                DQSIEN_AUTOK_B0_RK0_STATUS0_AUTOK_DONE_B0_RK0);
+            error[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(
+                DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst),
+                DQSIEN_AUTOK_B0_RK0_STATUS0_AUTOK_ERR_B0_RK0);
+
+            /* If autok fail, done flag will not be asserted. */
+            if (done[dqs_i] || error[dqs_i]) {
+                /* Done and Pass */
+                if (error[dqs_i] == 0) {
+                    mck_center[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(
+                        DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst),
+                        DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C_MCK_B0_RK0);
+                    ui_center[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(
+                        DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst),
+                        DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C__UI_B0_RK0);
+                    pi_center[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(
+                        DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst),
+                        DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C__PI_B0_RK0);
+
+                    mck_left[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(
+                        DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst),
+                        DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L_MCK_B0_RK0);
+                    ui_left[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(
+                        DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst),
+                        DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L__UI_B0_RK0);
+                    pi_left[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(
+                        DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst),
+                        DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L__PI_B0_RK0);
+
+                    /* If early break mode not enabled, right boundary could be found */
+                    if (auto_param->early_break == DISABLE) {
+                        mck_right[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(
+                            DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst),
+                            DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R_MCK_B0_RK0);
+                        ui_right[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(
+                            DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst),
+                            DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R__UI_B0_RK0);
+                        pi_right[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(
+                            DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst),
+                            DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R__PI_B0_RK0);
+                    }
+                }
+                else
+                {
+                    /* If error occurred for this byte, it will be treated as a DONE condition */
+                    done[dqs_i] = 1;
+                }
+
+                if (auto_param->dbg_mode == ENABLE) {
+                    U32 dbg_reg_addr;
+                    U32 dbg_reg_idx;
+                    U32 dbg_reg_val;
+
+                    dbg_reg_addr = DRAMC_REG_ADDR(
+                        DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS0 + byte_ofst);
+                    for (dbg_reg_idx = 0;
+                        dbg_reg_idx < RXDQS_GATING_AUTO_DBG_REG_NUM;
+                        dbg_reg_idx++, dbg_reg_addr += 4) {
+                        dbg_reg_val = u4IO32Read4B(dbg_reg_addr);
+
+                        mcSHOW_ERR_MSG(("B%d Gating AUTOK DBG Status-%d: [0x%08x]\n",
+                            dqs_i, dbg_reg_idx, dbg_reg_val));
+                    }
+                }
+            }
+            else
+            {
+                mcSHOW_ERR_MSG(("B%d Gating AUTOK didn't be done\n", dqs_i));
+            }
+            done_bytes++;
+        }
+
+        mcDELAY_MS(1);
+    }
+
+    /* Log it */
+    for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) {
+        mcSHOW_DBG_MSG(("[Gating][%s] AUTOK of CH-%d, Rk-%d, Byte-%d:\n",
+            error[dqs_i]? "Fail" : "Pass", p->channel, p->rank, dqs_i));
+
+        if (done[dqs_i]) {
+            if (error[dqs_i] == 0) {
+                mcSHOW_DBG_MSG(("\tcenter(%2d, %2d, %2d)\n",
+                            mck_center[dqs_i], ui_center[dqs_i], pi_center[dqs_i]));
+                mcSHOW_DBG_MSG(("\tleft(%2d, %2d, %2d)\n",
+                            mck_left[dqs_i], ui_left[dqs_i], pi_left[dqs_i]));
+
+                if (auto_param->early_break == DISABLE) {
+                    mcSHOW_DBG_MSG(("\tright(%2d, %2d, %2d)\n",
+                                mck_right[dqs_i], ui_right[dqs_i], pi_right[dqs_i]));
+                }
+            }
+            if (error[dqs_i]) {
+                ret = DRAM_FAIL;
+            } else {
+                /* If passed, shall set the result to RG */
+                best_win->best_dqsien_dly_mck[dqs_i] = mck_center[dqs_i];
+                best_win->best_dqsien_dly_ui[dqs_i] = ui_center[dqs_i];
+                best_win->best_dqsien_dly_pi[dqs_i] = pi_center[dqs_i];
+            }
+        }
+    }
+
+    rxdqs_gating_auto_cal_stop(p);
+
+    return ret;
+}
+
+static DRAM_STATUS_T dramc_rx_dqs_gating_auto_cal(DRAMC_CTX_T *p)
+{
+    struct rxdqs_gating_auto_param auto_param;
+    struct rxdqs_gating_best_win rxdqs_best_win;
+    struct rxdqs_gating_cal rxdqs_cal;
+    DRAM_STATUS_T ret;
+    U8 start_ui, end_ui;
+    U8 mck2ui_hw; //mck2ui_rg, freq_div
+
+    U32 reg_backup_address[ ] = {
+        (DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)),
+        (DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4)),
+        (DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR))
+    };
+
+    DramcBackupRegisters(p, reg_backup_address,
+        sizeof (reg_backup_address) / sizeof (U32));
+
+    ret = DRAM_OK;
+
+    memset((void *)&auto_param, 0, sizeof auto_param);
+    memset((void *)&rxdqs_best_win, 0, sizeof rxdqs_best_win);
+    memset((void *)&rxdqs_cal, 0, sizeof rxdqs_cal);
+
+    if (vGet_Div_Mode(p) == DIV4_MODE)
+        rxdqs_cal.dqsien_freq_div = 2;
+    else
+        rxdqs_cal.dqsien_freq_div = 4;
+    rxdqs_cal.dqsien_ui_per_mck = DQS_GW_UI_PER_MCK;
+
+    if (!rxdqs_gating_bypass(p)) {
+        if (vGet_Div_Mode(p) == DIV16_MODE)
+            mck2ui_hw = 16;
+        else if (vGet_Div_Mode(p) == DIV8_MODE)
+            mck2ui_hw = 8;
+        else
+            mck2ui_hw = 4;
+
+#if ENABLE_GATING_AUTOK_WA
+        if (__wa__gating_autok_init_ui[p->rank] > 3)
+            start_ui = __wa__gating_autok_init_ui[p->rank] - 3;
+        else
+#endif
+        start_ui = u1GetGatingStartPos(p, AUTOK_ON);
+        end_ui = start_ui + 32;
+
+        /* Set auto calibration params */
+        auto_param.early_break = ENABLE;
+        auto_param.dbg_mode = ENABLE;
+        auto_param.init_mck = start_ui / mck2ui_hw;
+        auto_param.init_ui = start_ui % mck2ui_hw;
+        auto_param.end_mck = end_ui / mck2ui_hw;
+        auto_param.end_ui = end_ui % mck2ui_hw;
+        auto_param.pi_offset = 2; /* 2 ^ 2 = 4 */
+        auto_param.burst_len = RXDQS_BURST_LEN_8;
+
+
+#if FOR_DV_SIMULATION_USED == 1
+        cal_sv_rand_args_t *psra = get_psra();
+
+        if (psra) {
+            auto_param.early_break =
+                    psra->dqsien_autok_early_break_en? ENABLE: DISABLE;
+            auto_param.dbg_mode =
+                    psra->dqsien_autok_dbg_mode_en? ENABLE: DISABLE;
+            auto_param.pi_offset =
+                    psra->dqsien_autok_pi_offset? ENABLE: DISABLE;
+        }
+#endif /* FOR_DV_SIMULATION_USED == 1 */
+
+        rxdqs_gating_auto_cal_cfg(p, &auto_param);
+
+        /* Trigger HW auto k */
+        rxdqs_gating_auto_cal_trigger(p);
+
+        ret = rxdqs_gating_auto_cal_status(p, &auto_param, &rxdqs_best_win);
+        if (ret == DRAM_OK)
+            vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_OK);
+
+        rxdqs_gating_auto_xlate(p, &rxdqs_best_win, &rxdqs_cal);
+    }
+
+    rxdqs_gating_fastk_save_restore(p, &rxdqs_best_win, &rxdqs_cal);
+    rxdqs_gating_set_final_result(p, rxdqs_cal.dqsien_ui_per_mck, &rxdqs_best_win);
+
+    rxdqs_gating_misc_process(p, &rxdqs_best_win);
+    DramcRestoreRegisters(p, reg_backup_address,
+        sizeof (reg_backup_address) / sizeof (U32));
+
+    DramPhyReset(p);
+
+    return ret;
+}
+#endif
+
+static void rxdqs_gating_sw_cal_init(DRAMC_CTX_T *p, U8 use_enhanced_rdqs)
+{
+
+    /* Disable Per-Bank ref */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_CONF0),  0, SHU_CONF0_PBREFEN);
+
+    /*----------------
+     * From DV
+     *------------------------*/
+    if (p->frequency == 800) {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1),
+            0x1, MISC_STBCAL1_STBCNT_SW_RST);
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1),
+        0x1, MISC_STBCAL1_STBCNT_SHU_RST_EN);
+
+    /* SELPH_MODE = BY RANK */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2),
+        0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN);
+
+    if (p->dram_type == TYPE_LPDDR5) {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2),
+            0x1, MISC_STBCAL2_STB_PICG_EARLY_1T_EN);
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1),
+        0x1, MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD);
+
+    /* PICG_EARLY_EN */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6),
+        0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6),
+        0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2),
+        0x1, MISC_STBCAL2_STB_PICG_EARLY_1T_EN);
+
+    /* BURST_MODE */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
+        0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE);
+
+#if (__LP5_COMBO__)
+    if (is_lp5_family(p)) {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9),
+            0x1, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9),
+            0x1, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1);
+    } else
+#endif
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9),
+            0x1, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9),
+            0x1, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1);
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6),
+        0x2, B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6),
+        0x2, B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL),
+        0x1, MISC_STBCAL_DQSIENMODE);
+
+    /* New Rank Mode */
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2),
+        P_Fld(0x1, MISC_STBCAL2_STB_IG_XRANK_CG_RST) |
+        P_Fld(0x1, MISC_STBCAL2_STB_RST_BY_RANK) |
+        P_Fld(0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN));
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2),
+        0x1, B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2),
+        0x1, B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1);
+
+    //DramcHWGatingOnOff(p, 0);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1,
+        MISC_STBCAL2_STBENCMPEN);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0), 0,
+        RX_SET0_DM4TO1MODE);
+
+    /* enable &reset DQS counter */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1,
+        MISC_STBCAL2_DQSG_CNT_EN);
+    mcDELAY_US(4); /* wait 1 auto refresh after DQS Counter enable */
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1,
+        MISC_STBCAL2_DQSG_CNT_RST);
+    mcDELAY_US(1); /* delay 2T */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0,
+        MISC_STBCAL2_DQSG_CNT_RST);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1),
+        u1GetRank(p), MISC_CTRL1_R_DMSTBENCMP_RK_OPT);
+    DramcEngine2Init(p, 0x55000000,
+        0xaa000000 | GATING_PATTERN_NUM_LP5, TEST_AUDIO_PATTERN, 0, TE_NO_UI_SHIFT);
+
+    if (use_enhanced_rdqs) {
+        /* TBD. Enter Enhanced RDQS training mode */
+    }
+}
+
+static void rxdqs_gating_set_dqsien_dly(DRAMC_CTX_T *p, U8 dly_ui,
+    struct rxdqs_gating_cal *rxdqs_cal)
+{
+    //U32 value;
+    U32 reg_mck, reg_ui;
+    U32 reg_mck_p1, reg_ui_p1;
+#if GATING_RODT_LATANCY_EN
+    U32 reg_mck_rodt, reg_ui_rodt;
+    U32 reg_mck_rodt_p1, reg_ui_rodt_p1;
+#endif
+    U8 mck2ui = rxdqs_cal->dqsien_ui_per_mck;
+
+    rxdqs_cal->dqsien_dly_mck = dly_ui / rxdqs_cal->dqsien_ui_per_mck;
+    rxdqs_cal->dqsien_dly_ui = dly_ui % rxdqs_cal->dqsien_ui_per_mck;
+    rxdqs_cal->dqsien_dly_mck_p1 = (dly_ui + rxdqs_cal->dqsien_freq_div) / mck2ui;
+    rxdqs_cal->dqsien_dly_ui_p1 = (dly_ui + rxdqs_cal->dqsien_freq_div) % mck2ui;
+
+    reg_mck = rxdqs_cal->dqsien_dly_mck;
+    reg_ui = rxdqs_cal->dqsien_dly_ui;
+    reg_mck_p1 = rxdqs_cal->dqsien_dly_mck_p1;
+    reg_ui_p1 = rxdqs_cal->dqsien_dly_ui_p1;
+
+#if GATING_RODT_LATANCY_EN
+    value = (reg_mck * mck2ui) + reg_ui;
+
+    if (value >= 11) {
+        /* For RODT, MCK2UI is different from Gating */
+        U8 rodt_mck2ui = get_rodt_mck2ui(p);
+
+        value -= 11;
+        reg_mck_rodt = value / rodt_mck2ui;
+        reg_ui_rodt = value % rodt_mck2ui;
+
+        reg_mck_rodt_p1 = reg_mck_rodt;
+        reg_ui_rodt_p1 = reg_ui_rodt;
+    } else {
+
+        reg_mck_rodt = 0;
+        reg_ui_rodt = 0;
+        reg_mck_rodt_p1 = 4;
+        reg_ui_rodt_p1 = 4;
+        mcSHOW_DBG_MSG(("[Warning] RODT cannot be -11UI\n"));
+    }
+#endif
+
+    /* Set DQSIEN delay in MCK and UI */
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
+        P_Fld(reg_mck,
+        SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+        P_Fld(reg_ui,
+        SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+        P_Fld(reg_mck_p1,
+        SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) |
+        P_Fld(reg_ui_p1,
+        SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
+        P_Fld(reg_mck,
+        SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+        P_Fld(reg_ui,
+        SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+        P_Fld(reg_mck_p1,
+        SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) |
+        P_Fld(reg_ui_p1,
+        SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1));
+
+#if GATING_RODT_LATANCY_EN
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY),
+        P_Fld(reg_mck_rodt,
+        SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
+        P_Fld(reg_ui_rodt,
+        SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
+        P_Fld(reg_mck_rodt_p1,
+        SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) |
+        P_Fld(reg_ui_rodt_p1,
+        SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY),
+        P_Fld(reg_mck_rodt,
+        SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
+        P_Fld(reg_ui_rodt,
+        SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
+        P_Fld(reg_mck_rodt_p1,
+        SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) |
+        P_Fld(reg_ui_rodt_p1,
+        SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1));
+#endif
+}
+
+static void rxdqs_gating_sw_cal_trigger(DRAMC_CTX_T *p,
+    struct rxdqs_gating_cal *rxdqs_cal)
+{
+#if 0//ENABLE_DDR800_OPEN_LOOP_MODE_OPTION -> No 0.5UI after A60868
+    if (u1IsPhaseMode(p) == TRUE) {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0),
+            rxdqs_cal->dqsien_dly_pi >> 4, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0),
+            rxdqs_cal->dqsien_dly_pi >> 4, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1);
+    } else
+#endif
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY),
+            rxdqs_cal->dqsien_dly_pi, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY),
+            rxdqs_cal->dqsien_dly_pi, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+    }
+    DramPhyReset(p);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1,
+        MISC_STBCAL2_DQSG_CNT_RST);
+    mcDELAY_US(1);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0,
+        MISC_STBCAL2_DQSG_CNT_RST);
+
+    /* enable TE2, audio pattern */
+    DramcEngine2Run(p, TE_OP_READ_CHECK, TEST_AUDIO_PATTERN);
+}
+
+static void rxdqs_gating_get_leadlag(DRAMC_CTX_T *p,
+    struct rxdqs_gating_trans *rxdqs_trans,
+    struct rxdqs_gating_cal *rxdqs_cal)
+{
+    U8 dqs_i;
+    U8 debounce_thrd_PI = 16;
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) {
+        if (dqs_i == 0) {
+            rxdqs_trans->dqs_lead[0] = u4IO32ReadFldAlign(
+                DRAMC_REG_ADDR(DDRPHY_REG_MISC_PHY_RGS_STBEN_B0),
+                MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LEAD_B0);
+            rxdqs_trans->dqs_lag[0] = u4IO32ReadFldAlign(
+                DRAMC_REG_ADDR(DDRPHY_REG_MISC_PHY_RGS_STBEN_B0),
+                MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LAG_B0);
+        } else {
+            if (isLP4_DSC){
+                rxdqs_trans->dqs_lead[1] = u4IO32ReadFldAlign(
+                    DRAMC_REG_ADDR(DDRPHY_REG_MISC_PHY_RGS_STBEN_CMD),
+                    MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LEAD);
+                rxdqs_trans->dqs_lag[1] = u4IO32ReadFldAlign(
+                    DRAMC_REG_ADDR(DDRPHY_REG_MISC_PHY_RGS_STBEN_CMD),
+                    MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LAG);
+            } else {
+                rxdqs_trans->dqs_lead[1] = u4IO32ReadFldAlign(
+                    DRAMC_REG_ADDR(DDRPHY_REG_MISC_PHY_RGS_STBEN_B1),
+                    MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LEAD_B1);
+                rxdqs_trans->dqs_lag[1] = u4IO32ReadFldAlign(
+                    DRAMC_REG_ADDR(DDRPHY_REG_MISC_PHY_RGS_STBEN_B1),
+                    MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LAG_B1);
+            }
+
+        }
+
+        if ((rxdqs_trans->dqs_lead[dqs_i] == 1) &&
+            (rxdqs_trans->dqs_lag[dqs_i] == 1)) {
+            rxdqs_trans->dqs_high[dqs_i]++;
+            rxdqs_trans->dqs_transition[dqs_i] = 1;
+
+            /* Record the latest value that causes (lead, lag) = (1, 1) */
+            rxdqs_trans->dqsien_dly_mck_leadlag[dqs_i] =
+                rxdqs_cal->dqsien_dly_mck;
+            rxdqs_trans->dqsien_dly_ui_leadlag[dqs_i] =
+                rxdqs_cal->dqsien_dly_ui;
+            rxdqs_trans->dqsien_dly_pi_leadlag[dqs_i] =
+                rxdqs_cal->dqsien_dly_pi;
+        } else if ((rxdqs_trans->dqs_high[dqs_i] *
+            rxdqs_cal->dqsien_pi_adj_step) >= debounce_thrd_PI) {
+            /* Consecutive 16 PI DQS high for de-glitch */
+            if (((rxdqs_trans->dqs_lead[dqs_i] == 1) &&
+                (rxdqs_trans->dqs_lag[dqs_i] == 0)) ||
+                ((rxdqs_trans->dqs_lead[dqs_i] == 0) &&
+                (rxdqs_trans->dqs_lag[dqs_i] == 1))) {
+                rxdqs_trans->dqs_transition[dqs_i]++;
+            }
+        #if GATING_LEADLAG_LOW_LEVEL_CHECK
+            else if ((rxdqs_trans->dqs_lead[dqs_i] == 0) &&
+                (rxdqs_trans->dqs_lag[dqs_i] == 0)){
+                if ((rxdqs_trans->dqs_low[dqs_i] *
+                     rxdqs_cal->dqsien_pi_adj_step) >= debounce_thrd_PI) {
+                /* (lead, lag) = (0, 0), transition done */
+                rxdqs_trans->dqs_transitioned[dqs_i] = 1;
+                    }
+                rxdqs_trans->dqs_low[dqs_i]++;
+            }else {
+                  rxdqs_trans->dqs_high[dqs_i] = 0;
+                  rxdqs_trans->dqs_low[dqs_i] = 0;
+                }
+        #else
+        else {
+            /* (lead, lag) = (0, 0), transition done */
+            rxdqs_trans->dqs_transitioned[dqs_i] = 1;
+        }
+        #endif
+        } else {
+            /* Lead/lag = (1, 1) number is too few. Reset dqs_high */
+            rxdqs_trans->dqs_high[dqs_i] = 0;
+        #if GATING_LEADLAG_LOW_LEVEL_CHECK
+            rxdqs_trans->dqs_low[dqs_i] = 0;
+        #endif
+        }
+    }
+}
+
+static U8 rxdqs_gating_sw_cal(DRAMC_CTX_T *p,
+    struct rxdqs_gating_trans *rxdqs_trans,
+    struct rxdqs_gating_cal *rxdqs_cal, U8 *pass_byte_count,
+    struct rxdqs_gating_best_win *best_win, U8 dly_ui, U8 dly_ui_end)
+{
+    U8 gating_error[DQS_BYTE_NUMBER];
+    U32 debug_cnt[DQS_BYTE_NUMBER];
+    U32 debug_pass_cnt;
+    U8 dqs_i;
+    //U8 dqs_result_r, dqs_result_f;
+    //U16 debug_cnt_per_byte;
+    U8 passed_bytes;
+
+    memset(debug_cnt, 0, sizeof(debug_cnt));
+    passed_bytes = *pass_byte_count;
+
+    rxdqs_gating_sw_cal_trigger(p, rxdqs_cal);
+
+    if (p->rank == RANK_0) {
+        gating_error[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(
+            DDRPHY_REG_MISC_STBERR_ALL),
+            MISC_STBERR_ALL_GATING_ERROR_B0_RK0);
+        gating_error[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(
+            DDRPHY_REG_MISC_STBERR_ALL),
+            MISC_STBERR_ALL_GATING_ERROR_B1_RK0);
+    } else {
+        gating_error[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(
+            DDRPHY_REG_MISC_STBERR_ALL),
+            MISC_STBERR_ALL_GATING_ERROR_B0_RK1);
+        gating_error[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(
+            DDRPHY_REG_MISC_STBERR_ALL),
+            MISC_STBERR_ALL_GATING_ERROR_B1_RK1);
+    }
+
+    /* read DQS counter
+     * Note: DQS counter is no longer used as pass condition. Here
+     * Read it and log it is just as debug method. Any way, DQS counter
+     * can still be used as a clue: it will be n*0x23 when gating is correct
+     */
+    debug_cnt[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CAL_DQSG_CNT_B0));
+    debug_cnt[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CAL_DQSG_CNT_B1));
+
+    /* read (lead, lag) */
+    rxdqs_gating_get_leadlag(p, rxdqs_trans, rxdqs_cal);
+
+    mcSHOW_DBG_MSG2(("%2d %2d %2d | ",
+        rxdqs_cal->dqsien_dly_mck, rxdqs_cal->dqsien_dly_ui,
+        rxdqs_cal->dqsien_dly_pi));
+    mcSHOW_DBG_MSG2(("B1->B0 | %x %x | %x %x | (%d %d) (%d %d)\n",
+        debug_cnt[1], debug_cnt[0],
+        gating_error[1], gating_error[0],
+        rxdqs_trans->dqs_lead[1], rxdqs_trans->dqs_lag[1],
+        rxdqs_trans->dqs_lead[0], rxdqs_trans->dqs_lag[0]));
+
+#if (__LP5_COMBO__)
+    if((is_lp5_family(p)) && (vGet_Div_Mode(p) == DIV16_MODE))
+        debug_pass_cnt = (GATING_GOLDEND_DQSCNT_LP5 >> 1);
+    else
+#endif
+        debug_pass_cnt = GATING_GOLDEND_DQSCNT_LP5;
+
+    /* Decide the window center */
+    for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) {
+        if (passed_bytes & (1 << dqs_i))
+            continue;
+
+        if ((gating_error[dqs_i] == 0) && (debug_cnt[dqs_i] == debug_pass_cnt)) {
+            /* Calcuate DQSIEN position */
+            if (rxdqs_trans->dqs_transitioned[dqs_i] != 0) {
+                U8 pass_count = rxdqs_trans->dqs_transition[dqs_i];
+                U8 offset = (pass_count * rxdqs_cal->dqsien_pi_adj_step) / 2;
+                U8 mck2ui, ui2pi, freq_div;
+                U8 tmp;
+
+                mck2ui = rxdqs_cal->dqsien_ui_per_mck;
+                ui2pi = rxdqs_cal->dqsien_pi_per_ui;
+                freq_div = rxdqs_cal->dqsien_freq_div;
+
+                /* PI */
+                tmp = rxdqs_trans->dqsien_dly_pi_leadlag[dqs_i] + offset;
+                best_win->best_dqsien_dly_pi[dqs_i] = tmp % ui2pi;
+                best_win->best_dqsien_dly_pi_p1[dqs_i] =
+                    best_win->best_dqsien_dly_pi[dqs_i];
+
+                /* UI & MCK - P0 */
+                tmp /= ui2pi;
+                tmp = rxdqs_trans->dqsien_dly_ui_leadlag[dqs_i] + tmp;
+                best_win->best_dqsien_dly_ui[dqs_i] = tmp % mck2ui;
+                best_win->best_dqsien_dly_mck[dqs_i] =
+                    rxdqs_trans->dqsien_dly_mck_leadlag[dqs_i] + (tmp / mck2ui);
+
+                /* UI & MCK - P1 */
+                best_win->best_dqsien_dly_ui_p1[dqs_i] =
+                    best_win->best_dqsien_dly_mck[dqs_i] * mck2ui +
+                    best_win->best_dqsien_dly_ui[dqs_i] + freq_div; /* Total UI for Phase1 */
+                /*mcSHOW_DBG_MSG(("Total UI for P1: %d, mck2ui %d\n",
+                    best_win->best_dqsien_dly_mck_p1[dqs_i], mck2ui));*/
+                best_win->best_dqsien_dly_mck_p1[dqs_i] =
+                    best_win->best_dqsien_dly_ui_p1[dqs_i] / mck2ui;
+                best_win->best_dqsien_dly_ui_p1[dqs_i] =
+                    best_win->best_dqsien_dly_ui_p1[dqs_i] % mck2ui;
+
+                /*mcSHOW_DBG_MSG(("best dqsien dly found for B%d: "
+                    "(%2d, %2d, %2d)\n", dqs_i,
+                    best_win->best_dqsien_dly_mck[dqs_i],
+                    best_win->best_dqsien_dly_ui[dqs_i],
+                    best_win->best_dqsien_dly_pi[dqs_i]));*/
+
+                passed_bytes |= 1 << dqs_i;
+
+                if ((p->data_width == DATA_WIDTH_16BIT) &&
+                    (passed_bytes == 0x3)) {
+                    dly_ui = dly_ui_end;
+                    break;
+                }
+            }
+        } else {
+            /* Clear lead lag info in case lead/lag flag toggled
+             * while gating counter & gating error still incorrect
+             */
+            rxdqs_trans->dqs_high[dqs_i] = 0;
+            rxdqs_trans->dqs_transition[dqs_i] = 0;
+            rxdqs_trans->dqs_transitioned[dqs_i] = 0;
+        }
+    }
+
+    *pass_byte_count = passed_bytes;
+    return dly_ui;
+}
+
+static DRAM_STATUS_T dramc_rx_dqs_gating_sw_cal(DRAMC_CTX_T *p,
+    U8 use_enhance_rdqs)
+{
+    struct rxdqs_gating_cal rxdqs_cal;
+    struct rxdqs_gating_trans rxdqs_trans;
+    struct rxdqs_gating_best_win rxdqs_best_win;
+    U8 dly_ui, dly_ui_start, dly_ui_end;
+    U8 pi_per_ui, ui_per_mck, freq_div;
+    U8 pass_byte_count;
+    //U32 value;
+    //U8 dqs_i;
+    U8 u1GatingErrorFlag=0;
+
+    if (p == NULL) {
+        mcSHOW_ERR_MSG(("[Error] Context NULL\n"));
+        return DRAM_FAIL;
+    }
+
+    memset(&rxdqs_cal, 0, sizeof(struct rxdqs_gating_cal));
+    memset(&rxdqs_trans, 0, sizeof(struct rxdqs_gating_trans));
+    memset(&rxdqs_best_win, 0, sizeof(struct rxdqs_gating_best_win));
+
+    pi_per_ui = DQS_GW_PI_PER_UI; /* 1 UI = ? PI. Sams as CBT, differ according to data rate?? */
+    ui_per_mck = DQS_GW_UI_PER_MCK; /* 1 mck = ? UI. Decided by (Tmck/Tck) * (Tck/Twck) */
+    if (vGet_Div_Mode(p) == DIV4_MODE)
+        freq_div = 2;
+    else
+        freq_div = 4;
+
+    if (u1IsPhaseMode(p))
+        rxdqs_cal.dqsien_pi_adj_step = (0x1 << 4);
+    else
+        rxdqs_cal.dqsien_pi_adj_step = DQS_GW_FINE_STEP;
+
+#if ENABLE_GATING_AUTOK_WA
+    if (__wa__gating_swk_for_autok)
+        rxdqs_cal.dqsien_pi_adj_step = pi_per_ui;
+#endif
+    rxdqs_cal.dqsien_pi_per_ui = pi_per_ui;
+    rxdqs_cal.dqsien_ui_per_mck = ui_per_mck;
+    rxdqs_cal.dqsien_freq_div = freq_div;
+
+    U32 reg_backup_address[ ] = {
+        (DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2)),
+    };
+
+    /* Register backup */
+    DramcBackupRegisters(p, reg_backup_address,
+        sizeof (reg_backup_address) / sizeof (U32));
+
+    if (!rxdqs_gating_bypass(p)) {
+        rxdqs_gating_sw_cal_init(p, use_enhance_rdqs);
+
+#if 1
+        #if (LP5_DDR4266_RDBI_WORKAROUND)
+        if((is_lp5_family(p)) && (p->frequency == 2133))
+            dly_ui_start = 15;
+        else if((is_lp5_family(p)) && (p->frequency == 2750))
+            dly_ui_start = 12;
+        else
+            dly_ui_start = u1GetGatingStartPos(p, AUTOK_OFF);//7; //12;ly_ui_start + 32;
+        #else
+        #if __LP5_COMBO__
+            if((is_lp5_family(p)) && ((p->frequency == 2133) || (p->frequency == 2750)))
+                dly_ui_start = 5;
+            else
+        #endif
+                dly_ui_start = u1GetGatingStartPos(p, AUTOK_OFF);//7; //12;ly_ui_start + 32;
+        #endif
+
+        dly_ui_end = dly_ui_start+ 32;
+        pass_byte_count = 0;
+#else
+        #if __LP5_COMBO__
+        if (is_lp5_family(p))
+        {
+            if (p->frequency == 1600)
+                dly_ui_start = 7; //12;
+            else
+                dly_ui_start = 8; //12;
+
+            dly_ui_end = dly_ui_start + 32;
+            pass_byte_count = 0;
+        }
+        else
+        #endif
+        {
+             dly_ui_start = 9; //12; Eddie change to 9 for Hynix Normal Mode
+             if(p->freq_sel==LP4_DDR4266)
+             {
+                dly_ui_start = 16;
+             }
+             dly_ui_end = dly_ui_start + 32;
+             pass_byte_count = 0;
+        }
+#endif
+
+
+        for (dly_ui = dly_ui_start; dly_ui < dly_ui_end;
+            dly_ui += DQS_GW_COARSE_STEP) {
+            rxdqs_gating_set_dqsien_dly(p, dly_ui, &rxdqs_cal);
+
+            for (rxdqs_cal.dqsien_dly_pi = 0; rxdqs_cal.dqsien_dly_pi <
+                pi_per_ui; rxdqs_cal.dqsien_dly_pi +=
+                rxdqs_cal.dqsien_pi_adj_step) {
+                dly_ui = rxdqs_gating_sw_cal(p, &rxdqs_trans, &rxdqs_cal,
+                    &pass_byte_count, &rxdqs_best_win, dly_ui, dly_ui_end);
+
+                if (dly_ui == dly_ui_end)
+                    break;
+            }
+        }
+
+        DramcEngine2End(p);
+
+        //check if there is no pass taps for each DQS
+        if (pass_byte_count == 0x3)//byte0 pass: pass_byte_count bit0=1, byte1 pass: pass_byte_count bit1=1 .LP4/LP5 pass=0x3(2 bytes). need modification for LP3 pass=0xf(4 bytes)
+        {
+            u1GatingErrorFlag=0;
+            vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_OK);
+        }
+        else
+            {
+                u1GatingErrorFlag=1;
+            mcSHOW_ERR_MSG(("error, no all pass taps in DQS!,pass_byte_count=%d\n", pass_byte_count));
+        }
+
+
+#if (ENABLE_GATING_AUTOK_WA)
+        if (!u1GatingErrorFlag && __wa__gating_swk_for_autok) {
+            U8 ui[DQS_BYTE_NUMBER], ui_min = 0xff;
+            U8 dqs_i;
+            for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++){
+                ui[dqs_i] = rxdqs_best_win.best_dqsien_dly_mck[dqs_i] * ui_per_mck +
+                rxdqs_best_win.best_dqsien_dly_ui[dqs_i];
+
+                if (ui[dqs_i] < ui_min)
+                    ui_min = ui[dqs_i];
+            }
+            __wa__gating_autok_init_ui[p->rank] = ui_min;
+
+            DramcRestoreRegisters(p, reg_backup_address,
+                sizeof (reg_backup_address) / sizeof (U32));
+            return DRAM_OK;
+        }
+#endif
+    }
+
+    rxdqs_gating_fastk_save_restore(p, &rxdqs_best_win, &rxdqs_cal);
+    rxdqs_gating_misc_process(p, &rxdqs_best_win);
+
+    mcSHOW_DBG_MSG4(("[Gating] SW calibration Done\n"));
+
+    /* Set MCK & UI */
+    rxdqs_gating_set_final_result(p, ui_per_mck, &rxdqs_best_win);
+
+    DramcRestoreRegisters(p, reg_backup_address,
+        sizeof (reg_backup_address) / sizeof (U32));
+
+    DramPhyReset(p);
+
+    return DRAM_OK;
+}
+
+/* LPDDR5 Rx DQS Gating */
+DRAM_STATUS_T dramc_rx_dqs_gating_cal(DRAMC_CTX_T *p,
+        u8 autok, U8 use_enhanced_rdqs)
+{
+    DRAM_STATUS_T ret;
+
+    vPrintCalibrationBasicInfo(p);
+
+    mcSHOW_DBG_MSG(("[DramcGating] \n"));
+
+#if ENABLE_GATING_AUTOK_WA
+     if (autok) {
+         __wa__gating_swk_for_autok = 1;
+         dramc_rx_dqs_gating_sw_cal(p, use_enhanced_rdqs);
+         __wa__gating_swk_for_autok = 0;
+     }
+#endif
+
+     // default set FAIL
+    vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_FAIL);
+
+    /* Try HW auto calibration first. If failed,
+     * will try SW mode.
+     */
+#if GATING_AUTO_K_SUPPORT
+    if (autok) {
+#if ENABLE_GATING_AUTOK_WA
+        if (rxdqs_gating_bypass(p)) /* Already done by SWK */
+            return DRAM_OK;
+#endif
+
+        ret = dramc_rx_dqs_gating_auto_cal(p);
+        if (ret == DRAM_OK) {
+            return DRAM_OK;
+        }
+
+        mcSHOW_ERR_MSG(("[Error] Gating auto calibration fail!!\n"));
+    }
+#endif
+
+    mcSHOW_DBG_MSG(("SW mode calibration\n"));
+
+    return dramc_rx_dqs_gating_sw_cal(p, use_enhanced_rdqs);
+}
+
+///TODO: wait for porting +++
+#if GATING_ADJUST_TXDLY_FOR_TRACKING
+void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p)
+{
+    U8 dqs_i; //u1RankRxDVS = 0
+    U8 u1RankIdx, u1RankMax; //u1RankBak
+    S8 s1ChangeDQSINCTL;
+#if XRTRTR_NEW_CROSS_RK_MODE
+    U16 u2PHSINCTL = 0;
+    U32 u4Rank_Sel_MCK_P0[2], u4Rank_Sel_MCK_P1[2], u4RANKINCTL_STB;
+#endif
+#if RDSEL_TRACKING_EN
+    //U32 u4PI_value[2] = {0};
+#endif
+    U32 backup_rank;
+    U32 u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R, reg_TX_dly_DQSgated_min = 0;
+    //U32 u4ReadRODT, u4ReadTXDLY[RANK_MAX][DQS_BYTE_NUMBER], u4ReadTXDLY_P1[RANK_MAX][DQS_BYTE_NUMBER]
+    U8 mck2ui_shift;
+
+    backup_rank = u1GetRank(p);
+
+#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
+    if (vGet_Div_Mode(p) == DIV8_MODE)
+    {
+        // wei-jen: DQSgated_min should be 2 when freq >= 1333, 1 when freq < 1333
+        if (p->frequency >= 1333)
+        {
+            reg_TX_dly_DQSgated_min = 2;
+        }
+        else
+        {
+            reg_TX_dly_DQSgated_min = 1;
+        }
+    }
+    else // for LPDDR4 1:4 mode
+    {
+        //tg: DDR800/400: reg_TX_dly_DQSgated (min) =1
+        reg_TX_dly_DQSgated_min = 1;
+    }
+#else
+    // wei-jen: DQSgated_min should be 3 when freq >= 1333, 2 when freq < 1333
+    if (p->frequency >= 1333)
+    {
+        reg_TX_dly_DQSgated_min = 3;
+    }
+    else
+    {
+        reg_TX_dly_DQSgated_min = 2;
+    }
+#endif
+
+    //Sylv_ia MP setting is switched to new mode, so RANKRXDVS can be set as 0 (review by HJ Huang)
+#if 0
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DQ7), u1RankRxDVS, SHU_B0_DQ7_R_DMRANKRXDVS_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B1_DQ7), u1RankRxDVS, SHU_B1_DQ7_R_DMRANKRXDVS_B1);
+#endif
+    // === End of DVS setting =====
+
+    s1ChangeDQSINCTL = reg_TX_dly_DQSgated_min - u1TXDLY_Cal_min;
+
+    //mcDUMP_REG_MSG(("\n[dumpRG] RxdqsGatingPostProcess\n"));
+
+    mcSHOW_DBG_MSG(("[RxdqsGatingPostProcess] freq %d\n"
+                    "ChangeDQSINCTL %d, reg_TX_dly_DQSgated_min %d, u1TXDLY_Cal_min %d\n",
+                        p->frequency,
+                        s1ChangeDQSINCTL, reg_TX_dly_DQSgated_min, u1TXDLY_Cal_min));
+    /*mcDUMP_REG_MSG(("[RxdqsGatingPostProcess] freq %d\n"
+                       "ChangeDQSINCTL %d, reg_TX_dly_DQSgated_min %d, u1TXDLY_Cal_min %d\n",
+                        p->frequency,
+                        s1ChangeDQSINCTL, reg_TX_dly_DQSgated_min, u1TXDLY_Cal_min));*/
+
+    if (vGet_Div_Mode(p) == DIV16_MODE)
+        mck2ui_shift = 4;
+    else if (vGet_Div_Mode(p) == DIV8_MODE)
+        mck2ui_shift = 3;
+    else
+        mck2ui_shift = 2;
+
+    if (s1ChangeDQSINCTL != 0)  // need to change DQSINCTL and TXDLY of each byte
+    {
+        u1TXDLY_Cal_min += s1ChangeDQSINCTL;
+        u1TXDLY_Cal_max += s1ChangeDQSINCTL;
+
+        if (p->support_rank_num == RANK_DUAL)
+            u1RankMax = RANK_MAX;
+        else
+             u1RankMax = RANK_1;
+
+        for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++)
+        {
+            mcSHOW_DBG_MSG2(("Rank: %d\n", u1RankIdx));
+            //mcDUMP_REG_MSG(("Rank: %d\n", u1RankIdx));
+
+            for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++)
+            {
+#if 1
+                U8 total_ui, total_ui_P1;
+                total_ui = (ucbest_coarse_mck_backup[u1RankIdx][dqs_i] << 4) + ucbest_coarse_ui_backup[u1RankIdx][dqs_i];
+                total_ui_P1 = (ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] << 4) + ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i];
+
+                total_ui += (s1ChangeDQSINCTL << mck2ui_shift);
+                total_ui_P1 += (s1ChangeDQSINCTL << mck2ui_shift);
+
+                ucbest_coarse_mck_backup[u1RankIdx][dqs_i] = (total_ui >> 4);
+                ucbest_coarse_ui_backup[u1RankIdx][dqs_i] = total_ui & 0xf;
+
+                ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] = (total_ui_P1 >> 4);
+                ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i] = total_ui_P1 & 0xf;
+#else
+                if (vGet_Div_Mode(p) == DIV8_MODE)
+                {
+                    u4ReadTXDLY[u1RankIdx][dqs_i] = ucbest_coarse_mck_backup[u1RankIdx][dqs_i];
+                    u4ReadTXDLY_P1[u1RankIdx][dqs_i] = ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i];
+
+                    u4ReadTXDLY[u1RankIdx][dqs_i] += s1ChangeDQSINCTL;
+                    u4ReadTXDLY_P1[u1RankIdx][dqs_i] += s1ChangeDQSINCTL;
+
+                    ucbest_coarse_mck_backup[u1RankIdx][dqs_i] = u4ReadTXDLY[u1RankIdx][dqs_i];
+                    ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] = u4ReadTXDLY_P1[u1RankIdx][dqs_i];
+                }
+                else // LP3 or LP4 1:4 mode
+                {
+                    u4ReadTXDLY[u1RankIdx][dqs_i] = ((ucbest_coarse_mck_backup[u1RankIdx][dqs_i] << 1) + ((ucbest_coarse_ui_backup[u1RankIdx][dqs_i] >> 2) & 0x1));
+                    u4ReadTXDLY_P1[u1RankIdx][dqs_i] = ((ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] << 1) + ((ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i] >> 2) & 0x1));
+
+                    u4ReadTXDLY[u1RankIdx][dqs_i] += s1ChangeDQSINCTL;
+                    u4ReadTXDLY_P1[u1RankIdx][dqs_i] += s1ChangeDQSINCTL;
+
+                    ucbest_coarse_mck_backup[u1RankIdx][dqs_i] = (u4ReadTXDLY[u1RankIdx][dqs_i] >> 1);
+                    ucbest_coarse_ui_backup[u1RankIdx][dqs_i] = ((u4ReadTXDLY[u1RankIdx][dqs_i] & 0x1) << 2) + (ucbest_coarse_ui_backup[u1RankIdx][dqs_i] & 0x3);
+
+                    ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] = (u4ReadTXDLY_P1[u1RankIdx][dqs_i] >> 1);
+                    ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i] = ((u4ReadTXDLY_P1[u1RankIdx][dqs_i] & 0x1) << 2) + (ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i] & 0x3);
+                }
+#endif
+                mcSHOW_DBG_MSG(("PostProcess best DQS%d dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_backup[u1RankIdx][dqs_i]));
+                //mcDUMP_REG_MSG(("PostProcess best DQS%d dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_backup[u1RankIdx][dqs_i]));
+#ifdef FOR_HQA_REPORT_USED
+                HQA_Log_Message_for_Report(p, p->channel, u1RankIdx, HQA_REPORT_FORMAT0,
+                    "Gating_Center_", "2T", dqs_i, ucbest_coarse_mck_backup[u1RankIdx][dqs_i], NULL);
+                HQA_Log_Message_for_Report(p, p->channel, u1RankIdx, HQA_REPORT_FORMAT0,
+                    "Gating_Center_", "05T", dqs_i, ucbest_coarse_ui_backup[u1RankIdx][dqs_i], NULL);
+#endif
+            }
+            for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++)
+            {
+                mcSHOW_DBG_MSG(("PostProcess best DQS%d P1 dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i]));
+                //mcDUMP_REG_MSG(("PostProcess best DQS%d P1 dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i]));
+            }
+        }
+
+        for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++)
+        {
+            vSetRank(p, u1RankIdx);
+            // 4T or 2T coarse tune
+            /* Set DQSIEN delay in MCK and UI */
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
+                P_Fld(ucbest_coarse_mck_backup[u1RankIdx][0],
+                SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
+                P_Fld(ucbest_coarse_ui_backup[u1RankIdx][0],
+                SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
+                P_Fld(ucbest_coarse_mck_P1_backup[u1RankIdx][0],
+                SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) |
+                P_Fld(ucbest_coarse_ui_P1_backup[u1RankIdx][0],
+                SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0));
+
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
+                P_Fld(ucbest_coarse_mck_backup[u1RankIdx][1],
+                SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
+                P_Fld(ucbest_coarse_ui_backup[u1RankIdx][1],
+                SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
+                P_Fld(ucbest_coarse_mck_P1_backup[u1RankIdx][1],
+                SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) |
+                P_Fld(ucbest_coarse_ui_P1_backup[u1RankIdx][1],
+                SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1));
+        #if RDSEL_TRACKING_EN
+            if(p->frequency >= RDSEL_TRACKING_TH)
+            {
+                //Byte 0
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI),
+                    (ucbest_coarse_mck_backup[u1RankIdx][0] << 4) | (ucbest_coarse_ui_backup[u1RankIdx][0]),
+                    SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0);//UI
+                //Byte 1
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI),
+                    (ucbest_coarse_mck_backup[u1RankIdx][1] << 4) | (ucbest_coarse_ui_backup[u1RankIdx][1]),
+                    SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1);//UI
+            }
+        #endif
+        }
+    }
+    vSetRank(p, backup_rank);
+
+    u4ReadDQSINCTL = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL),
+        MISC_SHU_RK_DQSCTL_DQSINCTL);
+    //mcDUMP_REG_MSG(("u4ReadDQSINCTL=%d\n", u4ReadDQSINCTL));
+    u4ReadDQSINCTL -= s1ChangeDQSINCTL;
+
+    #if ENABLE_READ_DBI
+    if (p->DBI_R_onoff[p->dram_fsp])
+    {
+        u4ReadDQSINCTL++;
+        #if 0//cc mark for reg not found
+        u4ReadRODT = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), SHU_ODTCTRL_RODT);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), u4ReadRODT + 1, SHU_ODTCTRL_RODT); //update RODT value when READ_DBI is on
+        #endif
+    }
+    #endif
+
+#if XRTRTR_NEW_CROSS_RK_MODE
+        for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++)
+        {
+            if (ucbest_coarse_mck_backup[RANK_0][dqs_i] > ucbest_coarse_mck_backup[RANK_1][dqs_i])
+            {
+                u4Rank_Sel_MCK_P0[dqs_i] = (ucbest_coarse_mck_backup[RANK_0][dqs_i] > 0)? (ucbest_coarse_mck_backup[RANK_0][dqs_i] - 1): 0;
+                u4Rank_Sel_MCK_P1[dqs_i] = (ucbest_coarse_mck_P1_backup[RANK_0][dqs_i] > 0)? (ucbest_coarse_mck_P1_backup[RANK_0][dqs_i] - 1): 0;
+            }
+            else
+            {
+                u4Rank_Sel_MCK_P0[dqs_i] = (ucbest_coarse_mck_backup[RANK_1][dqs_i] > 0)? (ucbest_coarse_mck_backup[RANK_1][dqs_i] - 1): 0;
+                u4Rank_Sel_MCK_P1[dqs_i] = (ucbest_coarse_mck_P1_backup[RANK_1][dqs_i] > 0)? (ucbest_coarse_mck_P1_backup[RANK_1][dqs_i] - 1): 0;
+            }
+        }
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_RANK_SELPH_UI_DLY),
+            P_Fld(u4Rank_Sel_MCK_P0[0], SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B0) |
+            P_Fld(u4Rank_Sel_MCK_P1[0], SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B0));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_RANK_SELPH_UI_DLY),
+            P_Fld(u4Rank_Sel_MCK_P0[1], SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B1) |
+            P_Fld(u4Rank_Sel_MCK_P1[1], SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B1));
+
+        u4RANKINCTL_STB = (u4ReadDQSINCTL > 2)? (u4ReadDQSINCTL - 2): 0;
+        u2PHSINCTL = (u4ReadDQSINCTL == 0)? 0: (u4ReadDQSINCTL - 1);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), u4RANKINCTL_STB, MISC_SHU_RANKCTL_RANKINCTL_STB);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RANK_SEL_STB), u2PHSINCTL, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL);
+#endif
+
+#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
+    // Wei-Jen: RANKINCTL_RXDLY = RANKINCTL = RankINCTL_ROOT = u4ReadDQSINCTL-2, if XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY enable
+    // Wei-Jen: New algorithm : u4ReadDQSINCTL-2 >= 0
+    if (u4ReadDQSINCTL >= 2)
+    {
+        u4RankINCTL_ROOT = u4ReadDQSINCTL - 2;
+    }
+    else
+    {
+        u4RankINCTL_ROOT = 0;
+        mcSHOW_ERR_MSG(("u4RankINCTL_ROOT <2, Please check\n"));
+#if (__ETT__)
+        while (1);
+#endif
+    }
+#else
+    //Modify for corner IC failed at HQA test XTLV
+    if (u4ReadDQSINCTL >= 3)
+    {
+        u4RankINCTL_ROOT = u4ReadDQSINCTL - 3;
+    }
+    else
+    {
+        u4RankINCTL_ROOT = 0;
+        mcSHOW_ERR_MSG(("u4RankINCTL_ROOT <3, Risk for supporting 1066/RL8\n"));
+    }
+#endif
+
+    //DQSINCTL
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL),
+        u4ReadDQSINCTL, MISC_SHU_RK_DQSCTL_DQSINCTL);  //Rank0 DQSINCTL
+    vSetRank(p, RANK_1);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL),
+        u4ReadDQSINCTL, MISC_SHU_RK_DQSCTL_DQSINCTL);  //Rank1 DQSINCTL
+    vSetRank(p, backup_rank);
+
+    //No need to update RODT. If we update RODT, also need to update SELPH_ODTEN0_TXDLY
+    //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), u4ReadDQSINCTL, SHU_ODTCTRL_RODT);           //RODT = DQSINCTL
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL),
+        u4ReadDQSINCTL, MISC_SHU_RANKCTL_RANKINCTL_PHY);  //RANKINCTL_PHY = DQSINCTL
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL),
+        u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL);  //RANKINCTL= DQSINCTL -3
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL),
+        u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL_ROOT1);  //RANKINCTL_ROOT1= DQSINCTL -3
+
+#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL),
+        u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL_RXDLY);
+
+    u4XRTR2R = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ACTIM_XRT), SHU_ACTIM_XRT_XRTR2R);
+
+    mcSHOW_DBG_MSG2(("TX_dly_DQSgated check: min %d  max %d, ChangeDQSINCTL=%d\n", u1TXDLY_Cal_min, u1TXDLY_Cal_max, s1ChangeDQSINCTL));
+    mcSHOW_DBG_MSG2(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R));
+    //mcDUMP_REG_MSG(("TX_dly_DQSgated check: min %d  max %d, ChangeDQSINCTL=%d\n", u1TXDLY_Cal_min, u1TXDLY_Cal_max, s1ChangeDQSINCTL));
+    //mcDUMP_REG_MSG(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R));
+#else
+    //XRTR2R=A-phy forbidden margin(6T) + reg_TX_dly_DQSgated (max) +Roundup(tDQSCKdiff/MCK+0.25MCK)+1(05T sel_ph margin)-1(forbidden margin overlap part)
+    //Roundup(tDQSCKdiff/MCK+1UI) =1~2 all LP3 and LP4 timing
+    //u4XRTR2R= 8 + u1TXDLY_Cal_max;  // 6+ u1TXDLY_Cal_max +2
+
+    //Modify for corner IC failed at HQA test XTLV @ 3200MHz
+    u4XRTR2R = 8 + u1TXDLY_Cal_max + 1;  // 6+ u1TXDLY_Cal_max +2
+    if (u4XRTR2R > 12)
+    {
+        u4XRTR2R = 12;
+        mcSHOW_ERR_MSG(("XRTR2R > 12, Max value is 12\n"));
+    }
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ACTIM_XRT), u4XRTR2R, SHU_ACTIM_XRT_XRTR2R);
+
+    mcSHOW_DBG_MSG2(("TX_dly_DQSgated check: min %d  max %d, ChangeDQSINCTL=%d\n", u1TXDLY_Cal_min, u1TXDLY_Cal_max, s1ChangeDQSINCTL));
+    mcSHOW_DBG_MSG2(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R));
+    //mcDUMP_REG_MSG(("TX_dly_DQSgated check: min %d  max %d, ChangeDQSINCTL=%d\n", u1TXDLY_Cal_min, u1TXDLY_Cal_max, s1ChangeDQSINCTL));
+    //mcDUMP_REG_MSG(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R));
+#endif
+
+#if 0//ENABLE_RODT_TRACKING
+    //Because Ki_bo+,WE2,Bi_anco,Vin_son...or behind project support WDQS, they need to apply the correct new setting
+    //The following 2 items are indepentent
+    //1. if TX_WDQS on(by vendor_id) or p->odt_onoff = 1, ROEN/RODTE/RODTE2 = 1
+    //2. if ENABLE_RODT_TRACKING on, apply new setting and RODTENSTB_TRACK_EN = ROEN
+    // LP4 support only
+    U8 u1ReadROEN;
+    u1ReadROEN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), SHU_ODTCTRL_ROEN);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_RODTENSTB), P_Fld(0xff, SHU_RODTENSTB_RODTENSTB_EXT) | \
+                                                            P_Fld(u1ReadROEN, SHU_RODTENSTB_RODTENSTB_TRACK_EN));
+#endif
+
+#ifdef XRTR2W_PERFORM_ENHANCE_RODTEN
+    // LP4 support only
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB),
+        P_Fld(0x0fff, MISC_SHU_RODTENSTB_RODTENSTB_EXT) |
+        P_Fld(1, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) |
+        P_Fld(1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN));
+#endif
+
+    vSetRank(p, backup_rank);
+
+
+}
+#endif
+
+#if GATING_ADJUST_TXDLY_FOR_TRACKING
+void DramcRxdqsGatingPreProcess(DRAMC_CTX_T *p)
+{
+    u1TXDLY_Cal_min = 0xff;
+    u1TXDLY_Cal_max = 0;
+}
+#endif
+///TODO: wait for porting ---
+
+#endif
+
+#if RDSEL_TRACKING_EN
+void RDSELRunTimeTracking_preset(DRAMC_CTX_T *p)
+{
+    S32 s4PosVH, s4NegVH;
+
+    s4PosVH = divRoundClosest(400, ((1000000 / p->frequency) / 64));
+    s4NegVH = 1;
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RDSEL_TRACK), P_Fld(s4PosVH, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)
+                                                    | P_Fld(s4NegVH, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG));
+}
+#endif
+
+#if __LP5_COMBO__
+static void vSetLP5DramRDDQC_DQandDMI(DRAMC_CTX_T *p, U8 eDQMode, U8 eDMIMode)
+{
+    // Set DQ
+    if (eDQMode == 0)   // Invert
+        u1MR20Value[p->dram_fsp] &= ~0x80;
+    else // low-fixed
+        u1MR20Value[p->dram_fsp] |= 0x80;
+
+    // Set DMI
+    if (eDMIMode == 0)  // By pattern
+        u1MR20Value[p->dram_fsp] &= ~0x40;
+    else // low-fixed
+        u1MR20Value[p->dram_fsp] |= 0x40;
+
+    DramcModeRegWriteByRank(p, p->rank, 20, u1MR20Value[p->dram_fsp]);
+}
+
+static void vSetLP5Dram_WCKON_OnOff(DRAMC_CTX_T *p, U8 u1OnOff)
+{
+    U8 rk;
+    U8 backup_mrsrk;
+
+    // Issue MR18 OP[4] to enable/disable WCK always ON mode
+    if (u1OnOff == ON)
+        u1MR18Value[p->dram_fsp] |= 0x10;  // OP[4] WCK ON = 1
+    else
+        u1MR18Value[p->dram_fsp] &= 0xEF;  // OP[4] WCK ON = 0
+
+    backup_mrsrk = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0),
+        SWCMD_CTRL0_MRSRK);
+
+    //zj DramcModeRegWriteByRank(p, p->rank, 18, u1MR18Value[p->dram_fsp]);
+    for (rk = RANK_0; rk < p->support_rank_num; rk++) {
+        DramcModeRegWriteByRank(p, rk, 18, u1MR18Value[p->dram_fsp]);
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), backup_mrsrk,
+        SWCMD_CTRL0_MRSRK);
+}
+#endif
+
+#if RDDQC_PINMUX_WORKAROUND
+static void RDDQCPinmuxWorkaround(DRAMC_CTX_T *p)
+{
+    U8 *uiLPDDR_RDDQC_Mapping;
+#if (__LP5_COMBO__)
+    const U8 uiLPDDR5_RDDQC_Mapping_POP[CHANNEL_NUM][16] =
+    {
+        {
+            8, 9, 10, 11, 12, 15, 14, 13,
+            0, 1, 2, 3, 4, 7, 6, 5,
+        },
+        #if (CHANNEL_NUM>1)
+        {
+            8, 9, 10, 11, 12, 15, 14, 13,
+            0, 1, 2, 3, 4, 7, 6, 5,
+        },
+        #endif
+    };
+
+#endif
+    const U8 uiLPDDR4_RDDQC_Mapping_POP[PINMUX_MAX][CHANNEL_NUM][16] =
+    {
+        {
+        // for EMCP
+            //CH-A
+            {
+		0, 1, 2, 3, 7, 4, 6, 5,
+		9, 8, 12, 14, 15, 10, 13, 11
+            },
+#if (CHANNEL_NUM>1)
+            //CH-B
+            {
+		0, 1, 7, 4, 3, 2, 6, 5,
+		9, 8, 12, 14, 15, 10, 11, 13
+            },
+#endif
+#if (CHANNEL_NUM>2)
+            //CH-C
+            {
+		0, 1, 2, 3, 7, 4, 6, 5,
+		9, 8, 12, 14, 15, 10, 13, 11
+            },
+            //CH-D
+            {
+		0, 1, 7, 4, 3, 2, 6, 5,
+		9, 8, 12, 14, 15, 10, 11, 13
+            },
+#endif
+        },
+        {
+        // for DSC_2CH, HFID RESERVED
+            //CH-A
+            {
+		0, 1, 4, 3, 2, 5, 7, 6,
+		9, 8, 10, 11, 15, 13, 12, 14
+            },
+#if (CHANNEL_NUM>1)
+            //CH-B
+            {
+		0, 1, 2, 5, 3, 4, 7, 6,
+		8, 9, 10, 11, 15, 14, 13, 12
+            },
+            #endif
+            #if (CHANNEL_NUM>2)
+            //CH-C
+            {
+		0, 1, 2, 3, 4, 5, 6, 7,
+		8, 9, 10, 11, 12, 13, 14, 15
+            },
+            //CH-D
+            {
+		0, 1, 2, 3, 4, 5, 6, 7,
+		8, 9, 10, 11, 12, 13, 14, 15
+            },
+#endif
+        },
+        {
+        // for MCP
+            //CH-A
+            {
+                0, 1, 6, 2, 4, 7, 3, 5,
+                8, 9, 10, 12, 13, 11, 15, 14
+            },
+            #if (CHANNEL_NUM>1)
+            //CH-B
+            {
+                0, 1, 7, 4, 2, 5, 6, 3,
+                9, 8, 10, 12, 11, 14, 13, 15
+            },
+            #endif
+            #if (CHANNEL_NUM>2)
+            //CH-C
+            {
+                1, 0, 3, 2, 4, 7, 6, 5,
+                8, 9, 10, 12, 15, 14, 11, 13
+            },
+            //CH-D
+            {
+                0, 1, 7, 4, 2, 5, 6, 3,
+                9, 8, 10, 12, 11, 14, 13, 15
+            },
+            #endif
+        },
+        {
+        // for DSC_180
+            //CH-A
+            {
+                8, 9, 14, 15, 12, 13, 11, 10,
+                1, 0, 3, 2, 7, 6, 4, 5
+            },
+            #if (CHANNEL_NUM>1)
+            //CH-B
+            {
+                9, 8, 13, 12, 15, 10, 11, 14,
+                0, 1, 3, 2, 4, 6, 5, 7
+            },
+            #endif
+            #if (CHANNEL_NUM>2)
+            //CH-C
+            {
+                0, 1, 6, 7, 4, 5, 3, 2,
+                9, 8, 11, 10, 15, 14, 12, 13
+            },
+            //CH-D
+            {
+                1, 0, 5, 4, 7, 2, 3, 6,
+                8, 9, 11, 10, 12, 14, 13, 15
+            },
+            #endif
+        }
+    };
+
+    #if (__LP5_COMBO__)
+    if (is_lp5_family(p))
+    {
+        uiLPDDR_RDDQC_Mapping = (U8 *)uiLPDDR5_RDDQC_Mapping_POP[p->channel];
+    }
+    else
+    #endif
+    {
+        uiLPDDR_RDDQC_Mapping = (U8 *)uiLPDDR4_RDDQC_Mapping_POP[p->DRAMPinmux][p->channel];
+    }
+
+
+    //Set RDDQC pinmux
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX1), P_Fld(uiLPDDR_RDDQC_Mapping[0], MRR_BIT_MUX1_MRR_BIT0_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[1], MRR_BIT_MUX1_MRR_BIT1_SEL) |
+                                                               P_Fld(uiLPDDR_RDDQC_Mapping[2], MRR_BIT_MUX1_MRR_BIT2_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[3], MRR_BIT_MUX1_MRR_BIT3_SEL));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX2), P_Fld(uiLPDDR_RDDQC_Mapping[4], MRR_BIT_MUX2_MRR_BIT4_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[5], MRR_BIT_MUX2_MRR_BIT5_SEL) |
+                                                               P_Fld(uiLPDDR_RDDQC_Mapping[6], MRR_BIT_MUX2_MRR_BIT6_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[7], MRR_BIT_MUX2_MRR_BIT7_SEL));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX3), P_Fld(uiLPDDR_RDDQC_Mapping[8], MRR_BIT_MUX3_MRR_BIT8_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[9], MRR_BIT_MUX3_MRR_BIT9_SEL) |
+                                                               P_Fld(uiLPDDR_RDDQC_Mapping[10], MRR_BIT_MUX3_MRR_BIT10_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[11], MRR_BIT_MUX3_MRR_BIT11_SEL));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX4), P_Fld(uiLPDDR_RDDQC_Mapping[12], MRR_BIT_MUX4_MRR_BIT12_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[13], MRR_BIT_MUX4_MRR_BIT13_SEL) |
+                                                               P_Fld(uiLPDDR_RDDQC_Mapping[14], MRR_BIT_MUX4_MRR_BIT14_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[15], MRR_BIT_MUX4_MRR_BIT15_SEL));
+
+}
+#endif
+
+#define RDDQCGOLDEN_LP5_MR30_BIT_CTRL_LOWER   RDDQCGOLDEN_MR15_GOLDEN
+#define RDDQCGOLDEN_LP5_MR31_BIT_CTRL_UPPER   RDDQCGOLDEN_MR20_GOLDEN
+#define RDDQCGOLDEN_LP5_MR32_PATTERN_A        RDDQCGOLDEN_MR32_GOLDEN
+#define RDDQCGOLDEN_LP5_MR33_PATTERN_B        RDDQCGOLDEN_MR40_GOLDEN
+static U32 DramcRxWinRDDQCInit(DRAMC_CTX_T *p)
+{
+    //int i;
+    //U8 *uiLPDDR_O1_Mapping;
+    //U16 temp_value = 0;
+    U8 RDDQC_Bit_Ctrl_Lower = 0x55;
+    U8 RDDQC_Bit_Ctrl_Upper = 0x55;
+    U8 RDDQC_Pattern_A = 0x5A;
+    U8 RDDQC_Pattern_B = 0x3C;
+
+#if FOR_DV_SIMULATION_USED == 1
+    cal_sv_rand_args_t *psra = get_psra();
+
+    if (psra) {
+        RDDQC_Bit_Ctrl_Lower = psra->low_byte_invert_golden & 0xFF;
+        RDDQC_Bit_Ctrl_Upper = psra->upper_byte_invert_golden & 0xFF;
+        RDDQC_Pattern_A = psra->mr_dq_a_golden;
+        RDDQC_Pattern_B = psra->mr_dq_b_golden;
+
+        /*
+         * TODO
+         *
+         * sv also passes mr20_6 and mr20_7 to sa.
+         * currently, sa does NOT use these two random arguments.
+         */
+    }
+#endif /* FOR_DV_SIMULATION_USED == 1 */
+
+    // Disable Read DBI
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7), 0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7), 0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1GetRank(p), SWCMD_CTRL0_MRSRK);
+
+#if RDDQC_PINMUX_WORKAROUND
+    // Translate pin order by MRR bit sel
+    RDDQCPinmuxWorkaround(p);
+#endif
+
+    // Set golden values into dram MR
+#if (__LP5_COMBO__ == TRUE)
+    if (TRUE == is_lp5_family(p))
+    {
+        DramcModeRegWriteByRank(p, p->rank, 31, RDDQC_Bit_Ctrl_Lower);
+        DramcModeRegWriteByRank(p, p->rank, 32, RDDQC_Bit_Ctrl_Upper);
+        DramcModeRegWriteByRank(p, p->rank, 33, RDDQC_Pattern_A);
+        DramcModeRegWriteByRank(p, p->rank, 34, RDDQC_Pattern_B);
+    }
+    else
+#endif
+    {
+        DramcModeRegWriteByRank(p, p->rank, 15, RDDQC_Bit_Ctrl_Lower);
+        DramcModeRegWriteByRank(p, p->rank, 20, RDDQC_Bit_Ctrl_Upper);
+        DramcModeRegWriteByRank(p, p->rank, 32, RDDQC_Pattern_A);
+        DramcModeRegWriteByRank(p, p->rank, 40, RDDQC_Pattern_B);
+    }
+
+    //Set golden values into RG, watch out the MR_index of RGs are reference LP4
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RDDQCGOLDEN),
+            P_Fld(RDDQC_Bit_Ctrl_Lower, RDDQCGOLDEN_LP5_MR30_BIT_CTRL_LOWER) |
+            P_Fld(RDDQC_Bit_Ctrl_Upper, RDDQCGOLDEN_LP5_MR31_BIT_CTRL_UPPER) |
+            P_Fld(RDDQC_Pattern_A, RDDQCGOLDEN_LP5_MR32_PATTERN_A) |
+            P_Fld(RDDQC_Pattern_B, RDDQCGOLDEN_LP5_MR33_PATTERN_B));
+
+    // Open gated clock, by KaiHsin   (DCM)
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ8),
+            P_Fld(1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ8),
+            P_Fld(1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1));
+
+#if (__LP5_COMBO__ == TRUE)
+    if (is_lp5_family(p))
+    {
+        // Set function mode applied to DQ & DMI
+//        U8 RDDQC_RDC_DQ_mode = 0;
+//        U8 RDDQC_RDC_DMI_mode = 0;
+
+//        vSetLP5DramRDDQC_DQandDMI(p, RDDQC_RDC_DQ_mode, RDDQC_RDC_DMI_mode);
+
+//        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RDDQCGOLDEN1),
+//                P_Fld(RDDQC_RDC_DQ_mode, RDDQCGOLDEN1_LP5_MR20_7_GOLDEN) |
+//                P_Fld(RDDQC_RDC_DMI_mode, RDDQCGOLDEN1_LP5_MR20_6_GOLDEN));
+
+        if (is_heff_mode(p) == FALSE)
+        {
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0), 1, SHU_COMMON0_LP5WCKON);
+
+            // Enable MR18 "WCK always ON mode"
+            vSetLP5Dram_WCKON_OnOff(p, ON);
+        }
+
+        RunTime_SW_Cmd(p, RUNTIME_SWCMD_CAS_FS);
+    }
+#endif
+    return 0;
+}
+#if 0
+static U32 DramcRxWinRDDQCEnd(DRAMC_CTX_T *p)
+{
+    // Recover MPC Rank
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), 0, SWCMD_CTRL0_MRSRK);
+
+#if (__LP5_COMBO__ == TRUE)
+    if (is_lp5_family(p))
+    {
+        RunTime_SW_Cmd(p, RUNTIME_SWCMD_CAS_OFF);
+
+        if (is_heff_mode(p) == FALSE)
+        {
+            // Disable MR18 "WCK always ON mode"
+            vSetLP5Dram_WCKON_OnOff(p, OFF);
+
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0), 0, SHU_COMMON0_LP5WCKON);
+        }
+    }
+#endif
+    return 0;
+}
+#endif
+static void SetRxVref(DRAMC_CTX_T *p, U8 u1Vref_B0, U8 u1Vref_B1)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL),
+                            P_Fld(u1Vref_B0, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0) |
+                            P_Fld(u1Vref_B0, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0));
+    if (!isLP4_DSC)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL),
+                                P_Fld(u1Vref_B1, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1) |
+                                P_Fld(u1Vref_B1, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B1));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_PHY_VREF_SEL),
+                                P_Fld(u1Vref_B1, SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_LB) |
+                                P_Fld(u1Vref_B1, SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_UB));
+    }
+}
+#if 0
+static void SetRxDqDelay(DRAMC_CTX_T *p, U8 ii, S16 iDelay)
+{
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + (ii * 4)),
+            P_Fld(iDelay, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+            P_Fld(iDelay, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + (ii * 4)),
+            P_Fld(iDelay, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+            P_Fld(iDelay, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
+}
+
+static void SetRxDqDqsDelay(DRAMC_CTX_T *p, S16 iDelay)
+{
+    U8 ii; //u1ByteIdx
+    //U32 u4value;
+
+    if (iDelay <= 0)
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5), (-iDelay), SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5), (-iDelay), SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1);
+        //DramPhyReset(p);
+    }
+    else
+    {
+        // Adjust DQM output delay.
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), iDelay, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), iDelay, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1);
+        //DramPhyReset(p);
+
+        // Adjust DQ output delay.
+        for (ii = 0; ii < 4; ii++)
+            SetRxDqDelay(p, ii, iDelay);
+
+    }
+}
+
+/* Issue "RD DQ Calibration"
+ * 1. SWCMD_CTRL1_RDDQC_LP_ENB = 1 to stop RDDQC burst
+ * 2. RDDQCEN = 1 for RDDQC
+ * 3. Wait rddqc_response = 1
+ * 4. Read compare result
+ * 5. RDDQCEN = 0
+ */
+
+ static U32 DramcRxWinRDDQCRun(DRAMC_CTX_T *p)
+{
+    U32 u4Result = 0, u4TmpResult;
+    DRAM_STATUS_T u4Response = DRAM_FAIL;
+
+    //Issue RD DQ calibration
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL1), 1, SWCMD_CTRL1_RDDQC_LP_ENB);
+
+    // Trigger and wait
+    REG_TRANSFER_T TriggerReg = {DRAMC_REG_SWCMD_EN, SWCMD_EN_RDDQCEN};
+    REG_TRANSFER_T RepondsReg = {DRAMC_REG_SPCMDRESP, SPCMDRESP_RDDQC_RESPONSE};
+    u4Response = DramcTriggerAndWait(p, TriggerReg, RepondsReg);
+
+    // Read RDDQC compare result
+    u4TmpResult = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RDQC_CMP));
+    u4Result = (0xFFFF) & ((u4TmpResult) | (u4TmpResult >> 16)); // (BL0~7) | (BL8~15)
+
+#if (FEATURE_RDDQC_K_DMI == TRUE)
+    // Read DQM compare result
+    u4TmpResult = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RDQC_DQM_CMP), RDQC_DQM_CMP_RDDQC_DQM_CMP0_ERR);
+    u4TmpResult |= u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RDQC_DQM_CMP), RDQC_DQM_CMP_RDDQC_DQM_CMP1_ERR);
+    u4Result |= (u4TmpResult << 16);
+#endif
+
+    //R_DMRDDQCEN -> 0
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RDDQCEN);
+
+    return u4Result;
+}
+#endif
+DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
+                                              RX_PATTERN_OPTION_T u1UseTestEngine,
+                                              U8 *u1AssignedVref,
+                                              U8 isAutoK,
+                                              U8 K_Type)
+{
+    U8 u1BitIdx, u1ByteIdx; //ii
+    //U32 u1vrefidx;
+    //U8 ucbit_first, ucbit_last;
+    //S16 iDelay = 0, S16DelayBegin = 0, u4DelayStep=1;
+    U16 u16DelayStep = 1; //u16DelayEnd = 0
+    //U32 uiFinishCount;
+    //U32 u4err_value, u4fail_bit, u4value;
+    PASS_WIN_DATA_T FinalWinPerBit[DQ_DATA_WIDTH + RDDQC_ADD_DMI_NUM]; //WinPerBit[DQ_DATA_WIDTH + RDDQC_ADD_DMI_NUM]
+    S32 iDQSDlyPerbyte[DQS_BYTE_NUMBER], iDQMDlyPerbyte[DQS_BYTE_NUMBER];//, iFinalDQSDly[DQS_NUMBER];
+    U8 u1VrefScanEnable = FALSE;
+    //U16 u2TempWinSum[DQS_BYTE_NUMBER]={0}, u2rx_window_sum[DQS_BYTE_NUMBER]={0}, u2TmpDQMSum=0;
+    U16 u2FinalVref [DQS_BYTE_NUMBER]= {0xe, 0xe}; //u2VrefLevel
+    U16 u2VrefBegin, u2VrefEnd, u2VrefStep;
+    //U32 u4fail_bit_R, u4fail_bit_F;
+    U8  u1RXEyeScanEnable=(K_Type==NORMAL_K ? DISABLE : ENABLE),u1PrintCalibrationProc;
+    //U16 u1min_bit_by_vref[DQS_BYTE_NUMBER], u1min_winsize_by_vref[DQS_BYTE_NUMBER];
+    //U16 u1min_bit[DQS_BYTE_NUMBER], u1min_winsize[DQS_BYTE_NUMBER]={0};
+    U8 u1CalDQMNum = 0;
+    //U32 u4PassFlags = 0xFFFF;
+
+    U16 backup_RX_FinalVref_Value[DQS_BYTE_NUMBER]={0};
+    U32 backup_DQS_Dly_Value[DQS_BYTE_NUMBER]={0};
+    U32 backup_DQM_Dly_Value[DQS_BYTE_NUMBER]={0};
+    U32 backup_DQ_Dly_Value[DQ_DATA_WIDTH]={0};
+#if ENABLE_EYESCAN_GRAPH
+    U8 EyeScan_index[DQ_DATA_WIDTH + RDDQC_ADD_DMI_NUM] = {0};
+    U8 u1pass_in_this_vref_flag[DQ_DATA_WIDTH + RDDQC_ADD_DMI_NUM];
+#endif
+
+    U8 backup_rank, rank_i, u1KnownVref[2]={0xff, 0xff};
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    // error handling
+    if (!p)
+    {
+        mcSHOW_ERR_MSG(("context NULL\n"));
+        return DRAM_FAIL;
+    }
+
+
+    U32 u4RegBackupAddress[] =
+    {
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_AUTOK_CFG0)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_AUTOK_CFG1)),
+    #if RDDQC_PINMUX_WORKAROUND
+        (DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX1)),
+        (DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX2)),
+        (DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX3)),
+        (DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX4)),
+    #endif
+    };
+
+    //Back up dramC register
+    DramcBackupRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress));
+
+#if (FEATURE_RDDQC_K_DMI == TRUE)
+    if (u1UseTestEngine == PATTERN_RDDQC)
+    {
+        u1CalDQMNum = 2;
+        iDQMDlyPerbyte[0] = -0xFFFFFF;
+        iDQMDlyPerbyte[1] = -0xFFFFFF;
+    }
+    else
+#endif
+    {
+        u1CalDQMNum = 0;
+        iDQMDlyPerbyte[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0);
+        iDQMDlyPerbyte[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1);
+
+    }
+
+
+    if (u1RXEyeScanEnable)
+    {
+        backup_RX_FinalVref_Value[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL), SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0);
+        if (!isLP4_DSC)
+            backup_RX_FinalVref_Value[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL), SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1);
+        else
+            backup_RX_FinalVref_Value[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_PHY_VREF_SEL), SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_LB);
+
+        backup_DQS_Dly_Value[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5), SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0);
+        backup_DQS_Dly_Value[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5), SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1);
+
+        backup_DQM_Dly_Value[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0);
+        backup_DQM_Dly_Value[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1);
+
+        for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2)
+        {
+            backup_DQ_Dly_Value[u1BitIdx  ] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + u1BitIdx * 2), SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0);
+            backup_DQ_Dly_Value[u1BitIdx+1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + u1BitIdx * 2), SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0);
+            backup_DQ_Dly_Value[u1BitIdx+8] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + u1BitIdx * 2), SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1);
+            backup_DQ_Dly_Value[u1BitIdx+9] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + u1BitIdx * 2), SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1);
+        }
+
+#if ENABLE_EYESCAN_GRAPH
+        if (u1UseTestEngine == PATTERN_TEST_ENGINE)
+        {
+            for(u1vrefidx=0; u1vrefidx<EYESCAN_RX_VREF_RANGE_END;u1vrefidx++)
+            {
+                for (u1BitIdx = 0; u1BitIdx < DQ_DATA_WIDTH; u1BitIdx++)
+                {
+                    for(ii=0; ii<EYESCAN_BROKEN_NUM; ii++)
+                    {
+                        gEyeScan_Min[u1vrefidx][u1BitIdx][ii] = EYESCAN_DATA_INVALID;
+                        gEyeScan_Max[u1vrefidx][u1BitIdx][ii] = EYESCAN_DATA_INVALID;
+
+                        gEyeScan_ContinueVrefHeight[u1BitIdx] = 0;
+                        gEyeScan_TotalPassCount[u1BitIdx] = 0;
+                    }
+                }
+            }
+        }
+#endif
+    }
+
+    //RX_ARDQS_DLY_LAT_EN=1: RX delay will update when GATE_EN=0, and can prevent glitch in ACD.
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10), 1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0);
+    if (!isLP4_DSC)
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10), 1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1);
+    else
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD10), 1, SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA);
+
+
+    //When doing RxWindowPerbitCal, should make sure that auto refresh is disable
+    vAutoRefreshSwitch(p, DISABLE);
+    //CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL);
+
+    backup_rank = u1GetRank(p);
+
+    //defult set result fail. When window found, update the result as oK
+    if (u1UseTestEngine == PATTERN_TEST_ENGINE)
+    {
+        if (u1RXEyeScanEnable == DISABLE)
+        {
+            vSetCalibrationResult(p, DRAM_CALIBRATION_RX_PERBIT, DRAM_FAIL);
+        }
+
+        // Something wrong with TA2 pattern -- SI, which causes RX autoK fail.
+        if (isAutoK == TRUE)
+        {
+            DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT);
+        }
+        else
+        {
+#if ENABLE_K_WITH_WORST_SI_UI_SHIFT
+            DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//UI_SHIFT + LEN1
+#else
+            DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern, 0, TE_NO_UI_SHIFT);
+#endif
+        }
+    }
+    else
+    {
+        if (u1RXEyeScanEnable == DISABLE)
+        {
+            vSetCalibrationResult(p, DRAM_CALIBRATION_RX_RDDQC, DRAM_FAIL);
+        }
+        DramcRxWinRDDQCInit(p);
+    }
+
+    // Intialize, diable RX Vref
+    u2VrefBegin = 0;
+    u2VrefEnd = 0;
+    u2VrefStep = 1;
+
+    if ((u1UseTestEngine == PATTERN_TEST_ENGINE))
+    {
+    #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
+        if ((p->rank==RANK_0) || (p->frequency >= RX_VREF_DUAL_RANK_K_FREQ) || (u1RXEyeScanEnable==1))
+            u1VrefScanEnable =1;
+    #else
+            u1VrefScanEnable =0;
+    #endif
+    }
+
+    u1PrintCalibrationProc = ((u1VrefScanEnable == 0) || (u1RXEyeScanEnable == 1) || (u1AssignedVref != NULL));
+
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+    if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE)))
+    {
+        mcSHOW_DBG_MSG(("[FAST_K] Bypass RX Calibration\n"));
+    }
+    else
+#endif
+    {
+
+        //mcDUMP_REG_MSG(("\n[dumpRG] %s\n",u1UseTestEngine==PATTERN_RDDQC?"RDDQC":"DramcRxWindowPerbitCal"));
+#if VENDER_JV_LOG
+#if 0 //BU don't want customer knows our RX's ability
+        if (u1UseTestEngine == 1)
+            vPrintCalibrationBasicInfo_ForJV(p);
+#endif
+#else
+        vPrintCalibrationBasicInfo(p);
+#endif
+        //mcSHOW_DBG_MSG2(("Start DQ dly to find pass range UseTestEngine =%d\n", u1UseTestEngine));
+    }
+
+    mcSHOW_DBG_MSG(("[RxWindowPerbitCal] UseTestEngine: %s, RX Vref Scan: %d, Autok:%d\n", u1UseTestEngine==PATTERN_RDDQC?"RDDQC":"DramcRxWindowPerbitCal", u1VrefScanEnable, isAutoK));
+
+    if (u1VrefScanEnable)
+    {
+        if ((Get_Vref_Calibration_OnOff(p) == VREF_CALI_OFF) && (u1RXEyeScanEnable == 0))
+        {
+            u2VrefBegin = 0;
+            u2VrefEnd = 0;
+            u1KnownVref[0] = gFinalRXVrefDQForSpeedUp[p->channel][p->rank][p->odt_onoff][0];// byte 0
+            u1KnownVref[1] = gFinalRXVrefDQForSpeedUp[p->channel][p->rank][p->odt_onoff][1];// byte 1
+
+            if (u1UseTestEngine == PATTERN_TEST_ENGINE && ((u1KnownVref[0] == 0) || (u1KnownVref[1] == 0)))
+            {
+//                mcSHOW_ERR_MSG(("\nWrong frequency K order= %d\n"));
+                #if __ETT__
+                while (1);
+                #endif
+            }
+        }
+        else if (u1AssignedVref != NULL)  // need to specify RX Vref and don't scan RX Vref.
+        {
+            u2VrefBegin = 0;
+            u2VrefEnd = 0;
+            u1KnownVref[0] = u1AssignedVref[0];  // byte 0
+            u1KnownVref[1] = u1AssignedVref[1];  // byte 1
+        }
+        else
+        {
+            #if (SW_CHANGE_FOR_SIMULATION || FOR_DV_SIMULATION_USED)
+            u2VrefBegin = RX_VREF_RANGE_BEGIN;
+            #else
+            if (u1RXEyeScanEnable == 0)
+            {
+                if (p->odt_onoff)
+                {
+                    u2VrefBegin = RX_VREF_RANGE_BEGIN_ODT_ON;
+                }
+                else
+                {
+                    u2VrefBegin = RX_VREF_RANGE_BEGIN_ODT_OFF;
+                }
+                u2VrefEnd = RX_VREF_RANGE_END-1;
+
+                //mcSHOW_DBG_MSG(("\nSet Vref Range= %d -> %d\n",u2VrefBegin,u2VrefEnd));
+            }
+            else
+            {
+                u2VrefBegin = 0;//Lewis@20160817: Enlarge RX Vref range for eye scan
+                u2VrefEnd = EYESCAN_RX_VREF_RANGE_END-1;
+                //mcSHOW_DBG_MSG(("\nSet Eyescan Vref Range= %d -> %d\n",u2VrefBegin,u2VrefEnd));
+            }
+        #endif
+        }
+
+        if (u1RXEyeScanEnable == 0)
+        {
+            u2VrefStep = RX_VREF_RANGE_STEP;
+        }
+        else
+        {
+            u2VrefStep = EYESCAN_GRAPH_RX_VREF_STEP;
+        }
+
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), 1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0);
+        if (!isLP4_DSC)
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), 1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1);
+        else
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD5), 1, CA_CMD5_RG_RX_ARCMD_VREF_EN);
+    }
+    else // Disable RX Vref
+    {
+        u2VrefBegin = 0;
+        u2VrefEnd = 0;
+        u2VrefStep = 1;
+    }
+
+    //if RDDQD, roughly calibration
+    if (u1UseTestEngine == PATTERN_RDDQC)
+        u16DelayStep <<= 1;
+
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+    if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE)))
+    {
+        // load RX DQS and DQM delay from eMMC
+        for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+        {
+            if (u1VrefScanEnable)
+            {
+                // load RX Vref from eMMC
+            #if ( SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_VREF_CAL)
+                u2FinalVref[u1ByteIdx] = p->pSavetimeData->u1RxWinPerbitVref_Save[p->channel][p->rank][u1ByteIdx];
+            #endif
+            }
+
+            iDQSDlyPerbyte[u1ByteIdx] = p->pSavetimeData->u1RxWinPerbit_DQS[p->channel][p->rank][u1ByteIdx];
+            iDQMDlyPerbyte[u1ByteIdx] = p->pSavetimeData->u1RxWinPerbit_DQM[p->channel][p->rank][u1ByteIdx];
+        }
+
+        // load RX DQ delay from eMMC
+        for (u1BitIdx = 0; u1BitIdx < 16; u1BitIdx++)
+        {
+            FinalWinPerBit[u1BitIdx].best_dqdly = p->pSavetimeData->u1RxWinPerbit_DQ[p->channel][p->rank][u1BitIdx];
+        }
+
+        if (u1RXEyeScanEnable == DISABLE)
+        {
+            if (u1UseTestEngine == PATTERN_TEST_ENGINE)
+                vSetCalibrationResult(p, DRAM_CALIBRATION_RX_PERBIT, DRAM_FAST_K);
+            else
+                vSetCalibrationResult(p, DRAM_CALIBRATION_RX_RDDQC, DRAM_FAST_K);
+        }
+    }
+#endif
+    if (u1RXEyeScanEnable)
+    {
+        u2FinalVref[0] = backup_RX_FinalVref_Value[0];
+        u2FinalVref[1] = backup_RX_FinalVref_Value[1];
+
+        iDQSDlyPerbyte[0] = backup_DQS_Dly_Value[0];
+        iDQSDlyPerbyte[1] = backup_DQS_Dly_Value[1];
+
+        iDQMDlyPerbyte[0] = backup_DQM_Dly_Value[0];
+        iDQMDlyPerbyte[1] = backup_DQM_Dly_Value[1];
+
+        for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2)
+        {
+            FinalWinPerBit[u1BitIdx    ].best_dqdly = backup_DQ_Dly_Value[u1BitIdx  ];
+            FinalWinPerBit[u1BitIdx + 1].best_dqdly = backup_DQ_Dly_Value[u1BitIdx+1];
+            FinalWinPerBit[u1BitIdx + 8].best_dqdly = backup_DQ_Dly_Value[u1BitIdx+8];
+            FinalWinPerBit[u1BitIdx + 9].best_dqdly = backup_DQ_Dly_Value[u1BitIdx+9];
+        }
+    }
+
+    if (u1VrefScanEnable == TRUE)
+    {
+        // When only calibrate RX Vref for Rank 0, apply the same value for Rank 1.
+        for (rank_i = p->rank; rank_i < p->support_rank_num; rank_i++)
+        {
+            vSetRank(p, rank_i);
+
+            SetRxVref(p, u2FinalVref[0], u2FinalVref[1]);
+
+            for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+            {
+                mcSHOW_DBG_MSG(("\nFinal RX Vref Byte %d = %d to rank%d", u1ByteIdx, u2FinalVref[u1ByteIdx], rank_i));
+                //mcDUMP_REG_MSG(("\nFinal RX Vref Byte %d = %d to rank%d", u1ByteIdx, u2FinalVref[u1ByteIdx], rank_i));
+
+                gFinalRXVrefDQ[p->channel][rank_i][u1ByteIdx] = (U8) u2FinalVref[u1ByteIdx];
+                gFinalRXVrefDQForSpeedUp[p->channel][rank_i][p->odt_onoff][u1ByteIdx] = (U8) u2FinalVref[u1ByteIdx];
+            }
+        }
+        vSetRank(p, backup_rank);
+    }
+    mcSHOW_DBG_MSG(("\n"));
+
+#if DUMP_TA2_WINDOW_SIZE_RX_TX
+    //RX
+    if (u1UseTestEngine == PATTERN_TEST_ENGINE)
+    {
+        U32 u4B0Tatal =0;
+        U32 u4B1Tatal =0;
+        mcSHOW_DBG_MSG(("RX window per bit CH[%d] Rank[%d] window size\n", p->channel, p->rank));
+        for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
+        {
+            mcSHOW_DBG_MSG(("DQ[%d] size = %d\n", u1BitIdx, gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx]));
+            if(u1BitIdx < 8)
+            {
+                u4B0Tatal += gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx];
+            }
+            else
+            {
+                u4B1Tatal += gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx];
+            }
+        }
+        mcSHOW_DBG_MSG(("total rx window size B0: %d B1: %d\n", u4B0Tatal, u4B1Tatal));
+    }
+#endif
+
+    // set dqs delay, (dqm delay)
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5),
+            P_Fld((U32)iDQSDlyPerbyte[0], SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4),
+            P_Fld((U32)iDQMDlyPerbyte[0], SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5),
+            P_Fld((U32)iDQSDlyPerbyte[1], SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4),
+            P_Fld((U32)iDQMDlyPerbyte[1], SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1));
+
+    // set dq delay
+    for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2)
+    {
+         vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + u1BitIdx * 2),
+                                        P_Fld(((U32)FinalWinPerBit[u1BitIdx].best_dqdly), SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
+                                        P_Fld(((U32)FinalWinPerBit[u1BitIdx + 1].best_dqdly), SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+
+         vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + u1BitIdx * 2),
+                                        P_Fld((U32)FinalWinPerBit[u1BitIdx + 8].best_dqdly, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
+                                        P_Fld((U32)FinalWinPerBit[u1BitIdx + 9].best_dqdly, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
+
+        //mcSHOW_DBG_MSG(("u1BitId %d  Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2,
+        //                FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly,  FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly));
+    }
+
+    DramPhyReset(p);
+
+#if RDDQC_PINMUX_WORKAROUND
+    DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+#endif
+
+    vSetRank(p, backup_rank);
+    //vPrintCalibrationBasicInfo(p);
+
+#ifdef ETT_PRINT_FORMAT
+    mcSHOW_DBG_MSG(("\nDQS Delay:\nDQS0 = %d, DQS1 = %d\n"
+                    "DQM Delay:\nDQM0 = %d, DQM1 = %d\n",
+                        iDQSDlyPerbyte[0], iDQSDlyPerbyte[1],
+                        iDQMDlyPerbyte[0], iDQMDlyPerbyte[1]));
+    /*mcDUMP_REG_MSG(("\nDQS Delay:\nDQS0 = %d, DQS1 = %d\n"
+                    "DQM Delay:\nDQM0 = %d, DQM1 = %d\n",
+                        iDQSDlyPerbyte[0], iDQSDlyPerbyte[1],
+                        iDQMDlyPerbyte[0], iDQMDlyPerbyte[1]));*/
+#else
+    mcSHOW_DBG_MSG(("\nDQS Delay:\nDQS0 = %2d, DQS1 = %2d\n"
+                    "DQM Delay:\nDQM0 = %2d, DQM1 = %2d\n",
+                        iDQSDlyPerbyte[0], iDQSDlyPerbyte[1],
+                        iDQMDlyPerbyte[0], iDQMDlyPerbyte[1]));
+    /*mcDUMP_REG_MSG(("\nDQS Delay:\nDQS0 = %2d, DQS1 = %2d\n"
+                    "DQM Delay:\nDQM0 = %2d, DQM1 = %2d\n",
+                        iDQSDlyPerbyte[0], iDQSDlyPerbyte[1],
+                        iDQMDlyPerbyte[0], iDQMDlyPerbyte[1]));*/
+#endif
+    mcSHOW_DBG_MSG(("DQ Delay:\n"));
+    //mcDUMP_REG_MSG(("DQ Delay:\n"));
+
+    for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx = u1BitIdx + 4)
+    {
+#ifdef ETT_PRINT_FORMAT
+        mcSHOW_DBG_MSG(("DQ%d =%d, DQ%d =%d, DQ%d =%d, DQ%d =%d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly));
+        //mcDUMP_REG_MSG(("DQ%d =%d, DQ%d =%d, DQ%d =%d, DQ%d =%d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly));
+#else
+        mcSHOW_DBG_MSG(("DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly));
+        //mcDUMP_REG_MSG(("DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly));
+#endif
+    }
+    mcSHOW_DBG_MSG(("\n"));
+    mcSHOW_DBG_MSG4(("[DramcRxWindowPerbitCal] Done\n"));
+
+    #if LP5_DDR4266_RDBI_WORKAROUND
+    if((is_lp5_family(p)) && (p->frequency >= 2133))
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7), 1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7), 1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1);
+    }
+    #endif
+
+return DRAM_OK;
+
+    // Log example  ==> Neec to update
+    /*
+------------------------------------------------------
+Start calculate dq time and dqs time /
+Find max DQS delay per byte / Adjust DQ delay to align DQS...
+------------------------------------------------------
+bit# 0 : dq time=11 dqs time= 8
+bit# 1 : dq time=11 dqs time= 8
+bit# 2 : dq time=11 dqs time= 6
+bit# 3 : dq time=10 dqs time= 8
+bit# 4 : dq time=11 dqs time= 8
+bit# 5 : dq time=10 dqs time= 8
+bit# 6 : dq time=11 dqs time= 8
+bit# 7 : dq time= 9 dqs time= 6
+----seperate line----
+bit# 8 : dq time=12 dqs time= 7
+bit# 9 : dq time=10 dqs time= 8
+bit#10 : dq time=11 dqs time= 8
+bit#11 : dq time=10 dqs time= 8
+bit#12 : dq time=11 dqs time= 8
+bit#13 : dq time=11 dqs time= 8
+bit#14 : dq time=11 dqs time= 8
+bit#15 : dq time=12 dqs time= 8
+----seperate line----
+bit#16 : dq time=11 dqs time= 7
+bit#17 : dq time=10 dqs time= 8
+bit#18 : dq time=11 dqs time= 7
+bit#19 : dq time=11 dqs time= 6
+bit#20 : dq time=10 dqs time= 9
+bit#21 : dq time=11 dqs time=10
+bit#22 : dq time=11 dqs time=10
+bit#23 : dq time= 9 dqs time= 9
+----seperate line----
+bit#24 : dq time=12 dqs time= 6
+bit#25 : dq time=13 dqs time= 6
+bit#26 : dq time=13 dqs time= 7
+bit#27 : dq time=11 dqs time= 7
+bit#28 : dq time=12 dqs time= 8
+bit#29 : dq time=10 dqs time= 8
+bit#30 : dq time=13 dqs time= 7
+bit#31 : dq time=11 dqs time= 8
+----seperate line----
+==================================================
+    dramc_rxdqs_perbit_swcal_v2
+    channel=2(2:cha, 3:chb) apply = 1
+==================================================
+DQS Delay :
+ DQS0 = 0 DQS1 = 0 DQS2 = 0 DQS3 = 0
+DQ Delay :
+DQ 0 =  1 DQ 1 =  1 DQ 2 =  2 DQ 3 =  1
+DQ 4 =  1 DQ 5 =  1 DQ 6 =  1 DQ 7 =  1
+DQ 8 =  2 DQ 9 =  1 DQ10 =  1 DQ11 =  1
+DQ12 =  1 DQ13 =  1 DQ14 =  1 DQ15 =  2
+DQ16 =  2 DQ17 =  1 DQ18 =  2 DQ19 =  2
+DQ20 =  0 DQ21 =  0 DQ22 =  0 DQ23 =  0
+DQ24 =  3 DQ25 =  3 DQ26 =  3 DQ27 =  2
+DQ28 =  2 DQ29 =  1 DQ30 =  3 DQ31 =  1
+_______________________________________________________________
+   */
+}
+
+#if SIMULATION_RX_DVS
+static U8 DramcRxDVSCal(DRAMC_CTX_T *p, U8 u1byte)
+{
+    U8 u1rising_lead, u1falling_lead, u1rising_lag, u1falling_lag, u1lead_lag;
+
+    if (u1byte == 0)
+    {
+        u1rising_lead = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS0), MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LEAD_B0);
+        u1falling_lead = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS1), MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LEAD_B0);
+        u1rising_lag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS0), MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B0);
+        u1falling_lag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS1), MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LAG_B0);
+    }
+    else //byte1
+    {
+        u1rising_lead = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS0), MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B1);
+        u1falling_lead = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS1), MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LEAD_B1);
+        u1rising_lag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS0), MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B1);
+        u1falling_lag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS1), MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LAG_B1);
+    }
+
+    mcSHOW_DBG_MSG2(("Byte%d | LEAD(%d %d) | LAG(%d %d)\n", u1byte, u1rising_lead, u1falling_lead, u1rising_lag, u1falling_lag));
+
+    u1lead_lag = (u1rising_lead | u1falling_lead | u1rising_lag | u1falling_lag);
+
+    return u1lead_lag;
+}
+
+DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p)
+{
+    U8 ii, u1ByteIdx;
+    S16 iDelay = 0, S16DelayBegin = 0;
+    U16 u16DelayEnd = 0, u16DelayStep = 1;
+    U32 u4err_value;
+
+    U8 u1lead_lag, u1DVS_first_flag[DQS_BYTE_NUMBER]={0}, u1DVS_first_pass[DQS_BYTE_NUMBER]={0}, u1DVS_pass_window[DQS_BYTE_NUMBER]={0}, u1finish_flag[DQS_BYTE_NUMBER]={0};
+    U32 u4RegBackupAddress[] =
+    {
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4)),
+    };
+
+    // error handling
+    if (!p)
+    {
+        mcSHOW_ERR_MSG(("context NULL\n"));
+        return DRAM_FAIL;
+    }
+
+    mcSHOW_DBG_MSG(("[RX DVS calibration]\n"));
+
+    //When doing RxWindowPerbitCal, should make sure that auto refresh is disable
+    vAutoRefreshSwitch(p, DISABLE);
+    //CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), 1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), 1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1);
+
+    //defult set result fail. When window found, update the result as oK
+#if ENABLE_K_WITH_WORST_SI_UI_SHIFT
+    DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//PIC Need to check if need to use UI_SHIFT;//UI_SHIFT + LEN1
+#else
+    DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT);
+#endif
+
+
+#if (__LP5_COMBO__ == TRUE)
+    if (is_lp5_family(p))
+    {
+        // 1 step = 1/4 delay cell
+        // Adjust step = 1/2/4(precision adjustment) by data-rate
+        if (p->frequency <= GetFreqBySel(p,LP5_DDR3200))
+            u16DelayStep = 4;
+        else if (p->frequency <= GetFreqBySel(p,LP5_DDR4800)) // 3733, 4266, 4800
+            u16DelayStep = 2;
+        else // 5500, 6000, 6400
+            u16DelayStep = 1;
+    }
+    else
+#endif
+    {
+        u16DelayStep = 4;
+    }
+    // Just for DV SIM test
+    S16DelayBegin = -80;
+    u16DelayEnd = 100;
+
+    mcSHOW_DBG_MSG2(("\nRX Delay %d -> %d, step: %d\n", S16DelayBegin, u16DelayEnd, u16DelayStep));
+
+    {
+        // Adjust DQM output delay to 0
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4),
+                P_Fld(0, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
+                P_Fld(0, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4),
+                P_Fld(0, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
+                P_Fld(0, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
+
+        // Adjust DQ output delay to 0
+        //every 2bit dq have the same delay register address
+        for (ii = 0; ii < 4; ii++)
+            SetRxDqDelay(p, ii, 0);
+        {
+            // non-autok flow
+            for (iDelay = S16DelayBegin; iDelay <= u16DelayEnd; iDelay += u16DelayStep)
+            {
+                SetRxDqDqsDelay(p, iDelay);
+
+                u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, p->test_pattern);
+
+                mcSHOW_DBG_MSG2(("iDelay= %4d, err_value: 0x%x", iDelay, u4err_value));
+
+                for(u1ByteIdx=0; u1ByteIdx<DQS_BYTE_NUMBER; u1ByteIdx++)
+                {
+                    u1lead_lag = DramcRxDVSCal(p, u1ByteIdx);
+
+                    if ((u1lead_lag == 0) && (u1DVS_first_flag[u1ByteIdx] == 0) && (((u4err_value >> (u1ByteIdx<<3)) & 0xff) == 0))
+                    {
+                        u1DVS_first_pass[u1ByteIdx] = iDelay;
+                        u1DVS_first_flag[u1ByteIdx] = 1;
+
+                        mcSHOW_DBG_MSG2(("Byte%d find first pass delay\n"))
+                    }
+                    else if (((u1lead_lag == 1) || (((u4err_value >> (u1ByteIdx<<3)) & 0xff) != 0)) && (u1DVS_first_flag[u1ByteIdx] == 1) && (u1finish_flag[u1ByteIdx] == 0))
+                    {
+                        u1DVS_pass_window[u1ByteIdx] = iDelay - u1DVS_first_pass[u1ByteIdx] - u16DelayStep;
+
+                        if (u1DVS_pass_window[u1ByteIdx] < 7) //if window size bigger than 7, consider as real pass window.
+                        {
+                            u1DVS_pass_window[u1ByteIdx] = 0;
+                            u1DVS_first_flag[u1ByteIdx] = 0;
+                            mcSHOW_DBG_MSG2(("Byte%d find fake window\n"))
+                        }
+                        else
+                        {
+                             u1finish_flag[u1ByteIdx] = 1;
+                             mcSHOW_DBG_MSG2(("Byte%d find pass window\n"))
+                        }
+                    }
+                }
+
+                if ((u1finish_flag[0]==1) && (u1finish_flag[1]==1))
+                {
+                    mcSHOW_DBG_MSG2(("Two byte DVS window find, early break!\n"));
+                    break;
+                }
+            }
+        }
+    }
+
+    DramcEngine2End(p);
+
+    for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+    {
+        u1DVS_increase[p->rank][u1ByteIdx] = (u1DVS_pass_window[u1ByteIdx] > 8)? ((u1DVS_pass_window[u1ByteIdx] - 8) >> 3): 0;
+        mcSHOW_DBG_MSG(("\nByte %d final DVS window size(M) %d, DVS increase %d\n", u1ByteIdx, u1DVS_pass_window[u1ByteIdx], u1DVS_increase[p->rank][u1ByteIdx]));
+    }
+
+    DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+
+    vAutoRefreshSwitch(p, ENABLE);
+
+    DramPhyReset(p);
+
+    vPrintCalibrationBasicInfo(p);
+
+    mcSHOW_DBG_MSG(("\n\n"));
+    mcSHOW_DBG_MSG4(("[DramcRxDVSWindowCal] Done\n"));
+
+return DRAM_OK;
+}
+
+void DramcDramcRxDVSCalPostProcess(DRAMC_CTX_T *p)
+{
+    U8 rank_i, u1ByteIdx, u1DVS_increase_final, u1DVS_dly_final[DQS_BYTE_NUMBER]={0};
+    U8 backup_rank = p->rank;
+
+    for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+    {
+        if (p->support_rank_num == RANK_DUAL)
+            u1DVS_increase_final = (u1DVS_increase[RANK_0][u1ByteIdx] < u1DVS_increase[RANK_1][u1ByteIdx])? u1DVS_increase[RANK_0][u1ByteIdx] : u1DVS_increase[RANK_1][u1ByteIdx];
+        else
+            u1DVS_increase_final = u1DVS_increase[p->rank][u1ByteIdx];
+
+        if (u1ByteIdx == 0)
+        {
+            u1DVS_dly_final[u1ByteIdx] = u1DVS_increase_final + (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0));
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0);
+        }
+        else //byte1
+        {
+            u1DVS_dly_final[u1ByteIdx] = u1DVS_increase_final + (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1));
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1);
+        }
+        mcSHOW_DBG_MSG(("Byte%d final DVS delay: %d\n", u1ByteIdx, u1DVS_dly_final[u1ByteIdx]));
+    }
+
+    for(rank_i=RANK_0; rank_i< p->support_rank_num; rank_i++)
+    {
+        vSetRank(p, rank_i);
+        DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, DVS_CAL_KEEP_VREF, AUTOK_OFF, NORMAL_K);
+    }
+
+    if ((DramcRxDVSCal(p, 0) == 1) || (DramcRxDVSCal(p, 1) == 1)) //Prevent set wrong DV dly
+    {
+        mcSHOW_ERR_MSG(("Final DVS delay is out of RX window\n"));
+        for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+        {
+            if (u1DVS_dly_final[u1ByteIdx] > 0)
+            {
+                u1DVS_dly_final[u1ByteIdx] -= 1;
+                if (u1ByteIdx == 0)
+                {
+                    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0);
+                }
+                else //byte1
+                {
+                    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1);
+                }
+            }
+            for(rank_i=RANK_0; rank_i< p->support_rank_num; rank_i++)
+            {
+                vSetRank(p, rank_i);
+                DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, DVS_CAL_KEEP_VREF, AUTOK_OFF, NORMAL_K);
+            }
+        }
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), 1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), 1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1);
+
+    vSetRank(p, backup_rank);
+}
+#endif
+
+#if SIMULATION_DATLAT
+static void dle_factor_handler(DRAMC_CTX_T *p, U8 curr_val)
+{
+    U8 u1DATLAT_DSEL = 0;
+    U8 u1DLECG_OptionEXT1 = 0;
+    U8 u1DLECG_OptionEXT2 = 0;
+    U8 u1DLECG_OptionEXT3 = 0;
+
+    // If (RX_PIPE_BYPASS_ENABLE == 1) bypass RX PIPE, so RG_DATLAT_DSEL = RG_DATLAT
+    // else RG_DATLAT_DSEL = RG_DATLAT - 1
+    if (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL), SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN))
+    {
+        u1DATLAT_DSEL = curr_val;
+    }
+    else
+    {
+        if (curr_val < 1)
+            u1DATLAT_DSEL = curr_val;
+        else
+            u1DATLAT_DSEL = curr_val - 1;
+    }
+
+//    mcSHOW_DBG_MSG(("DATLAT: %d, u1DATLAT_DSEL: %d\n", curr_val, u1DATLAT_DSEL));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT),
+            P_Fld(curr_val, MISC_SHU_RDAT_DATLAT) |
+            P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL) |
+            P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
+
+    // Had been adjusted for 868 already.
+    //(>=8 & <14) set EXT1 =1, EXT2=0, EXT3=0
+    //(>= 14 & <19) set EXT1=1, EXT2=1, EXT3=0
+    //(>=19) set EXT1=1, EXT2=1, EXT3=1
+    u1DLECG_OptionEXT1 = (curr_val >= 8)? (1): (0);
+    u1DLECG_OptionEXT2 = (curr_val >= 14)? (1): (0);
+    u1DLECG_OptionEXT3 = (curr_val >= 19)? (1): (0);
+//    mcSHOW_DBG_MSG(("u1DLECG_OptionEXT1: %d, 2 for %d, 3 for %d\n", u1DLECG_OptionEXT1, u1DLECG_OptionEXT2, u1DLECG_OptionEXT3));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_RX_CG_SET0),
+            P_Fld(u1DLECG_OptionEXT1, SHU_RX_CG_SET0_READ_START_EXTEND1) |
+            P_Fld(u1DLECG_OptionEXT1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
+            P_Fld((u1DLECG_OptionEXT2), SHU_RX_CG_SET0_READ_START_EXTEND2) |
+            P_Fld((u1DLECG_OptionEXT2), SHU_RX_CG_SET0_DLE_LAST_EXTEND2) |
+            P_Fld((u1DLECG_OptionEXT3), SHU_RX_CG_SET0_READ_START_EXTEND3) |
+            P_Fld((u1DLECG_OptionEXT3), SHU_RX_CG_SET0_DLE_LAST_EXTEND3));
+
+    DramPhyReset(p);
+
+}
+
+static U8 aru1RxDatlatResult[RANK_MAX];
+DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p)
+{
+    //U8 ii, ucStartCalVal = 0;
+    U32 u4prv_register_080;
+    //U32 u4err_value = 0xffffffff;
+    U8 ucfirst, ucbegin, ucsum, ucbest_step; //ucpipe_num = 0;
+    U16 u2DatlatBegin;
+
+    // error handling
+    if (!p)
+    {
+        mcSHOW_ERR_MSG(("context NULL\n"));
+        return DRAM_FAIL;
+    }
+
+    //mcDUMP_REG_MSG(("\n[dumpRG] DramcRxdatlatCal\n"));
+    #if VENDER_JV_LOG
+    vPrintCalibrationBasicInfo_ForJV(p);
+    #else
+    vPrintCalibrationBasicInfo(p);
+    #endif
+    mcSHOW_DBG_MSG(("[RxdatlatCal]\n"));
+
+    // pre-save
+    // 0x07c[6:4]   DATLAT bit2-bit0
+    u4prv_register_080 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT));
+
+    //default set FAIL
+    vSetCalibrationResult(p, DRAM_CALIBRATION_DATLAT, DRAM_FAIL);
+
+    // init best_step to default
+    ucbest_step = (U8) u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT), MISC_SHU_RDAT_DATLAT);
+    mcSHOW_DBG_MSG2(("DATLAT Default: 0x%x\n", ucbest_step));
+    //mcDUMP_REG_MSG(("DATLAT Default: 0x%x\n", ucbest_step));
+
+    // 1.set DATLAT 0-15 (0-21 for MT6595)
+    // 2.enable engine1 or engine2
+    // 3.check result  ,3~4 taps pass
+    // 4.set DATLAT 2nd value for optimal
+
+    // Initialize
+    ucfirst = 0xff;
+    ucbegin = 0;
+    ucsum = 0;
+
+    DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//UI_SHIFT + LEN1
+    u2DatlatBegin = 0;
+
+#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_DATLAT)
+    if (p->femmc_Ready == 1)
+    {
+        ucbest_step = p->pSavetimeData->u1RxDatlat_Save[p->channel][p->rank];
+    }
+#endif
+
+    aru1RxDatlatResult[p->rank] = ucbest_step;
+
+    mcSHOW_DBG_MSG(("best_step = %d\n\n", ucbest_step));
+    //mcDUMP_REG_MSG(("best_step=%d\n\n", ucbest_step));
+
+#if __A60868_TO_BE_PORTING__
+#if __ETT__
+    U8 _init_Datlat_value = vDramcACTimingGetDatLat(p);
+    if ((_init_Datlat_value > (ucbest_step + 1)) || (_init_Datlat_value < (ucbest_step - 1)))
+    {
+        mcSHOW_DBG_MSG(("[WARNING!!] Datlat initial value(%d) = best_step(%d) %c %d, out of range!\n\n",
+                           _init_Datlat_value,
+                           ucbest_step,
+                           (ucbest_step > _init_Datlat_value)? '-': '+',
+                           abs(ucbest_step - _init_Datlat_value)));
+        while (1);
+    }
+#endif
+#endif
+#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_DATLAT)
+    if (p->femmc_Ready == 1)
+    {
+        dle_factor_handler(p, ucbest_step);
+        vSetCalibrationResult(p, DRAM_CALIBRATION_DATLAT, DRAM_FAST_K);
+    }
+#endif
+
+    mcSHOW_DBG_MSG4(("[DramcRxdatlatCal] Done\n"));
+    return DRAM_OK;
+
+}
+
+DRAM_STATUS_T DramcDualRankRxdatlatCal(DRAMC_CTX_T *p)
+{
+    U8 u1FinalDatlat, u1Datlat0, u1Datlat1;
+
+    u1Datlat0 = aru1RxDatlatResult[0];
+    u1Datlat1 = aru1RxDatlatResult[1];
+
+    if (p->support_rank_num == RANK_DUAL)
+    {
+        if (u1Datlat0 > u1Datlat1)
+        {
+            u1FinalDatlat = u1Datlat0;
+        }
+        else
+        {
+            u1FinalDatlat = u1Datlat1;
+        }
+    }
+    else
+    {
+        u1FinalDatlat = u1Datlat0;
+    }
+
+#if ENABLE_READ_DBI
+    if (p->DBI_R_onoff[p->dram_fsp])
+    {
+      u1FinalDatlat++;
+    }
+#endif
+
+    dle_factor_handler(p, u1FinalDatlat);
+
+#if RDSEL_TRACKING_EN
+    if(p->frequency >= RDSEL_TRACKING_TH)
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RDSEL_TRACK), u1FinalDatlat, SHU_MISC_RDSEL_TRACK_DMDATLAT_I);
+    }
+#endif
+
+    mcSHOW_DBG_MSG(("[DualRankRxdatlatCal] RK0: %d, RK1: %d, Final_Datlat %d\n", u1Datlat0, u1Datlat1, u1FinalDatlat));
+    //mcDUMP_REG_MSG(("[DualRankRxdatlatCal] RK0: %d, RK1: %d, Final_Datlat %d\n", u1Datlat0, u1Datlat1, u1FinalDatlat));
+
+
+#if defined(FOR_HQA_TEST_USED) && defined(FOR_HQA_REPORT_USED)
+    {   U8 backup_rank, rank_index;
+
+        backup_rank = u1GetRank(p);
+        for(rank_index = RANK_0; rank_index < p->support_rank_num; rank_index++)
+        {
+            vSetRank(p, rank_index);
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, "DATLAT", "", 0, u1FinalDatlat, NULL);
+        }
+        vSetRank(p, backup_rank);
+    }
+#endif
+
+    return DRAM_OK;
+
+}
+#endif // SIMULATION_DATLAT
+
+#if SIMULATION_TX_PERBIT
+
+//=============================================================
+///// DramC TX perbi calibration ----------Begin--------------
+//=============================================================
+//-------------------------------------------------------------------------
+/** DramcTxWindowPerbitCal (v2)
+ *  TX DQS per bit SW calibration.
+ *  @param p                Pointer of context created by DramcCtxCreate.
+ *  @param  apply           (U8): 0 don't apply the register we set  1 apply the register we set ,default don't apply.
+ *  @retval status          (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL
+ */
+//-------------------------------------------------------------------------
+#if (SW_CHANGE_FOR_SIMULATION || FOR_DV_SIMULATION_USED)
+#define TX_VREF_RANGE_BEGIN       0
+#define TX_VREF_RANGE_END           2 // binary 110010
+#define TX_VREF_RANGE_STEP         2
+#else
+#define TX_VREF_RANGE_BEGIN       16
+#define TX_VREF_RANGE_END           50 // binary 110010
+#define TX_VREF_RANGE_STEP         2
+#endif
+
+#define TX_DQ_UI_TO_PI_TAP         64 // 1 PI = tCK/64, total 128 PI, 1UI = 32 PI
+#define TX_PHASE_DQ_UI_TO_PI_TAP         32 // 1 PI = tCK/64, total 128 PI, 1UI = 32 PI for DDR800 semi open loop mode
+#define LP4_TX_VREF_DATA_NUM 50
+#define LP4_TX_VREF_PASS_CONDITION 0
+#define TX_PASS_WIN_CRITERIA    7
+#define LP4_TX_VREF_BOUNDARY_NOT_READY 0xff
+
+typedef struct _PASS_WIN_DATA_BY_VREF_T
+{
+    U16 u2VrefUsed;
+    U16 u2WinSum_byVref;
+    U8 u1WorseBitWinSize_byVref;
+    U8 u1WorseBitIdx_byVref;
+} PASS_WIN_DATA_BY_VREF_T;
+
+#if 0
+static U16 WDQSMode2AcTxOEShift(DRAMC_CTX_T *p)
+{
+    U16 u2TxDQOEShift = 0;
+
+    switch (p->frequency)
+    {
+        case 1866:
+            u2TxDQOEShift = 19;
+            break;
+        case 1600:
+        case 1200:
+        case 800:
+        case 600:
+            u2TxDQOEShift = 15;
+            break;
+        case 933:
+            u2TxDQOEShift = 11;
+            break;
+        case 400:
+            u2TxDQOEShift = 16;
+            break;
+        default:
+            mcSHOW_ERR_MSG(("[WDQSMode2AcTxOEShift] frequency err!\n"));
+            #if __ETT__
+            while (1);
+            #endif
+    }
+
+    return u2TxDQOEShift;
+}
+#endif
+void TxWinTransferDelayToUIPI(DRAMC_CTX_T *p, U16 uiDelay, U8 u1AdjustPIToCenter, U8* pu1UILarge_DQ, U8* pu1UISmall_DQ, U8* pu1PI, U8* pu1UILarge_DQOE, U8* pu1UISmall_DQOE)
+{
+    U8 u1Small_ui_to_large, u1PI = 0, u164PIto1UI, u1TxDQOEShift = 0;
+    U16 u2TmpValue, u2DQOE_shift;
+    DDR800_MODE_T eDdr800Mode = vGet_DDR_Loop_Mode(p);
+    U8 u1PiTap = (u1IsPhaseMode(p) == TRUE) ? TX_PHASE_DQ_UI_TO_PI_TAP : TX_DQ_UI_TO_PI_TAP;
+
+    u1Small_ui_to_large = u1MCK2UI_DivShift(p);
+
+    #if ENABLE_WDQS_MODE_2
+    u1TxDQOEShift = WDQSMode2AcTxOEShift(p);
+    #else
+    u1TxDQOEShift = TX_DQ_OE_SHIFT_LP4;
+    #endif
+
+    if(pu1PI != NULL)
+    {
+        u1PI = uiDelay & (u1PiTap-1);
+        *pu1PI =u1PI;
+    }
+
+    if (u1IsLP4Div4DDR800(p) /*DDR800 close loop mode*/ || u1IsPhaseMode(p))
+        u164PIto1UI = 0;
+    else
+        u164PIto1UI = 1;
+
+    u2TmpValue = (uiDelay /u1PiTap)<<u164PIto1UI; // 1:8 mode for 2UI carry, DDR800 1:4 mode for 1UI carry
+
+    if (u1AdjustPIToCenter && (pu1PI != NULL) && (eDdr800Mode == CLOSE_LOOP_MODE))
+    {
+        if (u1PI < 10)
+        {
+            u1PI += (u1PiTap) >> 1;
+            u2TmpValue --;
+        }
+        else if (u1PI > u1PiTap - 10)
+        {
+            u1PI -= (u1PiTap) >> 1;
+            u2TmpValue ++;
+        }
+
+        *pu1PI = u1PI;
+    }
+
+    #if 0
+    *pu1UISmall_DQ = u2TmpValue % u1Small_ui_to_large;
+    *pu1UILarge_DQ = u2TmpValue / u1Small_ui_to_large;
+    #else
+    *pu1UISmall_DQ = u2TmpValue - ((u2TmpValue >> u1Small_ui_to_large) << u1Small_ui_to_large);
+    *pu1UILarge_DQ = (u2TmpValue >> u1Small_ui_to_large);
+    #endif
+    // calculate DQ OE according to DQ UI
+    #if (__LP5_COMBO__ == TRUE)
+    if (TRUE == is_lp5_family(p))
+    {
+        u2TmpValue -= TX_DQ_OE_SHIFT_LP5;
+    }
+    else
+    #endif
+    {
+        u2TmpValue -= u1TxDQOEShift;
+    }
+
+    if(((u1MR03Value[p->dram_fsp]&0x80)>>7)==1) //if WDBI is on, OE_DLY don't need to shift 1 MCK with DLY
+    {
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+            u2DQOE_shift = 4; //OE_shift = OE_shift - 3(original OE position) + 4 (MCK)
+        else
+            u2DQOE_shift = 8; //OE_shift = OE_shift - 3(original OE position) + 8 (MCK)
+
+        u2TmpValue += u2DQOE_shift;
+    }
+
+    *pu1UISmall_DQOE = u2TmpValue - ((u2TmpValue >> u1Small_ui_to_large) << u1Small_ui_to_large);
+    *pu1UILarge_DQOE = (u2TmpValue >> u1Small_ui_to_large);
+}
+
+#if 0
+static void TxPrintWidnowInfo(DRAMC_CTX_T *p, PASS_WIN_DATA_T WinPerBitData[])
+{
+    U8 u1BitIdx;
+
+    for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx++)
+    {
+    #ifdef ETT_PRINT_FORMAT
+        mcSHOW_DBG_MSG(("TX Bit%d (%d~%d) %d %d,   Bit%d (%d~%d) %d %d,", \
+            u1BitIdx, WinPerBitData[u1BitIdx].first_pass, WinPerBitData[u1BitIdx].last_pass, WinPerBitData[u1BitIdx].win_size, WinPerBitData[u1BitIdx].win_center, \
+            u1BitIdx + 8, WinPerBitData[u1BitIdx + 8].first_pass, WinPerBitData[u1BitIdx + 8].last_pass, WinPerBitData[u1BitIdx + 8].win_size, WinPerBitData[u1BitIdx + 8].win_center));
+    #else
+        mcSHOW_DBG_MSG(("TX Bit%2d (%2d~%2d) %2d %2d,   Bit%2d (%2d~%2d) %2d %2d,", \
+            u1BitIdx, WinPerBitData[u1BitIdx].first_pass, WinPerBitData[u1BitIdx].last_pass, WinPerBitData[u1BitIdx].win_size, WinPerBitData[u1BitIdx].win_center, \
+            u1BitIdx + 8, WinPerBitData[u1BitIdx + 8].first_pass, WinPerBitData[u1BitIdx + 8].last_pass, WinPerBitData[u1BitIdx + 8].win_size, WinPerBitData[u1BitIdx + 8].win_center));
+    #endif
+    #if PIN_CHECK_TOOL
+            PINInfo_flashtool.DQ_TX_WIN_SIZE[p->channel][p->rank][u1BitIdx] = WinPerBitData[u1BitIdx].win_size;
+            PINInfo_flashtool.DQ_TX_WIN_SIZE[p->channel][p->rank][u1BitIdx+8] = WinPerBitData[u1BitIdx+8].win_size;
+    #endif
+        mcSHOW_DBG_MSG(("\n"));
+    }
+    mcSHOW_DBG_MSG(("\n"));
+#if DUMP_TA2_WINDOW_SIZE_RX_TX
+    {
+        U32 u4B0Tatal=0;
+        U32 u4B1Tatal=0;
+        for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
+        {
+            if(u1BitIdx < 8)
+            {
+                u4B0Tatal += WinPerBitData[u1BitIdx].win_size;
+            }
+            else
+            {
+                u4B1Tatal += WinPerBitData[u1BitIdx].win_size;
+            }
+        }
+        mcSHOW_DBG_MSG(("\ntotal tx window size B0: %d B1: %d\n", u4B0Tatal, u4B1Tatal));
+    }
+#endif
+}
+#endif
+
+static void TXPerbitCalibrationInit(DRAMC_CTX_T *p, U8 calType)
+{
+    //Set TX delay chain to 0
+    if (calType != TX_DQ_DQS_MOVE_DQM_ONLY)
+    {
+    #if 1
+    #if PINMUX_AUTO_TEST_PER_BIT_TX
+        if(gTX_check_per_bit_flag == 1)
+        {
+            //not reset delay cell
+        }
+        else
+    #endif
+        {
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), 0);
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), 0);
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), 0);
+            vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1), 0);
+        }
+    #else
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU_R0_B0_DQ0), P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ7_DLY_B0)
+            | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ6_DLY_B0)
+            | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ5_DLY_B0)
+            | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ4_DLY_B0)
+            | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ3_DLY_B0)
+            | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ2_DLY_B0)
+            | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ1_DLY_B0)
+            | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ0_DLY_B0));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU_R0_B1_DQ0), P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ7_DLY_B1)
+            | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ6_DLY_B1)
+            | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ5_DLY_B1)
+            | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ4_DLY_B1)
+            | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ3_DLY_B1)
+            | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ2_DLY_B1)
+            | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ1_DLY_B1)
+            | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ0_DLY_B1));
+    #endif
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), 0x0, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), 0x0, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1);
+    }
+
+
+    //Use HW TX tracking value
+    //R_DMARPIDQ_SW :drphy_conf (0x170[7])(default set 1)
+    //   0: DQS2DQ PI setting controlled by HW
+    //R_DMARUIDQ_SW : Dramc_conf(0x156[15])(default set 1)
+    //    0: DQS2DQ UI setting controlled by HW
+    ///TODO: need backup original setting?
+    //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_MISC_CTRL1), 1, MISC_CTRL1_R_DMARPIDQ_SW);
+    //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_ARUIDQ_SW);
+
+}
+
+#define TX_TDQS2DQ_PRE_CAL 0
+#if TX_TDQS2DQ_PRE_CAL
+//  (1) DDR800 1:4 mode
+//  (2) DDR1200/1600 1:4 mode
+//  (3) 1:8 mode
+// The 3 condition have different MCK2UI/UI2PI. Therefore, TX DQS2DQ should be record separately.
+// Here, we record (2) and (3).  DDR800 1:4 skip recording DQS2DQ.
+U16 u2DQS2DQ_Pre_Cal[CHANNEL_NUM][RANK_MAX][2/*DIV_Mode*/] = {0};
+#endif
+
+static void TXScanRange_PI(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U16 *pu2Begin, U16 *pu2End)
+{
+    U8 u1MCK2UI, u1UI2PI, u1ByteIdx;
+    U32 u4RegValue_TXDLY, u4RegValue_dly;
+    U8 ucdq_ui_large_bak[DQS_BYTE_NUMBER], ucdq_ui_small_bak[DQS_BYTE_NUMBER];
+    U16 u2TempVirtualDelay, u2SmallestVirtualDelay = 0xffff;
+    U16 u2DQDelayBegin = 0, u2DQDelayEnd = 0;
+
+#if (__LP5_COMBO__ == TRUE)
+    if (TRUE == is_lp5_family(p))
+    {
+        u4RegValue_TXDLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_WR_MCK));
+        u4RegValue_dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_WR_UI));
+    }
+    else
+#endif
+    {
+        u4RegValue_TXDLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0));
+        u4RegValue_dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1));
+    }
+
+    u1MCK2UI = u1MCK2UI_DivShift(p);
+
+    if (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP)
+        u1UI2PI = 6;
+    else
+        u1UI2PI = 5;
+
+
+    // find smallest DQS delay
+    for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+    {
+        ucdq_ui_large_bak[u1ByteIdx] = (u4RegValue_TXDLY >> (u1ByteIdx << 2)) & 0x7;// MCK
+        ucdq_ui_small_bak[u1ByteIdx] = (u4RegValue_dly >> (u1ByteIdx << 2)) & 0x7;// UI
+        //wrlevel_dqs_final_delay[p->rank][u1ByteIdx]  ==> PI
+
+        //LP4 : Virtual Delay = 256 * MCK + 32*UI + PI;
+        //LP3 : Virtual Delay = 128 * MCK + 32*UI + PI;
+        u2TempVirtualDelay = (((ucdq_ui_large_bak[u1ByteIdx] << u1MCK2UI) + ucdq_ui_small_bak[u1ByteIdx]) << u1UI2PI) + wrlevel_dqs_final_delay[p->rank][u1ByteIdx];
+
+        if (u2TempVirtualDelay < u2SmallestVirtualDelay)
+        {
+            u2SmallestVirtualDelay = u2TempVirtualDelay;
+        }
+
+        //mcSHOW_DBG_MSG2(("Original DQS_B%d VirtualDelay %d = (%d %d %d)\n", u1ByteIdx, u2TempVirtualDelay,
+        //                ucdq_ui_large_bak[u1ByteIdx], ucdq_ui_small_bak[u1ByteIdx], wrlevel_dqs_final_delay[p->rank][u1ByteIdx]));
+    }
+
+    u2DQDelayBegin = u2SmallestVirtualDelay;
+
+    #if TX_TDQS2DQ_PRE_CAL
+    if (u1IsLP4Div4DDR800(p) == FALSE)
+    {
+        if (u2DQS2DQ_Pre_Cal[p->channel][p->rank][vGet_Div_Mode(p)] > 0)
+        {
+            U16 u2TmpShift;
+            mcSHOW_DBG_MSG(("TX_TDQS2DQ_PRE_CAL : change DQ begin %d -->", u2DQDelayBegin));
+
+            u2TmpShift = (u2DQS2DQ_Pre_Cal[p->channel][p->rank][vGet_Div_Mode(p)]* p->frequency) / 1000;
+            if (u2TmpShift >= 15)
+                u2TmpShift -= 15;
+            else
+                u2TmpShift = 0;
+
+            u2DQDelayBegin += u2TmpShift;
+            mcSHOW_DBG_MSG(("%d (+%d)\n", u2DQDelayBegin, u2TmpShift));
+        }
+    }
+    #endif
+
+    #if (__LP5_COMBO__)
+    if (is_lp5_family(p)) {
+        /* For DDR3200, +1.5 MCK */
+        if (p->frequency == 1600)
+            u2DQDelayBegin += (((1 << u1MCK2UI) + ((1 << u1MCK2UI) >> 1)) << u1UI2PI);
+        else if (p->frequency == 2133)
+            u2DQDelayBegin += ((1 << u1MCK2UI) << u1UI2PI);
+        else if (p->frequency == 2750)
+            u2DQDelayBegin += (9 << u1UI2PI);
+    }
+    #endif
+
+    #if TX_K_DQM_WITH_WDBI
+    if (calType == TX_DQ_DQS_MOVE_DQM_ONLY)
+    {
+        // DBI on, calibration range -1MCK
+        u2DQDelayBegin -= (1 << (u1MCK2UI + 5));
+    }
+    #endif
+    /* Scan range: 1MCK */
+    u2DQDelayEnd = u2DQDelayBegin + ((1 << u1MCK2UI) << u1UI2PI);
+
+    *pu2Begin = u2DQDelayBegin;
+    *pu2End = u2DQDelayEnd;
+
+    #if 0//TX_TDQS2DQ_PRE_CAL
+    mcSHOW_DBG_MSG(("TXScanRange_PI %d~%d\n", u2DQDelayBegin, u2DQDelayEnd));
+    #endif
+}
+
+
+static void TXScanRange_Vref(DRAMC_CTX_T *p, U8 u1VrefScanEnable, U16* pu2Range, U16 *pu2Begin, U16 *pu2End, U16 *pu2Setp)
+{
+	U16 u2VrefBegin = 0, u2VrefEnd = 0;
+
+    if (u1VrefScanEnable)
+    {
+    #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_VREF_CAL)
+        if (p->femmc_Ready == 1)
+        {
+            // if fast K, use TX Vref that saved.
+            u2VrefBegin = p->pSavetimeData->u1TxWindowPerbitVref_Save[p->channel][p->rank];
+            u2VrefEnd = u2VrefBegin + 1;
+        }
+    #endif
+    }
+    else //LPDDR3, the for loop will only excute u2VrefLevel=TX_VREF_RANGE_END/2.
+    {
+        u2VrefBegin = 0;
+        u2VrefEnd = 0;
+    }
+
+    *pu2Range = (!p->odt_onoff);
+    *pu2Begin = u2VrefBegin;
+    *pu2End = u2VrefEnd;
+    *pu2Setp = TX_VREF_RANGE_STEP;
+
+}
+
+static U16 TxChooseVref(DRAMC_CTX_T *p, PASS_WIN_DATA_BY_VREF_T pVrefInfo[], U8 u1VrefNum)
+{
+    U8 u1VrefIdx, u1WorseBitIdx = 0, u1WinSizeOfWorseBit = 0;
+    //U8 u1VrefPassBegin = LP4_TX_VREF_BOUNDARY_NOT_READY, u1VrefPassEnd = LP4_TX_VREF_BOUNDARY_NOT_READY, u1TempPassNum = 0, u1MaxVerfPassNum = 0;
+    //U8 u1VrefPassBegin_Final = LP4_TX_VREF_BOUNDARY_NOT_READY, u1VrefPassEnd_Final = LP4_TX_VREF_BOUNDARY_NOT_READY;
+    U16 u2MaxWinSum = 0;
+    U16 u2FinalVref = 0;
+
+    for (u1VrefIdx = 0; u1VrefIdx < u1VrefNum; u1VrefIdx++)
+    {
+        mcSHOW_DBG_MSG2(("TX Vref=%d, minBit %d, minWin=%d, winSum=%d\n",
+            pVrefInfo[u1VrefIdx].u2VrefUsed,
+            pVrefInfo[u1VrefIdx].u1WorseBitIdx_byVref,
+            pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref,
+            pVrefInfo[u1VrefIdx].u2WinSum_byVref));
+
+        #if LP4_TX_VREF_PASS_CONDITION
+        if ((pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref > LP4_TX_VREF_PASS_CONDITION))
+        {
+            if (u1VrefPassBegin == LP4_TX_VREF_BOUNDARY_NOT_READY)
+            {
+                u1VrefPassBegin = pVrefInfo[u1VrefIdx].u2VrefUsed;
+                u1TempPassNum = 1;
+            }
+            else
+                u1TempPassNum ++;
+
+            if (u1VrefIdx == u1VrefNum - 1)
+            {
+                u1VrefPassEnd = pVrefInfo[u1VrefIdx].u2VrefUsed;
+                if (u1TempPassNum > u1MaxVerfPassNum)
+                {
+                    u1VrefPassBegin_Final = u1VrefPassBegin;
+                    u1VrefPassEnd_Final = u1VrefPassEnd;
+                    u1MaxVerfPassNum = u1TempPassNum;
+                }
+            }
+        }
+        else
+        {
+            if ((u1VrefPassBegin != LP4_TX_VREF_BOUNDARY_NOT_READY) && (u1VrefPassEnd == LP4_TX_VREF_BOUNDARY_NOT_READY))
+            {
+                u1VrefPassEnd = pVrefInfo[u1VrefIdx].u2VrefUsed - TX_VREF_RANGE_STEP;
+                if (u1TempPassNum > u1MaxVerfPassNum)
+                {
+                    u1VrefPassBegin_Final = u1VrefPassBegin;
+                    u1VrefPassEnd_Final = u1VrefPassEnd;
+                    u1MaxVerfPassNum = u1TempPassNum;
+                }
+                u1VrefPassBegin = 0xff;
+                u1VrefPassEnd = 0xff;
+                u1TempPassNum = 0;
+            }
+        }
+        #endif
+    }
+
+    #if LP4_TX_VREF_PASS_CONDITION
+    //if((u1VrefPassBegin_Final !=LP4_TX_VREF_BOUNDARY_NOT_READY) && (u1VrefPassEnd_Final!=LP4_TX_VREF_BOUNDARY_NOT_READY))
+    if (u1MaxVerfPassNum > 0)
+    {
+        // vref pass window found
+        u2FinalVref = (u1VrefPassBegin_Final + u1VrefPassEnd_Final) >> 1;
+        mcSHOW_DBG_MSG(("[TxChooseVref] Window > %d, Vref (%d~%d), Final Vref %d\n", LP4_TX_VREF_PASS_CONDITION, u1VrefPassBegin_Final, u1VrefPassEnd_Final, u2FinalVref));
+    }
+    else
+    #endif
+    {
+        // not vref found
+        for (u1VrefIdx = 0; u1VrefIdx < u1VrefNum; u1VrefIdx++)
+        {
+            if ((pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref > u1WinSizeOfWorseBit) ||
+                ((pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref == u1WinSizeOfWorseBit) && (pVrefInfo[u1VrefIdx].u2WinSum_byVref > u2MaxWinSum)))
+            {
+                u1WinSizeOfWorseBit = pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref;
+                u1WorseBitIdx = pVrefInfo[u1VrefIdx].u1WorseBitIdx_byVref;
+                u2MaxWinSum = pVrefInfo[u1VrefIdx].u2WinSum_byVref;
+                u2FinalVref = pVrefInfo[u1VrefIdx].u2VrefUsed;
+            }
+        }
+
+        mcSHOW_DBG_MSG(("[TxChooseVref] Worse bit %d, Min win %d, Win sum %d, Final Vref %d\n", u1WorseBitIdx, u1WinSizeOfWorseBit, u2MaxWinSum, u2FinalVref));
+        //mcDUMP_REG_MSG(("[TxChooseVref] Worse bit %d, Min win %d, Win sum %d, Final Vref %d\n", u1WorseBitIdx, u1WinSizeOfWorseBit, u2MaxWinSum, u2FinalVref));
+    }
+
+    return u2FinalVref;
+}
+
+
+static void DramcTXSetVref(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefValue)
+{
+    U8 u1TempOPValue;
+
+#ifdef __LP5_COMBO__
+    if (is_lp5_family(p))
+        u1TempOPValue = ((u1VrefValue & 0x7f));
+    else
+#endif
+        u1TempOPValue = ((u1VrefValue & 0x3f) | (u1VrefRange << 6));
+
+    u1MR14Value[p->channel][p->rank][p->dram_fsp] = u1TempOPValue;
+    //For TX VREF of different byte
+
+    DramcModeRegWriteByRank(p, p->rank, 14, u1TempOPValue);
+#ifdef __LP5_COMBO__
+    if (is_lp5_family(p))
+        DramcModeRegWriteByRank(p, p->rank, 15, u1TempOPValue);
+#endif
+
+    #if CALIBRATION_SPEED_UP_DEBUG
+    mcSHOW_DBG_MSG2(("Yulia TX Vref : CH%d Rank%d, TX Range %d Vref %d\n\n", p->channel, p->rank, u1VrefRange, (u1VrefValue & 0x3f)));
+    #endif
+}
+
+
+static void TXSetFinalVref(DRAMC_CTX_T *p, U16 u2FinalRange, U16 u2FinalVref)
+{
+    DramcTXSetVref(p, u2FinalRange, u2FinalVref);
+
+#ifdef FOR_HQA_TEST_USED
+    gFinalTXVrefDQ[p->channel][p->rank] = (U8) u2FinalVref;
+#endif
+
+#if VENDER_JV_LOG
+    mcSHOW_DBG_MSG5(("\nFinal TX Range %d Vref %d\n\n", u2FinalRange, u2FinalVref));
+#else
+    mcSHOW_DBG_MSG(("\nFinal TX Range %d Vref %d\n\n", u2FinalRange, u2FinalVref));
+#endif
+
+    #if CALIBRATION_SPEED_UP_DEBUG
+    mcSHOW_DBG_MSG2(("Yulia TX Vref Final: CH%d Rank%d, TX Range %d Vref %d\n\n", p->channel, p->rank, u2FinalRange, u2FinalVref));
+    #endif
+}
+
+
+#if ENABLE_TX_TRACKING
+#if !BYPASS_CALIBRATION
+static
+#endif
+void TXUpdateTXTracking(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 ucdq_pi[], U8 ucdqm_pi[])
+{
+     if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQM_ONLY)
+     {
+         //make a copy to dramc reg for TX DQ tracking used
+         if (calType == TX_DQ_DQS_MOVE_DQ_ONLY)
+         {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI),
+                            P_Fld(ucdq_pi[0], SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(ucdq_pi[1], SHURK_PI_RK0_ARPI_DQ_B1));
+
+            // Source DQ
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL1),
+                                                    P_Fld(ucdq_pi[1], SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1) |
+                                                    P_Fld(ucdq_pi[0], SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0));
+            // Target DQ
+             vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL2),
+                                                     P_Fld(ucdq_pi[1], SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1) |
+                                                     P_Fld(ucdq_pi[0], SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0));
+         }
+
+         //if(calType ==TX_DQ_DQS_MOVE_DQM_ONLY || (calType ==TX_DQ_DQS_MOVE_DQ_ONLY))
+         {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI),
+                            P_Fld(ucdqm_pi[0], SHURK_PI_RK0_ARPI_DQM_B0) | P_Fld(ucdqm_pi[1], SHURK_PI_RK0_ARPI_DQM_B1));
+
+            // Target DQM
+             vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL5),
+                                                 P_Fld(ucdqm_pi[1], SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1) |
+                                                 P_Fld(ucdqm_pi[0], SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0));
+         }
+     }
+
+
+#if 0// for LP3 , TX tracking will be disable, don't need to set DQ delay in DramC.
+     ///TODO: check LP3 byte mapping of dramC
+     vIO32WriteFldMulti(DRAMC_REG_SHURK0_PI + (CHANNEL_A << POS_BANK_NUM), \
+                              P_Fld(ucdq_final_pi[0], SHURK0_PI_RK0_ARPI_DQ_B0) | P_Fld(ucdq_final_pi[1], SHURK0_PI_RK0_ARPI_DQ_B1));
+
+     vIO32WriteFldMulti(DRAMC_REG_SHURK0_PI + SHIFT_TO_CHB_ADDR, \
+                              P_Fld(ucdq_final_pi[2], SHURK0_PI_RK0_ARPI_DQ_B0) | P_Fld(ucdq_final_pi[3], SHURK0_PI_RK0_ARPI_DQ_B1));
+#endif
+
+}
+#endif //End ENABLE_TX_TRACKING
+
+#if !BYPASS_CALIBRATION
+static
+#endif
+void TXSetDelayReg_DQ(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdq_ui_large[], U8 ucdq_oen_ui_large[], U8 ucdq_ui_small[], U8 ucdq_oen_ui_small[], U8 ucdql_pi[])
+{
+    if (u1UpdateRegUI)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \
+                                     P_Fld(ucdq_ui_large[0], SHURK_SELPH_DQ0_TXDLY_DQ0) |
+                                     P_Fld(ucdq_ui_large[1], SHURK_SELPH_DQ0_TXDLY_DQ1) |
+                                     P_Fld(ucdq_oen_ui_large[0], SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
+                                     P_Fld(ucdq_oen_ui_large[1], SHURK_SELPH_DQ0_TXDLY_OEN_DQ1));
+
+        // DLY_DQ[2:0]
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), \
+                                     P_Fld(ucdq_ui_small[0], SHURK_SELPH_DQ2_DLY_DQ0) |
+                                     P_Fld(ucdq_ui_small[1], SHURK_SELPH_DQ2_DLY_DQ1) |
+                                     P_Fld(ucdq_oen_ui_small[0], SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
+                                     P_Fld(ucdq_oen_ui_small[1], SHURK_SELPH_DQ2_DLY_OEN_DQ1));
+    }
+
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), ucdql_pi[0], SHU_R0_B0_DQ0_SW_ARPI_DQ_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), ucdql_pi[1], SHU_R0_B1_DQ0_SW_ARPI_DQ_B1);
+}
+
+#if !BYPASS_CALIBRATION
+static
+#endif
+void TXSetDelayReg_DQM(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdqm_ui_large[], U8 ucdqm_oen_ui_large[], U8 ucdqm_ui_small[], U8 ucdqm_oen_ui_small[], U8 ucdqm_pi[])
+{
+    if (u1UpdateRegUI)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1),
+                                     P_Fld(ucdqm_ui_large[0], SHURK_SELPH_DQ1_TXDLY_DQM0) |
+                                     P_Fld(ucdqm_ui_large[1], SHURK_SELPH_DQ1_TXDLY_DQM1) |
+                                     P_Fld(ucdqm_oen_ui_large[0], SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
+                                     P_Fld(ucdqm_oen_ui_large[1], SHURK_SELPH_DQ1_TXDLY_OEN_DQM1));
+
+         // DLY_DQM[2:0]
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3),
+                                     P_Fld(ucdqm_ui_small[0], SHURK_SELPH_DQ3_DLY_DQM0) |
+                                     P_Fld(ucdqm_ui_small[1], SHURK_SELPH_DQ3_DLY_DQM1) |
+                                     P_Fld(ucdqm_oen_ui_small[0], SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
+                                     P_Fld(ucdqm_oen_ui_small[1], SHURK_SELPH_DQ3_DLY_OEN_DQM1));
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), ucdqm_pi[0], SHU_R0_B0_DQ0_SW_ARPI_DQM_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), ucdqm_pi[1], SHU_R0_B1_DQ0_SW_ARPI_DQM_B1);
+}
+
+#if TX_AUTO_K_SUPPORT
+static void Tx_Auto_K_Init(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 ucdq_pi, U8 u1PI_Len)
+{
+    u8 pi_thrd = 0xa;
+    //u8 early_break = 0x0;
+
+#if FOR_DV_SIMULATION_USED == 1
+    cal_sv_rand_args_t *psra = get_psra();
+
+    if (psra) {
+        pi_thrd = psra->tx_atk_pass_pi_thrd & 0xFF;
+        early_break = psra->tx_atk_early_break & 0xFF;
+    }
+#endif
+
+#if ENABLE_PA_IMPRO_FOR_TX_AUTOK
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DCM_SUB_CTRL), 0x1, DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_CG_SET0), 0x1, TX_CG_SET0_TX_ATK_CLKRUN);
+#endif
+
+    if (calType == TX_DQ_DQS_MOVE_DQ_DQM)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1),
+                                     P_Fld(0x1, TX_ATK_SET1_TX_ATK_DQ_PI_EN) |    //enable TX DQ auto K
+                                     P_Fld(0x1, TX_ATK_SET1_TX_ATK_DQM_PI_EN));   //enable TX DQM auto K
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET0),
+                                     P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B0_PI_INIT) |    //Set begin position of DQ B0
+                                     P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B1_PI_INIT) |    //Set begin position of DQ B1
+                                     P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQM_B0_PI_INIT) |   //Set begin position of DQM B0
+                                     P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQM_B1_PI_INIT));   //Set begin position of DQM B1
+    }
+    else if (calType == TX_DQ_DQS_MOVE_DQM_ONLY)
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_DQM_PI_EN);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET0),
+                                     P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQM_B0_PI_INIT) |
+                                     P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQM_B1_PI_INIT));
+    }
+    else
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_DQ_PI_EN);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET0),
+                                     P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B0_PI_INIT) |
+                                     P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B1_PI_INIT));
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMARPIDQ_SW); //Switch PI SW mode to HW mode (control by DRAMC not APHY)
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1),
+            P_Fld(u1PI_Len, TX_ATK_SET1_TX_ATK_PI_LEN) |    //enable TX auto k len
+            P_Fld(pi_thrd, TX_ATK_SET1_TX_ATK_PASS_PI_THRD));  //Set threshold of PI pass window
+#if (fcFOR_CHIP_ID == fcIPM) //Fix at Mar_gaux
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), early_break, TX_ATK_SET1_TX_ATK_EARLY_BREAK); //Enable early break
+#endif
+
+#if (__LP5_COMBO__ == TRUE)
+    if (TRUE == is_lp5_family(p))
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0),
+                P_Fld(0x5, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) |
+                P_Fld(0x1, SHU_TX_SET0_TXOEN_AUTOSET_EN));   //Enable OE auto adjust
+    }
+    else
+#endif
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0),
+                P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) |
+                P_Fld(0x1, SHU_TX_SET0_TXOEN_AUTOSET_EN));   //Enable OE auto adjust
+    }
+
+#if TX_AUTO_K_DEBUG_ENABLE
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_DBG_EN);
+#endif
+}
+
+static void Tx_Auto_K_complete_check(DRAMC_CTX_T *p)
+{
+    U32 u4loop_count = 0;
+
+    while ((u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_RESULT8), TX_ATK_RESULT8_TX_ATK_DONE) != 0x1))
+    {
+        mcDELAY_US(1);
+        u4loop_count++;
+        //mcSHOW_DBG_MSG(("Wait! TX auto K is not done!\n"));
+        if (u4loop_count > 100000)
+        {
+            mcSHOW_ERR_MSG(("Error! TX auto K is not done!\n"));
+            break;
+        }
+    }
+
+    if ((u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_RESULT8), TX_ATK_RESULT8_TX_ATK_FIND_PW) == 0x1))
+    {
+        vSetCalibrationResult(p, DRAM_CALIBRATION_TX_PERBIT, DRAM_OK);
+        mcSHOW_DBG_MSG(("Tx auto K, all bit find passs window\n"));
+    }
+    else
+    {
+        mcSHOW_ERR_MSG(("Error! TX auto K is fail!\n"));
+    }
+}
+
+static void Tx_Auto_K_Clear(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x0, TX_ATK_SET1_TX_ATK_TRIG); //Disable Tx auto K
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), 0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0x1, MISC_CTRL1_R_DMARPIDQ_SW);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x0, TX_ATK_SET1_TX_ATK_DBG_EN);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_CLR); //Clear state machine
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x0, TX_ATK_SET1_TX_ATK_CLR);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1),
+                                 P_Fld(0x0, TX_ATK_SET1_TX_ATK_PI_LEN) |
+                                 P_Fld(0x0, TX_ATK_SET1_TX_ATK_DQ_PI_EN) |
+                                 P_Fld(0x0, TX_ATK_SET1_TX_ATK_DQM_PI_EN));
+#if ENABLE_PA_IMPRO_FOR_TX_AUTOK
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_CG_SET0), 0x0, TX_CG_SET0_TX_ATK_CLKRUN);
+#endif
+}
+
+#if TX_AUTO_K_WORKAROUND
+static void Tx_Auto_K_DQM_Workaround(DRAMC_CTX_T *p)
+{
+    //U32 u4DQM_MCK, u4DQM_UI, u4DQM_PI_B0, u4DQM_PI_B1;
+    //Set RK1 DQM DLY to RK0
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), u4DQM_MCK_RK1_backup);
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), u4DQM_UI_RK1_backup);
+    vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), u4DQM_PI_RK1_backup[0]);
+    vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), u4DQM_PI_RK1_backup[1]);
+}
+static void Tx_Auto_K_DQ_Workaround(DRAMC_CTX_T *p)
+{
+    //U32 u4DQ_MCK, u4DQ_UI, u4DQ_PI_B0, u4DQ_PI_B1;
+    //Set RK1 DQM DLY to RK0
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), u4DQ_MCK_RK1_backup);
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), u4DQ_UI_RK1_backup);
+    vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), u4DQ_PI_RK1_backup[0]);
+    vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), u4DQ_PI_RK1_backup[1]);
+}
+#endif
+
+#if TX_AUTO_K_DEBUG_ENABLE
+static void Tx_Auto_K_Debug_Message(DRAMC_CTX_T *p, U8 u1PI_Len)
+{
+    U8 u1bit_num = 0, u1BitIdx;
+    U16 u2Length = 0, u2Length_max = 0;
+    U32 u4status;
+    U32 u4status_bit[4][DQ_DATA_WIDTH];
+
+    if (u1PI_Len == 0)
+        u2Length_max = 48;
+    else
+        u2Length_max = 32 * (1 + u1PI_Len);
+
+    for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), u1BitIdx, TX_ATK_SET1_TX_ATK_DBG_BIT_SEL);
+
+        u4status_bit[0][u1BitIdx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_DBG_BIT_STATUS1));
+        u4status_bit[1][u1BitIdx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_DBG_BIT_STATUS2));
+        u4status_bit[2][u1BitIdx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_DBG_BIT_STATUS3));
+        u4status_bit[3][u1BitIdx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_DBG_BIT_STATUS4));
+    }
+
+    mcSHOW_DBG_MSG2(("Debug TX DQ PASS/FAIL status:\n"));
+
+    for (u2Length = 0; u2Length < u2Length_max; u2Length++)
+    {
+        mcSHOW_DBG_MSG2(("Delay=%3d ", u2Length));
+
+        for (u1bit_num = 0; u1bit_num < p->data_width; u1bit_num++)
+        {
+            u4status = ((u4status_bit[u2Length / 32][u1bit_num] >> (u2Length % 32)) & 0x1);
+
+            if (u4status == 0)
+            {
+                mcSHOW_DBG_MSG2(("x"));
+            }
+            else
+            {
+                mcSHOW_DBG_MSG2(("o"));
+            }
+
+            if (u1bit_num == (p->data_width - 1))
+            {
+                mcSHOW_DBG_MSG2((" \n"));
+            }
+        }
+    }
+
+    //mcSHOW_DBG_MSG(("Debug DQ PASS(1)/FAIL(0) bit: %d, STATUS1: 0x%x, STATUS2: 0x%x, STATUS3: 0x%x, STATUS4: 0x%x,\n",u1BitIdx,u4status_bit[0][u1BitIdx],u4status_bit[1][u1BitIdx],u4status_bit[2][u1BitIdx],u4status_bit[3][u1BitIdx]));
+}
+#endif
+#endif
+
+#if TX_K_DQM_WITH_WDBI
+void vSwitchWriteDBISettings(DRAMC_CTX_T *p, U8 u1OnOff)
+{
+    S8 u1TXShiftMCK;
+
+    u1TXShiftMCK = (u1OnOff)? -1: 1;
+    DramcWriteShiftMCKForWriteDBI(p, u1TXShiftMCK); //Tx DQ/DQM -1 MCK for write DBI ON
+
+    SetDramModeRegForWriteDBIOnOff(p, p->dram_fsp, u1OnOff);
+    DramcWriteDBIOnOff(p, u1OnOff);
+
+    #if (TX_AUTO_K_SUPPORT && TX_AUTO_K_WORKAROUND)
+    if (p->rank == RANK_1)
+    {
+        u4DQ_MCK_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0));
+        u4DQ_UI_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2));
+        u4DQ_PI_RK1_backup[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0));
+        u4DQ_PI_RK1_backup[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0));
+    }
+    #endif
+}
+#endif
+
+DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 u1VrefScanEnable, u8 isAutoK)
+{
+    U8 u1BitTemp, u1BitIdx, u1ByteIdx, u1RankIdx, backup_rank;
+    U32 uiFinishCount;
+    PASS_WIN_DATA_T WinPerBit[DQ_DATA_WIDTH], VrefWinPerBit[DQ_DATA_WIDTH], FinalWinPerBit[DQ_DATA_WIDTH];
+
+    U16 uiDelay, u2DQDelayBegin, u2DQDelayEnd, u2DQDelayStep = 1;
+
+    U8 ucdq_pi, ucdq_ui_small, ucdq_ui_large, ucdq_oen_ui_small, ucdq_oen_ui_large;
+    U8 ucdq_ui_small_reg_value, u1UpdateRegUI;  // for UI and TXDLY change check, if different , set reg.
+
+    U8 ucdq_reg_pi[DQS_BYTE_NUMBER], ucdq_reg_ui_large[DQS_BYTE_NUMBER], ucdq_reg_ui_small[DQS_BYTE_NUMBER];
+    U8 ucdq_reg_oen_ui_large[DQS_BYTE_NUMBER], ucdq_reg_oen_ui_small[DQS_BYTE_NUMBER];
+
+    U8 ucdq_reg_dqm_pi[DQS_BYTE_NUMBER] = {0}, ucdq_reg_dqm_ui_large[DQS_BYTE_NUMBER] = {0}, ucdq_reg_dqm_ui_small[DQS_BYTE_NUMBER] = {0};
+    U8 ucdq_reg_dqm_oen_ui_large[DQS_BYTE_NUMBER] = {0}, ucdq_reg_dqm_oen_ui_small[DQS_BYTE_NUMBER] = {0};
+
+    #if 1//TX_DQM_CALC_MAX_MIN_CENTER
+    U16 u2DQM_Delay;  // LP4 only
+    U16 u2Center_min[DQS_BYTE_NUMBER] = {0}, u2Center_max[DQS_BYTE_NUMBER] = {0};
+    #endif
+    U8 u1EnableDelayCell = 0;
+    U16 u2DelayCellOfst[DQ_DATA_WIDTH] = {0};
+    U32 u4err_value, u4fail_bit;
+    U16 u2FinalRange = 0, u2FinalVref;
+    U16 u2VrefLevel, u2VrefBegin = 0, u2VrefEnd = 0, u2VrefStep;
+    U16 u2TempWinSum, u2MaxWindowSum = 0;//, u2tx_window_sum[LP4_TX_VREF_DATA_NUM]={0};
+    //U32 u4TempRegValue;
+    U8 u1min_bit, u1min_winsize = 0;
+    U8 u1VrefIdx = 0;
+    U8 u1PIDiff;
+    PASS_WIN_DATA_BY_VREF_T VrefInfo[LP4_TX_VREF_DATA_NUM];
+
+    if (!p)
+    {
+        mcSHOW_ERR_MSG(("context NULL\n"));
+        return DRAM_FAIL;
+    }
+
+    #if TX_AUTO_K_SUPPORT
+    U8 u1PI_Len, u1dq_shift;
+    U32 PwMaxInitReg[4] = {DRAMC_REG_TX_ATK_RESULT0, DRAMC_REG_TX_ATK_RESULT1, DRAMC_REG_TX_ATK_RESULT2, DRAMC_REG_TX_ATK_RESULT3};
+    U32 PwMaxLenReg[4] = {DRAMC_REG_TX_ATK_RESULT4, DRAMC_REG_TX_ATK_RESULT5, DRAMC_REG_TX_ATK_RESULT6, DRAMC_REG_TX_ATK_RESULT7};
+    U32 u4Length = 0;
+    #if TX_AUTO_K_WORKAROUND
+    U8 u1backup_Rank = 0;
+    #endif
+    #if TX_AUTO_K_WORKAROUND
+    U32 u4RegBackupAddress[] =
+    {
+        (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0)),
+        (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)),
+        (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1)),
+        (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3)),
+    };
+    #endif
+    #endif
+#if 0
+    if(0)//(p->channel==CHANNEL_D)
+    {
+        ucdq_reg_ui_large[0] = ucdq_reg_ui_large[1] = 2;
+        ucdq_reg_ui_small[0] = ucdq_reg_ui_small[1] = 1;
+        ucdq_reg_oen_ui_large[0] = ucdq_reg_oen_ui_large[1] = 1;
+        ucdq_reg_oen_ui_small[0] = ucdq_reg_oen_ui_small[1] = 6;
+        ucdq_reg_pi[0] = ucdq_reg_pi[1] = 20;
+
+
+        ucdq_reg_dqm_ui_large[0] = ucdq_reg_dqm_ui_large[1] = 2;
+        ucdq_reg_dqm_ui_small[0] = ucdq_reg_dqm_ui_small[1] = 1;
+        ucdq_reg_dqm_oen_ui_large[0] = ucdq_reg_dqm_oen_ui_large[1] = 1;
+        ucdq_reg_dqm_oen_ui_small[0] = ucdq_reg_dqm_oen_ui_small[1] = 6;
+        ucdq_reg_dqm_pi[0] = ucdq_reg_dqm_pi[1] = 20;
+
+        TXSetDelayReg_DQ(p, TRUE, ucdq_reg_ui_large, ucdq_reg_oen_ui_large, ucdq_reg_ui_small, ucdq_reg_oen_ui_small, ucdq_reg_pi);
+        TXSetDelayReg_DQM(p, TRUE, ucdq_reg_dqm_ui_large, ucdq_reg_dqm_oen_ui_large, ucdq_reg_dqm_ui_small, ucdq_reg_dqm_oen_ui_small, ucdq_reg_dqm_pi);
+        return;
+    }
+#endif
+    //mcDUMP_REG_MSG(("\n[dumpRG] DramcTxWindowPerbitCal\n"));
+#if VENDER_JV_LOG
+    if (calType == TX_DQ_DQS_MOVE_DQ_ONLY)
+        vPrintCalibrationBasicInfo_ForJV(p);
+#else
+        vPrintCalibrationBasicInfo(p);
+#endif
+    mcSHOW_DBG_MSG(("[TxWindowPerbitCal] caltype:%d Autok:%d\n", calType, isAutoK));
+
+    backup_rank = u1GetRank(p);
+
+    TXPerbitCalibrationInit(p, calType);
+    TXScanRange_PI(p, calType, &u2DQDelayBegin, &u2DQDelayEnd);
+    TXScanRange_Vref(p, u1VrefScanEnable, &u2FinalRange, &u2VrefBegin, &u2VrefEnd, &u2VrefStep);
+
+    //default set FAIL
+    vSetCalibrationResult(p, DRAM_CALIBRATION_TX_PERBIT, DRAM_FAIL);
+
+    if (isAutoK)
+    {
+    #if TX_AUTO_K_SUPPORT
+    //CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL); //Let CLK always on
+
+    //Set base address of TX MCK and UI
+    u1UpdateRegUI = 1;
+    uiDelay = u2DQDelayBegin;
+    u1PI_Len = 3;
+    TxWinTransferDelayToUIPI(p, uiDelay, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small);
+
+    for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+    {
+        if (u1UpdateRegUI)
+        {
+            ucdq_reg_ui_large[u1ByteIdx] = ucdq_ui_large;
+            ucdq_reg_ui_small[u1ByteIdx] = ucdq_ui_small;
+            ucdq_reg_oen_ui_large[u1ByteIdx] = ucdq_oen_ui_large;
+            ucdq_reg_oen_ui_small[u1ByteIdx] = ucdq_oen_ui_small;
+
+            ucdq_reg_dqm_ui_large[u1ByteIdx] = ucdq_ui_large;
+            ucdq_reg_dqm_ui_small[u1ByteIdx] = ucdq_ui_small;
+            ucdq_reg_dqm_oen_ui_large[u1ByteIdx] = ucdq_oen_ui_large;
+            ucdq_reg_dqm_oen_ui_small[u1ByteIdx] = ucdq_oen_ui_small;
+        }
+
+            ucdq_reg_pi[u1ByteIdx] = ucdq_pi;
+            ucdq_reg_dqm_pi[u1ByteIdx] = ucdq_pi;
+    }
+
+    #if TX_AUTO_K_WORKAROUND
+    if (p->rank == 1)
+    {
+        u1backup_Rank = 1;
+        p->rank = 0;
+        DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+    }
+    #endif
+
+    if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM)
+    {
+        TXSetDelayReg_DQ(p, u1UpdateRegUI, ucdq_reg_ui_large, ucdq_reg_oen_ui_large, ucdq_reg_ui_small, ucdq_reg_oen_ui_small, ucdq_reg_pi);
+        mcSHOW_DBG_MSG2(("TX Auto-K set begin delay DQ MCK: %d, UI: %d, PI: %d\n", ucdq_reg_ui_large[0], ucdq_reg_ui_small[0], ucdq_reg_pi[0]));
+
+        #if TX_AUTO_K_WORKAROUND
+        if ((calType == TX_DQ_DQS_MOVE_DQ_ONLY) && (u1backup_Rank == 1))
+            Tx_Auto_K_DQM_Workaround(p); //Set best DLY value of RK1 DQM to RK0 DQM
+        #endif
+    }
+    if (calType == TX_DQ_DQS_MOVE_DQM_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM)
+    {
+        TXSetDelayReg_DQM(p, u1UpdateRegUI, ucdq_reg_dqm_ui_large, ucdq_reg_dqm_oen_ui_large, ucdq_reg_dqm_ui_small, ucdq_reg_dqm_oen_ui_small, ucdq_reg_dqm_pi);
+
+        mcSHOW_DBG_MSG2(("TX Auto-K set begin delay DQM MCK: %d, UI: %d, PI: %d\n", ucdq_reg_dqm_ui_large[0], ucdq_reg_dqm_ui_small[0], ucdq_reg_dqm_pi[0]));
+
+        #if TX_AUTO_K_WORKAROUND
+        if ((calType == TX_DQ_DQS_MOVE_DQM_ONLY) && (u1backup_Rank == 1))
+            Tx_Auto_K_DQ_Workaround(p); //Set best DLY value of RK1 DQ to RK0 DQ
+        #endif
+    }
+
+    #if TX_AUTO_K_WORKAROUND
+    if (u1backup_Rank == 1)
+        p->rank = 1;
+    #endif
+
+    //Tx_Auto_K_Init(p, calType, ucdq_pi, u1PI_Len); //u1PI_Len = 1 means that PI len is 64 PI
+    #endif
+    }
+    else
+    {
+    if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE)
+        u2DQDelayStep = (1 << 3);
+    else if (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE)
+        u2DQDelayStep = (1 << 4);
+    else if (calType == TX_DQ_DQS_MOVE_DQ_DQM)
+        u2DQDelayStep = 2;
+    else
+        u2DQDelayStep = 1;
+#if __LP5_COMBO__
+    if (is_lp5_family(p))
+        u2DQDelayStep = 4; /* To speed up simulation */
+#endif
+    #if (FOR_DV_SIMULATION_USED == 1)
+        u2DQDelayStep = (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE) ? 16 : 8;
+    #endif
+    }
+
+#if 0
+    mcSHOW_DBG_MSG(("[TxWindowPerbitCal] calType=%d, VrefScanEnable %d (Range %d,  VrefBegin %d, u2VrefEnd %d)\n"
+                    "\nBegin, DQ Scan Range %d~%d\n",
+                    calType, u1VrefScanEnable, u2FinalRange, u2VrefBegin, u2VrefEnd, u2DQDelayBegin, u2DQDelayEnd));
+#endif
+
+    #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+    if (p->femmc_Ready == 1 && (p->Bypass_TXWINDOW))
+    {
+        for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+        {
+            u2Center_min[u1ByteIdx] = p->pSavetimeData->u1TxCenter_min_Save[p->channel][p->rank][u1ByteIdx];
+            u2Center_max[u1ByteIdx] = p->pSavetimeData->u1TxCenter_max_Save[p->channel][p->rank][u1ByteIdx];
+
+            for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx++)
+            {
+                u1BitTemp = u1ByteIdx * DQS_BIT_NUMBER + u1BitIdx;
+                FinalWinPerBit[u1BitTemp].win_center = p->pSavetimeData->u1Txwin_center_Save[p->channel][p->rank][u1BitTemp];
+            }
+        }
+        vSetCalibrationResult(p, DRAM_CALIBRATION_TX_PERBIT, DRAM_FAST_K);
+    }
+    else
+    #endif
+    {
+#if ENABLE_K_WITH_WORST_SI_UI_SHIFT
+        DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//UI_SHIFT + LEN1
+#else
+        DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT);
+#endif
+
+        for (u2VrefLevel = u2VrefBegin; u2VrefLevel <= u2VrefEnd; u2VrefLevel += u2VrefStep)
+        {
+            // SET tx Vref (DQ) here, LP3 no need to set this.
+            if (u1VrefScanEnable)
+            {
+                #if (!REDUCE_LOG_FOR_PRELOADER)
+                mcSHOW_DBG_MSG2(("\n\n\tLP4 TX VrefRange %d, VrefLevel=%d\n", u2FinalRange, u2VrefLevel));
+                #endif
+
+                #if VENDER_JV_LOG
+                if (calType == TX_DQ_DQS_MOVE_DQ_ONLY)
+                {
+                    mcSHOW_DBG_MSG5(("\n\tLP4 TX VrefRange %d, VrefLevel=%d\n", u2FinalRange, u2VrefLevel));
+                }
+                #endif
+
+                DramcTXSetVref(p, u2FinalRange, u2VrefLevel);
+            }
+            else
+            {
+                mcSHOW_DBG_MSG(("\n\tTX Vref Scan disable\n"));
+            }
+
+            // initialize parameters
+            uiFinishCount = 0;
+            u2TempWinSum = 0;
+            ucdq_ui_small_reg_value = 0xff;
+
+            for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
+            {
+                WinPerBit[u1BitIdx].first_pass = (S16)PASS_RANGE_NA;
+                WinPerBit[u1BitIdx].last_pass = (S16)PASS_RANGE_NA;
+                VrefWinPerBit[u1BitIdx].first_pass = (S16)PASS_RANGE_NA;
+                VrefWinPerBit[u1BitIdx].last_pass = (S16)PASS_RANGE_NA;
+            }
+
+            if (isAutoK)
+            {
+            #if TX_AUTO_K_SUPPORT
+            Tx_Auto_K_Init(p, calType, ucdq_pi, u1PI_Len); //u1PI_Len = 1 means that PI len is 64 PI
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_TRIG); //TX Auto K start
+            #endif
+            }
+            else
+            {
+            //Move DQ delay ,  1 PI = tCK/64, total 128 PI, 1UI = 32 PI
+            //For data rate 3200, max tDQS2DQ is 2.56UI (82 PI)
+            //For data rate 4266, max tDQS2DQ is 3.41UI (109 PI)
+            for (uiDelay = u2DQDelayBegin; uiDelay < u2DQDelayEnd; uiDelay += u2DQDelayStep)
+            {
+                TxWinTransferDelayToUIPI(p, uiDelay, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small);
+
+                // Check if TX UI changed, if not change , don't need to set reg again
+                if (ucdq_ui_small_reg_value != ucdq_ui_small)
+                {
+                    u1UpdateRegUI = 1;
+                    ucdq_ui_small_reg_value = ucdq_ui_small;
+                }
+                else
+                    u1UpdateRegUI = 0;
+
+                for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+                {
+                    if (u1UpdateRegUI)
+                    {
+                        ucdq_reg_ui_large[u1ByteIdx] = ucdq_ui_large;
+                        ucdq_reg_ui_small[u1ByteIdx] = ucdq_ui_small;
+                        ucdq_reg_oen_ui_large[u1ByteIdx] = ucdq_oen_ui_large;
+                        ucdq_reg_oen_ui_small[u1ByteIdx] = ucdq_oen_ui_small;
+
+                        ucdq_reg_dqm_ui_large[u1ByteIdx] = ucdq_ui_large;
+                        ucdq_reg_dqm_ui_small[u1ByteIdx] = ucdq_ui_small;
+                        ucdq_reg_dqm_oen_ui_large[u1ByteIdx] = ucdq_oen_ui_large;
+                        ucdq_reg_dqm_oen_ui_small[u1ByteIdx] = ucdq_oen_ui_small;
+                    }
+
+                    ucdq_reg_pi[u1ByteIdx] = ucdq_pi;
+                    ucdq_reg_dqm_pi[u1ByteIdx] = ucdq_pi;
+                }
+
+                if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM)
+                {
+                    TXSetDelayReg_DQ(p, u1UpdateRegUI, ucdq_reg_ui_large, ucdq_reg_oen_ui_large, ucdq_reg_ui_small, ucdq_reg_oen_ui_small, ucdq_reg_pi);
+                }
+
+                if (calType == TX_DQ_DQS_MOVE_DQM_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM)
+                {
+                    TXSetDelayReg_DQM(p, u1UpdateRegUI, ucdq_reg_dqm_ui_large, ucdq_reg_dqm_oen_ui_large, ucdq_reg_dqm_ui_small, ucdq_reg_dqm_oen_ui_small, ucdq_reg_dqm_pi);
+                }
+
+                u4err_value = 0;
+#if ENABLE_K_WITH_WORST_SI_UI_SHIFT
+                //DramcEngine2SetPat(p, p->test_pattern, 0, 0, TE_UI_SHIFT);
+                u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, p->test_pattern);
+#else
+                //audio + xtalk pattern
+                DramcEngine2SetPat(p, TEST_AUDIO_PATTERN, 0, 0, TE_NO_UI_SHIFT);
+                u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN);
+                DramcEngine2SetPat(p, TEST_XTALK_PATTERN, 0, 1, TE_NO_UI_SHIFT);
+                u4err_value |= DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN);
+#endif
+                //audio + xtalk pattern
+                //u4err_value = 0;
+                //DramcEngine2SetPat(p, TEST_AUDIO_PATTERN, 0, 0);
+                //u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN);
+                //DramcEngine2SetPat(p, TEST_XTALK_PATTERN, 0, 1);
+                //u4err_value |= DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN);
+
+                if (u1VrefScanEnable == 0 && (calType != TX_DQ_DQS_MOVE_DQM_ONLY))
+                {
+                    //mcSHOW_DBG_MSG(("Delay=%3d |%2d %2d %3d| %2d %2d| 0x%8x [0]",uiDelay, ucdq_ui_large,ucdq_ui_small, ucdq_pi, ucdq_oen_ui_large,ucdq_oen_ui_small, u4err_value));
+                    #ifdef ETT_PRINT_FORMAT
+                    if (u4err_value != 0)
+                    {
+                        mcSHOW_DBG_MSG3(("%d |%d %d %d|[0]", uiDelay, ucdq_ui_large, ucdq_ui_small, ucdq_pi));
+                    }
+                    #else
+                    mcSHOW_DBG_MSG3(("Delay=%3d |%2d %2d %3d| 0x%8x [0]", uiDelay, ucdq_ui_large, ucdq_ui_small, ucdq_pi, u4err_value));
+                    #endif
+                }
+
+                // check fail bit ,0 ok ,others fail
+                for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
+                {
+                    u4fail_bit = u4err_value & ((U32)1 << u1BitIdx);
+
+                    if (u1VrefScanEnable == 0 && (calType != TX_DQ_DQS_MOVE_DQM_ONLY))
+                    {
+                        if(u4err_value != 0)
+                        {
+                            if (u1BitIdx % DQS_BIT_NUMBER == 0)
+                            {
+                                mcSHOW_DBG_MSG3((" "));
+                            }
+
+                            if (u4fail_bit == 0)
+                            {
+                                 mcSHOW_DBG_MSG3(("o"));
+                            }
+                            else
+                            {
+                                mcSHOW_DBG_MSG3(("x"));
+                            }
+                        }
+                    }
+
+                    if (WinPerBit[u1BitIdx].first_pass == PASS_RANGE_NA)
+                    {
+                        if (u4fail_bit == 0) //compare correct: pass
+                        {
+                            WinPerBit[u1BitIdx].first_pass = uiDelay;
+
+                            #if TX_TDQS2DQ_PRE_CAL
+                            if ((u1IsLP4Div4DDR800(p) == FALSE) && (calType == TX_DQ_DQS_MOVE_DQ_ONLY) && (u1VrefScanEnable == FALSE))
+                            {
+                                if (u2DQS2DQ_Pre_Cal[p->channel][p->rank][vGet_Div_Mode(p)] == 0)
+                                {
+                                    u2DQS2DQ_Pre_Cal[p->channel][p->rank][vGet_Div_Mode(p)] = ((uiDelay - u2DQDelayBegin)* 1000) / p->frequency;
+                                }
+
+                                if (uiDelay == u2DQDelayBegin)
+                                {
+                                    mcSHOW_ERR_MSG(("TX_TDQS2DQ_PRE_CAL: Warning, possible miss TX window boundary\n"));
+                                    #if __ETT__
+                                    while (1);
+                                    #endif
+                                }
+                            }
+                            #endif
+                        }
+                    }
+                    else if (WinPerBit[u1BitIdx].last_pass == PASS_RANGE_NA)
+                    {
+                        if (u4fail_bit != 0) //compare error : fail
+                        {
+                            WinPerBit[u1BitIdx].last_pass = uiDelay - u2DQDelayStep;
+                        }
+                        else if (uiDelay >= (u2DQDelayEnd - u2DQDelayStep))
+                        {
+                            WinPerBit[u1BitIdx].last_pass = uiDelay;
+                            mcSHOW_ERR_MSG(("\nTx last pass not found!!\n"));
+                            #if __ETT__
+                                while(1);
+                            #endif
+                        }
+
+                        if (WinPerBit[u1BitIdx].last_pass != PASS_RANGE_NA)
+                        {
+                            if ((WinPerBit[u1BitIdx].last_pass - WinPerBit[u1BitIdx].first_pass) >= (VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass))
+                            {
+                                if ((VrefWinPerBit[u1BitIdx].last_pass != PASS_RANGE_NA) && (VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass) > 0)
+                                {
+                                    mcSHOW_DBG_MSG2(("Bit[%d] Bigger window update %d > %d, window broken?\n", u1BitIdx, \
+                                        (WinPerBit[u1BitIdx].last_pass - WinPerBit[u1BitIdx].first_pass), (VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass)));
+                                }
+
+                                //if window size bigger than TX_PASS_WIN_CRITERIA, consider as real pass window. If not, don't update finish counte and won't do early break;
+                                if (((WinPerBit[u1BitIdx].last_pass - WinPerBit[u1BitIdx].first_pass) > TX_PASS_WIN_CRITERIA)
+                                    ||((u2DQDelayStep>=16) && (WinPerBit[u1BitIdx].first_pass!=PASS_RANGE_NA))) //DDR400 stepsize is too big, can't find last pass.
+                                    uiFinishCount |= (1 << u1BitIdx);
+
+                                //update bigger window size
+                                VrefWinPerBit[u1BitIdx].first_pass = WinPerBit[u1BitIdx].first_pass;
+                                VrefWinPerBit[u1BitIdx].last_pass = WinPerBit[u1BitIdx].last_pass;
+                            }
+
+                            //reset tmp window
+                            WinPerBit[u1BitIdx].first_pass = PASS_RANGE_NA;
+                            WinPerBit[u1BitIdx].last_pass = PASS_RANGE_NA;
+                        }
+                     }
+                }
+
+                if(u1VrefScanEnable==0 && (calType != TX_DQ_DQS_MOVE_DQM_ONLY))
+                {
+                    if(u4err_value != 0)
+                    {
+                        mcSHOW_DBG_MSG3((" [MSB]\n"));
+                    }
+                }
+
+                //if all bits widnow found and all bits turns to fail again, early break;
+                if (uiFinishCount == 0xffff)
+                {
+                    vSetCalibrationResult(p, DRAM_CALIBRATION_TX_PERBIT, DRAM_OK);
+                    #if !REDUCE_LOG_FOR_PRELOADER
+                    #ifdef ETT_PRINT_FORMAT
+                    mcSHOW_DBG_MSG3(("TX calibration finding left boundary early break. PI DQ delay=0x%B\n", uiDelay));
+                    #else
+                    mcSHOW_DBG_MSG3(("TX calibration finding left boundary early break. PI DQ delay=0x%2x\n", uiDelay));
+                    #endif
+                    #endif
+                    break;  //early break
+                }
+            }
+            }
+
+            if (isAutoK)
+            {
+            #if TX_AUTO_K_SUPPORT
+                Tx_Auto_K_complete_check(p);
+                #if TX_AUTO_K_DEBUG_ENABLE
+                Tx_Auto_K_Debug_Message(p, u1PI_Len);
+                #endif
+            #endif
+            }
+
+            // (1) calculate per bit window size
+            // (2) find out min win of all DQ bits
+            // (3) calculate perbit window center
+            u1min_winsize = 0xff;
+            u1min_bit = 0xff;
+            for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
+            {
+                if (isAutoK)
+                {
+                #if TX_AUTO_K_SUPPORT
+                u1dq_shift = ((u1BitIdx % 4) * 8);
+                VrefWinPerBit[u1BitIdx].first_pass = u2DQDelayBegin - ucdq_pi + ((u4IO32Read4B(DRAMC_REG_ADDR(PwMaxInitReg[u1BitIdx / 4])) & (0xff << u1dq_shift)) >> u1dq_shift);
+                VrefWinPerBit[u1BitIdx].last_pass = ((u4IO32Read4B(DRAMC_REG_ADDR(PwMaxLenReg[u1BitIdx / 4])) & (0xff << u1dq_shift)) >> u1dq_shift) + VrefWinPerBit[u1BitIdx].first_pass;
+                VrefWinPerBit[u1BitIdx].win_size = ((u4IO32Read4B(DRAMC_REG_ADDR(PwMaxLenReg[u1BitIdx / 4])) & (0xff << u1dq_shift)) >> u1dq_shift);
+
+                if (u1PI_Len == 0)
+                    u4Length = 48;
+                else
+                    u4Length = 32 * (1 + u1PI_Len);
+
+                if ((VrefWinPerBit[u1BitIdx].first_pass == (int)(u2DQDelayBegin - ucdq_pi)) || (VrefWinPerBit[u1BitIdx].last_pass == (int)(u2DQDelayBegin + u4Length)))
+                {
+                    mcSHOW_ERR_MSG(("Error! Probably miss pass window!\n"));
+                }
+
+                mcSHOW_DBG_MSG(("TX DQ bit %d, first pass: %d, last pass: %d\n", u1BitIdx, VrefWinPerBit[u1BitIdx].first_pass, VrefWinPerBit[u1BitIdx].last_pass));
+                #else
+                //if(VrefWinPerBit[u1BitIdx].last_pass == VrefWinPerBit[u1BitIdx].first_pass)
+                if (VrefWinPerBit[u1BitIdx].first_pass == PASS_RANGE_NA)
+                    VrefWinPerBit[u1BitIdx].win_size = 0;
+                else
+                    VrefWinPerBit[u1BitIdx].win_size = VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass + u2DQDelayStep;
+                #endif
+                }
+                else
+                {
+                    if (VrefWinPerBit[u1BitIdx].first_pass == PASS_RANGE_NA)
+                        VrefWinPerBit[u1BitIdx].win_size = 0;
+                    else
+                        VrefWinPerBit[u1BitIdx].win_size = VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass + u2DQDelayStep;
+                }
+
+                if (VrefWinPerBit[u1BitIdx].win_size < u1min_winsize)
+                {
+                    u1min_bit = u1BitIdx;
+                    u1min_winsize = VrefWinPerBit[u1BitIdx].win_size;
+                }
+
+                u2TempWinSum += VrefWinPerBit[u1BitIdx].win_size;  //Sum of CA Windows for vref selection
+
+                #if VENDER_JV_LOG
+                if (calType == TX_DQ_DQS_MOVE_DQ_ONLY)
+                {
+                    mcSHOW_DBG_MSG5(("TX Bit%d, %d%%\n", u1BitIdx, (VrefWinPerBit[u1BitIdx].win_size * 100 + 31) / 32));
+                }
+                #endif
+
+
+                // calculate per bit window position and print
+                VrefWinPerBit[u1BitIdx].win_center = (VrefWinPerBit[u1BitIdx].first_pass + VrefWinPerBit[u1BitIdx].last_pass) >> 1;
+                #if PINMUX_AUTO_TEST_PER_BIT_TX
+                gFinalTXPerbitFirstPass[p->channel][u1BitIdx] = VrefWinPerBit[u1BitIdx].first_pass;
+                #endif
+            }
+
+
+            #if (__ETT__ || PIN_CHECK_TOOL)
+            if (u1VrefScanEnable == 0)
+            {
+                //mcSHOW_DBG_MSG(("\n\tCH=%d, VrefRange= %d, VrefLevel = %d\n", p->channel, u2FinalRange, u2VrefLevel));
+                TxPrintWidnowInfo(p, VrefWinPerBit);
+            }
+            #endif
+
+            if (u1VrefScanEnable == 1)
+            {
+                if (u2TempWinSum > u2MaxWindowSum)
+                    u2MaxWindowSum = u2TempWinSum;
+
+                VrefInfo[u1VrefIdx].u2VrefUsed = u2VrefLevel;
+                VrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref = u1min_winsize;
+                VrefInfo[u1VrefIdx].u1WorseBitIdx_byVref = u1min_bit;
+                VrefInfo[u1VrefIdx].u2WinSum_byVref = u2TempWinSum;
+                u1VrefIdx ++;
+            }
+
+            #if TX_AUTO_K_SUPPORT
+            if (isAutoK)
+                Tx_Auto_K_Clear(p);
+            #endif
+
+            #if LP4_TX_VREF_PASS_CONDITION
+            if (u1VrefScanEnable && (u2TempWinSum < (u2MaxWindowSum * 95 / 100)) && (u1min_winsize < LP4_TX_VREF_PASS_CONDITION))
+            #else
+            if (u1VrefScanEnable && (u2TempWinSum < (u2MaxWindowSum * 95 / 100)) && (u1min_winsize > TX_PASS_WIN_CRITERIA))
+            #endif
+            {
+                mcSHOW_DBG_MSG(("\nTX Vref early break, caculate TX vref\n"));
+                break;
+            }
+
+            #if TX_AUTO_K_SUPPORT
+            Tx_Auto_K_Clear(p);
+            #endif
+        }
+
+        DramcEngine2End(p);
+
+        #if (TX_AUTO_K_SUPPORT && TX_AUTO_K_WORKAROUND)
+        if ((isAutoK) && (p->rank == RANK_1))
+        {
+            vSetRank(p, RANK_0);
+            DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+            vSetRank(p, backup_rank);
+        }
+        #endif
+
+        if (u1VrefScanEnable == 0)// ..if time domain (not vref scan) , calculate window center of all bits.
+        {
+            // Calculate the center of DQ pass window
+            // Record center sum of each byte
+            for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+            {
+                #if 1//TX_DQM_CALC_MAX_MIN_CENTER
+                u2Center_min[u1ByteIdx] = 0xffff;
+                u2Center_max[u1ByteIdx] = 0;
+                #endif
+
+                for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx++)
+                {
+                    u1BitTemp = u1ByteIdx * DQS_BIT_NUMBER + u1BitIdx;
+                    memcpy(FinalWinPerBit, VrefWinPerBit, sizeof(PASS_WIN_DATA_T) * DQ_DATA_WIDTH);
+
+                    if (FinalWinPerBit[u1BitTemp].win_center < u2Center_min[u1ByteIdx])
+                        u2Center_min[u1ByteIdx] = FinalWinPerBit[u1BitTemp].win_center;
+
+                    if (FinalWinPerBit[u1BitTemp].win_center > u2Center_max[u1ByteIdx])
+                        u2Center_max[u1ByteIdx] = FinalWinPerBit[u1BitTemp].win_center;
+
+                    #ifdef FOR_HQA_TEST_USED
+                    if ((calType == TX_DQ_DQS_MOVE_DQ_ONLY) && (u1VrefScanEnable == 0))
+                    {
+                        gFinalTXPerbitWin[p->channel][p->rank][u1BitTemp] = FinalWinPerBit[u1BitTemp].win_size;
+                    }
+                    #endif
+                }
+            }
+        }
+    }
+
+    // SET tx Vref (DQ) = u2FinalVref, LP3 no need to set this.
+    if (u1VrefScanEnable)
+    {
+        #if SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_VREF_CAL
+        if (p->femmc_Ready == 1 && (p->Bypass_TXWINDOW))
+        {
+            u2FinalVref = p->pSavetimeData->u1TxWindowPerbitVref_Save[p->channel][p->rank];
+        }
+        else
+        #endif
+        {
+            u2FinalVref = TxChooseVref(p, VrefInfo, u1VrefIdx);
+        }
+
+        TXSetFinalVref(p, u2FinalRange, u2FinalVref);
+        return DRAM_OK;
+    }
+
+#ifdef FOR_HQA_TEST_USED
+    // LP4 DQ time domain || LP3 DQ_DQM time domain
+    if (calType == TX_DQ_DQS_MOVE_DQ_ONLY)
+    {
+        gFinalTXPerbitWin_min_max[p->channel][p->rank] = u1min_winsize;
+        if(u1min_winsize<16)
+        {
+            mcSHOW_ERR_MSG(("[WARNING] Smaller TX win !!\n"));
+            #if CHECK_HQA_CRITERIA
+            while(1);
+            #endif
+        }
+    }
+#endif
+
+    // LP3 only use "TX_DQ_DQS_MOVE_DQ_DQM" scan
+    // first freq 800(LP4-1600) doesn't support jitter meter(data < 1T), therefore, don't use delay cell
+    if ((calType == TX_DQ_DQS_MOVE_DQ_ONLY) && (p->frequency >= 1333) && (p->u2DelayCellTimex100 != 0))
+    {
+        u1EnableDelayCell = 1;
+        mcSHOW_DBG_MSG(("[TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =%d/100 ps\n", p->u2DelayCellTimex100));
+        //mcDUMP_REG_MSG(("[TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =%d/100 ps\n", p->u2DelayCellTimex100));
+    }
+
+    //Calculate the center of DQ pass window
+    //average the center delay
+    for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+    {
+        mcSHOW_DBG_MSG((" == TX Byte %d ==\n", u1ByteIdx));
+        //mcDUMP_REG_MSG((" == TX Byte %d ==\n", u1ByteIdx));
+        u2DQM_Delay = ((u2Center_min[u1ByteIdx] + u2Center_max[u1ByteIdx]) >> 1); //(max +min)/2
+
+        if (u1EnableDelayCell == 0)
+        {
+            uiDelay = u2DQM_Delay;
+        }
+        else// if(calType == TX_DQ_DQS_MOVE_DQ_ONLY)
+        {
+            uiDelay = u2Center_min[u1ByteIdx];  // for DQ PI delay , will adjust with delay cell
+
+            // calculate delay cell perbit
+            for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx++)
+            {
+                u1BitTemp = u1ByteIdx * DQS_BIT_NUMBER + u1BitIdx;
+                u1PIDiff = FinalWinPerBit[u1BitTemp].win_center - u2Center_min[u1ByteIdx];
+                if (p->u2DelayCellTimex100 != 0)
+                {
+                    u2DelayCellOfst[u1BitTemp] = (u1PIDiff * 100000000 / (DDRPhyGetRealFreq(p)<< 6)) / p->u2DelayCellTimex100;
+                    mcSHOW_DBG_MSG(("u2DelayCellOfst[%d]=%d cells (%d PI)\n", u1BitTemp, u2DelayCellOfst[u1BitTemp], u1PIDiff));
+                    //mcDUMP_REG_MSG(("u2DelayCellOfst[%d]=%d cells (%d PI)\n", u1BitTemp, u2DelayCellOfst[u1BitTemp], u1PIDiff));
+
+
+                    if(u2DelayCellOfst[u1BitTemp]>255)
+                    {
+                        mcSHOW_DBG_MSG(("[WARNING] TX DQ%d delay cell %d >255, adjust to 255 cell\n", u1BitIdx, u2DelayCellOfst[u1BitTemp]));
+                        u2DelayCellOfst[u1BitTemp] =255;
+                    }
+                }
+                else
+                {
+                    mcSHOW_ERR_MSG(("Error: Cell time (p->u2DelayCellTimex100) is 0 \n"));
+                    break;
+                }
+            }
+
+        }
+
+        TxWinTransferDelayToUIPI(p, uiDelay, 1, &ucdq_reg_ui_large[u1ByteIdx], &ucdq_reg_ui_small[u1ByteIdx], &ucdq_reg_pi[u1ByteIdx], \
+                                &ucdq_reg_oen_ui_large[u1ByteIdx], &ucdq_reg_oen_ui_small[u1ByteIdx]);
+
+        TxWinTransferDelayToUIPI(p, u2DQM_Delay, 1, &ucdq_reg_dqm_ui_large[u1ByteIdx], &ucdq_reg_dqm_ui_small[u1ByteIdx], &ucdq_reg_dqm_pi[u1ByteIdx], \
+                                &ucdq_reg_dqm_oen_ui_large[u1ByteIdx], &ucdq_reg_dqm_oen_ui_small[u1ByteIdx]);
+
+        if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM)
+        {
+            mcSHOW_DBG_MSG(("Update DQ  dly =%d (%d ,%d, %d)  DQ  OEN =(%d ,%d)\n",
+                            uiDelay, ucdq_reg_ui_large[u1ByteIdx], ucdq_reg_ui_small[u1ByteIdx], ucdq_reg_pi[u1ByteIdx], \
+                            ucdq_reg_oen_ui_large[u1ByteIdx], ucdq_reg_oen_ui_small[u1ByteIdx]));
+            /*mcDUMP_REG_MSG(("Update DQ  dly =%d (%d ,%d, %d)  DQ  OEN =(%d ,%d)\n",
+                            uiDelay, ucdq_reg_ui_large[u1ByteIdx], ucdq_reg_ui_small[u1ByteIdx], ucdq_reg_pi[u1ByteIdx], \
+                            ucdq_reg_oen_ui_large[u1ByteIdx], ucdq_reg_oen_ui_small[u1ByteIdx]));*/
+        }
+
+        //if(calType ==TX_DQ_DQS_MOVE_DQM_ONLY || calType== TX_DQ_DQS_MOVE_DQ_DQM)
+        {
+            mcSHOW_DBG_MSG(("Update DQM dly =%d (%d ,%d, %d)  DQM OEN =(%d ,%d)\n",
+                    u2DQM_Delay, ucdq_reg_dqm_ui_large[u1ByteIdx], ucdq_reg_dqm_ui_small[u1ByteIdx], ucdq_reg_dqm_pi[u1ByteIdx], \
+                    ucdq_reg_dqm_oen_ui_large[u1ByteIdx], ucdq_reg_dqm_oen_ui_small[u1ByteIdx]));
+            /*mcDUMP_REG_MSG(("Update DQM dly =%d (%d ,%d, %d)  DQM OEN =(%d ,%d)\n",
+                    u2DQM_Delay, ucdq_reg_dqm_ui_large[u1ByteIdx], ucdq_reg_dqm_ui_small[u1ByteIdx], ucdq_reg_dqm_pi[u1ByteIdx], \
+                    ucdq_reg_dqm_oen_ui_large[u1ByteIdx], ucdq_reg_dqm_oen_ui_small[u1ByteIdx]));*/
+        }
+        mcSHOW_DBG_MSG(("\n"));
+
+#ifdef FOR_HQA_REPORT_USED
+        if (calType == TX_DQ_DQS_MOVE_DQ_ONLY)
+        {
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "TX_Window_Center_", "BYTE", u1ByteIdx, uiDelay, NULL);
+
+            for (u1BitIdx = u1ByteIdx*8; u1BitIdx < u1ByteIdx*8+8; u1BitIdx++)
+            {
+                HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "TX_Window_Center_", "DQ", u1BitIdx, FinalWinPerBit[u1BitIdx].win_center, NULL);
+            }
+        }
+
+#if TX_K_DQM_WITH_WDBI
+        if ((p->DBI_W_onoff[p->dram_fsp]!=DBI_ON))
+        {
+            if (calType == TX_DQ_DQS_MOVE_DQ_ONLY && u1VrefScanEnable == FALSE)
+            {
+                HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, "TX_Window_Center_", "DQM", u1ByteIdx, u2DQM_Delay, NULL);
+            }
+        }
+        else
+        {
+            if (calType == TX_DQ_DQS_MOVE_DQM_ONLY)
+            {
+                HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, "TX_Window_Center_", "DQM", u1ByteIdx, u2DQM_Delay, NULL);
+        }
+        }
+#else
+        if (calType == TX_DQ_DQS_MOVE_DQ_ONLY && u1VrefScanEnable == FALSE)
+        {
+            HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, "TX_Window_Center_", "DQM", u1ByteIdx, u2DQM_Delay, NULL);
+        }
+#endif
+
+
+#if 0
+        HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "TX_Window_Center_", "LargeUI", u1ByteIdx, ucdq_reg_ui_large[u1ByteIdx], NULL);
+        HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, "TX_Window_Center_", "SmallUI", u1ByteIdx, ucdq_reg_ui_small[u1ByteIdx], NULL);
+        HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, "TX_Window_Center_", "PI", u1ByteIdx, ucdq_reg_pi[u1ByteIdx], NULL);
+#endif
+#endif
+
+    }
+
+
+#if REG_ACCESS_PORTING_DGB
+    RegLogEnable = 1;
+#endif
+
+        /* p->rank = RANK_0, save to Reg Rank0 and Rank1, p->rank = RANK_1, save to Reg Rank1 */
+        for (u1RankIdx = p->rank; u1RankIdx < RANK_MAX; u1RankIdx++)
+        {
+            vSetRank(p, u1RankIdx);
+
+            if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM)
+            {
+                TXSetDelayReg_DQ(p, TRUE, ucdq_reg_ui_large, ucdq_reg_oen_ui_large, ucdq_reg_ui_small, ucdq_reg_oen_ui_small, ucdq_reg_pi);
+            }
+
+            TXSetDelayReg_DQM(p, TRUE, ucdq_reg_dqm_ui_large, ucdq_reg_dqm_oen_ui_large, ucdq_reg_dqm_ui_small, ucdq_reg_dqm_oen_ui_small, ucdq_reg_dqm_pi);
+
+             if (u1EnableDelayCell)
+             {
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0),
+                           P_Fld(u2DelayCellOfst[3], SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)
+                         | P_Fld(u2DelayCellOfst[2], SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0)
+                         | P_Fld(u2DelayCellOfst[1], SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0)
+                         | P_Fld(u2DelayCellOfst[0], SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0));
+                 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1),
+                           P_Fld(u2DelayCellOfst[7], SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)
+                         | P_Fld(u2DelayCellOfst[6], SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0)
+                         | P_Fld(u2DelayCellOfst[5], SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0)
+                         | P_Fld(u2DelayCellOfst[4], SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0));
+                 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0),
+                           P_Fld(u2DelayCellOfst[11], SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)
+                         | P_Fld(u2DelayCellOfst[10], SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1)
+                         | P_Fld(u2DelayCellOfst[9], SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1)
+                         | P_Fld(u2DelayCellOfst[8], SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1));
+                 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1),
+                           P_Fld(u2DelayCellOfst[15], SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)
+                         | P_Fld(u2DelayCellOfst[14], SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1)
+                         | P_Fld(u2DelayCellOfst[13], SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1)
+                         | P_Fld(u2DelayCellOfst[12], SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1));
+             }
+            #if ENABLE_TX_TRACKING
+            TXUpdateTXTracking(p, calType, ucdq_reg_pi, ucdq_reg_dqm_pi);
+            #endif
+        }
+
+        vSetRank(p, backup_rank);
+
+        if (isAutoK)
+        {
+        #if TX_AUTO_K_SUPPORT
+            #if TX_AUTO_K_WORKAROUND
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET0),
+                                 P_Fld(ucdq_reg_pi[0], TX_ATK_SET0_TX_ATK_DQ_B0_PI_INIT) |
+                                 P_Fld(ucdq_reg_pi[1], TX_ATK_SET0_TX_ATK_DQ_B1_PI_INIT) |
+                                 P_Fld(ucdq_reg_dqm_pi[0], TX_ATK_SET0_TX_ATK_DQM_B0_PI_INIT) |
+                                 P_Fld(ucdq_reg_dqm_pi[1], TX_ATK_SET0_TX_ATK_DQM_B1_PI_INIT)); //If TX auto-k is enable, TX_PI will be switch to PI_INIT
+            #endif
+        #endif
+        }
+
+#if REG_ACCESS_PORTING_DGB
+    RegLogEnable = 0;
+#endif
+
+#if (TX_AUTO_K_SUPPORT && TX_AUTO_K_WORKAROUND)
+    if ((isAutoK) && (p->rank == RANK_1) && (calType == TX_DQ_DQS_MOVE_DQ_DQM))
+    {
+        u4DQM_MCK_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1));
+        u4DQM_UI_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3));
+        u4DQM_PI_RK1_backup[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0));
+        u4DQM_PI_RK1_backup[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0));
+        u4DQ_MCK_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0));
+        u4DQ_UI_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2));
+        u4DQ_PI_RK1_backup[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0));
+        u4DQ_PI_RK1_backup[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0));
+    }
+#endif
+
+    mcSHOW_DBG_MSG4(("[TxWindowPerbitCal] Done\n\n"));
+
+    #if 0
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_PADCTL4), 1, PADCTL4_CKEFIXON);  // test only
+    #endif
+
+    return DRAM_OK;
+}
+
+#endif //SIMULATION_TX_PERBIT
+
+#if ENABLE_EYESCAN_GRAPH
+void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p)
+{
+    U8 ucindex, u1BitIdx, u1ByteIdx;
+    U8 ii, backup_rank, u1PrintWinData, u1vrefidx;
+    PASS_WIN_DATA_T WinPerBit[DQ_DATA_WIDTH], VrefWinPerBit[DQ_DATA_WIDTH], FinalWinPerBit[DQ_DATA_WIDTH];
+    U16 tx_pi_delay[4], tx_dqm_pi_delay[4];
+    U16 u2DQDelayBegin, uiDelay;
+    U16 u2VrefLevel, u2VrefBegin, u2VrefEnd, u2VrefStep, u2VrefRange;
+    U8 ucdq_pi, ucdq_ui_small, ucdq_ui_large,ucdq_oen_ui_small, ucdq_oen_ui_large;
+    U32 uiFinishCount;
+    U16 u2TempWinSum, u2tx_window_sum=0;
+    U32 u4err_value, u4fail_bit;
+    #if 1//TX_DQM_CALC_MAX_MIN_CENTER
+    U16 u2Center_min[DQS_BYTE_NUMBER],u2Center_max[DQS_BYTE_NUMBER];
+    #endif
+
+    U16 TXPerbitWin_min_max = 0;
+    U32 min_bit, min_winsize;
+
+    U16 u2FinalVref=0xd;
+    U16 u2FinalRange=0;
+
+    U8 EyeScan_index[DQ_DATA_WIDTH];
+
+    U16 backup_u1MR14Value;
+    U8 u1pass_in_this_vref_flag[DQ_DATA_WIDTH];
+
+    U8 u1MCK2UI, u1UI2PI;
+
+    U32 u4RegBackupAddress[] =
+    {
+        (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0)),
+        (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2)),
+        (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1)),
+        (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)),
+    };
+
+    //if (gTX_EYE_Scan_only_higheset_freq_flag==1 && p->frequency != u2DFSGetHighestFreq(p)) return;
+
+    //backup register value
+    DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
+
+    backup_u1MR14Value = u1MR14Value[p->channel][p->rank][p->dram_fsp];
+
+    if (gFinalTXVrefDQ[p->channel][p->rank] ==0) //Set final TX Vref as default value
+        gFinalTXVrefDQ[p->channel][p->rank] = u1MR14Value[p->channel][p->rank][p->dram_fsp];
+
+    //set initial values
+    for(u1vrefidx=0; u1vrefidx<=VREF_VOLTAGE_TABLE_NUM_LP5-1;u1vrefidx++)
+    {
+        for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
+        {
+            for(ii=0; ii<EYESCAN_BROKEN_NUM; ii++)
+            {
+                gEyeScan_Min[u1vrefidx][u1BitIdx][ii] = EYESCAN_DATA_INVALID;
+                gEyeScan_Max[u1vrefidx][u1BitIdx][ii] = EYESCAN_DATA_INVALID;
+            }
+            gEyeScan_ContinueVrefHeight[u1BitIdx] = 0;
+            gEyeScan_TotalPassCount[u1BitIdx] = 0;
+        }
+    }
+
+
+    u1MCK2UI = u1MCK2UI_DivShift(p);
+
+    //if (vGet_DDR800_Mode(p) == DDR800_CLOSE_LOOP)
+    //    u1UI2PI = 6;
+    //else
+        u1UI2PI = 5;
+
+
+    for(u1ByteIdx=0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+    {
+        if (u1ByteIdx == 0)
+        {
+            tx_pi_delay[u1ByteIdx] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_DQ0)<<(u1MCK2UI+u1UI2PI)) +
+                          (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_DQ0)<<u1UI2PI) +
+                          u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), SHU_R0_B0_DQ0_SW_ARPI_DQ_B0);
+
+            tx_dqm_pi_delay[u1ByteIdx] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), SHURK_SELPH_DQ1_TXDLY_DQM0)<<(u1MCK2UI+u1UI2PI)) +
+                              (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), SHURK_SELPH_DQ3_DLY_DQM0)<<u1UI2PI) +
+                              u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), SHU_R0_B0_DQ0_SW_ARPI_DQM_B0);
+        }
+        else
+        {
+            tx_pi_delay[u1ByteIdx] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_DQ1)<<(u1MCK2UI+u1UI2PI)) +
+                          (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_DQ1)<<u1UI2PI) +
+                          u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), SHU_R0_B1_DQ0_SW_ARPI_DQ_B1);
+
+            tx_dqm_pi_delay[u1ByteIdx] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), SHURK_SELPH_DQ1_TXDLY_DQM1)<<(u1MCK2UI+u1UI2PI)) +
+                              (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), SHURK_SELPH_DQ3_DLY_DQM1)<<u1UI2PI) +
+                              u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), SHU_R0_B1_DQ0_SW_ARPI_DQM_B1);
+        }
+    }
+
+    if (tx_pi_delay[0] < tx_pi_delay[1])
+    {
+        u2DQDelayBegin = tx_pi_delay[0]-32;
+    }
+    else
+    {
+        u2DQDelayBegin = tx_pi_delay[1]-32;
+    }
+
+    u2VrefRange = 0;
+    u2VrefBegin = 0;
+    u2VrefEnd = (p->dram_type==TYPE_LPDDR5?VREF_VOLTAGE_TABLE_NUM_LP5:VREF_VOLTAGE_TABLE_NUM_LP4)-1;
+    u2VrefStep = EYESCAN_GRAPH_CATX_VREF_STEP;
+    mcSHOW_DBG_MSG3(("\nTX Vref %d -> %d, step: %d\n", u2VrefBegin, u2VrefEnd, u2VrefStep));
+
+#if ENABLE_K_WITH_WORST_SI_UI_SHIFT
+    DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//UI_SHIFT + LEN1
+#else
+    DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT);
+#endif
+
+
+    for(u2VrefLevel = u2VrefBegin; u2VrefLevel <= u2VrefEnd; u2VrefLevel += u2VrefStep)
+    {
+        //set vref
+//fra        u1MR14Value[p->channel][p->rank][p->dram_fsp] = (u2VrefLevel | (u2VrefRange<<6));
+        DramcTXSetVref(p, u2VrefRange, u2VrefLevel);
+        mcSHOW_DBG_MSG3(("\n\n Set TX VrefRange %d, VrefLevel=%d\n", u2VrefRange, u2VrefLevel));
+
+        // initialize parameters
+        uiFinishCount = 0;
+        u2TempWinSum =0;
+
+        for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
+        {
+            WinPerBit[u1BitIdx].first_pass = (S16)PASS_RANGE_NA;
+            WinPerBit[u1BitIdx].last_pass = (S16)PASS_RANGE_NA;
+            VrefWinPerBit[u1BitIdx].first_pass = (S16)PASS_RANGE_NA;
+            VrefWinPerBit[u1BitIdx].last_pass = (S16)PASS_RANGE_NA;
+
+            gEyeScan_DelayCellPI[u1BitIdx] = 0;
+
+            EyeScan_index[u1BitIdx] = 0;
+            u1pass_in_this_vref_flag[u1BitIdx] = 0;
+        }
+
+        for (uiDelay=0; uiDelay<64; uiDelay+=(u1IsPhaseMode(p)==TRUE ? 8 : 1))
+        {
+            TxWinTransferDelayToUIPI(p, tx_pi_delay[0]+uiDelay-32, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small);
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \
+                                             P_Fld(ucdq_ui_large, SHURK_SELPH_DQ0_TXDLY_DQ0) | \
+                                             P_Fld(ucdq_oen_ui_large, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), \
+                                             P_Fld(ucdq_ui_small, SHURK_SELPH_DQ2_DLY_DQ0) | \
+                                             P_Fld(ucdq_oen_ui_small, SHURK_SELPH_DQ2_DLY_OEN_DQ0));
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), ucdq_pi, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0);
+
+            TxWinTransferDelayToUIPI(p, tx_pi_delay[1]+uiDelay-32, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small);
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \
+                                             P_Fld(ucdq_ui_large, SHURK_SELPH_DQ0_TXDLY_DQ1) | \
+                                             P_Fld(ucdq_oen_ui_large, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), \
+                                             P_Fld(ucdq_ui_small, SHURK_SELPH_DQ2_DLY_DQ1) | \
+                                             P_Fld(ucdq_oen_ui_small, SHURK_SELPH_DQ2_DLY_OEN_DQ1));
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), ucdq_pi, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1);
+
+            TxWinTransferDelayToUIPI(p, tx_dqm_pi_delay[0]+uiDelay-32, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small);
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), \
+                                            P_Fld(ucdq_ui_large, SHURK_SELPH_DQ1_TXDLY_DQM0) | \
+                                            P_Fld(ucdq_oen_ui_large, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0));
+           vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), \
+                                            P_Fld(ucdq_ui_small, SHURK_SELPH_DQ3_DLY_DQM0) | \
+                                            P_Fld(ucdq_oen_ui_small, SHURK_SELPH_DQ3_DLY_OEN_DQM0));
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), ucdq_pi,  SHU_R0_B0_DQ0_SW_ARPI_DQM_B0);
+
+            TxWinTransferDelayToUIPI(p, tx_dqm_pi_delay[1]+uiDelay-32, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small);
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), \
+                                             P_Fld(ucdq_ui_large, SHURK_SELPH_DQ1_TXDLY_DQM1) | \
+                                             P_Fld(ucdq_oen_ui_large, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), \
+                                             P_Fld(ucdq_ui_small, SHURK_SELPH_DQ3_DLY_DQM1) | \
+                                             P_Fld(ucdq_oen_ui_small, SHURK_SELPH_DQ3_DLY_OEN_DQM1));
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), ucdq_pi, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1);
+
+            u4err_value=0;
+#if ENABLE_K_WITH_WORST_SI_UI_SHIFT
+            //DramcEngine2SetPat(p, p->test_pattern, 0, 0, TE_UI_SHIFT);
+            u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, p->test_pattern);
+#else
+            //audio + xtalk pattern
+            DramcEngine2SetPat(p, TEST_AUDIO_PATTERN, 0, 0, TE_NO_UI_SHIFT);
+            u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN);
+            DramcEngine2SetPat(p, TEST_XTALK_PATTERN, 0, 1, TE_NO_UI_SHIFT);
+            u4err_value |= DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN);
+#endif
+            // audio + xtalk pattern
+            //u4err_value=0;
+            //DramcEngine2SetPat(p,TEST_AUDIO_PATTERN, 0, 0, TE_NO_UI_SHIFT);
+            //u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN);
+            //DramcEngine2SetPat(p,TEST_XTALK_PATTERN, 0, 1, TE_NO_UI_SHIFT);
+            //u4err_value |= DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN);
+
+            // check fail bit ,0 ok ,others fail
+            for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
+            {
+                u4fail_bit = u4err_value&((U32)1<<u1BitIdx);
+
+                if (u4fail_bit == 0)
+                {
+                    gEyeScan_TotalPassCount[u1BitIdx]+=EYESCAN_GRAPH_CATX_VREF_STEP;
+                }
+
+                if(WinPerBit[u1BitIdx].first_pass== PASS_RANGE_NA)
+                {
+                    if(u4fail_bit==0) //compare correct: pass
+                    {
+                        WinPerBit[u1BitIdx].first_pass = uiDelay;
+                        u1pass_in_this_vref_flag[u1BitIdx] = 1;
+                    }
+                }
+                else if(WinPerBit[u1BitIdx].last_pass == PASS_RANGE_NA)
+                {
+                    if(u4fail_bit !=0) //compare error : fail
+                    {
+                        WinPerBit[u1BitIdx].last_pass  = (uiDelay-1);
+                    }
+                    else if (uiDelay>=63)
+                    {
+                        WinPerBit[u1BitIdx].last_pass  = 63;
+                    }
+
+                    if(WinPerBit[u1BitIdx].last_pass  !=PASS_RANGE_NA)
+                    {
+                        if((WinPerBit[u1BitIdx].last_pass -WinPerBit[u1BitIdx].first_pass) >= (VrefWinPerBit[u1BitIdx].last_pass -VrefWinPerBit[u1BitIdx].first_pass))
+                        {
+                            //if window size bigger than 7, consider as real pass window. If not, don't update finish counte and won't do early break;
+                            if((WinPerBit[u1BitIdx].last_pass -WinPerBit[u1BitIdx].first_pass) >7)
+                                uiFinishCount |= (1<<u1BitIdx);
+
+                            //update bigger window size
+                            VrefWinPerBit[u1BitIdx].first_pass = WinPerBit[u1BitIdx].first_pass;
+                            VrefWinPerBit[u1BitIdx].last_pass = WinPerBit[u1BitIdx].last_pass;
+                        }
+
+
+                            if (EyeScan_index[u1BitIdx] < EYESCAN_BROKEN_NUM)
+                            {
+#if VENDER_JV_LOG || defined(RELEASE)
+                                gEyeScan_Min[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = WinPerBit[u1BitIdx].first_pass;
+                                gEyeScan_Max[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = WinPerBit[u1BitIdx].last_pass;
+#else
+//fra                                gEyeScan_Min[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = WinPerBit[u1BitIdx].first_pass + tx_pi_delay[u1BitIdx/8]-32;
+//fra                                gEyeScan_Max[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = WinPerBit[u1BitIdx].last_pass + tx_pi_delay[u1BitIdx/8]-32;
+                                gEyeScan_Min[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = (S8) WinPerBit[u1BitIdx].first_pass;
+                                gEyeScan_Max[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = (S8) WinPerBit[u1BitIdx].last_pass;
+                                mcSHOW_DBG_MSG3(("VrefRange %d, VrefLevel=%d, u1BitIdx=%d, index=%d (%d, %d)==\n",u2VrefRange,u2VrefLevel, u1BitIdx, EyeScan_index[u1BitIdx], gEyeScan_Min[u2VrefLevel/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]], gEyeScan_Max[u2VrefLevel/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]]));
+                                gEyeScan_MinMax_store_delay[u1BitIdx/8] =  tx_pi_delay[u1BitIdx/8]-32; /* save this information for HQA pass/fail judgement used */
+#endif
+                                EyeScan_index[u1BitIdx]=EyeScan_index[u1BitIdx]+1;
+                            }
+
+
+                        //reset tmp window
+                        WinPerBit[u1BitIdx].first_pass = PASS_RANGE_NA;
+                        WinPerBit[u1BitIdx].last_pass = PASS_RANGE_NA;
+                    }
+                 }
+               }
+        }
+
+        min_winsize = 0xffff;
+        min_bit = 0xff;
+        for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
+        {
+            VrefWinPerBit[u1BitIdx].win_size = VrefWinPerBit[u1BitIdx].last_pass- VrefWinPerBit[u1BitIdx].first_pass +(VrefWinPerBit[u1BitIdx].last_pass==VrefWinPerBit[u1BitIdx].first_pass?0:1);
+
+            if (VrefWinPerBit[u1BitIdx].win_size < min_winsize)
+            {
+                min_bit = u1BitIdx;
+                min_winsize = VrefWinPerBit[u1BitIdx].win_size;
+            }
+
+            u2TempWinSum += VrefWinPerBit[u1BitIdx].win_size;  //Sum of CA Windows for vref selection
+
+            gEyeScan_WinSize[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx] = VrefWinPerBit[u1BitIdx].win_size;
+
+#ifdef FOR_HQA_TEST_USED
+            if((((backup_u1MR14Value>>6)&1) == u2VrefRange) && ((backup_u1MR14Value&0x3f)==u2VrefLevel))
+            {
+                gFinalTXPerbitWin[p->channel][p->rank][u1BitIdx] = VrefWinPerBit[u1BitIdx].win_size;
+            }
+#endif
+
+        }
+
+        if ((min_winsize > TXPerbitWin_min_max) || ((min_winsize == TXPerbitWin_min_max) && (u2TempWinSum >u2tx_window_sum)))
+        {
+            TXPerbitWin_min_max = min_winsize;
+            u2tx_window_sum =u2TempWinSum;
+            u2FinalRange = u2VrefRange;
+            u2FinalVref = u2VrefLevel;
+
+            //Calculate the center of DQ pass window
+            // Record center sum of each byte
+            for (u1ByteIdx=0; u1ByteIdx<DQS_BYTE_NUMBER; u1ByteIdx++)
+            {
+        #if 1//TX_DQM_CALC_MAX_MIN_CENTER
+                u2Center_min[u1ByteIdx] = 0xffff;
+                u2Center_max[u1ByteIdx] = 0;
+        #endif
+
+                for (u1BitIdx=0; u1BitIdx<DQS_BIT_NUMBER; u1BitIdx++)
+                {
+                    ucindex = u1ByteIdx * DQS_BIT_NUMBER + u1BitIdx;
+                    FinalWinPerBit[ucindex].first_pass = VrefWinPerBit[ucindex].first_pass;
+                    FinalWinPerBit[ucindex].last_pass =  VrefWinPerBit[ucindex].last_pass;
+                    FinalWinPerBit[ucindex].win_size = VrefWinPerBit[ucindex].win_size;
+                    FinalWinPerBit[ucindex].win_center = (FinalWinPerBit[ucindex].first_pass + FinalWinPerBit[ucindex].last_pass) >> 1;
+
+                    if(FinalWinPerBit[ucindex].win_center < u2Center_min[u1ByteIdx])
+                        u2Center_min[u1ByteIdx] = FinalWinPerBit[ucindex].win_center;
+
+                    if(FinalWinPerBit[ucindex].win_center > u2Center_max[u1ByteIdx])
+                        u2Center_max[u1ByteIdx] = FinalWinPerBit[ucindex].win_center;
+                }
+            }
+        }
+
+
+        if(u2VrefRange==0 && u2VrefLevel ==50 && p->dram_type!=TYPE_LPDDR5)
+        {
+            u2VrefRange = 1;
+            u2VrefLevel = 20;
+        }
+
+        for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
+        {
+            if (u1pass_in_this_vref_flag[u1BitIdx]) gEyeScan_ContinueVrefHeight[u1BitIdx]+=EYESCAN_GRAPH_CATX_VREF_STEP;  //count pass number of continue vref
+        }
+    }
+
+    DramcEngine2End(p);
+
+    //Calculate the center of DQ pass window
+    //average the center delay
+    for (u1ByteIdx=0; u1ByteIdx<DQS_BYTE_NUMBER; u1ByteIdx++)
+    {
+        uiDelay = ((u2Center_min[u1ByteIdx] + u2Center_max[u1ByteIdx])>>1); //(max +min)/2
+
+#if VENDER_JV_LOG || defined(RELEASE)
+        gEyeScan_CaliDelay[u1ByteIdx] = uiDelay;
+#else
+        gEyeScan_CaliDelay[u1ByteIdx] = uiDelay + tx_pi_delay[u1ByteIdx]-32;
+#endif
+    }
+
+
+    //restore to orignal value
+    DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
+
+    //restore Vref
+    #if __LP5_COMBO__
+    if (is_lp5_family(p))
+    {
+       u2VrefRange = 0;
+       u2VrefLevel = backup_u1MR14Value;
+    }
+    else
+    #endif
+    {
+       u2VrefRange = backup_u1MR14Value>>6;
+       u2VrefLevel = backup_u1MR14Value & 0x3f;
+    }
+    DramcTXSetVref(p, u2VrefRange, u2VrefLevel);
+    u1MR14Value[p->channel][p->rank][p->dram_fsp] = backup_u1MR14Value;
+
+}
+#endif
+
+#if TX_OE_CALIBATION
+#define TX_OE_PATTERN_USE_TA2 1
+#define TX_OE_SCAN_FULL_RANGE 0
+
+void DramcTxOECalibration(DRAMC_CTX_T *p)
+{
+    U8 u1ByteIdx; //ucBegin[2] = {0xff, 0xff}, ucEnd[2] = {0xff, 0xff}, ucbest_step[2];
+    //U8 ucbegin=0xff, , ucfirst, ucsum, ucbest_step;
+    //U32 u4RegValue_TXDLY, u4RegValue_dly, u4err_value;
+    //U16 u2Delay, u2TempVirtualDelay, u2SmallestVirtualDelay = 0xffff;
+    //U16 u2DQOEN_DelayBegin, u2DQEN_DelayEnd;
+    //U8 ucdq_ui_large_bak[DQS_BYTE_NUMBER], ucdq_ui_small_bak[DQS_BYTE_NUMBER];
+    U8 ucdq_oen_ui_large[2] = {0}, ucdq_oen_ui_small[2] = {0};
+    //U8 ucdq_current_ui_large, ucdq_current_ui_small;
+    //U8 ucdq_ui_large_reg_value=0xff, ucdq_ui_small_reg_value=0xff;
+    //U8 ucdq_final_dqm_oen_ui_large[DQS_BYTE_NUMBER] = {0}, ucdq_final_dqm_oen_ui_small[DQS_BYTE_NUMBER] = {0};
+    //DRAM_STATUS_T KResult;
+    U8 u1TxDQOEShift = 0;
+
+    u1TxDQOEShift = TX_DQ_OE_SHIFT_LP4;
+
+    //mcDUMP_REG_MSG(("\n[dumpRG] DramcTXOECalibration\n"));
+#if VENDER_JV_LOG
+    vPrintCalibrationBasicInfo_ForJV(p);
+#else
+    vPrintCalibrationBasicInfo(p);
+#endif
+
+#if TX_OE_PATTERN_USE_TA2
+    mcSHOW_DBG_MSG(("\n[DramC_TX_OE_Calibration] TA2\n"));
+#else
+    mcSHOW_DBG_MSG(("\n[DramC_TX_OE_Calibration] DMA\n"));
+#endif
+
+    //default set FAIL
+    vSetCalibrationResult(p, DRAM_CALIBRATION_TX_OE, DRAM_FAIL);
+
+#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION)
+    if (p->femmc_Ready == 1)
+    {
+        for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+        {
+            ucdq_oen_ui_large[u1ByteIdx] = p->pSavetimeData->u1TX_OE_DQ_MCK[p->channel][p->rank][u1ByteIdx];
+            ucdq_oen_ui_small[u1ByteIdx] = p->pSavetimeData->u1TX_OE_DQ_UI[p->channel][p->rank][u1ByteIdx];
+        }
+     vSetCalibrationResult(p, DRAM_CALIBRATION_TX_OE, DRAM_FAST_K);
+    }
+#endif
+
+    for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
+    {
+        mcSHOW_DBG_MSG(("Byte%d TX OE(2T, 0.5T) = (%d, %d)\n", u1ByteIdx, ucdq_oen_ui_large[u1ByteIdx], ucdq_oen_ui_small[u1ByteIdx]));
+        //mcDUMP_REG_MSG(("Byte%d TX OE(2T, 0.5T) = (%d, %d)\n", u1ByteIdx, ucdq_oen_ui_large[u1ByteIdx], ucdq_oen_ui_small[u1ByteIdx]));
+    }
+    mcSHOW_DBG_MSG(("\n\n"));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \
+                                    P_Fld(ucdq_oen_ui_large[0], SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | \
+                                    P_Fld(ucdq_oen_ui_large[1], SHURK_SELPH_DQ0_TXDLY_OEN_DQ1));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), \
+                                    P_Fld(ucdq_oen_ui_large[0], SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | \
+                                    P_Fld(ucdq_oen_ui_large[1], SHURK_SELPH_DQ1_TXDLY_OEN_DQM1));
+    // DLY_DQ[2:0]
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), \
+                                    P_Fld(ucdq_oen_ui_small[0], SHURK_SELPH_DQ2_DLY_OEN_DQ0) | \
+                                    P_Fld(ucdq_oen_ui_small[1], SHURK_SELPH_DQ2_DLY_OEN_DQ1) );
+     // DLY_DQM[2:0]
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), \
+                                     P_Fld(ucdq_oen_ui_small[0], SHURK_SELPH_DQ3_DLY_OEN_DQM0) | \
+                                     P_Fld(ucdq_oen_ui_small[1], SHURK_SELPH_DQ3_DLY_OEN_DQM1));
+
+}
+#endif
+
+#define fld_val(_reg, _fld) \
+	((_reg & Fld2Msk32(_fld)) >> Fld_shft(_fld))
+static void OECKCKE_Control(DRAMC_CTX_T *p, U32 option)
+{
+	/* In case to prevent illegal command during JM/8Phase cal and Duty cal,
+	 * OE for CK/CKE/CA/CS will be disabled. But CK/CKE has timing requirement.
+	 * Adding this flow to fix it
+	 */
+	static U32 u4CA_CMD2_backup = 0;
+	static U32 u4SHU_CA_CMD13_backup = 0;
+    static U32 u4CS_CTRL_backup = 0;
+    static U32 u4CKE_CTRL_backup = 0;
+	static U32 u4backup_done = 0;
+	BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+	if (option == DISABLE) {
+		if (u4backup_done == 1) {
+			mcSHOW_ERR_MSG(("[%s] Backup OE again without restored??\n", __func__));
+		#if __ETT__
+			while (1);
+		#else
+			ASSERT(0);
+		#endif
+		}
+		if (!isLP4_DSC)
+		{
+		    u4CA_CMD2_backup = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2));
+		    u4SHU_CA_CMD13_backup = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13));
+            u4CS_CTRL_backup = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CA_TX_ARCS_CTRL));
+		}
+		else
+		{
+		    u4CA_CMD2_backup = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2));
+		    u4SHU_CA_CMD13_backup = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13));
+            u4CKE_CTRL_backup = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_B1_TX_CKE_CTRL));
+		}
+		u4backup_done = 1;
+
+		/* CS/CKE/CA */
+        /* CKE need disable before CS */
+		if (!isLP4_DSC)
+		{
+            /* CKE/CA */
+		    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld( 0, CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA) \
+															  | P_Fld( 1, CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA) \
+															  | P_Fld( 0, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) \
+															  | P_Fld( 0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA));
+            /*  CS  */
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_TX_ARCS_CTRL), P_Fld( 0, CA_TX_ARCS_CTRL_RG_TX_ARCS_OE_TIE_SEL_C0));
+		}
+		else
+		{
+            /* CKE */
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_TX_CKE_CTRL), P_Fld( 0, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_SEL_B1) \
+                                    | P_Fld( 1, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_EN_B1));
+            /* CS/CA */
+		    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), P_Fld( 0, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1) \
+															  | P_Fld( 1, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) \
+															  | P_Fld( 0, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1) \
+															  | P_Fld( 0xff, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1));
+		}
+
+		mcDELAY_US(1);
+		if (!isLP4_DSC)
+		{
+			/* CLK */
+			vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld( 0, CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA) \
+																  | P_Fld( 1, CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA));
+
+			/* CLKB */
+			vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld( 0, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA) \
+																  | P_Fld( 1, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA));
+		}
+		else
+		{
+			/* CLK */
+			vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), P_Fld( 0, B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1) \
+																  | P_Fld( 1, B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1));
+
+			/* CLKB */
+			vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), P_Fld( 0, SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1) \
+																  | P_Fld( 1, SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1));
+		}
+	} else {
+		U32 u4CKOE_TieSel, u4CKOE_TieEn;
+		U32 u4CKBOE_TieSel, u4CKBOE_TieEn;
+		U32 u4CSOE_TieSel, u4CSOE_TieEn;
+		U32 u4CAOE_TieSel, u4CAOE_TieEn;
+		U32 u4CKEOE_TieSel, u4CKEOE_TieEN;
+
+		if (u4backup_done == 0) {
+			mcSHOW_ERR_MSG(("[%s] Restore OE while not backup??\n", __func__));
+		#if __ETT__
+			while (1);
+		#else
+			ASSERT(0);
+		#endif
+		}
+
+		u4CKOE_TieSel = fld_val(u4CA_CMD2_backup, CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA);
+		u4CKOE_TieEn = fld_val(u4CA_CMD2_backup, CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA);
+		u4CKBOE_TieSel = fld_val(u4SHU_CA_CMD13_backup, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA);
+		u4CKBOE_TieEn = fld_val(u4SHU_CA_CMD13_backup, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA);
+		u4CAOE_TieSel = fld_val(u4CA_CMD2_backup, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA);
+		u4CAOE_TieEn = fld_val(u4CA_CMD2_backup, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA);
+        if(!isLP4_DSC)
+        {
+            u4CSOE_TieSel = fld_val(u4CS_CTRL_backup, CA_TX_ARCS_CTRL_RG_TX_ARCS_OE_TIE_SEL_C0);
+            u4CSOE_TieEn = fld_val(u4CA_CMD2_backup, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA);
+            u4CKEOE_TieSel = fld_val(u4CA_CMD2_backup, CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA);
+            /* CKE OE controlled by CS OE */
+            u4CKEOE_TieEN = u4CSOE_TieEn;
+        }
+        else
+        {
+            u4CSOE_TieSel = fld_val(u4CA_CMD2_backup, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1);
+            u4CSOE_TieEn = fld_val(u4CA_CMD2_backup, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1);
+            u4CKEOE_TieSel = fld_val(u4CKE_CTRL_backup, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_SEL_B1);
+            u4CKEOE_TieEN = fld_val(u4CKE_CTRL_backup, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_EN_B1);
+        }
+
+		if (!isLP4_DSC)
+		{
+			/* CLK */
+			vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld( u4CKOE_TieSel, CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA) \
+																  | P_Fld( u4CKOE_TieEn, CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA));
+
+			/* CLKB */
+			vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld( u4CKBOE_TieSel, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA ) \
+																  | P_Fld( u4CKBOE_TieEn, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA));
+		}
+		else
+		{
+			/* CLK */
+			vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), P_Fld( u4CKOE_TieSel, B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1) \
+																  | P_Fld( u4CKOE_TieEn, B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1));
+
+			/* CLKB */
+			vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), P_Fld( u4CKBOE_TieSel, SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1 ) \
+																  | P_Fld( u4CKBOE_TieEn, SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1));
+		}
+
+		mcDELAY_US(1);
+		/* CS/CKE/CA */
+		/* CS need enable before CKE */
+		if (!isLP4_DSC)
+		{
+		/*  CS  */
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_TX_ARCS_CTRL), P_Fld( u4CSOE_TieSel, CA_TX_ARCS_CTRL_RG_TX_ARCS_OE_TIE_SEL_C0));
+		/*  CKE/CA  */
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld( u4CKEOE_TieSel, CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA) \
+																  | P_Fld( u4CSOE_TieEn, CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA) \
+																  | P_Fld( u4CAOE_TieSel, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) \
+																  | P_Fld( u4CAOE_TieEn, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA));
+		}
+		else
+		{
+		/*  CS/CA  */
+			vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), P_Fld( u4CSOE_TieSel, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1) \
+																  | P_Fld( u4CSOE_TieEn, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) \
+																  | P_Fld( u4CAOE_TieSel, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1) \
+																  | P_Fld( u4CAOE_TieEn, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1));
+            /*  CKE  */
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_TX_CKE_CTRL), P_Fld( u4CKEOE_TieSel, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_SEL_B1) \
+                              | P_Fld( u4CKEOE_TieEN, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_EN_B1));
+		}
+
+		u4backup_done = 0;
+	}
+}
+
+static void OEDisable(DRAMC_CTX_T *p)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    //OE disable - start
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), P_Fld( 0 , B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0 ) \
+                                                          | P_Fld( 1       , B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0  ) \
+                                                          | P_Fld( 0 , B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0 ) \
+                                                          | P_Fld( 1       , B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0  ) \
+                                                          | P_Fld( 0 , B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0 ) \
+                                                          | P_Fld( 1       , B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0  ) \
+                                                          | P_Fld( 0 , B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0 ) \
+                                                          | P_Fld( 1       , B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0  ) \
+                                                          | P_Fld( 0 , B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0 ) \
+                                                          | P_Fld( 0xff       , B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0  ) );
+    if (!isLP4_DSC)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), P_Fld( 0 , B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1 ) \
+                                                              | P_Fld( 1       , B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1  ) \
+                                                              | P_Fld( 0 , B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1 ) \
+                                                              | P_Fld( 1       , B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1  ) \
+                                                              | P_Fld( 0 , B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1 ) \
+                                                              | P_Fld( 1       , B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1  ) \
+                                                              | P_Fld( 0 , B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1 ) \
+                                                              | P_Fld( 1       , B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1  ) \
+                                                              | P_Fld( 0 , B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1 ) \
+                                                              | P_Fld( 0xff , B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1) );
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld( 0 , CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA ) \
+                                                              | P_Fld( 1       , CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA  ) \
+                                                              | P_Fld( 0 , CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA ) \
+                                                              | P_Fld( 1       , CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA  ) \
+                                                              | P_Fld( 0 , CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA ) \
+                                                              | P_Fld( 0xff , CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA) );
+    }
+
+    OECKCKE_Control(p, DISABLE);
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13) , P_Fld( 0 , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0  ) \
+                                                          | P_Fld( 1       , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0   ));
+    if (!isLP4_DSC)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13) , P_Fld( 0 , SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1  ) \
+                                                              | P_Fld( 1       , SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1   ));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13) , P_Fld( 0 , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA  ) \
+                                                              | P_Fld( 1       , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA   ));
+    }
+
+    //OE disable - end
+}
+
+#ifdef FOR_HQA_TEST_USED
+// P_lm_r is 6nm, use same table with M_rg__x
+VCORE_DELAYCELL_T gVcoreDelayCellTable[49]={    {500000, 512},
+                                                {506250, 496},
+                                                {512500, 482},
+                                                {518750, 469},
+                                                {525000, 457},
+                                                {531250, 445},
+                                                {537500, 434},
+                                                {543750, 423},
+                                                {550000, 412},
+                                                {556250, 402},
+                                                {562500, 393},
+                                                {568750, 384},
+                                                {575000, 377},
+                                                {581250, 369},
+                                                {587500, 362},
+                                                {593750, 355},
+                                                {600000, 348},
+                                                {606250, 341},
+                                                {612500, 335},
+                                                {618750, 328},
+                                                {625000, 322},
+                                                {631250, 317},
+                                                {637500, 312},
+                                                {643750, 307},
+                                                {650000, 302},
+                                                {656250, 297},
+                                                {662500, 292},
+                                                {668750, 288},
+                                                {675000, 284},
+                                                {681250, 280},
+                                                {687500, 276},
+                                                {693750, 272},
+                                                {700000, 269},
+                                                {706250, 265},
+                                                {712500, 262},
+                                                {718750, 258},
+                                                {725000, 255},
+                                                {731250, 252},
+                                                {737500, 249},
+                                                {743750, 246},
+                                                {750000, 243},
+                                                {756250, 241},
+                                                {762500, 238},
+                                                {768750, 236},
+                                                {775000, 233},
+                                                {781250, 231},
+                                                {787500, 229},
+                                                {793750, 227},
+                                                {800000, 225},
+                                                //{825000, 718},
+                                                //{831250, 717},
+                                                //{837500, 715},
+                                                //{843750, 713},
+                                                //{850000, 708},
+                                                //{856250, 705},
+                                                //{862500, 702},
+                                                //{868750, 700},
+                                                //{875000, 698}
+                                                };
+
+static U16 GetVcoreDelayCellTimeFromTable(DRAMC_CTX_T *p)
+{
+    U32 i;
+    U32 get_vcore = 0;
+    U16 delay_cell_ps = 0;
+    U8 u1delay_cell_cnt = 0;
+    VCORE_DELAYCELL_T *pVcoreDelayCellTable;
+
+#if (defined(DRAM_HQA) || __ETT__) && (FOR_DV_SIMULATION_USED == 0)
+    get_vcore = dramc_get_vcore_voltage();
+#endif
+
+    pVcoreDelayCellTable = (VCORE_DELAYCELL_T *)gVcoreDelayCellTable;
+    u1delay_cell_cnt = sizeof(gVcoreDelayCellTable)/sizeof(gVcoreDelayCellTable[0]);
+
+    for(i=0; i<u1delay_cell_cnt; i++)
+    {
+        if (get_vcore <= pVcoreDelayCellTable[i].u2Vcore)
+        {
+            delay_cell_ps = pVcoreDelayCellTable[i].u2DelayCell;
+            break;
+        }
+    }
+
+    mcSHOW_DBG_MSG(("[GetVcoreDelayCellTimeFromTable(%d)] VCore=%d(x100), DelayCell=%d(x100)\n", u1delay_cell_cnt, get_vcore, delay_cell_ps));
+
+    return delay_cell_ps;
+}
+#endif
+
+//-------------------------------------------------------------------------
+/** DramcJmeterCalib
+ *  start MIOCK jitter meter.
+ *  @param p                    Pointer of context created by DramcCtxCreate.
+ *  @param *pJmtrInfo       DQSIEN signal high/low level transaction status
+ *  @param u2JmDlyStep    Clk delay step w/ DQSIEN signal
+ */
+//-------------------------------------------------------------------------
+#if ENABLE_8PHASE_CALIBRATION || defined(ENABLE_MIOCK_JMETER)
+static void DramcJmeterInit(DRAMC_CTX_T *p, U8 u1IsJmtrK)
+{
+    OEDisable(p);
+
+    //DramcHWGatingOnOff(p, 0); // disable Gating tracking for DQS PI, Remove to vApplyConfigBeforeCalibration
+    if(u1IsJmtrK != TRUE)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), P_Fld(0x0, MISC_SHU_STBCAL_STBCALEN)
+                                                           | P_Fld(0x0, MISC_SHU_STBCAL_STB_SELPHCALEN));
+    }
+
+#if 0 // 8-Phase calib must to do before DLL init for test only
+    //@A60868, Reset PI code to avoid 8-phase offset
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0), 0, B0_DLL_ARPI0_RG_ARPI_RESETB_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0), 0, B1_DLL_ARPI0_RG_ARPI_RESETB_B1);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0), 0, CA_DLL_ARPI0_RG_ARPI_RESETB_CA);
+    mcDELAY_US(1);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0), 1, B0_DLL_ARPI0_RG_ARPI_RESETB_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0), 1, B1_DLL_ARPI0_RG_ARPI_RESETB_B1);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0), 1, CA_DLL_ARPI0_RG_ARPI_RESETB_CA);
+    //@A60868, End
+
+    // @A60868, DQSIEN PI offset clear to 0
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6), 0, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6), 0, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6), 0, SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA);
+#endif
+
+    // @A60868 for *RANK_SEL_SER_EN* = 0 to DA_RX_ARDQ_RANK_SEL_TXD_*[0]
+    //              for *RANK_SEL_SER_EN* = 1 to DA_RX_ARDQ_RANK_SEL_TXD_*[7:0]
+    // The *RANK_SEL_SER_EN* = 0 is old mode.
+    // The *RANK_SEL_SER_EN* = 1 is new mode when background no any access.
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), 0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), 0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11), 0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA);
+
+    //@Darren, DLL off to stable fix middle transion from high to low or low to high at high vcore
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1), P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA)
+                                        | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1), P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0)
+                                        | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1), P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1)
+                                        | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1));
+
+    //MCK4X CG
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMDQSIENCG_EN);
+    //@A60868, DQS PI mode for JMTR
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), 0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0); // DQS PI mode
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2), 0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1); // DQS PI mode
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN); // enable toggle cnt
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), 0, MISC_CTRL4_R_OPT2_CG_DQSIEN); // Remove to Golden settings for Jmeter clock
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0, MISC_STBCAL_DQSIENCG_NORMAL_EN); // @Darren need confirm for DQS*_ERR_CNT, APHY PICG freerun
+    //@A60868, End
+
+    // Bypass DQS glitch-free mode
+    // RG_RX_*RDQ_EYE_DLY_DQS_BYPASS_B**
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), 1, B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), 1, B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1);
+
+    //Enable DQ eye scan
+    //RG_*_RX_EYE_SCAN_EN
+    //RG_*_RX_VREF_EN
+    //RG_*_RX_SMT_EN
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), P_Fld(0x1, MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN)
+                                        | P_Fld(0x1, MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN)
+                                        | P_Fld(0x1, MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN));
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), 1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), 1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), 1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), 1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3), 1, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3), 1, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1);
+    //@A60868, JMTR en
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), 1, B0_PHY2_RG_RX_ARDQS_JM_EN_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), 1, B1_PHY2_RG_RX_ARDQS_JM_EN_B1);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_JMETER), 1, MISC_JMETER_JMTR_EN);
+    //@A60868, End
+
+    //@A60868, JM_SEL = 1, JM_SEL = 0 for LPBK
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), 1, B0_PHY2_RG_RX_ARDQS_JM_SEL_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), 1, B1_PHY2_RG_RX_ARDQS_JM_SEL_B1);
+    //@A60868, End
+
+    //Enable MIOCK jitter meter mode ( RG_RX_MIOCK_JIT_EN=1)
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_MIOCK_JIT_EN);
+
+    //Disable DQ eye scan (b'1), for counter clear
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_RX_EYE_SCAN_EN);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_DQSERRCNT_DIS);
+
+#if MIOCK_JMETER_CNT_WA
+    //Fix problem of diff between sample_cnt and ones_cnt. Should be removed after IPMV2.1 (except 60892)
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_EYESCAN_DQS_OPT);
+#endif
+
+}
+
+static void DramcJmeterCalib(DRAMC_CTX_T *p, JMETER_T *pJmtrInfo, U16 u2JmDlyStep, U8 u1IsJmtrK)
+{
+    U16 u2Jm_dly_start = 0, u2Jm_dly_end = 512, u2Jm_dly_step = u2JmDlyStep;
+    U16 ucdqs_dly, fgcurrent_value, fginitial_value;
+    U16 ucsearch_state = 0xffff;
+    U32 u4sample_cnt, u4ones_cnt[DQS_BYTE_NUMBER];
+    U8 check;
+
+    check = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), MISC_DUTYSCAN1_EYESCAN_DQS_OPT);
+
+    for (ucdqs_dly = u2Jm_dly_start; ucdqs_dly < u2Jm_dly_end; ucdqs_dly += u2Jm_dly_step)
+    {
+        //@A60868, Set CLK delay (RG_*_RX_ARDQS_JM_DLY_B*)
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), ucdqs_dly, B0_PHY2_RG_RX_ARDQS_JM_DLY_B0);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), ucdqs_dly, B1_PHY2_RG_RX_ARDQS_JM_DLY_B1);
+        //@A60868, End
+
+        //Reset eye scan counters (reg_sw_rst): 1 to 0
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_REG_SW_RST);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_REG_SW_RST);
+
+        //Enable DQ eye scan (b'1)
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN);
+
+        //2ns/sample, here we delay 1ms about 500 samples
+        mcDELAY_US(10);
+
+        //Disable DQ eye scan (b'1), for counter latch
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_RX_EYE_SCAN_EN);
+
+        //Read the counter values from registers (toggle_cnt*, dqs_err_cnt*);
+        u4sample_cnt = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_TOGGLE_CNT), MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT);
+        u4ones_cnt[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS0_ERR_CNT), MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT);
+        //u4ones_cnt[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS1_ERR_CNT), MISC_DUTY_DQS1_ERR_CNT_DQS1_ERR_CNT);
+        //u4ones_cnt[2] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS2_ERR_CNT), MISC_DUTY_DQS2_ERR_CNT_DQS2_ERR_CNT);
+        //u4ones_cnt[3] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS3_ERR_CNT), MISC_DUTY_DQS3_ERR_CNT_DQS3_ERR_CNT);
+#ifndef DDR_INIT_TIME_PROFILING
+        if (u1IsJmtrK == TRUE){
+            mcSHOW_DBG_MSG2(("%d : %d, %d\n", ucdqs_dly, u4sample_cnt, u4ones_cnt[0]));
+        }
+#endif
+
+        //change to boolean value
+        if (u4ones_cnt[0] < (u4sample_cnt / 2))
+        {
+            fgcurrent_value = 0;
+        }
+        else
+        {
+            fgcurrent_value = 1;
+        }
+
+
+        if (ucsearch_state == 0xffff)
+        {
+            //record initial value at the beginning
+            fginitial_value = fgcurrent_value;
+            ucsearch_state = 0;
+        }
+        else
+        {
+            // check if change value
+            if (fgcurrent_value != fginitial_value)
+            {
+                // start of the period
+                fginitial_value = fgcurrent_value;
+                pJmtrInfo->JmtrInfo[ucsearch_state].u1JmDelay = ucdqs_dly;
+                pJmtrInfo->JmtrInfo[ucsearch_state].u1TransLevel = fgcurrent_value;
+
+                ucsearch_state++;
+                pJmtrInfo->u1TransCnt = ucsearch_state;
+                if (ucsearch_state == CYCLE_1T)
+                    break; // 1T early break;
+            }
+        }
+    }
+}
+#endif
+
+//-------------------------------------------------------------------------
+/** DramcMiockJmeter
+ *  start MIOCK jitter meter.
+ *  @param p                Pointer of context created by DramcCtxCreate.
+ *  @param block_no         (U8): block 0 or 1.
+ *  @retval status          (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL
+ */
+//-------------------------------------------------------------------------
+
+#ifdef ENABLE_MIOCK_JMETER
+static U16 DramcMiockJmeter(DRAMC_CTX_T *p)
+{
+    U8 backup_rank, u1RankIdx;
+    U16 ucstart_period = 0, ucmiddle_period = 0, ucend_period = 0;
+    // Read PCW
+    U16 u2real_freq, u2real_period;
+    // DQSIEN
+    U8 u1RxGatingPI = 0, u1RxGatingPI_start = 0, u1RxGatingPI_end = 63;
+    // Jmeter Scan
+    JMETER_T JmtrInfo;
+    //U8 u1JmtrPrintCnt = 0;
+    U8 u1GatingPI_Step = 1;
+    U16 num_dlycell_perT;
+    U16 delay_cell_ps;
+
+    U32 u4RegBackupAddress[] =
+    {
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY)), // need porting to Jmeter
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY + DDRPHY_AO_RANK_OFFSET)), // need porting to Jmeter
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_JMETER)),
+        //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2)), // for gating on/off
+        //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2)), // for gating on/off
+        //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL)), // for gating on/off
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13)),
+
+    };
+
+    if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE)
+        u1GatingPI_Step = 1 << 3;
+    else if (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE)
+        u1GatingPI_Step = 1 << 4;
+    else
+        u1GatingPI_Step = 1;
+
+    backup_rank = u1GetRank(p);
+    memset(&JmtrInfo, 0, sizeof(JmtrInfo));
+
+    //backup register value
+    DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+
+    //mcDUMP_REG_MSG(("\n[dumpRG] DramcMiockJmeter\n"));
+
+    //default set fail
+    vSetCalibrationResult(p, DRAM_CALIBRATION_JITTER_METER, DRAM_FAIL);
+
+#if VENDER_JV_LOG
+    vPrintCalibrationBasicInfo_ForJV(p);
+#else
+    vPrintCalibrationBasicInfo(p);
+#endif
+    mcSHOW_DBG_MSG(("[DramcMiockJmeter]\n"));
+
+    DramcJmeterInit(p, TRUE);
+
+    for (u1RxGatingPI = u1RxGatingPI_start; u1RxGatingPI < u1RxGatingPI_end; u1RxGatingPI += u1GatingPI_Step)
+    {
+        mcSHOW_DBG_MSG2(("\nu1RxGatingPI = %d\n", u1RxGatingPI));
+
+        for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+        {
+            vSetRank(p, u1RankIdx);
+            // SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0[6] no use (ignore)
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), u1RxGatingPI, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); // for rank*_B0
+            //Darren---vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY), u1RxGatingPI, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); // for rank*_B0
+        }
+        vSetRank(p, backup_rank);
+
+        DramcJmeterCalib(p, &JmtrInfo, 4, TRUE);
+
+        if ((JmtrInfo.u1TransCnt == CYCLE_1T) || (JmtrInfo.u1TransCnt == CYCLE_05T)) // (1T or 0.5T)
+            break;
+    }
+
+    //restore to orignal value
+    OECKCKE_Control(p, ENABLE);
+    DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+
+#if 0 //@Darren, for debug print
+    for (u1JmtrPrintCnt = 0; u1JmtrPrintCnt < JmtrInfo.u1TransCnt; u1JmtrPrintCnt++)
+    {
+            mcSHOW_DBG_MSG(("\n\t JmtrInfo.JmtrInfo[%d].u1JmDelay = %d\n", u1JmtrPrintCnt, JmtrInfo.JmtrInfo[u1JmtrPrintCnt].u1JmDelay));
+            mcSHOW_DBG_MSG(("\n\t JmtrInfo.JmtrInfo[%d].u1TransLevel = %d\n", u1JmtrPrintCnt, JmtrInfo.JmtrInfo[u1JmtrPrintCnt].u1TransLevel));
+    }
+    mcSHOW_DBG_MSG(("\n\tMIOCK jitter meter - ucsearch_state = %d\n", ucsearch_state));
+#endif
+
+    if (JmtrInfo.u1TransCnt != CYCLE_1T)
+    {
+        if (JmtrInfo.u1TransCnt != CYCLE_05T)
+        {
+            mcSHOW_DBG_MSG(("\n\tMIOCK jitter meter - ch=%d\n", p->channel));
+            mcSHOW_DBG_MSG(("\tLess than 0.5T data. Cannot calculate delay cell time\n\n"));
+
+            delay_cell_ps = 0;   //for LP3 and LP4 lookup table used
+
+            return delay_cell_ps;
+        }
+        else
+        {   // for 0.5T
+            //Calculate 1 delay cell = ? ps
+            // 1T = ? delay cell
+            ucstart_period = JmtrInfo.JmtrInfo[0].u1JmDelay;
+            ucmiddle_period = JmtrInfo.JmtrInfo[JmtrInfo.u1TransCnt-1].u1JmDelay;
+            num_dlycell_perT = (ucmiddle_period - ucstart_period) * 2;
+            // 1T = ? ps
+        }
+    }
+    else
+    {   // for 1T
+        //Calculate 1 delay cell = ? ps
+        // 1T = ? delay cell
+        ucstart_period = JmtrInfo.JmtrInfo[0].u1JmDelay;
+        ucend_period = JmtrInfo.JmtrInfo[JmtrInfo.u1TransCnt-1].u1JmDelay;
+        num_dlycell_perT = (ucend_period - ucstart_period);
+        // 1T = ? ps
+    }
+    vSetCalibrationResult(p, DRAM_CALIBRATION_JITTER_METER, DRAM_OK);
+
+    u2real_freq = DDRPhyGetRealFreq(p);
+    u2real_period = (U16) (1000000 / u2real_freq);
+
+    //calculate delay cell time
+    delay_cell_ps = u2real_period * 100 / num_dlycell_perT;
+
+    if (JmtrInfo.u1TransCnt == CYCLE_1T)
+    { // 1T
+        mcSHOW_DBG_MSG(("\n\tMIOCK jitter meter\tch=%d\n\n"
+                        "1T = (%d-%d) = %d dly cells\n"
+                        "Clock freq = %d MHz, period = %d ps, 1 dly cell = %d/100 ps\n\n",
+                            p->channel,
+                            ucend_period, ucstart_period, num_dlycell_perT,
+                            u2real_freq, u2real_period, delay_cell_ps));
+        /*mcDUMP_REG_MSG(("\n\tMIOCK jitter meter\tch=%d\n\n"
+                        "1T = (%d-%d) = %d dly cells\n"
+                        "Clock freq = %d MHz, period = %d ps, 1 dly cell = %d/100 ps\n",
+                            p->channel,
+                            ucend_period, ucstart_period, num_dlycell_perT,
+                            u2real_freq, u2real_period, delay_cell_ps));*/
+    }
+    else
+    { // 0.5T
+        mcSHOW_DBG_MSG(("\n\tMIOCK jitter meter\tch=%d\n\n"
+                        "1T = (%d-%d)*2 = %d dly cells\n"
+                        "Clock freq = %d MHz, period = %d ps, 1 dly cell = %d/100 ps\n\n",
+                            p->channel,
+                            ucmiddle_period, ucstart_period, num_dlycell_perT,
+                            u2real_freq, u2real_period, delay_cell_ps));
+        /*mcDUMP_REG_MSG(("\n\tMIOCK jitter meter\tch=%d\n\n"
+                        "1T = (%d-%d)*2 = %d dly cells\n"
+                        "Clock freq = %d MHz, period = %d ps, 1 dly cell = %d/100 ps\n",
+                            p->channel,
+                            ucmiddle_period, ucstart_period, num_dlycell_perT,
+                            u2real_freq, u2real_period, delay_cell_ps));*/
+    }
+
+    return delay_cell_ps;
+
+// log example
+/* dly: sample_cnt   DQS0_cnt  DQS1_cnt
+    0 : 10962054,        0,        0
+    1 : 10958229,        0,        0
+    2 : 10961109,        0,        0
+    3 : 10946916,        0,        0
+    4 : 10955421,        0,        0
+    5 : 10967274,        0,        0
+    6 : 10893582,        0,        0
+    7 : 10974762,        0,        0
+    8 : 10990278,        0,        0
+    9 : 10972026,        0,        0
+   10 :  7421004,        0,        0
+   11 : 10943883,        0,        0
+   12 : 10984275,        0,        0
+   13 : 10955268,        0,        0
+   14 : 10960326,        0,        0
+   15 : 10952451,        0,        0
+   16 : 10956906,        0,        0
+   17 : 10960803,        0,        0
+   18 : 10944108,        0,        0
+   19 : 10959939,        0,        0
+   20 : 10959246,        0,        0
+   21 : 11002212,        0,        0
+   22 : 10919700,        0,        0
+   23 : 10977489,        0,        0
+   24 : 11009853,        0,        0
+   25 : 10991133,        0,        0
+   26 : 10990431,        0,        0
+   27 : 10970703,    11161,        0
+   28 : 10970775,   257118,        0
+   29 : 10934442,  9450467,        0
+   30 : 10970622, 10968475,        0
+   31 : 10968831, 10968831,        0
+   32 : 10956123, 10956123,        0
+   33 : 10950273, 10950273,        0
+   34 : 10975770, 10975770,        0
+   35 : 10983024, 10983024,        0
+   36 : 10981701, 10981701,        0
+   37 : 10936782, 10936782,        0
+   38 : 10889523, 10889523,        0
+   39 : 10985913, 10985913,    55562
+   40 : 10970235, 10970235,   272294
+   41 : 10996056, 10996056,  9322868
+   42 : 10972350, 10972350, 10969738
+   43 : 10963917, 10963917, 10963917
+   44 : 10967895, 10967895, 10967895
+   45 : 10961739, 10961739, 10961739
+   46 : 10937097, 10937097, 10937097
+   47 : 10937952, 10937952, 10937952
+   48 : 10926018, 10926018, 10926018
+   49 : 10943793, 10943793, 10943793
+   50 : 10954638, 10954638, 10954638
+   51 : 10968048, 10968048, 10968048
+   52 : 10944036, 10944036, 10944036
+   53 : 11012112, 11012112, 11012112
+   54 : 10969137, 10969137, 10969137
+   55 : 10968516, 10968516, 10968516
+   56 : 10952532, 10952532, 10952532
+   57 : 10985832, 10985832, 10985832
+   58 : 11002527, 11002527, 11002527
+   59 : 10950660, 10873571, 10950660
+   60 : 10949022, 10781797, 10949022
+   61 : 10974366, 10700617, 10974366
+   62 : 10972422,  1331974, 10972422
+   63 : 10926567,        0, 10926567
+   64 : 10961658,        0, 10961658
+   65 : 10978893,        0, 10978893
+   66 : 10962828,        0, 10962828
+   67 : 10957599,        0, 10957599
+   68 : 10969227,        0, 10969227
+   69 : 10960722,        0, 10960722
+   70 : 10970937,        0, 10963180
+   71 : 10962054,        0, 10711639
+   72 : 10954719,        0, 10612707
+   73 : 10958778,        0,   479589
+   74 : 10973898,        0,        0
+   75 : 11004156,        0,        0
+   76 : 10944261,        0,        0
+   77 : 10955340,        0,        0
+   78 : 10998153,        0,        0
+   79 : 10998774,        0,        0
+   80 : 10953234,        0,        0
+   81 : 10960020,        0,        0
+   82 : 10923831,        0,        0
+   83 : 10951362,        0,        0
+   84 : 10965249,        0,        0
+   85 : 10949103,        0,        0
+   86 : 10948707,        0,        0
+   87 : 10941147,        0,        0
+   88 : 10966572,        0,        0
+   89 : 10971333,        0,        0
+   90 : 10943721,        0,        0
+   91 : 10949337,        0,        0
+   92 : 10965942,        0,        0
+   93 : 10970397,        0,        0
+   94 : 10956429,        0,        0
+   95 : 10939896,        0,        0
+   96 : 10967112,        0,        0
+   97 : 10951911,        0,        0
+   98 : 10953702,        0,        0
+   99 : 10971090,        0,        0
+  100 : 10939590,        0,        0
+  101 : 10993392,        0,        0
+  102 : 10975932,        0,        0
+  103 : 10949499,    40748,        0
+  104 : 10962522,   258638,        0
+  105 : 10951524,   275292,        0
+  106 : 10982475,   417642,        0
+  107 : 10966887, 10564347,        0
+  ===============================================================================
+      MIOCK jitter meter - channel=0
+  ===============================================================================
+  1T = (107-29) = 78 delay cells
+  Clock frequency = 936 MHz, Clock period = 1068 ps, 1 delay cell = 13 ps
+*/
+}
+
+static U16 get_DelayCell_by_Vcore(U32 check_vcore_value)
+{
+    U8 i= 0;
+
+    for (i = SRAM_SHU0; i < DRAM_DFS_SRAM_MAX; i++)
+    {
+        if (JMeter_DelayCell_Table[i].Vcore == check_vcore_value)
+        {
+            return JMeter_DelayCell_Table[i].delay_cell_ps; //found !!
+        }
+    }
+
+    return 0; //not found
+}
+
+/* "picoseconds per delay cell" depends on Vcore only (frequency doesn't matter)
+ * 1. Retrieve current freq's vcore voltage using pmic API
+ * 2. Perform delay cell time calculation (Bypass if shuffle vcore value is the same as before)
+ */
+U16 GetVcoreDelayCellTime(DRAMC_CTX_T *p)
+{
+    U32 curr_vcore_value;
+    U16 delay_cell_ps;
+    int vcore_i=0;
+
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+    if(p->femmc_Ready==1)
+    {
+        mcSHOW_DBG_MSG(("[FAST_K] Freq=%d, DelayCellTimex100=%d\n", p->frequency, p->pSavetimeData->u2DelayCellTimex100));
+        return p->pSavetimeData->u2DelayCellTimex100;
+    }
+#endif
+
+#if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
+    curr_vcore_value = dramc_get_vcore_voltage();
+#endif
+
+    /* find delay cell by curr_vcore_value */
+    delay_cell_ps = get_DelayCell_by_Vcore(curr_vcore_value);
+
+    if (delay_cell_ps == 0)
+    {
+        /* not found!! */
+
+        /* can K JMeter */
+        if (p->frequency > 600)
+        {
+            delay_cell_ps = DramcMiockJmeter(p);
+
+#ifdef FOR_HQA_TEST_USED
+            /* if K fail, then look up table */
+            if (delay_cell_ps == 0) delay_cell_ps = GetVcoreDelayCellTimeFromTable(p); //lookup table
+#endif
+        }
+#ifdef FOR_HQA_TEST_USED
+        else
+    {
+            /* save K JMeter's time, use llok up table directly */
+            delay_cell_ps = GetVcoreDelayCellTimeFromTable(p); //lookup table
+    }
+#endif
+        if (delay_cell_ps == 0)
+        {
+            //not found finally
+            mcSHOW_ERR_MSG(("[%s] Get Delay Cell by Vcore fail!!\n", __func__));
+#if __ETT__
+            while(1);
+#endif
+        }
+
+        /* save values */
+        for(vcore_i=0; vcore_i<DRAM_DFS_SRAM_MAX; vcore_i++)
+        {
+            if (JMeter_DelayCell_Table[vcore_i].Vcore == 0) //save current vcore's delay cell
+    {
+                JMeter_DelayCell_Table[vcore_i].delay_cell_ps = delay_cell_ps;
+                JMeter_DelayCell_Table[vcore_i].Vcore = curr_vcore_value;
+                break;
+}
+        }
+    }
+#if __ETT__
+    mcSHOW_DBG_MSG(("[%s] Freq=%d, VCORE=%d, cell=%d\n", __func__, p->frequency, curr_vcore_value, delay_cell_ps));
+#endif
+
+    mcSHOW_DBG_MSG3(("DelayCellTimex100 (VCORE=%d, cell=%d)\n", JMeter_DelayCell_Table[vcore_i].Vcore, delay_cell_ps));
+
+#ifdef FOR_HQA_REPORT_USED
+    if (gHQALog_flag == 1)
+    {
+        HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("delaycell_CBT %d\n", delay_cell_ps));
+    }
+#endif
+
+    return delay_cell_ps;
+}
+
+void Get_RX_DelayCell(DRAMC_CTX_T *p)
+{
+#if defined(FOR_HQA_REPORT_USED) && (FOR_DV_SIMULATION_USED==0) && (SW_CHANGE_FOR_SIMULATION==0)
+
+    #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+        if(p->femmc_Ready == 1)
+        {
+            return;  //gHQALOG_RX_delay_cell_ps_075V is not used in fastk (Only needed in HQA report and eyescan log).
+        }
+    #endif
+
+        if (gHQALOG_RX_delay_cell_ps_075V == 0)
+        {
+#if __ETT__
+            mcSHOW_DBG_MSG(("RX delay cell calibration (%d):\n", hqa_vmddr_class));
+            switch (hqa_vmddr_class)
+    {
+                case 1:
+                    dramc_set_vcore_voltage(_SEL_PREFIX(VMDDR, HV, LP4));
+                    break;
+                case 2:
+                    dramc_set_vcore_voltage(_SEL_PREFIX(VMDDR, NV, LP4));
+                    break;
+                case 3:
+                    dramc_set_vcore_voltage(_SEL_PREFIX(VMDDR, LV, LP4));
+                    break;
+    }
+#else
+            // set vcore to RX used 0.75V
+            dramc_set_vcore_voltage(SEL_PREFIX_VMDDR);  //set vmddr voltage to vcore to K RX delay cell
+#endif
+
+            gHQALOG_RX_delay_cell_ps_075V = GetVcoreDelayCellTime(p);
+
+            // set vocre back
+            vSetVcoreByFreq(p);
+    }
+#endif
+}
+#endif
+
+//-------------------------------------------------------------------------
+/** Dramc8PhaseCal
+ *  start 8-Phase Calibration.
+ *  @param p                Pointer of context created by DramcCtxCreate.
+ *  @param block_no         (U8): block 0 or 1.
+ *  @retval status          (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL
+ */
+//-------------------------------------------------------------------------
+
+DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p)
+{
+#if ENABLE_8PHASE_CALIBRATION
+    U8 u18Ph_dly_loop_break = 0;
+    U8 u1DqsienPI = 0;
+    U8 u18Phase_SM = DQS_8PH_DEGREE_0, u18Ph_dly_final = 0xff;
+    U8 u18Ph_dly = 0, u18Ph_start = 0, u18Ph_end = 0;
+
+    U16 u2R0 = 0xffff, u2R180 = 0xffff, u2R = 0xffff;
+    U16 u2P = 0xffff, ucdqs_dly = 0;
+    S16 s2Err_code = 0x7fff, s2Err_code_min = 0x7fff;
+
+    U8 backup_rank, u1RankIdx, u18PhDlyBackup = 0;
+    U8 u1loop_cnt = 0, u1early_break_cnt = 5;
+
+    // Jmeter Scan
+    JMETER_T JmtrInfo;
+    U8 u1JmtrPrintCnt = 0;
+
+    U32 u4backup_broadcast= GetDramcBroadcast();
+    DRAM_STATUS_T eDRAMStatus = DRAM_OK;
+
+#ifdef DUMP_INIT_RG_LOG_TO_DE //for FT dump 3733 dram_init.c
+    return DRAM_OK;
+#endif
+
+    u1DqsienPI = 0x0;
+
+    // error handling
+    if (!p)
+    {
+        mcSHOW_ERR_MSG(("context NULL\n"));
+        return DRAM_FAIL;
+    }
+
+    if (p->frequency < 1866)
+    {
+        //mcSHOW_ERR_MSG(("skip 8-Phase Calib Freq is %d < 1866 !!!\n", p->frequency));
+        return DRAM_OK;
+    }
+
+    //mcDUMP_REG_MSG(("\n[dumpRG] Dramc8PhaseCal\n"));
+#if VENDER_JV_LOG
+    vPrintCalibrationBasicInfo_ForJV(p);
+#else
+    vPrintCalibrationBasicInfo(p);
+#endif
+
+    mcSHOW_DBG_MSG(("[Dramc8PhaseCal]\n"));
+
+    U32 u4RegBackupAddress[] =
+    {
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY)), // need porting to Jmeter
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY + DDRPHY_AO_RANK_OFFSET)), // need porting to Jmeter
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_JMETER)),
+        //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2)), // for gating on/off backup/restore
+        //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2)), // for gating on/off backup/restore
+        (DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL)), // for gating on/off backup/restore
+#if 0
+        (DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6)),
+#endif
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13)),
+
+    };
+
+    backup_rank = u1GetRank(p);
+    memset(&JmtrInfo, 0, sizeof(JmtrInfo));
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+    //backup register value
+    DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+
+    DramcJmeterInit(p, FALSE);
+
+    u18PhDlyBackup = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ1), SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0);
+
+    for (u18Phase_SM = DQS_8PH_DEGREE_0; u18Phase_SM < DQS_8PH_DEGREE_MAX; u18Phase_SM++)
+    {
+        switch (u18Phase_SM)
+        {
+            case DQS_8PH_DEGREE_0:
+                u1DqsienPI = 16;
+                u18Ph_start = 0;
+                u18Ph_end = 1;
+                break;
+            case DQS_8PH_DEGREE_180:
+                u1DqsienPI = 48;
+                u18Ph_start = 0;
+                u18Ph_end = 1;
+                break;
+            case DQS_8PH_DEGREE_45:
+                u1DqsienPI = 24;
+                u18Ph_start = 0;
+                u18Ph_end = 32;
+                break;
+            default:
+                mcSHOW_ERR_MSG(("u18Phase_SM err!\n"));
+                #if __ETT__
+                while (1);
+                #endif
+        }
+
+        mcSHOW_DBG_MSG2(("\n[Dramc8PhaseCal] 8-Phase SM_%d, 8PH_dly (%d~%d), DQSIEN PI = %d, 8PH_Dly = %d\n", u18Phase_SM, u18Ph_start, u18Ph_end, u1DqsienPI, u18PhDlyBackup));
+
+        //to see 1T(H,L) or 1T(L,H) from delaycell=0 to 127
+        //NOTE: Must set dual ranks for Rx path
+        for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+        {
+            vSetRank(p, u1RankIdx);
+            // SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0[6] no use (ignore)
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), u1DqsienPI, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); // for rank*_B0
+        }
+        vSetRank(p, backup_rank);
+
+        for (u18Ph_dly = u18Ph_start; u18Ph_dly < u18Ph_end; u18Ph_dly++)
+        {
+            mcSHOW_DBG_MSG2(("8PH dly = %d\n", u18Ph_dly));
+
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ1), u18Ph_dly, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1), u18Ph_dly, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1), u18Ph_dly, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA);
+
+            DramcJmeterCalib(p, &JmtrInfo, 1, FALSE);
+
+            for (u1JmtrPrintCnt = 0; u1JmtrPrintCnt < JmtrInfo.u1TransCnt; u1JmtrPrintCnt++)
+            {
+                if (JmtrInfo.JmtrInfo[u1JmtrPrintCnt].u1TransLevel == 1) // find the High Level
+                {
+                    ucdqs_dly = JmtrInfo.JmtrInfo[u1JmtrPrintCnt].u1JmDelay;
+
+                    if (u18Phase_SM == DQS_8PH_DEGREE_0)
+                    {
+                        u2R0 = ucdqs_dly;
+                        mcSHOW_DBG_MSG2(("R0 (H) = %d\n", u2R0));
+                        break; // break ucdqs_dly for loop
+                    }
+                    else if (u18Phase_SM == DQS_8PH_DEGREE_180)
+                    {
+                        u2R180 = ucdqs_dly;
+                        if (u2R180 > u2R0)
+                        {
+                            u2R = u2R0 + ((u2R180 - u2R0) >> 2); // u2R180 >= u2R0 for (u1R180 - u1R0)/4 for 180 degree. /2 for 90 degree
+                            mcSHOW_DBG_MSG2(("R = %d, R180 (H) = %d\n", u2R, u2R180));
+                            break; // break ucdqs_dly for loop
+                        }
+                    }
+                    else if (u18Phase_SM == DQS_8PH_DEGREE_45)
+                    {
+                        u2P = ucdqs_dly;
+                        if (u2P > u2R0) // u2P ~= DQS_8PH_DEGREE_180
+                        {
+                            // Absolute to find min diff
+                            if (u2R > u2P)
+                                s2Err_code = u2R - u2P;
+                            else
+                                s2Err_code = u2P - u2R;
+
+                            if (s2Err_code == 0)
+                            {
+                                s2Err_code_min = s2Err_code;
+                                u18Ph_dly_final = u18Ph_dly;
+                                u18Ph_dly_loop_break = 1;
+                            }
+                            else if (s2Err_code < s2Err_code_min)
+                            {
+                                s2Err_code_min = s2Err_code;
+                                u18Ph_dly_final = u18Ph_dly;
+                                u1loop_cnt = 0;
+                            }
+                            else if (s2Err_code >= s2Err_code_min)
+                            {
+                                // check early break for u18Ph_dly for loop
+                                u1loop_cnt++;
+                                if (u1loop_cnt > u1early_break_cnt)
+                                    u18Ph_dly_loop_break = 1;
+                            }
+
+                            mcSHOW_DBG_MSG2(("diff (P-R) = %d, min = %d, early break count = %d, R45 (H) = %d\n", s2Err_code, s2Err_code_min, u1loop_cnt, u2P));
+
+                            break; // if (s2Err_code == s2Err_code_min) for next u18Ph_dly
+                        }
+                    }
+                    else
+                    {
+                        mcSHOW_ERR_MSG(("u18Phase_SM err!\n"));
+                        #if __ETT__
+                        while (1);
+                        #endif
+                    }
+                }
+            }
+
+            // Error handing when not find transaction
+            if (JmtrInfo.u1TransCnt == u1JmtrPrintCnt)
+            {
+                u18Ph_dly_final = u18PhDlyBackup; //rollback to init settings
+                eDRAMStatus = DRAM_FAIL;
+                mcSHOW_ERR_MSG(("\n[Dramc8PhaseCal] 8-Phase SM_%d is fail (to Default) !!!\n", u18Phase_SM));
+                goto exit;
+            } else if (u18Ph_dly_loop_break == 1)
+                break; // early break
+        }
+    }
+
+exit:
+    mcSHOW_DBG_MSG(("\n[Dramc8PhaseCal] u18Ph_dly_final = %d\n\n", u18Ph_dly_final));
+    //mcDUMP_REG_MSG(("\n[Dramc8PhaseCal] u18Ph_dly_final = %d\n\n", u18Ph_dly_final));
+
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ1, u18Ph_dly_final, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ1, u18Ph_dly_final, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD1, u18Ph_dly_final, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA);
+
+    //restore to orignal value
+    OECKCKE_Control(p, ENABLE);
+    DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+
+    DramcBroadcastOnOff(u4backup_broadcast);
+
+    return eDRAMStatus;
+#endif
+}
+
+#if SIMULATION_SW_IMPED
+/* Impedance have a total of 19 steps, but the HW value mapping to hardware is 0~15, 29~31
+* This function adjusts passed value u1ImpVal by adjust step count "u1AdjStepCnt"
+* After adjustment, if value is 1. Too large (val > 31) -> set to max 31
+*                               2. Too small (val < 0) -> set to min 0
+*                               3. Value is between 15 & 29, adjust accordingly ( 15 < value < 29 )
+* returns: Impedance value after adjustment
+*/
+#if 0
+static U32 SwImpedanceAdjust(U32 u4ImpVal, S8 s1StepCnt)
+{
+    S32 S4ImpedanceTemp = (S32)u4ImpVal;
+
+   // Perform impedance value adjustment
+    S4ImpedanceTemp += s1StepCnt;
+    /* After adjustment, if value is 1. Too large (val > 31) -> set to max 31
+     *                               2. Too small (val < 0) -> set to min 0
+     *                               3. Value is between 15 & 29, adjust accordingly ( 15 < value < 29 )
+     */
+    if ((S4ImpedanceTemp > 15) && (S4ImpedanceTemp < 29)) //Value is between 15 & 29 ( 15 < value < 29)
+    {
+        S4ImpedanceTemp = S4ImpedanceTemp - 16 + 29;
+    }
+
+    if (S4ImpedanceTemp > 31) //Value after adjustment too large -> set to max 31
+    {
+        S4ImpedanceTemp = 31;
+    }
+    else if (S4ImpedanceTemp < 0) //Value after adjustment too small -> set to min 0
+    {
+        S4ImpedanceTemp = 0;
+    }
+
+    return (U32)S4ImpedanceTemp;
+}
+#endif
+//-------------------------------------------------------------------------
+/** vImpCalVrefSel
+ *  Set IMP_VREF_SEL for DRVP, DRVN, Run-time/Tracking
+ *  (Refer to "IMPCAL Settings" document register "RG_RIMP_VREF_SEL" settings)
+ *  @param p                Pointer of context created by DramcCtxCreate.
+ *  @param  freq_region     (enum): pass freq_region (IMP_LOW_FREQ/IMP_HIGH_FREQ) for LP4X
+ *  @param  u1ImpCalStage   (U8): During DRVP, DRVN, run-time/tracking stages
+ *                                some vref_sel values are different
+ */
+//-------------------------------------------------------------------------
+/* Definitions to make IMPCAL_VREF_SEL function more readable */
+#define IMPCAL_STAGE_DRVP     0
+#define IMPCAL_STAGE_DRVN     1
+#define IMPCAL_STAGE_ODTP     2
+#define IMPCAL_STAGE_ODTN     3
+#define IMPCAL_STAGE_TRACKING 4
+
+/* LP4X IMP_VREF_SEL w/o term ==== */
+#define IMP_TRACK_LP4X_LOWFREQ_VREF_SEL  0x37 // for <= DDR3733
+#define IMP_TRACK_LP4X_HIGHFREQ_VREF_SEL  0x3a // for > 3733 and Samsung NT-ODTN
+/* LPDDR5 IMP_VREF_SEL w/o term ==== */
+#define IMP_TRACK_LP5_LOWFREQ_VREF_SEL  0x38 // for <= DDR3733
+#define IMP_TRACK_LP5_HIGHFREQ_VREF_SEL  0x3a // for > 3733 and Samsung NT-ODTN
+
+static const U8 ImpLP4VrefSel[IMP_VREF_MAX][IMP_DRV_MAX] = {
+                  /* DRVP  DRVN  ODTP  ODTN */
+/* IMP_LOW_FREQ */  {0x37, 0x33, 0x00, 0x37},
+/* IMP_HIGH_FREQ */ {0x3a, 0x33, 0x00, 0x3a},
+/* IMP_NT_ODTN */   {0x2a, 0x2a, 0x00, 0x3a}
+};
+
+static const U8 ImpLP5VrefSel[IMP_VREF_MAX][IMP_DRV_MAX] = {
+                  /* DRVP  DRVN  ODTP  ODTN */
+/* IMP_LOW_FREQ */  {0x38, 0x33, 0x00, 0x38},
+/* IMP_HIGH_FREQ */ {0x3a, 0x33, 0x00, 0x3a},
+/* IMP_NT_ODTN */   {0x2a, 0x2a, 0x00, 0x3a}
+};
+
+/* Refer to "IMPCAL Settings" document register "RG_RIMP_VREF_SEL" settings */
+// @Maoauo: DRVP/ODTN for IMP tracking. But DRVN not support IMP tracking. (before La_fite)
+// DRVP/DRVN/ODTN for IMP tracking after Pe_trus
+static void vImpCalVrefSel(DRAMC_CTX_T *p, DRAMC_IMP_T efreq_region, U8 u1ImpCalStage)
+{
+    U8 u1RegTmpValue = 0;
+    U32 u4DrvFld = 0;
+
+    if (p->dram_type == TYPE_LPDDR4X)
+    {
+        if (u1ImpCalStage == IMPCAL_STAGE_TRACKING)
+            u1RegTmpValue = (efreq_region == IMP_LOW_FREQ) ? IMP_TRACK_LP4X_LOWFREQ_VREF_SEL : IMP_TRACK_LP4X_HIGHFREQ_VREF_SEL;
+        else
+            u1RegTmpValue = ImpLP4VrefSel[efreq_region][u1ImpCalStage];
+    }
+    else if (p->dram_type == TYPE_LPDDR5)
+    {
+        if (u1ImpCalStage == IMPCAL_STAGE_TRACKING)
+            u1RegTmpValue = (efreq_region == IMP_LOW_FREQ) ? IMP_TRACK_LP5_LOWFREQ_VREF_SEL : IMP_TRACK_LP5_HIGHFREQ_VREF_SEL;
+        else
+            u1RegTmpValue = ImpLP5VrefSel[efreq_region][u1ImpCalStage];
+    }
+    else
+    {
+        mcSHOW_ERR_MSG(("[vImpCalVrefSel] Warnning: Need confirm DRAM type for IMP_VREF_SEL !!!\n"));
+        #if __ETT__
+        while(1);
+        #endif
+    }
+
+    switch (u1ImpCalStage)
+    {
+        case IMPCAL_STAGE_DRVP:
+            u4DrvFld = SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP;
+            break;
+        case IMPCAL_STAGE_DRVN:
+            u4DrvFld = SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN;
+            break;
+        case IMPCAL_STAGE_ODTN:
+            u4DrvFld = SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN;
+            break;
+        case IMPCAL_STAGE_TRACKING:
+            break;
+        default:
+            mcSHOW_ERR_MSG(("[vImpCalVrefSel] Warnning: Need confirm u1ImpCalStage for SW IMP Calibration !!!\n"));
+            break;
+    }
+
+    // dbg msg after vref_sel selection
+    mcSHOW_DBG_MSG3(("[vImpCalVrefSel] IMP_VREF_SEL 0x%x, IMPCAL stage:%u, freq_region:%u\n",
+                      u1RegTmpValue, u1ImpCalStage, efreq_region));
+
+    /* Set IMP_VREF_SEL register field's value */
+    if (u1ImpCalStage == IMPCAL_STAGE_TRACKING) {
+        /* SEL_DVRP/ODTN shall diff by freq, value of them are equal */
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12), u1RegTmpValue, SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12), u1RegTmpValue, SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN);
+    } else {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12), u1RegTmpValue, u4DrvFld);
+    }
+
+    return;
+}
+
+void DramcSwImpedanceSaveRegister(DRAMC_CTX_T *p, U8 ca_freq_option, U8 dq_freq_option, U8 save_to_where)
+{
+    U32 backup_broadcast;
+    //U8 u1Hysteresis;
+
+    backup_broadcast = GetDramcBroadcast();
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+
+    /* Save RIMP_VREF_SEL by shuffle. Will be broadcasted to ALL CH even if unused */
+    vImpCalVrefSel(p, dq_freq_option, IMPCAL_STAGE_TRACKING);
+
+    //DQ
+    vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING1 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][DRVP], SHU_MISC_DRVING1_DQDRVP2) | P_Fld(gDramcImpedanceResult[dq_freq_option][DRVN], SHU_MISC_DRVING1_DQDRVN2));
+    vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING2 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][DRVP], SHU_MISC_DRVING2_DQDRVP1) | P_Fld(gDramcImpedanceResult[dq_freq_option][DRVN], SHU_MISC_DRVING2_DQDRVN1));
+    vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][ODTP], SHU_MISC_DRVING3_DQODTP2) | P_Fld(gDramcImpedanceResult[dq_freq_option][ODTN], SHU_MISC_DRVING3_DQODTN2));
+    vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING4 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][ODTP], SHU_MISC_DRVING4_DQODTP1) | P_Fld(gDramcImpedanceResult[dq_freq_option][ODTN], SHU_MISC_DRVING4_DQODTN1));
+
+    //DQS
+    #if SUPPORT_HYNIX_RX_DQS_WEAK_PULL
+    if (p->vendor_id == VENDOR_HYNIX)
+    {  U32 temp_value[4];
+        int i;
+        for(i=0; i<4; i++)
+        {
+            temp_value[i] = SwImpedanceAdjust(gDramcImpedanceResult[dq_freq_option][i], 2);
+        }
+         vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING1 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(temp_value[0], SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(temp_value[1], SHU_MISC_DRVING1_DQSDRVN2));
+         vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING1 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(temp_value[0], SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(temp_value[1], SHU_MISC_DRVING1_DQSDRVN1));
+         vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(temp_value[2], SHU_MISC_DRVING3_DQSODTP2) | P_Fld(temp_value[3], SHU_MISC_DRVING3_DQSODTN2));
+         vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(temp_value[2], SHU_MISC_DRVING3_DQSODTP) | P_Fld(temp_value[3], SHU_MISC_DRVING3_DQSODTN));
+    }
+    else
+    #endif
+    {
+        vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING1 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][DRVP], SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(gDramcImpedanceResult[dq_freq_option][DRVN], SHU_MISC_DRVING1_DQSDRVN2));
+        vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING1 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][DRVP], SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(gDramcImpedanceResult[dq_freq_option][DRVN], SHU_MISC_DRVING1_DQSDRVN1));
+        vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][ODTP], SHU_MISC_DRVING3_DQSODTP2) | P_Fld(gDramcImpedanceResult[dq_freq_option][ODTN], SHU_MISC_DRVING3_DQSODTN2));
+        vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][ODTP], SHU_MISC_DRVING3_DQSODTP) | P_Fld(gDramcImpedanceResult[dq_freq_option][ODTN], SHU_MISC_DRVING3_DQSODTN));
+    }
+
+    //CMD & CLK
+    vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING2 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[ca_freq_option][DRVP], SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(gDramcImpedanceResult[ca_freq_option][DRVN], SHU_MISC_DRVING2_CMDDRVN2));
+    vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING2 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[ca_freq_option][DRVP], SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(gDramcImpedanceResult[ca_freq_option][DRVN], SHU_MISC_DRVING2_CMDDRVN1));
+    vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING4 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[ca_freq_option][ODTP], SHU_MISC_DRVING4_CMDODTP2) | P_Fld(gDramcImpedanceResult[ca_freq_option][ODTN], SHU_MISC_DRVING4_CMDODTN2));
+    vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING4 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[ca_freq_option][ODTP], SHU_MISC_DRVING4_CMDODTP1) | P_Fld(gDramcImpedanceResult[ca_freq_option][ODTN], SHU_MISC_DRVING4_CMDODTN1));
+
+    //RG_TX_*RCKE_DRVP/RG_TX_*RCKE_DRVN doesn't set, so set 0xA first
+    //@Maoauo confirm, RG no function
+    //vIO32WriteFldAlign((DDRPHY_SHU_CA_CMD11 + save_to_where * SHU_GRP_DDRPHY_OFFSET), gDramcImpedanceResult[ca_freq_option][DRVP], SHU_CA_CMD11_RG_TX_ARCKE_DRVP);
+    //vIO32WriteFldAlign((DDRPHY_SHU_CA_CMD11 + save_to_where * SHU_GRP_DDRPHY_OFFSET), gDramcImpedanceResult[ca_freq_option][DRVN], SHU_CA_CMD11_RG_TX_ARCKE_DRVN);
+
+    //CKE
+    // CKE is full swing.
+    // LP4/LP4X set DRVP/DRVN as LP3's default value
+    // DRVP=8 -> 0xA for 868 by Alucary Chen
+    // DRVN=9 -> 0xA for 868 by Alucary Chen
+    //DRVP[4:0] = RG_TX_ARCMD_PU_PRE<1:0>, RG_TX_ARCLK_DRVN_PRE<2:0> for La_fite only
+    //@Darren-vIO32WriteFldAlign((DDRPHY_REG_SHU_CA_CMD3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), (8>>3)&0x3, SHU_CA_CMD3_RG_TX_ARCMD_PU_PRE); //Darren need confirm
+    //@Darren-vIO32WriteFldAlign((DDRPHY_REG_SHU_CA_CMD0 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 8&0x7, SHU_CA_CMD0_RG_TX_ARCLK_DRVN_PRE); //Darren need confirm
+    //DRVN[4:0] = RG_ARCMD_REV<12:8>
+    //@Darren-vIO32WriteFldAlign_All((DDRPHY_SHU_CA_DLL2 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 9, SHU_CA_DLL2_RG_TX_ARCKE_DRVN_B0);
+    #if (fcFOR_CHIP_ID == fcA60868) // for 868 CS and CKE control together
+    vIO32WriteFldAlign((DDRPHY_REG_MISC_SHU_DRVING8 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 0xA, MISC_SHU_DRVING8_CS_DRVP);
+    vIO32WriteFldAlign((DDRPHY_REG_MISC_SHU_DRVING8 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 0xA, MISC_SHU_DRVING8_CS_DRVN);
+    #elif (fcFOR_CHIP_ID == fc8195)
+    // @Darren, confirm with ACD Alucary,
+    // MISC_SHU_DRVING8_CS_DRVP & MISC_SHU_DRVING8_CS_DRVN -> DA_TX_ARCKE_DRVP_C0[4:0]   & DA_TX_ARCKE_DRVN_C0[4:0]
+    vIO32WriteFldAlign((DDRPHY_REG_MISC_SHU_DRVING8 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 0xF, MISC_SHU_DRVING8_CS_DRVP);
+    vIO32WriteFldAlign((DDRPHY_REG_MISC_SHU_DRVING8 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 0x14, MISC_SHU_DRVING8_CS_DRVN);
+    #endif
+
+    DramcBroadcastOnOff(backup_broadcast);
+}
+
+#if IMPEDANCE_HW_CALIBRATION
+static void Dramc_Hw_ImpedanceCal(DRAMC_CTX_T *p, DRAMC_IMP_T freq_region)
+{
+    U8 u1DrvType = 0;
+    U32 u4DRVP_Result = 0xff, u4ODTN_Result = 0xff, u4DRVN_Result = 0xff;
+
+    vAutoRefreshSwitch(p, ENABLE);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_CONF0), 0, SHU_CONF0_PBREFEN);
+
+    for (u1DrvType = DRVP; u1DrvType < IMP_DRV_MAX; u1DrvType++) // Calibration sequence for DRVP, DRVN and ODTN
+    {
+        if (u1DrvType == ODTP) // no use, skip ODTP
+            continue;
+
+        /* Set IMP_VREF_SEL value for DRVP/DRVN and ODTN */
+        vImpCalVrefSel(p, freq_region, u1DrvType);
+    }
+
+    ImpedanceTracking_DisImpHw_Setting(p, DISABLE);
+    //IMPCALCNT should be bigger than 0x4 (set as minimum value to save calibration time)
+    //clock_period *IMPCAL_CHKCYCLE* 16 should be bigger than 200ns.
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), P_Fld(4, SHU_MISC_IMPCAL1_IMPCALCNT) | P_Fld(1, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE));
+    DramcImpedanceTrackingEnable(p);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), 0, MISC_IMPCAL_IMPCAL_ECO_OPT); //No need to wait slave channel's handshake signal in calibration
+
+    mcDELAY_US(16); //Need to wait IMPCALCNT times of all-bank refresh
+
+    u4DRVN_Result = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_DRVNDQ_SAVE_1);
+    u4DRVP_Result = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_DRVPDQ_SAVE_1);
+    u4ODTN_Result = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_ODTNDQ_SAVE_1);
+
+    //DRVP=DRVP_FINAL
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), u4DRVP_Result, SHU_MISC_IMPCAL1_IMPDRVP);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), u4DRVN_Result, SHU_MISC_IMPCAL1_IMPDRVN);
+
+    mcSHOW_DBG_MSG(("[HwImpedanceCal] DRVP=%d, DRVN=%d, ODTN=%d\n", u4DRVP_Result, u4DRVN_Result, u4ODTN_Result));
+
+    gDramcImpedanceResult[freq_region][DRVP] = u4DRVP_Result;
+    gDramcImpedanceResult[freq_region][DRVN] = u4DRVN_Result;
+    gDramcImpedanceResult[freq_region][ODTP] = 0;
+    gDramcImpedanceResult[freq_region][ODTN] = u4ODTN_Result;
+
+    //vAutoRefreshSwitch(p, DISABLE);
+
+}
+
+#else
+static U32 DramcSwImpCalResult(DRAMC_CTX_T *p, const char *drvType, U32 u4Fld)
+{
+    U32 u4ImpxDrv = 0, u4ImpCalResult = 0;
+    U32 u4CheckImpChange = (u4Fld == SHU_MISC_IMPCAL1_IMPDRVP)? 1: 0;
+
+    for (u4ImpxDrv = 0; u4ImpxDrv < 32; u4ImpxDrv++)
+    {
+#if 0 // for A60868 no need
+        if (u4ImpxDrv == 16) //0~15, 29~31
+            u4ImpxDrv = 29;
+#endif
+
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), u4ImpxDrv, u4Fld);
+        mcDELAY_US(1);
+        u4ImpCalResult = u4IO32ReadFldAlign((DDRPHY_REG_MISC_PHY_RGS_CMD), MISC_PHY_RGS_CMD_RGS_RIMPCALOUT);
+        mcSHOW_DBG_MSG2(("OCD %s=%d ,CALOUT=%d\n", drvType, u4ImpxDrv, u4ImpCalResult));
+
+        if (u4ImpCalResult == u4CheckImpChange)//first found
+        {
+            mcSHOW_DBG_MSG2(("\nOCD %s calibration OK! %s=%d\n\n", drvType, drvType, u4ImpxDrv));
+            break;
+        }
+    }
+
+    if (u4ImpxDrv == 32) // Can't find SwImp drv results
+    {
+        u4ImpxDrv = 31;
+        mcSHOW_DBG_MSG2(("\nOCD %s calibration FAIL! %s=%d\n\n", drvType, drvType, u4ImpxDrv));
+    }
+
+    return u4ImpxDrv;
+}
+
+static void Dramc_Sw_ImpedanceCal(DRAMC_CTX_T *p, DRAMC_IMP_T freq_region)
+{
+    U8 u1DrvType = 0, u1CALI_ENP = 0, u1CALI_ENN = 0;
+    U32 u4DRVP_Result = 0xff, u4ODTN_Result = 0xff, u4DRVN_Result = 0xff;
+    U32 u4SwImpCalResult = 0, u4DrvFld = 0;
+    const char *drvStr = "NULL";
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), 1, MISC_IMPCAL_IMPCAL_CALI_EN);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), P_Fld(0, SHU_MISC_IMPCAL1_IMPDRVN) | P_Fld(0, SHU_MISC_IMPCAL1_IMPDRVP));
+
+    //LP4X: ODTN/DRVN/DRVP calibration start
+    for (u1DrvType = DRVP; u1DrvType < IMP_DRV_MAX; u1DrvType++) // Calibration sequence for DRVP, DRVN and ODTN
+    {
+        if (u1DrvType == ODTP) // no use, skip ODTP
+            continue;
+
+        /* Set IMP_VREF_SEL value for DRVP/DRVN and ODTN */
+        vImpCalVrefSel(p, freq_region, u1DrvType);
+
+        switch (u1DrvType)
+        {
+            case DRVP:
+                drvStr = "DRVP";
+                u1CALI_ENP = 0x1;
+                u1CALI_ENN = 0x0;
+                u4DrvFld = SHU_MISC_IMPCAL1_IMPDRVP;
+                u4DRVP_Result = 0;
+                break;
+            case DRVN:
+            case ODTN:
+                drvStr = (u1DrvType == DRVN)? "DRVN" : "ODTN";
+                u1CALI_ENP = 0x0;
+                u1CALI_ENN = (u1DrvType == DRVN)? 0x0: 0x1; // 0x1 change to ODTN path
+                u4DrvFld = SHU_MISC_IMPCAL1_IMPDRVN;
+                break;
+            default:
+                mcSHOW_ERR_MSG(("[DramcSwImpedanceCal] Warnning: Need confirm u1DrvType for SW IMP Calibration !!!\n"));
+                break;
+        }
+
+        // @A60868 for DRVn/p and ODTn select
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), u1CALI_ENP, MISC_IMPCAL_IMPCAL_CALI_ENP);  //MISC_IMP_CTRL1_RG_IMP_OCD_PUCMP_EN move to CALI_ENP
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), u1CALI_ENN, MISC_IMPCAL_IMPCAL_CALI_ENN);  //MISC_IMP_CTRL1_RG_RIMP_ODT_EN move to CALI_ENN
+
+        mcSHOW_DBG_MSG2(("\n\n\tK %s\n", drvStr));
+
+        //DRVP=DRVP_FINAL
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), u4DRVP_Result, SHU_MISC_IMPCAL1_IMPDRVP);  //PUCMP_EN move to CALI_ENP
+
+        //If RGS_TX_OCD_IMPCALOUTX=1
+        //RG_IMPX_DRVN++;
+        //Else save RG_IMPX_DRVN value and assign to DRVN
+        u4SwImpCalResult = DramcSwImpCalResult(p, drvStr, u4DrvFld);
+
+        switch (u1DrvType)
+        {
+            case DRVP:
+                u4DRVP_Result = u4SwImpCalResult;
+                break;
+            case DRVN:
+                u4DRVN_Result = u4SwImpCalResult;
+                break;
+            case ODTN:
+                u4ODTN_Result = u4SwImpCalResult;
+                break;
+            default:
+                mcSHOW_ERR_MSG(("[DramcSwImpedanceCal] Warnning: Need confirm u4SwImpCalResult for SW IMP Calibration !!!\n"));
+                break;
+        }
+    }
+
+    mcSHOW_DBG_MSG(("[SwImpedanceCal] DRVP=%d, DRVN=%d, ODTN=%d\n", u4DRVP_Result, u4DRVN_Result, u4ODTN_Result));
+
+    gDramcImpedanceResult[freq_region][DRVP] = u4DRVP_Result;
+    gDramcImpedanceResult[freq_region][DRVN] = u4DRVN_Result;
+    gDramcImpedanceResult[freq_region][ODTP] = 0;
+    gDramcImpedanceResult[freq_region][ODTN] = u4ODTN_Result;
+
+}
+#endif
+
+DRAM_STATUS_T DramcImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_region)
+{
+    //U32 u4BaklReg_DDRPHY_MISC_IMP_CTRL0, u4BaklReg_DDRPHY_MISC_IMP_CTRL1;
+    //U32 u4BaklReg_DRAMC_REG_IMPCAL;
+    U8 backup_channel;
+    U32 backup_broadcast;
+    U8 u1Drv05 = 0, u1DDR4 = 0;
+
+    U32 u4RegBackupAddress[] =
+    {
+        (DDRPHY_REG_MISC_IMPCAL),
+        #if IMPEDANCE_HW_CALIBRATION
+        (DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHB_ADDR),
+        (DRAMC_REG_ADDR(DRAMC_REG_DDRCOMMON0)),
+        (DRAMC_REG_DRAMC_PD_CTRL),
+        (DRAMC_REG_DRAMC_PD_CTRL+ SHIFT_TO_CHB_ADDR),
+        #if (CHANNEL_NUM > 2)
+        (DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHC_ADDR),
+        (DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHD_ADDR),
+        #endif
+        (DDRPHY_REG_MISC_CTRL0),
+        (DDRPHY_REG_MISC_CTRL0 + SHIFT_TO_CHB_ADDR),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_DRVING1)),
+        (DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_DRVING2)),
+        (DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0)),
+        #endif
+    };
+
+    backup_broadcast = GetDramcBroadcast();
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+    //default set FAIL
+    vSetCalibrationResult(p, DRAM_CALIBRATION_SW_IMPEDANCE, DRAM_FAIL);
+
+#if VENDER_JV_LOG
+    vPrintCalibrationBasicInfo_ForJV(p);
+#else
+    vPrintCalibrationBasicInfo(p);
+#endif
+
+    mcSHOW_DBG_MSG(("[DramcImpedenceCal]\n"));
+
+    //Suspend: DA_RIMP_DMSUS=1
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_LP_CTRL, P_Fld(0x0, MISC_LP_CTRL_RG_ARDMSUS_10) | \
+                        P_Fld(0x0, MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL) | \
+                        P_Fld(0x0, MISC_LP_CTRL_RG_RIMP_DMSUS_10) | \
+                        P_Fld(0x0, MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL));
+    //Disable IMP HW Tracking
+    //Hw Imp tracking disable for all channels Because SwImpCal will be K again when resume from DDR reserved mode
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 0, MISC_IMPCAL_IMPCAL_HW);
+    backup_channel = p->channel;
+    vSetPHY2ChannelMapping(p, CHANNEL_A);
+
+    //Register backup
+    //u4BaklReg_DDRPHY_MISC_IMP_CTRL0 = u4IO32Read4B((DDRPHY_MISC_IMP_CTRL0));
+    //u4BaklReg_DDRPHY_MISC_IMP_CTRL1 = u4IO32Read4B((DDRPHY_MISC_IMP_CTRL1));
+    //u4BaklReg_DRAMC_REG_IMPCAL = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL));
+    DramcBackupRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress));
+
+#if IMPEDANCE_HW_CALIBRATION
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DDRCOMMON0), 1, DDRCOMMON0_LPDDR4EN);
+    vIO32WriteFldMulti_All(DRAMC_REG_DRAMC_PD_CTRL, P_Fld(1, DRAMC_PD_CTRL_PHYCLKDYNGEN)\
+                                                   | P_Fld(1, DRAMC_PD_CTRL_DCMEN));
+#endif
+
+    //RG_IMPCAL_VREF_SEL (now set in vImpCalVrefSel())
+    //RG_IMPCAL_LP3_EN=0, RG_IMPCAL_LP4_EN=1
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMP_CTRL1), 0, MISC_IMP_CTRL1_RG_RIMP_PRE_EN);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), P_Fld(0, MISC_IMPCAL_IMPCAL_CALI_ENN) | P_Fld(1, MISC_IMPCAL_IMPCAL_IMPPDP) | \
+                                      P_Fld(1, MISC_IMPCAL_IMPCAL_IMPPDN)); //RG_RIMP_BIAS_EN and RG_RIMP_VREF_EN move to IMPPDP and IMPPDN
+#if __LP5_COMBO__
+    if (is_lp5_family(p))
+        u1DDR4 = 0;
+    else //LPDDR4
+#endif
+        u1DDR4 = 1;
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMP_CTRL1), P_Fld(1, MISC_IMP_CTRL1_RG_IMP_EN) | \
+                        P_Fld(0, MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL) | \
+                        P_Fld(1, MISC_IMP_CTRL1_RG_RIMP_VREF_EN) | \
+                        P_Fld(u1DDR4, MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL));
+    mcDELAY_US(1);
+
+    //RIMP_DRV05 for LP4/5
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12), u1Drv05, SHU_CA_CMD12_RG_RIMP_DRV05);
+
+    #if IMPEDANCE_HW_CALIBRATION
+        Dramc_Hw_ImpedanceCal(p, freq_region);
+    #else
+        Dramc_Sw_ImpedanceCal(p, freq_region);
+    #endif
+    //Register Restore
+    DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+    //vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), u4BaklReg_DRAMC_REG_IMPCAL);
+    //vIO32Write4B((DDRPHY_MISC_IMP_CTRL0), u4BaklReg_DDRPHY_MISC_IMP_CTRL0);
+    //vIO32Write4B((DDRPHY_MISC_IMP_CTRL1), u4BaklReg_DDRPHY_MISC_IMP_CTRL1);
+
+/*** default value if K fail
+    LP3:  DRVP=8, DRVN=9
+    LP4:  DRVP=6, DRVN=9, ODTN=14
+    LP4X(UT): DRVP=12, DRVN=9
+    LP4X(T):  DRVP=5, DRVN=9, ODTN=14
+    LP4P: DRVP=8, DRVN=10
+***/
+
+    #if 0//HYNIX_IMPX_ADJUST
+    if (u1Para)
+    {
+        u4ODTN_Result = ImpedanceAdjustment_Hynix(u4ODTN_Result, u1Para);
+    }
+    #endif
+
+#if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION
+    {
+        U8 u1drv;
+        {
+            for (u1drv = 0; u1drv < 4; u1drv++)
+            {
+                {
+                    gDramcImpedanceResult[freq_region][u1drv] = p->pSavetimeData->u1SwImpedanceResule[freq_region][u1drv];
+                    vSetCalibrationResult(p, DRAM_CALIBRATION_SW_IMPEDANCE, DRAM_FAST_K);
+                }
+            }
+        }
+    }
+#endif
+
+    mcSHOW_DBG_MSG(("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d\n", freq_region, gDramcImpedanceResult[freq_region][DRVP],
+                                         gDramcImpedanceResult[freq_region][DRVN], gDramcImpedanceResult[freq_region][ODTN]));
+
+#if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
+    if ((p->dram_type == TYPE_LPDDR4) && (freq_region == 0))
+    {
+        gDramcImpedanceResult[freq_region][DRVP] = SwImpedanceAdjust(gDramcImpedanceResult[freq_region][DRVP], gDramcSwImpedanceAdjust[freq_region][DRVP]);
+        gDramcImpedanceResult[freq_region][DRVN] = SwImpedanceAdjust(gDramcImpedanceResult[freq_region][DRVN], gDramcSwImpedanceAdjust[freq_region][ODTN]);
+    }
+    else
+    {
+        gDramcImpedanceResult[freq_region][DRVP] = SwImpedanceAdjust(gDramcImpedanceResult[freq_region][DRVP], gDramcSwImpedanceAdjust[freq_region][DRVP]);
+        gDramcImpedanceResult[freq_region][ODTN] = SwImpedanceAdjust(gDramcImpedanceResult[freq_region][ODTN], gDramcSwImpedanceAdjust[freq_region][ODTN]);
+    }
+
+    mcSHOW_DBG_MSG(("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d (After Adjust)\n", freq_region, gDramcImpedanceResult[freq_region][DRVP],
+                                         gDramcImpedanceResult[freq_region][DRVN], gDramcImpedanceResult[freq_region][ODTN]));
+#endif
+
+#if 0
+    //YingYu: only check for freq_region = 0 (un-term, DQ)
+    if (gDramcSwImpedanceResult[freq_region][DRVP] >= 31 && (freq_region == 0) ) {
+        mcSHOW_DBG_MSG(("SLT_BIN2\n"));
+        while (1);
+    }
+#else
+    // Alucary @ 2019/8/21
+    // freq_region == 0
+    // DRVP 0x1~0x16
+    // DRVN 10~23
+    // ODTN 0x3~0x13
+    if (freq_region==0)
+    {
+        if (!(gDramcImpedanceResult[freq_region][DRVP] >= 1 && gDramcImpedanceResult[freq_region][DRVP] <= 0x16) ||
+            !(gDramcImpedanceResult[freq_region][DRVN] >= 10 && gDramcImpedanceResult[freq_region][DRVN] <= 23) ||
+            !(gDramcImpedanceResult[freq_region][ODTN] >= 3 && gDramcImpedanceResult[freq_region][ODTN] <= 0x13)) {
+            #if defined(SLT)
+            mcSHOW_ERR_MSG(("[DramcInit] SLT_BIN2\n"));
+            while (1);
+            #else
+                mcSHOW_ERR_MSG(("[Warning] freq_region = %d, Unexpected value for impedance calibration\n", freq_region));
+                #if __ETT__
+                    while (1);
+                #endif
+            #endif
+        }else{
+            vSetCalibrationResult(p, DRAM_CALIBRATION_SW_IMPEDANCE, DRAM_OK);
+        }
+    }
+    else
+    {   // freq_region == 1
+        // DRVP 1~24 @ 2020/4/7
+        // 4266 VOH is K 395mV
+        // SS 130 LV DRVP 395mV will got 22
+        // need add 2 for margin
+        // so spec change to 24
+        // DRVN 10~30
+        // ODTN 3~12
+        if (!(gDramcImpedanceResult[freq_region][DRVP] >= 1 && gDramcImpedanceResult[freq_region][DRVP] <= 24) ||
+            !(gDramcImpedanceResult[freq_region][DRVN] >= 10 && gDramcImpedanceResult[freq_region][DRVN] <= 30) ||
+            !(gDramcImpedanceResult[freq_region][ODTN] >= 3 && gDramcImpedanceResult[freq_region][ODTN] <= 12)) {
+            #if defined(SLT)
+            mcSHOW_ERR_MSG(("[DramcInit] SLT_BIN2\n"));
+            while (1);
+            #else
+                mcSHOW_ERR_MSG(("[Warning] freq_region = %d, Unexpected value for impedance calibration\n", freq_region));
+                #if __ETT__
+                    while (1);
+                #endif
+            #endif
+        }else{
+            vSetCalibrationResult(p, DRAM_CALIBRATION_SW_IMPEDANCE, DRAM_OK);
+        }
+    }
+#endif
+
+#if PIN_CHECK_TOOL
+    if((gDramcImpedanceResult[freq_region][ODTN] ==0)||(gDramcImpedanceResult[freq_region][ODTN] >=31))
+    {
+        mcSHOW_DBG_MSG(("[WARNING] freq_region = %d, ODTN = %d ==> unexpect value\n", freq_region, gDramcImpedanceResult[freq_region][ODTN]));
+        PINInfo_flashtool.IMP_ERR_FLAG |= (0x1<<(freq_region+ODTN));
+    }
+    else if((gDramcImpedanceResult[freq_region][DRVP] ==0)||(gDramcImpedanceResult[freq_region][DRVP] >=31))
+    {
+        mcSHOW_DBG_MSG(("[WARNING] freq_region = %d, DRVP = %d ==> unexpect value\n", freq_region, gDramcImpedanceResult[freq_region][DRVP]));
+        PINInfo_flashtool.IMP_ERR_FLAG |= (0x1<<(freq_region+DRVP));
+    }
+    else if((gDramcImpedanceResult[freq_region][DRVN] ==0)||(gDramcImpedanceResult[freq_region][DRVN] >=31))
+    {
+        mcSHOW_DBG_MSG(("[WARNING] freq_region = %d, DRVN = %d ==> unexpect value\n", freq_region, gDramcImpedanceResult[freq_region][DRVN]));
+        PINInfo_flashtool.IMP_ERR_FLAG |= (0x1<<(freq_region+DRVN));
+    }
+#endif
+
+    mcSHOW_DBG_MSG4(("[DramcImpedanceCal] Done\n\n"));
+
+    vSetPHY2ChannelMapping(p, backup_channel);
+    DramcBroadcastOnOff(backup_broadcast);
+
+    return DRAM_OK;
+}
+#endif //SIMULATION_SW_IMPED
+
+#if ENABLE_WRITE_DBI || TX_K_DQM_WITH_WDBI
+void DramcWriteShiftMCKForWriteDBI(DRAMC_CTX_T *p, S8 iShiftMCK)
+{
+    U8 ucDataRateDivShift = 0;
+    S8 s1UIMove = 0;
+
+    ucDataRateDivShift = u1MCK2UI_DivShift(p);
+    s1UIMove = iShiftMCK * (S8)(1 << ucDataRateDivShift);
+    ShiftDQUI(p, s1UIMove, ALL_BYTES);
+}
+#endif
+
+#if ENABLE_DUTY_SCAN_V2
+
+#define DutyPrintAllLog         0
+
+#define DUTY_OFFSET_START -28
+#define DUTY_OFFSET_END 28
+#define DUTY_OFFSET_STEP 4
+
+#define CLOCK_PI_START 0
+#define CLOCK_PI_END 63
+
+#if FOR_DV_SIMULATION_USED
+#define CLOCK_PI_STEP 8
+#else
+#define CLOCK_PI_STEP 2
+#endif
+
+#define ClockDutyFailLowerBound 4500    // 45%
+#define ClockDutyFailUpperBound 5500    // 55%
+#define ClockDutyMiddleBound    5000    // 50%
+
+/*
+* duty form smallest to biggest
+* 011111->011110->...->000001-->000000=100000->100001-->...->111111
+*/
+static U8 DramcDutyDelayRGSettingConvert(DRAMC_CTX_T *p, S8 scDutyDelay,
+    U8 *tDly)
+{
+    U8 tDelay;
+
+    if (scDutyDelay < 0)
+    {
+        tDelay = -scDutyDelay;
+    }
+    else if (scDutyDelay > 0)
+    {
+        tDelay = scDutyDelay + (1 << 5);
+    }
+    else
+    {
+        tDelay = 0;
+    }
+
+    *tDly = tDelay;
+    return tDelay;
+}
+
+static void DramcClockDutySetClkDelayCell(DRAMC_CTX_T *p, S8 *scDutyDelay)
+{
+    U8 u1ShuffleIdx = 0;
+    U32 save_offset;
+    U8 tDelay;
+
+    DramcDutyDelayRGSettingConvert(p, scDutyDelay[0], &tDelay);
+
+#if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ
+    for(u1ShuffleIdx = 0; u1ShuffleIdx<DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
+#endif
+    {
+        save_offset = u1ShuffleIdx * SHU_GRP_DDRPHY_OFFSET;
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_TXDUTY + save_offset),
+            P_Fld(tDelay, SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY));
+    }
+}
+
+static void DQSDutyScan_SetDqsDelayCell(DRAMC_CTX_T *p, S8 *scDutyDelay)
+{
+    U8 u1ShuffleIdx = 0, u1DQSIdx;
+    U32 save_offset;
+    U8 tDelay[2];
+
+//    mcSHOW_DBG_MSG(("CH%d, Final DQS0 duty delay cell = %d\n", p->channel, scDutyDelay[0]));
+//    mcSHOW_DBG_MSG(("CH%d, Final DQS1 duty delay cell = %d\n", p->channel, scDutyDelay[1]));
+
+    for(u1DQSIdx=0; u1DQSIdx<2; u1DQSIdx++)
+    {
+        DramcDutyDelayRGSettingConvert(p, scDutyDelay[u1DQSIdx], &(tDelay[u1DQSIdx]));
+    }
+
+#if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ
+    for(u1ShuffleIdx = 0; u1ShuffleIdx<DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
+#endif
+    {
+        {
+            for(u1DQSIdx = 0; u1DQSIdx<2; u1DQSIdx++)
+            {
+                save_offset = u1ShuffleIdx * SHU_GRP_DDRPHY_OFFSET + u1DQSIdx*DDRPHY_AO_B0_B1_OFFSET;
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + save_offset,
+                    P_Fld(tDelay[u1DQSIdx], SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0));
+            }
+        }
+    }
+}
+
+#if __LP5_COMBO__
+static void WCKDutyScan_SetWCKDelayCell(DRAMC_CTX_T *p, S8 *scDutyDelay)
+{
+    U8 u1ShuffleIdx = 0, u1DQSIdx, u1RankIdx = 0;
+    U32 save_offset;
+    U8 tDelay[2];
+
+    for(u1DQSIdx=0; u1DQSIdx<2; u1DQSIdx++)
+    {
+        DramcDutyDelayRGSettingConvert(p, scDutyDelay[u1DQSIdx], &(tDelay[u1DQSIdx]));
+    }
+
+#if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ
+    for(u1ShuffleIdx = 0; u1ShuffleIdx<DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
+#endif
+    {
+        {
+            for(u1DQSIdx = 0; u1DQSIdx<2; u1DQSIdx++)
+            {
+                save_offset = u1ShuffleIdx * SHU_GRP_DDRPHY_OFFSET + u1DQSIdx*DDRPHY_AO_B0_B1_OFFSET;
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + save_offset,
+                    P_Fld(tDelay[u1DQSIdx], SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0));
+            }
+        }
+    }
+}
+#endif
+
+#if APPLY_DQDQM_DUTY_CALIBRATION
+static void DQDQMDutyScan_SetDQDQMDelayCell(DRAMC_CTX_T *p, U8 u1ChannelIdx, S8 *scDutyDelay, U8 k_type)
+{
+    U8 u1ShuffleIdx = 0, u1DQSIdx;
+    U32 save_offset;
+    U8 tDelay[2];
+
+    for(u1DQSIdx=0; u1DQSIdx<2; u1DQSIdx++)
+    {
+        DramcDutyDelayRGSettingConvert(p, scDutyDelay[u1DQSIdx], &(tDelay[u1DQSIdx]));
+    }
+
+#if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ
+    for(u1ShuffleIdx = 0; u1ShuffleIdx<DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
+#endif
+    {
+        for(u1DQSIdx = 0; u1DQSIdx<2; u1DQSIdx++)
+        {
+            save_offset = u1ShuffleIdx * SHU_GRP_DDRPHY_OFFSET + u1DQSIdx*DDRPHY_AO_B0_B1_OFFSET;
+
+            if (k_type == DutyScan_Calibration_K_DQ)
+            {
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + save_offset,
+                    P_Fld(tDelay[u1DQSIdx], SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0));
+            }
+
+            if (k_type == DutyScan_Calibration_K_DQM)
+            {
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + save_offset,
+                    P_Fld(tDelay[u1DQSIdx], SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0));
+            }
+        }
+    }
+}
+
+#if 0
+void DQDQMDutyScan_CopyDQRG2DQMRG(DRAMC_CTX_T *p)
+{
+    U8 u1ShuffleIdx = 0, u1DQSIdx, u1RankIdx = 0;
+    U32 save_offset;
+    U8 ucDQDQMDelay;
+    U8 ucRev_DQDQM_Bit0, ucRev_DQDQM_Bit1;
+
+#if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ
+    for(u1ShuffleIdx = 0; u1ShuffleIdx<DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
+#endif
+    {
+            for(u1DQSIdx = 0; u1DQSIdx<2; u1DQSIdx++)
+            {
+            save_offset = u1ShuffleIdx * SHU_GRP_DDRPHY_OFFSET + u1DQSIdx*DDRPHY_AO_B0_B1_OFFSET_0X80;
+
+            ucDQDQMDelay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DQ3) + save_offset, SHU_B0_DQ3_RG_ARDQ_DUTYREV_B0_DQ_DLY);
+            ucRev_DQDQM_Bit0 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DQ3) + save_offset, SHU_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0_BIT0);
+            ucRev_DQDQM_Bit1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DQ3) + save_offset, SHU_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0_BIT0);
+
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DQ3) + save_offset, P_Fld(ucDQDQMDelay, SHU_B0_DQ3_RG_ARDQ_DUTYREV_B0_DQM_DLY)
+                                                                    | P_Fld(ucRev_DQDQM_Bit0, SHU_B0_DQ3_RG_TX_ARDQS0_PU_B0_BIT0)
+                                                                    | P_Fld(ucRev_DQDQM_Bit1, SHU_B0_DQ3_RG_TX_ARDQS0_PU_B0_BIT1));
+            }
+        }
+    }
+#endif
+#endif
+
+
+// offset is not related to DQ/DQM/DQS
+// we have a circuit to measure duty, But this circuit is not very accurate
+// so we need to K offset of this circuit first
+// After we got this offset, then we can use it to measure duty
+// this offset can measure DQ/DQS/DQM, and every byte has this circuit, too.
+// B0/B1/CA all have one circuit.
+// CA's circuit can measure CLK duty
+// B0/B1's can measure DQ/DQM/DQS duty
+#if 0 //[FOR_CHROMEOS]
+static S8 DutyScan_Offset_Convert(U8 val)
+{
+    U8 calibration_sequence[15]= {
+        0xf, 0xe, 0xd, 0xc,
+        0xb, 0xa, 0x9, 0x0,
+        0x1, 0x2, 0x3, 0x4,
+        0x5, 0x6, 0x7
+    };
+
+    return ((S8)(calibration_sequence[val]>8 ? 0-(calibration_sequence[val]&0x7) : calibration_sequence[val]));
+
+}
+#endif
+#if 0
+static void DutyScan_SetDutyOffset(DRAMC_CTX_T *p, U8 u1B0, U8 u1B1, U8 u1CA)
+{
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), u1B0, B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3), u1B1, B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B1);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3), u1CA, CA_PHY3_RG_RX_ARCA_DUTY_VCAL_OFFSETC_CA);
+}
+
+static void DutyScan_Offset_Calibration(DRAMC_CTX_T *p, U8 *u1OfB0, U8 *u1OfB1, U8 *u1OfCA)
+{
+    U8 calibration_sequence[15]={0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7};
+    U8 i, read_val_b0, read_val_b1, read_val_ca;
+    U8 cal_i_b0=0xff, cal_i_b1=0xff, cal_i_ca=0xff;
+
+#if VENDER_JV_LOG
+    vPrintCalibrationBasicInfo_ForJV(p);
+#else
+    vPrintCalibrationBasicInfo(p);
+#endif
+
+    mcSHOW_DBG_MSG(("[Duty_Offset_Calibration]\n"));
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4),
+        P_Fld(0, MISC_CTRL4_R_OPT2_MPDIV_CG) |
+        P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQS));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL3),
+        P_Fld(0, MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT) |
+        P_Fld(0, MISC_CTRL3_ARPI_CG_DQS_OPT));
+
+
+
+    //B0/B1/CA RG setting
+    for(i=0; i<3; i++)
+    {
+        if (i<2)
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) + i*DDRPHY_AO_B0_B1_OFFSET,
+                P_Fld(1, B0_DQ6_RG_TX_ARDQ_DATA_SWAP_EN_B0) |
+                P_Fld(2, B0_DQ6_RG_TX_ARDQ_DATA_SWAP_B0));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2) + i*DDRPHY_AO_B0_B1_OFFSET,
+                P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0) |
+                P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0));
+        }
+        else
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6),
+                P_Fld(1, CA_CMD6_RG_TX_ARCMD_DATA_SWAP_EN) |
+                P_Fld(2, CA_CMD6_RG_TX_ARCMD_DATA_SWAP));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2),
+                P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA));
+        }
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ5) + i*DDRPHY_AO_B0_B1_OFFSET,
+            P_Fld(0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0));
+
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3) + i*DDRPHY_AO_B0_B1_OFFSET,
+            P_Fld(0x38, B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_VREF_SEL_B0) |
+            P_Fld(0x0, B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B0) |
+            P_Fld(0x1, B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_EN_B0));
+
+        mcDELAY_US(1);
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11) + i*DDRPHY_AO_B0_B1_OFFSET,
+            P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0));
+    }
+
+    mcSHOW_DBG_MSG2(("   Offset\tB0\tB1\tCA\n"));
+    mcSHOW_DBG_MSG2(("====================================================\n"));
+
+    for(i=0; i<15; i++)
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), calibration_sequence[i], B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B0);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3), calibration_sequence[i], B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B1);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3), calibration_sequence[i], CA_PHY3_RG_RX_ARCA_DUTY_VCAL_OFFSETC_CA);
+
+        mcDELAY_US(1);
+
+        read_val_b0 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYCAL_STATUS), MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B0);
+        read_val_b1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYCAL_STATUS), MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B1);
+        read_val_ca = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYCAL_STATUS), MISC_DUTYCAL_STATUS_RGS_RX_ARCA_DUTY_VCAL_CMP_OUT_C0);
+
+        //mcSHOW_DBG_MSG2(("   %d    \t%d\t%d\t%d\n", DutyScan_Offset_Convert(i), read_val_b0, read_val_b1, read_val_ca)); [FOR_CHROMEOS]
+
+        if (read_val_b0 == 0 && cal_i_b0==0xff)
+        {
+            cal_i_b0 = i;
+        }
+
+        if (read_val_b1 == 0 && cal_i_b1==0xff)
+        {
+            cal_i_b1 = i;
+        }
+
+        if (read_val_ca == 0 && cal_i_ca==0xff)
+        {
+            cal_i_ca = i;
+        }
+    }
+
+    if (cal_i_b0==0 || cal_i_b1==0 || cal_i_ca==0)
+    {
+        mcSHOW_ERR_MSG(("offset calibration i=-7 and AD_RX_*RDQ_O1_B*<2>/AD_RX_*RCA2_O1 ==0 !!\n"));
+    }
+    else if ((read_val_b0==1 && cal_i_b0==0xff) || (read_val_b1==1 && cal_i_b1==0xff) || (read_val_ca==1 && cal_i_ca==0xff))
+    {
+        mcSHOW_ERR_MSG(("offset calibration i=7 and AD_RX_*RDQ_O1_B*<2>/AD_RX_*RCA2_O1 ==1 !!\n"));
+        if (read_val_b0==1 && cal_i_b0==0xff)
+            cal_i_b0 = (i-1); //max
+        if (read_val_b1==1 && cal_i_b1==0xff)
+            cal_i_b1 = (i-1); //max
+        if (read_val_ca==1 && cal_i_ca==0xff)
+            cal_i_ca = (i-1); //max
+    }
+
+    mcSHOW_DBG_MSG2(("====================================================\n"));
+    //[FOR_CHROMEOS]
+    //mcSHOW_DBG_MSG(("   Final\tB0:%d\tB1:%d\tCA:%d\n",DutyScan_Offset_Convert(cal_i_b0),DutyScan_Offset_Convert(cal_i_b1),DutyScan_Offset_Convert(cal_i_ca)));
+    //mcDUMP_REG_MSG(("   Final\tB0:%d\tB1:%d\tCA:%d\n",DutyScan_Offset_Convert(cal_i_b0),DutyScan_Offset_Convert(cal_i_b1),DutyScan_Offset_Convert(cal_i_ca)));
+
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11),
+                 P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11),
+                 P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11),
+                 P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA));
+
+    if (cal_i_b0!=0xff)
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), calibration_sequence[cal_i_b0], B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B0);
+        *u1OfB0 = calibration_sequence[cal_i_b0];
+    }
+    if (cal_i_b1!=0xff)
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3), calibration_sequence[cal_i_b1], B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B1);
+        *u1OfB1 = calibration_sequence[cal_i_b1];
+    }
+    if (cal_i_ca!=0xff)
+    {
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3), calibration_sequence[cal_i_ca], CA_PHY3_RG_RX_ARCA_DUTY_VCAL_OFFSETC_CA);
+        *u1OfCA = calibration_sequence[cal_i_ca];
+    }
+
+    for(i=0; i<3; i++)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) + i*DDRPHY_AO_B0_B1_OFFSET,
+                     P_Fld(1, B0_DQ6_RG_RX_ARDQ_LPBK_EN_B0));
+    }
+
+    return;
+}
+#endif
+
+S8 gcFinal_K_CLK_delay_cell[DQS_BYTE_NUMBER];
+S8 gcFinal_K_DQS_delay_cell[DQS_BYTE_NUMBER];
+S8 gcFinal_K_WCK_delay_cell[DQS_BYTE_NUMBER];
+#if APPLY_DQDQM_DUTY_CALIBRATION
+S8 gcFinal_K_DQ_delay_cell[DQS_BYTE_NUMBER];
+S8 gcFinal_K_DQM_delay_cell[DQS_BYTE_NUMBER];
+#endif
+typedef struct _TEST_DUTY_AVG_LOG_PARAMETER_T
+{
+    U32 ucmost_approach_50_percent;
+    S8  scFinal_clk_delay_cell;
+    U32 ucFinal_period_duty_averige;
+    U32 ucFinal_period_duty_max;
+    U32 ucFinal_period_duty_min;
+    U32 ucFinal_duty_max_clk_dly;
+    U32 ucFinal_duty_min_clk_dly;
+} TEST_DUTY_AVG_LOG_PARAMETER_T;
+#if 0
+static DRAM_STATUS_T DutyScan_Calibration_Flow(DRAMC_CTX_T *p, U8 k_type, U8 ft_test_type)
+{
+    DRAM_STATUS_T KResult = DRAM_FAIL;
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+    REG_TRANSFER_T CA_SWAP_Reg,  B1_SWAP_Reg, CA_VrefSel_Reg,  B1_VrefSel_Reg, CA_CmpOut_Reg,  B1_CmpOut_Reg;
+
+    S8 scinner_duty_ofst, scFinal_clk_delay_cell[DQS_BYTE_NUMBER]={0,0}, scinner_duty_ofst_step;
+    S8 scinner_duty_ofst_start = 0, scinner_duty_ofst_end = 0;
+    S32 s4PICnt, s4PIBegin, s4PIEnd, s4PICnt_mod64;
+    S8 i, swap_idx, ucdqs_i, ucdqs_i_count=2;
+    U32 u4DutyDiff, u4DutyDiff_Limit=900;
+
+    U8 vref_sel_value[2], cal_out_value;
+    S32 duty_value[2];
+    S32 final_duty;
+
+    U32 ucperiod_duty_max=0, ucperiod_duty_min=0xffffffff, ucperiod_duty_max_clk_dly=0, ucperiod_duty_min_clk_dly=0;
+    U32 ucperiod_duty_averige=0, ucStart_period_duty_averige[DQS_BYTE_NUMBER]={0,0}, ucFinal_period_duty_averige[DQS_BYTE_NUMBER]={0,0}, ucmost_approach_50_percent=0xffffffff;
+    //U32 ucperiod_duty_averige_past=0, ;
+
+    /* temp local record duty calibration result of every step to find first pass and last pass */
+    TEST_DUTY_AVG_LOG_PARAMETER_T record_duty_log={0};
+    U32 record_ucmost_approach_50_percent, temp_value;
+    S8 temp_first_pass=0, temp_last_pass=0;
+
+    U32 ucFinal_period_duty_max[DQS_BYTE_NUMBER] = {0,0}, ucFinal_period_duty_min[DQS_BYTE_NUMBER] = {0,0};
+    U32 ucFinal_duty_max_clk_dly[DQS_BYTE_NUMBER]={0},ucFinal_duty_min_clk_dly[DQS_BYTE_NUMBER]={0};
+    U8 early_break_count=0;
+//fra    U8 str_clk_duty[]="CLK", str_dqs_duty[]="DQS", str_dq_duty[]="DQ", str_dqm_duty[]="DQM", str_wck_duty[]="WCK";
+    //U8 *str_clk_duty, *str_dqs_duty, *str_dq_duty, *str_dqm_duty, *str_wck_duty;
+
+//fra    U8 *str_who_am_I=str_clk_duty;
+    const char *str_who_am_I = "CLK";
+#if FT_DSIM_USED
+    S32 s4FT_Test_Final_duty[2][3]={0};
+#endif
+
+    U8 clksel =0;
+    U8 tDelay;
+    //U32 tmp;
+
+    if (!isLP4_DSC)
+    {
+        CA_SWAP_Reg.u4Addr = DDRPHY_REG_CA_CMD6;
+        CA_SWAP_Reg.u4Fld = CA_CMD6_RG_TX_ARCMD_DATA_SWAP;
+        B1_SWAP_Reg.u4Addr = DDRPHY_REG_B1_DQ6;
+        B1_SWAP_Reg.u4Fld = B1_DQ6_RG_TX_ARDQ_DATA_SWAP_B1;
+        CA_VrefSel_Reg.u4Addr = DDRPHY_REG_CA_PHY3;
+        CA_VrefSel_Reg.u4Fld = CA_PHY3_RG_RX_ARCA_DUTY_VCAL_VREF_SEL_CA;
+        B1_VrefSel_Reg.u4Addr = DDRPHY_REG_B1_PHY3;
+        B1_VrefSel_Reg.u4Fld = B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_VREF_SEL_B1;
+        CA_CmpOut_Reg.u4Addr = DDRPHY_REG_MISC_DUTYCAL_STATUS;
+        CA_CmpOut_Reg.u4Fld = MISC_DUTYCAL_STATUS_RGS_RX_ARCA_DUTY_VCAL_CMP_OUT_C0;
+        B1_CmpOut_Reg.u4Addr = DDRPHY_REG_MISC_DUTYCAL_STATUS;
+        B1_CmpOut_Reg.u4Fld = MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B1;
+    }
+    else
+    {
+        CA_SWAP_Reg.u4Addr = DDRPHY_REG_B1_DQ6;
+        CA_SWAP_Reg.u4Fld = B1_DQ6_RG_TX_ARDQ_DATA_SWAP_B1;
+        B1_SWAP_Reg.u4Addr = DDRPHY_REG_CA_CMD6;
+        B1_SWAP_Reg.u4Fld = CA_CMD6_RG_TX_ARCMD_DATA_SWAP;
+        CA_VrefSel_Reg.u4Addr = DDRPHY_REG_B1_PHY3;
+        CA_VrefSel_Reg.u4Fld = B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_VREF_SEL_B1;
+        B1_VrefSel_Reg.u4Addr = DDRPHY_REG_CA_PHY3;
+        B1_VrefSel_Reg.u4Fld = CA_PHY3_RG_RX_ARCA_DUTY_VCAL_VREF_SEL_CA;
+        CA_CmpOut_Reg.u4Addr = DDRPHY_REG_MISC_DUTYCAL_STATUS;
+        CA_CmpOut_Reg.u4Fld = MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B1;
+        B1_CmpOut_Reg.u4Addr = DDRPHY_REG_MISC_DUTYCAL_STATUS;
+        B1_CmpOut_Reg.u4Fld = MISC_DUTYCAL_STATUS_RGS_RX_ARCA_DUTY_VCAL_CMP_OUT_C0;
+    }
+
+
+    mcSHOW_DBG_MSG3(("\n[DutyScan_Calibration_Flow] k_type=%d\n", k_type));
+    /*TINFO="\n[DutyScan_Calibration_Flow] k_type=%d\n", k_type */
+
+    //CLK Source Select (DQ/DQM/DQS/CLK)
+    if (k_type == DutyScan_Calibration_K_CLK) // K CLK
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL3),
+            P_Fld(0, MISC_CTRL3_ARPI_CG_CLK_OPT));
+
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0),
+            P_Fld(1, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE));
+        ucdqs_i_count = 1;
+    }
+    else
+    {
+#if APPLY_DQDQM_DUTY_CALIBRATION
+        //CLK Source Select (DQ/DQM/DQS/CLK)
+        if (k_type == DutyScan_Calibration_K_DQ) // K DQ
+        {
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+            if(p->femmc_Ready==1)
+            {
+                DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ);
+                return DRAM_OK;
+            }
+#endif
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4),
+                P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQ));
+
+            clksel = 1;
+            str_who_am_I = "DQ";
+        }
+        else if (k_type == DutyScan_Calibration_K_DQM) // K DQM
+        {
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+            if(p->femmc_Ready==1)
+            {
+                DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM);
+                return DRAM_OK;
+            }
+#endif
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4),
+                P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQM));
+
+            clksel = 3;
+            str_who_am_I = "DQM";
+        }
+#endif
+        else if (k_type == DutyScan_Calibration_K_DQS) // K DQS
+        {
+            str_who_am_I = "DQS";
+        }
+        else if (k_type == DutyScan_Calibration_K_WCK) // K WCK
+        {
+            clksel = 2;
+            str_who_am_I = "WCK";
+        }
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0),
+            P_Fld(1, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE) |
+            P_Fld(1, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE));
+
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13),
+            P_Fld(0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0));
+        if (!isLP4_DSC)
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13),
+                P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1));
+        }
+        else
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13),
+                P_Fld(0, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA));
+        }
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3),
+        clksel, B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_CLK_SEL_B0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3),
+        clksel, B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_CLK_SEL_B1);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3),
+        clksel, CA_PHY3_RG_RX_ARCA_DUTY_VCAL_CLK_SEL_CA);
+
+    scinner_duty_ofst_start = DUTY_OFFSET_START;
+    scinner_duty_ofst_end = DUTY_OFFSET_END;
+
+#if FOR_DV_SIMULATION_USED
+    scinner_duty_ofst_step = DUTY_OFFSET_STEP * 2;
+#else
+    scinner_duty_ofst_step = DUTY_OFFSET_STEP;
+#endif
+
+#if FT_DSIM_USED
+    if (ft_test_type == 0)
+    {
+        scinner_duty_ofst_start=0;
+        scinner_duty_ofst_end=0;
+    }
+    else
+    {
+        scinner_duty_ofst_start = DUTY_OFFSET_START;
+        scinner_duty_ofst_end = DUTY_OFFSET_END;
+        scinner_duty_ofst_step = DUTY_OFFSET_END //8;
+    }
+#endif
+
+#if (fcFOR_CHIP_ID == fcA60868)
+    if (k_type == DutyScan_Calibration_K_CLK)
+    {
+        u4DutyDiff_Limit = 530;
+    }
+    else
+    {
+        u4DutyDiff_Limit = 580;
+    }
+#endif
+
+#if 0//(fcFOR_CHIP_ID == fcLafite)
+    if (k_type == DutyScan_Calibration_K_CLK && p->channel == CHANNEL_A)
+    {
+        s4PIBegin = 0;
+        s4PIEnd = 0;
+    }
+    else
+#endif
+    {
+        s4PIBegin = CLOCK_PI_START;
+        s4PIEnd = CLOCK_PI_END;
+    }
+
+    for(ucdqs_i=0; ucdqs_i<ucdqs_i_count; ucdqs_i++)
+    {
+        if (k_type == DutyScan_Calibration_K_CLK)
+        {
+            mcSHOW_DBG_MSG(("[%s Duty scan]\n", str_who_am_I));
+            /*TINFO="\n[CLK Duty scan]\n", ucdqs_i */
+        }
+        else
+        {
+            mcSHOW_DBG_MSG(("[%s B%d Duty scan]\n", str_who_am_I, ucdqs_i));
+            /*TINFO="\n[%s B%d Duty scan]\n", str_who_am_I, ucdqs_i */
+        }
+
+        ucmost_approach_50_percent=0xffff;
+        record_ucmost_approach_50_percent=0xffff;
+        early_break_count=0;
+
+        mcSHOW_DBG_MSG2(("   DutyOffset\tMaxDuty\tMinDuty\tAvgDuty\tAvg-50%%\tMax-Min\n"));
+
+        //Set Duty Offset
+        for(scinner_duty_ofst=scinner_duty_ofst_start; scinner_duty_ofst<=scinner_duty_ofst_end; scinner_duty_ofst+=scinner_duty_ofst_step)
+        {
+            ucperiod_duty_max = 0;
+            ucperiod_duty_min = 100000;
+
+            DramcDutyDelayRGSettingConvert(p, scinner_duty_ofst, &tDelay);
+
+            if (k_type == DutyScan_Calibration_K_DQS)
+            {
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + ucdqs_i*DDRPHY_AO_B0_B1_OFFSET,
+                    P_Fld(tDelay, SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0));
+            }
+#if __LP5_COMBO__
+            if (k_type == DutyScan_Calibration_K_WCK)
+            {
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + ucdqs_i*DDRPHY_AO_B0_B1_OFFSET,
+                    P_Fld(tDelay, SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0));
+            }
+#endif
+            if (k_type == DutyScan_Calibration_K_CLK)
+            {
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_TXDUTY),
+                    P_Fld(tDelay, SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY));
+            }
+
+
+#if APPLY_DQDQM_DUTY_CALIBRATION
+            if (k_type == DutyScan_Calibration_K_DQ)
+            {
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + ucdqs_i*DDRPHY_AO_B0_B1_OFFSET,
+                    P_Fld(tDelay, SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0));
+            }
+
+            if (k_type == DutyScan_Calibration_K_DQM)
+            {
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + ucdqs_i*DDRPHY_AO_B0_B1_OFFSET,
+                    P_Fld(tDelay, SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0));
+            }
+#endif
+
+            for(s4PICnt=s4PIBegin; s4PICnt<=s4PIEnd; s4PICnt+=CLOCK_PI_STEP)
+            {
+                s4PICnt_mod64 = (s4PICnt+64)&0x3f;//s4PICnt_mod64 = (s4PICnt+64)%64;
+#if DutyPrintAllLog
+                //if(scinner_duty_ofst!=DUTY_OFFSET_START)
+                mcSHOW_DBG_MSG(("PI= %d\n", s4PICnt_mod64));
+#endif
+
+                if (k_type == DutyScan_Calibration_K_DQS || k_type == DutyScan_Calibration_K_WCK)
+                {
+                    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0) + ucdqs_i*DDRPHY_AO_B0_B1_OFFSET, s4PICnt_mod64, SHU_R0_B0_DQ0_ARPI_PBYTE_B0);
+                }
+                else
+                if (k_type == DutyScan_Calibration_K_CLK)
+                {
+                    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), s4PICnt_mod64, SHU_R0_CA_CMD0_RG_ARPI_CLK);
+                }
+                else
+                if (k_type == DutyScan_Calibration_K_DQ)
+                {
+                    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0) + ucdqs_i*DDRPHY_AO_B0_B1_OFFSET, s4PICnt_mod64, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0);
+                }
+                else
+                if (k_type == DutyScan_Calibration_K_DQM)
+                {
+                    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0) + ucdqs_i*DDRPHY_AO_B0_B1_OFFSET, s4PICnt_mod64, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0);
+                }
+
+                for(swap_idx=0; swap_idx<2; swap_idx++)
+                {
+                    if (k_type == DutyScan_Calibration_K_CLK)
+                    {
+                        if (swap_idx==0)
+                        {
+                            vIO32WriteFldAlign(DRAMC_REG_ADDR(CA_SWAP_Reg.u4Addr), 2, CA_SWAP_Reg.u4Fld);
+                        }
+                        else
+                        {
+                            vIO32WriteFldAlign(DRAMC_REG_ADDR(CA_SWAP_Reg.u4Addr), 3, CA_SWAP_Reg.u4Fld);
+                        }
+
+                        vref_sel_value[swap_idx]= 0;
+                        vIO32WriteFldAlign(DRAMC_REG_ADDR(CA_VrefSel_Reg.u4Addr), vref_sel_value[swap_idx], CA_VrefSel_Reg.u4Fld);
+                    }
+                    else
+                    {
+                        if (swap_idx==0)
+                        {
+                            if (ucdqs_i==0)
+                            {
+                                vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), 2, B0_DQ6_RG_TX_ARDQ_DATA_SWAP_B0);
+                            }
+                            else
+                            {
+                                vIO32WriteFldAlign(DRAMC_REG_ADDR(B1_SWAP_Reg.u4Addr), 2, B1_SWAP_Reg.u4Fld);
+                            }
+                        }
+                        else
+                        {
+                            if (ucdqs_i==0)
+                            {
+                                vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), 3, B0_DQ6_RG_TX_ARDQ_DATA_SWAP_B0);
+                            }
+                            else
+                            {
+                                vIO32WriteFldAlign(DRAMC_REG_ADDR(B1_SWAP_Reg.u4Addr), 3, B1_SWAP_Reg.u4Fld);
+                            }
+                        }
+
+                        vref_sel_value[swap_idx]= 0;
+                        if (ucdqs_i==0)
+                        {
+                            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), vref_sel_value[swap_idx], B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_VREF_SEL_B0);
+                        }
+                        else
+                        {
+                            vIO32WriteFldAlign(DRAMC_REG_ADDR(B1_VrefSel_Reg.u4Addr), vref_sel_value[swap_idx], B1_VrefSel_Reg.u4Fld);
+                        }
+                    }
+
+                    for(i=6; i>=0; i--)
+                    {
+                        if (k_type == DutyScan_Calibration_K_CLK)
+                        {
+                            vref_sel_value[swap_idx] |= (1<<i);
+                            vIO32WriteFldAlign(DRAMC_REG_ADDR(CA_VrefSel_Reg.u4Addr), vref_sel_value[swap_idx], CA_VrefSel_Reg.u4Fld);
+                            mcDELAY_US(1);
+
+                            cal_out_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(CA_CmpOut_Reg.u4Addr), CA_CmpOut_Reg.u4Fld);
+
+                            if (cal_out_value == 0)
+                            {
+                                vref_sel_value[swap_idx] &= ~(1<<i);
+                            }
+                        }
+                        else
+                        {
+                            vref_sel_value[swap_idx] |= (1<<i);
+                            if (ucdqs_i==0)
+                            {
+                                vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), vref_sel_value[swap_idx], B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_VREF_SEL_B0);
+                            }
+                            else
+                            {
+                                vIO32WriteFldAlign(DRAMC_REG_ADDR(B1_VrefSel_Reg.u4Addr), vref_sel_value[swap_idx], B1_VrefSel_Reg.u4Fld);
+                            }
+                            mcDELAY_US(1);
+
+                            if (ucdqs_i==0)
+                            {
+                                cal_out_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYCAL_STATUS), MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B0);
+                            }
+                            else
+                            {
+                                cal_out_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(B1_CmpOut_Reg.u4Addr), B1_CmpOut_Reg.u4Fld);
+                            }
+
+#if DutyPrintAllLog
+                            mcSHOW_DBG_MSG(("Fra i=%d vref_sel_value[swap_idx]=%x, cal_out=%d\n",i, vref_sel_value[swap_idx], cal_out_value));
+#endif
+
+                            if (cal_out_value == 0)
+                            {
+                                vref_sel_value[swap_idx] &= ~(1<<i);
+                            }
+                        }
+                    }
+                }
+
+
+                for(swap_idx=0; swap_idx<2; swap_idx++)
+                {
+                    //La_fite duty calculation
+                    #if 0 //zj
+                    if (vref_sel_value[swap_idx]<=31)
+                    {
+                        duty_value[swap_idx] = ((vref_sel_value[swap_idx]-21)*726)/10+5017;
+                    }
+                    else
+                    {
+                        duty_value[swap_idx] = ((vref_sel_value[swap_idx]-32)*475)/10+5786;
+                    }
+                    #endif
+                    //A60868 duty calculcation
+                    //duty = vref_sel * 0.624 + 15.366
+                    duty_value[swap_idx] = ((vref_sel_value[swap_idx]*624)+15366) / 10;
+                }
+
+#if DutyPrintAllLog
+                mcSHOW_DBG_MSG(("\t[%d][%d] B%d : Vref_Sel=0x%x, Swap Vref_Sel=0x%x\n", scinner_duty_ofst, s4PICnt, ucdqs_i, vref_sel_value[0], vref_sel_value[1]));
+                mcSHOW_DBG_MSG(("\t[%d][%d] B%d : duty_value=%d, Swap duty_value=%d\n", scinner_duty_ofst, s4PICnt, ucdqs_i, duty_value[0], duty_value[1]));
+#endif
+
+                final_duty = 5000+((duty_value[0]-duty_value[1])/2);
+
+                if (final_duty > (S32) ucperiod_duty_max)
+                {
+                    ucperiod_duty_max = final_duty;
+                    ucperiod_duty_max_clk_dly = s4PICnt;
+                }
+                if (final_duty < (S32) ucperiod_duty_min)
+                {
+                    ucperiod_duty_min = final_duty;
+                    ucperiod_duty_min_clk_dly = s4PICnt;
+                }
+
+#if DutyPrintAllLog
+                mcSHOW_DBG_MSG(("\t[%d][%d] B%d : Final_Duty=%d\n", scinner_duty_ofst, s4PICnt, ucdqs_i, final_duty));
+#endif
+            }
+
+
+
+            ucperiod_duty_averige = (ucperiod_duty_max + ucperiod_duty_min)>>1;
+
+#if FT_DSIM_USED
+            if (ft_test_type==1)
+            {
+                if (scinner_duty_ofst==DUTY_OFFSET_START)
+                {
+                    s4FT_Test_Final_duty[ucdqs_i][0] = ucperiod_duty_averige;
+                }
+                else
+                if (scinner_duty_ofst==0)
+                {
+                    s4FT_Test_Final_duty[ucdqs_i][1] = ucperiod_duty_averige;
+                }
+                else
+                if (scinner_duty_ofst==DUTY_OFFSET_END)
+                {
+                    s4FT_Test_Final_duty[ucdqs_i][2] = ucperiod_duty_averige;
+                }
+            }
+#endif
+
+            mcSHOW_DBG_MSG2(("   [%d]     ",scinner_duty_ofst));
+            mcSHOW_DBG_MSG2(("\t%d%%",ucperiod_duty_max));
+            /*TINFO="\tMAX Duty = %d%%(X100), CLK PI=%d\n",ucperiod_duty_max, ucperiod_duty_max_clk_dly */
+            mcSHOW_DBG_MSG2(("\t%d%%",ucperiod_duty_min));
+            /*TINFO="\tMIN Duty = %d%%(X100), CLK PI=%d\n",ucperiod_duty_min, ucperiod_duty_min_clk_dly */
+            mcSHOW_DBG_MSG2(("\t%d%%", ucperiod_duty_averige));
+            /*TINFO="\tAVG Duty = %d%%(X100)\n", ucperiod_duty_averige */
+            mcSHOW_DBG_MSG2(("\t%d%%", (ucperiod_duty_averige-ClockDutyMiddleBound)*(ucperiod_duty_averige>=ClockDutyMiddleBound?1:-1)));
+            /*TINFO="\tAVG Duty = %d%%(X100)\n", ucperiod_duty_averige */
+            mcSHOW_DBG_MSG2(("\t%d%%", (ucperiod_duty_max-ucperiod_duty_min)));
+            /*TINFO="\tAVG Duty = %d%%(X100)\n", ucperiod_duty_averige */
+
+            if ((ucperiod_duty_max-ucperiod_duty_min)<=20)
+            {
+                mcSHOW_ERR_MSG(("\n[DutyScan Cal] Warnning: Need confirm duty calibration (MaxDuty-MinDuty<=50) !!!\n"));
+            }
+
+            if (scinner_duty_ofst == scinner_duty_ofst_start)
+            {
+                ucStart_period_duty_averige[ucdqs_i] = ucperiod_duty_averige;
+            }
+
+            if (ucperiod_duty_averige >= ClockDutyMiddleBound)
+            {
+                    /* record duty calibration result of every step */
+                    temp_value = ucperiod_duty_averige-ClockDutyMiddleBound+(ucperiod_duty_max-ucperiod_duty_min)*3/4;
+            }
+            else
+            {
+                    /* record duty calibration result of every step */
+                    temp_value = ClockDutyMiddleBound-ucperiod_duty_averige+(ucperiod_duty_max-ucperiod_duty_min)*3/4;
+            }
+
+            if (temp_value < record_ucmost_approach_50_percent)
+            {
+                record_ucmost_approach_50_percent = temp_value;
+                temp_first_pass = temp_last_pass = scinner_duty_ofst;
+
+                record_duty_log.ucmost_approach_50_percent = temp_value;
+                record_duty_log.ucFinal_period_duty_averige = ucperiod_duty_averige;
+                record_duty_log.ucFinal_period_duty_max = ucperiod_duty_max;
+                record_duty_log.ucFinal_period_duty_min = ucperiod_duty_min;
+                record_duty_log.ucFinal_duty_max_clk_dly = ucperiod_duty_max_clk_dly;
+                record_duty_log.ucFinal_duty_min_clk_dly = ucperiod_duty_min_clk_dly;
+            }
+            else if (temp_value == record_ucmost_approach_50_percent)
+            {
+                temp_last_pass = scinner_duty_ofst;
+            }
+
+            if (ucperiod_duty_averige >= ClockDutyMiddleBound)
+            {
+                if ((scinner_duty_ofst<=0 && (temp_value <= ucmost_approach_50_percent)) ||
+                     (scinner_duty_ofst>0 && (temp_value < ucmost_approach_50_percent)))
+                {
+                    ucmost_approach_50_percent = temp_value;
+
+                    mcSHOW_DBG_MSG2(("\t ==> ucmost_approach_50_percent = %d%%(X100) !!!",ucmost_approach_50_percent));
+                    /*TINFO="!!! ucmost_approach_50_percent = %d%%(X100) !!!\n",ucmost_approach_50_percent */
+
+                    early_break_count = 0;
+                }
+                else
+                {
+                    early_break_count ++;
+                    if (early_break_count>=2)
+                    {
+                        mcSHOW_DBG_MSG2(("\t ==> Early Break !!!\n"));
+                        break; //early break;
+                    }
+                }
+            }
+            else
+            {
+                if ((scinner_duty_ofst<=0 && (temp_value <= ucmost_approach_50_percent)) ||
+                    (scinner_duty_ofst>0 && (temp_value < ucmost_approach_50_percent)))
+                {
+                    ucmost_approach_50_percent = temp_value;
+
+                    mcSHOW_DBG_MSG2(("\t ==> ucmost_approach_50_percent = %d%%(X100) !!!",ucmost_approach_50_percent));
+                    /*TINFO="!!! ucmost_approach_50_percent = %d%%(X100) !!!\n",ucmost_approach_50_percent */
+
+                    early_break_count = 0;
+                }
+                else
+                {
+                    early_break_count ++;
+                    if (early_break_count>=2)
+                    {
+                        mcSHOW_DBG_MSG2(("\t ==> Early Break !!!\n"));
+                        break; //early break;
+                    }
+                }
+            }
+
+            mcSHOW_DBG_MSG2(("\n"));
+            /*TINFO="\n" */
+        }
+
+        /* set this best pass to final result */
+        scFinal_clk_delay_cell[ucdqs_i] = (temp_first_pass + temp_last_pass) / 2; /* best step is (first pass+last pass)/2 */
+        ucFinal_period_duty_averige[ucdqs_i] = record_duty_log.ucFinal_period_duty_averige;
+        ucFinal_period_duty_max[ucdqs_i] = record_duty_log.ucFinal_period_duty_max;
+        ucFinal_period_duty_min[ucdqs_i] = record_duty_log.ucFinal_period_duty_min;
+        ucFinal_duty_max_clk_dly[ucdqs_i] = record_duty_log.ucFinal_duty_max_clk_dly;
+        ucFinal_duty_min_clk_dly[ucdqs_i] = record_duty_log.ucFinal_duty_min_clk_dly;
+
+        mcSHOW_DBG_MSG4(("[%d] record_duty_log_ucmost_approach_50_percent=%d\n",scinner_duty_ofst, record_duty_log.ucmost_approach_50_percent));
+        mcSHOW_DBG_MSG(("Find : first_pass = %d, last_pass = %d \n", temp_first_pass, temp_last_pass));
+        mcSHOW_DBG_MSG(("Final : Best Pass = %d\n", scFinal_clk_delay_cell[ucdqs_i]));
+    }
+
+    mcSHOW_DBG_MSG2(("====================================================\n"));
+
+    for(ucdqs_i=0; ucdqs_i<ucdqs_i_count; ucdqs_i++)
+    {
+        //for SLT, use ERR_MSG to force print log
+        if (k_type == DutyScan_Calibration_K_CLK)
+        {
+            mcSHOW_DBG_MSG(("Final %s duty delay cell = %d\n", str_who_am_I, scFinal_clk_delay_cell[ucdqs_i]));
+            //mcDUMP_REG_MSG(("Final %s duty delay cell = %d\n", str_who_am_I, scFinal_clk_delay_cell[ucdqs_i]));
+
+            /*TINFO="Final %s duty delay cell = %d\n", str_who_am_I, scFinal_clk_delay_cell[ucdqs_i] */
+        }
+        else
+        {
+            mcSHOW_DBG_MSG(("Final %s %d duty delay cell = %d\n", str_who_am_I, ucdqs_i, scFinal_clk_delay_cell[ucdqs_i]));
+            //mcDUMP_REG_MSG(("Final %s %d duty delay cell = %d\n", str_who_am_I, ucdqs_i, scFinal_clk_delay_cell[ucdqs_i]));
+
+            /*TINFO="Final %s %d duty delay cell = %d\n", str_who_am_I, ucdqs_i, scFinal_clk_delay_cell[ucdqs_i] */
+        }
+        mcSHOW_DBG_MSG(("[%d] MAX Duty = %d%%(X100), PI = %d\n",scFinal_clk_delay_cell[ucdqs_i], ucFinal_period_duty_max[ucdqs_i], ucFinal_duty_max_clk_dly[ucdqs_i]));
+        /*TINFO="[%d] MAX Duty = %d%%(X100), DQS PI = %d\n",scFinal_clk_delay_cell[ucdqs_i], ucFinal_period_duty_max[ucdqs_i], ucFinal_duty_max_clk_dly[ucdqs_i] */
+        mcSHOW_DBG_MSG(("[%d] MIN Duty = %d%%(X100), PI = %d\n",scFinal_clk_delay_cell[ucdqs_i], ucFinal_period_duty_min[ucdqs_i], ucFinal_duty_min_clk_dly[ucdqs_i]));
+        /*TINFO="[%d] MIN Duty = %d%%(X100), DQS PI = %d\n",scFinal_clk_delay_cell[ucdqs_i], ucFinal_period_duty_min[ucdqs_i], ucFinal_duty_min_clk_dly[ucdqs_i] */
+        mcSHOW_DBG_MSG(("[%d] AVG Duty = %d%%(X100)\n", scFinal_clk_delay_cell[ucdqs_i], ucFinal_period_duty_averige[ucdqs_i]));
+        /*TINFO="[%d] AVG Duty = %d%%(X100)\n", scFinal_clk_delay_cell[ucdqs_i], ucFinal_period_duty_averige[ucdqs_i] */
+
+        // expend Delay code from +/-4 to +/-8
+        if ((scFinal_clk_delay_cell[ucdqs_i]>8)||(scFinal_clk_delay_cell[ucdqs_i]<-8))
+        {
+            mcSHOW_ERR_MSG(("[DutyScan Cal] Warnning: Need confirm Duty calibration (Duty Offset Unexpected) !!!\n"));
+            #if __ETT__
+            if (p->channel==CHANNEL_B)
+            {
+                while(1);
+            }
+            #endif
+        }
+        // expect final duty avg will be larger the the first one
+        if ((ucFinal_period_duty_averige[ucdqs_i]-ucStart_period_duty_averige[ucdqs_i])<100)
+        {
+            mcSHOW_ERR_MSG(("\n[DutyScan Cal] Warnning: Need confirm duty calibration (duty offset not moving) !!!\n"));
+            #if __ETT__
+            while(1);
+            #endif
+        }
+
+        //Duty Pass/Fail Criteria
+        u4DutyDiff = ucFinal_period_duty_max[ucdqs_i]-ucFinal_period_duty_min[ucdqs_i];
+        if ((((k_type == DutyScan_Calibration_K_CLK) || (k_type == DutyScan_Calibration_K_DQS)) && (u4DutyDiff < u4DutyDiff_Limit)) ||
+        #if APPLY_DQDQM_DUTY_CALIBRATION
+           (((k_type == DutyScan_Calibration_K_DQ) || (k_type == DutyScan_Calibration_K_DQM)) && (u4DutyDiff < u4DutyDiff_Limit)))
+        #else
+           (((k_type == DutyScan_Calibration_K_DQ) || (k_type == DutyScan_Calibration_K_DQM)) && ((u4DutyDiff < u4DutyDiff_Limit) && (ucFinal_period_duty_averige[ucdqs_i] >= 4550 && ucFinal_period_duty_averige[ucdqs_i] <= 5450))))
+        #endif
+        {
+            if (k_type == DutyScan_Calibration_K_CLK)
+            {
+                mcSHOW_DBG_MSG(("CH%d %s Duty spec in!! Max-Min= %d%%\n\n",p->channel, str_who_am_I, u4DutyDiff));
+                /*TINFO="\nCH%d %s Duty spec in!! Max-Min= %d%%\n",p->channel, str_who_am_I, u4DutyDiff */
+            }
+            else
+            {
+                mcSHOW_DBG_MSG(("CH%d %s %d Duty spec in!! Max-Min= %d%%\n\n",p->channel, str_who_am_I, ucdqs_i, u4DutyDiff));
+                /*TINFO="\nCH%d %s %d Duty spec in!! Max-Min= %d%%\n",p->channel, str_who_am_I, ucdqs_i, u4DutyDiff */
+            }
+            KResult = DRAM_OK;
+        }
+        else
+        {
+            if (k_type == DutyScan_Calibration_K_CLK)
+            {
+                mcSHOW_ERR_MSG(("CH%d %s Duty spec out!! Max-Min= %d%% >%d%%\n\n", p->channel, str_who_am_I, u4DutyDiff, u4DutyDiff_Limit));
+                /*TINFO="\nCH%d %s Duty spec out!! Max-Min= %d%% >8%%\n", p->channel, str_who_am_I, u4DutyDiff */
+                #if __ETT__
+                if (p->channel==CHANNEL_B)
+                {
+                    while(1);
+                }
+                #endif
+            }
+            else
+            {
+                mcSHOW_ERR_MSG(("CH%d %s %d Duty spec out!! Max-Min= %d%% >%d%%\n\n", p->channel, str_who_am_I, ucdqs_i, u4DutyDiff, u4DutyDiff_Limit));
+                /*TINFO="\nCH%d %s %d Duty spec out!! Max-Min= %d%% >8%%\n", p->channel, str_who_am_I, ucdqs_i, u4DutyDiff */
+                #if __ETT__
+                //while(1);
+                #endif
+            }
+        }
+    }
+
+#if FT_DSIM_USED
+    if (ft_test_type==0)
+    {
+        FT_Duty_Compare_PassFail(p->channel, k_type, ucFinal_period_duty_max[0] , ucFinal_period_duty_min[0],ucFinal_period_duty_max[1] , ucFinal_period_duty_min[1]);
+    }
+    else
+    {
+        FT_Duty_Ofst_Diff_PassFail(p->channel, k_type, s4FT_Test_Final_duty[0][0], s4FT_Test_Final_duty[0][1], s4FT_Test_Final_duty[0][2], s4FT_Test_Final_duty[1][0], s4FT_Test_Final_duty[1][1], s4FT_Test_Final_duty[1][2]);
+    }
+    *GPIO_GPIO_DOUT0  |= 0x04000000; //PAD_PWM_0,      // Lafi_te / round done
+#else
+    for(ucdqs_i=0; ucdqs_i<ucdqs_i_count; ucdqs_i++)
+    {
+        u4DutyDiff = ucFinal_period_duty_max[ucdqs_i] - ucFinal_period_duty_min[ucdqs_i];
+
+#if DQS_DUTY_SLT_CONDITION_TEST
+        if (k_type == DutyScan_Calibration_K_CLK || (k_type == DutyScan_Calibration_K_DQS))
+        {
+            u4DQSDutyDiff_Rec[p->channel][ucdqs_i][u1GlobalTestCnt]=u4DutyDiff;
+
+            u4DQSDutyDutyDly[p->channel][ucdqs_i] = scFinal_clk_delay_cell[ucdqs_i];
+
+            if(u4DutyDiff > u4DQSDutyDiff_Max[p->channel][ucdqs_i])
+                u4DQSDutyDiff_Max[p->channel][ucdqs_i] = u4DutyDiff;
+
+            if(u4DutyDiff < u4DQSDutyDiff_Min[p->channel][ucdqs_i])
+                u4DQSDutyDiff_Min[p->channel][ucdqs_i] = u4DutyDiff;
+
+            u4DQSDutyDiff_Avrg[p->channel][ucdqs_i]  += u4DutyDiff;
+        }
+#endif
+    }
+
+#endif
+
+    if (k_type == DutyScan_Calibration_K_DQS)
+    {
+        // backup final values
+        gcFinal_K_DQS_delay_cell[0] = scFinal_clk_delay_cell[0];
+        gcFinal_K_DQS_delay_cell[1] = scFinal_clk_delay_cell[1];
+
+        DQSDutyScan_SetDqsDelayCell(p, scFinal_clk_delay_cell);
+
+#ifdef FOR_HQA_TEST_USED
+        gFinalDQSDuty[p->channel][0] = scFinal_clk_delay_cell[0];
+        gFinalDQSDuty[p->channel][1] = scFinal_clk_delay_cell[1];
+        gFinalDQSDutyMinMax[p->channel][0][0] = ucFinal_period_duty_min[0];
+        gFinalDQSDutyMinMax[p->channel][0][1] = ucFinal_period_duty_max[0];
+        gFinalDQSDutyMinMax[p->channel][1][0] = ucFinal_period_duty_min[1];
+        gFinalDQSDutyMinMax[p->channel][1][1] = ucFinal_period_duty_max[1];
+#endif
+    }
+#if __LP5_COMBO__
+    if (k_type == DutyScan_Calibration_K_WCK)
+    {
+        // backup final values
+        gcFinal_K_WCK_delay_cell[0] = scFinal_clk_delay_cell[0];
+        gcFinal_K_WCK_delay_cell[1] = scFinal_clk_delay_cell[1];
+
+        WCKDutyScan_SetWCKDelayCell(p, scFinal_clk_delay_cell);
+
+#if 0 //zj #ifdef FOR_HQA_TEST_USED
+        gFinalDQSDuty[p->channel][0] = scFinal_clk_delay_cell[0];
+        gFinalDQSDuty[p->channel][1] = scFinal_clk_delay_cell[1];
+        gFinalDQSDutyMinMax[p->channel][0][0] = ucFinal_period_duty_min[0];
+        gFinalDQSDutyMinMax[p->channel][0][1] = ucFinal_period_duty_max[0];
+        gFinalDQSDutyMinMax[p->channel][1][0] = ucFinal_period_duty_min[1];
+        gFinalDQSDutyMinMax[p->channel][1][1] = ucFinal_period_duty_max[1];
+#endif
+    }
+#endif
+    if (k_type == DutyScan_Calibration_K_CLK)
+    {
+        DramcClockDutySetClkDelayCell(p, scFinal_clk_delay_cell);
+
+        // backup final values
+        gcFinal_K_CLK_delay_cell[0] = scFinal_clk_delay_cell[0];
+        gcFinal_K_CLK_delay_cell[1] = scFinal_clk_delay_cell[1];
+
+#ifdef FOR_HQA_TEST_USED
+        gFinalClkDuty[p->channel] = scFinal_clk_delay_cell[0];
+        gFinalClkDutyMinMax[p->channel][0] = ucFinal_period_duty_min[0];
+        gFinalClkDutyMinMax[p->channel][1] = ucFinal_period_duty_max[0];
+#endif
+    }
+
+#if APPLY_DQDQM_DUTY_CALIBRATION
+    if (k_type == DutyScan_Calibration_K_DQ)
+    {
+        // backup final values
+        gcFinal_K_DQ_delay_cell[0] = scFinal_clk_delay_cell[0];
+        gcFinal_K_DQ_delay_cell[1] = scFinal_clk_delay_cell[1];
+
+        DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, scFinal_clk_delay_cell, DutyScan_Calibration_K_DQ);
+    }
+
+    if (k_type == DutyScan_Calibration_K_DQM)
+    {
+        // backup final values
+        gcFinal_K_DQM_delay_cell[0] = scFinal_clk_delay_cell[0];
+        gcFinal_K_DQM_delay_cell[1] = scFinal_clk_delay_cell[1];
+
+        DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, scFinal_clk_delay_cell, DutyScan_Calibration_K_DQM);
+    }
+#endif
+
+    DramPhyReset(p);
+
+    mcSHOW_DBG_MSG3(("[DutyScan_Calibration_Flow] ====Done====\n"));
+    /*TINFO="[DutyScan_Calibration_Flow] ====Done====\n" */
+
+    return KResult;
+}
+#endif
+void DramcNewDutyCalibration(DRAMC_CTX_T *p)
+{
+    U8 u1backup_rank;
+    //U8 u1OfsB0=0, u1OfsB1=0, u1OfsCA=0;
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    //OE releated RG
+    U32 backup_DDRPHY_REG_B0_DQ2=0, backup_DDRPHY_REG_B1_DQ2=0, backup_DDRPHY_REG_CA_CMD2=0;
+    U32 backup_DDRPHY_REG_SHU_B0_DQ13=0, backup_DDRPHY_REG_SHU_B1_DQ13=0, backup_DDRPHY_REG_SHU_CA_CMD13=0;
+
+#if(DQS_DUTY_SLT_CONDITION_TEST)
+        U16 u2TestCnt, u2FailCnt=0, u2TestCntTotal =20; //fra 400;
+        U8 u1ByteIdx, u1PI_FB;
+        U32 u4Variance;
+#endif
+
+    //DRAM_STATUS_T u2FailStatusByCh={0};
+
+    //backup register value
+#if FT_DSIM_USED==0
+#if 0
+    U32 u4RegBackupAddress[] =
+    {
+        DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0),
+        DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4),
+        DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL3),
+
+        DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6),
+        DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3),
+        DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ5),
+        DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0),
+
+        DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2),
+        DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2),
+        DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2),
+
+        DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6),
+        DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3),
+        DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ5),
+        DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0),
+
+        DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11),
+        DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11),
+        DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11),
+
+        DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6),
+        DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3),
+        DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD5),
+        DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0),
+
+        DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_LPBK_CTRL),
+        DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_LPBK_CTRL),
+        DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_LPBK_CTRL),
+    };
+#endif
+#endif
+
+    u1backup_rank = u1GetRank(p);
+    vSetRank(p, RANK_0);
+
+    //backup OE releated RG , must put at begin of duty function !!
+    backup_DDRPHY_REG_B0_DQ2 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2));
+    if (!isLP4_DSC)
+        backup_DDRPHY_REG_B1_DQ2 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2));
+    else
+        backup_DDRPHY_REG_CA_CMD2 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2));
+    backup_DDRPHY_REG_SHU_B0_DQ13 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13));
+    if (!isLP4_DSC)
+        backup_DDRPHY_REG_SHU_B1_DQ13 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13));
+    else
+        backup_DDRPHY_REG_SHU_CA_CMD13 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13));
+
+    //default set fail
+    vSetCalibrationResult(p, DRAM_CALIBRATION_DUTY_SCAN, DRAM_FAIL);
+
+#if !FT_DSIM_USED
+#if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ
+    if (p->frequency == u2DFSGetHighestFreq(p))
+#else
+    //TODO if(Get_PRE_MIOCK_JMETER_HQA_USED_flag()==0)
+#endif
+#endif
+    {
+        #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+        if(p->femmc_Ready==1)
+        {
+            DramcClockDutySetClkDelayCell(p, p->pSavetimeData->s1ClockDuty_clk_delay_cell[p->channel]);
+            DQSDutyScan_SetDqsDelayCell(p, p->pSavetimeData->s1DQSDuty_clk_delay_cell[p->channel]);
+            #if __LP5_COMBO__
+            WCKDutyScan_SetWCKDelayCell(p, p->pSavetimeData->s1WCKDuty_clk_delay_cell[p->channel]);
+            #endif
+            #if APPLY_DQDQM_DUTY_CALIBRATION
+            DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM);
+            DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ);
+            #endif
+
+            vSetCalibrationResult(p, DRAM_CALIBRATION_DUTY_SCAN, DRAM_FAST_K);
+            return;
+        }
+        #endif
+                //clear global variables to 0 delay
+
+
+
+
+
+            //Clk free run {Move to Init_DRAM() and only call once}
+            //zj EnableDramcPhyDCM(p, 0);
+
+            //Fix rank to rank0
+
+            //backup register value
+
+            /* Set OE/ODT loopback MUX to DATA at LPBK path from WL @ 20200529
+                    00    tie low
+                    01    DATA
+                    10    OE
+                    11    ODT
+            */
+
+
+
+
+                    //copy DQ RG to DQM
+
+
+            //restore to orignal value
+
+
+
+
+
+    }
+
+    OECKCKE_Control(p, ENABLE);
+    //restore OE releated RG , must put at end of duty function !!
+    vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), backup_DDRPHY_REG_B0_DQ2);
+    if (!isLP4_DSC)
+        vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), backup_DDRPHY_REG_B1_DQ2);
+    else
+        vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), backup_DDRPHY_REG_CA_CMD2);
+    vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13), backup_DDRPHY_REG_SHU_B0_DQ13);
+    if (!isLP4_DSC)
+        vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), backup_DDRPHY_REG_SHU_B1_DQ13);
+    else
+        vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), backup_DDRPHY_REG_SHU_CA_CMD13);
+
+
+    vSetRank(p, u1backup_rank);
+}
+#endif
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
new file mode 100644
index 000000000000..f95215dcae80
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
@@ -0,0 +1,3313 @@
+/*----------------------------------------------------------------------------*
+ * Copyright Statement:                                                       *
+ *                                                                            *
+ *   This software/firmware and related documentation ("MediaTek Software")   *
+ * are protected under international and related jurisdictions'copyright laws *
+ * as unpublished works. The information contained herein is confidential and *
+ * proprietary to MediaTek Inc. Without the prior written permission of       *
+ * MediaTek Inc., any reproduction, modification, use or disclosure of        *
+ * MediaTek Software, and information contained herein, in whole or in part,  *
+ * shall be strictly prohibited.                                              *
+ * MediaTek Inc. Copyright (C) 2010. All rights reserved.                     *
+ *                                                                            *
+ *   BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND     *
+ * AGREES TO THE FOLLOWING:                                                   *
+ *                                                                            *
+ *   1)Any and all intellectual property rights (including without            *
+ * limitation, patent, copyright, and trade secrets) in and to this           *
+ * Software/firmware and related documentation ("MediaTek Software") shall    *
+ * remain the exclusive property of MediaTek Inc. Any and all intellectual    *
+ * property rights (including without limitation, patent, copyright, and      *
+ * trade secrets) in and to any modifications and derivatives to MediaTek     *
+ * Software, whoever made, shall also remain the exclusive property of        *
+ * MediaTek Inc.  Nothing herein shall be construed as any transfer of any    *
+ * title to any intellectual property right in MediaTek Software to Receiver. *
+ *                                                                            *
+ *   2)This MediaTek Software Receiver received from MediaTek Inc. and/or its *
+ * representatives is provided to Receiver on an "AS IS" basis only.          *
+ * MediaTek Inc. expressly disclaims all warranties, expressed or implied,    *
+ * including but not limited to any implied warranties of merchantability,    *
+ * non-infringement and fitness for a particular purpose and any warranties   *
+ * arising out of course of performance, course of dealing or usage of trade. *
+ * MediaTek Inc. does not provide any warranty whatsoever with respect to the *
+ * software of any third party which may be used by, incorporated in, or      *
+ * supplied with the MediaTek Software, and Receiver agrees to look only to   *
+ * such third parties for any warranty claim relating thereto.  Receiver      *
+ * expressly acknowledges that it is Receiver's sole responsibility to obtain *
+ * from any third party all proper licenses contained in or delivered with    *
+ * MediaTek Software.  MediaTek is not responsible for any MediaTek Software  *
+ * releases made to Receiver's specifications or to conform to a particular   *
+ * standard or open forum.                                                    *
+ *                                                                            *
+ *   3)Receiver further acknowledge that Receiver may, either presently       *
+ * and/or in the future, instruct MediaTek Inc. to assist it in the           *
+ * development and the implementation, in accordance with Receiver's designs, *
+ * of certain softwares relating to Receiver's product(s) (the "Services").   *
+ * Except as may be otherwise agreed to in writing, no warranties of any      *
+ * kind, whether express or implied, are given by MediaTek Inc. with respect  *
+ * to the Services provided, and the Services are provided on an "AS IS"      *
+ * basis. Receiver further acknowledges that the Services may contain errors  *
+ * that testing is important and it is solely responsible for fully testing   *
+ * the Services and/or derivatives thereof before they are used, sublicensed  *
+ * or distributed. Should there be any third party action brought against     *
+ * MediaTek Inc. arising out of or relating to the Services, Receiver agree   *
+ * to fully indemnify and hold MediaTek Inc. harmless.  If the parties        *
+ * mutually agree to enter into or continue a business relationship or other  *
+ * arrangement, the terms and conditions set forth herein shall remain        *
+ * effective and, unless explicitly stated otherwise, shall prevail in the    *
+ * event of a conflict in the terms in any agreements entered into between    *
+ * the parties.                                                               *
+ *                                                                            *
+ *   4)Receiver's sole and exclusive remedy and MediaTek Inc.'s entire and    *
+ * cumulative liability with respect to MediaTek Software released hereunder  *
+ * will be, at MediaTek Inc.'s sole discretion, to replace or revise the      *
+ * MediaTek Software at issue.                                                *
+ *                                                                            *
+ *   5)The transaction contemplated hereunder shall be construed in           *
+ * accordance with the laws of Singapore, excluding its conflict of laws      *
+ * principles.  Any disputes, controversies or claims arising thereof and     *
+ * related thereto shall be settled via arbitration in Singapore, under the   *
+ * then current rules of the International Chamber of Commerce (ICC).  The    *
+ * arbitration shall be conducted in English. The awards of the arbitration   *
+ * shall be final and binding upon both parties and shall be entered and      *
+ * enforceable in any court of competent jurisdiction.                        *
+ *---------------------------------------------------------------------------*/
+#include "dramc_common.h"
+#include "dramc_dv_init.h"
+#include "dramc_int_global.h"
+#include "x_hal_io.h"
+#include "sv_c_data_traffic.h"
+#include "dramc_pi_api.h"
+#if (FOR_DV_SIMULATION_USED == 0)
+#include "dramc_top.h"
+#endif
+#include <emi.h>
+
+DRAMC_CTX_T dram_ctx_chb;
+
+#if (FOR_DV_SIMULATION_USED == 1)
+U8 gu1BroadcastIsLP4 = TRUE;
+#endif
+
+bool gAndroid_DVFS_en = TRUE;
+bool gUpdateHighestFreq = FALSE;
+
+#define DV_SIMULATION_BYTEMODE 0
+#define DV_SIMULATION_LP5_TRAINING_MODE1 1
+#define DV_SIMULATION_LP5_CBT_PHASH_R 1
+
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+   SAVE_TIME_FOR_CALIBRATION_T SavetimeData;
+#endif
+
+U8 gHQA_Test_Freq_Vcore_Level = 0;  // 0: only 1 freq  , others are multi freq  1: low vcore 2: high vcore
+
+u8 ett_fix_freq = 0xff; // 0xFF=all freq by gFreqTbl. The 0x"X" != 0xFF for single freq by gFreqTbl index, ex: 0x3 for DDR3733
+
+DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = {
+    {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K,  VREF_CALI_OFF,  CLOSE_LOOP_MODE},  // highest freq of term group (3733) must k first.
+    {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K,  VREF_CALI_ON,   CLOSE_LOOP_MODE},  // highest freq of term group (3733) must k first.
+#if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
+    {LP4_DDR400  /*2*/, DIV4_MODE, SRAM_SHU7, DUTY_DEFAULT, VREF_CALI_OFF,  OPEN_LOOP_MODE},
+#endif
+    {LP4_DDR800  /*2*/, DIV4_MODE, SRAM_SHU6, DUTY_DEFAULT, VREF_CALI_OFF,  SEMI_OPEN_LOOP_MODE},  //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT)
+    {LP4_DDR1866 /*3*/, DIV8_MODE, SRAM_SHU3, DUTY_LAST_K,  VREF_CALI_OFF,  CLOSE_LOOP_MODE},  // highest freq of unterm group (2400) must k first.
+    {LP4_DDR1200 /*4*/, DIV8_MODE, SRAM_SHU5, DUTY_LAST_K,  VREF_CALI_OFF,  CLOSE_LOOP_MODE},  // highest freq of unterm group (2400) must k first.
+    {LP4_DDR2400 /*5*/, DIV8_MODE, SRAM_SHU2, DUTY_NEED_K,  VREF_CALI_ON,   CLOSE_LOOP_MODE},  // highest freq of unterm group (2400) must k first.
+    {LP4_DDR1600 /*6*/, DIV8_MODE, SRAM_SHU4, DUTY_DEFAULT, VREF_CALI_ON,   CLOSE_LOOP_MODE},  //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT)
+};
+
+DRAMC_CTX_T DramCtx_LPDDR4 =
+{
+    CHANNEL_SINGLE, // Channel number
+    CHANNEL_A,          // DRAM_CHANNEL
+    RANK_DUAL,        //DRAM_RANK_NUMBER_T
+    RANK_0,               //DRAM_RANK_T
+
+#ifdef MTK_FIXDDR1600_SUPPORT
+    LP4_DDR1600,
+#else
+#if __FLASH_TOOL_DA__
+    LP4_DDR1600,
+#else
+#if (DV_SIMULATION_LP4 == 1)
+    LP4_DDR1600,
+#else
+    LP5_DDR3200,
+#endif
+#endif
+#endif
+#if DV_SIMULATION_LP4
+    TYPE_LPDDR4X,        // DRAM_DRAM_TYPE_T
+#else
+    TYPE_LPDDR5,
+#endif
+    FSP_0 , //// DRAM Fast switch point type, only for LP4, useless in LP3
+    FSP_0 , //// boot_fsp
+    ODT_OFF,
+    {CBT_NORMAL_MODE, CBT_NORMAL_MODE},  // bring up LP4X rank0 & rank1 use normal mode
+#if ENABLE_READ_DBI
+    {DBI_OFF,DBI_ON},  //read DBI
+#else
+    {DBI_OFF,DBI_OFF}, //read DBI
+#endif
+#if ENABLE_WRITE_DBI
+    {DBI_OFF,DBI_ON},  // write DBI
+#else
+    {DBI_OFF,DBI_OFF},  // write DBI
+#endif
+    DATA_WIDTH_16BIT,     // DRAM_DATA_WIDTH_T
+    DEFAULT_TEST2_1_CAL,    // test2_1;
+    DEFAULT_TEST2_2_CAL,    // test2_2;
+#if ENABLE_K_WITH_WORST_SI_UI_SHIFT
+    TEST_WORST_SI_PATTERN,    // test_pattern;
+#else
+    TEST_XTALK_PATTERN,
+#endif
+#if (DV_SIMULATION_LP4 == 1)
+    800,                  // frequency
+    800,                  // freqGroup
+#else
+    1600,
+    1600,
+#endif
+    0x88, //vendor_id initial value
+    REVISION_ID_MAGIC,
+    0xff, //density
+    {0,0},
+    270,  // u2DelayCellTimex100;
+
+#if PRINT_CALIBRATION_SUMMARY
+    //aru4CalResultFlag[CHANNEL_NUM][RANK_MAX]
+    {{0,0,}},
+    //aru4CalExecuteFlag[CHANNEL_NUM][RANK_MAX]
+    {{0,0,}},
+    1,
+    0,
+#endif
+    {0}, //BOOL arfgWriteLevelingInitShif;
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+    FALSE, //femmc_Ready
+    0,
+    0,
+    0,
+    &SavetimeData,
+#endif
+    &gFreqTbl[DRAM_DFS_SRAM_MAX-1], // default is DDR1600 1:8 mode
+    DRAM_DFS_REG_SHU0,
+    TRAINING_MODE2,
+    CBT_PHASE_RISING,
+    0,  //new CBT pattern
+    PHYPLL_MODE,
+    DBI_OFF,
+    FSP_MAX,
+    PINMUX_EMCP,
+    {DISABLE,DISABLE},  // disable 10GB
+    0,
+};
+
+
+
+#if defined(DDR_INIT_TIME_PROFILING) || (__ETT__ && SUPPORT_SAVE_TIME_FOR_CALIBRATION)
+DRAMC_CTX_T gTimeProfilingDramCtx;
+U8 gtime_profiling_flag = 0;
+#endif
+
+void vSetVcoreByFreq(DRAMC_CTX_T *p)
+{
+#if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
+#if __FLASH_TOOL_DA__
+    dramc_set_vcore_voltage(750000);
+#else
+    unsigned int vio18, vcore, vdram, vddq, vmddr;
+    //int ret;
+
+    vio18 = vcore = vdram = vddq = vmddr = 0;
+
+#if __ETT__
+    hqa_set_voltage_by_freq(p, &vio18, &vcore, &vdram, &vddq, &vmddr);
+#elif defined(VCORE_BIN)
+    switch (vGet_Current_SRAMIdx(p)) {
+    case SRAM_SHU0:  //4266
+    #ifdef VOLTAGE_SEL
+        vcore = vcore_voltage_select(KSHU0);
+        if (!vcore)
+    #endif
+        vcore = get_vcore_uv_table(0);
+        break;
+    case SRAM_SHU1:   //3200
+    #ifdef VOLTAGE_SEL
+        vcore = vcore_voltage_select(KSHU1);
+        if (!vcore)
+    #endif
+        vcore = (get_vcore_uv_table(0) + get_vcore_uv_table(1)) >> 1;
+        break;
+    case SRAM_SHU2:  //2400
+    case SRAM_SHU3:  //1866
+    #ifdef VOLTAGE_SEL
+        vcore = vcore_voltage_select(KSHU2);
+        if (!vcore)
+    #endif
+        vcore = (get_vcore_uv_table(0) + get_vcore_uv_table(2)) >> 1;
+        break;
+    case SRAM_SHU4:  //1600
+    case SRAM_SHU5:  //1200
+    case SRAM_SHU6:  //800
+    #ifdef VOLTAGE_SEL
+        vcore = vcore_voltage_select(KSHU4);
+        if (!vcore)
+    #endif
+        vcore = (get_vcore_uv_table(0) + get_vcore_uv_table(3)) >> 1;
+        break;
+    }
+#else
+    switch (vGet_Current_SRAMIdx(p)) {
+    case SRAM_SHU0: // 4266
+    #ifdef VOLTAGE_SEL
+        vcore = vcore_voltage_select(KSHU0);
+    #else
+        vcore = SEL_PREFIX_VCORE(LP4, KSHU0);
+    #endif
+        break;
+    case SRAM_SHU1: // 3200
+    #ifdef VOLTAGE_SEL
+        vcore = vcore_voltage_select(KSHU1);
+    #else
+        vcore = SEL_PREFIX_VCORE(LP4, KSHU1);
+    #endif
+        break;
+    case SRAM_SHU2: // 2400
+    case SRAM_SHU3: //1866
+    #ifdef VOLTAGE_SEL
+        vcore = vcore_voltage_select(KSHU2);
+    #else
+        vcore = SEL_PREFIX_VCORE(LP4, KSHU2);
+    #endif
+        break;
+    case SRAM_SHU4: //1600
+    case SRAM_SHU5: //1200
+    case SRAM_SHU6: //800
+#if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
+    case SRAM_SHU7: //400
+#endif
+    #ifdef VOLTAGE_SEL
+        vcore = vcore_voltage_select(KSHU4);
+    #else
+        vcore = SEL_PREFIX_VCORE(LP4, KSHU4);
+    #endif
+        break;
+    default:
+        return;
+    }
+#endif
+
+    if (vcore)
+        dramc_set_vcore_voltage(vcore);
+
+#if defined(DRAM_HQA)
+    if (vio18)
+        dramc_set_vio18_voltage(vio18);
+
+    if (vdram)
+        dramc_set_vmdd_voltage(p->dram_type, vdram);
+
+    if (vddq)
+        dramc_set_vmddq_voltage(p->dram_type, vddq);
+
+    if (vmddr)
+        dramc_set_vmddr_voltage(vmddr);
+#endif
+
+#ifdef FOR_HQA_REPORT_USED
+    switch (vGet_Current_SRAMIdx(p)) {
+        case SRAM_SHU0: //3733
+        case SRAM_SHU1: //3200
+    case SRAM_SHU2: //2400
+    case SRAM_SHU3: //1866
+    case SRAM_SHU4: //1600
+    case SRAM_SHU5: //1200
+    case SRAM_SHU6: //800
+#if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
+    case SRAM_SHU7: //400
+#endif
+        gHQA_Test_Freq_Vcore_Level = 0; //only 1 freq
+            break;
+        default:
+            print("[HQA] undefined shuffle level for Vcore (SHU%d)\r\n", vGet_Current_SRAMIdx(p));
+#if __ETT__
+            while(1);
+#endif
+            break;
+    }
+#endif
+
+
+#ifndef DDR_INIT_TIME_PROFILING
+    print("Read voltage for %d, %d\n", p->frequency, vGet_Current_SRAMIdx(p));
+    print("Vio18 = %d\n", dramc_get_vio18_voltage());
+    print("Vcore = %d\n", dramc_get_vcore_voltage());
+    print("Vdram = %d\n", dramc_get_vmdd_voltage(p->dram_type));
+    print("Vddq = %d\n", dramc_get_vmddq_voltage(p->dram_type));
+    print("Vmddr = %d\n", dramc_get_vmddr_voltage());
+#endif
+
+#endif
+#endif
+}
+
+U32 vGetVoltage(DRAMC_CTX_T *p, U32 get_voltage_type)
+{
+#if (defined(DRAM_HQA) || defined(__ETT__)) && (FOR_DV_SIMULATION_USED == 0)
+    if (get_voltage_type==0)
+        return dramc_get_vcore_voltage();
+
+    if (get_voltage_type==1)
+        return dramc_get_vmdd_voltage(p->dram_type);
+
+    if (get_voltage_type==2)
+        return dramc_get_vmddq_voltage(p->dram_type);
+
+    if (get_voltage_type==3)
+           return dramc_get_vio18_voltage();
+    if (get_voltage_type==4)
+             return dramc_get_vmddr_voltage();
+
+#endif
+
+    return 0;
+}
+
+
+#if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION
+#define RUNTIME_SHMOO_ON_GOING  0x00
+#define RUNTIME_SHMOO_END       0xff
+void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p)
+{
+    U8 backup_channel, backup_rank;
+    U16 tx_pi_delay, tx_dqm_pi_delay;
+    S16 rx_first_delay=0x1fff, rx_first_delay_bit=0xff, rx_last_delay=-0x1fff, rx_last_delay_bit=0xff;
+    U8 u1BitIdx;
+    U32 u4value;
+    PASS_WIN_DATA_T FinalWinPerBit[DQ_DATA_WIDTH];
+    U8 ui_large_value, ui_small_value, pi_value;
+    U8 ui_dqm_large_value, ui_dqm_small_value, pi_dqm_value;
+#if 0
+    U8 ui_oen_large_value, ui_oen_small_value, pi_oen_value;
+    U8 ui_dqm_oen_large_value, ui_dqm_oen_small_value, pi_dqm_oen_value;
+#endif
+    U8 scan_invert_flag=0;
+
+    backup_channel = p->channel;
+    backup_rank = p->rank;
+
+    p->channel = RUNTIME_SHMOO_TEST_CHANNEL;
+    p->rank = RUNTIME_SHMOO_TEST_RANK;
+
+#if RUNTIME_SHMOO_TX
+    if (RUNTIME_SHMOO_TEST_BYTE == 0)
+    {
+        tx_pi_delay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_DQ0) * 256 +
+                      u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_DQ0) * 32 +
+                      u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), SHU_R0_B0_DQ0_SW_ARPI_DQ_B0);
+
+        tx_dqm_pi_delay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), SHURK_SELPH_DQ1_TXDLY_DQM0) * 256 +
+                          u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), SHURK_SELPH_DQ3_DLY_DQM0) * 32 +
+                          u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), SHU_R0_B0_DQ0_SW_ARPI_DQM_B0);
+    }
+    else
+    {
+        tx_pi_delay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_DQ1) * 256 +
+                      u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_DQ1) * 32 +
+                      u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), SHU_R0_B1_DQ0_SW_ARPI_DQ_B1);
+
+        tx_dqm_pi_delay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), SHURK_SELPH_DQ1_TXDLY_DQM1) * 256 +
+                          u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), SHURK_SELPH_DQ3_DLY_DQM1) * 32 +
+                          u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), SHU_R0_B1_DQ0_SW_ARPI_DQM_B1);
+    }
+#endif
+
+#if RUNTIME_SHMOO_RX
+//    vAutoRefreshSwitch(p, ENABLE);
+
+    for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++)
+    {
+        FinalWinPerBit[u1BitIdx].first_pass=p->pSavetimeData->u1RxWinPerbitDQ_firsbypass_Save[p->channel][p->rank][u1BitIdx+RUNTIME_SHMOO_TEST_BYTE*8];
+        FinalWinPerBit[u1BitIdx].last_pass=p->pSavetimeData->u1RxWinPerbitDQ_lastbypass_Save[p->channel][p->rank][u1BitIdx+RUNTIME_SHMOO_TEST_BYTE*8];
+    }
+
+    //find smallest first and largest last pass
+    for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++)
+    {
+        if (FinalWinPerBit[u1BitIdx].first_pass < rx_first_delay)
+        {
+            rx_first_delay = FinalWinPerBit[u1BitIdx].first_pass;
+            rx_first_delay_bit = u1BitIdx;
+        }
+        if (FinalWinPerBit[u1BitIdx].last_pass > rx_last_delay)
+        {
+            rx_last_delay = FinalWinPerBit[u1BitIdx].last_pass;
+            rx_last_delay_bit = u1BitIdx;
+        }
+    }
+#endif
+
+#if __ETT__
+    mcSHOW_ERR_MSG(("fra dramc_get_rshmoo_pass_cnt = %x\n",dramc_get_rshmoo_pass_cnt()));
+    mcSHOW_ERR_MSG(("fra femmc_Ready = %d ==\n",p->femmc_Ready));
+#else
+    print("fra dramc_get_rshmoo_pass_cnt = %x\n",dramc_get_rshmoo_pass_cnt());
+    print("fra femmc_Ready = %d ==\n",p->femmc_Ready);
+#endif
+
+    if (p->femmc_Ready==0 ||
+ ((p->pSavetimeData->Runtime_Shmoo_para.TX_Channel!=RUNTIME_SHMOO_TEST_CHANNEL) || (p->pSavetimeData->Runtime_Shmoo_para.TX_Rank!=RUNTIME_SHMOO_TEST_RANK) || (p->pSavetimeData->Runtime_Shmoo_para.TX_Byte!=RUNTIME_SHMOO_TEST_BYTE))) //first K
+    {
+#if RUNTIME_SHMOO_TX
+        p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_ON_GOING; //on going
+        p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction=0;
+        p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay = tx_pi_delay-32+RUNTIME_SHMOO_TEST_PI_DELAY_START;
+        p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay;
+        p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay = tx_dqm_pi_delay-32+RUNTIME_SHMOO_TEST_PI_DELAY_START;
+        p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay;
+        if (RUNTIME_SHMOO_TEST_VREF_START<51)
+        {
+            p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 0;
+            p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value = RUNTIME_SHMOO_TEST_VREF_START;
+        }
+        else
+        {
+            p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 1;
+            p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value = RUNTIME_SHMOO_TEST_VREF_START-51+21;
+        }
+        p->pSavetimeData->Runtime_Shmoo_para.TX_Channel = RUNTIME_SHMOO_TEST_CHANNEL;
+        p->pSavetimeData->Runtime_Shmoo_para.TX_Rank = RUNTIME_SHMOO_TEST_RANK;
+        p->pSavetimeData->Runtime_Shmoo_para.TX_Byte = RUNTIME_SHMOO_TEST_BYTE;
+#endif
+
+#if RUNTIME_SHMOO_RX
+        p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_ON_GOING; //on going
+        p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction=0;
+        p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 0;
+        p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value = 0;
+        for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++)
+        {
+            p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx] = FinalWinPerBit[u1BitIdx].first_pass- RUNTIME_SHMOO_RX_TEST_MARGIN;
+        }
+        p->pSavetimeData->Runtime_Shmoo_para.RX_Original_delay = p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0];
+        p->pSavetimeData->Runtime_Shmoo_para.TX_Channel = RUNTIME_SHMOO_TEST_CHANNEL;
+        p->pSavetimeData->Runtime_Shmoo_para.TX_Rank = RUNTIME_SHMOO_TEST_RANK;
+        p->pSavetimeData->Runtime_Shmoo_para.TX_Byte = RUNTIME_SHMOO_TEST_BYTE;
+#endif
+    }
+//fra    else  if (dramc_get_rshmoo_step())
+    else if ((dramc_get_rshmoo_step()) && (p->pSavetimeData->Runtime_Shmoo_para.flag != RUNTIME_SHMOO_END))
+    {
+        //judge scan direction
+        if (RUNTIME_SHMOO_FAST_K == 0)
+        {
+            p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction=0;
+        }
+        else
+        {
+            if (dramc_get_rshmoo_pass_cnt() > (RUNTIME_SHMOO_FAST_K-1))
+            {
+                if (p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction==0)
+                {
+                    p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction=1;
+                }
+                else
+                {
+                    p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction=0;
+                }
+
+                scan_invert_flag = 1;
+            }
+        }
+
+        if (scan_invert_flag == 0)
+        {
+            if (p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction==0)
+            {
+#if RUNTIME_SHMOO_TX
+        p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay += RUNTIME_SHMOO_TEST_PI_DELAY_STEP;
+        if (p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay > p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay+RUNTIME_SHMOO_TEST_PI_DELAY_END)
+        {
+            p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay;
+            p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP;
+
+            if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value+p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range*30) > RUNTIME_SHMOO_TEST_VREF_END)
+            {
+                p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish
+            }
+            else
+            {
+                if (p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range==0)
+                {
+                    if (p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value > 50)
+                    {
+                        p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 1;
+                        p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value -= 30;
+                    }
+                }
+            }
+        }
+
+        p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay += RUNTIME_SHMOO_TEST_PI_DELAY_STEP;
+        if (p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay > p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay+RUNTIME_SHMOO_TEST_PI_DELAY_END)
+        {
+            p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay;
+        }
+#endif
+
+#if RUNTIME_SHMOO_RX
+                for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++)
+                {
+                    p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx] += RUNTIME_SHMOO_TEST_PI_DELAY_STEP;
+                }
+                if (p->pSavetimeData->Runtime_Shmoo_para.RX_delay[rx_last_delay_bit] > rx_last_delay+RUNTIME_SHMOO_RX_TEST_MARGIN)
+                {
+                    for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++)
+                    {
+                        p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx] = FinalWinPerBit[u1BitIdx].first_pass - RUNTIME_SHMOO_RX_TEST_MARGIN;
+                    }
+                    p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP;
+                    if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value) > RUNTIME_SHMOO_RX_VREF_RANGE_END)
+                    {
+                        p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish
+                    }
+                }
+#endif
+    }
+            else
+            {
+#if RUNTIME_SHMOO_TX
+                p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay -= RUNTIME_SHMOO_TEST_PI_DELAY_STEP;
+                if (p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay < p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay)
+                {
+                    p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay + (RUNTIME_SHMOO_TEST_PI_DELAY_END+1);
+                    p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP;
+
+                    if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value+p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range*30) > RUNTIME_SHMOO_TEST_VREF_END)
+                    {
+                        p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish
+                    }
+                    else
+                    {
+                        if (p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range==0)
+                        {
+                            if (p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value > 50)
+                            {
+                                p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 1;
+                                p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value -= 30;
+                            }
+                        }
+                    }
+                }
+
+                p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay -= RUNTIME_SHMOO_TEST_PI_DELAY_STEP;
+                if (p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay < p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay)
+                {
+                    p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay + (RUNTIME_SHMOO_TEST_PI_DELAY_END+1);
+                }
+#endif
+
+#if RUNTIME_SHMOO_RX
+                for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++)
+                {
+                    p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx] -= RUNTIME_SHMOO_TEST_PI_DELAY_STEP;
+                }
+                if (p->pSavetimeData->Runtime_Shmoo_para.RX_delay[rx_first_delay_bit] < rx_first_delay-RUNTIME_SHMOO_RX_TEST_MARGIN)
+                {
+                    for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++)
+                    {
+                        p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx] = FinalWinPerBit[u1BitIdx].last_pass + RUNTIME_SHMOO_RX_TEST_MARGIN;
+                    }
+                    p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP;
+                    if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value) > RUNTIME_SHMOO_RX_VREF_RANGE_END)
+                    {
+                        p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish
+                    }
+                }
+#endif
+
+            }
+        }
+        else
+        {
+            if (p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction==0)
+            {
+#if RUNTIME_SHMOO_TX
+                p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay;
+                p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP;
+
+                if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value+p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range*30) > RUNTIME_SHMOO_TEST_VREF_END)
+                {
+                    p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish
+                }
+                else
+                {
+                    if (p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range==0)
+                    {
+                        if (p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value > 50)
+                        {
+                            p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 1;
+                            p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value -= 30;
+                        }
+                    }
+                }
+
+                p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay;
+#endif
+
+#if RUNTIME_SHMOO_RX
+                for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++)
+                {
+                    p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx] = FinalWinPerBit[u1BitIdx].first_pass - RUNTIME_SHMOO_RX_TEST_MARGIN;
+                }
+                p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP;
+
+                if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value) > RUNTIME_SHMOO_RX_VREF_RANGE_END)
+                {
+                    p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish
+                }
+#endif
+            }
+            else
+            {
+#if RUNTIME_SHMOO_TX
+                p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay + (RUNTIME_SHMOO_TEST_PI_DELAY_END+1);
+                //p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP;
+
+                p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_Original_DQM_PI_delay + (RUNTIME_SHMOO_TEST_PI_DELAY_END+1);
+#endif
+
+#if RUNTIME_SHMOO_RX
+                for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++)
+                {
+                    p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx] = FinalWinPerBit[u1BitIdx].last_pass + RUNTIME_SHMOO_RX_TEST_MARGIN;
+                }
+#endif
+            }
+        }
+    }
+
+#if __ETT__
+    mcSHOW_ERR_MSG(("Fra RunTime Shmoo CH%d, Rank%d, Byte%d\n",RUNTIME_SHMOO_TEST_CHANNEL, RUNTIME_SHMOO_TEST_RANK, RUNTIME_SHMOO_TEST_BYTE ));
+#else
+    print("Fra RunTime Shmoo CH%d, Rank%d, Byte%d\n",RUNTIME_SHMOO_TEST_CHANNEL, RUNTIME_SHMOO_TEST_RANK, RUNTIME_SHMOO_TEST_BYTE );
+#endif
+
+//fra    if (p->pSavetimeData->Runtime_Shmoo_para.flag != RUNTIME_SHMOO_END)
+    {
+#if RUNTIME_SHMOO_TX
+#if __ETT__
+        mcSHOW_ERR_MSG(("Fra RunTime Shmoo original K TX Vref = (%d, %d)\n", (u1MR14Value[RUNTIME_SHMOO_TEST_CHANNEL][RUNTIME_SHMOO_TEST_RANK][p->dram_fsp]>>6) & 1, u1MR14Value[RUNTIME_SHMOO_TEST_CHANNEL][RUNTIME_SHMOO_TEST_RANK][p->dram_fsp] & 0x3f));
+        mcSHOW_ERR_MSG(("Fra RunTime Shmoo original K TX Byte%d PI Delay = %d\n", RUNTIME_SHMOO_TEST_BYTE, p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay+32-RUNTIME_SHMOO_TEST_PI_DELAY_START));
+
+        mcSHOW_ERR_MSG(("Fra RunTime Shmoo TX Vref = (%d, %d)\n", p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value));
+        mcSHOW_ERR_MSG(("Fra RunTime Shmoo TX Byte%d PI Delay = %d\n", RUNTIME_SHMOO_TEST_BYTE, p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay-p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay));
+#else
+        print("Fra RunTime Shmoo original K TX Vref = (%d, %d)\n", (u1MR14Value[RUNTIME_SHMOO_TEST_CHANNEL][RUNTIME_SHMOO_TEST_RANK][p->dram_fsp]>>6) & 1, u1MR14Value[RUNTIME_SHMOO_TEST_CHANNEL][RUNTIME_SHMOO_TEST_RANK][p->dram_fsp] & 0x3f);
+        print("Fra RunTime Shmoo original K TX Byte%d PI Delay = %d\n", RUNTIME_SHMOO_TEST_BYTE, p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay+32-RUNTIME_SHMOO_TEST_PI_DELAY_START);
+
+        print("Fra RunTime Shmoo TX Vref = (%d, %d)\n", p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value);
+        print("Fra RunTime Shmoo TX Byte%d PI Delay = %d\n", RUNTIME_SHMOO_TEST_BYTE, p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay-p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay);
+#endif
+#endif
+
+#if RUNTIME_SHMOO_RX
+        mcSHOW_ERR_MSG(("Fra RunTime Shmoo K RX Vref = %d\n", p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value));
+        mcSHOW_ERR_MSG(("Fra RunTime Shmoo RX Byte%d Delay = %d\n", RUNTIME_SHMOO_TEST_BYTE, p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0]));
+#endif
+
+#if RUNTIME_SHMOO_TX
+        TxWinTransferDelayToUIPI(p, TX_DQ_DQS_MOVE_DQ_DQM, p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay, 1, &ui_large_value, &ui_small_value, &pi_value);
+        TxWinTransferDelayToUIPI(p, TX_DQ_DQS_MOVE_DQ_DQM, p->pSavetimeData->Runtime_Shmoo_para.TX_DQM_PI_delay, 1, &ui_dqm_large_value, &ui_dqm_small_value, &pi_dqm_value);
+
+        if (RUNTIME_SHMOO_TEST_BYTE == 0)
+        {
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), ui_large_value, SHURK_SELPH_DQ0_TXDLY_DQ0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), ui_small_value, SHURK_SELPH_DQ2_DLY_DQ0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), pi_value, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0);
+
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), ui_dqm_large_value, SHURK_SELPH_DQ1_TXDLY_DQM0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), ui_dqm_small_value, SHURK_SELPH_DQ3_DLY_DQM0);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), pi_dqm_value, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0);
+        }
+        else
+        {
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), ui_large_value, SHURK_SELPH_DQ0_TXDLY_DQ1);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), ui_small_value, SHURK_SELPH_DQ2_DLY_DQ1);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), pi_value, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1);
+
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), ui_dqm_large_value, SHURK_SELPH_DQ1_TXDLY_DQM1);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), ui_dqm_small_value, SHURK_SELPH_DQ3_DLY_DQM1);
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), pi_dqm_value, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1);
+        }
+        DramcTXSetVref(p, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value);
+
+        //DLL all off from Justin
+    #if 0
+    #if ENABLE_MCK8X_MODE
+        vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_SHU_CA_DLL0), 0x0, SHU_CA_DLL0_RG_ARDLL_PHDET_EN_CA_SHU);
+        vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DLL0), 0x0, SHU_B0_DLL0_RG_ARDLL_PHDET_EN_B0_SHU);
+        vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_SHU_B1_DLL0), 0x0, SHU_B1_DLL0_RG_ARDLL_PHDET_EN_B1_SHU);
+    #else
+        vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_CA_DLL_ARPI2), 0x0, CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA);
+        vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_B0_DLL_ARPI2), 0x0, B0_DLL_ARPI2_RG_ARDLL_PHDET_EN_B0);
+        vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_B1_DLL_ARPI2), 0x0, B1_DLL_ARPI2_RG_ARDLL_PHDET_EN_B1);
+    #endif
+    #endif
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DLL1, 0x0, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0);
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DLL1, 0x0, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1);
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_DLL1, 0x0, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA);
+
+#endif
+
+
+
+#if RUNTIME_SHMOO_RX
+    // here has a problem, RX dq is perbit but I just can choose one (bit0) to do compare and setting
+    if (p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0] <=0)
+    {
+#if 0
+        // Set DQS delay
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ6 + 0x50*RUNTIME_SHMOO_TEST_BYTE), \
+                                P_Fld((-p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0]),SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0) |P_Fld((-p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0]),SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0));
+
+        // Set DQM delay to 0
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ6 + 0x50*RUNTIME_SHMOO_TEST_BYTE), \
+                                P_Fld(0,SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0) |P_Fld(0,SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0));
+
+        DramPhyReset(p);
+#endif
+        // Set DQ delay to 0
+        for (u1BitIdx=0; u1BitIdx<4; u1BitIdx++)
+        {
+                vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + DDRPHY_AO_B0_B1_OFFSET*RUNTIME_SHMOO_TEST_BYTE + u1BitIdx*4), 0);//DQ0~DQ7
+        }
+    }
+    else
+    {
+#if 0
+        // Set DQS delay to 0
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ6 + 0x50*RUNTIME_SHMOO_TEST_BYTE), \
+                                P_Fld(0,SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0) |P_Fld(0,SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0));
+
+
+        // Adjust DQM output delay.
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ6 + 0x50*RUNTIME_SHMOO_TEST_BYTE), \
+                                P_Fld(p->pSavetimeData->Runtime_Shmoo_para.RX_delay,SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0) |P_Fld(p->pSavetimeData->Runtime_Shmoo_para.RX_delay,SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0));
+
+        DramPhyReset(p);
+#endif
+        // Adjust DQ output delay.
+        for (u1BitIdx=0; u1BitIdx<8; u1BitIdx+=2)
+        {
+             vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0+ (DDRPHY_AO_B0_B1_OFFSET*RUNTIME_SHMOO_TEST_BYTE) +u1BitIdx*2), \
+                                            P_Fld(((U32)p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx]),SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |\
+                                            P_Fld(((U32)p->pSavetimeData->Runtime_Shmoo_para.RX_delay[u1BitIdx+1]),SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0));
+
+        }
+    }
+
+    //Set Vref
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ5 + DDRPHY_AO_B0_B1_OFFSET*RUNTIME_SHMOO_TEST_BYTE), p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0);  // LP4 and LP4x with term: 0xe
+#endif
+    }
+
+    //save parameters to eMMC
+#if EMMC_READY
+    write_offline_dram_calibration_data(vGet_Current_SRAMIdx(p), p->pSavetimeData);
+#endif
+    mcSHOW_ERR_MSG(("Fra Save calibration result to emmc\n"));
+
+    //copy parameters to memory for kernel test script used
+    //wait for YiRong's SRAM copy function
+#if RUNTIME_SHMOO_TX
+    dramc_set_rshmoo_info(p->pSavetimeData->Runtime_Shmoo_para.TX_Rank, p->pSavetimeData->Runtime_Shmoo_para.TX_Channel,
+        p->pSavetimeData->Runtime_Shmoo_para.TX_Byte, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value,
+        p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay-p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay, 1, (p->pSavetimeData->Runtime_Shmoo_para.flag == RUNTIME_SHMOO_END) ? 1 : 0);
+#endif
+
+#if RUNTIME_SHMOO_RX
+    dramc_set_rshmoo_info(p->pSavetimeData->Runtime_Shmoo_para.TX_Rank, p->pSavetimeData->Runtime_Shmoo_para.TX_Channel,
+        p->pSavetimeData->Runtime_Shmoo_para.TX_Byte, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value,
+        p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0], 1, (p->pSavetimeData->Runtime_Shmoo_para.flag == RUNTIME_SHMOO_END) ? 1 : 0);
+
+//    vAutoRefreshSwitch(p, DISABLE); //After gating, Rx and Tx calibration, auto refresh should be disable
+
+#endif
+
+    p->channel = backup_channel;
+    p->rank = backup_rank;
+}
+#endif
+
+
+///TODO: wait for porting +++
+#ifdef FIRST_BRING_UP
+void Test_Broadcast_Feature(DRAMC_CTX_T *p)
+{
+    U32 u4RegBackupAddress[] =
+    {
+        (DRAMC_REG_SHURK_SELPH_DQ2),
+        (DRAMC_REG_SHURK_SELPH_DQ2 + SHIFT_TO_CHB_ADDR),
+
+        (DDRPHY_REG_SHU_RK_B0_DQ0),
+        (DDRPHY_REG_SHU_RK_B0_DQ0 + SHIFT_TO_CHB_ADDR),
+    };
+    U32 read_value;
+    U32 backup_broadcast;
+
+    backup_broadcast = GetDramcBroadcast();
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+    DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+
+    vIO32Write4B(DRAMC_REG_SHURK_SELPH_DQ2, 0xA55A00FF);
+    vIO32Write4B(DDRPHY_REG_SHU_RK_B0_DQ0, 0xA55A00FF);
+
+    read_value = u4IO32Read4B(DRAMC_REG_SHURK_SELPH_DQ2 + SHIFT_TO_CHB_ADDR);
+    if (read_value != 0xA55A00FF)
+    {
+        mcSHOW_ERR_MSG(("Check Erro! Broad Cast CHA RG to CHB Fail!!\n"));
+        while (1);
+    }
+
+    read_value = u4IO32Read4B(DDRPHY_REG_SHU_RK_B0_DQ0 + SHIFT_TO_CHB_ADDR);
+    if (read_value != 0xA55A00FF)
+    {
+        mcSHOW_ERR_MSG(("Check Erro! Broad Cast CHA RG to CHB Fail!!\n"));
+        while (1);
+    }
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+    DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
+
+    DramcBroadcastOnOff(backup_broadcast);
+}
+#endif
+
+#if __ETT__
+void ett_set_emi_rank1_address(void)
+{
+    static unsigned int remap_rank1_done = 0;
+
+    if (!remap_rank1_done)
+    {
+    #ifndef MT6880_FPGA
+        set_emi_before_rank1_mem_test();
+    #endif
+        remap_rank1_done = 1;
+    }
+}
+#endif
+
+static void mem_test_address_calculation(DRAMC_CTX_T * p, U32 uiSrcAddr, U32*pu4Dest)
+{
+#if __ETT__
+    ett_set_emi_rank1_address();
+
+    *pu4Dest = uiSrcAddr - RANK0_START_VA + RANK1_START_VA;
+#else
+    *pu4Dest = uiSrcAddr + p->ranksize[RANK_0];
+#endif
+}
+
+#if CPU_RW_TEST_AFTER_K
+static void vDramCPUReadWriteTestAfterCalibration(DRAMC_CTX_T *p)
+{
+    U8 u1DumpInfo=0, u1RankIdx;
+    U32 uiLen, uiRankdAddr[RANK_MAX];
+    U32 pass_count, err_count;
+    U64 count, uiFixedAddr; //[FOR_CHROMEOS] Change type from U32 to U64
+    uiLen = 0xffff;
+
+#if GATING_ONLY_FOR_DEBUG
+    DramcGatingDebugInit(p);
+#endif
+
+    uiRankdAddr[0] = DDR_BASE;
+    mem_test_address_calculation(p, DDR_BASE, &uiRankdAddr[1]);
+
+    for(u1RankIdx =0; u1RankIdx< p->support_rank_num; u1RankIdx++)
+    {
+        u1DumpInfo=0;
+        err_count=0;
+        pass_count=0;
+
+        #if !__ETT__
+        // scy: not to test rank1 (wrong addr 0x0000_0000)
+        if (u1RankIdx >= 1)
+            continue;
+        #endif
+
+        #if GATING_ONLY_FOR_DEBUG
+        DramcGatingDebugRankSel(p, u1RankIdx);
+        #endif
+
+        uiFixedAddr = uiRankdAddr[u1RankIdx];
+
+        for (count= 0; count<uiLen; count+=4)
+        {
+            *(volatile unsigned int   *)(count +uiFixedAddr) = count + (0x5a5a <<16);
+        }
+
+        for (count=0; count<uiLen; count+=4)
+        {
+            if (*(volatile unsigned int   *)(count +uiFixedAddr) != count + (0x5a5a <<16))
+            {
+                //mcSHOW_DBG_MSG(("[Fail] Addr %xh = %xh\n",count, *(volatile unsigned int   *)(count)));
+                err_count++;
+            }
+            else
+                pass_count ++;
+        }
+
+#if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION
+        if (err_count==0)
+        {
+#if __ETT__
+            mcSHOW_ERR_MSG(("CH %c,RANK %d,BYTE %d,VRANGE %d,VREF %d,PI %d,MEM_RESULT PASS\n",
+                p->pSavetimeData->Runtime_Shmoo_para.TX_Channel == 0 ? 'A' : 'B',
+                p->pSavetimeData->Runtime_Shmoo_para.TX_Rank,
+                p->pSavetimeData->Runtime_Shmoo_para.TX_Byte,
+                p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range,
+                p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value,
+                p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay-p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay));
+#else
+            print("CH %c,RANK %d,BYTE %d,VRANGE %d,VREF %d,PI %d,MEM_RESULT PASS\n",
+                p->pSavetimeData->Runtime_Shmoo_para.TX_Channel == 0 ? 'A' : 'B',
+                p->pSavetimeData->Runtime_Shmoo_para.TX_Rank,
+                p->pSavetimeData->Runtime_Shmoo_para.TX_Byte,
+                p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range,
+                p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value,
+                p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay-p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay);
+#endif
+        }
+#else
+        if(err_count)
+        {
+            mcSHOW_DBG_MSG2(("[MEM_TEST] Rank %d Fail.", u1RankIdx));
+            u1DumpInfo =1;
+#if defined(SLT)
+            mcSHOW_ERR_MSG(("\n[EMI] EMI_FATAL_ERR_FLAG = 0x00000001, line: %d\n",__LINE__));
+            while(1);
+#endif
+        }
+        else
+        {
+            mcSHOW_DBG_MSG2(("[MEM_TEST] Rank %d OK.", u1RankIdx));
+        }
+        mcSHOW_DBG_MSG2(("(uiFixedAddr 0x%llX, Pass count =%d, Fail count =%d)\n", uiFixedAddr, pass_count, err_count)); //[FOR_CHROMEOS]
+#endif
+    }
+
+    if(u1DumpInfo)
+    {
+        // Read gating error flag
+        #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
+        DramcDumpDebugInfo(p);
+        #endif
+    }
+
+    #if GATING_ONLY_FOR_DEBUG
+    DramcGatingDebugExit(p);
+    #endif
+}
+#endif
+
+
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+#if !EMMC_READY
+u32 g_dram_save_time_init_done[DRAM_DFS_SRAM_MAX] = {0};
+SAVE_TIME_FOR_CALIBRATION_T SaveTimeDataByShuffle[DRAM_DFS_SRAM_MAX];
+#endif
+static DRAM_STATUS_T DramcSave_Time_For_Cal_End(DRAMC_CTX_T *p)
+{
+    if (!u1IsLP4Family(p->dram_type))
+        return DRAM_FAIL;
+
+    if (p->femmc_Ready == 0)
+    {
+        #if EMMC_READY
+        write_offline_dram_calibration_data(vGet_Current_SRAMIdx(p), p->pSavetimeData);
+        mcSHOW_DBG_MSG(("[FAST_K] Save calibration result to emmc\n"));
+        #else
+        g_dram_save_time_init_done[vGet_Current_SRAMIdx(p)] = 1;
+        memcpy(&(SaveTimeDataByShuffle[vGet_Current_SRAMIdx(p)]), p->pSavetimeData, sizeof(SAVE_TIME_FOR_CALIBRATION_T));
+        mcSHOW_DBG_MSG(("[FAST_K] Save calibration result to SW memory\n"));
+        #endif
+    }
+    else
+    {
+        mcSHOW_DBG_MSG(("[FAST_K] Bypass saving calibration result to emmc\n"));
+    }
+
+    return DRAM_OK;
+}
+
+static DRAM_STATUS_T DramcSave_Time_For_Cal_Init(DRAMC_CTX_T *p)
+{
+    if (!u1IsLP4Family(p->dram_type))
+        return DRAM_FAIL;
+
+    if (doe_get_config("fullk"))
+        return DRAM_FAIL;
+
+    // Parepare fask k data
+    #if EMMC_READY
+    // scy: only need to read emmc one time for each boot-up
+    //if (g_dram_save_time_init_done == 1)
+    //    return DRAM_OK;
+    //else
+    //    g_dram_save_time_init_done = 1;
+    if (read_offline_dram_calibration_data(vGet_Current_SRAMIdx(p), p->pSavetimeData) < 0)
+        {
+        p->femmc_Ready = 0;
+        memset(p->pSavetimeData, 0, sizeof(SAVE_TIME_FOR_CALIBRATION_T));
+        }
+    else
+        {
+        p->femmc_Ready = 1;
+        }
+
+    #else //EMMC is not avaliable, load off-line data
+
+    if (g_dram_save_time_init_done[vGet_Current_SRAMIdx(p)] == 0)
+    {
+        p->femmc_Ready = 0;
+        memset(p->pSavetimeData, 0, sizeof(SAVE_TIME_FOR_CALIBRATION_T));
+    }
+    else
+    {
+        memcpy(p->pSavetimeData, &(SaveTimeDataByShuffle[vGet_Current_SRAMIdx(p)]), sizeof(SAVE_TIME_FOR_CALIBRATION_T));
+        p->femmc_Ready = 1;
+    }
+    #endif
+
+    if (p->femmc_Ready == 1)
+    {
+        if (p->frequency < 1600)
+        {   // freq < 1600, TX and RX tracking are disable. Therefore, bypass calibration.
+            p->Bypass_RDDQC = 1;
+            p->Bypass_RXWINDOW = 1;
+            p->Bypass_TXWINDOW = 1;
+    }
+    else
+    {
+            p->Bypass_RDDQC = 1;
+            p->Bypass_RXWINDOW = !ENABLE_RX_TRACKING;
+            p->Bypass_TXWINDOW = 0;
+    }
+
+#if RUNTIME_SHMOO_RELEATED_FUNCTION
+        p->Bypass_RDDQC = 1;
+        p->Bypass_RXWINDOW = 1;
+        p->Bypass_TXWINDOW = 1;
+#endif
+    }
+
+#if EMMC_READY
+    mcSHOW_DBG_MSG(("[FAST_K] DramcSave_Time_For_Cal_Init SRAM_SHU%d, femmc_Ready=%d\n", vGet_Current_SRAMIdx(p), p->femmc_Ready));
+#else
+    mcSHOW_DBG_MSG(("[FAST_K] DramcSave_Time_For_Cal_Init SRAM_SHU%d, Init_done=%d, femmc_Ready=%d\n", vGet_Current_SRAMIdx(p), g_dram_save_time_init_done[vGet_Current_SRAMIdx(p)], p->femmc_Ready));
+#endif
+    mcSHOW_DBG_MSG(("[FAST_K] Bypass_RDDQC %d, Bypass_RXWINDOW=%d, Bypass_TXWINDOW=%d\n", p->Bypass_RDDQC, p->Bypass_RXWINDOW, p->Bypass_TXWINDOW));
+
+    return DRAM_OK;
+}
+#endif
+
+#if ENABLE_RANK_NUMBER_AUTO_DETECTION
+static void DramRankNumberDetection(DRAMC_CTX_T *p)
+{
+    U8 u1RankBak;
+
+    u1RankBak = u1GetRank(p);  // backup current rank setting
+
+    vSetPHY2ChannelMapping(p, CHANNEL_A); // when switching channel, must update PHY to Channel Mapping
+    vSetRank(p, RANK_1);
+
+    if (DramcWriteLeveling(p, AUTOK_ON, PI_BASED) == DRAM_OK)
+    {
+        p->support_rank_num = RANK_DUAL;
+        vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, 0, SA_RESERVE_SINGLE_RANK);  //keep support_rank_num to reserved rg
+    }
+    else
+    {
+        p->support_rank_num = RANK_SINGLE;
+        vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, 1, SA_RESERVE_SINGLE_RANK);  //keep support_rank_num to reserved rg
+    }
+    mcSHOW_DBG_MSG2(("[RankNumberDetection] %d\n", p->support_rank_num));
+
+    vSetRank(p, u1RankBak);  // restore rank setting
+}
+#endif
+
+#if (FOR_DV_SIMULATION_USED == 0)
+static void UpdateGlobal10GBEnVariables(DRAMC_CTX_T *p)
+{
+    p->u110GBEn[RANK_0] = (get_row_width_by_emi(RANK_0) >= 18) ? ENABLE : DISABLE;
+    p->u110GBEn[RANK_1] = (get_row_width_by_emi(RANK_1) >= 18) ? ENABLE : DISABLE;
+    //mcSHOW_DBG_MSG(("[10GBEn] RANK0=%d, RANK1=%d\n", p->u110GBEn[RANK_0], p->u110GBEn[RANK_1]));
+}
+#endif
+
+void vCalibration_Flow_For_MDL(DRAMC_CTX_T *p)
+{
+    U8 u1RankMax;
+    S8 s1RankIdx;
+
+#if GATING_ADJUST_TXDLY_FOR_TRACKING
+    DramcRxdqsGatingPreProcess(p);
+#endif
+
+    if (p->support_rank_num == RANK_DUAL)
+        u1RankMax = RANK_MAX;
+    else
+        u1RankMax = RANK_1;
+
+    for (s1RankIdx = RANK_0; s1RankIdx < u1RankMax; s1RankIdx++)
+    {
+        vSetRank(p, s1RankIdx);
+
+        vAutoRefreshSwitch(p, ENABLE); //when doing gating, RX and TX calibration, auto refresh should be enable
+        dramc_rx_dqs_gating_cal(p, AUTOK_OFF, 0);
+        DramcRxWindowPerbitCal(p, PATTERN_RDDQC, NULL, AUTOK_OFF, NORMAL_K);
+
+#if MRW_CHECK_ONLY
+        mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+#endif
+        vAutoRefreshSwitch(p, DISABLE); //After gating, Rx and Tx calibration, auto refresh should be disable
+    }
+
+    vSetRank(p, RANK_0); // Set p's rank back to 0 (Avoids unexpected auto-rank offset calculation in u4RegBaseAddrTraslate())
+
+#if GATING_ADJUST_TXDLY_FOR_TRACKING
+    DramcRxdqsGatingPostProcess(p);
+#endif
+}
+
+static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInfo)
+{
+    U8 u1RankIdx, u1DieNumber = 0; //u1ChannelIdx, u1RankMax,
+    U16 u2Density;
+    U16 u2MR7;
+    U16 u2MR8 = 0;
+    U64 u8Size = 0, u8Size_backup = 0;
+    //U64 u8ChannelSize;
+    //U32 u4ChannelNumber = 1, u4RankNumber = 1;
+
+    if (p->revision_id != REVISION_ID_MAGIC)
+        return 0;
+
+    vSetPHY2ChannelMapping(p, CHANNEL_A);
+
+    // Read MR5 for Vendor ID
+    DramcModeRegReadByRank(p, RANK_0, 5, &(p->vendor_id));// for byte mode, don't show value of another die.
+    p->vendor_id &= 0xFF;
+    mcSHOW_DBG_MSG2(("[GetDramInforAfterCalByMRR] Vendor %x.\n", p->vendor_id));
+    // Read MR6 for Revision ID
+    DramcModeRegReadByRank(p, RANK_0, 6, &(p->revision_id));// for byte mode, don't show value of another die.
+    mcSHOW_DBG_MSG2(("[GetDramInforAfterCalByMRR] Revision %x.\n", p->revision_id));
+    // Read MR6 for Revision ID2
+    DramcModeRegReadByRank(p, RANK_0, 7, &u2MR7);// for byte mode, don't show value of another die.
+    mcSHOW_DBG_MSG2(("[GetDramInforAfterCalByMRR] Revision 2 %x.\n", u2MR7));
+#if (!__ETT__) && (FOR_DV_SIMULATION_USED==0)
+    set_dram_mr(5, p->vendor_id);
+    set_dram_mr(6, p->revision_id);
+    set_dram_mr(7, u2MR7);
+#endif
+    if (DramInfo != NULL)
+    {
+        DramInfo->u2MR5VendorID = p->vendor_id;
+        DramInfo->u2MR6RevisionID = p->revision_id;
+
+            for(u1RankIdx =0; u1RankIdx<RANK_MAX; u1RankIdx++)
+                DramInfo->u8MR8Density[u1RankIdx] =0;
+    }
+
+    // Read MR8 for dram density
+    for (u1RankIdx = 0; u1RankIdx < (p->support_rank_num); u1RankIdx++)
+    {
+        #if 0//PRINT_CALIBRATION_SUMMARY
+        if ((p->aru4CalExecuteFlag[u1ChannelIdx][u1RankIdx] != 0) && \
+            (p->aru4CalResultFlag[u1ChannelIdx][u1RankIdx] == 0))
+        #endif
+        {
+            DramcModeRegReadByRank(p, u1RankIdx, 0, &(gu2MR0_Value[u1RankIdx]));
+            mcSHOW_DBG_MSG2(("MR0 0x%x\n", gu2MR0_Value[u1RankIdx]));
+
+            DramcModeRegReadByRank(p, u1RankIdx, 8, &u2Density);
+            mcSHOW_DBG_MSG2(("MR8 0x%x\n", u2Density));
+            u2MR8 |= (u2Density & 0xFF) << (u1RankIdx * 8);
+
+            u1DieNumber = 1;
+            if (((u2Density >> 6) & 0x3) == 1) //OP[7:6] =0, x16 (normal mode)
+                u1DieNumber = 2;
+
+            if (DramInfo != NULL)
+                DramInfo->u1DieNum[u1RankIdx] = u1DieNumber;
+
+            u2Density = (u2Density >> 2) & 0xf;
+
+            switch (u2Density)
+            {
+                ///TODO: Darren, please check the value of u8Size.
+                case 0x0:
+                    u8Size = 0x20000000;  //4Gb = 512MB
+                    //mcSHOW_DBG_MSG(("[EMI]DRAM density = 4Gb\n"));
+                    break;
+                case 0x1:
+                    u8Size = 0x30000000;  //6Gb = 768MB
+                    //mcSHOW_DBG_MSG(("[EMI]DRAM density = 6Gb\n"));
+                    break;
+                case 0x2:
+                    u8Size = 0x40000000;  //8Gb = 1GB = 2^30 bytes = 0x40000000 bytes
+                    //mcSHOW_DBG_MSG(("[EMI]DRAM density = 8Gb\n"));
+                    break;
+                case 0x3:
+                    u8Size = 0x60000000;  //12Gb = 1.5GB = 3^30 bytes = 0x60000000 bytes
+                    //mcSHOW_DBG_MSG(("[EMI]DRAM density = 12Gb\n"));
+                    break;
+                case 0x4:
+                    u8Size = 0x80000000;  //16Gb = 2GB = 4^30 bytes = 0x80000000 bytes
+                    //mcSHOW_DBG_MSG(("[EMI]DRAM density = 16Gb\n"));
+                    break;
+                case 0x5:
+                    u8Size = 0xc0000000; //24Gb = 3GB = 6^30 bytes = 0xc0000000 bytes
+                    //mcSHOW_DBG_MSG(("[EMI]DRAM density = 24Gb\n"));
+                    break;
+                case 0x6:
+                    u8Size = 0x100000000L; //32Gb = 4GB = 8^30 bytes = 0x10000000 bytes
+                    //mcSHOW_DBG_MSG(("[EMI]DRAM density = 32Gb\n"));
+                    break;
+                default:
+                    u8Size = 0; //reserved
+            }
+
+    #if (fcFOR_CHIP_ID == fc8195)
+            if (p->support_channel_num == CHANNEL_SINGLE)
+                u8Size >>= 1;
+    #endif
+
+            if (u8Size_backup < u8Size) // find max dram size for vDramcACTimingOptimize
+            {
+                u8Size_backup = u8Size;
+                p->density = u2Density;
+            }
+
+            p->ranksize[u1RankIdx] = u8Size * u1DieNumber;  //dram rank size = density * DieNumber
+
+            if (DramInfo != NULL)
+            {
+                DramInfo->u8MR8Density[u1RankIdx] = p->ranksize[u1RankIdx];
+            }
+        }
+    DramInfo->u4RankNum = p->support_rank_num;
+    // 1GB = 2^30 bytes
+        // u8Size * (2^3) / (2^30)  ==>Gb
+        mcSHOW_DBG_MSG2(("RK%d, DieNum %d, Density %dGb, RKsize %dGb.\n\n", u1RankIdx, u1DieNumber, (U32)(u8Size >> 27), (U32)(p->ranksize[u1RankIdx] >> 27)));
+    }
+#if (!__ETT__) && (FOR_DV_SIMULATION_USED==0)
+    set_dram_mr(8, u2MR8);
+#endif
+    return 0;
+}
+
+static void vCalibration_Flow_LP4(DRAMC_CTX_T *p)
+{
+    U8 u1RankMax;
+    S8 s1RankIdx;
+    //DRAM_STATUS_T VrefStatus;
+
+#ifdef DDR_INIT_TIME_PROFILING
+    U32 CPU_Cycle;
+    TimeProfileBegin();
+#endif
+
+#if 0//SIMULATION_RX_INPUT_BUF  // skip when bring up
+        //TODO: no shuffle, only need to do once under highest freq.
+        if((p->frequency >= 2133) && (p->rank == RANK_0))
+        //if (p->rank == RANK_0)
+            DramcRXInputBufferOffsetCal(p);
+
+#ifdef DDR_INIT_TIME_PROFILING
+        CPU_Cycle=TimeProfileEnd();
+        mcSHOW_TIME_MSG(("\tRX input cal takes %d us\n", CPU_Cycle));
+        TimeProfileBegin();
+#endif
+#endif
+
+#if GATING_ADJUST_TXDLY_FOR_TRACKING
+    DramcRxdqsGatingPreProcess(p);
+#endif
+
+    if (p->support_rank_num==RANK_DUAL)
+        u1RankMax = RANK_MAX;
+    else
+        u1RankMax = RANK_1;
+
+    //vAutoRefreshSwitch(p, DISABLE); //auto refresh is set as disable in LP4_DramcSetting, so don't need to disable again
+    vAutoRefreshSwitch(p, DISABLE);
+
+#if 1//(SIMUILATION_CBT == 1)
+    for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++)
+    {
+        vSetRank(p, s1RankIdx);
+        #if PINMUX_AUTO_TEST_PER_BIT_CA
+        CheckCAPinMux(p);
+        #endif
+
+        CmdBusTrainingLP45(p, AUTOK_OFF, NORMAL_K);
+
+        #if ENABLE_EYESCAN_GRAPH
+            if (GetEyeScanEnable(p, EYESCAN_TYPE_CBT) == ENABLE)
+            {
+                CmdBusTrainingLP45(p, AUTOK_OFF, EYESCAN_K);
+                print_EYESCAN_LOG_message(p, EYESCAN_TYPE_CBT); //draw CBT eyescan
+            }
+        #endif
+
+        #ifdef DDR_INIT_TIME_PROFILING
+        CPU_Cycle=TimeProfileEnd();
+        mcSHOW_TIME_MSG(("\tRank %d CBT takes %d us\n", s1RankIdx, CPU_Cycle));
+        TimeProfileBegin();
+        #endif
+    }
+    vSetRank(p, RANK_0);
+
+#if __Petrus_TO_BE_PORTING__
+    No_Parking_On_CLRPLL(p);
+#endif
+
+    //@Darren, Fix high freq keep FSP0 for CA term workaround (PPR abnormal)
+    // The patch must to do after cbt training
+    ShuffleDfsToOriginalFSP(p);
+#endif
+
+#if 0//(SIMULATION_WRITE_LEVELING == 1)
+    for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++)
+    {
+        vSetRank(p, s1RankIdx);
+
+        vAutoRefreshSwitch(p, DISABLE); //When doing WriteLeveling, should make sure that auto refresh is disable
+
+#if (!WCK_LEVELING_FM_WORKAROUND)
+        if (u1IsLP4Family(p->dram_type))
+#endif
+        {
+            if (!(u1IsLP4Div4DDR800(p) && (p->rank == RANK_1))) // skip for DDR800 rank1
+            {
+                mcSHOW_DBG_MSG(("\n----->DramcWriteLeveling(PI) begin...\n"));
+
+                DramcWriteLeveling(p, AUTOK_OFF, PI_BASED);
+
+                mcSHOW_DBG_MSG(("DramcWriteLeveling(PI) end<-----\n\n"));
+            }
+        }
+
+        #ifdef DDR_INIT_TIME_PROFILING
+        CPU_Cycle=TimeProfileEnd();
+        mcSHOW_TIME_MSG(("\tRank %d Write leveling takes %d us\n", s1RankIdx, CPU_Cycle));
+        TimeProfileBegin();
+        #endif
+    }
+    vSetRank(p, RANK_0);
+
+    #if ENABLE_WDQS_MODE_2 // <=DDR1600 reduce PI change code time
+    if (!(u1IsLP4Div4DDR800(p)) && (p->frequency <= 800) && (p->support_rank_num == RANK_DUAL)) // skip DDR800semi, for DDR1200/DDR1600 only
+        WriteLevelingPosCal(p, PI_BASED);
+    #elif ENABLE_TX_WDQS // for WDQS mode 1 to avoid dual rank PI code incorrect
+    if (!(u1IsLP4Div4DDR800(p)) && (p->support_rank_num == RANK_DUAL))
+        WriteLevelingPosCal(p, PI_BASED);
+    #endif
+#endif /* (SIMULATION_WRITE_LEVELING == 1) */
+
+    for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++)
+    {
+        vSetRank(p, s1RankIdx);
+
+#if 1//(SIMULATION_WRITE_LEVELING == 1)
+        vAutoRefreshSwitch(p, DISABLE); //When doing WriteLeveling, should make sure that auto refresh is disable
+
+#if (!WCK_LEVELING_FM_WORKAROUND)
+        if (u1IsLP4Family(p->dram_type))
+#endif
+        {
+            if ((!((vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) && (p->rank == RANK_1))) // skip for DDR800 RANK1
+                 && (!(vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE))) // skip for DDR400 
+            {
+                //mcSHOW_DBG_MSG(("\n----->DramcWriteLeveling(PI) begin...\n"));
+
+                DramcWriteLeveling(p, AUTOK_ON, PI_BASED);
+
+               //mcSHOW_DBG_MSG(("DramcWriteLeveling(PI) end<-----\n\n"));
+            }
+
+            #ifdef DDR_INIT_TIME_PROFILING
+            CPU_Cycle=TimeProfileEnd();
+            mcSHOW_TIME_MSG(("\tRank %d Write leveling takes %d us\n", s1RankIdx, CPU_Cycle));
+            TimeProfileBegin();
+            #endif
+        }
+#endif /* (SIMULATION_WRITE_LEVELING == 1) */
+
+        #if LJPLL_FREQ_DEBUG_LOG
+        DDRPhyFreqMeter(p);
+        #endif
+
+        vAutoRefreshSwitch(p, ENABLE); //when doing gating, RX and TX calibration, auto refresh should be enable
+
+        dramc_rx_dqs_gating_cal(p, AUTOK_OFF, 0);
+
+        #ifdef DDR_INIT_TIME_PROFILING
+        CPU_Cycle=TimeProfileEnd();
+        mcSHOW_TIME_MSG(("\tRank %d Gating takes %d us\n", s1RankIdx, CPU_Cycle));
+        TimeProfileBegin();
+        #endif
+
+        #if LJPLL_FREQ_DEBUG_LOG
+            DDRPhyFreqMeter(p);
+        #endif
+
+#if ENABLE_RX_INPUT_BUFF_OFF_K  // skip when bring up
+        if((p->frequency >= 2133) && (p->rank == RANK_0))
+            DramcRXInputBufferOffsetCal(p);
+
+#ifdef DDR_INIT_TIME_PROFILING
+        CPU_Cycle=TimeProfileEnd();
+        mcSHOW_TIME_MSG(("\tRX input cal takes %d us\n", CPU_Cycle));
+        TimeProfileBegin();
+#endif
+#endif
+
+        DramcRxWindowPerbitCal(p, PATTERN_RDDQC, NULL, AUTOK_OFF, NORMAL_K);
+
+        #ifdef DDR_INIT_TIME_PROFILING
+        CPU_Cycle=TimeProfileEnd();
+        mcSHOW_TIME_MSG(("\tRank %d RX RDDQC takes %d us\n", s1RankIdx, CPU_Cycle));
+        TimeProfileBegin();
+        #endif
+
+        #if LJPLL_FREQ_DEBUG_LOG
+            DDRPhyFreqMeter(p);
+        #endif
+
+#if MRW_CHECK_ONLY
+        mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+#endif
+
+        DramcTxWindowPerbitCal(p, TX_DQ_DQS_MOVE_DQ_DQM, FALSE, AUTOK_OFF);
+
+        if (Get_Vref_Calibration_OnOff(p)==VREF_CALI_ON)
+        {
+            DramcTxWindowPerbitCal(p, TX_DQ_DQS_MOVE_DQ_ONLY, TRUE, AUTOK_OFF);
+        }
+
+#if PINMUX_AUTO_TEST_PER_BIT_TX
+        CheckTxPinMux(p);
+#endif
+        DramcTxWindowPerbitCal(p, TX_DQ_DQS_MOVE_DQ_ONLY, FALSE, AUTOK_OFF);
+
+#if TX_K_DQM_WITH_WDBI
+        if ((p->DBI_W_onoff[p->dram_fsp]==DBI_ON))
+        {
+            // K DQM with DBI_ON, and check DQM window spec.
+            //mcSHOW_DBG_MSG(("[TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.\n\n"));
+            vSwitchWriteDBISettings(p, DBI_ON);
+            DramcTxWindowPerbitCal((DRAMC_CTX_T *) p, TX_DQ_DQS_MOVE_DQM_ONLY, FALSE, AUTOK_OFF);
+            vSwitchWriteDBISettings(p, DBI_OFF);
+        }
+#endif
+
+    #if ENABLE_EYESCAN_GRAPH
+        if (GetEyeScanEnable(p, EYESCAN_TYPE_TX) == ENABLE)
+        {
+            Dramc_K_TX_EyeScan_Log(p);
+            print_EYESCAN_LOG_message(p, EYESCAN_TYPE_TX); //draw TX eyescan
+        }
+    #endif
+
+        #ifdef DDR_INIT_TIME_PROFILING
+        CPU_Cycle=TimeProfileEnd();
+        mcSHOW_TIME_MSG(("\tRank %d TX calibration takes %d us\n", s1RankIdx, CPU_Cycle));
+        TimeProfileBegin();
+        #endif
+
+        #if LJPLL_FREQ_DEBUG_LOG
+            DDRPhyFreqMeter(p);
+        #endif
+
+        DramcRxdatlatCal(p);
+
+        #ifdef DDR_INIT_TIME_PROFILING
+        CPU_Cycle=TimeProfileEnd();
+        mcSHOW_TIME_MSG(("\tRank %d Datlat takes %d us\n", s1RankIdx, CPU_Cycle));
+        TimeProfileBegin();
+        #endif
+
+        #if LJPLL_FREQ_DEBUG_LOG
+            DDRPhyFreqMeter(p);
+        #endif
+
+#if PINMUX_AUTO_TEST_PER_BIT_RX
+        CheckRxPinMux(p);
+#endif
+
+        DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, NULL /*Set Vref = 0 to test*/, AUTOK_ON, NORMAL_K);
+
+        #ifdef DDR_INIT_TIME_PROFILING
+        CPU_Cycle=TimeProfileEnd();
+        mcSHOW_TIME_MSG(("\tRank %d RX calibration takes %d us\n", s1RankIdx, CPU_Cycle));
+        TimeProfileBegin();
+        #endif
+       // DramcRxdqsGatingCal(p);
+
+#if ENABLE_EYESCAN_GRAPH
+        if (GetEyeScanEnable(p, EYESCAN_TYPE_RX) == ENABLE)
+        {
+            DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, NULL /*Set Vref = 0 to test*/, AUTOK_ON, EYESCAN_K);
+            print_EYESCAN_LOG_message(p, EYESCAN_TYPE_RX); //draw RX eyescan
+        }
+#endif
+
+#if (SIMULATION_RX_DVS == 1)
+    if (p->frequency >=2133)
+        DramcRxDVSWindowCal(p);
+#endif
+
+#if TX_OE_CALIBATION && !ENABLE_WDQS_MODE_2
+        if(p->frequency >= 1600)
+        {
+            DramcTxOECalibration(p);
+        }
+#endif
+
+        vAutoRefreshSwitch(p, DISABLE);
+
+        #if ENABLE_TX_TRACKING
+        DramcDQSOSCSetMR18MR19(p);
+        DramcDQSOSCMR23(p);
+        #endif
+
+    }
+
+#if __Petrus_TO_BE_PORTING__
+    #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+    if(p->femmc_Ready==0)
+    #endif
+    {
+        if(p->frequency >= RX_VREF_DUAL_RANK_K_FREQ)  // for 3733/4266
+        {
+            U8 u1ByteIdx, u1HighFreqRXVref[2];
+            for(u1ByteIdx =0 ; u1ByteIdx<DQS_BYTE_NUMBER; u1ByteIdx++)
+            {
+                u1HighFreqRXVref[u1ByteIdx] = (gFinalRXVrefDQ[p->channel][RANK_0][u1ByteIdx] + gFinalRXVrefDQ[p->channel][RANK_1][u1ByteIdx]) >> 1;
+                mcSHOW_DBG_MSG(("RX Vref Byte%d (u1HighFreqRXVref) = %d = (%d+ %d)>>1\n", u1ByteIdx, u1HighFreqRXVref[u1ByteIdx], gFinalRXVrefDQ[p->channel][RANK_0][u1ByteIdx], gFinalRXVrefDQ[p->channel][RANK_1][u1ByteIdx]));
+            }
+
+            for(s1RankIdx=RANK_0; s1RankIdx < u1RankMax; s1RankIdx++)
+            {
+                vSetRank(p, s1RankIdx);
+                DramcRxWindowPerbitCal((DRAMC_CTX_T *) p, 1, u1HighFreqRXVref);
+            }
+        }
+    }
+#endif
+
+    vSetRank(p, RANK_0); // Set p's rank back to 0 (Avoids unexpected auto-rank offset calculation in u4RegBaseAddrTraslate())
+
+    #if ENABLE_TX_TRACKING
+    DramcDQSOSCShuSettings(p);
+    #endif
+
+#if (SIMULATION_GATING && GATING_ADJUST_TXDLY_FOR_TRACKING)
+    DramcRxdqsGatingPostProcess(p);
+#endif
+
+#if TDQSCK_PRECALCULATION_FOR_DVFS
+    DramcDQSPrecalculation_preset(p);
+#endif
+
+#if SIMULATION_RX_DVS
+    if (p->frequency >=2133)
+        DramcDramcRxDVSCalPostProcess(p);
+#endif
+
+    DramcDualRankRxdatlatCal(p);
+
+#if RDSEL_TRACKING_EN
+    if (p->frequency >= RDSEL_TRACKING_TH)
+        RDSELRunTimeTracking_preset(p);
+#endif
+
+#if XRTWTW_NEW_CROSS_RK_MODE
+    if(p->support_rank_num == RANK_DUAL)
+    {
+        XRTWTW_SHU_Setting(p);
+    }
+#endif
+
+#if __Petrus_TO_BE_PORTING__
+#if LJPLL_FREQ_DEBUG_LOG
+    DDRPhyFreqMeter(p);
+#endif
+#endif
+
+    #ifdef DDR_INIT_TIME_PROFILING
+    CPU_Cycle=TimeProfileEnd();
+    mcSHOW_TIME_MSG(("\tMisc takes %d us\n\n", s1RankIdx, CPU_Cycle));
+    #endif
+}
+
+static void vDramCalibrationSingleChannel(DRAMC_CTX_T *p)
+{
+    vCalibration_Flow_LP4(p);
+}
+
+void vDramCalibrationAllChannel(DRAMC_CTX_T *p)
+{
+    U8 channel_idx, rank_idx;
+
+#ifdef FOR_HQA_REPORT_USED
+    print_HQA_message_before_CalibrationAllChannel(p);
+#endif
+
+#ifdef DDR_INIT_TIME_PROFILING
+    PROFILING_TIME_T ptime;
+
+    TimeProfileGetTick(&ptime);
+#endif
+
+    CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ALL_CHANNEL);
+    for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
+    {
+        vSetPHY2ChannelMapping(p, channel_idx);// when switching channel, must update PHY to Channel Mapping
+        CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ONE_CHANNEL);
+        vDramCalibrationSingleChannel(p);
+    }
+
+    vSetPHY2ChannelMapping(p, CHANNEL_A);
+
+#if PRINT_CALIBRATION_SUMMARY
+    vPrintCalibrationResult(p);
+#endif
+
+#ifdef FOR_HQA_TEST_USED
+    #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+    if (p->femmc_Ready == 1)
+    {
+        mcSHOW_DBG_MSG(("\nCalibration fast K is enable, cannot show HQA measurement information\n"));
+    }
+    else
+    #endif
+    print_HQA_measure_message(p);
+#endif
+
+#if defined(DEVIATION)
+    if(p->frequency == u2DFSGetHighestFreq(p))
+    {
+        SetDeviationVref(p);
+        #if  !__ETT__
+        vSetDeviationVariable();
+        #endif
+    }
+#endif
+
+    /* Enable/Disable calibrated rank's DBI function accordingly */
+#if ENABLE_READ_DBI
+    //Read DBI ON
+    vSetRank(p, RANK_0);
+    vSetPHY2ChannelMapping(p, CHANNEL_A);
+
+    DramcReadDBIOnOff(p, p->DBI_R_onoff[p->dram_fsp]);
+#endif
+
+#if ENABLE_WRITE_DBI
+    // Just settle the DBI parameters which would be stored into shuffle space.
+    if (p->DBI_W_onoff[p->dram_fsp])
+    {
+        for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
+        {
+            vSetPHY2ChannelMapping(p, channel_idx);
+
+            for (rank_idx = RANK_0; rank_idx < RANK_MAX; rank_idx++)
+            {
+                vSetRank(p, rank_idx);
+                DramcWriteShiftMCKForWriteDBI(p, -1); //Tx DQ/DQM -1 MCK for write DBI ON
+            }
+            vSetRank(p, RANK_0);
+        }
+        vSetPHY2ChannelMapping(p, CHANNEL_A);
+
+        // Improve Write DBI Power
+        ApplyWriteDBIPowerImprove(p, ENABLE);
+
+        #if ENABLE_WRITE_DBI_Protect
+        ApplyWriteDBIProtect(p, ENABLE);
+        #endif
+    }
+
+    DramcWriteDBIOnOff(p, p->DBI_W_onoff[p->dram_fsp]);
+#endif
+
+#if TX_PICG_NEW_MODE
+    TXPICGSetting(p);
+#endif
+
+#if XRTRTR_NEW_CROSS_RK_MODE
+    if (p->support_rank_num == RANK_DUAL)
+    {
+        XRTRTR_SHU_Setting(p);
+    }
+#endif
+
+#if (ENABLE_TX_TRACKING || TDQSCK_PRECALCULATION_FOR_DVFS)
+    FreqJumpRatioCalculation(p);
+#endif
+
+#ifdef TEMP_SENSOR_ENABLE
+    DramcHMR4_Presetting(p);
+#endif
+
+#if DRAMC_MODIFIED_REFRESH_MODE
+    DramcModifiedRefreshMode(p);
+#endif
+
+#if DRAMC_CKE_DEBOUNCE
+    DramcCKEDebounce(p);
+#endif
+
+#if ENABLE_TX_TRACKING
+    U8 backup_channel = p->channel;
+    U8 channelIdx;
+
+    for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++)
+    {
+        vSetPHY2ChannelMapping(p, channelIdx);
+        DramcHwDQSOSC(p);
+    }
+
+    vSetPHY2ChannelMapping(p, backup_channel);
+    //mcSHOW_DBG_MSG(("TX_TRACKING: ON\n"));
+//#else
+    //mcSHOW_DBG_MSG(("TX_TRACKING: OFF\n"));
+#endif
+
+#if ENABLE_DFS_RUNTIME_MRW
+    DFSRuntimeMRW_preset_AfterK(p, vGet_Current_SRAMIdx(p));
+#endif
+
+#ifdef DDR_INIT_TIME_PROFILING
+    mcSHOW_TIME_MSG(("  (4) vDramCalibrationAllChannel() take %d ms\n\r", TimeProfileDiffUS(&ptime) / 1000));
+#endif
+}
+
+U8 gGet_MDL_Used_Flag = 0;
+void Set_MDL_Used_Flag(U8 value)
+{
+    gGet_MDL_Used_Flag = value;
+}
+
+U8 Get_MDL_Used_Flag(void)
+{
+    return gGet_MDL_Used_Flag;
+}
+
+DRAMC_CTX_T *psCurrDramCtx;
+U8 gfirst_init_flag = 0;
+//extern int MustStop;
+int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_extern, DRAM_INFO_BY_MRR_T *DramInfo, U8 get_mdl_used)
+{
+    #if !SW_CHANGE_FOR_SIMULATION
+
+    //int mem_start, len, s4value;
+    DRAMC_CTX_T * p;
+    //U8 ucstatus = 0;
+    //U32 u4value;
+    //U8 chIdx;
+    U8 final_shu;
+
+#ifdef DDR_INIT_TIME_PROFILING
+    U32 CPU_Cycle;
+    TimeProfileBegin();
+#endif
+
+    psCurrDramCtx = &DramCtx_LPDDR4;
+
+#if defined(DDR_INIT_TIME_PROFILING) || (__ETT__ && SUPPORT_SAVE_TIME_FOR_CALIBRATION)
+    if (gtime_profiling_flag == 0)
+    {
+        memcpy(&gTimeProfilingDramCtx, psCurrDramCtx, sizeof(DRAMC_CTX_T));
+        gtime_profiling_flag = 1;
+    }
+
+    p = &gTimeProfilingDramCtx;
+    gfirst_init_flag = 0;
+
+    //DramcConfInfraReset(p);  //No need when DDR_INIT_TIME_PROFILING_TEST_CNT=1
+#else
+    p = psCurrDramCtx;
+#endif
+
+    p->new_cbt_mode = 1;
+
+    Set_MDL_Used_Flag(get_mdl_used);
+
+    p->dram_type = dram_type;
+
+    /* Convert DRAM_CBT_MODE_EXTERN_T to DRAM_CBT_MODE_T */
+    switch ((int)dram_cbt_mode_extern)
+    {
+        case CBT_R0_R1_NORMAL:
+            p->dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE;
+            p->dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE;
+            break;
+        case CBT_R0_R1_BYTE:
+            p->dram_cbt_mode[RANK_0] = CBT_BYTE_MODE1;
+            p->dram_cbt_mode[RANK_1] = CBT_BYTE_MODE1;
+            break;
+        case CBT_R0_NORMAL_R1_BYTE:
+            p->dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE;
+            p->dram_cbt_mode[RANK_1] = CBT_BYTE_MODE1;
+            break;
+        case CBT_R0_BYTE_R1_NORMAL:
+            p->dram_cbt_mode[RANK_0] = CBT_BYTE_MODE1;
+            p->dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE;
+            break;
+        default:
+            mcSHOW_ERR_MSG(("Error!"));
+            break;
+    }
+    mcSHOW_DBG_MSG2(("dram_cbt_mode_extern: %d\n"
+                      "dram_cbt_mode [RK0]: %d, [RK1]: %d\n",
+                      (int)dram_cbt_mode_extern, p->dram_cbt_mode[RANK_0], p->dram_cbt_mode[RANK_1]));
+
+#if ENABLE_APB_MASK_WRITE
+    U32 u4GPTTickCnt;
+    TimeProfileBegin();
+
+    EnableDramcAPBMaskWrite(p);
+    DramcRegAPBWriteMask(p);
+
+    u4GPTTickCnt = TimeProfileEnd();
+    mcSHOW_TIME_MSG(("[DramcRegAPBWriteMask] take %d ms\n", u4GPTTickCnt / 1000));
+
+    TestAPBMaskWriteFunc(p);
+
+    while (1);
+#endif
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);   //LP4 broadcast on
+
+    if (gfirst_init_flag == 0)
+    {
+        MPLLInit();
+        Global_Option_Init(p);
+        gfirst_init_flag = 1;
+    }
+
+#ifdef FIRST_BRING_UP
+    if (p->support_channel_num != CHANNEL_SINGLE)
+        Test_Broadcast_Feature(p);
+#endif
+
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+    {
+        U32 backup_broadcast;
+        backup_broadcast = GetDramcBroadcast();
+        DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+        mdl_setting(p);
+        UpdateGlobal10GBEnVariables(p); // @Darren, for 10GB
+        TA2_Test_Run_Time_HW_Set_Column_Num(p);
+        DramcBroadcastOnOff(backup_broadcast);
+    }
+#endif
+
+    mcSHOW_DBG_MSG(("\n\n[Bian_co] %s\n dram_type %d, R0 cbt_mode %d, R1 cbt_mode %d VENDOR=%d\n\n", _VERSION_, p->dram_type, p->dram_cbt_mode[RANK_0], p->dram_cbt_mode[RANK_1], p->vendor_id));
+
+#if __Petrus_TO_BE_PORTING__
+    vDramcInit_PreSettings(p);
+#endif
+
+    // DramC & PHY init for all channels
+    //===  First frequency ======
+
+#if defined(DUMP_INIT_RG_LOG_TO_DE)
+    vSetDFSFreqSelByTable(p, &gFreqTbl[1]); //0:3200 1:4266, 2:800, 3:1866, 4:1200, 5:2400, 6:1600
+#else
+    vSetDFSFreqSelByTable(p, &gFreqTbl[DRAM_DFS_SRAM_MAX-1]);
+    //vSetDFSFreqSelByTable(p, &gFreqTbl[1]);
+#endif
+
+#if (DUAL_FREQ_K==0) || (__FLASH_TOOL_DA__)
+    gAndroid_DVFS_en = FALSE; //skip ETT DVFS stress
+#endif
+
+#if RUNTIME_SHMOO_RELEATED_FUNCTION
+    ett_fix_freq = 1; /* only 1600 & 4266 */
+#endif
+
+    if (ett_fix_freq != 0xff)
+        gAndroid_DVFS_en = FALSE;
+
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+    DramcSave_Time_For_Cal_Init(p);
+#endif
+#ifndef LOOPBACK_TEST
+    if (p->dram_type == TYPE_LPDDR4X) // LP4/LP4P need confirm
+    {
+        // LP4 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266
+        // LP5 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266
+        DramcImpedanceCal(p, 1, IMP_LOW_FREQ);
+        DramcImpedanceCal(p, 1, IMP_HIGH_FREQ);
+        #if ENABLE_SAMSUNG_NT_ODT
+        DramcImpedanceCal(p, 1, IMP_NT_ODTN); // for Samsung NT ODTN
+        #endif
+    }
+    else
+    {
+        mcSHOW_ERR_MSG(("[DramcImpedanceCal] Warnning: Need confirm DRAM type for SW IMP Calibration !!!\n"));
+        #if __ETT__
+        while (1);
+        #endif
+    }
+#endif
+
+#ifdef DDR_INIT_TIME_PROFILING
+    CPU_Cycle = TimeProfileEnd();
+    mcSHOW_TIME_MSG(("(0)Pre_Init + SwImdepance takes %d ms\n\r", CPU_Cycle / 1000));
+#endif
+
+#ifdef DUMP_INIT_RG_LOG_TO_DE
+    gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 1;
+    mcSHOW_DUMP_INIT_RG_MSG(("\n\n//=== DDR\033[1;32m%d\033[m\n",p->frequency<<1));
+#endif
+
+    //Clk free run
+    //EnableDramcPhyDCM(p, 0);
+
+    DFSInitForCalibration(p);
+
+#ifdef TEST_MODE_MRS
+    if (global_which_test == 0)
+        TestModeTestMenu();
+#endif
+
+
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+    if (p->femmc_Ready==1)
+    {
+        p->support_rank_num = p->pSavetimeData->support_rank_num;
+    }
+    else
+#endif
+    {
+#if ENABLE_RANK_NUMBER_AUTO_DETECTION
+        if (Get_MDL_Used_Flag()==GET_MDL_USED)
+        {
+            DramRankNumberDetection(p);
+            DFSInitForCalibration(p);  // Restore setting after rank dection (especially DQ= DQS+16)
+        }
+#endif
+
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+        p->pSavetimeData->support_rank_num = p->support_rank_num;
+#endif
+    }
+
+    #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+    U32 backup_broadcast;
+    backup_broadcast = GetDramcBroadcast();
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+    emi_init2();
+    DramcBroadcastOnOff(backup_broadcast);
+    #endif
+
+    if (Get_MDL_Used_Flag()==GET_MDL_USED)
+    {
+        // only K CHA to save time
+        vSetPHY2ChannelMapping(p, CHANNEL_A);
+        vCalibration_Flow_For_MDL(p); // currently for LP4
+        GetDramInforAfterCalByMRR(p, DramInfo);
+        return 0;
+    }
+    else //NORMAL_USED
+    {
+        vDramCalibrationAllChannel(p);
+        GetDramInforAfterCalByMRR(p, DramInfo);
+        vDramcACTimingOptimize(p);
+    }
+
+    #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+    DramcSave_Time_For_Cal_End(p);
+    #endif
+
+
+#if (DUAL_FREQ_K) && (!__FLASH_TOOL_DA__)
+    DramcSaveToShuffleSRAM(p, DRAM_DFS_REG_SHU0, vGet_Current_SRAMIdx(p));
+
+    #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+    DramcSave_Time_For_Cal_End(p);
+    #endif
+    LoadShuffleSRAMtoDramc(p, vGet_Current_SRAMIdx(p), DRAM_DFS_REG_SHU1); //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT)
+
+    S8 u1ShuIdx;
+    S8 s1ShuStart, s1ShuEnd;
+
+    if (ett_fix_freq != 0xff) {
+        s1ShuStart = ett_fix_freq;
+        s1ShuEnd = ett_fix_freq;
+        gFreqTbl[ett_fix_freq].vref_calibartion_enable = VREF_CALI_ON;
+    } else {
+        s1ShuStart = DRAM_DFS_SRAM_MAX - 2;
+        s1ShuEnd = SRAM_SHU0;
+    }
+
+    for (u1ShuIdx = s1ShuStart; u1ShuIdx >= s1ShuEnd; u1ShuIdx--)
+    {
+        vSetDFSFreqSelByTable(p, &gFreqTbl[u1ShuIdx]);
+        #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+        DramcSave_Time_For_Cal_Init(p);
+        #endif
+        DFSInitForCalibration(p);
+        vDramCalibrationAllChannel(p);
+        vDramcACTimingOptimize(p);
+
+        #if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION
+        if (p->frequency == u2DFSGetHighestFreq(p))
+        {
+            DramcRunTimeShmooRG_BackupRestore(p);
+            RunTime_Shmoo_update_parameters(p);
+        }
+        #endif
+
+        DramcSaveToShuffleSRAM(p, DRAM_DFS_REG_SHU0, gFreqTbl[u1ShuIdx].SRAMIdx);
+
+        #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+        DramcSave_Time_For_Cal_End(p);
+        #endif
+    }
+#endif //(DUAL_FREQ_K) && (!__FLASH_TOOL_DA__)
+
+
+#ifdef DDR_INIT_TIME_PROFILING
+    TimeProfileBegin();
+#endif
+
+    vAfterCalibration(p);
+
+#ifdef ENABLE_POST_PACKAGE_REPAIR
+    PostPackageRepair();
+#endif
+
+#if __Petrus_TO_BE_PORTING__
+
+#if 0//TX_OE_CALIBATION, for DMA test
+    U8 u1ChannelIdx, u1RankIdx;
+    for (u1ChannelIdx = 0; u1ChannelIdx < (p->support_channel_num); u1ChannelIdx++)
+        for (u1RankIdx = 0; u1RankIdx < (p->support_rank_num); u1RankIdx++)
+        {
+            vSetPHY2ChannelMapping(p, u1ChannelIdx);
+            vSetRank(p, u1RankIdx);
+            DramcTxOECalibration(p);
+        }
+
+    vSetPHY2ChannelMapping(p, CHANNEL_A);
+    vSetRank(p, RANK_0);
+
+    U32 u4err_value;
+    DramcDmaEngine((DRAMC_CTX_T *)p, 0x50000000, 0x60000000, 0xff00, 8, DMA_PREPARE_DATA_ONLY, p->support_channel_num);
+    u4err_value = DramcDmaEngine((DRAMC_CTX_T *)p, 0x50000000, 0x60000000, 0xff00, 8, DMA_CHECK_DATA_ACCESS_AND_COMPARE, p->support_channel_num);
+    mcSHOW_DBG_MSG(("DramC_TX_OE_Calibration  0x%X\n", u4err_value));
+#endif
+
+#if !LCPLL_IC_SCAN
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+    print_DBG_info(p);
+    Dump_EMIRegisters(p);
+#endif
+#endif
+
+#if 0
+    DramcRegDump(p, SRAM_SHU0);
+#endif
+
+// ETT_NO_DRAM #endif
+
+#if ETT_NO_DRAM
+    //NoDramDramcRegDump(p);
+    NoDramRegFill();
+#endif
+#endif //#if __Petrus_TO_BE_PORTING__
+
+    #if DRAMC_MODEREG_CHECK
+    DramcModeReg_Check(p);
+    #endif
+
+    #if PIN_CHECK_TOOL
+    vPrintPinInfoResult(p);
+    vGetErrorTypeResult(p);
+    #endif
+
+    #if CPU_RW_TEST_AFTER_K
+    mcSHOW_DBG_MSG2(("\n[MEM_TEST] 02: After DFS, before run time config\n"));
+    vDramCPUReadWriteTestAfterCalibration(p);
+    #endif
+
+    #if TA2_RW_TEST_AFTER_K
+    mcSHOW_DBG_MSG2(("\n[TA2_TEST]\n"));
+    TA2_Test_Run_Time_HW(p);
+    #endif
+
+#if __ETT__
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+    if (!(p->femmc_Ready == 0))
+#elif defined(DDR_INIT_TIME_PROFILING)
+if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) //last time of loop
+#endif
+#endif
+    {
+        EnableDFSHwModeClk(p);
+        mcSHOW_DBG_MSG2(("DFS_SHUFFLE_HW_MODE: ON\n"));
+        if (gAndroid_DVFS_en == TRUE) // shuffle to DDR3733 boot
+        {
+#if defined(SLT)
+#ifdef SLT_2400_EXIT_PRELOADER
+            final_shu = SRAM_SHU0; //DDR2400
+#else
+            final_shu = SRAM_SHU0;  //DDR3200
+#endif
+#else
+            final_shu = SRAM_SHU0;  //DDR4266
+#endif
+
+            vSetDFSFreqSelByTable(p, get_FreqTbl_by_SRAMIndex(p, final_shu));
+#if REPLACE_DFS_RG_MODE
+            DramcDFSDirectJump_SPMMode(p, SRAM_SHU1);
+            DramcDFSDirectJump_SPMMode(p, final_shu);
+#else
+            DramcDFSDirectJump_SRAMShuRGMode(p, SRAM_SHU1);
+            DramcDFSDirectJump_SRAMShuRGMode(p, final_shu);
+#endif
+        }
+
+
+#if __Petrus_TO_BE_PORTING__
+        #if (DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM && defined(DUMMY_READ_FOR_TRACKING))
+        DramcDummyReadForSPMSideBand(p); // SPM dummy read 1us <-> 4us for DVT only (it must call after TransferPLLToSPMControl)
+        #endif
+
+        EnableDramcTrackingBySPMControl(p);
+
+        mcSHOW_DBG_MSG2(("\n\nSettings after calibration\n\n"));
+        //mcDUMP_REG_MSG(("\n\nSettings after calibration\n\n"));
+#endif
+
+
+        DramcRunTimeConfig(p);
+
+        #if DUMP_ALLSUH_RG
+        DumpAllChAllShuRG(p);
+        #endif
+    }
+
+    #if CPU_RW_TEST_AFTER_K
+    mcSHOW_DBG_MSG2(("\n[MEM_TEST] 03: After run time config\n"));
+    vDramCPUReadWriteTestAfterCalibration(p);
+    #endif
+
+    #if TA2_RW_TEST_AFTER_K
+    mcSHOW_DBG_MSG2(("\n[TA2_TEST]\n"));
+    TA2_Test_Run_Time_HW(p);
+    #endif
+
+
+#if (__ETT__ && CPU_RW_TEST_AFTER_K)
+    /* 0x46000000 is LK base addr */
+    //while(1)
+    {
+        //if ((s4value = dramc_complex_mem_test (0x46000000, 0x2000)) == 0)
+        if ((s4value = dramc_complex_mem_test (0x40024000, 0x20000)) == 0)
+        {
+            mcSHOW_DBG_MSG3(("1st complex R/W mem test pass\n"));
+        }
+        else
+        {
+            mcSHOW_DBG_MSG3(("1st complex R/W mem test fail :-%d\n", -s4value));
+#if defined(SLT)
+            mcSHOW_ERR_MSG(("[EMI] EMI_FATAL_ERR_FLAG = 0x00000001, line: %d\n",__LINE__));
+            while (1);
+#endif
+        }
+    }
+#endif
+
+#if MRW_CHECK_ONLY
+    vPrintFinalModeRegisterSetting(p);
+#endif
+
+#ifdef DDR_INIT_TIME_PROFILING
+    CPU_Cycle = TimeProfileEnd();
+    mcSHOW_TIME_MSG(("  (5) After calibration takes %d ms\n\r", CPU_Cycle / 1000));
+#endif  // end of DDR_INIT_TIME_PROFILING
+
+#endif//SW_CHANGE_FOR_SIMULATION
+
+#if defined(FOR_HQA_REPORT_USED)
+    print_HQA_SLT_BIN_message(p);
+#endif
+
+#if DVT_TEST_RX_FIFO_MISMATCH_IRQ_CLEAN
+    DVTRxFifoMismatchIrqClean(p);
+#endif
+
+    //final_shu = SRAM_SHU7;
+    //vSetDFSFreqSelByTable(p, get_FreqTbl_by_SRAMIndex(p, final_shu));
+    //DramcDFSDirectJump(p, SRAM_SHU1);//Switch to CLRPLL
+    //DramcDFSDirectJump(p, final_shu);//Switch to CLRPLL
+    //if(MustStop)
+    //    while(1);
+    //ETT_DRM(p);
+
+    return 0;
+}
+///TODO: wait for porting ---
+
+
+#if FOR_DV_SIMULATION_USED
+
+///TODO: wait for porting +++
+void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args_t *psra)
+{
+    U8 ii;
+
+    ///TODO: wait for porting +++
+#if GATING_ADJUST_TXDLY_FOR_TRACKING
+    DramcRxdqsGatingPreProcess(DramConfig);
+#endif
+    ///TODO: wait for porting ---
+
+    vAutoRefreshSwitch(DramConfig, DISABLE);
+
+#if (SIMUILATION_CBT == 1)
+    for (ii = RANK_0; ii < DramConfig->support_rank_num; ii++)
+    {
+        vSetRank(DramConfig, ii);
+
+        if (!psra || psra->cbt) {
+            mcSHOW_DBG_MSG6(("\n----->DramcCBT begin...\n"));
+            timestamp_show();
+        #if CBT_O1_PINMUX_WORKAROUND
+            CmdBusTrainingLP45(DramConfig, AUTOK_OFF); //Cannot use aito-k in A60868
+        #else
+            if (psra)
+                CmdBusTrainingLP45(DramConfig, psra->cbt_autok, NORMAL_K);
+            else
+                CmdBusTrainingLP45(DramConfig, AUTOK_OFF, NORMAL_K);
+        #endif
+            timestamp_show();
+            mcSHOW_DBG_MSG6(("DramcCBT end<-----\n\n"));
+        }
+    #if ENABLE_EYESCAN_GRAPH
+        if (GetEyeScanEnable(DramConfig, EYESCAN_TYPE_CBT) == ENABLE)
+        {
+            mcSHOW_DBG_MSG6(("CBT EYESCAN start<-----\n\n"));
+            CmdBusTrainingLP45(DramConfig, AUTOK_OFF, EYESCAN_K);
+            print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_CBT); //draw CBT eyescan
+            mcSHOW_DBG_MSG6(("CBT EYESCAN end<-----\n\n"));
+        }
+       #endif
+    }
+
+    vSetRank(DramConfig, RANK_0);
+
+    ShuffleDfsToOriginalFSP(DramConfig);
+
+    ///TODO: wait for porting +++
+#if __A60868_TO_BE_PORTING__
+    No_Parking_On_CLRPLL(DramConfig);
+#endif // __A60868_TO_BE_PORTING__
+    ///TODO: wait for porting ---
+#endif /* (SIMUILATION_CBT == 1) */
+
+    for (ii = RANK_0; ii < DramConfig->support_rank_num; ii++)
+    {
+        vSetRank(DramConfig, ii);
+
+        vAutoRefreshSwitch(DramConfig, DISABLE); //When doing WriteLeveling, should make sure that auto refresh is disable
+
+#if (SIMULATION_WRITE_LEVELING == 1)
+#if (!WCK_LEVELING_FM_WORKAROUND)
+    if (u1IsLP4Family(DramConfig->dram_type))
+#endif
+    {
+        if (!(u1IsPhaseMode(DramConfig) && (DramConfig->rank == RANK_1))) // skip for DDR800 and DDR400 rank1
+        {
+            if (!psra || psra->wl) {
+                mcSHOW_DBG_MSG6(("\n----->DramcWriteLeveling(PI) begin...\n"));
+                timestamp_show();
+                if (psra)
+                {
+                    DramcWriteLeveling(DramConfig, psra->wl_autok, PI_BASED);
+                }
+                else
+                    DramcWriteLeveling(DramConfig, AUTOK_OFF, PI_BASED);
+
+                timestamp_show();
+                mcSHOW_DBG_MSG6(("DramcWriteLeveling(PI) end<-----\n\n"));
+            }
+        }
+    }
+#endif /* (SIMULATION_WRITE_LEVELING == 1) */
+
+        vAutoRefreshSwitch(DramConfig, ENABLE);
+
+#if (SIMULATION_GATING == 1)
+        if (!psra || psra->gating) {
+            mcSHOW_DBG_MSG6(("\n----->DramcGating begin...\n"));
+            timestamp_show();
+            if (psra)
+                dramc_rx_dqs_gating_cal(DramConfig, psra->gating_autok, 0);
+            else
+                dramc_rx_dqs_gating_cal(DramConfig, AUTOK_OFF, 0);
+            timestamp_show();
+            mcSHOW_DBG_MSG6(("DramcGating end < -----\n\n"));
+        }
+#endif
+
+#if (SIMULATION_RX_RDDQC == 1)
+        if (!psra || psra->rddqc) {
+            mcSHOW_DBG_MSG6(("\n----->DramcRxWindowPerbitCal RDDQC begin...\n"));
+            timestamp_show();
+
+            #if 0 // Used when testing LP5 RK1 WCK2CK in high efficiency mode and differential mode.
+            p->rank = 1;
+            // For test HEFF = 1 / WCKDUAL = 0
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL), 0, SHU_WCKCTRL_WCKDUAL);
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0),
+                    P_Fld(1, SHU_COMMON0_LP5WCKON) |
+                    P_Fld(1, SHU_COMMON0_LP5HEFF_MODE));
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), 0, CKECTRL_CKE2RANK_OPT8);
+            #endif
+            DramcRxWindowPerbitCal(DramConfig, PATTERN_RDDQC, NULL, AUTOK_OFF, NORMAL_K);
+            timestamp_show();
+            mcSHOW_DBG_MSG6(("DramcRxWindowPerbitCal end<-----\n\n"));
+        }
+
+#endif // (SIMULATION_RX_RDDQC == 1)
+
+#if (__LP5_COMBO__ == TRUE)
+#if (SIMULATION_DUTY_CYC_MONITOR == 1)
+        if (is_lp5_family(DramConfig) && DramConfig->frequency >= GetFreqBySel(DramConfig,LP5_DDR4266))
+        {
+            if (!psra) {
+                mcSHOW_DBG_MSG6(("\n----->DramcDutyCycleMonitor begin...\n"));
+                timestamp_show();
+                DramcDutyCycleMonitor(DramConfig);
+                timestamp_show();
+                mcSHOW_DBG_MSG6(("DramcDutyCycleMonitor end<-----\n\n"));
+
+                mcSHOW_DBG_MSG6(("\n----->DramcWriteLeveling(DLY) begin...\n"));
+                timestamp_show();
+                DramcWriteLeveling(DramConfig, psra->wl_autok, DLY_BASED);
+                timestamp_show();
+                mcSHOW_DBG_MSG6(("DramcWriteLeveling(DLY)end<-----\n\n"));
+            }
+        }
+#endif /* (SIMULATION_DUTY_CYC_MONITOR == 1) */
+#endif // (__LP5_COMBO__ == TRUE)
+
+#if (SIMULATION_TX_PERBIT == 1)
+        if (!psra || psra->tx_perbit) {
+            mcSHOW_DBG_MSG6(("\n----->DramcTxWindowPerbitCal begin...\n"));
+            timestamp_show();
+            if (psra)
+                DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_DQM,
+                        FALSE, psra->tx_auto_cal);
+            else
+                DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_DQM,
+                        FALSE, AUTOK_OFF);
+            if (Get_Vref_Calibration_OnOff(DramConfig) == VREF_CALI_ON) {
+                if (psra)
+                    DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY,
+                            TRUE, psra->tx_auto_cal);
+                else
+                    DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY,
+                            TRUE, AUTOK_OFF);
+            }
+            if (psra)
+                DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY,
+                        FALSE, psra->tx_auto_cal);
+            else
+                DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY,
+                        FALSE, AUTOK_OFF);
+            timestamp_show();
+            mcSHOW_DBG_MSG6(("DramcTxWindowPerbitCal end<-----\n\n"));
+
+        #if ENABLE_EYESCAN_GRAPH
+                if (GetEyeScanEnable(DramConfig, EYESCAN_TYPE_TX) == ENABLE)
+                {
+                    mcSHOW_DBG_MSG6(("\n----->DramcTxEYESCAN begin...\n"));
+                    Dramc_K_TX_EyeScan_Log(DramConfig);
+                    print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_TX); //draw TX eyescan
+                    mcSHOW_DBG_MSG6(("\n----->DramcTxEYESCAN end...\n"));
+                }
+               #endif
+        }
+#endif // (SIMULATION_TX_PERBIT == 1)
+
+#if (SIMULATION_DATLAT == 1)
+        if (1) { // No parameter in correspondence with by now
+            mcSHOW_DBG_MSG6(("\n----->DramcRxdatlatCal begin...\n"));
+            timestamp_show();
+
+            DramcRxdatlatCal(DramConfig);
+
+            timestamp_show();
+            mcSHOW_DBG_MSG6(("DramcRxdatlatCal end<-----\n\n"));
+        }
+#endif // (SIMULATION_DATLAT == 1)
+
+#if (SIMULATION_RX_PERBIT == 1)
+        if (!psra || psra->rx_perbit) {
+            mcSHOW_DBG_MSG6(("\n----->DramcRxWindowPerbitCal begin...\n"));
+            timestamp_show();
+            if (psra)
+                DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE,
+                        NULL /*Set Vref = 0 to test*/, psra->rx_auto_cal, NORMAL_K);
+            else
+                DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE,
+                        NULL /*Set Vref = 0 to test*/, AUTOK_OFF, NORMAL_K);
+            timestamp_show();
+            mcSHOW_DBG_MSG6(("DramcRxWindowPerbitCal end<-----\n\n"));
+
+            #if ENABLE_EYESCAN_GRAPH
+                if (GetEyeScanEnable(DramConfig, EYESCAN_TYPE_RX) == ENABLE)
+                {
+                    mcSHOW_DBG_MSG6(("DramcRxWindowPerbitCal EYESCAN start<-----\n\n"));
+                    DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE, NULL /*Set Vref = 0 to test*/, AUTOK_ON, EYESCAN_K);
+                    print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_RX); //draw RX eyescan
+                    mcSHOW_DBG_MSG6(("DramcRxWindowPerbitCal EYESCAN end<-----\n\n"));
+                }
+            #endif
+        }
+#endif // (SIMULATION_RX_PERBIT == 1)
+
+#if (SIMULATION_RX_DVS == 1)
+    if (DramConfig->frequency >=2133)
+        DramcRxDVSWindowCal(DramConfig);
+#endif
+
+#if TX_OE_CALIBATION
+        if (DramConfig->frequency >= 1600)
+        {
+            DramcTxOECalibration(DramConfig);
+        }
+#endif // TX_OE_CALIBATION
+
+        #if ENABLE_TX_TRACKING
+        #if 0 /* Starting from Vinson, no need to pre-calculate MR23 for different freqs */
+        if (gu1MR23Done == FALSE)
+        {
+            DramcDQSOSCAuto(p);
+        }
+        #endif
+        DramcDQSOSCAuto(DramConfig);
+        DramcDQSOSCMR23(DramConfig);
+        DramcDQSOSCSetMR18MR19(DramConfig);
+        #endif
+    }
+
+    vSetRank(DramConfig, RANK_0);
+
+    #if ENABLE_TX_TRACKING
+    DramcDQSOSCShuSettings(DramConfig);
+    #endif
+
+///TODO: wait for porting +++
+#if GATING_ADJUST_TXDLY_FOR_TRACKING
+    DramcRxdqsGatingPostProcess(DramConfig);
+#endif
+
+#if TDQSCK_PRECALCULATION_FOR_DVFS
+    DramcDQSPrecalculation_preset(DramConfig);
+#endif
+
+#if SIMULATION_RX_DVS
+    if (DramConfig->frequency >=2133)
+        DramcDramcRxDVSCalPostProcess(DramConfig);
+#endif
+
+#if XRTWTW_NEW_CROSS_RK_MODE
+    if (DramConfig->support_rank_num == RANK_DUAL)
+    {
+        XRTWTW_SHU_Setting(DramConfig);
+    }
+#endif
+
+#if DV_SIMULATION_DATLAT
+    DramcDualRankRxdatlatCal(DramConfig);
+#endif
+
+#if RDSEL_TRACKING_EN
+    if (DramConfig->frequency != 400)
+        RDSELRunTimeTracking_preset(DramConfig);
+#endif
+
+///TODO: wait for porting ---
+
+}
+
+void DPI_vDramCalibrationAllChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args_t *psra)
+{
+    U8 channel_idx, rank_idx;
+
+    CKEFixOnOff(DramConfig, TO_ALL_RANK, CKE_FIXOFF, TO_ALL_CHANNEL);
+    for (channel_idx = CHANNEL_A; channel_idx < DramConfig->support_channel_num; channel_idx++)
+    {
+        vSetPHY2ChannelMapping(DramConfig, channel_idx);// when switching channel, must update PHY to Channel Mapping
+        CKEFixOnOff(DramConfig, TO_ALL_RANK, CKE_FIXON, TO_ONE_CHANNEL);
+        DPI_vDramCalibrationSingleChannel(DramConfig, psra);
+    }
+
+    vSetPHY2ChannelMapping(DramConfig, CHANNEL_A);
+
+///TODO: wait for porting +++
+#if ENABLE_READ_DBI
+    DramcReadDBIOnOff(DramConfig, DramConfig->DBI_R_onoff[DramConfig->dram_fsp]);
+#endif
+
+#if ENABLE_WRITE_DBI
+    // Just settle the DBI parameters which would be stored into shuffle space.
+    if (DramConfig->DBI_W_onoff[DramConfig->dram_fsp])
+    {
+        for (channel_idx = CHANNEL_A; channel_idx < DramConfig->support_channel_num; channel_idx++)
+        {
+            vSetPHY2ChannelMapping(DramConfig, channel_idx);
+
+            for (rank_idx = RANK_0; rank_idx < DramConfig->support_rank_num; rank_idx++)
+            {
+                vSetRank(DramConfig, rank_idx);
+                DramcWriteShiftMCKForWriteDBI(DramConfig, -1); //Tx DQ/DQM -1 MCK for write DBI ON
+            }
+            vSetRank(DramConfig, RANK_0);
+        }
+        vSetPHY2ChannelMapping(DramConfig, CHANNEL_A);
+
+        // Improve Write DBI Power
+        ApplyWriteDBIPowerImprove(DramConfig, ENABLE);
+
+        #if ENABLE_WRITE_DBI_Protect
+        ApplyWriteDBIProtect(DramConfig, ENABLE);
+        #endif
+    }
+    DramcWriteDBIOnOff(DramConfig, DramConfig->DBI_W_onoff[DramConfig->dram_fsp]);
+
+
+#endif
+
+#if XRTRTR_NEW_CROSS_RK_MODE
+    if (DramConfig->support_rank_num == RANK_DUAL)
+    {
+        XRTRTR_SHU_Setting(DramConfig);
+    }
+#endif
+
+#if DV_SIMULATION_DFS
+#if (ENABLE_TX_TRACKING || TDQSCK_PRECALCULATION_FOR_DVFS)
+    FreqJumpRatioCalculation(DramConfig);
+#endif
+#endif
+
+#ifdef TEMP_SENSOR_ENABLE
+    DramcHMR4_Presetting(DramConfig);
+#endif
+
+#if ENABLE_TX_TRACKING
+    U8 backup_channel = DramConfig->channel;
+    U8 channelIdx;
+
+    for (channelIdx = CHANNEL_A; channelIdx < DramConfig->support_channel_num; channelIdx++)
+    {
+        vSetPHY2ChannelMapping(DramConfig, channelIdx);
+        DramcHwDQSOSC(DramConfig);
+    }
+
+    vSetPHY2ChannelMapping(DramConfig, backup_channel);
+    mcSHOW_DBG_MSG6(("TX_TRACKING: ON\n"));
+#else
+    mcSHOW_DBG_MSG6(("TX_TRACKING: OFF\n"));
+#endif
+
+///TODO: wait for porting ---
+
+}
+
+///TODO: wait for porting +++
+#if __A60868_TO_BE_PORTING__
+void RG_dummy_write(DRAMC_CTX_T *p, U32 pattern)
+{
+    unsigned int ii;
+    for (ii = 0; ii < 20; ii++)
+        vIO32WriteFldAlign(DDRPHY_RFU_0X1D4, pattern, RFU_0X1D4_RESERVED_0X1D4);
+}
+
+void EnablePLLtoSPMControl(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_SPM_DVFS_CONTROL_SEL); // DFS SPM mode for calibration
+}
+#endif // __A60868_TO_BE_PORTING__
+///TODO: wait for porting ---
+
+void dump_dramc_ctx(DRAMC_CTX_T *p)
+{
+    mcSHOW_DBG_MSG6(("== DRAMC_CTX_T ==\n"));
+    mcSHOW_DBG_MSG6(("support_channel_num:    %d\n", p->support_channel_num));
+    mcSHOW_DBG_MSG6(("channel:                %d\n", p->channel));
+    mcSHOW_DBG_MSG6(("support_rank_num:       %d\n", p->support_rank_num));
+    mcSHOW_DBG_MSG6(("rank:                   %d\n", p->rank));
+    mcSHOW_DBG_MSG6(("freq_sel:               %d\n", p->freq_sel));
+    mcSHOW_DBG_MSG6(("SRAMIdx:               %d\n", vGet_Current_SRAMIdx(p)));
+    mcSHOW_DBG_MSG6(("dram_type:              %d\n", p->dram_type));
+    mcSHOW_DBG_MSG6(("dram_fsp:               %d\n", p->dram_fsp));
+    mcSHOW_DBG_MSG6(("odt_onoff:              %d\n", p->odt_onoff));
+    mcSHOW_DBG_MSG6(("dram_cbt_mode:          %d, %d\n", (int)p->dram_cbt_mode[0], (int)p->dram_cbt_mode[1]));
+    mcSHOW_DBG_MSG6(("DBI_R_onoff:            %d, %d\n", (int)p->DBI_R_onoff[0], (int)p->DBI_R_onoff[1]));
+    mcSHOW_DBG_MSG6(("DBI_W_onoff:            %d, %d\n", (int)p->DBI_W_onoff[0], (int)p->DBI_W_onoff[1]));
+    mcSHOW_DBG_MSG6(("data_width:             %d\n", p->data_width));
+    mcSHOW_DBG_MSG6(("test2_1:             0x%x\n", p->test2_1));
+    mcSHOW_DBG_MSG6(("test2_2:             0x%x\n", p->test2_2));
+    mcSHOW_DBG_MSG6(("frequency:              %d\n", p->frequency));
+    mcSHOW_DBG_MSG6(("freqGroup:              %d\n", p->freqGroup));
+    mcSHOW_DBG_MSG6(("lp5_training_mode:              %d\n", p->lp5_training_mode));
+    mcSHOW_DBG_MSG6(("lp5_cbt_phase:              %d\n", p->lp5_cbt_phase));
+    mcSHOW_DBG_MSG6(("new_cbt_mode:              %d\n", p->new_cbt_mode));
+    mcSHOW_DBG_MSG6(("u1PLLMode:              %d\n", p->u1PLLMode));
+    mcSHOW_DBG_MSG6(("curDBIState:              %d\n", p->curDBIState));
+}
+
+
+void DPI_SW_main_LP4(DRAMC_CTX_T *ExtConfig, cal_sv_rand_args_t *psra)
+{
+    u32 value;
+#if DV_SIMULATION_DFS
+    S8 s1ShuIdx;
+#endif
+
+    DRAMC_CTX_T *p = &DramCtx_LPDDR4; //default;
+
+    p->dram_type = ExtConfig->dram_type;
+    if(p->dram_type==TYPE_LPDDR5)
+    {
+        MEM_TYPE = LPDDR5;
+    }
+    else
+    {
+        MEM_TYPE = LPDDR4;
+    }
+
+    p->dram_cbt_mode[0] = ExtConfig->dram_cbt_mode[0];
+    p->dram_cbt_mode[1] = ExtConfig->dram_cbt_mode[1];
+    p->freq_sel = ExtConfig->freq_sel;
+    p->frequency = ExtConfig->frequency;
+    p->freqGroup = ExtConfig->freqGroup;
+    p->new_cbt_mode = ExtConfig->new_cbt_mode;
+
+#if 0 // for Refs
+DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = {
+    {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K,  VREF_CALI_OFF,  CLOSE_LOOP_MODE},  // highest freq of term group (3733) must k first.
+    {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K,  VREF_CALI_ON,   CLOSE_LOOP_MODE},  // highest freq of term group (3733) must k first.
+    {LP4_DDR800  /*2*/, DIV4_MODE, SRAM_SHU6, DUTY_DEFAULT, VREF_CALI_OFF,  SEMI_OPEN_LOOP_MODE},  //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT)
+    {LP4_DDR1866 /*3*/, DIV8_MODE, SRAM_SHU3, DUTY_LAST_K,  VREF_CALI_OFF,  CLOSE_LOOP_MODE},  // highest freq of unterm group (2400) must k first.
+    {LP4_DDR1200 /*4*/, DIV8_MODE, SRAM_SHU5, DUTY_LAST_K,  VREF_CALI_OFF,  CLOSE_LOOP_MODE},  // highest freq of unterm group (2400) must k first.
+    {LP4_DDR2400 /*5*/, DIV8_MODE, SRAM_SHU2, DUTY_NEED_K,  VREF_CALI_ON,   CLOSE_LOOP_MODE},  // highest freq of unterm group (2400) must k first.
+    {LP4_DDR1600 /*6*/, DIV8_MODE, SRAM_SHU4, DUTY_DEFAULT, VREF_CALI_ON,  CLOSE_LOOP_MODE},  //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT)
+};
+#endif
+    if (u1IsLP4Family(p->dram_type))
+    {
+        if((ExtConfig->freq_sel==LP4_DDR3733) || (ExtConfig->freq_sel==LP4_DDR4266))
+        {
+            p->pDFSTable = &gFreqTbl[1];
+        }
+        else if(ExtConfig->freq_sel==LP4_DDR1600)
+        {
+            p->pDFSTable = &gFreqTbl[DRAM_DFS_SRAM_MAX - 1];
+        }
+        else if(ExtConfig->freq_sel==LP4_DDR800)
+        {
+            p->pDFSTable = &gFreqTbl[2];
+        }
+#if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
+        else if(ExtConfig->freq_sel==LP4_DDR400)
+        {
+            p->pDFSTable = &gFreqTbl[2];
+        }
+#endif
+    }
+
+    enter_function();
+
+    if (!psra) {
+        /*
+         * for SA's simulation
+         */
+        mcSHOW_DBG_MSG6(("enter SA's simulation flow.\n"));
+        p->support_channel_num = CHANNEL_SINGLE;
+        p->channel = CHANNEL_A;
+        p->support_rank_num = RANK_DUAL;
+        /* DramRank */
+        p->rank = RANK_0;
+        /* DRAMC operation clock frequency in MHz */
+        #if (fcFOR_CHIP_ID == fcA60868)
+        #if DV_SIMULATION_DFS
+        p->pDFSTable = &gFreqTbl[DRAM_DFS_SRAM_MAX-1];
+        #endif
+        #endif
+#if 0
+        /* DRAM type */
+        #if DV_SIMULATION_LP4
+        p->dram_type = TYPE_LPDDR4X;
+        //p->freq_sel = LP4_DDR3200;//DV_SIMULATION_RUN_FREQ_SEL;
+        //p->frequency = 1600;//DV_SIMULATION_RUN_FREQ;
+        p->freq_sel = LP4_DDR1600;//DV_SIMULATION_RUN_FREQ_SEL;
+        p->frequency = 800;//DV_SIMULATION_RUN_FREQ;
+        #else
+        p->dram_type = TYPE_LPDDR5;
+        p->freq_sel = LP5_DDR3200;//DV_SIMULATION_RUN_FREQ_SEL;
+        p->frequency = 1600;//DV_SIMULATION_RUN_FREQ;
+        #endif
+#endif
+        /* DRAM Fast switch point type, only for LP4, useless in LP3 */
+        p->dram_fsp = FSP_0;
+
+#if 0
+        #if DV_SIMULATION_BYTEMODE
+        p->dram_cbt_mode[RANK_0] = CBT_BYTE_MODE1;
+        p->dram_cbt_mode[RANK_1] = CBT_BYTE_MODE1;
+        #else
+        p->dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE;
+        p->dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE;
+        #endif
+#endif
+        /* IC and DRAM read DBI */
+        p->DBI_R_onoff[FSP_0] = DBI_OFF; /* only for LP4, uesless in LP3 */
+        p->DBI_R_onoff[FSP_1] = DBI_OFF; /* only for LP4, uesless in LP3 */
+        #if ENABLE_READ_DBI
+        p->DBI_R_onoff[FSP_1] = DBI_ON; /* only for LP4, uesless in LP3 */
+        #else
+        p->DBI_R_onoff[FSP_1] = DBI_OFF; /* only for LP4, uesless in LP3 */
+        #endif
+        /* IC and DRAM write DBI */
+        p->DBI_W_onoff[FSP_0] = DBI_OFF; /* only for LP4, uesless in LP3 */
+        p->DBI_W_onoff[FSP_1] = DBI_OFF; /* only for LP4, uesless in LP3 */
+        #if ENABLE_WRITE_DBI
+        p->DBI_W_onoff[FSP_1] = DBI_ON; /* only for LP4, uesless in LP3 */
+        #else
+        p->DBI_W_onoff[FSP_1] = DBI_OFF; /* only for LP4, uesless in LP3 */
+        #endif
+        /* bus width */
+        p->data_width = DATA_WIDTH_16BIT;
+        /* DRAMC internal test engine-2 parameters in calibration */
+        p->test2_1 = DEFAULT_TEST2_1_CAL;
+        p->test2_2 = DEFAULT_TEST2_2_CAL;
+        /* DRAMC test pattern in calibration */
+        p->test_pattern = TEST_XTALK_PATTERN;
+        /* u2DelayCellTimex100 */
+        p->u2DelayCellTimex100 = 250; // @Darren, 2.5ps
+        p->vendor_id = 0x1;
+        p->density = 0;
+        /* p->ranksize = {0,0}; */
+        p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
+        #if DV_SIMULATION_LP5_TRAINING_MODE1
+        p->lp5_training_mode = TRAINING_MODE1;
+        #else
+        p->lp5_training_mode = TRAINING_MODE2;
+        #endif
+
+        #if DV_SIMULATION_LP5_CBT_PHASH_R
+        p->lp5_cbt_phase = CBT_PHASE_RISING;
+        #else
+        p->lp5_cbt_phase = CBT_PHASE_FALLING;
+        #endif
+    } else {
+        /*
+         * for DV's regression
+         */
+        mcSHOW_DBG_MSG6(("enter DV's regression flow.\n"));
+        p->support_channel_num = CHANNEL_SINGLE;
+        p->channel = psra->calibration_channel;
+        p->support_rank_num = RANK_DUAL;
+        /* DramRank */
+        p->rank = psra->calibration_rank;
+        /* DRAMC operation clock frequency in MHz */
+        #if (fcFOR_CHIP_ID == fcA60868)
+        #if DV_SIMULATION_DFS
+        p->pDFSTable = &gFreqTbl[DRAM_DFS_SRAM_MAX-1];
+        #endif
+        #endif
+
+        /* DRAM type */
+        //p->dram_type = psra->dram_type;
+        //p->freq_sel = LP5_DDR4266;//DV_SIMULATION_RUN_FREQ_SEL;
+        //p->frequency = 2133;//DV_SIMULATION_RUN_FREQ;
+        set_type_freq_by_svargs(p, psra);
+
+        /* DRAM Fast switch point type, only for LP4, useless in LP3 */
+        p->dram_fsp = FSP_0;
+
+        p->dram_cbt_mode[RANK_0] = psra->rk0_cbt_mode;
+        p->dram_cbt_mode[RANK_1] = psra->rk1_cbt_mode;
+
+        /* IC and DRAM read DBI */
+        p->DBI_R_onoff[FSP_0] = (psra->mr3_value >> 6) & 0x1; /* only for LP4, uesless in LP3 */
+        p->DBI_R_onoff[FSP_1] = (psra->mr3_value >> 6) & 0x1; /* only for LP4, uesless in LP3 */
+        p->DBI_R_onoff[FSP_2] = (psra->mr3_value >> 6) & 0x1;
+        /* IC and DRAM write DBI */
+        p->DBI_W_onoff[FSP_0] = (psra->mr3_value >> 7) & 0x1; /* only for LP4, uesless in LP3 */
+        p->DBI_W_onoff[FSP_1] = (psra->mr3_value >> 7) & 0x1; /* only for LP4, uesless in LP3 */
+        p->DBI_W_onoff[FSP_2] = (psra->mr3_value >> 7) & 0x1;
+        /* bus width */
+        p->data_width = DATA_WIDTH_16BIT;
+        /* DRAMC internal test engine-2 parameters in calibration */
+        p->test2_1 = DEFAULT_TEST2_1_CAL;
+        p->test2_2 = DEFAULT_TEST2_2_CAL;
+        /* DRAMC test pattern in calibration */
+        p->test_pattern = TEST_XTALK_PATTERN;
+        /* u2DelayCellTimex100 */
+        p->u2DelayCellTimex100 = 0;
+        p->vendor_id = 0x1;
+        p->density = 0;
+        /* p->ranksize = {0,0}; */
+        p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
+        p->lp5_training_mode = psra->cbt_training_mode;
+        p->lp5_cbt_phase = psra->cbt_phase;
+        p->new_cbt_mode = psra->new_cbt_mode;
+    }
+
+#if QT_GUI_Tool
+    p->lp5_training_mode = ExtConfig->lp5_training_mode;
+#endif
+
+    if (psra && is_lp5_family(p)) {
+        p->dram_fsp = (psra->mr16_value >> 2) & 0x3;
+    } else if (psra && u1IsLP4Family(p->dram_type)) {
+        p->dram_fsp = (psra->mr13_value >> 7) & 0x1;
+    }
+
+//    p->dram_type = TYPE_LPDDR5;
+//    #define __FW_VER__ "WCK leveling with DLY +16! and MRinit for FSP1 -- 777"
+    #define __FW_VER__ "All struct move done, new RX range -- 444"
+
+    if (u1IsLP4Family(p->dram_type)) {
+        mcSHOW_DBG_MSG6(("%s enter == LP4 == ...%s\n", __FUNCTION__, __FW_VER__));
+    } else {
+        mcSHOW_DBG_MSG6(("%s enter == LP5 == ...%s\n", __FUNCTION__, __FW_VER__));
+    }
+    mcSHOW_DBG_MSG6((CHK_INCLUDE_LOCAL_HEADER));
+
+    mcSHOW_DBG_MSG6(("SIMULATION_LP4_ZQ           ... %d\n", SIMULATION_LP4_ZQ));
+    mcSHOW_DBG_MSG6(("SIMULATION_SW_IMPED         ... %d\n", SIMULATION_SW_IMPED));
+    mcSHOW_DBG_MSG6(("SIMULATION_MIOCK_JMETER     ... %d\n", SIMULATION_MIOCK_JMETER));
+    mcSHOW_DBG_MSG6(("SIMULATION_8PHASE           ... %d\n", SIMULATION_8PHASE));
+    mcSHOW_DBG_MSG6(("SIMULATION_RX_INPUT_BUF     ... %d\n", SIMULATION_RX_INPUT_BUF));
+    mcSHOW_DBG_MSG6(("SIMUILATION_CBT             ... %d\n", SIMUILATION_CBT));
+    mcSHOW_DBG_MSG6(("SIMULATION_WRITE_LEVELING   ... %d\n", SIMULATION_WRITE_LEVELING));
+    mcSHOW_DBG_MSG6(("SIMULATION_DUTY_CYC_MONITOR ... %d\n", SIMULATION_DUTY_CYC_MONITOR));
+    mcSHOW_DBG_MSG6(("SIMULATION_GATING           ... %d\n", SIMULATION_GATING));
+    mcSHOW_DBG_MSG6(("SIMULATION_DATLAT           ... %d\n", SIMULATION_DATLAT));
+    mcSHOW_DBG_MSG6(("SIMULATION_RX_RDDQC         ... %d\n", SIMULATION_RX_RDDQC));
+    mcSHOW_DBG_MSG6(("SIMULATION_RX_PERBIT        ... %d\n", SIMULATION_RX_PERBIT));
+    mcSHOW_DBG_MSG6(("SIMULATION_TX_PERBIT        ... %d\n", SIMULATION_TX_PERBIT));
+    mcSHOW_DBG_MSG6(("\n\n"));
+
+    mcSHOW_DBG_MSG6(("============== CTX before calibration ================\n"));
+    dump_dramc_ctx(p);
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+    //vIO32Write4B_All2(p, DDRPHY_SHU_RK_CA_CMD1, 0x0FFF);
+    value = u4Dram_Register_Read(p, DRAMC_REG_DDRCOMMON0);
+    mcSHOW_DBG_MSG6(("Get Addr:0x%x, Value:0x%x\n", DRAMC_REG_DDRCOMMON0, value));
+
+    value = u4Dram_Register_Read(p, DDRPHY_REG_SHU_RK_CA_CMD1);
+    mcSHOW_DBG_MSG6(("Get Addr:0x%x, Value:0x%x\n", DDRPHY_REG_SHU_RK_CA_CMD1, value));
+
+    value = u4Dram_Register_Read(p, DDRPHY_REG_MISC_DQO1);
+    mcSHOW_DBG_MSG6(("Get Addr:0x%x, Value:0x%x\n", DDRPHY_REG_MISC_DQO1, value));
+
+    value = u4Dram_Register_Read(p, DDRPHY_MD32_REG_SSPM_TIMER0_RESET_VAL );
+    mcSHOW_DBG_MSG6(("Get Addr:0x%x, Value:0x%x\n", DDRPHY_MD32_REG_SSPM_TIMER0_RESET_VAL, value));
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON); //LP4 broadcast on
+
+    Global_Option_Init(p);
+
+#if __A60868_TO_BE_PORTING__
+    vDramcInit_PreSettings(p);
+
+    DDRPhyFreqSel(p, p->pDFSTable->freq_sel);
+
+    vSetPHY2ChannelMapping(p, p->channel);
+#endif // __A60868_TO_BE_PORTING__
+    ///TODO: wait for porting ---
+
+
+    if (u1IsLP4Family(p->dram_type))
+    {
+        vSetDFSFreqSelByTable(p, p->pDFSTable); // for LP4x
+    }
+    else ///TODO: Jeremy, modify this when LP5 gFreqtbl ready
+    {
+        DDRPhyFreqSel(p, p->freq_sel);
+    }
+
+#if (SIMULATION_SW_IMPED == 1)
+    mcSHOW_DBG_MSG6(("\n----->DramcImpedanceCal begin...\n"));
+    timestamp_show();
+    // LP4 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266
+    // LP5 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266
+    DramcImpedanceCal(p, 1, IMP_LOW_FREQ);
+    DramcImpedanceCal(p, 1, IMP_HIGH_FREQ);
+    timestamp_show();
+    mcSHOW_DBG_MSG6(("DramcImpedanceCal end<-----\n\n"));
+#endif /* (SIMULATION_SW_IMPED == 1) */
+
+#if DV_SIMULATION_INIT_C
+    ///TODO: wait for porting +++
+    DramcInit(p);
+
+    // Before calibration setting
+    vBeforeCalibration(p);
+#if __A60868_TO_BE_PORTING__
+    #if DV_SIMULATION_BEFORE_K
+    vApplyConfigBeforeCalibration(p);
+    //vMR2InitForSimulationTest(p);
+    #endif
+
+#ifdef DUMP_INIT_RG_LOG_TO_DE
+    #if 0 //Dump RG to other shuffle for FT used, don't delete
+        mcSHOW_DUMP_INIT_RG_MSG(("\n\n\n\n\n\n===== Save to Shuffle RG ======\n"));
+        DramcSaveToShuffleReg(p, DRAM_DFS_SHUFFLE_1, DRAM_DFS_SHUFFLE_3);
+    #endif
+        while (1);
+#endif
+#endif
+#endif // __A60868_TO_BE_PORTING__
+    ///TODO: wait for porting ---
+
+
+#if (SIMULATION_MIOCK_JMETER == 1)
+    mcSHOW_DBG_MSG6(("\n----->DramcMiockJmeter begin...\n"));
+    timestamp_show();
+    p->u2DelayCellTimex100 = GetVcoreDelayCellTime(p);
+    timestamp_show();
+    mcSHOW_DBG_MSG6(("DramcMiockJmeter end<-----\n\n"));
+#endif /* (SIMULATION_MIOCK_JMETER == 1) */
+
+#if (SIMULATION_8PHASE == 1)
+    if(is_lp5_family(p) && (p->frequency >= 2133)) {
+        mcSHOW_DBG_MSG6(("\n----->Dramc8PhaseCal begin...\n"));
+        timestamp_show();
+        Dramc8PhaseCal(p); // it must set before duty calib
+        timestamp_show();
+        mcSHOW_DBG_MSG6(("Dramc8PhaseCal end<-----\n\n"));
+    }
+#endif /* (SIMULATION_8PHASE == 1) */
+
+    ///TODO: wait for porting +++
+    #if !DV_SIMULATION_DFS // No calib will use legacy mode init settings
+    DPI_vDramCalibrationAllChannel(p, psra); // for DDR1600 1:8 mode
+    #endif
+
+#if DV_SIMULATION_DFS
+    DramcSaveToShuffleSRAM(p, DRAM_DFS_REG_SHU0, vGet_Current_SRAMIdx(p));
+    LoadShuffleSRAMtoDramc(p, vGet_Current_SRAMIdx(p), DRAM_DFS_REG_SHU1); //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT)
+
+    #if (fcFOR_CHIP_ID == fcA60868)
+    for (s1ShuIdx = DRAM_DFS_SRAM_MAX - 10; s1ShuIdx >= 0; s1ShuIdx--)
+    #else
+    for (s1ShuIdx = DRAM_DFS_SRAM_MAX - 2; s1ShuIdx >= 0; s1ShuIdx--)
+    #endif
+    {
+        vSetDFSFreqSelByTable(p, &gFreqTbl[s1ShuIdx]);
+        DramcInit(p);
+        // Before calibration setting
+        vBeforeCalibration(p);
+
+        #if DV_SIMULATION_BEFORE_K
+        vApplyConfigBeforeCalibration(p);
+        #endif
+
+        #if (SIMULATION_8PHASE == 1)
+        if(is_lp5_family(p) && (p->frequency >= 2133)) {
+            mcSHOW_DBG_MSG6(("\n----->Dramc8PhaseCal begin...\n"));
+            timestamp_show();
+            Dramc8PhaseCal(p); // it must set before duty calib
+            timestamp_show();
+            mcSHOW_DBG_MSG6(("Dramc8PhaseCal end<-----\n\n"));
+        }
+        #endif /* (SIMULATION_8PHASE == 1) */
+
+        #if !DV_SIMULATION_DFS // No calib will use legacy mode init settings
+        DPI_vDramCalibrationAllChannel(p, psra); // for gDVDFSTbl
+        #endif
+        DramcSaveToShuffleSRAM(p, DRAM_DFS_REG_SHU0, gFreqTbl[s1ShuIdx].SRAMIdx);
+    }
+#endif
+    ///TODO: wait for porting ---
+
+
+
+
+    ///TODO: wait for porting +++
+    vAfterCalibration(p);
+
+#if SIMULATION_RUNTIME_CONFIG
+    DramcRunTimeConfig(p);
+#endif
+
+#if 0//__A60868_TO_BE_PORTING__
+#if DV_SIMULATION_AFTER_K
+    vApplyConfigAfterCalibration(p);
+#endif
+
+#if DV_SIMULATION_RUN_TIME_MRW
+    enter_pasr_dpd_config(0, 0xFF);
+#endif
+
+#if DV_SIMULATION_RUN_TIME_MRR
+    DramcModeRegReadByRank(p, RANK_0, 4, &u2val1);
+    DramcModeRegReadByRank(p, RANK_0, 5, &u2val2);
+    DramcModeRegReadByRank(p, RANK_0, 8, &u2val3);
+    mcSHOW_DBG_MSG(("[Runtime time MRR] MR4 = 0x%x, MR5 = 0x%x, MR8 = 0x%x\n", u2val1, u2val2, u2val3));
+#endif
+
+#if 0//DV_SIMULATION_DFS // NOTE: Don't use DramcDFSDirectJump_SPMMode. it will cause NULL object access.
+    // high freq -> low freq
+    for (s1ShuIdx = 0; s1ShuIdx < DV_SIMULATION_DFS_SHU_MAX; s1ShuIdx++)
+            DramcDFSDirectJump_SRAMShuRGMode(p, gDVDFSTbl[s1ShuIdx].SRAMIdx);
+    // low freq -> high freq
+    for (s1ShuIdx = DV_SIMULATION_DFS_SHU_MAX - 1; s1ShuIdx >= DRAM_DFS_SHUFFLE_1; s1ShuIdx--)
+            DramcDFSDirectJump_SRAMShuRGMode(p, gDVDFSTbl[s1ShuIdx].SRAMIdx);
+#endif
+
+#if DV_SIMULATION_SPM_CONTROL
+    EnablePLLtoSPMControl(p);
+#endif
+
+    RG_dummy_write(p, 0xAAAAAAAA);
+#endif // __A60868_TO_BE_PORTING__
+    ///TODO: wait for porting ---
+
+    //Temp_TA2_Test_After_K(p);
+
+    //Ett_Mini_Strss_Test(p);
+#if MRW_CHECK_ONLY
+    vPrintFinalModeRegisterSetting(p);
+#endif
+#if PRINT_CALIBRATION_SUMMARY
+    vPrintCalibrationResult(p);
+#endif
+
+    exit_function();
+}
+
+/*
+ * start_dramk -- c calibration entry for SA's simulation
+ */
+void start_dramk(void)
+{
+    DRAMC_CTX_T *p;
+
+    enter_function();
+    broadcast_off();
+    p = &DramCtx_LPDDR4;
+    DPI_SW_main_LP4(p, NULL);
+    exit_function();
+}
+
+/*
+ * sa_calibration -- c calibration entry for DV's regression
+ *
+ * @psra: random arguments from sv to c for calibration controlling
+ */
+void sa_calibration(cal_sv_rand_args_t *psra)
+{
+    DRAMC_CTX_T *p;
+
+    enter_function();
+    if (psra == NULL) {
+        mcSHOW_DBG_MSG6(("psv_args is NULL.\n"));
+        goto out;
+    }
+
+    print_sv_args(psra);
+    if (!valid_magic(psra)) {
+        mcSHOW_DBG_MSG6(("sv arguments is invalid.\n"));
+        goto out;
+    }
+
+    set_psra(psra);
+    broadcast_off();
+    if (psra->calibration_channel == SV_CHN_A)
+        p = &DramCtx_LPDDR4;
+    else
+        p = &dram_ctx_chb;
+
+    DPI_SW_main_LP4(p, psra);
+
+out:
+    exit_function();
+    return;
+}
+
+
+///TODO: wait for porting +++
+#if __A60868_TO_BE_PORTING__
+#if SW_CHANGE_FOR_SIMULATION
+void main(void)
+{
+
+    DRAMC_CTX_T DramConfig;
+    DramConfig.channel = CHANNEL_A;
+    DramConfig.support_rank_num = RANK_DUAL;
+    // DramRank
+    DramConfig.rank = RANK_0;
+    // DRAM type
+    DramConfig.dram_type = TYPE_LPDDR4X;
+    // DRAM Fast switch point type, only for LP4, useless in LP3
+    DramConfig.dram_fsp = FSP_0;
+    // DRAM CBT mode, only for LP4, useless in LP3
+    DramConfig.dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE;
+    DramConfig.dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE;
+    // IC and DRAM read DBI
+    DramConfig.DBI_R_onoff[FSP_0] = DBI_OFF;             // only for LP4, uesless in LP3
+    #if ENABLE_READ_DBI
+    DramConfig.DBI_R_onoff[FSP_1] = DBI_ON;              // only for LP4, uesless in LP3
+    #else
+    DramConfig.DBI_R_onoff[FSP_1] = DBI_OFF;        // only for LP4, uesless in LP3
+    #endif
+    // IC and DRAM write DBI
+    DramConfig.DBI_W_onoff[FSP_0] = DBI_OFF;             // only for LP4, uesless in LP3
+    #if ENABLE_WRITE_DBI
+    DramConfig.DBI_W_onoff[FSP_1] = DBI_ON;              // only for LP4, uesless in LP3
+    #else
+    DramConfig.DBI_W_onoff[FSP_1] = DBI_OFF;         // only for LP4, uesless in LP3
+    #endif
+    // bus width
+    DramConfig.data_width = DATA_WIDTH_32BIT;
+    // DRAMC internal test engine-2 parameters in calibration
+    DramConfig.test2_1 = DEFAULT_TEST2_1_CAL;
+    DramConfig.test2_2 = DEFAULT_TEST2_2_CAL;
+    // DRAMC test pattern in calibration
+    DramConfig.test_pattern = TEST_XTALK_PATTERN;
+    // DRAMC operation clock frequency in MHz
+    DramConfig.frequency = 800;
+
+    //DramConfig.enable_rx_scan_vref =DISABLE;
+    //DramConfig.enable_tx_scan_vref =DISABLE;
+    //DramConfig.dynamicODT = DISABLE;
+
+    MPLLInit();
+
+    Global_Option_Init(&DramConfig);
+
+    // DramC & PHY init for all channels
+    DDRPhyFreqSel(&DramConfig, LP4_DDR1600);
+
+
+#if WRITE_LEVELING_MOVE_DQS_INSTEAD_OF_CLK
+    memset(DramConfig.arfgWriteLevelingInitShif, FALSE, sizeof(DramConfig.arfgWriteLevelingInitShif));
+    //>fgWriteLevelingInitShif= FALSE;
+#endif
+
+    DramcInit(&DramConfig);
+
+    vApplyConfigBeforeCalibration(&DramConfig);
+    vMR2InitForSimulationTest(&DramConfig);
+
+    vSetPHY2ChannelMapping(&DramConfig, DramConfig.channel);
+
+    #if SIMULATION_SW_IMPED
+    DramcImpedanceCal(&DramConfig, 1, LOW_FREQ);  //for DRVN/P and ODTN
+    //DramcImpedanceCal(&DramConfig, 1, HIGH_FREQ);  //for DRVN/P and ODTN
+    #endif
+
+
+#if SIMULATION_LP4_ZQ
+     if (DramConfig.dram_type == TYPE_LPDDR4 || DramConfig.dram_type == TYPE_LPDDR4X || DramConfig.dram_type == TYPE_LPDDR4P)
+     {
+         DramcZQCalibration(&DramConfig);
+     }
+#endif
+
+    #if SIMUILATION_LP4_CBT
+    CmdBusTrainingLP4(&DramConfig);
+    #endif
+
+#if SIMULATION_WRITE_LEVELING
+    DramcWriteLeveling(&DramConfig);
+#endif
+
+    #if SIMULATION_GATING
+    // Gating calibration of single rank
+    DramcRxdqsGatingCal(&DramConfig);
+
+    // Gating calibration of both rank
+    //DualRankDramcRxdqsGatingCal(&DramConfig);
+    #endif
+
+#if SIMUILATION_LP4_RDDQC
+    DramcRxWindowPerbitCal(&DramConfig, 0, NULL);
+#endif
+
+    #if SIMULATION_DATLAT
+    // RX Datlat calibration of single rank
+    DramcRxdatlatCal(&DramConfig);
+
+    // RX Datlat calibration of two rank
+    //DramcDualRankRxdatlatCal(&DramConfig);
+    #endif
+
+    #if SIMULATION_RX_PERBIT
+    DramcRxWindowPerbitCal(&DramConfig, 1, NULL);
+    #endif
+
+    #if SIMULATION_TX_PERBIT
+    DramcTxWindowPerbitCal(&DramConfig, TX_DQ_DQS_MOVE_DQ_DQM);
+    DramcTxWindowPerbitCal(&DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY);
+    #endif
+
+    #if ENABLE_READ_DBI
+    //Read DBI ON
+    SetDramModeRegForReadDBIOnOff(&DramConfig, DramConfig.dram_fsp, DramConfig.DBI_R_onoff[DramConfig.dram_fsp]);
+    #endif
+
+    #if ENABLE_WRITE_DBI
+    //Write DBI ON
+    DramcWriteShiftMCKForWriteDBI(&DramConfig, -1);
+    SetDramModeRegForWriteDBIOnOff(&DramConfig, DramConfig.dram_fsp, DramConfig.DBI_W_onoff[DramConfig.dram_fsp]);
+    #endif
+
+    #if ENABLE_READ_DBI
+    DramcReadDBIOnOff(&DramConfig, DramConfig.DBI_R_onoff[DramConfig.dram_fsp]);
+    #endif
+
+    #if ENABLE_WRITE_DBI
+    DramcWriteDBIOnOff(&DramConfig, DramConfig.DBI_W_onoff[DramConfig.dram_fsp]);
+    #endif
+}
+#endif //SW_CHANGE_FOR_SIMULATION
+#endif // __A60868_TO_BE_PORTING__
+///TODO: wait for porting ---
+#endif
+
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c
new file mode 100644
index 000000000000..10323d32d346
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c
@@ -0,0 +1,2289 @@
+//=============================================================================
+//  Include Files
+//=============================================================================
+//#include <common.h>
+//#include <ett_common.h>
+//#include <test_case_controller.h>
+//#include <api.h>
+//#include "gpio.h"
+//#include "ett_cust.h"
+//#include "emi_setting.h"
+//#include "pll.h"
+//#include "dramc_pi_api.h"
+
+#include "dramc_common.h"
+#include "dramc_int_global.h"
+#include "dramc_top.h"
+#include "dramc_custom.h"
+
+
+
+
+#if !__FLASH_TOOL_DA__ && !__ETT__
+//#include "custom_emi.h"   //[FOR_CHROMEOS]
+#endif
+
+#include <emi_hw.h>
+#include <emi.h>
+// #include "voltage.h"
+
+#include <soc/dramc_param.h>
+#include <soc/emi.h>
+
+#if DRAM_AUXADC_CONFIG
+#include <mtk_auxadc_sw.h>
+#endif
+
+
+#if (FOR_DV_SIMULATION_USED==0)
+#if 0 /* FIXME: need regulator control */
+#include <pmic.h>
+/* now we can use definition MTK_PMIC_MT6330
+ * ==============================================================
+ * PMIC   |Power |Dflt. Volt. |Step   |Support FPWM |Cmt.
+ * --------------------------------------------------------------
+ * MT6359 |Vcore |0.8v        |6.25mV |Yes          |
+ *        |vio18_2  |1.8v        |0.1V   |No           |
+ * --------------------------------------------------------------
+ * MT6362 |Vdram |1.125v      |5mV    |Yes          |(DRAM Vdram)
+ *        |vmddr |0.75v       |10mV   |No           |(AP Vdram)
+ *        |Vddq  |0.6v        |10mV   |No           |
+ * ==============================================================
+ */
+#define MTK_PMIC_MT6359
+#endif
+#endif
+
+#if !__ETT__
+#define mt_reg_sync_write(x,y) mt_reg_sync_writel(y,x)
+#endif
+
+#ifdef MTK_PMIC_MT6359
+#include <regulator/mtk_regulator.h>
+#include <mt6359.h>
+#endif
+
+#if !__ETT__
+#define CQ_DMA_BASE (0x10212000)
+#endif
+
+
+#if !__ETT__ && CFG_ENABLE_DCACHE
+#define DRAMC_ASSERT(expr)                                            \
+    do {                                                        \
+        if (!(expr)) {                                          \
+      plat_clean_invalidate_dcache();														\
+	    ASSERT(expr);					\
+	}							\
+    } while (0)
+#else
+#define DRAMC_ASSERT(expr)         ASSERT(expr)
+#endif
+
+//=============================================================================
+//  Definition
+//=============================================================================
+
+#if DRAM_AUXADC_CONFIG
+static unsigned int get_ch_num_by_auxadc(void);
+#endif
+//=============================================================================
+//  Global Variables
+//=============================================================================
+static unsigned char auto_detect_done;
+//static int enable_combo_dis = 0;
+//static unsigned short mr5;
+//static unsigned short mr6;
+//static unsigned short mr7;
+//static unsigned short mr8;
+unsigned int channel_num_auxadc = 4;
+#if DRAM_AUXADC_CONFIG
+unsigned int dram_type_auxadc;
+#endif
+
+#ifdef MTK_PMIC_MT6359
+//static struct mtk_regulator reg_vio18_2, reg_vmdd2, reg_vcore, reg_vmddq, reg_vmddr;
+static struct mtk_regulator reg_vio18, reg_vdram, reg_vcore, reg_vddq, reg_vmddr;
+#endif
+
+#ifdef LAST_DRAMC
+static LAST_DRAMC_INFO_T* last_dramc_info_ptr;
+#endif
+
+#ifdef VOLTAGE_SEL
+static VOLTAGE_SEL_INFO_T voltage_sel_info_ptr;
+#endif
+
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+#if (!__ETT__)
+//#include <storage_api.h> //[FOR_CHROMEOS]
+#endif
+static int read_offline_dram_mdl_data(DRAM_INFO_BY_MRR_T *DramInfo);
+static int write_offline_dram_mdl_data(DRAM_INFO_BY_MRR_T *DramInfo);
+#endif
+
+#if defined(SLT) && (!__ETT__)
+#include <pl_version.h>
+static u64 part_dram_data_addr_slt = 0;
+int read_slt_data(DRAM_SLT_DATA_T *data);
+int write_slt_data(DRAM_SLT_DATA_T *data);
+int clean_slt_data(void);
+#endif
+//=============================================================================
+//  External references
+//=============================================================================
+extern char* opt_dle_value;
+
+void print_DBG_info(DRAMC_CTX_T *p);
+
+#if ENABLE_PINMUX_FOR_RANK_SWAP
+static void EMI_rank_swap_emi_setting(EMI_SETTINGS *emi_set)
+{
+	static unsigned int temp;
+
+	if (emi_set->EMI_CONA_VAL & 0x20000) {
+		temp = emi_set->EMI_CONA_VAL;
+		emi_set->EMI_CONA_VAL &= ~(0xF3F0F0F0);
+		emi_set->EMI_CONA_VAL |= (temp & 0xC0C0C0C0) >> 2;
+		emi_set->EMI_CONA_VAL |= (temp & 0x30303030) << 2;
+		emi_set->EMI_CONA_VAL |= (temp & 0x02000000) >> 1;
+		emi_set->EMI_CONA_VAL |= (temp & 0x01000000) << 1;
+
+		temp = emi_set->EMI_CONH_VAL;
+		emi_set->EMI_CONH_VAL &= ~(0xFFFF0030);
+		emi_set->EMI_CONH_VAL |= (temp & 0xF0F00000) >> 4;
+		emi_set->EMI_CONH_VAL |= (temp & 0x0F0F0000) << 4;
+		emi_set->EMI_CONH_VAL |= (temp & 0x00000020) >> 1;
+		emi_set->EMI_CONH_VAL |= (temp & 0x00000010) << 1;
+
+		temp = emi_set->CHN0_EMI_CONA_VAL;
+		emi_set->CHN0_EMI_CONA_VAL &= ~(0x00FFF0FC);
+		emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x00F00000) >> 4;
+		emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x000F0000) << 4;
+		emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x0000C0C0) >> 2;
+		emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x00003030) << 2;
+		emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x00000008) >> 1;
+		emi_set->CHN0_EMI_CONA_VAL |= (temp & 0x00000004) << 1;
+
+		temp = emi_set->CHN1_EMI_CONA_VAL;
+		emi_set->CHN1_EMI_CONA_VAL &= ~(0x00FFF0FC);
+		emi_set->CHN1_EMI_CONA_VAL |= (temp & 0x00F00000) >> 4;
+		emi_set->CHN1_EMI_CONA_VAL |= (temp & 0x000F0000) << 4;
+		emi_set->CHN1_EMI_CONA_VAL |= (temp & 0x0000C0C0) >> 2;
+		emi_set->CHN1_EMI_CONA_VAL |= (temp & 0x00003030) << 2;
+		emi_set->CHN1_EMI_CONA_VAL |= (temp & 0x00000008) >> 1;
+		emi_set->CHN1_EMI_CONA_VAL |= (temp & 0x00000004) << 1;
+
+		emi_set->CHN0_EMI_CONA_VAL |= 0x80000000;
+		emi_set->CHN1_EMI_CONA_VAL |= 0x80000000;
+
+		temp = emi_set->DRAM_RANK_SIZE[0];
+		emi_set->DRAM_RANK_SIZE[0] = emi_set->DRAM_RANK_SIZE[1];
+		emi_set->DRAM_RANK_SIZE[1] = temp;
+
+		if (emi_set->dram_cbt_mode_extern == CBT_R0_NORMAL_R1_BYTE)
+			emi_set->dram_cbt_mode_extern = CBT_R0_BYTE_R1_NORMAL;
+		else if (emi_set->dram_cbt_mode_extern == CBT_R0_BYTE_R1_NORMAL)
+			emi_set->dram_cbt_mode_extern = CBT_R0_NORMAL_R1_BYTE;
+	}
+}
+
+void EMI_rank_swap_handle(void)
+{
+	static unsigned int handled = 0;
+	int i;
+
+	if (!handled) {
+		EMI_rank_swap_emi_setting(&g_default_emi_setting);
+		handled = 1;
+	}
+}
+#endif
+
+void mdl_setting(DRAMC_CTX_T *p)
+{
+	EMI_SETTINGS *emi_set = &g_default_emi_setting;
+
+	emi_init();
+
+	enable_infra_emi_broadcast(1);
+	//The following is MDL settings
+	set_cen_emi_cona(emi_set->EMI_CONA_VAL);
+	set_cen_emi_conf(emi_set->EMI_CONF_VAL);
+	set_cen_emi_conh(emi_set->EMI_CONH_VAL);
+
+	// CHNA and CHNB uses the same CH0 setting
+	set_chn_emi_cona(emi_set->CHN0_EMI_CONA_VAL);
+	//set_chn_emi_conc(0x4);
+	enable_infra_emi_broadcast(0);
+
+	p->vendor_id = emi_set->iLPDDR3_MODE_REG_5;
+}
+#if 0
+unsigned int check_gating_error(void)
+{
+	unsigned int ret = 0, i, phy_base, err_code = 0;
+	unsigned int misc_stberr_all, misc_stberr_rk0_r, misc_stberr_rk0_f, misc_stberr_rk1_r, misc_stberr_rk1_f;
+
+	phy_base = Channel_A_DDRPHY_AO_BASE_ADDRESS;
+
+	for (i = 0; i < CHANNEL_NUM; ++i, phy_base += 0x10000, err_code = 0) {
+		misc_stberr_all   = *(volatile unsigned int*)(phy_base + 0x1500);
+		misc_stberr_rk0_r = *(volatile unsigned int*)(phy_base + 0x1504);
+		misc_stberr_rk0_f = *(volatile unsigned int*)(phy_base + 0x1508);
+		misc_stberr_rk1_r = *(volatile unsigned int*)(phy_base + 0x150c);
+		misc_stberr_rk1_f = *(volatile unsigned int*)(phy_base + 0x1510);
+
+		if (misc_stberr_all & (1 << 16)) {
+			ret |= (1 << i);
+#ifdef LAST_DRAMC
+			if ((misc_stberr_rk0_r & 0xffff) != 0) {
+				err_code |= ERR_DRAM_GATING_RK0_R;
+			}
+			if ((misc_stberr_rk0_f & 0xffff) != 0) {
+				err_code |= ERR_DRAM_GATING_RK0_F;
+			}
+			if ((misc_stberr_rk1_r & 0xffff) != 0) {
+				err_code |= ERR_DRAM_GATING_RK1_R;
+			}
+			if ((misc_stberr_rk1_f & 0xffff) != 0) {
+				err_code |= ERR_DRAM_GATING_RK1_F;
+			}
+			dram_fatal_set_gating_err(i, err_code);
+			dram_fatal_set_stberr(i, 0, (misc_stberr_rk0_r & 0xffff) | ((misc_stberr_rk0_f & 0xffff) << 16));
+			dram_fatal_set_stberr(i, 1, (misc_stberr_rk1_r & 0xffff) | ((misc_stberr_rk1_f & 0xffff) << 16));
+		} else {
+			dram_fatal_set_gating_err(i, 0);
+			dram_fatal_set_stberr(i, 0, 0);
+			dram_fatal_set_stberr(i, 1, 0);
+#endif
+		}
+	}
+
+	return ret;
+}
+#endif
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+void print_DBG_info(DRAMC_CTX_T *p)
+{
+#ifndef OLYMPUS_TO_BE_PORTING
+    //unsigned int addr = 0x0;
+    //U32 u4value;
+
+#ifdef DDR_INIT_TIME_PROFILING
+    return;
+#endif
+
+    mcSHOW_DBG_MSG(("EMI_CONA=%x\n", get_cen_emi_cona()));
+
+    //RISCReadAll();
+#endif
+}
+#endif
+
+int mt_get_dram_type(void)
+{
+	unsigned int dtype = mt_get_dram_type_from_hw_trap();
+
+	if (dtype == TYPE_LPDDR4X)
+		return DTYPE_LPDDR4X;
+	else
+		DRAMC_ASSERT(0);
+
+	return 0;
+}
+
+int mt_get_freq_setting(DRAMC_CTX_T *p)
+{
+    return p->frequency;
+}
+
+#ifdef DDR_RESERVE_MODE
+extern u32 g_ddr_reserve_enable;
+extern u32 g_ddr_reserve_success;
+#define TIMEOUT 3
+extern void before_Dramc_DDR_Reserved_Mode_setting(void);
+
+#define	CHAN_DRAMC_NAO_MISC_STATUSA(base)	(base + 0x80)
+#define SREF_STATE				(1 << 16)
+
+static unsigned int is_dramc_exit_slf(void)
+{
+	unsigned int ret;
+
+	ret = *(volatile unsigned *)CHAN_DRAMC_NAO_MISC_STATUSA(Channel_A_DRAMC_NAO_BASE_ADDRESS);
+	if ((ret & SREF_STATE) != 0) {
+		dramc_crit("DRAM CHAN-A is in self-refresh (MISC_STATUSA = 0x%x)\n", ret);
+		return 0;
+	}
+
+	ret = *(volatile unsigned *)CHAN_DRAMC_NAO_MISC_STATUSA(Channel_B_DRAMC_NAO_BASE_ADDRESS);
+	if ((ret & SREF_STATE) != 0) {
+		dramc_crit("DRAM CHAN-B is in self-refresh (MISC_STATUSA = 0x%x)\n", ret);
+		return 0;
+	}
+
+#if CHANNEL_NUM > 2
+    if (channel_num_auxadc > 2) {
+        ret = *(volatile unsigned *)CHAN_DRAMC_NAO_MISC_STATUSA(Channel_C_DRAMC_NAO_BASE_ADDRESS);
+        if ((ret & SREF_STATE) != 0) {
+            dramc_crit("DRAM CHAN-C is in self-refresh (MISC_STATUSA = 0x%x)\n", ret);
+            return 0;
+        }
+
+        ret = *(volatile unsigned *)CHAN_DRAMC_NAO_MISC_STATUSA(Channel_D_DRAMC_NAO_BASE_ADDRESS);
+        if ((ret & SREF_STATE) != 0) {
+            dramc_crit("DRAM CHAN-D is in self-refresh (MISC_STATUSA = 0x%x)\n", ret);
+            return 0;
+        }
+    }
+#endif
+
+	dramc_crit("ALL DRAM CHAN is not in self-refresh\n");
+	return 1;
+}
+
+#endif
+
+unsigned int dramc_set_vcore_voltage(unsigned int vcore)
+{
+#ifdef MTK_PMIC_MT6359
+	return mtk_regulator_set_voltage(&reg_vcore, vcore, MAX_VCORE);
+#endif
+	return 0;
+}
+
+unsigned int dramc_get_vcore_voltage(void)
+{
+#ifdef MTK_PMIC_MT6359
+	return mtk_regulator_get_voltage(&reg_vcore);
+#else
+	return 0;
+#endif
+}
+
+unsigned int dramc_set_vmdd_voltage(unsigned int ddr_type, unsigned int vdram)
+{
+#ifdef MTK_PMIC_MT6359
+	mtk_regulator_set_voltage(&reg_vdram, vdram, MAX_VDRAM);
+#endif
+	return 0;
+}
+
+unsigned int dramc_get_vmdd_voltage(unsigned int ddr_type)
+{
+#ifdef MTK_PMIC_MT6359
+	//return mtk_regulator_get_voltage(&reg_vmdd2);
+	return mtk_regulator_get_voltage(&reg_vdram);
+#else
+	return 0;
+#endif
+}
+
+unsigned int dramc_set_vmddq_voltage(unsigned int ddr_type, unsigned int vddq)
+{
+#ifdef MTK_PMIC_MT6359
+	//mtk_regulator_set_voltage(&reg_vmddq, vddq, MAX_VDDQ);
+	mtk_regulator_set_voltage(&reg_vddq, vddq, MAX_VDDQ);
+#endif
+	return 0;
+}
+
+unsigned int dramc_get_vmddq_voltage(unsigned int ddr_type)
+{
+#ifdef MTK_PMIC_MT6359
+	//return mtk_regulator_get_voltage(&reg_vmddq);
+	return mtk_regulator_get_voltage(&reg_vddq);
+#else
+	return 0;
+#endif
+}
+
+unsigned int dramc_set_vmddr_voltage(unsigned int vmddr)
+{
+#ifdef MTK_PMIC_MT6359
+	return mtk_regulator_set_voltage(&reg_vmddr, vmddr, MAX_VMDDR);
+#endif
+	return 0;
+}
+
+unsigned int dramc_get_vmddr_voltage(void)
+{
+#ifdef MTK_PMIC_MT6359
+	return mtk_regulator_get_voltage(&reg_vmddr);
+#else
+	return 0;
+#endif
+}
+
+unsigned int dramc_set_vio18_voltage(unsigned int vio18)
+{
+#ifdef MTK_PMIC_MT6359
+	//unsigned int twist = vio18 % UNIT_VIO18_STEP / UNIT_VIO18;
+	//vio18 -= vio18 % UNIT_VIO18_STEP;
+	//pmic_config_interface(PMIC_RG_VIO18_2_VOCAL_ADDR, twist, PMIC_RG_VIO18_2_VOCAL_MASK, PMIC_RG_VIO18_2_VOCAL_SHIFT);
+	//pmic_config_interface(PMIC_RG_VM18_VOCAL_ADDR, twist, PMIC_RG_VM18_VOCAL_MASK, PMIC_RG_VM18_VOCAL_SHIFT);
+	return mtk_regulator_set_voltage(&reg_vio18, vio18, MAX_VIO18);
+#else
+	return 0;
+#endif
+}
+
+
+unsigned int dramc_get_vio18_voltage(void)
+{
+#ifdef MTK_PMIC_MT6359
+//	unsigned int twist = 0;
+	//pmic_read_interface(PMIC_RG_VIO18_2_VOCAL_ADDR, (void*)&twist, PMIC_RG_VIO18_2_VOCAL_MASK, PMIC_RG_VIO18_2_VOCAL_SHIFT);
+//	pmic_read_interface(PMIC_RG_VM18_VOCAL_ADDR, &twist, PMIC_RG_VM18_VOCAL_MASK, PMIC_RG_VM18_VOCAL_SHIFT);
+//	return mtk_regulator_get_voltage(&reg_vio18) + twist * UNIT_VIO18;
+    return mtk_regulator_get_voltage(&reg_vio18);
+#else
+	return 0;
+#endif
+}
+
+unsigned int is_discrete_lpddr4(void)
+{
+#if DRAM_AUXADC_CONFIG
+	return dram_type_auxadc;
+#else 
+	return TRUE; /* for 4ch DSC */ 
+#endif
+}
+
+unsigned int mt_get_dram_type_from_hw_trap(void)
+{
+	#if  1 //for bring up use
+		return TYPE_LPDDR4X;
+	#else
+	unsigned int trap = get_dram_type() & 0x7;
+	switch (trap) {
+		case 0:
+			return TYPE_LPDDR4X;
+		//case 1:
+		//case 2:
+		//case 3:
+		//case 4:
+		//case 5:
+		//	return TYPE_LPDDR3;
+		//case 6:
+		//	return TYPE_LPDDR4;
+		default:
+			printf("[dramc] Wrond HW Trapping.\n");
+			DRAMC_ASSERT(0);
+			break;
+	}
+	#endif
+	return 0;
+
+}
+
+void setup_dramc_voltage_by_pmic(void)
+{
+#ifdef VOLTAGE_SEL
+	int vcore;
+#endif
+#ifdef MTK_PMIC_MT6359
+	int ret;
+
+	ret = mtk_regulator_get("vio18", &reg_vio18);
+	if (ret)
+		dramc_debug("mtk_regulator_get vio18 fail\n");
+
+	ret = mtk_regulator_get("vgpu11", &reg_vcore);
+	if (ret)
+		dramc_debug("mtk_regulator_get vcore fail\n");
+
+	ret = mtk_regulator_get("VDRAM1", &reg_vdram);
+	if (ret)
+		printf("mtk_regulator_get vdram fail\n");
+
+	ret = mtk_regulator_get("VDRAM2", &reg_vddq);
+	if (ret)
+		printf("mtk_regulator_get vddq fail\n");
+
+	ret = mtk_regulator_get("VMDDR", &reg_vmddr);
+	if (ret)
+		printf("mtk_regulator_get vmddr fail\n");
+
+	mtk_regulator_set_mode(&reg_vcore, 0x1);
+	mtk_regulator_set_mode(&reg_vdram, 0x1);
+
+	#ifdef VOLTAGE_SEL
+    //dramc_set_vio18_voltage(vio18_voltage_select());
+	#else
+    //dramc_set_vio18_voltage(SEL_VIO18);
+	#endif
+#if defined(VCORE_BIN)
+	#ifdef VOLTAGE_SEL
+	vcore = vcore_voltage_select(KSHU0);
+	if (vcore)
+		dramc_set_vcore_voltage(vcore);
+	else
+	#endif
+	dramc_set_vcore_voltage(get_vcore_uv_table(0));
+#else
+	#ifdef VOLTAGE_SEL
+	dramc_set_vcore_voltage(vcore_voltage_select(KSHU0));
+	#else
+	dramc_set_vcore_voltage(SEL_PREFIX_VCORE(LP4, KSHU0));
+	#endif
+#endif
+	#ifdef VOLTAGE_SEL
+	dramc_set_vmdd_voltage(TYPE_LPDDR4, vdram_voltage_select());
+	#else
+	dramc_set_vmdd_voltage(TYPE_LPDDR4, SEL_PREFIX_VDRAM(LP4));
+	#endif
+
+	#ifdef VOLTAGE_SEL
+	dramc_set_vmddq_voltage(TYPE_LPDDR4, vddq_voltage_select());
+	#else
+	dramc_set_vmddq_voltage(TYPE_LPDDR4, SEL_PREFIX_VDDQ);
+	#endif
+
+	#ifdef VOLTAGE_SEL
+	dramc_set_vmddr_voltage(vmddr_voltage_select());
+	#else
+	dramc_set_vmddr_voltage(SEL_PREFIX_VMDDR);
+	#endif
+
+	dramc_debug("Vio18 = %d\n", dramc_get_vio18_voltage());
+	dramc_debug("Vcore = %d\n", dramc_get_vcore_voltage());
+	dramc_debug("Vdram = %d\n", dramc_get_vmdd_voltage(TYPE_LPDDR4));
+	dramc_debug("Vddq = %d\n", dramc_get_vmddq_voltage(TYPE_LPDDR4));
+	dramc_debug("vmddr = %d\n", dramc_get_vmddr_voltage());
+#endif
+}
+
+static void restore_vcore_setting(void)
+{
+#ifdef VOLTAGE_SEL
+	int vcore;
+#endif
+#ifdef MTK_PMIC_MT6359
+	int ret;
+
+	ret = mtk_regulator_get("vgpu11", &reg_vcore);
+	if (ret)
+		printf("mtk_regulator_get vcore fail\n");
+
+#if defined(VCORE_BIN)
+	#ifdef VOLTAGE_SEL
+	vcore = vcore_voltage_select(KSHU0);
+	if ((doe_get_config("dram_fix_3094_0825")) || (doe_get_config("dram_all_3094_0825")) || (doe_get_config("dram_opp0_3733_others_3094_0825")))
+			dramc_set_vcore_voltage(825000);
+	else if (doe_get_config("dram_fix_3094_0725") || (doe_get_config("dram_fix_2400_0725")) || (doe_get_config("dram_fix_1534_0725")) || (doe_get_config("dram_fix_1200_0725")) || (doe_get_config("dram_all_3094_0725")) || (doe_get_config("dram_all_1534_0725")) || (doe_get_config("dram_opp0_3094_others_1534_0725")) || (doe_get_config("dram_opp0_2400_others_1534_0725")))
+			dramc_set_vcore_voltage(725000);
+	else if ((doe_get_config("dram_fix_1200_065")) || (doe_get_config("dram_fix_800_065")))
+			dramc_set_vcore_voltage(650000);
+	else if (vcore)
+			dramc_set_vcore_voltage(vcore);
+	else
+	#endif
+	dramc_set_vcore_voltage(get_vcore_uv_table(0));
+#else
+	#ifdef VOLTAGE_SEL
+	dramc_set_vcore_voltage(vcore_voltage_select(KSHU0));
+	#else
+	dramc_set_vcore_voltage(SEL_PREFIX_VCORE(LP4, KSHU0));
+	#endif
+#endif
+
+	dramc_debug("Vcore = %d\n", dramc_get_vcore_voltage());
+#endif
+}
+#if 0
+static void restore_pmic_setting(void)
+{
+#ifdef MTK_PMIC_MT6359
+	int ret;
+
+	restore_vcore_setting();
+
+	ret = mtk_regulator_get("VDRAM1", &reg_vdram);
+	if (ret) {
+		printf("mtk_regulator_get vdram fail\n");
+		return;
+	}
+
+	ret = mtk_regulator_get("VDRAM2", &reg_vddq);
+	if (ret) {
+		printf("mtk_regulator_get vddq fail\n");
+		return;
+	}
+
+	ret = mtk_regulator_get("VMDDR", &reg_vmddr);
+	if (ret) {
+		printf("mtk_regulator_get vmddr fail\n");
+		return;
+	}
+
+	ret = mtk_regulator_get("vio18", &reg_vio18);
+	if (ret) {
+		printf("mtk_regulator_get vio18 fail\n");
+		return;
+	}
+
+#if 0 //for bring-up
+	dramc_set_vmdd_voltage(TYPE_LPDDR4, 1125000);
+	dramc_set_vmddq_voltage(TYPE_LPDDR4, 600000);
+	dramc_set_vmddr_voltage(750000);
+#else
+	#ifdef VOLTAGE_SEL
+	dramc_set_vmdd_voltage(TYPE_LPDDR4, vdram_voltage_select());
+	#else
+	dramc_set_vmdd_voltage(TYPE_LPDDR4, SEL_PREFIX_VDRAM(LP4));
+	#endif
+
+	#ifdef VOLTAGE_SEL
+	dramc_set_vmddq_voltage(TYPE_LPDDR4, vddq_voltage_select());
+	#else
+	dramc_set_vmddq_voltage(TYPE_LPDDR4, SEL_PREFIX_VDDQ);
+	#endif
+
+	#ifdef VOLTAGE_SEL
+	dramc_set_vmddr_voltage(vmddr_voltage_select());
+	#else
+	dramc_set_vmddr_voltage(SEL_PREFIX_VMDDR);
+	#endif
+
+	#ifdef VOLTAGE_SEL
+	dramc_set_vio18_voltage(vio18_voltage_select());
+	#else
+	dramc_set_vio18_voltage(SEL_VIO18);
+	#endif
+#endif
+	dramc_debug("Vdram = %d\n", dramc_get_vmdd_voltage(TYPE_LPDDR4));
+	dramc_debug("Vddq = %d\n", dramc_get_vmddq_voltage(TYPE_LPDDR4));
+	dramc_debug("vmddr = %d\n", dramc_get_vmddr_voltage());
+	dramc_debug("Vio18 = %d\n", dramc_get_vio18_voltage());
+#endif
+}
+#endif
+void switch_dramc_voltage_to_auto_mode(void)
+{
+#ifdef MTK_PMIC_MT6359
+	mtk_regulator_set_mode(&reg_vcore, 0x0);
+	mtk_regulator_set_mode(&reg_vdram, 0x0);
+#endif
+}
+
+void release_dram(void)
+{
+#ifdef DDR_RESERVE_MODE
+    int i;
+    int counter = TIMEOUT;
+
+    // scy: restore pmic setting (VCORE, VDRAM, VSRAM, VDDQ)
+    restore_pmic_setting();
+
+    drm_release_rg_dramc_conf_iso();//Release DRAMC/PHY conf ISO
+
+#if DDR_RESERVE_NEW_MODE //new modw
+    ASVA5_8_New_Mode_1();
+    Dramc_DDR_Reserved_Mode_setting();
+    drm_release_rg_dramc_iso();//Release PHY IO ISO
+    ASVA5_8_New_Mode_2();
+#else //old mode
+    Dramc_DDR_Reserved_Mode_setting();
+    ASVA5_8_CSCA_Pull_Down_EN();
+    drm_release_rg_dramc_iso();//Release PHY IO ISO
+    ASVA5_8_CSCA_Pull_Down_DIS();
+#endif
+
+    drm_release_rg_dramc_sref();//Let DRAM Leave SR
+
+    while(counter)
+    {
+        if(is_dramc_exit_slf() == 1) /* expect to exit dram-self-refresh */
+            break;
+        counter--;
+    }
+
+    if(counter == 0)
+    {
+        if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==1)
+        {
+            dramc_crit("[DDR Reserve] release dram from self-refresh FAIL!\n");
+            g_ddr_reserve_success = 0;
+        }
+    }
+    else
+    {
+         dramc_crit("[DDR Reserve] release dram from self-refresh PASS!\n");
+    }
+    Dramc_DDR_Reserved_Mode_AfterSR();
+
+#if DDR_RESERVE_NEW_MODE //new modw
+    ASVA5_8_New_Mode_3();
+#endif
+
+    //Expect to Use LPDDR3200 and PHYPLL as output, so no need to handle
+    //shuffle status since the status will be reset by system reset
+    //There is an PLLL_SHU_GP in SPM which will reset by system reset
+
+    // setup for EMI: touch center EMI and channel EMI to enable CLK
+    dramc_crit("[DDR reserve] EMI CEN CONA: %x\n", get_cen_emi_cona());
+    dramc_crit("[DDR reserve] EMI CHN CONA: %x\n", get_chn_emi_cona());
+    for (i=0;i<10;i++);
+
+    return;
+#endif
+}
+
+unsigned int DRAM_MRR(int MRR_num)
+{
+    u16 MRR_value = 0x0;
+    DRAMC_CTX_T *p = psCurrDramCtx;
+
+    DramcModeRegRead(p, MRR_num, &MRR_value);
+    return MRR_value;
+}
+
+static int mt_get_dram_type_for_dis(void)
+{
+    return TYPE_LPDDR4X;
+}
+
+#ifdef DRAM_QVL_CHECK
+static int check_qvl(DRAM_INFO_BY_MRR_T *dram_info, unsigned int dram_type)
+{
+	unsigned int mr5;
+	unsigned long long rank_size[2];
+	char id[22];
+	int emmc_nand_id_len=16;
+	int fw_id_len;
+	int result;
+	int i;
+
+	mr5 = dram_info->u2MR5VendorID & 0xFF;
+
+	rank_size[0] = dram_info->u8MR8Density[0]; //now only K CHA to save time
+	rank_size[1] = dram_info->u8MR8Density[1]; //now only K CHA to save time
+
+        result = platform_get_mcp_id(id, emmc_nand_id_len,&fw_id_len);
+	for (i = 0; i < num_of_emi_records; i++) {
+		dramc_crit("[DRAMC] %s(%d),%s(%x),%s(%x),%s(0x%llx),%s(0x%llx)\n",
+			"qvl", i,
+			"type", qvl_list[i].type,
+			"mr5", qvl_list[i].iLPDDR3_MODE_REG_5,
+			"rank0_size", qvl_list[i].DRAM_RANK_SIZE[0], //DA need  (unsigned int) (qvl_list[i].DRAM_RANK_SIZE[0] & 0xFFFFFFFF), (unsigned int)(qvl_list[i].DRAM_RANK_SIZE[0] >> 32),
+			"rank1_size", qvl_list[i].DRAM_RANK_SIZE[1]);//DA need (unsigned int) (qvl_list[i].DRAM_RANK_SIZE[1] & 0xFFFFFFFF), (unsigned int)(qvl_list[i].DRAM_RANK_SIZE[1] >> 32));
+		/* check DRAM type */
+		if ((qvl_list[i].type & 0xF) != (dram_type & 0xF))
+			continue;
+
+		/* check MR5 */
+		if (qvl_list[i].iLPDDR3_MODE_REG_5 != mr5)
+			continue;
+
+		/* check rank size */
+		if (qvl_list[i].DRAM_RANK_SIZE[0] != rank_size[0])
+			continue;
+		if (qvl_list[i].DRAM_RANK_SIZE[1] != rank_size[1])
+			continue;
+
+		/* check storage ID if MCP */
+		if (qvl_list[i].type & 0xF00) {
+			if (!result) {
+				if (memcmp(id, qvl_list[i].ID, qvl_list[i].id_length)) {
+					dramc_crit("[DRAMC] storage id mismatch\n", i);
+					continue;
+				} else
+					return 0;
+			}
+		} else
+			return 0;
+	}
+
+	return -1;
+}
+#endif
+
+int get_dram_channel_support_nr(void)
+{
+    return DRAMC_MAX_CH;
+}
+
+int get_dram_channel_nr(void)
+{
+	return get_channel_nr_by_emi();
+}
+
+int get_dram_rank_nr(void)
+{
+	int cen_emi_cona;
+
+#ifdef DDR_RESERVE_MODE
+	if (g_ddr_reserve_enable==1 && g_ddr_reserve_success==1)
+		return get_rank_nr_by_emi();
+#endif
+
+#ifdef DRAM_ADAPTIVE
+	if (!auto_detect_done)
+		DRAMC_ASSERT(0);
+#endif
+
+	cen_emi_cona = g_default_emi_setting.EMI_CONA_VAL;
+
+	if ((cen_emi_cona & (1 << 17)) != 0 || //for channel 0
+	    (cen_emi_cona & (1 << 16)) != 0 )  //for channel 1
+		return 2;
+	else
+		return 1;
+}
+
+int get_dram_mr_cnt(void)
+{
+    return DRAMC_MR_CNT;
+}
+
+int get_dram_freq_cnt(void)
+{
+    return DRAMC_FREQ_CNT;
+}
+
+#if (FOR_DV_SIMULATION_USED==0)
+#if !__FLASH_TOOL_DA__ && !__ETT__
+/*
+ * setup block
+ */
+
+void get_dram_rank_size(u64 dram_rank_size[DRAMC_MAX_RK])
+{
+	int rank_nr, i;
+
+#ifdef DDR_RESERVE_MODE
+	if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==1){
+		get_rank_size_by_emi(dram_rank_size);
+		return;
+	}
+#endif
+
+#ifdef DRAM_ADAPTIVE
+	if (!auto_detect_done)
+		DRAMC_ASSERT(0);
+#endif
+
+	rank_nr = get_dram_rank_nr();
+
+	for(i = 0; i < rank_nr; i++) {
+		dram_rank_size[i] = g_default_emi_setting.DRAM_RANK_SIZE[i];
+		if (channel_num_auxadc > 2)
+			dram_rank_size[i] = dram_rank_size[i] << 1;
+		dramc_debug("%d:dram_rank_size:%llx\n",i,dram_rank_size[i]);
+	}
+}
+
+void get_dram_freq_step(u32 dram_freq_step[])
+{
+	unsigned int i;
+	unsigned int defined_step[DRAMC_FREQ_CNT] = {
+		4266, 3200, 2400, 1866, 1600, 1200, 800};
+
+	for (i = 0; i < DRAMC_FREQ_CNT; i++) {
+		dram_freq_step[i] = defined_step[i];
+	}
+}
+
+void set_dram_mr(unsigned int index, unsigned short value)
+{
+#if 0
+	unsigned short value_2rk;
+
+	value_2rk = value & 0xFF;
+	value_2rk |= (value_2rk << 8);
+
+	switch (index) {
+	case 5:
+		mr5 = value_2rk;
+		break;
+	case 6:
+		mr6 = value_2rk;
+		break;
+	case 7:
+		mr7 = value_2rk;
+		break;
+	case 8:
+		mr8 = value;
+	default:
+		break;
+	}
+#endif
+}
+
+unsigned short get_dram_mr(unsigned int index)
+{
+	unsigned int value = 0;
+#if 0
+	switch (index) {
+	case 5:
+		value = last_dramc_info_ptr->mr5;
+		break;
+	case 6:
+		value = last_dramc_info_ptr->mr6;
+		break;
+	case 7:
+		value = last_dramc_info_ptr->mr7;
+		break;
+	case 8:
+		value = last_dramc_info_ptr->mr8;
+	default:
+		break;
+	}
+	return (unsigned short)(value & 0xFFFF);
+#else
+	return (unsigned short)(value & 0xFFFF);
+#endif
+}
+
+void get_dram_mr_info(struct mr_info_t mr_info[])
+{
+#if 0
+	unsigned int i;
+	unsigned int mr_list[DRAMC_MR_CNT] = {5, 6, 7, 8};
+
+	for (i = 0; i < DRAMC_MR_CNT; i++) {
+		mr_info[i].mr_index = mr_list[i];
+		mr_info[i].mr_value = get_dram_mr(mr_list[i]);
+	}
+#endif
+}
+
+#endif //#if !__FLASH_TOOL_DA__ && !__ETT__
+#endif
+#if 0
+void freq_table_are_all_3094(void)
+{
+   gFreqTbl[0].freq_sel = LP4_DDR3200;
+   gFreqTbl[0].divmode = DIV8_MODE;
+   gFreqTbl[0].SRAMIdx= SRAM_SHU1;
+   gFreqTbl[0].duty_calibration_mode = DUTY_NEED_K;
+   gFreqTbl[0].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[0].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[1].freq_sel = LP4_DDR3200;
+   gFreqTbl[1].divmode = DIV8_MODE;
+   gFreqTbl[1].SRAMIdx = SRAM_SHU3;
+   gFreqTbl[1].duty_calibration_mode = DUTY_NEED_K;
+   gFreqTbl[1].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[1].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[2].freq_sel = LP4_DDR3200;
+   gFreqTbl[2].divmode = DIV8_MODE;
+   gFreqTbl[2].SRAMIdx = SRAM_SHU2;
+   gFreqTbl[2].duty_calibration_mode = DUTY_NEED_K;
+   gFreqTbl[2].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[2].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[3].freq_sel = LP4_DDR3200;
+   gFreqTbl[3].divmode = DIV8_MODE;
+   gFreqTbl[3].SRAMIdx = SRAM_SHU0;
+   gFreqTbl[3].duty_calibration_mode = DUTY_NEED_K;
+   gFreqTbl[3].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[3].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[4].freq_sel = LP4_DDR3200;
+   gFreqTbl[4].divmode = DIV8_MODE;
+   gFreqTbl[4].SRAMIdx = SRAM_SHU5;
+   gFreqTbl[4].duty_calibration_mode = DUTY_NEED_K;
+   gFreqTbl[4].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[4].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[5].freq_sel = LP4_DDR3200;
+   gFreqTbl[5].divmode = DIV8_MODE;
+   gFreqTbl[5].SRAMIdx = SRAM_SHU4;
+   gFreqTbl[5].duty_calibration_mode = DUTY_NEED_K;
+   gFreqTbl[5].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[5].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[6].freq_sel = LP4_DDR3200;
+   gFreqTbl[6].divmode = DIV8_MODE;
+   gFreqTbl[6].SRAMIdx = SRAM_SHU6;
+   gFreqTbl[6].duty_calibration_mode = DUTY_NEED_K;
+   gFreqTbl[6].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[6].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+}
+
+void freq_table_are_all_1534(void)
+{
+   gFreqTbl[0].freq_sel = LP4_DDR1600;
+   gFreqTbl[0].divmode = DIV8_MODE;
+   gFreqTbl[0].SRAMIdx = SRAM_SHU1;
+   gFreqTbl[0].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[0].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[0].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[1].freq_sel = LP4_DDR1600;
+   gFreqTbl[1].divmode = DIV8_MODE;
+   gFreqTbl[1].SRAMIdx = SRAM_SHU3;
+   gFreqTbl[1].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[1].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[1].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[2].freq_sel = LP4_DDR1600;
+   gFreqTbl[2].divmode = DIV8_MODE;
+   gFreqTbl[2].SRAMIdx = SRAM_SHU2;
+   gFreqTbl[2].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[2].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[2].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[3].freq_sel = LP4_DDR1600;
+   gFreqTbl[3].divmode = DIV8_MODE;
+   gFreqTbl[3].SRAMIdx = SRAM_SHU0;
+   gFreqTbl[3].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[3].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[3].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[4].freq_sel = LP4_DDR1600;
+   gFreqTbl[4].divmode = DIV8_MODE;
+   gFreqTbl[4].SRAMIdx = SRAM_SHU5;
+   gFreqTbl[4].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[4].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[4].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[5].freq_sel = LP4_DDR1600;
+   gFreqTbl[5].divmode = DIV8_MODE;
+   gFreqTbl[5].SRAMIdx = SRAM_SHU4;
+   gFreqTbl[5].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[5].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[5].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[6].freq_sel = LP4_DDR1600;
+   gFreqTbl[6].divmode = DIV8_MODE;
+   gFreqTbl[6].SRAMIdx = SRAM_SHU6;
+   gFreqTbl[6].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[6].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[6].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+}
+
+void freq_table_opp0_3733_others_3094(void)
+{
+   gFreqTbl[0].freq_sel = LP4_DDR3200;
+   gFreqTbl[0].divmode = DIV8_MODE;
+   gFreqTbl[0].SRAMIdx = SRAM_SHU1;
+   gFreqTbl[0].duty_calibration_mode = DUTY_NEED_K;
+   gFreqTbl[0].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[0].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[1].freq_sel = LP4_DDR3200;
+   gFreqTbl[1].divmode = DIV8_MODE;
+   gFreqTbl[1].SRAMIdx = SRAM_SHU3;
+   gFreqTbl[1].duty_calibration_mode = DUTY_NEED_K;
+   gFreqTbl[1].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[1].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[2].freq_sel = LP4_DDR3200;
+   gFreqTbl[2].divmode = DIV8_MODE;
+   gFreqTbl[2].SRAMIdx = SRAM_SHU2;
+   gFreqTbl[2].duty_calibration_mode = DUTY_NEED_K;
+   gFreqTbl[2].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[2].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[3].freq_sel = LP4_DDR3733;
+   gFreqTbl[3].divmode = DIV8_MODE;
+   gFreqTbl[3].SRAMIdx = SRAM_SHU0;
+   gFreqTbl[3].duty_calibration_mode = DUTY_NEED_K;
+   gFreqTbl[3].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[3].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[4].freq_sel = LP4_DDR3200;
+   gFreqTbl[4].divmode = DIV8_MODE;
+   gFreqTbl[4].SRAMIdx = SRAM_SHU5;
+   gFreqTbl[4].duty_calibration_mode = DUTY_NEED_K;
+   gFreqTbl[4].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[4].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[5].freq_sel = LP4_DDR3200;
+   gFreqTbl[5].divmode = DIV8_MODE;
+   gFreqTbl[5].SRAMIdx = SRAM_SHU4;
+   gFreqTbl[5].duty_calibration_mode = DUTY_NEED_K;
+   gFreqTbl[5].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[5].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[6].freq_sel = LP4_DDR3200;
+   gFreqTbl[6].divmode = DIV8_MODE;
+   gFreqTbl[6].SRAMIdx = SRAM_SHU6;
+   gFreqTbl[6].duty_calibration_mode = DUTY_NEED_K;
+   gFreqTbl[6].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[6].ddr_loop_mode = CLOSE_LOOP_MODE;
+}
+
+void freq_table_opp0_3094_others_1534(void)
+{
+   gFreqTbl[0].freq_sel = LP4_DDR1600;
+   gFreqTbl[0].divmode = DIV8_MODE;
+   gFreqTbl[0].SRAMIdx = SRAM_SHU1;
+   gFreqTbl[0].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[0].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[0].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[1].freq_sel = LP4_DDR1600;
+   gFreqTbl[1].divmode = DIV8_MODE;
+   gFreqTbl[1].SRAMIdx = SRAM_SHU3;
+   gFreqTbl[1].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[1].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[1].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[2].freq_sel = LP4_DDR1600;
+   gFreqTbl[2].divmode = DIV8_MODE;
+   gFreqTbl[2].SRAMIdx = SRAM_SHU2;
+   gFreqTbl[2].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[2].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[2].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[3].freq_sel = LP4_DDR3200;
+   gFreqTbl[3].divmode = DIV8_MODE;
+   gFreqTbl[3].SRAMIdx = SRAM_SHU0;
+   gFreqTbl[3].duty_calibration_mode = DUTY_NEED_K;
+   gFreqTbl[3].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[3].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[4].freq_sel = LP4_DDR1600;
+   gFreqTbl[4].divmode = DIV8_MODE;
+   gFreqTbl[4].SRAMIdx = SRAM_SHU5;
+   gFreqTbl[4].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[4].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[4].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[5].freq_sel = LP4_DDR1600;
+   gFreqTbl[5].divmode = DIV8_MODE;
+   gFreqTbl[5].SRAMIdx = SRAM_SHU4;
+   gFreqTbl[5].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[5].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[5].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[6].freq_sel = LP4_DDR1600;
+   gFreqTbl[6].divmode = DIV8_MODE;
+   gFreqTbl[6].SRAMIdx = SRAM_SHU6;
+   gFreqTbl[6].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[6].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[6].ddr_loop_mode = CLOSE_LOOP_MODE;
+}
+
+void freq_table_opp0_2400_others_1534(void)
+{
+   gFreqTbl[0].freq_sel = LP4_DDR1600;
+   gFreqTbl[0].divmode = DIV8_MODE;
+   gFreqTbl[0].SRAMIdx = SRAM_SHU1;
+   gFreqTbl[0].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[0].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[0].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[1].freq_sel = LP4_DDR1600;
+   gFreqTbl[1].divmode = DIV8_MODE;
+   gFreqTbl[1].SRAMIdx = SRAM_SHU3;
+   gFreqTbl[1].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[1].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[1].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[2].freq_sel = LP4_DDR1600;
+   gFreqTbl[2].divmode = DIV8_MODE;
+   gFreqTbl[2].SRAMIdx = SRAM_SHU2;
+   gFreqTbl[2].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[2].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[2].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[3].freq_sel = LP4_DDR2400;
+   gFreqTbl[3].divmode = DIV8_MODE;
+   gFreqTbl[3].SRAMIdx = SRAM_SHU0;
+   gFreqTbl[3].duty_calibration_mode = DUTY_NEED_K;
+   gFreqTbl[3].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[3].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[4].freq_sel = LP4_DDR1600;
+   gFreqTbl[4].divmode = DIV8_MODE;
+   gFreqTbl[4].SRAMIdx = SRAM_SHU5;
+   gFreqTbl[4].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[4].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[4].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[5].freq_sel = LP4_DDR1600;
+   gFreqTbl[5].divmode = DIV8_MODE;
+   gFreqTbl[5].SRAMIdx = SRAM_SHU4;
+   gFreqTbl[5].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[5].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[5].ddr_loop_mode = CLOSE_LOOP_MODE;
+
+   gFreqTbl[6].freq_sel = LP4_DDR1600;
+   gFreqTbl[6].divmode = DIV8_MODE;
+   gFreqTbl[6].SRAMIdx = SRAM_SHU6;
+   gFreqTbl[6].duty_calibration_mode = DUTY_DEFAULT;
+   gFreqTbl[6].vref_calibartion_enable = VREF_CALI_ON;
+   gFreqTbl[6].ddr_loop_mode = CLOSE_LOOP_MODE;
+}
+#endif
+
+#if (CFG_DRAM_LOG_TO_STORAGE)
+#include <blkdev.h>
+#include <partition.h>
+#include <storage_api.h>
+
+extern u64 get_part_addr(const char *name);
+u64 part_dram_data_addr_uart = 0;
+u32 log_start = 0;
+static char logbuf[1024];
+static int logcount;
+#endif
+
+#ifdef VOLTAGE_SEL
+void update_voltage_select_info(void)
+{
+	voltage_sel_info_ptr.vcore = doe_get_config("vcore");
+	voltage_sel_info_ptr.vdram = doe_get_config("vdram");
+	voltage_sel_info_ptr.vddq = doe_get_config("vddq");
+	voltage_sel_info_ptr.vmddr = doe_get_config("vmddr");
+	voltage_sel_info_ptr.vio18 = doe_get_config("vio18");
+
+	print("DOE setting: vcore %d, vdram %d, vddq %d, vmddr %d, vio18 %d \n",
+		voltage_sel_info_ptr.vcore, voltage_sel_info_ptr.vdram,
+		voltage_sel_info_ptr.vddq, voltage_sel_info_ptr.vmddr,
+		voltage_sel_info_ptr.vio18);
+}
+
+int vio18_voltage_select()
+{
+	if (voltage_sel_info_ptr.vio18 == LEVEL_LV) {
+		return HQA_VIO18_LV;
+	} else if (voltage_sel_info_ptr.vio18 == LEVEL_HV) {
+		return HQA_VIO18_HV;
+	} else {
+		return HQA_VIO18_NV;
+	}
+}
+
+int vmddr_voltage_select()
+{
+	if (voltage_sel_info_ptr.vmddr == LEVEL_LV) {
+		return HQA_VMDDR_LV_LP4;
+	} else if (voltage_sel_info_ptr.vmddr == LEVEL_HV) {
+		return HQA_VMDDR_HV_LP4;
+	} else {
+		return HQA_VMDDR_NV_LP4;
+	}
+}
+
+int vddq_voltage_select()
+{
+	if (voltage_sel_info_ptr.vddq == LEVEL_LV) {
+		return HQA_VDDQ_LV_LP4;
+	} else if (voltage_sel_info_ptr.vddq == LEVEL_HV) {
+		return HQA_VDDQ_HV_LP4;
+	} else {
+		return HQA_VDDQ_NV_LP4;
+	}
+}
+
+int vdram_voltage_select(void)
+{
+	if (voltage_sel_info_ptr.vdram == LEVEL_LV) {
+		return HQA_VDRAM_LV_LP4;
+	} else if (voltage_sel_info_ptr.vdram == LEVEL_HV) {
+		return HQA_VDRAM_HV_LP4;
+	} else {
+		return HQA_VDRAM_NV_LP4;
+	}
+}
+
+int vcore_voltage_select(DRAM_KSHU kshu)
+{
+	int ret = 0;
+	if (voltage_sel_info_ptr.vcore == LEVEL_LV) {
+		switch(kshu) {
+			case KSHU0:
+				ret = HQA_VCORE_LV_LP4_KSHU0_PL;
+				break;
+			case KSHU1:
+				ret = HQA_VCORE_LV_LP4_KSHU1_PL;
+				break;
+			case KSHU2:
+				ret = HQA_VCORE_LV_LP4_KSHU2_PL;
+				break;
+			case KSHU3:
+				ret = HQA_VCORE_LV_LP4_KSHU3_PL;
+				break;
+			case KSHU4:
+				ret = HQA_VCORE_LV_LP4_KSHU4_PL;
+				break;
+			case KSHU5:
+				ret = HQA_VCORE_LV_LP4_KSHU5_PL;
+				break;
+			case KSHU6:
+				ret = HQA_VCORE_LV_LP4_KSHU6_PL;
+				break;
+		};
+	} else if (voltage_sel_info_ptr.vcore == LEVEL_HV) {
+		switch(kshu) {
+			case KSHU0:
+				ret = HQA_VCORE_HV_LP4_KSHU0_PL;
+				break;
+			case KSHU1:
+				ret = HQA_VCORE_HV_LP4_KSHU1_PL;
+				break;
+			case KSHU2:
+				ret = HQA_VCORE_HV_LP4_KSHU2_PL;
+				break;
+			case KSHU3:
+				ret = HQA_VCORE_HV_LP4_KSHU3_PL;
+				break;
+			case KSHU4:
+				ret = HQA_VCORE_HV_LP4_KSHU4_PL;
+				break;
+			case KSHU5:
+				ret = HQA_VCORE_HV_LP4_KSHU5_PL;
+				break;
+			case KSHU6:
+				ret = HQA_VCORE_HV_LP4_KSHU6_PL;
+				break;
+		};
+	} else {
+#if defined(VCORE_BIN)
+		ret = 0;
+#else
+		switch(kshu) {
+			case KSHU0:
+				ret = HQA_VCORE_NV_LP4_KSHU0_PL;
+				break;
+			case KSHU1:
+				ret = HQA_VCORE_NV_LP4_KSHU1_PL;
+				break;
+			case KSHU2:
+				ret = HQA_VCORE_NV_LP4_KSHU2_PL;
+				break;
+			case KSHU3:
+				ret = HQA_VCORE_NV_LP4_KSHU3_PL;
+				break;
+			case KSHU4:
+				ret = HQA_VCORE_NV_LP4_KSHU4_PL;
+				break;
+			case KSHU5:
+				ret = HQA_VCORE_NV_LP4_KSHU5_PL;
+				break;
+			case KSHU6:
+				ret = HQA_VCORE_NV_LP4_KSHU6_PL;
+				break;
+		};
+#endif
+	}
+
+	return ret;
+}
+
+#endif
+
+#ifdef DRAM_ADAPTIVE
+static int update_dram_setting(EMI_SETTINGS *default_emi_setting, unsigned int dram_type, DRAM_INFO_BY_MRR_T *dram_info)
+{
+	default_emi_setting->type = dram_type;
+
+	if (dram_info != NULL) {
+		default_emi_setting->DRAM_RANK_SIZE[0] = (u64)dram_info->u8MR8Density[0];
+		default_emi_setting->DRAM_RANK_SIZE[1] = (u64)dram_info->u8MR8Density[1];
+
+		default_emi_setting->iLPDDR3_MODE_REG_5 = dram_info->u2MR5VendorID;
+
+		if (dram_info->u4RankNum == 1) { // single rank
+			if (dram_info->u1DieNum[RANK_0] == 1)
+				default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_NORMAL;
+			else if (dram_info->u1DieNum[RANK_0] == 2)
+				default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_BYTE;
+			else
+				return -1;
+		} else if (dram_info->u4RankNum == 2) { // dual rank
+			if ((dram_info->u1DieNum[RANK_0] == 1) && (dram_info->u1DieNum[RANK_1] == 1))
+				default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_NORMAL;
+			else if ((dram_info->u1DieNum[RANK_0] == 1) && (dram_info->u1DieNum[RANK_1] == 2))
+				default_emi_setting->dram_cbt_mode_extern = CBT_R0_NORMAL_R1_BYTE;
+			else if ((dram_info->u1DieNum[RANK_0] == 2) && (dram_info->u1DieNum[RANK_1] == 1))
+				default_emi_setting->dram_cbt_mode_extern = CBT_R0_BYTE_R1_NORMAL;
+			else if ((dram_info->u1DieNum[RANK_0] == 2) && (dram_info->u1DieNum[RANK_1] == 2))
+				default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_BYTE;
+			else
+				return -2;
+		} else
+			return -3;
+	} else
+		return -4;
+
+	return 0;
+}
+
+static int decode_emi_info(EMI_INFO_T *emi_info, unsigned int dram_type, DRAM_INFO_BY_MRR_T *dram_info)
+{
+	unsigned int i;
+	unsigned long long die_size;
+
+	emi_info->dram_type = dram_type;
+	emi_info->ch_num = 2; //2; //FIXME use GPIO
+	emi_info->bank_width[0] = 3;
+	emi_info->bank_width[1] = 3;
+	emi_info->col_width[0] = 10;
+	emi_info->col_width[1] = 10;
+
+	if (dram_info != NULL) {
+        emi_info->rank_size[0] = (u64)dram_info->u8MR8Density[0];
+        emi_info->rank_size[1] = (u64)dram_info->u8MR8Density[1];
+        /**
+         * die size = chn * rank_num * rank_size
+         **/
+        //emi_info->rank_size[0] /= emi_info->ch_num;
+        //emi_info->rank_size[1] /= emi_info->ch_num;
+		emi_info->rk_num = dram_info->u4RankNum;
+
+		/**
+		 * ranksize    row width
+		 *     4Gb   ->   15
+		 *     8Gb   ->   16
+		 *    16Gb   ->   17
+		 *    32Gb   ->   18
+		 **/
+		for (i = 0; i < emi_info->rk_num; i++) {
+			die_size = emi_info->rank_size[i] / dram_info->u1DieNum[i];
+
+			switch (die_size | (dram_info->u1DieNum[i] << 4) | u1IsLP4Family(dram_type)) {
+			case 0x20000011ULL: // 4Gb, x16, LP4
+			case 0x20000021ULL: // 4Gb, x8, LP4
+			case 0x40000021ULL: // 8Gb, x8, LP4
+			case 0x30000011ULL: // 6Gb, x16, LP4
+			case 0x40000011ULL: // 8Gb, x16, LP4
+				emi_info->row_width[i] = 15;
+				break;
+			case 0x30000021ULL: // 6Gb, x8, LP4
+			case 0x60000011ULL: // 12Gb, x16, LP4
+			case 0x80000011ULL: // 16Gb, x16, LP4
+				emi_info->row_width[i] = 16;
+				break;
+			case 0x060000021ULL: // 12Gb, x8, LP4
+			case 0x080000021ULL: // 16Gb, x8, LP4
+			case 0x0C0000011ULL: // 24Gb, x16, LP4
+			case 0x100000011ULL: // 32Gb, x16, LP4
+				emi_info->row_width[i] = 17;
+				break;
+			case 0x0C0000021ULL: // 24Gb, x8, LP4
+			case 0x100000021ULL: // 32Gb, x8, LP4
+				emi_info->row_width[i] = 18;
+				break;
+			default:
+				return -1;
+			}
+		}
+	} else
+		return -1;
+	return 0;
+}
+#endif
+
+#if (FOR_DV_SIMULATION_USED==0)
+void dram_auto_detection(void)
+{
+	DRAM_INFO_BY_MRR_T dram_info;
+	EMI_INFO_T emi_info;
+	DRAM_CBT_MODE_EXTERN_T dram_mode;
+	unsigned int dram_type;
+	int ret;
+	
+	dram_type = (unsigned int)mt_get_dram_type_for_dis();
+	g_default_emi_setting.type &= ~0xFF;
+	g_default_emi_setting.type |= (dram_type & 0xFF);
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+	if (!u1IsLP4Family(dram_type) ||
+		read_offline_dram_mdl_data(&dram_info) < 0) {
+#endif
+		dram_mode = (u1IsLP4Family(dram_type))?
+			CBT_BYTE_MODE1 : CBT_NORMAL_MODE;
+#if defined(SLT)
+		SLT_Test_Main_Flow(dram_type, dram_mode, &dram_info, SLT_USED);
+#endif
+		Init_DRAM(dram_type, dram_mode, &dram_info, GET_MDL_USED);
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+		if (u1IsLP4Family(dram_type))
+			write_offline_dram_mdl_data(&dram_info);
+	}
+#endif
+
+#ifdef DRAM_QVL_CHECK
+	ret = check_qvl(&dram_info, dram_type);
+	if (ret) {
+		dramc_crit("[DRAMC] check_qvl err %d\n", ret);
+		DRAMC_ASSERT(0);
+	}
+#endif
+
+	ret = update_dram_setting(&g_default_emi_setting, dram_type, &dram_info);
+    if (ret) {
+		dramc_crit("[DRAMC] update_dram_setting err %d\n", ret);
+		DRAMC_ASSERT(0);
+	}
+
+	ret = decode_emi_info(&emi_info, dram_type, &dram_info);
+	if (ret) {
+		dramc_crit("[DRAMC] decode_emi_info err %d\n", ret);
+		DRAMC_ASSERT(0);
+	}
+
+    // different files for mt6880 and 6890 (different folder)
+	ret = update_emi_setting(&g_default_emi_setting, &emi_info);
+	if (ret) {
+		dramc_crit("[DRAMC] update_emi_setting err %d\n", ret);
+		DRAMC_ASSERT(0);
+	}
+
+	auto_detect_done = 1;
+}
+
+void mt_set_emi(struct dramc_param *dparam)
+{
+	//int index;
+	/*unsigned int SW_CTRL_VC, HW_CTRL_VC;*/
+	EMI_SETTINGS *emi_set;
+	dramc_crit("[DRAMC] Dram fast K start\n");
+#ifdef VOLTAGE_SEL
+	update_voltage_select_info();
+#endif
+
+#if ENABLE_PINMUX_FOR_RANK_SWAP
+	EMI_rank_swap_handle();
+#endif
+
+	// set voltage and hw trapping before mdl
+	setup_dramc_voltage_by_pmic();
+/*
+	if ((doe_get_config("dram_all_3094_0825")) || (doe_get_config("dram_all_3094_0725")))
+		freq_table_are_all_3094();
+	else if	(doe_get_config("dram_all_1534_0725"))
+		freq_table_are_all_1534();
+	else if	(doe_get_config("dram_opp0_3733_others_3094_0825"))
+		freq_table_opp0_3733_others_3094();
+	else if	(doe_get_config("dram_opp0_3094_others_1534_0725"))
+		freq_table_opp0_3094_others_1534();
+	else if	(doe_get_config("dram_opp0_2400_others_1534_0725"))
+		freq_table_opp0_2400_others_1534();
+*/
+#if DRAM_AUXADC_CONFIG
+	get_ch_num_by_auxadc();
+#endif
+
+#ifdef DRAM_ADAPTIVE
+	dram_auto_detection();
+#endif
+	emi_set = &g_default_emi_setting;
+
+#ifdef DDR_RESERVE_MODE
+	if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==0)
+		Before_Init_DRAM_While_Reserve_Mode_fail(emi_set->type & 0xF);
+#endif
+
+#if (CFG_DRAM_LOG_TO_STORAGE)
+		log_start = 1;
+		print("log_start=0x%x part_dram_data_addr_uart=0x%llx \n",log_start,part_dram_data_addr_uart);
+#endif
+#if defined(SLT)
+    SLT_Init_DRAM((emi_set->type & 0xF), emi_set->dram_cbt_mode_extern, NULL, NORMAL_USED);
+#else
+	Init_DRAM((emi_set->type & 0xF), emi_set->dram_cbt_mode_extern, NULL, NORMAL_USED);
+#endif
+	switch_dramc_voltage_to_auto_mode();
+	restore_vcore_setting();
+
+#if (CFG_DRAM_LOG_TO_STORAGE)
+    log_start = 0;
+    print("log_start=0x%x part_dram_data_addr_uart=0x%llx \n",log_start,part_dram_data_addr_uart);
+#endif
+#if 0
+	{
+		DRAMC_CTX_T * p = psCurrDramCtx;
+		DramcRegDump(p);
+	}
+#endif
+}
+#endif
+
+#define DRAMC_ADDR_SHIFT_CHN(addr, channel) (addr + (channel * 0x10000))
+
+static void put_dummy_read_pattern(unsigned long long dst_pa, unsigned long long src_pa, unsigned int len)
+{
+	*((volatile unsigned int *)(CQ_DMA_BASE + 0x018)) = 7 << 16;
+
+	*((volatile unsigned int *)(CQ_DMA_BASE + 0x01c)) = src_pa;
+	*((volatile unsigned int *)(CQ_DMA_BASE + 0x060)) = 0;
+
+	*((volatile unsigned int *)(CQ_DMA_BASE + 0x020)) = dst_pa & 0xffffffff;
+	*((volatile unsigned int *)(CQ_DMA_BASE + 0x064)) = dst_pa >> 32;
+
+	*((volatile unsigned int *)(CQ_DMA_BASE + 0x024)) = len;
+	dsb();
+	*((volatile unsigned int *)(CQ_DMA_BASE + 0x008)) = 0x1;
+
+	while(*((volatile unsigned int *)(CQ_DMA_BASE + 0x008)));
+}
+
+unsigned int get_dramc_addr(dram_addr_t *dram_addr, unsigned int offset)
+{
+	static char init_pattern = 0;
+	unsigned int channel_num, rank_num;
+	unsigned long long dummy_read_addr;
+	unsigned long long rank_size[DRAMC_MAX_RK];
+	unsigned int index;
+	unsigned int *src_addr;
+
+	channel_num = (unsigned int) get_dram_channel_nr();
+	rank_num = (unsigned int) get_dram_rank_nr();
+	get_rank_size_by_emi(rank_size);
+	dummy_read_addr = 0x40000000;
+	src_addr = (unsigned int *) 0x40000000;
+
+	if (dram_addr->ch >= channel_num) {
+		mcSHOW_DBG_MSG(("[DRAMC] invalid channel: %d\n", dram_addr->ch));
+		return 0;
+	}
+
+	if (dram_addr->rk >= rank_num) {
+		mcSHOW_DBG_MSG(("[DRAMC] invalid rank: %d\n", dram_addr->rk));
+		return 0;
+	}
+
+	for (index = 0; index <= dram_addr->rk; index++)
+		dummy_read_addr += rank_size[index];
+	dummy_read_addr -= offset;
+	dummy_read_addr &= ~(0x300);
+
+	if (offset == 0x20) {
+		for (index = 0; index < 4; index++)
+			*(src_addr + index) = 0xAAAA5555;
+
+		if (!init_pattern) {
+			for (index = 0; index < channel_num; index++) {
+				put_dummy_read_pattern(dummy_read_addr | (index << 8),
+					(unsigned long long) src_addr, 16);
+			}
+
+			init_pattern = 1;
+		}
+	}
+
+	dram_addr->full_sys_addr = dummy_read_addr;
+	phy_addr_to_dram_addr(dram_addr, dummy_read_addr);
+
+	return dram_addr->addr;
+}
+
+unsigned int get_dummy_read_addr(dram_addr_t *dram_addr)
+{
+	return get_dramc_addr(dram_addr, 0x20); // 32-byte align for dummy RW pattern
+}
+
+static unsigned int get_ta2_addr(dram_addr_t *dram_addr)
+{
+	return (get_dramc_addr(dram_addr, 0x1000) >> 2) & 0xFFFFFFF8;
+}
+
+void init_ta2_single_channel(unsigned int channel)
+{
+	unsigned int temp;
+	dram_addr_t dram_addr;
+	DRAMC_CTX_T *p = psCurrDramCtx;
+	int test_cnt;
+
+	// disable self test engine1 and self test engine2
+	temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel)) & 0x1FFFFFFF;
+	vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel), temp);
+
+	// set rank address for test agent to auto
+	temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A4, channel)) & 0x8FFFFFFF;
+	temp |= (0x4 << 28);
+	vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A4, channel), temp);
+
+	// set test for both rank0 and rank1
+	temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel)) & 0xFFFFFFF0;
+	vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel), temp | 0x1);
+
+	// set base address for test agent to reserved space
+	dram_addr.ch = channel;
+	dram_addr.rk = 0;
+	temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_RK_TEST2_A1, channel)) & 0x00000007);
+	vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_RK_TEST2_A1, channel), temp | get_ta2_addr(&dram_addr));
+	dram_addr.rk = 1;
+	temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_RK_TEST2_A1+0x200, channel)) & 0x00000007);
+	vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_RK_TEST2_A1+0x200, channel), temp | get_ta2_addr(&dram_addr));
+
+	// set test length (offset) to 0x20
+	temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A2, channel)) & 0x0000000F) | (0x20 << 4);
+	vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A2, channel), temp);
+
+	// set TA2 pattern to the worst case
+	test_cnt = (get_dram_rank_nr() > 1) ? 1 : 0;
+	vIO32WriteFldAlign(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel), 0, TEST2_A3_TESTAUDPAT);
+	vIO32WriteFldAlign(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel), test_cnt, TEST2_A3_TESTCNT);
+	vIO32WriteFldAlign(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A4, channel), 1, TEST2_A4_TESTXTALKPAT);
+
+	return;
+}
+
+#ifdef LAST_DRAMC
+
+static unsigned int is_last_dramc_initialized(void)
+{
+	if(last_dramc_info_ptr->ta2_result_magic != LAST_DRAMC_MAGIC_PATTERN) {
+		return 0;
+	} else {
+		return 1;
+	}
+}
+
+void update_last_dramc_info(void)
+{
+	unsigned int chn;
+	unsigned long long latch_result = 0;
+	unsigned int temp;
+	unsigned int *curr;
+	DRAMC_CTX_T *p = psCurrDramCtx;
+
+	// init checksum and magic pattern
+	if(last_dramc_info_ptr->ta2_result_magic != LAST_DRAMC_MAGIC_PATTERN) {
+		last_dramc_info_ptr->ta2_result_magic = LAST_DRAMC_MAGIC_PATTERN;
+		last_dramc_info_ptr->ta2_result_last = 0;
+		last_dramc_info_ptr->ta2_result_past = 0;
+		last_dramc_info_ptr->ta2_result_checksum = LAST_DRAMC_MAGIC_PATTERN;
+		last_dramc_info_ptr->reboot_count = 0;
+		last_dramc_info_ptr->mr5 = mr5;
+		last_dramc_info_ptr->mr6 = mr6;
+		last_dramc_info_ptr->mr7 = mr7;
+		last_dramc_info_ptr->mr8 = mr8;
+	} else {
+		last_dramc_info_ptr->ta2_result_checksum ^= last_dramc_info_ptr->reboot_count;
+		last_dramc_info_ptr->reboot_count++;
+		last_dramc_info_ptr->ta2_result_checksum ^= last_dramc_info_ptr->reboot_count;
+	}
+
+	// TODO: check DCS status
+
+	// read data from latch register and reset
+	for (chn = 0; chn < CHANNEL_NUM; ++chn) {
+		//dramc_crit("[LastDRAMC] latch result before RST: %x\n", u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)));
+		latch_result = (latch_result << 16) | u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)) & 0xFFFF;
+		temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_RST, chn));
+		vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_RST, chn), temp | 0x00000001);
+		vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_RST, chn), temp & 0xFFFFFFFE);
+		//dramc_crit("[LastDRAMC] latch result after RST: %x\n", u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)));
+
+	}
+
+	last_dramc_info_ptr->ta2_result_checksum ^= last_dramc_info_ptr->ta2_result_past ^ latch_result;
+	last_dramc_info_ptr->ta2_result_past = last_dramc_info_ptr->ta2_result_last;
+	last_dramc_info_ptr->ta2_result_last = latch_result;
+	for (temp = 0; temp < sizeof(LAST_DRAMC_INFO_T) / sizeof(temp); temp++) {
+		curr = (unsigned int *)last_dramc_info_ptr + temp;
+		dramc_crit("[LastDRAMC] 0x%x: 0x%x\n", curr, *curr);
+	}
+
+	return;
+}
+
+void init_ta2_all_channel(void)
+{
+	unsigned int chn;
+
+	update_last_dramc_info();
+
+	//cache flush after update dramc info
+	#if CFG_ENABLE_DCACHE
+	plat_clean_invalidate_dcache();
+	#endif
+	// TODO: consider DCS
+	for (chn = 0; chn < CHANNEL_NUM; ++chn)
+		init_ta2_single_channel(chn);
+}
+
+
+unsigned int check_gating_err_in_dramc_latch(void)
+{
+	unsigned int chn, ret = 0;
+	DRAMC_CTX_T *p = psCurrDramCtx;
+
+	if ((g_boot_reason == BR_POWER_KEY) || (g_boot_reason == BR_USB)
+			|| mtk_wdt_is_pmic_full_reset() || (is_last_dramc_initialized() == 0)){
+		dramc_crit("for cold boot, always return 0\n");
+		return 0;
+	}
+
+	for (chn = 0; chn <= 3; ++chn) {
+		dramc_crit("[dramc] latch check in channel %d (0x%x)\n",
+				chn, u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)));
+		if (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)) & 0x4000) {
+			dramc_crit("[dramc] found gating error in channel %d (0x%x)\n",
+					chn, u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)));
+			ret |= (1 << chn);
+		}
+	}
+
+	return ret;
+}
+
+void dram_fatal_exception_detection_start(void)
+{
+	last_dramc_info_ptr = (LAST_DRAMC_INFO_T *) get_dbg_info_base(KEY_LAST_DRAMC);
+
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+	part_dram_data_addr = get_part_addr("boot_para") + 0x100000; // addr = 0x108000
+	if (part_dram_data_addr != 0x0)
+		dramc_crit("[dramc] init partition address is 0x%llx\n", part_dram_data_addr);
+	else {
+		dramc_crit("[dramc] init partition address is incorrect !!!\n");
+	}
+#endif
+
+#if defined(SLT)
+	part_dram_data_addr_slt = get_part_addr("boot_para") + 0x100000;
+#endif
+
+	if ((g_boot_reason == BR_POWER_KEY) || (g_boot_reason == BR_USB)
+			|| mtk_wdt_is_pmic_full_reset() || (is_last_dramc_initialized() == 0)){
+		/* cold boot: initialize last_dram_fatal_err_flag and dram_fatal_err_flag */
+		dramc_crit("[dramc] init SRAM region for DRAM exception detection\n");
+		last_dramc_info_ptr->last_fatal_err_flag = 0x0;
+		last_dramc_info_ptr->storage_api_err_flag = 0x0;
+		dram_fatal_init_stberr();
+	} else {
+		last_dramc_info_ptr->last_fatal_err_flag = last_dramc_info_ptr->fatal_err_flag;
+		last_dramc_info_ptr->storage_api_err_flag = 0x0;
+		dram_fatal_backup_stberr();
+		dram_fatal_init_stberr();
+	}
+
+	last_dramc_info_ptr->fatal_err_flag = 1 << OFFSET_DRAM_FATAL_ERR;
+	dsb();
+}
+
+void dram_fatal_exception_detection_end(void)
+{
+	last_dramc_info_ptr->fatal_err_flag = 0x0;
+	dsb();
+}
+
+unsigned int check_dram_fatal_exception(void)
+{
+	dramc_crit("[dramc] DRAM_FATAL_ERR_FLAG = 0x%x\n", last_dramc_info_ptr->fatal_err_flag);
+
+	return ((last_dramc_info_ptr->fatal_err_flag & ~((1 << OFFSET_DRAM_FATAL_ERR)|DDR_RSV_MODE_ERR_MASK)) != 0x0) ? 1 : 0;
+}
+
+unsigned int check_last_dram_fatal_exception(void)
+{
+	dramc_crit("[dramc] LAST_DRAM_FATAL_ERR_FLAG = 0x%x\n", last_dramc_info_ptr->last_fatal_err_flag);
+
+	return ((last_dramc_info_ptr->last_fatal_err_flag & ~(DDR_RSV_MODE_ERR_MASK)) != 0x0) ? 1 : 0;
+}
+
+void dram_fatal_set_ta2_err(unsigned int chn, unsigned int err_code)
+{
+	unsigned int shift = OFFSET_DRAM_TA2_ERR + 2 * chn, ret;
+
+	if (chn > 3)
+		return;
+
+	ret = last_dramc_info_ptr->fatal_err_flag & ~(0x7 << shift);
+	last_dramc_info_ptr->fatal_err_flag = ret | ((err_code & 0x7) << shift);
+	dsb();
+}
+
+void dram_fatal_set_gating_err(unsigned int chn, unsigned int err_code)
+{
+	unsigned int shift = OFFSET_DRAM_GATING_ERR + 4 * chn, ret;
+
+	if (chn > 3)
+		return;
+
+	ret = last_dramc_info_ptr->fatal_err_flag & ~(0xf << shift);
+	last_dramc_info_ptr->fatal_err_flag = ret | ((err_code & 0xf) << shift);
+	dsb();
+}
+
+void dram_fatal_init_stberr(void)
+{
+	last_dramc_info_ptr->gating_err[0][0] = 0x0;
+	last_dramc_info_ptr->gating_err[0][1] = 0x0;
+	last_dramc_info_ptr->gating_err[1][0] = 0x0;
+	last_dramc_info_ptr->gating_err[1][1] = 0x0;
+	last_dramc_info_ptr->gating_err[2][0] = 0x0;
+	last_dramc_info_ptr->gating_err[2][1] = 0x0;
+	last_dramc_info_ptr->gating_err[3][0] = 0x0;
+	last_dramc_info_ptr->gating_err[3][1] = 0x0;
+
+	dsb();
+}
+
+void dram_fatal_backup_stberr(void)
+{
+	last_dramc_info_ptr->last_gating_err[0][0] = last_dramc_info_ptr->gating_err[0][0];
+	last_dramc_info_ptr->last_gating_err[0][1] = last_dramc_info_ptr->gating_err[0][1];
+	last_dramc_info_ptr->last_gating_err[1][0] = last_dramc_info_ptr->gating_err[1][0];
+	last_dramc_info_ptr->last_gating_err[1][1] = last_dramc_info_ptr->gating_err[1][1];
+	last_dramc_info_ptr->last_gating_err[2][0] = last_dramc_info_ptr->gating_err[2][0];
+	last_dramc_info_ptr->last_gating_err[2][1] = last_dramc_info_ptr->gating_err[2][1];
+	last_dramc_info_ptr->last_gating_err[3][0] = last_dramc_info_ptr->gating_err[3][0];
+	last_dramc_info_ptr->last_gating_err[3][1] = last_dramc_info_ptr->gating_err[3][1];
+
+	dsb();
+}
+
+void dram_fatal_set_stberr(unsigned int chn, unsigned int rk, unsigned int err_code)
+{
+	if ((chn > 3) || (rk > 1))
+		return;
+
+	last_dramc_info_ptr->gating_err[chn][rk] = err_code;
+
+	dsb();
+}
+
+void dram_fatal_set_err(unsigned int err_code, unsigned int mask, unsigned int offset)
+{
+	unsigned int ret;
+
+	ret = last_dramc_info_ptr->fatal_err_flag & ~(mask << offset);
+	last_dramc_info_ptr->fatal_err_flag = ret | ((err_code & mask) << offset);
+	dsb();
+}
+
+#endif
+
+#if (FOR_DV_SIMULATION_USED==0) // for DV sim build pass
+int doe_get_config(const char* feature)
+{
+#if defined(ENABLE_DOE)
+	char *doe_feature = dconfig_getenv(feature);
+	int doe_result = atoi(doe_feature);
+	dramc_crit("DOE force setting %s=%d\n", feature, doe_result);
+	return doe_result;
+#elif defined(NVCORE_NVDRAM)
+	return LEVEL_NV;
+#elif defined(LVCORE_LVDRAM)
+	return LEVEL_LV;
+#elif defined(HVCORE_HVDRAM)
+	return LEVEL_HV;
+#else
+	return 0;
+#endif
+}
+#endif
+
+#if (CFG_DRAM_LOG_TO_STORAGE)
+void log_to_storage(const char c)
+{
+	int ret, clr_count;
+	blkdev_t *bootdev = NULL;
+	static u8 logen = 0;
+
+	bootdev = blkdev_get(CFG_BOOT_DEV);
+
+	if (log_start && (!logen)) {
+		logen = 1;
+		logcount = 0;
+		part_dram_data_addr_uart = get_part_addr("boot_para") + 0x100000; // addr = 0x1f300000, the first 1MB for debug
+		memset(&logbuf, 0, sizeof(logbuf));
+		for (clr_count = 0; clr_count < 3072 ; clr_count++) //3M
+			ret = blkdev_write(bootdev, (part_dram_data_addr_uart + (1024 * clr_count)), 1024, (u8*)&logbuf, storage_get_part_id(STORAGE_PHYS_PART_USER));
+	}
+
+	if (log_start) {
+//    	if (((((char) c >> 4) & 0x7) > 1) & ((((char) c >> 4) & 0x7) < 7))
+//        logbuf[logcount] = ((char) c & 0xF0) | (((char) c >> 2) & 0x03) | (((char) c << 2) & 0x0C);
+//			else
+				logbuf[logcount] = (char) c;
+    	logcount = logcount + 1;
+    	//write to storage
+    	if (logcount==1024) {
+    		logcount = 0;
+    		ret = blkdev_write(bootdev, part_dram_data_addr_uart, 1024, (u8*)&logbuf, storage_get_part_id(STORAGE_PHYS_PART_USER));
+    		part_dram_data_addr_uart = part_dram_data_addr_uart + 1024;
+    	}
+    }
+}
+#endif
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+
+#if !__ETT__
+//[FOR_CHROMEOS]
+//#include <blkdev.h>
+//#include <partition.h>
+//#include <pl_version.h>
+#else
+#include "ett_common.h"
+#include "emi.h"
+#endif
+u32 g_dram_storage_api_err_code;
+#if 0 //[FOR_CHROMEOS]
+static u16 crc16(const u8* data, u32 length){
+	u8 x;
+	u16 crc = 0xFFFF;
+
+	while (length--) {
+		x = crc >> 8 ^ *data++;
+		x ^= x >> 4;
+		crc = (crc << 8) ^ ((u8)(x << 12)) ^ ((u8)(x <<5)) ^ ((u8)x);
+	}
+	return crc;
+}
+
+static void assign_checksum_for_dram_data(DRAM_CALIBRATION_SHU_DATA_T *shu_data)
+{
+	/* need to initialize checksum to 0 before calculation */
+	shu_data->checksum = 0;
+	shu_data->checksum = crc16((u8*)shu_data, sizeof(*shu_data));
+}
+
+static int check_checksum_for_dram_data(DRAM_CALIBRATION_SHU_DATA_T *shu_data)
+{
+	u16 checksum_in_storage = shu_data->checksum;
+
+	assign_checksum_for_dram_data(shu_data);
+
+	return (shu_data->checksum == checksum_in_storage) ? 1 : 0;
+}
+
+#if !__ETT__
+static void assign_checksum_for_mdl_data(DRAM_CALIBRATION_MRR_DATA_T *mrr_info)
+{
+	/* need to initialize checksum to 0 before calculation */
+	mrr_info->checksum = 0;
+	mrr_info->checksum = crc16((u8*)mrr_info, sizeof(*mrr_info));
+}
+
+
+static int check_checksum_for_mdl_data(DRAM_CALIBRATION_MRR_DATA_T *mrr_info)
+{
+	u16 checksum_in_storage = mrr_info->checksum;
+
+	assign_checksum_for_mdl_data(mrr_info);
+
+	return (mrr_info->checksum == checksum_in_storage) ? 1 : 0;
+}
+#endif
+#endif
+static void fastk_data_dump(struct sdram_params *params, u8 shu){
+#if 0
+	print("[Full_K]Fastk data dump \n");
+	print("shuffle %d(For verify: cbt_final_vref CHA:%u, CHB: %u)\n", shu, params->cbt_final_vref[CHANNEL_A][RANK_0], params->cbt_final_vref[CHANNEL_B][RANK_0]);
+	print("shuffle %d(For verify: WL B0:%u, B1: %u)\n", shu, params->wr_level[CHANNEL_A][RANK_0][0], params->wr_level[CHANNEL_B][RANK_0][0]);
+	print("shuffle %d(For verify: tx_window_vref CHA:%u, CHB: %u)\n", shu, params->tx_window_vref[CHANNEL_A][RANK_0], params->tx_window_vref[CHANNEL_B][RANK_0]);
+	print("shuffle %d(For verify: rx_datlat CHA:%u, CHB: %u)\n", shu, params->rx_datlat[CHANNEL_A][RANK_0], params->rx_datlat[CHANNEL_B][RANK_0]);
+	print("shuffle %d(For verify: rx_datlat CHA:%u, CHB: %u)\n", shu, params->rx_datlat[CHANNEL_A][RANK_0], params->rx_datlat[CHANNEL_B][RANK_0]);
+
+	print("shuffle %d(For verify: cbt_final_vref CHC:%u, CHD: %u)\n", shu, params->cbt_final_vref[CHANNEL_C][RANK_0], params->cbt_final_vref[CHANNEL_D][RANK_0]);
+	print("shuffle %d(For verify: WL CHC:%u, CHD: %u)\n", shu, params->wr_level[CHANNEL_C][RANK_0][0], params->wr_level[CHANNEL_D][RANK_0][0]);
+	print("shuffle %d(For verify: tx_window_vref CHC:%u, CHD: %u)\n", shu, params->tx_window_vref[CHANNEL_C][RANK_0], params->tx_window_vref[CHANNEL_D][RANK_0]);
+	print("shuffle %d(For verify: rx_datlat CHC:%u, CHD: %u)\n", shu, params->rx_datlat[CHANNEL_C][RANK_0], params->rx_datlat[CHANNEL_D][RANK_0]);
+	print("shuffle %d(For verify: rx_datlat CHC:%u, CHD: %u)\n", shu, params->rx_datlat[CHANNEL_C][RANK_0], params->rx_datlat[CHANNEL_D][RANK_0]);
+	print("\n");
+#endif
+}
+static int read_offline_dram_mdl_data(DRAM_INFO_BY_MRR_T *DramInfo)
+{
+	return -1;
+}
+
+static int write_offline_dram_mdl_data(DRAM_INFO_BY_MRR_T *DramInfo)
+{
+    return -1;
+}
+int read_offline_dram_calibration_data(DRAM_DFS_SRAM_SHU_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData)
+{
+
+	struct sdram_params *params;
+
+	if (!dramc_params)
+		return -1;
+	params = &dramc_params->dramc_datas.freq_params[shuffle];
+
+	dramc_info("read calibration data from shuffle %d(For verify: WL B0:%u, B1: %u)\n",
+		   shuffle, params->wr_level[CHANNEL_A][RANK_0][0], params->wr_level[CHANNEL_B][RANK_0][0]);
+	/* copy the data stored in storage to the data structure for calibration */
+	memcpy(offLine_SaveData, params, sizeof(*offLine_SaveData));
+	fastk_data_dump(params, shuffle);
+
+	return 0;
+}
+
+int write_offline_dram_calibration_data(DRAM_DFS_SRAM_SHU_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData)
+{
+    return 0;
+}
+
+int clean_dram_calibration_data(void)
+{
+    return 0;
+}
+
+#else
+#if 0
+DRAM_CALIBRATION_DATA_T dram_data; // using global variable to avoid stack overflow
+
+static int read_offline_dram_mdl_data(DRAM_INFO_BY_MRR_T *DramInfo)
+{
+    return -1;
+}
+static int write_offline_dram_mdl_data(DRAM_INFO_BY_MRR_T *DramInfo)
+{
+   return -1;
+}
+
+int read_offline_dram_calibration_data(DRAM_DFS_SRAM_SHU_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData)
+{
+	return 0;
+}
+
+int write_offline_dram_calibration_data(DRAM_DFS_SRAM_SHU_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData)
+{
+	return 0;
+}
+
+int clean_dram_calibration_data(void)
+{
+	return;
+}
+#endif
+#endif
+
+#ifdef LAST_DRAMC
+void set_err_code_for_storage_api(void)
+{
+
+	last_dramc_info_ptr->storage_api_err_flag = g_dram_storage_api_err_code;
+	dsb();
+
+}
+#endif
+
+#if defined(SLT) && (!__ETT__)
+#include <storage_api.h>
+#include <emi.h>
+int clean_slt_data(void)
+{
+	DRAM_SLT_DATA_T data;
+	data.header.stage_status = -1;
+	data.header.pl_version = PL_VERSION;
+	return write_slt_data(&data);
+}
+
+int read_slt_data(DRAM_SLT_DATA_T *data)
+{
+	int i, ret;
+	blkdev_t *bootdev = NULL;
+
+	if (data == NULL) {
+		dramc_crit("[dramc_slt] SLT data == NULL, skip\n");
+	}
+
+	bootdev = blkdev_get(CFG_BOOT_DEV);
+	if (bootdev == NULL) {
+		dramc_crit("[dramc_slt] can't find boot device(%d)\n", CFG_BOOT_DEV);
+		return SLT_ERR_NO_DEV;
+	}
+
+	if (!part_dram_data_addr_slt) {
+		return SLT_ERR_NO_ADDR;
+	}
+
+	ret = blkdev_read(bootdev, part_dram_data_addr_slt, sizeof(DRAM_SLT_DATA_T), (u8*)data, storage_get_part_id(STORAGE_PHYS_PART_USER));
+
+	if (ret != 0) {
+		return SLT_ERR_READ_FAIL;
+	}
+
+	if (data->header.pl_version != PL_VERSION) {
+		dramc_crit("[dramc_slt] PL_VERSION mismatch\n");
+		clean_slt_data();
+		blkdev_read(bootdev, part_dram_data_addr_slt, sizeof(DRAM_SLT_DATA_T), (u8*)data, storage_get_part_id(STORAGE_PHYS_PART_USER));
+	}
+
+	return 0;
+}
+
+int write_slt_data(DRAM_SLT_DATA_T *data)
+{
+	int ret;
+	blkdev_t *bootdev = NULL;
+
+	if (data == NULL) {
+		dramc_crit("[dramc_slt] data == NULL, skip\n");
+		return SLT_ERR_NO_DATA;
+	}
+
+	bootdev = blkdev_get(CFG_BOOT_DEV);
+	if (bootdev == NULL) {
+		dramc_crit("[dramc_slt] can't find boot device(%d)\n", CFG_BOOT_DEV);
+		return SLT_ERR_NO_DEV;
+	}
+
+	if (!part_dram_data_addr_slt) {
+		return SLT_ERR_NO_ADDR;
+	}
+
+	data->header.pl_version = PL_VERSION;
+
+	ret = blkdev_write(bootdev, part_dram_data_addr_slt, sizeof(DRAM_SLT_DATA_T), (u8*)data, storage_get_part_id(STORAGE_PHYS_PART_USER));
+	if (ret != 0) {
+		dramc_crit("[dramc_slt] blkdev_write failed\n");
+		return SLT_ERR_WRITE_FAIL;
+	}
+
+	return 0;
+}
+#endif
+
+#if __FLASH_TOOL_DA__
+unsigned int get_mr8_by_mrr(U8 channel, U8 rank)
+{
+	DRAMC_CTX_T *p = psCurrDramCtx;
+	unsigned int mr8_value;
+
+	p->channel = channel;
+
+	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), rank, SWCMD_CTRL0_MRRRK);
+	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), 8, SWCMD_CTRL0_MRSMA);
+	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_MRREN);
+	while (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRR_RESPONSE) ==0)
+		mcDELAY_US(1);
+	mr8_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS), MRR_STATUS_MRR_REG);
+	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_MRREN);
+	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), 0, SWCMD_CTRL0_MRRRK);
+
+	return (mr8_value & 0xff);
+}
+#endif
+
+/* Get Channel Number from AUXADC */
+#if DRAM_AUXADC_CONFIG
+static unsigned int get_ch_num_by_auxadc(void)
+{
+    unsigned int ret = 0, voltage = 0;//, u1ch_num = 0;
+    ret = iio_read_channel_processed(5, &voltage);
+    if (ret == 0) {
+        if (voltage < 700) /* 4CH with DSC */
+        	{
+				channel_num_auxadc = CHANNEL_FOURTH;
+				dram_type_auxadc = PINMUX_DSC;
+        	}
+        else if (voltage >= 700 && voltage < 1200) /* 2CH with eMCP */
+        	{
+	    		channel_num_auxadc = CHANNEL_DUAL;
+				dram_type_auxadc = PINMUX_EMCP;
+        	}
+		else /* 2CH with DSC*/
+			{
+	    		channel_num_auxadc = CHANNEL_DUAL;
+				dram_type_auxadc = PINMUX_DSC;			
+			}
+        dramc_crit("Channel num from auxadc: %d, \n", channel_num_auxadc);
+        dramc_crit("dram_type_auxadc from auxadc: %d, \n", dram_type_auxadc);
+        dramc_crit("voltage from auxadc: %d, \n", voltage);
+   	}
+    else
+        dramc_crit("Error! Read AUXADC value fail\n");
+	
+}
+#endif
+
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c
new file mode 100644
index 000000000000..2a99e4c50dc1
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c
@@ -0,0 +1,2114 @@
+/*----------------------------------------------------------------------------*
+ * Copyright Statement:                                                       *
+ *                                                                            *
+ *   This software/firmware and related documentation ("MediaTek Software")   *
+ * are protected under international and related jurisdictions'copyright laws *
+ * as unpublished works. The information contained herein is confidential and *
+ * proprietary to MediaTek Inc. Without the prior written permission of       *
+ * MediaTek Inc., any reproduction, modification, use or disclosure of        *
+ * MediaTek Software, and information contained herein, in whole or in part,  *
+ * shall be strictly prohibited.                                              *
+ * MediaTek Inc. Copyright (C) 2010. All rights reserved.                     *
+ *                                                                            *
+ *   BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND     *
+ * AGREES TO THE FOLLOWING:                                                   *
+ *                                                                            *
+ *   1)Any and all intellectual property rights (including without            *
+ * limitation, patent, copyright, and trade secrets) in and to this           *
+ * Software/firmware and related documentation ("MediaTek Software") shall    *
+ * remain the exclusive property of MediaTek Inc. Any and all intellectual    *
+ * property rights (including without limitation, patent, copyright, and      *
+ * trade secrets) in and to any modifications and derivatives to MediaTek     *
+ * Software, whoever made, shall also remain the exclusive property of        *
+ * MediaTek Inc.  Nothing herein shall be construed as any transfer of any    *
+ * title to any intellectual property right in MediaTek Software to Receiver. *
+ *                                                                            *
+ *   2)This MediaTek Software Receiver received from MediaTek Inc. and/or its *
+ * representatives is provided to Receiver on an "AS IS" basis only.          *
+ * MediaTek Inc. expressly disclaims all warranties, expressed or implied,    *
+ * including but not limited to any implied warranties of merchantability,    *
+ * non-infringement and fitness for a particular purpose and any warranties   *
+ * arising out of course of performance, course of dealing or usage of trade. *
+ * MediaTek Inc. does not provide any warranty whatsoever with respect to the *
+ * software of any third party which may be used by, incorporated in, or      *
+ * supplied with the MediaTek Software, and Receiver agrees to look only to   *
+ * such third parties for any warranty claim relating thereto.  Receiver      *
+ * expressly acknowledges that it is Receiver's sole responsibility to obtain *
+ * from any third party all proper licenses contained in or delivered with    *
+ * MediaTek Software.  MediaTek is not responsible for any MediaTek Software  *
+ * releases made to Receiver's specifications or to conform to a particular   *
+ * standard or open forum.                                                    *
+ *                                                                            *
+ *   3)Receiver further acknowledge that Receiver may, either presently       *
+ * and/or in the future, instruct MediaTek Inc. to assist it in the           *
+ * development and the implementation, in accordance with Receiver's designs, *
+ * of certain softwares relating to Receiver's product(s) (the "Services").   *
+ * Except as may be otherwise agreed to in writing, no warranties of any      *
+ * kind, whether express or implied, are given by MediaTek Inc. with respect  *
+ * to the Services provided, and the Services are provided on an "AS IS"      *
+ * basis. Receiver further acknowledges that the Services may contain errors  *
+ * that testing is important and it is solely responsible for fully testing   *
+ * the Services and/or derivatives thereof before they are used, sublicensed  *
+ * or distributed. Should there be any third party action brought against     *
+ * MediaTek Inc. arising out of or relating to the Services, Receiver agree   *
+ * to fully indemnify and hold MediaTek Inc. harmless.  If the parties        *
+ * mutually agree to enter into or continue a business relationship or other  *
+ * arrangement, the terms and conditions set forth herein shall remain        *
+ * effective and, unless explicitly stated otherwise, shall prevail in the    *
+ * event of a conflict in the terms in any agreements entered into between    *
+ * the parties.                                                               *
+ *                                                                            *
+ *   4)Receiver's sole and exclusive remedy and MediaTek Inc.'s entire and    *
+ * cumulative liability with respect to MediaTek Software released hereunder  *
+ * will be, at MediaTek Inc.'s sole discretion, to replace or revise the      *
+ * MediaTek Software at issue.                                                *
+ *                                                                            *
+ *   5)The transaction contemplated hereunder shall be construed in           *
+ * accordance with the laws of Singapore, excluding its conflict of laws      *
+ * principles.  Any disputes, controversies or claims arising thereof and     *
+ * related thereto shall be settled via arbitration in Singapore, under the   *
+ * then current rules of the International Chamber of Commerce (ICC).  The    *
+ * arbitration shall be conducted in English. The awards of the arbitration   *
+ * shall be final and binding upon both parties and shall be entered and      *
+ * enforceable in any court of competent jurisdiction.                        *
+ *---------------------------------------------------------------------------*/
+
+//-----------------------------------------------------------------------------
+// Include files
+//-----------------------------------------------------------------------------
+#include "dramc_common.h"
+#include "dramc_int_global.h"
+#include "x_hal_io.h"
+#if (FOR_DV_SIMULATION_USED == 0)
+#include "dramc_top.h"
+#endif
+
+//-----------------------------------------------------------------------------
+// Global variables
+//-----------------------------------------------------------------------------
+
+//U8 gu1MR23Done = FALSE; /* Not used starting from Vinson (all freqs use MR23=0x3F) */
+U8 gu1MR23[CHANNEL_NUM][RANK_MAX];
+/* DQSOSCTHRD_INC & _DEC are 12 bits (Starting from Vinson) */
+U16 gu2DQSOSCTHRD_INC[CHANNEL_NUM][RANK_MAX];
+U16 gu2DQSOSCTHRD_DEC[CHANNEL_NUM][RANK_MAX];
+U16 gu2MR18[CHANNEL_NUM][RANK_MAX]; /* Stores MRR MR18 (DQS ocillator count - MSB) */
+U16 gu2MR19[CHANNEL_NUM][RANK_MAX]; /* Stores MRR MR19 (DQS ocillator count - LSB) */
+U16 gu2DQSOSC[CHANNEL_NUM][RANK_MAX]; /* Stores tDQSOSC results */
+U16 gu2DQSOscCnt[CHANNEL_NUM][RANK_MAX][2];
+
+
+void DramcDQSOSCInit(void)
+{
+    memset(gu1MR23, 0x3F, sizeof(gu1MR23)); /* MR23 should be 0x3F for all freqs (Starting from Vinson) */
+    memset(gu2DQSOSCTHRD_INC, 0x6, sizeof(gu2DQSOSCTHRD_INC));
+    memset(gu2DQSOSCTHRD_DEC, 0x4, sizeof(gu2DQSOSCTHRD_DEC));
+}
+
+#if DQSOSC_SCSM
+static DRAM_STATUS_T DramcStartDQSOSC_SCSM(DRAMC_CTX_T *p)
+{
+    U32 u4Response;
+    U32 u4TimeCnt;
+    U32 u4MRSRKBak;
+
+    u4TimeCnt = TIME_OUT_CNT;
+    mcSHOW_DBG_MSG2(("[DQSOSC]\n"));
+
+    u4MRSRKBak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), SWCMD_CTRL0_MRSRK);
+
+    //!!R_DMMRSRK(R_DMMPCRKEN=1) specify rank0 or rank1
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0, DQSOSCR_DQSOSC2RK);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1GetRank(p), SWCMD_CTRL0_MRSRK);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION), 1, MPC_OPTION_MPCRKEN);
+
+    //R_DMDQSOSCENEN, 0x1E4[10]=1 for DQSOSC Start
+    //Wait dqsoscen_response=1 (dramc_conf_nao, 0x3b8[29])
+    //R_DMDQSOSCENEN, 0x1E4[10]=0
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_DQSOSCENEN);
+
+    do
+    {
+        u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_DQSOSCEN_RESPONSE);
+        u4TimeCnt --;
+        mcDELAY_US(1);
+    } while ((u4Response == 0) && (u4TimeCnt > 0));
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_DQSOSCENEN);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u4MRSRKBak, SWCMD_CTRL0_MRSRK);
+
+    if (u4TimeCnt == 0)//time out
+    {
+        mcSHOW_ERR_MSG(("Start fail (time out)\n"));
+        return DRAM_FAIL;
+    }
+
+    return DRAM_OK;
+}
+#endif
+
+#if DQSOSC_RTSWCMD
+static DRAM_STATUS_T DramcStartDQSOSC_RTSWCMD(DRAMC_CTX_T *p)
+{
+    U32 u4Response, u4TimeCnt;
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2),
+            P_Fld(0, SWCMD_CTRL2_RTSWCMD_AGE) |
+            P_Fld(u1GetRank(p), SWCMD_CTRL2_RTSWCMD_RK));
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL),
+            1, MPC_CTRL_RTSWCMD_HPRI_EN);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT),
+            0x2a, RTSWCMD_CNT_RTSWCMD_CNT);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
+            2, SWCMD_EN_RTSWCMD_SEL);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
+            1, SWCMD_EN_RTSWCMDEN);
+
+    u4TimeCnt = TIME_OUT_CNT;
+
+    do {
+        u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3),
+                SPCMDRESP3_RTSWCMD_RESPONSE);
+        u4TimeCnt--;
+        mcDELAY_US(5);
+    } while ((u4Response == 0) && (u4TimeCnt > 0));
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
+            0, SWCMD_EN_RTSWCMDEN);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL),
+            0, MPC_CTRL_RTSWCMD_HPRI_EN);
+
+    if (u4TimeCnt == 0)//time out
+    {
+        mcSHOW_ERR_MSG(("[LP5 RT SW Cmd MRW ] Resp fail (time out)\n"));
+        return DRAM_FAIL;
+    }
+
+    return DRAM_OK;
+}
+#endif
+
+#if DQSOSC_SWCMD
+static DRAM_STATUS_T DramcStartDQSOSC_SWCMD(DRAMC_CTX_T *p)
+{
+    U32 u4Response;
+    U32 u4TimeCnt = TIME_OUT_CNT;
+    U32 u4RegBackupAddress[] = {DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)};
+
+    // Backup rank, CKE fix on/off, HW MIOCK control settings
+    DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
+
+    mcSHOW_DBG_MSG4(("[ZQCalibration]\n"));
+    //mcFPRINTF((fp_A60501, "[ZQCalibration]\n"));
+
+    // Disable HW MIOCK control to make CLK always on
+    DramCLKAlwaysOnOff(p, ON, TO_ONE_CHANNEL);
+    mcDELAY_US(1);
+
+    //if CKE2RANK=1, only need to set CKEFIXON, it will apply to both rank.
+    CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ONE_CHANNEL);
+
+    //ZQCAL Start
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_WCK2DQI_START_SWTRIG);
+
+    do
+    {
+        u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_WCK2DQI_START_SWTRIG_RESPONSE);
+        u4TimeCnt --;
+        mcDELAY_US(1);  // Wait tZQCAL(min) 1us or wait next polling
+
+        mcSHOW_DBG_MSG4(("%d- ", u4TimeCnt));
+        //mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt));
+    }while((u4Response==0) &&(u4TimeCnt>0));
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_WCK2DQI_START_SWTRIG);
+
+    if(u4TimeCnt==0)//time out
+    {
+        mcSHOW_ERR_MSG(("ZQCAL Start fail (time out)\n"));
+        //mcFPRINTF((fp_A60501, "ZQCAL Start fail (time out)\n"));
+        return DRAM_FAIL;
+    }
+
+    // Restore rank, CKE fix on, HW MIOCK control settings
+    DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
+
+    mcSHOW_DBG_MSG4(("\n[DramcZQCalibration] Done\n\n"));
+    //mcFPRINTF((fp_A60501, "\n[DramcZQCalibration] Done\n\n"));
+
+    return DRAM_OK;
+}
+#endif
+
+static DRAM_STATUS_T DramcStartDQSOSC(DRAMC_CTX_T *p)
+{
+#if DQSOSC_SCSM
+    return DramcStartDQSOSC_SCSM(p);
+#elif DQSOSC_RTSWCMD
+    return DramcStartDQSOSC_RTSWCMD(p);
+#else //DQSOSC_SWCMD
+    return DramcStartDQSOSC_SWCMD(p);
+#endif
+}
+
+DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p)
+{
+    U8 u1MR23 = gu1MR23[p->channel][p->rank];
+    U16 u2MR18, u2MR19;
+    U16 u2DQSCnt;
+    U16 u2DQSOsc[2];
+    U32 u4RegBak[2];
+
+#if MRW_CHECK_ONLY
+    mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+#endif
+
+    u4RegBak[0] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL));
+    u4RegBak[1] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL));
+
+    //LPDDR4-3200,     PI resolution = tCK/64 =9.76ps
+    //Only if MR23>=16, then error < PI resolution.
+    //Set MR23 == 0x3f, stop after 63*16 clock
+    //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), u1GetRank(p), MRS_MRSRK);
+    DramcModeRegWriteByRank(p, p->rank, 23, u1MR23);
+
+    //SW mode
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), 1, SHU_DQSOSC_SET0_DQSOSCENDIS);
+
+    // Disable HW MIOCK control to make CLK always on
+    DramCLKAlwaysOnOff(p, ON, TO_ONE_CHANNEL);
+
+    CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL);
+
+    DramcStartDQSOSC(p);
+    mcDELAY_US(1);
+
+    DramcModeRegReadByRank(p, p->rank, 18, &u2MR18);
+    DramcModeRegReadByRank(p, p->rank, 19, &u2MR19);
+
+#if (SW_CHANGE_FOR_SIMULATION == 0)
+    //B0
+    u2DQSCnt = (u2MR18 & 0x00FF) | ((u2MR19 & 0x00FF) << 8);
+    if (u2DQSCnt != 0)
+        u2DQSOsc[0] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * DDRPhyGetRealFreq(p)); //tDQSOSC = 16*MR23*tCK/2*count
+    else
+        u2DQSOsc[0] = 0;
+
+    //B1
+    u2DQSCnt = (u2MR18 >> 8) | ((u2MR19 & 0xFF00));
+    if (u2DQSCnt != 0)
+        u2DQSOsc[1] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * DDRPhyGetRealFreq(p)); //tDQSOSC = 16*MR23*tCK/2*count
+    else
+        u2DQSOsc[1] = 0;
+    mcSHOW_DBG_MSG2(("[DQSOSCAuto] RK%d, (LSB)MR18= 0x%x, (MSB)MR19= 0x%x, tDQSOscB0 = %d ps tDQSOscB1 = %d ps\n", u1GetRank(p), u2MR18, u2MR19, u2DQSOsc[0], u2DQSOsc[1]));
+#endif
+
+    gu2MR18[p->channel][p->rank] = u2MR18;
+    gu2MR19[p->channel][p->rank] = u2MR19;
+    gu2DQSOSC[p->channel][p->rank] = u2DQSOsc[0];
+
+    if (u2DQSOsc[1] != 0 && u2DQSOsc[1] < u2DQSOsc[0])
+        gu2DQSOSC[p->channel][p->rank] = u2DQSOsc[1];
+
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4RegBak[0]);
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4RegBak[1]);
+
+    return DRAM_OK;
+}
+
+
+#if ENABLE_TX_TRACKING
+/* Using gu2DQSOSC results calculated from DramcDQSOSCAuto
+ * -> calculate DQSOSCTHRD_INC, DQSOSCTHRD_DEC
+ * _INC, _DEC formulas are extracted from "Verification plan of Vinson LPDDR4 HW TX Tracking" doc
+ */
+DRAM_STATUS_T DramcDQSOSCMR23(DRAMC_CTX_T *p)
+{
+#if (SW_CHANGE_FOR_SIMULATION == 0)
+    /* Preloader doesn't support floating point numbers -> Manually expand/simpify _INC, _DEC formula */
+    U8 u1MR23 = gu1MR23[p->channel][p->rank];
+    U16 u2DQSOSC = gu2DQSOSC[p->channel][p->rank];
+    U32 u4tCK = 1000000 / DDRPhyGetRealFreq(p);
+
+    if (u2DQSOSC != 0)
+    {
+        gu2DQSOSCTHRD_INC[p->channel][p->rank] = (3 * u1MR23 * u4tCK * u4tCK) / (u2DQSOSC * u2DQSOSC * 20);
+        gu2DQSOSCTHRD_DEC[p->channel][p->rank] = (u1MR23 * u4tCK * u4tCK) / (u2DQSOSC * u2DQSOSC * 10);
+    }
+
+    mcSHOW_DBG_MSG2(("CH%d_RK%d: MR19=0x%X, MR18=0x%X, DQSOSC=%d, MR23=%u, INC=%u, DEC=%u\n", p->channel, p->rank,
+                    gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank], gu2DQSOSC[p->channel][p->rank],
+                    u1MR23, gu2DQSOSCTHRD_INC[p->channel][p->rank], gu2DQSOSCTHRD_DEC[p->channel][p->rank]));
+#endif
+    return DRAM_OK;
+}
+
+
+/* Sets DQSOSC_BASE for specified rank/byte */
+DRAM_STATUS_T DramcDQSOSCSetMR18MR19(DRAMC_CTX_T *p)
+{
+    U16 u2DQSOscCnt[2];
+
+    DramcDQSOSCAuto(p);
+
+    //B0
+    gu2DQSOscCnt[p->channel][p->rank][0] = u2DQSOscCnt[0] = (gu2MR18[p->channel][p->rank] & 0x00FF) | ((gu2MR19[p->channel][p->rank] & 0x00FF) << 8);
+    //B1
+    gu2DQSOscCnt[p->channel][p->rank][1] = u2DQSOscCnt[1] = (gu2MR18[p->channel][p->rank] >> 8) | ((gu2MR19[p->channel][p->rank] & 0xFF00));
+
+    if ((p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) && (gu2DQSOscCnt[p->channel][p->rank][1] == 0))
+    {
+        gu2DQSOscCnt[p->channel][p->rank][1] = u2DQSOscCnt[1] = u2DQSOscCnt[0];
+    }
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC), P_Fld(u2DQSOscCnt[0], SHURK_DQSOSC_DQSOSC_BASE_RK0) | P_Fld(u2DQSOscCnt[1], SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
+
+    mcSHOW_DBG_MSG2(("CH%d RK%d: MR19=%X, MR18=%X\n", p->channel, p->rank, gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank]));
+    //mcDUMP_REG_MSG(("CH%d RK%d: MR19=%X, MR18=%X\n", p->channel, p->rank, gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank]));
+    return DRAM_OK;
+}
+
+DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p)
+{
+    U16 u2PRDCNT = 0x3FF, u2PRDCNTtmp = 0x3FF;
+    U8 u1PRDCNT_DIV = 4;
+    U16 u2DQSOSCENCNT = 0xFFF;
+    U8 u1FILT_PITHRD = 0;
+    U8 u1W2R_SEL = 0;
+    U8 u1RankIdx, u1RankIdxBak;
+    U8 u1DQSOSCRCNT = 0, u1IsDiv4 = 0, u1RoundUp= 0;
+
+    u1RankIdxBak = u1GetRank(p);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), 0x0, SHU_TX_SET0_DQS2DQ_FILT_PITHRD);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0x0, DQSOSCR_R_DMDQS2DQ_FILT_OPT);
+    if (p->frequency <= 400)
+    {
+        u1FILT_PITHRD = 0x5;
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+            u1W2R_SEL = 0x2;
+        else
+            u1W2R_SEL = 0x5;
+    }
+    else if (p->frequency <= 600)
+    {
+        u1FILT_PITHRD = 0x6;
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+            u1W2R_SEL = 0x2;
+        else
+            u1W2R_SEL = 0x5;
+    }
+    else if (p->frequency <= 800)
+    {
+        u1FILT_PITHRD = 0x6;
+        if (vGet_Div_Mode(p) == DIV4_MODE)
+            u1W2R_SEL = 0x2;
+        else
+            u1W2R_SEL = 0x5;
+    }
+    else if (p->frequency <= 933)
+    {
+        u1FILT_PITHRD = 0x9;
+        u1W2R_SEL = 0x2;
+    }
+    else if (p->frequency <= 1200)
+    {
+        u1FILT_PITHRD = 0xb;
+        u1W2R_SEL = 0x2;
+    }
+    else if (p->frequency <= 1333)
+    {
+        u1FILT_PITHRD = 0xc;
+        u1W2R_SEL = 0x2;
+    }
+    else if (p->frequency <= 1600)
+    {
+        u1FILT_PITHRD = 0xE;
+        u1W2R_SEL = 0x2;
+    }
+    else if (p->frequency <= 1866)
+    {
+        u1FILT_PITHRD = 0x12;
+        u1W2R_SEL = 0x2;
+    }
+    else    //4266
+    {
+        u1FILT_PITHRD = 0x17;
+        u1W2R_SEL = 0x2;
+    }
+
+    if (vGet_Div_Mode(p) == DIV4_MODE)
+    {
+        u1PRDCNT_DIV = 2;
+        u1IsDiv4 = 1;
+    }
+
+    u1DQSOSCRCNT = ((p->frequency<< u1IsDiv4))/100;
+    if ((p->frequency%100) != 0) // @Darren,  Round up for tOSCO timing (40ns)
+        u1DQSOSCRCNT++;
+
+    if (gu1MR23[p->channel][RANK_1] > gu1MR23[p->channel][RANK_0])
+        u2PRDCNTtmp = ((gu1MR23[p->channel][RANK_1]*100)/u1PRDCNT_DIV);
+    else
+        u2PRDCNTtmp = ((gu1MR23[p->channel][RANK_0]*100)/u1PRDCNT_DIV);
+
+     u2PRDCNT = (u2PRDCNTtmp + ((u1DQSOSCRCNT*100)/16))/100;
+     u1RoundUp = (u2PRDCNTtmp + ((u1DQSOSCRCNT*100)/16))%100;
+     if (u1RoundUp != 0)
+        u2PRDCNT++;
+
+    //Don't power down dram during DQS interval timer run time, (MR23[7:0] /4) + (tOSCO/MCK unit/16)
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), u2PRDCNT, SHU_DQSOSC_SET0_DQSOSC_PRDCNT); //@Darren, unit: 16MCK and tOSCO=40ns/MCK
+
+    //set tOSCO constraint to read MR18/MR19, should be > 40ns/MCK
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSCR), u1DQSOSCRCNT, SHU_DQSOSCR_DQSOSCRCNT);//@Darren, unit: MCK to meet spec. tOSCO=40ns/MCK
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), (u1FILT_PITHRD>>1), SHU_TX_SET0_DQS2DQ_FILT_PITHRD);
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), P_Fld(u1W2R_SEL, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL));
+
+    /* Starting from Vinson, DQSOSCTHRD_INC & _DEC is split into RK0 and RK1 */
+    //Rank 0/1
+    for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC_THRD), gu2DQSOSCTHRD_INC[p->channel][u1RankIdx], SHURK_DQSOSC_THRD_DQSOSCTHRD_INC);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC_THRD), gu2DQSOSCTHRD_DEC[p->channel][u1RankIdx], SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC);
+    }
+    vSetRank(p, u1RankIdxBak);
+
+    //set interval to do MPC(start DQSOSC) command, and dramc send DQSOSC start to rank0/1/2 at the same time
+    //TX tracking period unit: 3.9us
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), u2DQSOSCENCNT, SHU_DQSOSC_SET0_DQSOSCENCNT);
+
+    return DRAM_OK;
+}
+
+void DramcHwDQSOSC(DRAMC_CTX_T *p)
+{
+    DRAM_RANK_T rank_bak = u1GetRank(p);
+    DRAM_CHANNEL_T ch_bak = p->channel;
+
+    //Enable TX tracking new mode
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0), 1, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT);
+
+    //Enable Freq_RATIO update
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_TRACKING_SET0), P_Fld(1, TX_TRACKING_SET0_SHU_PRELOAD_TX_HW)
+                                            | P_Fld(0, TX_TRACKING_SET0_SHU_PRELOAD_TX_START)
+                                            | P_Fld(0, TX_TRACKING_SET0_SW_UP_TX_NOW_CASE));
+
+    //DQSOSC MPC command violation
+#if ENABLE_TMRRI_NEW_MODE
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 1, MPC_CTRL_MPC_BLOCKALE_OPT);
+#else
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 0, MPC_CTRL_MPC_BLOCKALE_OPT);
+#endif
+
+    //DQS2DQ UI/PI setting controlled by HW
+    #if ENABLE_SW_TX_TRACKING
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 1, MISC_CTRL1_R_DMARPIDQ_SW);
+    #else
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMARPIDQ_SW);
+    #if ENABLE_PA_IMPRO_FOR_TX_TRACKING
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DCM_SUB_CTRL), 1, DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING);
+    #endif
+    #endif
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_ARUIDQ_SW);
+
+    //Set dqsosc oscillator run time by MRW
+    //write RK0 MR23
+    #if 0
+    vSetRank(p, RANK_0);
+    vSetPHY2ChannelMapping(p, CHANNEL_A);
+    DramcModeRegWrite(p, 23, u1MR23);
+    vSetPHY2ChannelMapping(p, CHANNEL_B);
+    DramcModeRegWrite(p, 23, u1MR23);
+    //write RK1 MR23
+    vSetRank(p, RANK_1);
+    vSetPHY2ChannelMapping(p, CHANNEL_A);
+    DramcModeRegWrite(p, 23, u1MR23);
+    vSetPHY2ChannelMapping(p, CHANNEL_B);
+    DramcModeRegWrite(p, 23, u1MR23);
+    #endif
+
+    //Enable HW read MR18/MR19 for each rank
+    #if ENABLE_SW_TX_TRACKING
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_DQSOSCRDIS);
+    #else
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0, DQSOSCR_DQSOSCRDIS);
+    #endif
+
+    vSetRank(p, RANK_0);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC), 1, RK_DQSOSC_DQSOSCR_RK0EN);
+    if (p->support_rank_num == RANK_DUAL)
+    {
+        vSetRank(p, RANK_1);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC), 1, RK_DQSOSC_DQSOSCR_RK0EN);
+    }
+
+    //@Jouling, Update MP setting
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 1, TX_SET0_DRSCLR_RK0_EN); //Set as 1 to fix issue of RANK_SINGLE, dual rank can also be enable
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_DQSOSC_CALEN);
+
+    vSetRank(p, rank_bak);
+    vSetPHY2ChannelMapping(p, ch_bak);
+}
+
+void Enable_TX_Tracking(DRAMC_CTX_T *p)
+{
+    //open loop mode and semi-open do not enable tracking
+    if (u1IsPhaseMode(p) == TRUE)
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0, 1, SHU_DQSOSC_SET0_DQSOSCENDIS);
+    }
+    else
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0, 0, SHU_DQSOSC_SET0_DQSOSCENDIS);
+    }
+}
+#endif
+
+#if RDSEL_TRACKING_EN
+void Enable_RDSEL_Tracking(DRAMC_CTX_T *p, U16 u2Freq)
+{
+    //Only enable at DDR4266
+    if (u2Freq >= RDSEL_TRACKING_TH) //add if(u1ShuffleIdx==DRAM_DFS_SRAM_MAX) to avoid enable tx-tracking when running DDR800 as RG-SHU0
+    {
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, 0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN);
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN)
+                                                                         | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK));
+    }
+    else
+    {
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, 0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN);
+    }
+}
+#endif
+
+#ifdef HW_GATING
+void Enable_Gating_Tracking(DRAMC_CTX_T *p)
+{
+    //open loop mode and semi-open do not enable tracking
+    if (u1IsPhaseMode(p) == TRUE)
+    {
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_STBCAL,
+            P_Fld(0x0, MISC_SHU_STBCAL_STBCALEN) |
+            P_Fld(0x0, MISC_SHU_STBCAL_STB_SELPHCALEN));
+    } else {
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_STBCAL,
+            P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) |
+            P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN));
+    }
+}
+#endif
+
+#if ENABLE_PER_BANK_REFRESH
+void Enable_PerBank_Refresh(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF0, 1, SHU_CONF0_PBREFEN);
+}
+#endif
+
+void Enable_ClkTxRxLatchEn(DRAMC_CTX_T *p)
+{
+
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ13, 1, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0);
+    if (!isLP4_DSC)
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ13, 1, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1);
+    else
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD13, 1, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA);
+
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ10, 1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0);
+    if (!isLP4_DSC)
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ10, 1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1);
+    else
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10, 1, SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA);
+
+    // Set 1 to be make TX DQS/DQ/DQM PI take effect when TX OE low, for new cross rank mode.
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ2, 1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0);
+    if (!isLP4_DSC)
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ2, 1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1);
+    else
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD2, 1, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA);
+
+    // Default settings before init
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ11, 1, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ11, 1, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD11, 1, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA);
+
+    if(!isLP4_DSC)
+    {
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD10, P_Fld(0, SHU_CA_CMD10_RG_RX_ARCLK_RANK_SEL_LAT_EN_CA)\
+                                                                    | P_Fld(0, SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_RANK_SEL_LAT_EN_CA));
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD11, 0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA);
+    }
+    else
+    {
+        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ10, P_Fld(0, SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1)\
+                                                                    | P_Fld(0, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1));
+        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ11, 0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1);
+    }
+}
+
+#if ENABLE_TX_WDQS // @Darren, To avoid unexpected DQS toggle during calibration
+void Enable_TxWDQS(DRAMC_CTX_T *p)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+
+    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ13, P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0)
+                                                                | P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0)
+                                                                | P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0)
+                                                                | P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0));
+    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ13, P_Fld(!isLP4_DSC, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1)
+                                                                | P_Fld(!isLP4_DSC, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1)
+                                                                | P_Fld(!isLP4_DSC, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1)
+                                                                | P_Fld(!isLP4_DSC, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1));
+    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD13, P_Fld(isLP4_DSC, SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_EN_CA)
+                                                                | P_Fld(isLP4_DSC, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_EN_CA)
+                                                                | P_Fld(isLP4_DSC, SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_DATA_TIE_EN_CA)
+                                                                | P_Fld(isLP4_DSC, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA));
+}
+#endif
+#if 0
+static void Enable_and_Trigger_TX_Retry(DRAMC_CTX_T *p)
+{
+#if TX_RETRY_CONTROL_BY_SPM
+    vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 1, TX_RETRY_SET0_XSR_TX_RETRY_SPM_MODE);
+#else
+    vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 0, TX_RETRY_SET0_XSR_TX_RETRY_SPM_MODE);
+#endif
+    vIO32WriteFldMulti_All(DRAMC_REG_TX_RETRY_SET0, P_Fld(1, TX_RETRY_SET0_TX_RETRY_SHU_RESP_OPT)
+                                            | P_Fld(0, TX_RETRY_SET0_TX_RETRY_UPDPI_CG_OPT)
+                                            | P_Fld(1, TX_RETRY_SET0_XSR_TX_RETRY_OPT)
+                                            | P_Fld(0, TX_RETRY_SET0_XSR_TX_RETRY_EN)
+                                            | P_Fld(0, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN)); //If using SW mode, don;t have to set this field
+    //open loop mode and semi-open do not enable tracking
+    if (u1IsPhaseMode(p) == TRUE)
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0, 1, SHU_DQSOSC_SET0_DQSOSCENDIS);
+    }
+    else
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0, 0, SHU_DQSOSC_SET0_DQSOSCENDIS);
+    }
+}
+#endif
+#if ENABLE_SW_TX_TRACKING & __ETT__
+void DramcSWTxTracking(DRAMC_CTX_T *p)
+{
+    U8 u1MR4OnOff;
+    U8 rankIdx, rankBak;
+    U8 u1SRAMShuLevel = vGet_Current_SRAMIdx(p);
+    U8 u1CurrentShuLevel;
+    U16 u2MR1819_Base[RANK_MAX][2], u2MR1819_Runtime[RANK_MAX][2];
+    U16 u2DQSOSC_INC[RANK_MAX] = {6}, u2DQSOSC_DEC[RANK_MAX] = {4};
+    U8 u1AdjPI[RANK_MAX][2];
+    U8 u1OriginalPI_DQ[DRAM_DFS_SRAM_MAX][RANK_MAX][2];
+    U8 u1UpdatedPI_DQ[DRAM_DFS_SRAM_MAX][RANK_MAX][2];
+    U8 u1OriginalPI_DQM[DRAM_DFS_SRAM_MAX][RANK_MAX][2];
+    U8 u1UpdatedPI_DQM[DRAM_DFS_SRAM_MAX][RANK_MAX][2];
+    U8 u1FreqRatioTX[DRAM_DFS_SRAM_MAX];
+    U8 shuIdx, shuBak, byteIdx;
+
+    if (gAndroid_DVFS_en)
+    {
+    for (shuIdx = 0; shuIdx < DRAM_DFS_SRAM_MAX; shuIdx++)
+    {
+        DRAM_DFS_FREQUENCY_TABLE_T *pDstFreqTbl = get_FreqTbl_by_SRAMIndex(p, shuIdx);
+        if (pDstFreqTbl == NULL)
+        {
+            mcSHOW_ERR_MSG(("NULL pFreqTbl %d\n", shuIdx));
+            while (1);
+        }
+
+        if (pDstFreqTbl->freq_sel == LP4_DDR800)
+        {
+            u1FreqRatioTX[shuIdx] = 0;
+        }
+        else
+        {
+            u1FreqRatioTX[shuIdx] = ((GetFreqBySel(p, pDstFreqTbl->freq_sel)) * 8) / p->frequency;
+            mcSHOW_DBG_MSG2(("[SWTxTracking] ShuLevel=%d, Ratio[%d]=%d (%d, %d)\n", u1SRAMShuLevel, shuIdx, u1FreqRatioTX[shuIdx], GetFreqBySel(p, pDstFreqTbl->freq_sel), p->frequency));
+        }
+    }
+    }
+    else
+    {
+        u1FreqRatioTX[0] = 8;
+    }
+
+    mcSHOW_DBG_MSG2(("[SWTxTracking] channel=%d\n", p->channel));
+    rankBak = u1GetRank(p);
+    shuBak = p->ShuRGAccessIdx;
+
+    u1CurrentShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_DVFS_STATUS, DVFS_STATUS_OTHER_SHU_GP);
+
+    for (shuIdx = 0; shuIdx < DRAM_DFS_SRAM_MAX; shuIdx++)
+    {
+        if (shuIdx == u1SRAMShuLevel || !gAndroid_DVFS_en) {
+            p->ShuRGAccessIdx = u1CurrentShuLevel;
+        } else {
+            LoadShuffleSRAMtoDramc(p, shuIdx, !u1CurrentShuLevel);
+            p->ShuRGAccessIdx = !u1CurrentShuLevel;
+        }
+
+        for (rankIdx = RANK_0;rankIdx < p->support_rank_num;rankIdx++)
+        {
+            vSetRank(p, rankIdx);
+
+            u1OriginalPI_DQ[shuIdx][p->rank][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), SHURK_PI_RK0_ARPI_DQ_B0);
+            u1OriginalPI_DQ[shuIdx][p->rank][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), SHURK_PI_RK0_ARPI_DQ_B1);
+
+            u1OriginalPI_DQM[shuIdx][p->rank][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), SHURK_PI_RK0_ARPI_DQM_B0);
+            u1OriginalPI_DQM[shuIdx][p->rank][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), SHURK_PI_RK0_ARPI_DQM_B1);
+        }
+
+        if (!gAndroid_DVFS_en)
+            break;
+    }
+
+    u1MR4OnOff = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), HMR4_REFRDIS);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_REFRDIS);
+
+    p->ShuRGAccessIdx = u1CurrentShuLevel;
+
+    for (rankIdx = RANK_0;rankIdx < p->support_rank_num;rankIdx++)
+    {
+        vSetRank(p, rankIdx);
+
+        u2DQSOSC_INC[p->rank] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC_THRD), SHURK_DQSOSC_THRD_DQSOSCTHRD_INC);
+        u2DQSOSC_DEC[p->rank] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC_THRD), SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC);
+
+        u2MR1819_Base[p->rank][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC), SHURK_DQSOSC_DQSOSC_BASE_RK0);
+        u2MR1819_Base[p->rank][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC), SHURK_DQSOSC_DQSOSC_BASE_RK0_B1);
+
+        DramcDQSOSCAuto(p);
+
+        u2MR1819_Runtime[p->rank][0] = (gu2MR18[p->channel][p->rank] & 0x00FF) | ((gu2MR19[p->channel][p->rank] & 0x00FF) << 8);
+        if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1)
+        {
+            u2MR1819_Runtime[p->rank][1] = (gu2MR18[p->channel][p->rank] >> 8) | ((gu2MR19[p->channel][p->rank] & 0xFF00));
+        }
+        else
+        {
+            u2MR1819_Runtime[p->rank][1] = u2MR1819_Runtime[p->rank][0];
+        }
+
+        //INC : MR1819>base. PI-
+        //DEC : MR1819<base. PI+
+        for (byteIdx = 0; byteIdx < 2; byteIdx++)
+        {
+            U16 deltaMR1819 = 0;
+
+            if (u2MR1819_Runtime[p->rank][byteIdx] >= u2MR1819_Base[p->rank][byteIdx])
+            {
+                deltaMR1819 = u2MR1819_Runtime[p->rank][byteIdx] - u2MR1819_Base[p->rank][byteIdx];
+                u1AdjPI[rankIdx][byteIdx] = deltaMR1819 / u2DQSOSC_INC[rankIdx];
+                for (shuIdx = 0; shuIdx < DRAM_DFS_SRAM_MAX; shuIdx++)
+                {
+                    u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx] - (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]);
+                    u1UpdatedPI_DQM[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQM[shuIdx][rankIdx][byteIdx] - (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]);
+                    mcSHOW_DBG_MSG2(("SHU%u CH%d RK%d B%d, Base=%X Runtime=%X delta=%d INC=%d PI=0x%B Adj=%d newPI=0x%B\n", shuIdx, p->channel, u1GetRank(p), byteIdx
+                                , u2MR1819_Base[p->rank][byteIdx], u2MR1819_Runtime[p->rank][byteIdx], deltaMR1819, u2DQSOSC_INC[rankIdx]
+                                , u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx], (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]), u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx]));
+
+                    if (!gAndroid_DVFS_en)
+                        break;
+                }
+            }
+            else
+            {
+                deltaMR1819 = u2MR1819_Base[p->rank][byteIdx] - u2MR1819_Runtime[p->rank][byteIdx];
+                u1AdjPI[rankIdx][byteIdx] = deltaMR1819 / u2DQSOSC_DEC[rankIdx];
+                for (shuIdx = 0; shuIdx < DRAM_DFS_SRAM_MAX; shuIdx++)
+                {
+                    u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx] + (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]);
+                    u1UpdatedPI_DQM[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQM[shuIdx][rankIdx][byteIdx] + (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]);
+                    mcSHOW_DBG_MSG2(("SHU%u CH%d RK%d B%d, Base=%X Runtime=%X delta=%d DEC=%d PI=0x%B Adj=%d newPI=0x%B\n", shuIdx, p->channel, u1GetRank(p), byteIdx
+                                , u2MR1819_Base[p->rank][byteIdx], u2MR1819_Runtime[p->rank][byteIdx], deltaMR1819, u2DQSOSC_DEC[rankIdx]
+                                , u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx], (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]), u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx]));
+
+                    if (!gAndroid_DVFS_en)
+                        break;
+                }
+            }
+        }
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_TXUPDMODE);
+
+    if (gAndroid_DVFS_en)
+    {
+    p->ShuRGAccessIdx = !u1CurrentShuLevel;
+    for (shuIdx = 0; shuIdx < DRAM_DFS_SRAM_MAX; shuIdx++)
+    {
+        LoadShuffleSRAMtoDramc(p, shuIdx, !u1CurrentShuLevel);
+
+        for (rankIdx = RANK_0;rankIdx < p->support_rank_num;rankIdx++)
+        {
+            vSetRank(p, rankIdx);
+
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0),
+                    P_Fld(u1UpdatedPI_DQ[shuIdx][p->rank][0], SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+                    P_Fld(u1UpdatedPI_DQM[shuIdx][p->rank][0], SHU_R0_B0_DQ0_SW_ARPI_DQM_B0));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0),
+                    P_Fld(u1UpdatedPI_DQ[shuIdx][p->rank][1], SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+                    P_Fld(u1UpdatedPI_DQM[shuIdx][p->rank][1], SHU_R0_B1_DQ0_SW_ARPI_DQM_B1));
+        }
+
+        DramcSaveToShuffleSRAM(p, !u1CurrentShuLevel, shuIdx);
+    }
+    }
+
+    p->ShuRGAccessIdx = u1CurrentShuLevel;
+    shuIdx = (gAndroid_DVFS_en) ? u1SRAMShuLevel : 0;
+    for (rankIdx = RANK_0;rankIdx < p->support_rank_num;rankIdx++)
+    {
+        vSetRank(p, rankIdx);
+
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0),
+                P_Fld(u1UpdatedPI_DQ[shuIdx][p->rank][0], SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
+                P_Fld(u1UpdatedPI_DQM[shuIdx][p->rank][0], SHU_R0_B0_DQ0_SW_ARPI_DQM_B0));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0),
+                P_Fld(u1UpdatedPI_DQ[shuIdx][p->rank][1], SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
+                P_Fld(u1UpdatedPI_DQM[shuIdx][p->rank][1], SHU_R0_B1_DQ0_SW_ARPI_DQM_B1));
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_MANUTXUPD);
+
+    while ((u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TCMDO1LAT), TCMDO1LAT_MANUTXUPD_B0_DONE) != 1) && (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TCMDO1LAT), TCMDO1LAT_MANUTXUPD_B1_DONE) != 1))
+    {
+        mcDELAY_US(1);
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0, DQSOSCR_TXUPDMODE);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0, DQSOSCR_MANUTXUPD);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), u1MR4OnOff, HMR4_REFRDIS);
+
+    vSetRank(p, rankBak);
+    p->ShuRGAccessIdx = shuBak;
+}
+#endif
+
+
+#if ENABLE_RX_TRACKING
+void DramcRxInputDelayTrackingInit_Common(DRAMC_CTX_T *p)
+{
+    U8 ii, backup_rank;
+    U32 u4WbrBackup = GetDramcBroadcast();
+
+    backup_rank = u1GetRank(p);
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+
+    //Enable RX_FIFO macro DIV4 clock CG
+    vIO32WriteFldAlign((DDRPHY_REG_MISC_CG_CTRL1), 0xffffffff, MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL);
+
+    for (ii = RANK_0; ii < p->support_rank_num; ii++)
+    {
+        vSetRank(p, ii);
+
+        //DVS mode to RG mode
+        vIO32WriteFldAlign((DDRPHY_REG_RK_B0_RXDVS2), 0x0, RK_B0_RXDVS2_R_RK0_DVS_MODE_B0);
+        vIO32WriteFldAlign((DDRPHY_REG_RK_B1_RXDVS2), 0x0, RK_B1_RXDVS2_R_RK0_DVS_MODE_B1);
+
+        //Turn off F_DLY individual calibration option (CTO_AGENT_RDAT cannot separate DR/DF error)
+        //tracking rising and update rising/falling together
+        vIO32WriteFldAlign((DDRPHY_REG_RK_B0_RXDVS2), 0x1, RK_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0);
+        vIO32WriteFldAlign((DDRPHY_REG_RK_B1_RXDVS2), 0x1, RK_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1);
+
+        //DQ/DQM/DQS DLY MAX/MIN value under Tracking mode
+        /* DQS, DQ, DQM (DQ, DQM are tied together now) -> controlled using DQM MAX_MIN */
+
+        /* Byte 0 */
+        vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS3), P_Fld(0x0, RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0) | P_Fld(0xff, RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0));
+        vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS4), P_Fld(0x0, RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0) | P_Fld(0x1ff, RK_B0_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B0));
+
+        /* Byte 1 */
+        vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS3), P_Fld(0x0, RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1) | P_Fld(0xff, RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1));
+        vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS4), P_Fld(0x0, RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1) | P_Fld(0x1ff, RK_B1_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B1));
+
+        //Threshold for LEAD/LAG filter
+        vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS1), P_Fld(0x0, RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD) | P_Fld(0x0, RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG));
+        vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS1), P_Fld(0x0, RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD) | P_Fld(0x0, RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG));
+
+        //DQ/DQS Rx DLY adjustment for tracking mode
+        vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS2), P_Fld(0x1, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0) | P_Fld(0x1, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0));
+        vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS2), P_Fld(0x1, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1) | P_Fld(0x1, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1));
+
+        vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS2), P_Fld(0x3, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0) | P_Fld(0x3, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0));
+        vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS2), P_Fld(0x3, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1) | P_Fld(0x3, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1));
+
+    }
+    vSetRank(p, backup_rank);
+
+    //Tracking lead/lag counter >> Rx DLY adjustment fixed to 1
+    vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x0, B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0);
+    vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x0, B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1);
+
+    //DQIEN pre-state option to block update for RX ASVA  1-2
+    vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x1, B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0);
+    vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x1, B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1);
+
+    DramcBroadcastOnOff(u4WbrBackup);
+}
+#endif
+
+#if SIMULATION_RX_DVS || ENABLE_RX_TRACKING
+void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+    U8 u1DVS_Delay;
+    U8 u1DVS_En=1;
+    U32 u4WbrBackup = GetDramcBroadcast();
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+
+    //Monitor window size setting
+    //DDRPHY.SHU*_B*_DQ5.RG_RX_ARDQS0_DVS_DLY_B* (suggested value from A-PHY owner)
+//WHITNEY_TO_BE_PORTING
+#if (fcFOR_CHIP_ID == fc8195)
+    //              6400    5500    4266    3733    3200    2400    1600    1200    800
+    //UI            156p    181p    234p    268p    312p    417p    625p    833p    1250p
+    //DVS_EN        O       O       O       O       O       O       X       X       X
+    //INI           1       2       3       N=5     N=5     N=7     N=12    N=15    N=15
+    //DVS delay     O       O       O       X       X       X       X       X       X
+    //calibration
+
+    if(p->frequency >= 3200)
+    {
+        u1DVS_Delay =1;
+    }
+    else if(p->frequency >= 2250)
+    {
+        u1DVS_Delay = 2;
+    }
+    else if(p->frequency >= 2133)
+    {
+        u1DVS_Delay = 3;
+    }
+    else if(p->frequency >= 1600)
+    {
+        u1DVS_Delay =5;
+    }
+    else if(p->frequency >= 1200)
+    {
+        u1DVS_Delay =7;
+    }
+    else if(p->frequency >= 800)
+    {
+        u1DVS_Delay =12;
+        u1DVS_En =0;
+    }
+    else
+    {
+        u1DVS_Delay =15;
+        u1DVS_En =0;
+    }
+#endif
+
+#if RX_DVS_NOT_SHU_WA
+    if (isLP4_DSC)
+    {
+        //CA_CMD5_RG_RX_ARCLK_DVS_EN is not shu RG, so always enable. Fixed in IPMv2
+        u1DVS_En =1;
+    }
+#endif
+
+    //Note that DVS DLY is _DQS_ and DVS_EN is _DQ_
+    vIO32WriteFldAlign((DDRPHY_REG_SHU_B0_DQ5), u1DVS_Delay, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0);
+    if (!isLP4_DSC)
+    {
+    vIO32WriteFldAlign((DDRPHY_REG_SHU_B1_DQ5), u1DVS_Delay, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1);
+    }
+    else
+    {
+        vIO32WriteFldAlign((DDRPHY_REG_SHU_CA_CMD5), u1DVS_Delay, SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY);
+    }
+
+    /* Bian_co HW design issue: run-time PBYTE flag will lose it's function and become per-bit -> set to 0 */
+    vIO32WriteFldMulti((DDRPHY_REG_SHU_B0_DQ7), P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0)
+                                                        | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0));
+    vIO32WriteFldMulti((DDRPHY_REG_SHU_B1_DQ7), P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1)
+                                                        | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1));
+    //Note that DVS DLY is _DQS_ and DVS_EN is _DQ_
+    //Enable A-PHY DVS LEAD/LAG
+    vIO32WriteFldAlign((DDRPHY_REG_SHU_B0_DQ11), u1DVS_En, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0);
+    if (!isLP4_DSC)
+    {
+    vIO32WriteFldAlign((DDRPHY_REG_SHU_B1_DQ11), u1DVS_En, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1);
+    }
+    else
+    {
+        vIO32WriteFldAlign((DDRPHY_REG_CA_CMD5), u1DVS_En, CA_CMD5_RG_RX_ARCLK_DVS_EN);
+    }
+
+    DramcBroadcastOnOff(u4WbrBackup);
+}
+#endif
+
+#if ENABLE_RX_TRACKING
+void DramcRxInputDelayTrackingHW(DRAMC_CTX_T *p)
+{
+    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
+    DRAM_CHANNEL_T channel_bak = p->channel;
+    U8 ii, backup_rank;
+    U32 u4WbrBackup = GetDramcBroadcast();
+    DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
+
+    vSetPHY2ChannelMapping(p, CHANNEL_A);
+    backup_rank = u1GetRank(p);
+
+    //Rx DLY tracking setting (Static)
+    vIO32WriteFldMulti((DDRPHY_REG_B0_RXDVS0),
+                                           P_Fld(1, B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0) |
+                                           P_Fld(0, B0_RXDVS0_R_RX_RANKINCTL_B0) |
+                                           P_Fld(1, B0_RXDVS0_R_RX_RANKINSEL_B0));
+
+    vIO32WriteFldMulti((DDRPHY_REG_B1_RXDVS0),
+                                           P_Fld(1, B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1) |
+                                           P_Fld(0, B1_RXDVS0_R_RX_RANKINCTL_B1) |
+                                           P_Fld(1, B1_RXDVS0_R_RX_RANKINSEL_B1));
+
+    vIO32WriteFldMulti((DDRPHY_REG_B0_DQ9), P_Fld(0x1, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0) | P_Fld(0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0));
+    vIO32WriteFldMulti((DDRPHY_REG_B1_DQ9), P_Fld(!isLP4_DSC, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1) | P_Fld(0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1));
+    vIO32WriteFldMulti((DDRPHY_REG_CA_CMD9), P_Fld(isLP4_DSC, CA_CMD9_R_DMRXDVS_RDSEL_LAT_CA) | P_Fld(0, CA_CMD9_R_DMRXDVS_VALID_LAT_CA));
+
+    //Rx DLY tracking function CG enable
+    vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x1, B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0);
+    vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x1, B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1);
+
+    //Rx DLY tracking lead/lag counter enable
+    vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x1, B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0);
+    vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x1, B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1);
+
+#ifdef DPM_CONTROL_AFTERK
+    vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 3, LPIF_LOW_POWER_CFG_1_DPHY_RXDLY_TRACK_EN);
+#endif
+
+    //fra 0: origin mode (use LEAD/LAG rising tracking)     1: new mode (use LEAD/LAG rising/fall tracking, more faster)
+    vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS1), 1, B0_RXDVS1_F_LEADLAG_TRACK_B0);
+    vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS1), 1, B1_RXDVS1_F_LEADLAG_TRACK_B1);
+
+    for (ii = RANK_0; ii < p->support_rank_num; ii++)
+    {
+        vSetRank(p, ii);
+
+        //Rx DLY tracking update enable (HW mode)
+        vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS2),
+                                               P_Fld(2, RK_B0_RXDVS2_R_RK0_DVS_MODE_B0) |
+                                               P_Fld(1, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0) |
+                                               P_Fld(1, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0));
+
+        vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS2),
+                                               P_Fld(2, RK_B1_RXDVS2_R_RK0_DVS_MODE_B1) |
+                                               P_Fld(1, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1) |
+                                               P_Fld(1, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1));
+    }
+    vSetRank(p, backup_rank);
+
+    //Rx DLY tracking: "TRACK_CLR" let rx_dly reload the correct dly setting
+    vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 1, B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0);
+    vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 1, B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1);
+    vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0, B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0);
+    vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0, B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1);
+
+    DramcBroadcastOnOff(u4WbrBackup);
+}
+#endif
+
+///TODO: wait for porting +++
+#if __A60868_TO_BE_PORTING__
+#if RX_DLY_TRACK_ONLY_FOR_DEBUG
+void DramcRxDlyTrackDebug(DRAMC_CTX_T *p)
+{
+    /* indicate ROW_ADR = 2 for dummy write & read for Rx dly track debug feature, avoid pattern overwrite by MEM_TEST
+     * pattern(0xAAAA5555) locates: 0x40010000, 0x40010100, 0x80010000, 0x80010100 */
+
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK0_DUMMY_RD_ADR), P_Fld(2, RK0_DUMMY_RD_ADR_DMY_RD_RK0_ROW_ADR)
+                        | P_Fld(0, RK0_DUMMY_RD_ADR_DMY_RD_RK0_COL_ADR)
+                        | P_Fld(0, RK0_DUMMY_RD_ADR_DMY_RD_RK0_LEN));
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK1_DUMMY_RD_ADR), P_Fld(2, RK1_DUMMY_RD_ADR_DMY_RD_RK1_ROW_ADR)
+                        | P_Fld(0, RK1_DUMMY_RD_ADR_DMY_RD_RK1_COL_ADR)
+                        | P_Fld(0, RK1_DUMMY_RD_ADR_DMY_RD_RK1_LEN));
+    vIO32WriteFldAlign_All(DRAMC_REG_RK0_DUMMY_RD_BK, 0, RK0_DUMMY_RD_BK_DMY_RD_RK0_BK);
+    vIO32WriteFldAlign_All(DRAMC_REG_RK1_DUMMY_RD_BK, 0, RK1_DUMMY_RD_BK_DMY_RD_RK1_BK);
+
+    vIO32Write4B_All(DRAMC_REG_RK0_DUMMY_RD_WDATA0, 0xAAAA5555);
+    vIO32Write4B_All(DRAMC_REG_RK0_DUMMY_RD_WDATA1, 0xAAAA5555);
+    vIO32Write4B_All(DRAMC_REG_RK0_DUMMY_RD_WDATA2, 0xAAAA5555);
+    vIO32Write4B_All(DRAMC_REG_RK0_DUMMY_RD_WDATA3, 0xAAAA5555);
+    vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA0, 0xAAAA5555);
+    vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA1, 0xAAAA5555);
+    vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA2, 0xAAAA5555);
+    vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA3, 0xAAAA5555);
+
+    //disable Rx dly track debug and clear status lock
+    vIO32WriteFldMulti_All((DDRPHY_MISC_RXDVS2), P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN)
+                        | P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR)
+                        | P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN));
+
+    //trigger dummy write pattern 0xAAAA5555
+    vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DMY_WR_DBG);
+    vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x0, DUMMY_RD_DMY_WR_DBG);
+
+    // enable Rx dly track debug feature
+    vIO32WriteFldMulti_All((DDRPHY_MISC_RXDVS2), P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN)
+                        | P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR)
+                        | P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN));
+}
+
+void DramcPrintRxDlyTrackDebugStatus(DRAMC_CTX_T *p)
+{
+    U32 backup_rank, u1ChannelBak, u4value;
+    U8 u1ChannelIdx, u1ChannelMax = p->support_channel_num;//channel A/B ...
+
+    u1ChannelBak = p->channel;
+    backup_rank = u1GetRank(p);
+
+    for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
+    {
+        p->channel = u1ChannelIdx;
+
+        u4value = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_MISC_DQ_RXDLY_TRRO18));
+        //mcSHOW_DBG_MSG(("\nCH_%d DQ_RXDLY_TRRO18 = 0x\033[1;36m%x\033[m\n",u1ChannelIdx,u4value));
+        if (u4value & 1)
+        {
+            mcSHOW_DBG_MSG3(("=== CH_%d DQ_RXDLY_TRRO18 = 0x\033[1;36m%x\033[m, %s %s shu: %d\n", u1ChannelIdx, u4value,
+                        u4value & 0x2? "RK0: fail":"",u4value&0x4?"RK1: fail":"", (u4value >> 4) & 0x3));
+        }
+    }
+}
+#endif
+
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+#if (__ETT__ || CPU_RW_TEST_AFTER_K)
+void DramcPrintRXDQDQSStatus(DRAMC_CTX_T *p, U8 u1Channel)
+{
+    U8 u1RankIdx, u1RankMax, u1ChannelBak, u1ByteIdx, ii;
+    U32 u4ResultDQS_PI, u4ResultDQS_UI, u4ResultDQS_UI_P1;
+    U8 u1Dqs_pi[DQS_BIT_NUMBER], u1Dqs_ui[DQS_BIT_NUMBER], u1Dqs_ui_P1[DQS_BIT_NUMBER];
+    U16 u2TmpValue, u2TmpUI[DQS_BYTE_NUMBER], u2TmpPI[DQS_BYTE_NUMBER];
+    U32 MANUDLLFRZ_bak, STBSTATE_OPT_bak;
+    U32 backup_rank;
+    U8 u1DQX_B0, u1DQS0, u1DQX_B1, u1DQS1;
+
+    u1ChannelBak = p->channel;
+    vSetPHY2ChannelMapping(p, u1Channel);
+    backup_rank = u1GetRank(p);
+
+    if (p->support_rank_num == RANK_DUAL)
+        u1RankMax = RANK_MAX;
+    else
+         u1RankMax = RANK_1;
+
+    for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+        mcSHOW_DBG_MSG3(("[RXDQDQSStatus] CH%d, RK%d\n", p->channel, u1RankIdx));
+        if (u1RankIdx == 0)
+        u4ResultDQS_PI = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_MISC_DQ_RXDLY_TRRO22));
+        if (u1RankIdx == 1)
+        u4ResultDQS_PI = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_MISC_DQ_RXDLY_TRRO23));
+
+        u1DQX_B0 = u4ResultDQS_PI & 0xff;
+        u1DQS0 = (u4ResultDQS_PI >> 8) & 0xff;
+        u1DQX_B1 = (u4ResultDQS_PI >> 16) & 0xff;
+        u1DQS1 = (u4ResultDQS_PI >> 24) & 0xff;
+
+        mcSHOW_DBG_MSG3(("DQX_B0, DQS0, DQX_B1, DQS1 =(%d, %d, %d, %d)\n\n", u1DQX_B0, u1DQS0, u1DQX_B1, u1DQS1));
+
+        }
+    vSetRank(p, backup_rank);
+
+    p->channel = u1ChannelBak;
+    vSetPHY2ChannelMapping(p, u1ChannelBak);
+}
+#endif
+#endif
+
+void DummyReadForDqsGatingRetryShuffle(DRAMC_CTX_T *p, bool bEn)
+{
+    if (bEn == 1)
+    {
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DQSG_RETRY1, P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM)//Retry once
+                                     | P_Fld(1, MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE)
+                                     | P_Fld(0, MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN)
+                                     | P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_SW_EN)
+                                     | P_Fld(1, MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE)
+                                     | P_Fld(1, MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE)
+                                     | P_Fld(1, MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS));
+    }
+    else
+    {
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DQSG_RETRY1, P_Fld(0, MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE)
+                                     | P_Fld(0, MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN)
+                                     | P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_SW_EN));
+    }
+    return;
+}
+
+void DummyReadForDqsGatingRetryNonShuffle(DRAMC_CTX_T *p, bool bEn)
+{
+    U8 backup_rank = p->rank;
+    U8 rankIdx;
+
+    if (bEn == 1)
+    {
+        vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL);//Dummy Read rank selection is controlled by Test Agent
+        vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(1, DUMMY_RD_DQSG_DMYRD_EN)
+                                     | P_Fld(p->support_rank_num, DUMMY_RD_RANK_NUM)
+                                     | P_Fld(1, DUMMY_RD_DUMMY_RD_SW));
+        for (rankIdx = RANK_0; rankIdx < p->support_rank_num; rankIdx++)
+        {
+            vSetRank(p, rankIdx);
+            vIO32WriteFldAlign_All(DRAMC_REG_RK_DUMMY_RD_ADR, 0, RK_DUMMY_RD_ADR_DMY_RD_LEN);
+        }
+        vSetRank(p, backup_rank);
+    }
+    else
+    {
+    }
+    return;
+}
+
+#endif // __A60868_TO_BE_PORTING__
+
+#ifdef DUMMY_READ_FOR_TRACKING
+void DramcDummyReadAddressSetting(DRAMC_CTX_T *p)
+{
+    U8 backup_channel = p->channel, backup_rank = p->rank;
+    U8 channelIdx, rankIdx;
+    dram_addr_t dram_addr;
+
+//    for (channelIdx = CHANNEL_A; channelIdx < CHANNEL_NUM; channelIdx++)
+	for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++)
+    {
+        vSetPHY2ChannelMapping(p, channelIdx);
+        for (rankIdx = RANK_0; rankIdx < RANK_MAX; rankIdx++)
+        {
+            vSetRank(p, rankIdx);
+
+            dram_addr.ch = channelIdx;
+            dram_addr.rk = rankIdx;
+
+            get_dummy_read_addr(&dram_addr);
+            mcSHOW_DBG_MSG3(("=== dummy read address: CH_%d, RK%d, row: 0x%x, bk: %d, col: 0x%x\n\n",
+                    channelIdx, rankIdx, dram_addr.row, dram_addr.bk, dram_addr.col));
+
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR2), P_Fld(dram_addr.row, RK_DUMMY_RD_ADR2_DMY_RD_ROW_ADR)
+                                                                        | P_Fld(dram_addr.bk, RK_DUMMY_RD_ADR2_DMY_RD_BK));
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR), P_Fld(dram_addr.col, RK_DUMMY_RD_ADR_DMY_RD_COL_ADR)
+                                                                        | P_Fld(0, RK_DUMMY_RD_ADR_DMY_RD_LEN));
+        }
+    }
+
+    vSetPHY2ChannelMapping(p, backup_channel);
+    vSetRank(p, backup_rank);
+
+}
+
+void DramcDummyReadForTrackingEnable(DRAMC_CTX_T *p)
+{
+    U8 backup_rank = p->rank;
+    U8 rankIdx;
+
+    /* Dummy read pattern (Better efficiency during rx dly tracking) DE: YH Tsai, Wei-jen */
+    for (rankIdx = RANK_0; rankIdx < p->support_rank_num; rankIdx++)
+    {
+        vSetRank(p, rankIdx);
+
+        vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA0, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA0_DMY_RD_RK0_WDATA0
+        vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA1, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA1_DMY_RD_RK0_WDATA1
+        vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA2, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA2_DMY_RD_RK0_WDATA2
+        vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA3, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA3_DMY_RD_RK0_WDATA3
+    }
+    vSetRank(p, backup_rank);
+
+    vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL);//Dummy Read rank selection is controlled by Test Agent
+
+#if 0//__ETT__
+    /* indicate ROW_ADR = 2 for Dummy Write pattern address, in order to avoid pattern will be overwrited by MEM_TEST(test range 0xffff)
+     * Pattern locates: 0x40010000, 0x40010100, 0x80010000, 0x80010100 */
+    dram_addr_t dram_addr;
+
+    dram_addr.ch = 0;
+    dram_addr.rk = 0;
+    get_dummy_read_addr(&dram_addr);
+
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK0_DUMMY_RD_ADR), P_Fld(dram_addr.row, RK0_DUMMY_RD_ADR_DMY_RD_RK0_ROW_ADR)
+                        | P_Fld(dram_addr.col, RK0_DUMMY_RD_ADR_DMY_RD_RK0_COL_ADR)
+                        | P_Fld(0, RK0_DUMMY_RD_ADR_DMY_RD_RK0_LEN));
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_RK0_DUMMY_RD_BK), dram_addr.bk, RK0_DUMMY_RD_BK_DMY_RD_RK0_BK);
+
+    dram_addr.rk = 1;
+    get_dummy_read_addr(&dram_addr);
+
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK1_DUMMY_RD_ADR), P_Fld(dram_addr.row, RK1_DUMMY_RD_ADR_DMY_RD_RK1_ROW_ADR)
+                        | P_Fld(dram_addr.col, RK1_DUMMY_RD_ADR_DMY_RD_RK1_COL_ADR)
+                        | P_Fld(0, RK1_DUMMY_RD_ADR_DMY_RD_RK1_LEN));
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_RK1_DUMMY_RD_BK), dram_addr.bk, RK1_DUMMY_RD_BK_DMY_RD_RK1_BK);
+
+    /* trigger dummy write pattern 0xAAAA5555 */
+    vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DMY_WR_DBG);
+    vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x0, DUMMY_RD_DMY_WR_DBG);
+#else
+    DramcDummyReadAddressSetting(p);
+#endif
+
+    /* DUMMY_RD_RX_TRACK = 1:
+     * During "RX input delay tracking enable" and "DUMMY_RD_EN=1" Dummy read will force a read command to a certain rank,
+     * ignoring whether or not EMI has executed a read command to that certain rank in the past 4us.
+     */
+
+    if (p->frequency >= 1600)
+    {
+#ifdef DPM_CONTROL_AFTERK
+        vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1,
+            P_Fld(3, LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL) | P_Fld(3, LPIF_LOW_POWER_CFG_1_DMYRD_EN));
+#endif
+        vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(1, DUMMY_RD_DMY_RD_RX_TRACK) | P_Fld(1, DUMMY_RD_DUMMY_RD_EN));
+        mcSHOW_DBG_MSG2(("High Freq DUMMY_READ_FOR_TRACKING: ON\n"));
+    }
+    else
+    {
+        mcSHOW_DBG_MSG2(("Low Freq DUMMY_READ_FOR_TRACKING: OFF\n"));
+    }
+
+    return;
+}
+#endif
+
+#ifdef IMPEDANCE_HW_SAVING
+void DramcImpedanceHWSaving(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_IMPCAL_HWSAVE_EN);
+}
+#endif
+
+#ifdef IMPEDANCE_TRACKING_ENABLE
+void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p)
+{
+    U8 u1CHAB_en = DISABLE;
+    #if 0  //Impedance tracking offset for DRVP+2
+    vIO32WriteFldMulti_All(DRAMC_REG_IMPEDAMCE_CTRL1, P_Fld(2, IMPEDAMCE_CTRL1_DQS1_OFF) | P_Fld(2, IMPEDAMCE_CTRL1_DOS2_OFF));
+    vIO32WriteFldMulti_All(DRAMC_REG_IMPEDAMCE_CTRL2, P_Fld(2, IMPEDAMCE_CTRL2_DQ1_OFF) | P_Fld(2, IMPEDAMCE_CTRL2_DQ2_OFF));
+    #endif
+
+    #ifdef IMP_DEBUG_ENABLE
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DBG_IRQ_CTRL9, P_Fld(1, MISC_DBG_IRQ_CTRL9_IMP_CLK_ERR_CLEAN)
+                                                        | P_Fld(1, MISC_DBG_IRQ_CTRL9_IMP_CMD_ERR_CLEAN)
+                                                        | P_Fld(1, MISC_DBG_IRQ_CTRL9_IMP_DQ1_ERR_CLEAN)
+                                                        | P_Fld(1, MISC_DBG_IRQ_CTRL9_IMP_DQ0_ERR_CLEAN)
+                                                        | P_Fld(1, MISC_DBG_IRQ_CTRL9_IMP_DQS_ERR_CLEAN)
+                                                        | P_Fld(1, MISC_DBG_IRQ_CTRL9_IMP_ODTN_ERR_CLEAN)
+                                                        | P_Fld(1, MISC_DBG_IRQ_CTRL9_IMP_DRVN_ERR_CLEAN)
+                                                        | P_Fld(1, MISC_DBG_IRQ_CTRL9_IMP_DRVP_ERR_CLEAN));
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMP_CTRL1, 1, MISC_IMP_CTRL1_IMP_ABN_LAT_CLR);
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_IMP_CTRL1, P_Fld(3, MISC_IMP_CTRL1_IMP_DIFF_THD) | P_Fld(0, MISC_IMP_CTRL1_IMP_ABN_LAT_CLR));
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMP_CTRL1, 1, MISC_IMP_CTRL1_IMP_ABN_LAT_EN);
+    #endif
+
+    //Write (DRAMC _BASE+ 0x8B) [31:0] = 32'he4000000//enable impedance tracking
+    //u1CHAB_en = (p->support_channel_num == CHANNEL_DUAL) ? ENABLE : DISABLE;
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL0, u1CHAB_en, MISC_CTRL0_IMPCAL_CHAB_EN);//Set CHA this bit to enable dual channel tracking
+
+    //During shuffle, after CH_A IMP update done, CH_B has no enough time to update (IMPCAL_IMPCAL_DRVUPDOPT=1)
+    //enable ECO function for impedance load last tracking result of previous shuffle level (IMPCAL_IMPCAL_CHGDRV_ECO_OPT=1)
+    //enable ECO function for impcal_sm hange when DRVP>=0x1D (IMPCAL_IMPCAL_SM_ECO_OPT=1)
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_IMPCAL, P_Fld(1, MISC_IMPCAL_IMPCAL_HW) | P_Fld(0, MISC_IMPCAL_IMPCAL_EN) |
+                                             P_Fld(1, MISC_IMPCAL_IMPCAL_SWVALUE_EN) | P_Fld(1, MISC_IMPCAL_IMPCAL_NEW_OLD_SL) |
+                                             P_Fld(1, MISC_IMPCAL_IMPCAL_DRVUPDOPT) | P_Fld(1, MISC_IMPCAL_IMPCAL_CHGDRV_ECO_OPT) |
+                                             P_Fld(1, MISC_IMPCAL_IMPCAL_SM_ECO_OPT) | P_Fld(1, MISC_IMPCAL_IMPBINARY) |
+                                             P_Fld(1, MISC_IMPCAL_DRV_ECO_OPT));
+
+    //dual channel continuously tracking @ system busy, self-refresh, Hhbrid-S1
+    //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL0, 0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT);
+    //@tg.Only CHA do Impcal tracking, CHB sync CHA result value
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) |
+                                         P_Fld(0x0, MISC_CTRL0_IMPCAL_TRACK_DISABLE));
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0 + SHIFT_TO_CHB_ADDR, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) |
+                                         P_Fld(0x1, MISC_CTRL0_IMPCAL_TRACK_DISABLE));
+
+    // no update imp CA, because CA is unterm now
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV);
+
+    // CH_A set 1, CH_B set 0 (mp setting)
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL, P_Fld(0, MISC_IMPCAL_DIS_SUS_CH0_DRV) |
+                                         P_Fld(1, MISC_IMPCAL_DIS_SUS_CH1_DRV) |
+                                         P_Fld(0, MISC_IMPCAL_IMPSRCEXT) |      //Update mp setting
+                                         P_Fld(1, MISC_IMPCAL_IMPCAL_ECO_OPT)); //Update mp setting
+    vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHB_ADDR, P_Fld(1, MISC_IMPCAL_DIS_SUS_CH0_DRV) |
+                                         P_Fld(0, MISC_IMPCAL_DIS_SUS_CH1_DRV) |
+                                         P_Fld(1, MISC_IMPCAL_IMPSRCEXT) |      //Update mp setting
+                                         P_Fld(0, MISC_IMPCAL_IMPCAL_ECO_OPT)); //Update mp setting
+#if (CHANNEL_NUM > 2)
+	if (channel_num_auxadc > 2) {
+    	vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHC_ADDR, P_Fld(0, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(1, MISC_IMPCAL_DIS_SUS_CH1_DRV));
+	    vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHD_ADDR, P_Fld(1, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(0, MISC_IMPCAL_DIS_SUS_CH1_DRV));
+		}
+#endif
+
+    //Maoauo: keep following setting for SPMFW enable REFCTRL0_DRVCGWREF = 1 (Imp SW Save mode)
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_DRVCGWREF); //@Maoauo, Wait AB refresh to avoid IO drive via logic design
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_DQDRVSWUPD);
+}
+#endif
+
+#if __ETT__
+void DramcPrintIMPTrackingStatus(DRAMC_CTX_T *p, U8 u1Channel)
+{
+#ifdef IMPEDANCE_TRACKING_ENABLE
+
+    U8 u1RankIdx, u1RankMax, u1ChannelBak, u1ByteIdx, ii;
+    U8 DQS_DRVN_2, DQS_DRVP_2, DQS_ODTN_2, DQS_DRVN, DQS_DRVP, DQS_ODTN;
+    U8 DQ_DRVN_2, DQ_DRVP_2, DQ_ODTN_2, DQ_DRVN, DQ_DRVP, DQ_ODTN;
+    U8 CMD_DRVN_2, CMD_DRVP_2, CMD_ODTN_2, CMD_DRVN, CMD_DRVP, CMD_ODTN;
+
+    u1ChannelBak = p->channel;
+    vSetPHY2ChannelMapping(p, u1Channel);
+
+    mcSHOW_DBG_MSG3(("[IMPTrackingStatus] CH=%d\n", p->channel));
+
+//    if (u1Channel == CHANNEL_A)
+    {//460 464: ODTN DRVP, 468 46C: DRVN DRVP
+
+        //DQS
+        DQS_DRVN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS2), MISC_IMPCAL_STATUS2_DRVNDQS_SAVE_2);
+        DQS_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS2), MISC_IMPCAL_STATUS2_DRVPDQS_SAVE_2);
+        DQS_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS2), MISC_IMPCAL_STATUS2_ODTNDQS_SAVE_2);
+        DQS_DRVN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS1), MISC_IMPCAL_STATUS1_DRVNDQS_SAVE_1);
+        DQS_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS1), MISC_IMPCAL_STATUS1_DRVPDQS_SAVE_1);
+        DQS_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS1), MISC_IMPCAL_STATUS1_ODTNDQS_SAVE_1);
+
+        //DQ
+        DQ_DRVN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS4), MISC_IMPCAL_STATUS4_DRVNDQ_SAVE_2);
+        DQ_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS4), MISC_IMPCAL_STATUS4_DRVPDQ_SAVE_2);
+        DQ_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS4), MISC_IMPCAL_STATUS4_ODTNDQ_SAVE_2);
+        DQ_DRVN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_DRVNDQ_SAVE_1);
+        DQ_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_DRVPDQ_SAVE_1);
+        DQ_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_ODTNDQ_SAVE_1);
+
+        //CMD
+        CMD_DRVN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS8), MISC_IMPCAL_STATUS8_DRVNCMD_SAVE_2);
+        CMD_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS8), MISC_IMPCAL_STATUS8_DRVPCMD_SAVE_2);
+        CMD_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS8), MISC_IMPCAL_STATUS8_ODTNCMD_SAVE_2);
+        CMD_DRVN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS7), MISC_IMPCAL_STATUS7_DRVNCMD_SAVE_1);
+        CMD_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS7), MISC_IMPCAL_STATUS7_DRVPCMD_SAVE_1);
+        CMD_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS7), MISC_IMPCAL_STATUS7_ODTNCMD_SAVE_1);
+    }
+#if 0
+    else
+    {
+        U8 shu_level;
+
+        //Channel B is workaround
+        shu_level = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHUSTATUS), SHUSTATUS_SHUFFLE_LEVEL);
+        mcSHOW_DBG_MSG(("shu_level=%d\n", shu_level));
+
+        //DQ
+        DQ_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING1 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING1_DQDRV2_DRVP);
+        DQ_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING2 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING2_DQDRV1_DRVP);
+        DQ_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING3 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING3_DQODT2_ODTN);
+        DQ_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING4 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING4_DQODT1_ODTN);
+
+        //DQS
+        DQS_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING1 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING1_DQSDRV2_DRVP);
+        DQS_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING1 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING1_DQSDRV1_DRVP);
+        DQS_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING3 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING3_DQSODT2_ODTN);
+        DQS_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING3 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING3_DQSODT1_ODTN);
+
+        //CMD
+        CMD_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING2 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING2_CMDDRV2_DRVP);
+        CMD_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING2 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING2_CMDDRV1_DRVP);
+        CMD_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING4 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING4_CMDODT2_ODTN);
+        CMD_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING4 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING4_CMDODT1_ODTN);
+    }
+#endif
+
+    mcSHOW_DBG_MSG3(("\tDRVN_2\tDRVP_2\tODTN_2\tDRVN\tDRVP\tODTN\n"
+                    "DQS\t%d\t%d\t%d\t%d\t%d\t%d\n"
+                    "DQ\t%d\t%d\t%d\t%d\t%d\t%d\n"
+                    "CMD\t%d\t%d\t%d\t%d\t%d\t%d\n",
+                    DQS_DRVN_2, DQS_DRVP_2, DQS_ODTN_2, DQS_DRVN, DQS_DRVP, DQS_ODTN,
+                    DQ_DRVN_2, DQ_DRVP_2, DQ_ODTN_2, DQ_DRVN, DQ_DRVP, DQ_ODTN,
+                    CMD_DRVN_2, CMD_DRVP_2, CMD_ODTN_2, CMD_DRVN, CMD_DRVP, CMD_ODTN));
+
+    p->channel = u1ChannelBak;
+    vSetPHY2ChannelMapping(p, u1ChannelBak);
+#endif
+}
+#endif
+/* divRoundClosest() - to round up to the nearest integer
+ * discard four, but treat five as whole (of decimal points)
+ */
+int divRoundClosest(const int n, const int d)
+{
+  return ((n < 0) ^ (d < 0))? ((n - d / 2) / d): ((n + d / 2) / d);
+}
+
+
+#if (ENABLE_TX_TRACKING || TDQSCK_PRECALCULATION_FOR_DVFS)
+void FreqJumpRatioCalculation(DRAMC_CTX_T *p)
+{
+    U32 shuffle_src_freq, shuffle_dst_index, jump_ratio_index;
+    U16 u2JumpRatio[12] = {0}; /* Used to record __DBQUOTE_ANCHOR__ calulation results */
+    U16 u2Freq = 0;
+
+    /* Calculate jump ratios and save to u2JumpRatio array */
+    jump_ratio_index = 0;
+
+    if (vGet_DDR_Loop_Mode(p) == CLOSE_LOOP_MODE)
+    {
+        shuffle_src_freq = p->frequency;
+        for (shuffle_dst_index = SRAM_SHU0; shuffle_dst_index < DRAM_DFS_SRAM_MAX; shuffle_dst_index++)
+        {
+            DRAM_DFS_FREQUENCY_TABLE_T *pDstFreqTbl = get_FreqTbl_by_SRAMIndex(p, shuffle_dst_index);
+            if (pDstFreqTbl == NULL)
+            {
+                mcSHOW_ERR_MSG(("NULL pFreqTbl\n"));
+                #if __ETT__
+                while (1);
+                #endif
+            }
+            #if 0 //cc mark since been removed in new flow
+            if (pDstFreqTbl->freq_sel == LP4_DDR800)
+            {
+                u2JumpRatio[jump_ratio_index] = 0;
+            }
+            else
+            #endif
+            {
+                u2Freq = GetFreqBySel(p, pDstFreqTbl->freq_sel);
+                u2JumpRatio[jump_ratio_index] = divRoundClosest(u2Freq * 32, shuffle_src_freq);
+                //u2JumpRatio[jump_ratio_index] = (pDstFreqTbl->frequency/shuffle_src_freq)*32;
+                //mcSHOW_DBG_MSG3(("shuffle_%d=DDR%d / shuffle_%d=DDR%d \n", shuffle_dst_index, pFreqTbl->frequency<<1,
+                //                                                            shuffle_src_index, get_FreqTbl_by_SRAMIndex(p,shuffle_src_index)->frequency<<1));
+                //mcSHOW_DBG_MSG3(("Jump_RATIO_%d : 0x%x\n", jump_ratio_index, u2JumpRatio[jump_ratio_index],
+                //                                            get_FreqTbl_by_SRAMIndex(p,shuffle_src_index)->frequency));
+            }
+            #if DUMP_ALLSUH_RG
+            mcSHOW_DBG_MSG(("[DUMPLOG] %d Jump_RATIO[%d]=%d, Jump_DDR%d=%d, Jump_DDR%d=%d\n", p->frequency*2, jump_ratio_index, u2JumpRatio[jump_ratio_index], vGet_Current_SRAMIdx(p), shuffle_src_freq << 1, shuffle_dst_index, u2Freq << 1));
+            #endif
+            jump_ratio_index++;
+        }
+    }
+
+    /* Save jumpRatios into corresponding register fields */
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(u2JumpRatio[0], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0)
+                                                            | P_Fld(u2JumpRatio[1], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1)
+                                                            | P_Fld(u2JumpRatio[2], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2)
+                                                            | P_Fld(u2JumpRatio[3], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3));
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_FREQ_RATIO_SET1, P_Fld(u2JumpRatio[4], SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4)
+                                                            | P_Fld(u2JumpRatio[5], SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5)
+                                                            | P_Fld(u2JumpRatio[6], SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6)
+                                                            | P_Fld(u2JumpRatio[7], SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7));
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_FREQ_RATIO_SET2, P_Fld(u2JumpRatio[8], SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8)
+                                                            | P_Fld(u2JumpRatio[9], SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9));
+    return;
+}
+#endif
+
+
+#if TDQSCK_PRECALCULATION_FOR_DVFS
+void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)
+{
+    U8 mck, ui, pi;
+    U8 mck_p1, ui_p1;
+    U8 byte_idx, rank;
+    U8 backup_rank;
+    U8 mck2ui;
+    U8 set_value;
+
+    backup_rank = u1GetRank(p);
+
+#if 1//(fcFOR_CHIP_ID == fc8195)
+    mck2ui = 4;
+#else
+    ///TODO: use vGet_Div_Mode() instead later
+    if (vGet_Div_Mode(p) == DIV16_MODE)
+        mck2ui = 4; /* 1:16 mode */
+    else if (vGet_Div_Mode(p) == DIV8_MODE)
+        mck2ui = 3; /* 1: 8 mode */
+    else
+        mck2ui = 2; /* 1: 4 mode */
+#endif
+
+    mcSHOW_DBG_MSG2(("Pre-setting of DQS Precalculation\n"));
+
+    for (byte_idx = 0; byte_idx < DQS_BYTE_NUMBER; byte_idx++) {
+        for (rank = RANK_0; rank < p->support_rank_num; rank++) {
+            vSetRank(p, rank);
+
+            if (byte_idx == 0) {
+                mck = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
+                    SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0);
+                ui = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
+                    SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0);
+
+                mck_p1= u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
+                    SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0);
+                ui_p1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
+                    SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0);
+
+                pi = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY),
+                    SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
+
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI),
+                    P_Fld((mck << mck2ui) + ui, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0) |
+                    P_Fld(pi, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0));
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI),
+                    P_Fld((mck << mck2ui) +ui, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) |
+                    P_Fld((mck_p1 << mck2ui) + ui_p1, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0) |
+                    P_Fld(pi, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0));
+            } else {
+                mck = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
+                    SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1);
+                ui = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
+                    SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1);
+
+                mck_p1= u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
+                    SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1);
+                ui_p1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
+                    SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1);
+
+                pi = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY),
+                    SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
+
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI),
+                    P_Fld((mck << mck2ui) + ui, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1) |
+                    P_Fld(pi, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1));
+                vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI),
+                    P_Fld((mck << mck2ui) +ui, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) |
+                    P_Fld((mck_p1 << mck2ui) + ui_p1, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1) |
+                    P_Fld(pi, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0));
+            }
+        }
+    }
+
+    vSetRank(p, backup_rank);
+
+    /* Disable DDR800semi and DDR400open precal */
+    if (vGet_DDR_Loop_Mode(p) != CLOSE_LOOP_MODE)
+    {
+        set_value = 1;
+    }
+    else
+    {
+        set_value = 0;
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_PRE_TDQSCK),
+        set_value, SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_CG_CTRL),
+        set_value, MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN);
+    #if DUMP_ALLSUH_RG
+    mcSHOW_DBG_MSG(("[DUMPLOG] %d RX_DQS_PREK_DISABLE Channel%d %d\n", p->frequency * 2, p->channel, set_value));
+    #endif
+}
+
+#if 0
+void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)//Test tDQSCK_temp Pre-calculation
+{
+    U8 u1ByteIdx, u1RankNum, u1RankBackup = p->rank;
+    U8 u1ShuLevel = vGet_Current_SRAMIdx(p);
+    U8 u1UI_value, u1PI_value, u1MCK_value;
+    U16 u2Byte_offset;
+    U32 u1Delay_Addr[2] = {0}, u1Delay_Fld[2];
+    REG_FLD_DQS_PRE_K TransferReg;
+
+    mcSHOW_DBG_MSG(("Pre-setting of DQS Precalculation\n"));
+    mcDUMP_REG_MSG(("Pre-setting of DQS Precalculation\n"));
+
+    if ((u1ShuLevel >= SRAM_SHU4) && (u1ShuLevel <= SRAM_SHU7))
+    { //SHU4, 5, 6, 7
+        u1Delay_Addr[0] = ((u1ShuLevel / 6) * 0x4) + 0x30; //Offset of phase0 UI register
+        u1Delay_Addr[1] = 0x38; //Offset of phase1 UI register
+        u2Byte_offset = 0xc;
+    }
+    else if (u1ShuLevel >= SRAM_SHU8)
+    {  //SHU8, 9
+        u1Delay_Addr[0] = 0x260; //Offset of phase0 UI register
+        u1Delay_Addr[1] = 0x268; //Offset of phase1 UI register
+        u2Byte_offset = 0x4;
+    }
+    else //SHU0, 1, 2, 3
+    {
+        u1Delay_Addr[0] = ((u1ShuLevel / 2) * 0x4); //Offset of phase0 UI register
+        u1Delay_Addr[1] = 0x8; //Offset of phase1 UI register
+        u2Byte_offset = 0xc;
+    }
+
+    u1Delay_Fld[0] = u1ShuLevel % 2; //Field of phase0 PI and UI
+    u1Delay_Fld[1] = u1ShuLevel % 4; //Field of phase1 UI
+
+    switch (u1Delay_Fld[0]) //Phase0 UI and PI
+    {
+        case 0:
+            TransferReg.u4UI_Fld = RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0;
+            TransferReg.u4PI_Fld = RK0_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R0;
+            break;
+        case 1:
+            TransferReg.u4UI_Fld = RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0;
+            TransferReg.u4PI_Fld = RK0_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R0;
+            break;
+        default:
+            break;
+    }
+
+    if (u1ShuLevel == SRAM_SHU8)
+    {
+        TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ9_P1_B0R0; //Byte0
+        TransferReg.u4UI_Fld_P1[1] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ9_P1_B1R0; //Byte1
+    }
+    else if (u1ShuLevel == SRAM_SHU9)
+    {
+        TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ10_P1_B0R0; //Byte0
+        TransferReg.u4UI_Fld_P1[1] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ10_P1_B1R0; //Byte1
+    }
+    else //(u1ShuLevel < SRAM_SHU8)
+    {
+        switch (u1Delay_Fld[1]) //Phase1 UI
+        {
+            case 0:
+                TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0;
+                break;
+            case 1:
+                TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0;
+                break;
+            case 2:
+                TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0;
+                break;
+            case 3:
+                TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R0;
+                break;
+            default:
+                break;
+        }
+    }
+
+    for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++)
+    {
+        for (u1RankNum = 0; u1RankNum < p->support_rank_num; u1RankNum++)
+        {
+            vSetRank(p, u1RankNum);
+
+            if (u1ByteIdx == 0)
+            {
+                u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED);
+                u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED);
+                u1PI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_DQSIEN), SHURK0_DQSIEN_R0DQS0IEN);
+            }
+            else //Byte1
+            {
+                u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED);
+                u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED);
+                u1PI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_DQSIEN), SHURK0_DQSIEN_R0DQS1IEN);
+            }
+
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[0] + (u1ByteIdx * u2Byte_offset)), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld);//UI
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[0] + (u1ByteIdx * u2Byte_offset)), u1PI_value, TransferReg.u4PI_Fld); //PI
+
+            if (u1ByteIdx == 0)
+            {
+                u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1);
+                u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1);
+            }
+            else //Byte1
+            {
+                u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1);
+                u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1);
+            }
+
+            if ((u1ShuLevel == SRAM_SHU8) || (u1ShuLevel == SRAM_SHU9))
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[1]), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld_P1[u1ByteIdx]); //phase1 UI
+            else
+                vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[1] + (u1ByteIdx * u2Byte_offset)), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld_P1[0]); //phase1 UI
+        }
+    }
+    vSetRank(p, u1RankBackup);
+
+    return;
+}
+#endif
+
+void DramcDQSPrecalculation_enable(DRAMC_CTX_T *p)
+{
+    //DQS pre-K new mode
+    //cc mark removed vIO32WriteFldAlign_All(DRAMC_REG_RK0_PRE_TDQSCK15, 0x1, RK0_PRE_TDQSCK15_SHUFFLE_LEVEL_MODE_SELECT);
+    //Enable pre-K HW
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_PRECAL_HW);
+    //Select HW flow
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_REG_DVFS);
+    //Set Auto save to RG
+    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL);
+}
+#endif
+
+#if 0 /* CC mark to use DV initial setting */
+void DramcHWGatingInit(DRAMC_CTX_T *p)
+{
+#ifdef HW_GATING
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
+        0, MISC_SHU_STBCAL_STBCALEN);
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL),
+        P_Fld(0, MISC_STBCAL_STBCAL2R) |
+        //cc mark P_Fld(0,STBCAL_STB_SELPHYCALEN) |
+        P_Fld(0, MISC_STBCAL_STBSTATE_OPT) |
+        P_Fld(0, MISC_STBCAL_RKCHGMASKDIS) |
+        P_Fld(0, MISC_STBCAL_REFUICHG) |
+        P_Fld(1, MISC_STBCAL_PICGEN));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), P_Fld(1, MISC_STBCAL_DQSIENCG_CHG_EN));
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0, MISC_STBCAL_CG_RKEN);
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 1, MISC_STBCAL_DQSIENCG_NORMAL_EN);
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 1, MISC_CTRL1_R_DMDQSIENCG_EN);
+
+    DramcHWDQSGatingTracking_ModeSetting(p);
+#endif
+}
+#endif
+
+void DramcHWGatingOnOff(DRAMC_CTX_T *p, U8 u1OnOff)
+{
+#ifdef HW_GATING
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2),
+        u1OnOff, MISC_STBCAL2_STB_GERRSTOP);
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
+        u1OnOff, MISC_SHU_STBCAL_STBCALEN);
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
+        u1OnOff, MISC_SHU_STBCAL_STB_SELPHCALEN);
+#else
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0,
+        MISC_STBCAL2_STB_GERRSTOP);
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
+        0, MISC_SHU_STBCAL_STBCALEN);
+    vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
+        0, MISC_SHU_STBCAL_STB_SELPHCALEN);
+#endif
+}
+
+
+void DramcHWGatingDebugOnOff(DRAMC_CTX_T *p, U8 u1OnOff)
+{
+#ifdef HW_GATING
+    // STBCAL2_STB_DBG_EN = 0x3, byte0/1 enable
+    U8 u1EnB0B1 = (u1OnOff == ENABLE)? 0x3: 0x0;
+
+    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_STBCAL2,
+        P_Fld(u1EnB0B1, MISC_STBCAL2_STB_DBG_EN) |
+        P_Fld(u1OnOff, MISC_STBCAL2_STB_PIDLYCG_IG) |
+        P_Fld(u1OnOff, MISC_STBCAL2_STB_UIDLYCG_IG) |
+        P_Fld(u1OnOff, MISC_STBCAL2_STB_GERRSTOP) |
+        P_Fld(0, MISC_STBCAL2_STB_DBG_CG_AO) |
+        P_Fld(0, MISC_STBCAL2_STB_DBG_UIPI_UPD_OPT));
+#endif
+
+#if ENABLE_RX_FIFO_MISMATCH_DEBUG
+    vIO32WriteFldAlign_All(DDRPHY_REG_B0_DQ9, 1, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0);
+    vIO32WriteFldAlign_All(DDRPHY_REG_B1_DQ9, 1, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1);
+#endif
+}
+
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+#if (__ETT__ || CPU_RW_TEST_AFTER_K)
+#if 0 // Please use memeset to initail value, due to different CHANNEL_NUM
+U16 u2MaxGatingPos[CHANNEL_NUM][RANK_MAX][DQS_NUMBER] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+U16 u2MinGatingPos[CHANNEL_NUM][RANK_MAX][DQS_NUMBER] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+#endif
+void DramcPrintHWGatingStatus(DRAMC_CTX_T *p, U8 u1Channel)
+{
+#ifdef HW_GATING
+    U8 u1RankIdx, u1RankMax, u1ChannelBak;
+    U8 u1Dqs_pi[DQS_BIT_NUMBER]={0}, u1Dqs_ui[DQS_BIT_NUMBER]={0}, u1Dqs_ui_P1[DQS_BIT_NUMBER]={0};
+    U32 MANUDLLFRZ_bak, STBSTATE_OPT_bak;
+    U32 backup_rank;
+
+    u1ChannelBak = p->channel;
+    vSetPHY2ChannelMapping(p, u1Channel);
+    backup_rank = u1GetRank(p);
+
+    if (p->support_rank_num == RANK_DUAL)
+        u1RankMax = RANK_MAX;
+    else
+        u1RankMax = RANK_1;
+
+    MANUDLLFRZ_bak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL), DLLFRZ_CTRL_MANUDLLFRZ);
+    STBSTATE_OPT_bak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), MISC_STBCAL_STBSTATE_OPT);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL), 1, DLLFRZ_CTRL_MANUDLLFRZ);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 1, MISC_STBCAL_STBSTATE_OPT);
+
+    for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+        mcSHOW_DBG_MSG3(("[DramcHWGatingStatus] Channel=%d, Rank=%d\n", p->channel, u1RankIdx));
+
+        u1Dqs_pi[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0),
+            GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_PI_DLY_RK0);
+        u1Dqs_ui[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0),
+            GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_UI_P0_DLY_RK0);
+        u1Dqs_ui_P1[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0),
+            GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_UI_P1_DLY_RK0);;
+
+        u1Dqs_pi[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0),
+            GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_PI_DLY_RK0);
+        u1Dqs_ui[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0),
+            GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P0_DLY_RK0);
+        u1Dqs_ui_P1[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0),
+            GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P1_DLY_RK0);;
+
+        mcSHOW_DBG_MSG3(("Byte0(ui, pi) =(%x, %x)  Byte1(ui, pi) =(%x, %x)\n",
+            u1Dqs_ui[0], u1Dqs_pi[0], u1Dqs_ui[1], u1Dqs_pi[1]));
+        mcSHOW_DBG_MSG3(("UI_Phase1 (DQS0~1) =(%x, %x)\n\n",
+            u1Dqs_ui_P1[0], u1Dqs_ui_P1[1]));
+    }
+
+    vSetRank(p, backup_rank);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), STBSTATE_OPT_bak, MISC_STBCAL_STBSTATE_OPT);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL), MANUDLLFRZ_bak, DLLFRZ_CTRL_MANUDLLFRZ);
+
+    p->channel = u1ChannelBak;
+    vSetPHY2ChannelMapping(p, u1ChannelBak);
+#endif
+}
+#if 0
+static void DramcHWGatingTrackingRecord(DRAMC_CTX_T *p, U8 u1Channel)
+{
+#ifdef HW_GATING
+#if __A60868_TO_BE_PORTING__
+    U8 u1RankIdx, u1RankMax, u1Info_NUM, u1Info_Max_MUM = 16;
+    U8 u1ChannelBak, u1RankBak;
+
+    U8 u1DBG_Dqs0_DFS, u1DBG_Dqs0_Lead, u1DBG_Dqs0_Lag, u1DBG_Dqs0_UI, u1DBG_Dqs0_PI;
+    U8 u1DBG_Dqs1_DFS, u1DBG_Dqs1_Lead, u1DBG_Dqs1_Lag, u1DBG_Dqs1_UI, u1DBG_Dqs1_PI;
+    U16 u4DBG_Dqs0_Info, u4DBG_Dqs1_Info;
+    U32 u4DBG_Dqs01_Info;
+
+    U32 u4Dqs0_MAX_MIN_DLY, u4Dqs1_MAX_MIN_DLY;
+    U16 u2Dqs0_UI_MAX_DLY, u2Dqs0_PI_MAX_DLY, u2Dqs0_UI_MIN_DLY, u2Dqs0_PI_MIN_DLY;
+    U16 u2Dqs1_UI_MAX_DLY, u2Dqs1_PI_MAX_DLY, u2Dqs1_UI_MIN_DLY, u2Dqs1_PI_MIN_DLY;
+    U8 u1ShuffleLevel;
+
+    u1ChannelBak = p->channel;
+    vSetPHY2ChannelMapping(p, u1Channel);
+    u1RankBak = u1GetRank(p);
+
+    if (p->support_rank_num == RANK_DUAL)
+        u1RankMax = RANK_MAX;
+    else
+         u1RankMax = RANK_1;
+
+    //Run Time HW Gating Debug Information
+    //for(u1RankIdx=0; u1RankIdx<u1RankMax; u1RankIdx++)
+    for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+
+        u1ShuffleLevel = u4IO32ReadFldAlign(DRAMC_REG_SHUSTATUS, SHUSTATUS_SHUFFLE_LEVEL);
+
+        mcSHOW_DBG_MSG3(("\n[HWGatingTrackingRecord] Channel=%d, Rank=%d, SHU_LEVEL=%d\n", p->channel, u1RankIdx, u1ShuffleLevel));
+
+        mcSHOW_DBG_MSG3(("Run Time HW Gating Debug Information :\n"));
+        mcSHOW_DBG_MSG3(("        B0=(DFS,Lead,Lag,4T, UI, PI), B1=(DFS,Lead,Lag,4T, UI, PI)\n"));
+
+        for (u1Info_NUM = 0; u1Info_NUM < u1Info_Max_MUM; u1Info_NUM++)
+        {
+          //DFS_ST(Shuffle Level): bit[15:14]
+          //Shift_R(Lead): bit[13]
+          //Shift_L(Lag) : bit[12]
+          //UI_DLY : bit[11:06]
+          //PI_DLY : bit[05:00]
+          u4DBG_Dqs01_Info = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RK0_B01_STB_DBG_INFO_00 + 0x4 * u1Info_NUM));
+          u4DBG_Dqs0_Info = (u4DBG_Dqs01_Info >> 0) & 0xffff;
+          u4DBG_Dqs1_Info = (u4DBG_Dqs01_Info >> 16) & 0xffff;
+
+          u1DBG_Dqs0_DFS = (u4DBG_Dqs0_Info >> 14) & 0x03;
+          u1DBG_Dqs0_Lead = (u4DBG_Dqs0_Info >> 13) & 0x01;
+          u1DBG_Dqs0_Lag = (u4DBG_Dqs0_Info >> 12) & 0x01;
+          u1DBG_Dqs0_UI = (u4DBG_Dqs0_Info >> 6) & 0x3f;
+          u1DBG_Dqs0_PI = (u4DBG_Dqs0_Info >> 0) & 0x3f;
+
+          u1DBG_Dqs1_DFS = (u4DBG_Dqs1_Info >> 14) & 0x03;
+          u1DBG_Dqs1_Lead = (u4DBG_Dqs1_Info >> 13) & 0x01;
+          u1DBG_Dqs1_Lag = (u4DBG_Dqs1_Info >> 12) & 0x01;
+          u1DBG_Dqs1_UI = (u4DBG_Dqs1_Info >> 6) & 0x3f;
+          u1DBG_Dqs1_PI = (u4DBG_Dqs1_Info >> 0) & 0x3f;
+
+          if (u1Info_NUM < 10)
+          {
+            mcSHOW_DBG_MSG3(("Info= %d ", u1Info_NUM));
+          }
+          else
+          {
+            mcSHOW_DBG_MSG3(("Info=%d ", u1Info_NUM));
+          }
+
+          mcSHOW_DBG_MSG3(("B0=(  %d,  %d,  %d,  %d,  %d, %d), B1=(  %d,  %d,  %d,  %d,  %d,  %d)\n",
+          u1DBG_Dqs0_DFS, u1DBG_Dqs0_Lead, u1DBG_Dqs0_Lag, u1DBG_Dqs0_UI / 8, u1DBG_Dqs0_UI % 8, u1DBG_Dqs0_PI,
+          u1DBG_Dqs1_DFS, u1DBG_Dqs1_Lead, u1DBG_Dqs1_Lag, u1DBG_Dqs1_UI / 8, u1DBG_Dqs1_UI % 8, u1DBG_Dqs1_PI));
+        }
+
+        //Run Time HW Gating Max and Min Value Record
+        //Run Time HW Gating MAX_DLY UI : bit[27:22]
+        //Run Time HW Gating MAX_DLY PI : bit[21:16]
+        //Run Time HW Gating MIN_DLY UI : bit[11:06]
+        //Run Time HW Gating MIN_DLY PI : bit[05:00]
+        u4Dqs0_MAX_MIN_DLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RK0_B0_STB_MAX_MIN_DLY));
+        u2Dqs0_UI_MAX_DLY = (u4Dqs0_MAX_MIN_DLY >> 22) & 0x3f;
+        u2Dqs0_PI_MAX_DLY = (u4Dqs0_MAX_MIN_DLY >> 16) & 0x3f;
+        u2Dqs0_UI_MIN_DLY = (u4Dqs0_MAX_MIN_DLY >> 6) & 0x3f;
+        u2Dqs0_PI_MIN_DLY = (u4Dqs0_MAX_MIN_DLY >> 0) & 0x3f;
+
+        u4Dqs1_MAX_MIN_DLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RK0_B1_STB_MAX_MIN_DLY));
+        u2Dqs1_UI_MAX_DLY = (u4Dqs1_MAX_MIN_DLY >> 22) & 0x3f;
+        u2Dqs1_PI_MAX_DLY = (u4Dqs1_MAX_MIN_DLY >> 16) & 0x3f;
+        u2Dqs1_UI_MIN_DLY = (u4Dqs1_MAX_MIN_DLY >> 6) & 0x3f;
+        u2Dqs1_PI_MIN_DLY = (u4Dqs1_MAX_MIN_DLY >> 0) & 0x3f;
+
+        mcSHOW_DBG_MSG3(("B0 = MAX(4T, UI, PI) MIN(4T, UI, PI), B1 = MAX(4T, UI, PI) MIN(4T, UI, PI)\n"));
+        mcSHOW_DBG_MSG3(("B0 = MAX( %d,  %d, %d) MIN( %d,  %d, %d),  B1 = MAX( %d,  %d, %d) MIN( %d,  %d, %d)\n",
+                        u2Dqs0_UI_MAX_DLY / 8, u2Dqs0_UI_MAX_DLY % 8, u2Dqs0_PI_MAX_DLY,
+                        u2Dqs0_UI_MIN_DLY / 8, u2Dqs0_UI_MIN_DLY % 8, u2Dqs0_PI_MIN_DLY,
+                        u2Dqs1_UI_MAX_DLY / 8, u2Dqs1_UI_MAX_DLY % 8, u2Dqs1_PI_MAX_DLY,
+                        u2Dqs1_UI_MIN_DLY / 8, u2Dqs1_UI_MIN_DLY % 8, u2Dqs1_PI_MIN_DLY));
+    }
+    vSetRank(p, u1RankBak);
+    p->channel = u1ChannelBak;
+    vSetPHY2ChannelMapping(p, u1ChannelBak);
+#endif
+#endif
+}
+#endif
+///TODO: wait for porting +++
+#if __A60868_TO_BE_PORTING__
+
+void DramcPrintRXFIFODebugStatus(DRAMC_CTX_T *p)
+{
+#if RX_PICG_NEW_MODE
+    //RX FIFO debug feature, MP setting should enable debug function for Gating error information
+    //APHY control new mode
+    U32 u1ChannelBak, u4value;
+    U8 u1ChannelIdx;
+
+    u1ChannelBak = p->channel;
+
+    for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
+    {
+        p->channel = u1ChannelIdx;
+
+        u4value = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBERR_RK0_R)) & (0xf << 24); //DDRPHY NAO bit24~27
+        if (u4value)
+        {
+            mcSHOW_DBG_MSG2(("\n[RXFIFODebugStatus] CH_%d MISC_STBERR_RK0_R_RX_ARDQ = 0x\033[1;36m%x\033[m for Gating error information\n", u1ChannelIdx, u4value));
+        }
+    }
+    p->channel = u1ChannelBak;
+    vSetPHY2ChannelMapping(p, u1ChannelBak);
+#endif
+}
+#endif  //#if __ETT__
+#endif
+
+#endif /// __A60868_TO_BE_PORTING__
+///TODO: wait for porting +++
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_utility.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_utility.c
new file mode 100644
index 000000000000..9490465b8d0a
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_utility.c
@@ -0,0 +1,3308 @@
+/*----------------------------------------------------------------------------*
+ * Copyright Statement:                                                       *
+ *                                                                            *
+ *   This software/firmware and related documentation ("MediaTek Software")   *
+ * are protected under international and related jurisdictions'copyright laws *
+ * as unpublished works. The information contained herein is confidential and *
+ * proprietary to MediaTek Inc. Without the prior written permission of       *
+ * MediaTek Inc., any reproduction, modification, use or disclosure of        *
+ * MediaTek Software, and information contained herein, in whole or in part,  *
+ * shall be strictly prohibited.                                              *
+ * MediaTek Inc. Copyright (C) 2010. All rights reserved.                     *
+ *                                                                            *
+ *   BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND     *
+ * AGREES TO THE FOLLOWING:                                                   *
+ *                                                                            *
+ *   1)Any and all intellectual property rights (including without            *
+ * limitation, patent, copyright, and trade secrets) in and to this           *
+ * Software/firmware and related documentation ("MediaTek Software") shall    *
+ * remain the exclusive property of MediaTek Inc. Any and all intellectual    *
+ * property rights (including without limitation, patent, copyright, and      *
+ * trade secrets) in and to any modifications and derivatives to MediaTek     *
+ * Software, whoever made, shall also remain the exclusive property of        *
+ * MediaTek Inc.  Nothing herein shall be construed as any transfer of any    *
+ * title to any intellectual property right in MediaTek Software to Receiver. *
+ *                                                                            *
+ *   2)This MediaTek Software Receiver received from MediaTek Inc. and/or its *
+ * representatives is provided to Receiver on an "AS IS" basis only.          *
+ * MediaTek Inc. expressly disclaims all warranties, expressed or implied,    *
+ * including but not limited to any implied warranties of merchantability,    *
+ * non-infringement and fitness for a particular purpose and any warranties   *
+ * arising out of course of performance, course of dealing or usage of trade. *
+ * MediaTek Inc. does not provide any warranty whatsoever with respect to the *
+ * software of any third party which may be used by, incorporated in, or      *
+ * supplied with the MediaTek Software, and Receiver agrees to look only to   *
+ * such third parties for any warranty claim relating thereto.  Receiver      *
+ * expressly acknowledges that it is Receiver's sole responsibility to obtain *
+ * from any third party all proper licenses contained in or delivered with    *
+ * MediaTek Software.  MediaTek is not responsible for any MediaTek Software  *
+ * releases made to Receiver's specifications or to conform to a particular   *
+ * standard or open forum.                                                    *
+ *                                                                            *
+ *   3)Receiver further acknowledge that Receiver may, either presently       *
+ * and/or in the future, instruct MediaTek Inc. to assist it in the           *
+ * development and the implementation, in accordance with Receiver's designs, *
+ * of certain softwares relating to Receiver's product(s) (the "Services").   *
+ * Except as may be otherwise agreed to in writing, no warranties of any      *
+ * kind, whether express or implied, are given by MediaTek Inc. with respect  *
+ * to the Services provided, and the Services are provided on an "AS IS"      *
+ * basis. Receiver further acknowledges that the Services may contain errors  *
+ * that testing is important and it is solely responsible for fully testing   *
+ * the Services and/or derivatives thereof before they are used, sublicensed  *
+ * or distributed. Should there be any third party action brought against     *
+ * MediaTek Inc. arising out of or relating to the Services, Receiver agree   *
+ * to fully indemnify and hold MediaTek Inc. harmless.  If the parties        *
+ * mutually agree to enter into or continue a business relationship or other  *
+ * arrangement, the terms and conditions set forth herein shall remain        *
+ * effective and, unless explicitly stated otherwise, shall prevail in the    *
+ * event of a conflict in the terms in any agreements entered into between    *
+ * the parties.                                                               *
+ *                                                                            *
+ *   4)Receiver's sole and exclusive remedy and MediaTek Inc.'s entire and    *
+ * cumulative liability with respect to MediaTek Software released hereunder  *
+ * will be, at MediaTek Inc.'s sole discretion, to replace or revise the      *
+ * MediaTek Software at issue.                                                *
+ *                                                                            *
+ *   5)The transaction contemplated hereunder shall be construed in           *
+ * accordance with the laws of Singapore, excluding its conflict of laws      *
+ * principles.  Any disputes, controversies or claims arising thereof and     *
+ * related thereto shall be settled via arbitration in Singapore, under the   *
+ * then current rules of the International Chamber of Commerce (ICC).  The    *
+ * arbitration shall be conducted in English. The awards of the arbitration   *
+ * shall be final and binding upon both parties and shall be entered and      *
+ * enforceable in any court of competent jurisdiction.                        *
+ *---------------------------------------------------------------------------*/
+
+//-----------------------------------------------------------------------------
+// Include files
+//-----------------------------------------------------------------------------
+#include "dramc_common.h"
+#include "dramc_int_global.h" //for gu1BroadcastIsLP4
+#include "dramc_dv_init.h"
+#include "x_hal_io.h"
+#if (FOR_DV_SIMULATION_USED == 0)
+#include "dramc_top.h"
+#endif
+#include "emi.h"
+//#include "dramc_register.h"
+#if __ETT__
+#include <barriers.h>
+#endif
+#if DRAM_AUXADC_CONFIG
+#include <mtk_auxadc_sw.h>
+#endif
+//-----------------------------------------------------------------------------
+// Global variables
+//-----------------------------------------------------------------------------
+
+#if (fcFOR_CHIP_ID == fcA60868)
+U8 u1EnterRuntime;
+#endif
+
+U8 u1IsLP4Family(DRAM_DRAM_TYPE_T dram_type)
+{
+    if (dram_type == TYPE_LPDDR5)
+        return FALSE;
+    else
+        return TRUE;
+}
+
+u8 is_lp5_family(DRAMC_CTX_T *p)
+{
+    return p->dram_type == TYPE_LPDDR5? TRUE: FALSE;
+}
+
+u8 is_heff_mode(DRAMC_CTX_T *p)
+{
+    u8 res = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0),
+            SHU_COMMON0_LP5HEFF_MODE);
+    mcSHOW_DBG_MSG5(("HEFF Mode: %d\n", res));
+    return res? TRUE: FALSE;
+}
+
+#if __LP5_COMBO__
+static u8 lp5heff;
+
+u8 lp5heff_save_disable(DRAMC_CTX_T *p)
+{
+    /* save it */
+    lp5heff = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0),
+            SHU_COMMON0_LP5HEFF_MODE);
+
+    /* disable it */
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0),
+            P_Fld(0, SHU_COMMON0_LP5HEFF_MODE));
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RKCFG),
+        0, RKCFG_CKE2RANK);
+
+
+    return lp5heff;
+}
+
+void lp5heff_restore(DRAMC_CTX_T *p)
+{
+    /* restore it */
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0),
+            P_Fld(lp5heff, SHU_COMMON0_LP5HEFF_MODE));
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RKCFG),
+        lp5heff, RKCFG_CKE2RANK);
+}
+#endif
+
+#if FOR_DV_SIMULATION_USED
+U8 u1BroadcastOnOff = 0;
+#endif
+U32 GetDramcBroadcast(void)
+{
+#if (fcFOR_CHIP_ID == fcA60868)
+    return 0;
+#endif
+
+#if (FOR_DV_SIMULATION_USED == 0)
+    return *((volatile unsigned int *)(DRAMC_WBR));
+#else
+    return u1BroadcastOnOff;
+#endif
+}
+
+void DramcBroadcastOnOff(U32 bOnOff)
+{
+#if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
+
+    #if (fcFOR_CHIP_ID == fcA60868)
+        return; //disable broadcast in A60868
+    #endif
+
+    #if __Petrus_TO_BE_PORTING__
+        U8 u1BroadcastStatus = 0;
+        // INFRA_RSVD3[9:8] = protect_set_clr_mask
+        u1BroadcastStatus = (*((volatile unsigned int *)(INFRA_RSVD3)) >> 8) & 0x3;
+        if (u1BroadcastStatus & 0x1) // Enable new infra access by Preloader
+        {
+            if (bOnOff == DRAMC_BROADCAST_ON)
+                *((volatile unsigned int *)(DRAMC_WBR_SET)) = DRAMC_BROADCAST_SET;
+            else
+                *((volatile unsigned int *)(DRAMC_WBR_CLR)) = DRAMC_BROADCAST_CLR;
+        }
+        else
+    #endif
+		if (bOnOff == DRAMC_BROADCAST_ON) {
+			if (channel_num_auxadc > 2)
+                *((volatile unsigned int *)(DRAMC_WBR)) = DRAMC_BROADCAST_ON_4CH;
+			else
+				*((volatile unsigned int *)(DRAMC_WBR)) = DRAMC_BROADCAST_ON_2CH;
+			}
+		else {
+            *((volatile unsigned int *)(DRAMC_WBR)) = bOnOff;
+			}
+        dsb();
+#endif
+
+#if (FOR_DV_SIMULATION_USED == 1)
+        if (gu1BroadcastIsLP4 == TRUE)
+        {
+            #if (fcFOR_CHIP_ID == fcA60868)
+            bOnOff = 0;
+            #endif
+            if (bOnOff)
+            {
+                broadcast_on();
+                mcSHOW_DBG_MSG2(("Broadcast ON\n"));
+                u1BroadcastOnOff = bOnOff;
+            }
+            else
+            {
+                broadcast_off();
+                mcSHOW_DBG_MSG2(("Broadcast OFF\n"));
+                u1BroadcastOnOff = bOnOff;
+            }
+        }
+#endif
+
+#ifdef DUMP_INIT_RG_LOG_TO_DE
+        if(gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag)
+        {
+            U8 u1BroadcastStatus = 0;
+            U32 addr, val;
+
+            addr = DRAMC_WBR;
+            val = bOnOff;
+            // *((volatile unsigned int *)(DRAMC_WBR)) = bOnOff;
+
+            mcSHOW_DUMP_INIT_RG_MSG(("*((UINT32P)(0x%x)) = 0x%x;\n",addr, val));
+    //        mcDELAY_MS(1);
+#if (FOR_DV_SIMULATION_USED==0)
+            GPT_Delay_ms(1);
+#endif
+        }
+#endif
+    }
+
+
+
+#if __ETT__
+const U32 u4Cannot_Use_Dramc_WBR_Reg[]=
+{
+    DDRPHY_REG_CA_DLL_ARPI5,
+    DDRPHY_REG_B0_DLL_ARPI5,
+    DDRPHY_REG_B1_DLL_ARPI5,
+
+    DDRPHY_REG_SHU_CA_DLL0,
+    DDRPHY_REG_SHU_CA_DLL1,
+
+    DDRPHY_REG_CA_LP_CTRL0,
+
+    DDRPHY_REG_MISC_DVFSCTL2,
+    DDRPHY_REG_MISC_SHU_OPT,
+
+    DDRPHY_REG_MISC_DVFSCTL,
+    DDRPHY_REG_MISC_DVFSCTL3,
+
+    DDRPHY_REG_MISC_CKMUX_SEL,
+    DRAMC_REG_DVFS_CTRL0
+};
+#define CANNOT_USE_WBR_SIZE ((sizeof(u4Cannot_Use_Dramc_WBR_Reg)) / (sizeof(U32)))
+void CheckDramcWBR(U32 u4address)
+{
+
+    U32 i, channel_and_value;
+    if (GetDramcBroadcast()==DRAMC_BROADCAST_ON)
+    {
+        #if (CHANNEL_NUM > 2)
+			if (channel_num_auxadc > 2) {
+            channel_and_value = 0x3;
+				}
+        #else //for channel number = 1 or 2
+            channel_and_value = 0x1;
+        #endif
+        if ((((u4address - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & channel_and_value) != CHANNEL_A)
+        {
+            mcSHOW_ERR_MSG(("Error! virtual address 0x%x is not CHA and cannot use Dramc WBR\n", u4address));
+            while (1);
+        }
+            for (i = 0; i < CANNOT_USE_WBR_SIZE; i++)
+            {
+                if (u4Cannot_Use_Dramc_WBR_Reg[i] == u4address)
+                {
+                    mcSHOW_ERR_MSG(("Error! virtual address 0x%x cannot use Dramc WBR\n", u4address));
+                    while (1);
+                }
+             }
+     }
+}
+#endif
+
+void vSetPHY2ChannelMapping(DRAMC_CTX_T *p, U8 u1Channel)
+{
+    p->channel = (DRAM_CHANNEL_T)u1Channel;
+}
+
+U8 vGetPHY2ChannelMapping(DRAMC_CTX_T *p)
+{
+    return p->channel;
+}
+#if 0
+static U8 GetChannelInfoToConf(DRAMC_CTX_T *p)
+{
+    U8 u1ch_num = CHANNEL_NUM;
+#if ((fcFOR_CHIP_ID == fc8195) && (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0))
+    EMI_SETTINGS *emi_set;
+    U32 u4value = 0;
+
+    emi_set = &g_default_emi_setting;
+
+    u4value = (emi_set->EMI_CONA_VAL >> 8) & 0x3;//CONA 8,9th 0:1ch, 1:2ch, 2:4ch
+
+    if (u4value == 0)
+        u1ch_num = CHANNEL_SINGLE;
+    else if (u4value == 1)
+        u1ch_num = CHANNEL_DUAL;
+#if (CHANNEL_NUM > 2)
+	    else if (u4value == 2)
+			if (channel_num_auxadc > 2) {
+		        u1ch_num = CHANNEL_FOURTH;
+				}
+#endif
+    mcSHOW_DBG_MSG2(("Channel num: %d, CONA[0x%x]\n", u1ch_num, emi_set->EMI_CONA_VAL));
+#endif
+    return u1ch_num;
+}
+#endif
+void vSetChannelNumber(DRAMC_CTX_T *p)
+{
+#if DRAM_AUXADC_CONFIG
+    p->support_channel_num = channel_num_auxadc;//GetChannelInfoToConf(p);
+#else
+    p->support_channel_num = CHANNEL_FOURTH;
+#endif
+}
+
+void vSetRank(DRAMC_CTX_T *p, U8 ucRank)
+{
+    p->rank = (DRAM_RANK_T)ucRank;
+}
+
+U8 u1GetRank(DRAMC_CTX_T *p)
+{
+    return p->rank;
+}
+
+void vSetRankNumber(DRAMC_CTX_T *p)
+{
+#if(FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
+    if (u4IO32ReadFldAlign(DRAMC_REG_SA_RESERVE, SA_RESERVE_SINGLE_RANK) == 1)
+    {
+        p->support_rank_num =RANK_SINGLE;
+    }
+    else
+#endif
+    {
+        p->support_rank_num = RANK_DUAL;
+    }
+}
+
+void vSetFSPNumber(DRAMC_CTX_T *p)
+{
+#if (__LP5_COMBO__ == TRUE)
+    if (TRUE == is_lp5_family(p))
+        p->support_fsp_num = 3;
+    else
+#endif
+        p->support_fsp_num = 2;
+}
+
+static void setFreqGroup(DRAMC_CTX_T *p)
+{
+
+    /* Below listed conditions represent freqs that exist in ACTimingTable
+     * -> Should cover freqGroup settings for all real freq values
+     */
+#if (__LP5_COMBO__ == TRUE)
+    if (TRUE == is_lp5_family(p))
+    {
+        if (p->frequency <= 400) // DDR800
+        {
+            p->freqGroup = 400;
+        }
+        else if (p->frequency <= 600) // DDR1200
+        {
+            p->freqGroup = 600;
+        }
+        else if (p->frequency <= 800) // DDR1600
+        {
+            p->freqGroup = 800;
+        }
+        else if (p->frequency <= 933) //DDR1866
+        {
+            p->freqGroup = 933;
+        }
+        else if (p->frequency <= 1200) //DDR2400, DDR2280
+        {
+            p->freqGroup = 1200;
+        }
+        else if (p->frequency <= 1600) // DDR3200
+        {
+            p->freqGroup = 1600;
+        }
+        else if (p->frequency <= 1866) // DDR3733
+        {
+            p->freqGroup = 1866;
+        }
+        else if (p->frequency <= 2133) // DDR4266
+        {
+            p->freqGroup = 2133;
+        }
+        else if (p->frequency <= 2400) // DDR4800
+        {
+            p->freqGroup = 2400;
+        }
+        else if (p->frequency <= 2750) // DDR5500
+        {
+            p->freqGroup = 2750;
+        }
+        else if (p->frequency <= 3000) // DDR6000
+        {
+            p->freqGroup = 3000;
+        }
+        else // DDR6600
+        {
+            p->freqGroup = 3300;
+        }
+    }
+    else
+#endif
+    {
+        if (p->frequency <= 200) // DDR400
+        {
+            p->freqGroup = 200;
+        }
+        else if (p->frequency <= 400) // DDR800
+        {
+            p->freqGroup = 400;
+        }
+        else if (p->frequency <= 600) // DDR1200
+        {
+            p->freqGroup = 600;
+        }
+        else if (p->frequency <= 800) // DDR1600
+        {
+            p->freqGroup = 800;
+        }
+        else if (p->frequency <= 933) //DDR1866
+        {
+            p->freqGroup = 933;
+        }
+        else if (p->frequency <= 1200) //DDR2400, DDR2280
+        {
+            p->freqGroup = 1200;
+        }
+        else if (p->frequency <= 1333) // DDR2667
+        {
+            p->freqGroup = 1333;
+        }
+        else if (p->frequency <= 1600) // DDR3200
+        {
+            p->freqGroup = 1600;
+        }
+        else if (p->frequency <= 1866) // DDR3733
+        {
+            p->freqGroup = 1866;
+        }
+        else // DDR4266
+        {
+            p->freqGroup = 2133;
+        }
+    }
+
+    mcSHOW_DBG_MSG4(("[setFreqGroup] p-> frequency %u, freqGroup: %u\n", p->frequency, p->freqGroup));
+    return;
+}
+
+
+#define CKGEN_FMETER 0x0
+#define ABIST_FMETER 0x1
+
+U16 gddrphyfmeter_value[DRAM_DFS_SRAM_MAX] = {0};
+
+U16 DDRPhyGetRealFreq(DRAMC_CTX_T *p)
+{
+    U8 u1SRAMShuLevel = vGet_Current_SRAMIdx(p);
+
+    /* The result may be used as divisor, so need to avoid 0 returned */
+    if(gddrphyfmeter_value[u1SRAMShuLevel])
+    {
+        return gddrphyfmeter_value[u1SRAMShuLevel];
+    }else{
+        mcSHOW_ERR_MSG(("gddrphyfmeter_value[%d] = 0, return p->frequency\n", u1SRAMShuLevel));
+        return p->frequency;
+    }
+}
+
+#if __ETT__  || defined(SLT)
+void GetPhyPllFrequency(DRAMC_CTX_T *p)
+{
+    //U8 u1ShuLevel = u4IO32ReadFldAlign(DRAMC_REG_SHUSTATUS, SHUSTATUS_SHUFFLE_LEVEL);
+    U8 u1ShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_DVFS_STATUS, DVFS_STATUS_OTHER_SHU_GP);
+    U32 u4PLL5_ADDR = DDRPHY_REG_SHU_PHYPLL1 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel;
+    U32 u4PLL8_ADDR = DDRPHY_REG_SHU_PHYPLL2 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel;
+    U32 u4B0_DQ = DDRPHY_REG_SHU_B0_DQ1 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel;
+    U32 u4PLL3_ADDR = DDRPHY_REG_SHU_PHYPLL3 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel;
+    //Darren-U32 u4PLL4 = DDRPHY_SHU_PLL4 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel; // for DDR4266
+    U32 u4B0_DQ6 = DDRPHY_REG_SHU_B0_DQ6 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel;
+
+    /* VCOFreq = FREQ_XTAL x ((RG_RCLRPLL_SDM_PCW) / 2^(RG_*_RCLRPLL_PREDIV)) / 2^(RG_*_RCLRPLL_POSDIV) */
+    U32 u4SDM_PCW = u4IO32ReadFldAlign(u4PLL5_ADDR, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW);
+    U32 u4PREDIV = u4IO32ReadFldAlign(u4PLL8_ADDR, SHU_PHYPLL2_RG_RPHYPLL_PREDIV);
+    U32 u4POSDIV = u4IO32ReadFldAlign(u4PLL8_ADDR, SHU_PHYPLL2_RG_RPHYPLL_POSDIV);
+    U32 u4CKDIV4 = u4IO32ReadFldAlign(u4B0_DQ, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0);
+    U8 u1FBKSEL = u4IO32ReadFldAlign(u4PLL3_ADDR, SHU_PHYPLL3_RG_RPHYPLL_FBKSEL);
+    //Darren-U16 u2CKMUL2 = u4IO32ReadFldAlign(u4PLL4, SHU_PLL4_RG_RPHYPLL_RESERVED);
+    U8 u1SopenDQ = u4IO32ReadFldAlign(u4B0_DQ6, SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0);
+    U8 u1OpenDQ = u4IO32ReadFldAlign(u4B0_DQ6, SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0);
+
+    U32 u4VCOFreq = (((52>>u4PREDIV)*(u4SDM_PCW>>8))>>u4POSDIV) << u1FBKSEL;
+    U32 u4DataRate = u4VCOFreq>>u4CKDIV4;
+    if ((u1SopenDQ == ENABLE)||(u1OpenDQ == ENABLE)) // for 1:4 mode DDR800 (3.2G/DIV4) and DDR400 (1.6G/DIV4)
+        u4DataRate >>= 2;
+
+    //mcSHOW_DBG_MSG(("PCW=0x%X, u4PREDIV=%d, u4POSDIV=%d, CKDIV4=%d, DataRate=%d\n", u4SDM_PCW, u4PREDIV, u4POSDIV, u4CKDIV4, u4DataRate));
+    mcSHOW_DBG_MSG2(("[F] DataRate=%d at SHU%d\n", u4DataRate, u1ShuLevel));
+}
+#endif
+
+DRAM_PLL_FREQ_SEL_T vGet_PLL_FreqSel(DRAMC_CTX_T *p)
+{
+    return p->pDFSTable->freq_sel;
+}
+
+void vSet_PLL_FreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel)
+{
+    p->pDFSTable->freq_sel = sel;
+}
+
+DDR800_MODE_T vGet_DDR_Loop_Mode(DRAMC_CTX_T *p)
+{
+    return p->pDFSTable->ddr_loop_mode;
+}
+
+void vSet_Div_Mode(DRAMC_CTX_T *p, DIV_MODE_T eMode)
+{
+    p->pDFSTable->divmode = eMode;
+}
+
+DIV_MODE_T vGet_Div_Mode(DRAMC_CTX_T *p)
+{
+    return p->pDFSTable->divmode;
+}
+
+void vSet_Current_SRAMIdx(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T u1SRAMIdx)
+{
+    p->pDFSTable->SRAMIdx = u1SRAMIdx;
+}
+
+DRAM_DFS_SRAM_SHU_T vGet_Current_SRAMIdx(DRAMC_CTX_T *p)
+{
+    return p->pDFSTable->SRAMIdx;
+}
+
+#if 0
+void vSet_Duty_Calibration_Mode(DRAMC_CTX_T *p, U8 kMode)
+{
+    p->pDFSTable->duty_calibration_mode = kMode;
+}
+#endif
+
+DUTY_CALIBRATION_T Get_Duty_Calibration_Mode(DRAMC_CTX_T *p)
+{
+    return p->pDFSTable->duty_calibration_mode;
+}
+
+VREF_CALIBRATION_ENABLE_T Get_Vref_Calibration_OnOff(DRAMC_CTX_T *p)
+{
+#if FOR_DV_SIMULATION_USED
+    return VREF_CALI_OFF; //@ tg add for simulation speed up
+#else
+    return p->pDFSTable->vref_calibartion_enable;
+#endif
+}
+
+/* vGet_Dram_CBT_Mode
+ * Due to current HW design (both ranks share the same set of ACTiming regs), mixed
+ * mode LP4 now uses byte mode ACTiming settings. This means most calibration steps
+ * should use byte mode code flow.
+ * Note: The below items must have per-rank settings (Don't use this function)
+ * 1. CBT training 2. TX tracking
+ */
+DRAM_CBT_MODE_T vGet_Dram_CBT_Mode(DRAMC_CTX_T *p)
+{
+    if (p->support_rank_num == RANK_DUAL)
+    {
+        if(p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE && p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)
+            return CBT_NORMAL_MODE;
+    }
+    else // Single rank
+    {
+        if(p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE)
+            return CBT_NORMAL_MODE;
+    }
+
+    return CBT_BYTE_MODE1;
+}
+
+
+void vPrintCalibrationBasicInfo(DRAMC_CTX_T *p)
+{
+#if __ETT__
+    mcSHOW_DBG_MSG(("===============================================================================\n"));
+    mcSHOW_DBG_MSG(("Dram Type= %d, Freq= %u, FreqGroup= %u, CH_%d, rank %d\n"
+                    "fsp= %d, odt_onoff= %d, Byte mode= %d, DivMode= %d\n",
+                        p->dram_type, DDRPhyGetRealFreq(p), p->freqGroup, p->channel, p->rank,
+                        p->dram_fsp, p->odt_onoff, p->dram_cbt_mode[p->rank], vGet_Div_Mode(p)));
+    mcSHOW_DBG_MSG(("===============================================================================\n"));
+
+#else
+    mcSHOW_DBG_MSG(("===============================================================================\n"
+                    "Dram Type= %d, Freq= %u, CH_%d, rank %d\n"
+                    "fsp= %d, odt_onoff= %d, Byte mode= %d, DivMode= %d\n"
+                    "===============================================================================\n",
+                        p->dram_type,
+                        p->frequency /*DDRPhyFMeter()*/,
+                        p->channel,
+                        p->rank,
+                        p->dram_fsp,
+                        p->odt_onoff,
+                        p->dram_cbt_mode[p->rank],
+                        vGet_Div_Mode(p)));
+#endif
+}
+
+#if 0
+void vPrintCalibrationBasicInfo_ForJV(DRAMC_CTX_T *p)
+{
+    mcSHOW_DBG_MSG5(("\n\nDram type:"));
+
+    switch (p->dram_type)
+    {
+        case TYPE_LPDDR4:
+            mcSHOW_DBG_MSG5(("LPDDR4\t"));
+            break;
+
+        case TYPE_LPDDR4X:
+            mcSHOW_DBG_MSG5(("LPDDR4X\t"));
+            break;
+
+        case TYPE_LPDDR4P:
+            mcSHOW_DBG_MSG5(("LPDDR4P\t"));
+            break;
+    }
+
+    mcSHOW_DBG_MSG5(("Freq: %d, FreqGroup %u, channel %d, rank %d\n"
+                     "dram_fsp= %d, odt_onoff= %d, Byte mode= %d, DivMode= %d\n\n",
+                                        p->frequency, p->freqGroup, p->channel, p->rank,
+                                        p->dram_fsp, p->odt_onoff, p->dram_cbt_mode[p->rank], vGet_Div_Mode(p)));
+
+    return;
+}
+#endif
+
+U16 GetFreqBySel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel)
+{
+    U16 u2freq=0;
+
+    switch(sel)
+    {
+        case LP4_DDR4266:
+            u2freq=2133;
+            break;
+        case LP4_DDR3733:
+            u2freq=1866;
+            break;
+        case LP4_DDR3200:
+            u2freq=1600;
+            break;
+        case LP4_DDR2667:
+            u2freq=1333;
+            break;
+        case LP4_DDR2400:
+            u2freq=1200;
+            break;
+        case LP4_DDR1866:
+            u2freq=933;
+            break;
+        case LP4_DDR1600:
+            u2freq=800;
+            break;
+        case LP4_DDR1200:
+            u2freq=600;
+            break;
+        case LP4_DDR800:
+            u2freq=400;
+            break;
+        case LP4_DDR400:
+            u2freq=200;
+            break;
+
+        case LP5_DDR6400:
+            u2freq=3200;
+            break;
+        case LP5_DDR6000:
+            u2freq=3000;
+            break;
+        case LP5_DDR5500:
+            u2freq=2750;
+            break;
+        case LP5_DDR4800:
+            u2freq=2400;
+            break;
+        case LP5_DDR4266:
+            u2freq=2133;
+            break;
+        case LP5_DDR3733:
+            u2freq=1866;
+            break;
+        case LP5_DDR3200:
+            u2freq=1600;
+            break;
+        case LP5_DDR2400:
+            u2freq=1200;
+            break;
+        case LP5_DDR1600:
+            u2freq=800;
+            break;
+        case LP5_DDR1200:
+            u2freq=600;
+            break;
+        case LP5_DDR800:
+            u2freq=400;
+            break;
+
+        default:
+            mcSHOW_ERR_MSG(("[GetFreqBySel] freq sel is incorrect !!!\n"));
+            break;
+    }
+
+    return u2freq;
+}
+
+DRAM_PLL_FREQ_SEL_T GetSelByFreq(DRAMC_CTX_T *p, U16 u2freq)
+{
+    DRAM_PLL_FREQ_SEL_T sel=0;
+
+    switch(u2freq)
+    {
+        case 2133:
+            sel=LP4_DDR4266;
+            break;
+        case 1866:
+            sel=LP4_DDR3733;
+            break;
+        case 1600:
+            sel=LP4_DDR3200;
+            break;
+        case 1333:
+            sel=LP4_DDR2667;
+            break;
+        case 1200:
+            sel=LP4_DDR2400;
+            break;
+        case 933:
+            sel=LP4_DDR1866;
+            break;
+        case 800:
+            sel=LP4_DDR1600;
+            break;
+        case 600:
+            sel=LP4_DDR1200;
+            break;
+        case 400:
+            sel=LP4_DDR800;
+            break;
+        case 200:
+            sel=LP4_DDR400;
+            break;
+        default:
+            mcSHOW_ERR_MSG(("[GetSelByFreq] sel is incorrect !!!\n"));
+            break;
+    }
+
+    return sel;
+}
+
+void DDRPhyFreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel)
+{
+    p->freq_sel = sel;
+    p->frequency = GetFreqBySel(p, sel);
+#if __LP5_COMBO__
+    if(is_lp5_family(p))
+    {
+        ///TODO: Dennis
+        //p->dram_fsp = (p->frequency < LP5_MRFSP_TERM_FREQ)? FSP_0: FSP_1;
+        p->dram_fsp = FSP_0;
+        #if LP5_DDR4266_RDBI_WORKAROUND
+        if(p->frequency >= 2133)
+            p->DBI_R_onoff[FSP_0] = DBI_ON;
+        #endif
+        p->odt_onoff = (p->frequency < LP5_MRFSP_TERM_FREQ)? ODT_OFF: ODT_ON;
+    }
+    else
+#endif
+    {
+        p->dram_fsp = (p->frequency < LP4_MRFSP_TERM_FREQ)? FSP_0: FSP_1;
+        p->odt_onoff = (p->frequency < LP4_MRFSP_TERM_FREQ)? ODT_OFF: ODT_ON;
+    }
+
+    if (p->dram_type == TYPE_LPDDR4P)
+        p->odt_onoff = ODT_OFF;
+
+    setFreqGroup(p); /* Set p->freqGroup to support freqs not in ACTimingTable */
+
+    ///TODO: add DBI_onoff by condition
+    //p->DBI_onoff = p->odt_onoff;
+}
+
+
+U16 u2DFSGetHighestFreq(DRAMC_CTX_T * p)
+{
+    U8 u1ShuffleIdx = 0;
+    U16 u2Freq=0;
+    static U16 u2FreqMax=0;
+
+    if ((u2FreqMax == 0) || (gUpdateHighestFreq == TRUE))
+    {
+        gUpdateHighestFreq = FALSE;
+        u2FreqMax = 0;
+        for (u1ShuffleIdx = 0; u1ShuffleIdx < DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
+        {
+            u2Freq = GetFreqBySel(p, gFreqTbl[u1ShuffleIdx].freq_sel);
+            if(u2FreqMax < u2Freq)
+                u2FreqMax = u2Freq;
+        }
+    }
+
+    return u2FreqMax;
+}
+
+U8 GetEyeScanEnable(DRAMC_CTX_T * p, U8 get_type)
+{
+#if ENABLE_EYESCAN_GRAPH
+#if (fcFOR_CHIP_ID == fcA60868)  //need check unterm highest freq is saved at SRAM_SHU4??
+    //CBT
+    if (get_type == EYESCAN_TYPE_CBT)
+        if (ENABLE_EYESCAN_CBT==1) return ENABLE;  //TO DO :Temp Force open EYESCAN
+
+    //RX
+    if (get_type == EYESCAN_TYPE_RX)
+        if (ENABLE_EYESCAN_RX==1) return ENABLE;  //TO DO :Temp Force open EYESCAN
+
+    //TX
+    if (get_type == EYESCAN_TYPE_TX)
+        if (ENABLE_EYESCAN_TX==1) return ENABLE;  //TO DO :Temp Force open EYESCAN
+
+#else
+    //CBT
+    if (get_type == EYESCAN_TYPE_CBT)
+    {
+        if (gCBT_EYE_Scan_flag==DISABLE) return DISABLE;
+        if (gCBT_EYE_Scan_only_higheset_freq_flag == DISABLE) return ENABLE;  //K All freq
+        if (p->frequency == u2DFSGetHighestFreq(p)) return ENABLE;      // K highest freq
+        if (gEye_Scan_unterm_highest_flag==ENABLE && vGet_Current_SRAMIdx(p)==SRAM_SHU2) return ENABLE;         // K unterm highest freq
+    }
+
+    //RX
+    if (get_type == EYESCAN_TYPE_RX)
+    {
+        if (gRX_EYE_Scan_flag==DISABLE) return DISABLE;
+        if (gRX_EYE_Scan_only_higheset_freq_flag == DISABLE) return ENABLE;  //K All freq
+        if (p->frequency == u2DFSGetHighestFreq(p)) return ENABLE;      // K highest freq
+        if (gEye_Scan_unterm_highest_flag==ENABLE && vGet_Current_SRAMIdx(p)==SRAM_SHU2) return ENABLE;         // K unterm highest freq
+    }
+
+    //TX
+    if (get_type == EYESCAN_TYPE_TX)
+    {
+        if (gTX_EYE_Scan_flag==DISABLE) return DISABLE;
+        if (gTX_EYE_Scan_only_higheset_freq_flag == DISABLE) return ENABLE;  //K All freq
+        if (p->frequency == u2DFSGetHighestFreq(p)) return ENABLE;      // K highest freq
+        if (gEye_Scan_unterm_highest_flag==ENABLE && vGet_Current_SRAMIdx(p)==SRAM_SHU2) return ENABLE;         // K unterm highest freq
+    }
+
+#endif
+#endif
+
+    return DISABLE;
+}
+
+void DramcWriteDBIOnOff(DRAMC_CTX_T *p, U8 onoff)
+{
+    // DRAMC Write-DBI On/Off
+    vIO32WriteFldAlign_All(DRAMC_REG_SHU_TX_SET0, onoff, SHU_TX_SET0_DBIWR);
+    mcSHOW_DBG_MSG2(("DramC Write-DBI %s\n", ((onoff == DBI_ON) ? "on" : "off")));
+}
+
+void DramcReadDBIOnOff(DRAMC_CTX_T *p, U8 onoff)
+{
+    // DRAMC Read-DBI On/Off
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ7, onoff, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0);
+    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ7, onoff, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1);
+    mcSHOW_DBG_MSG2(("DramC Read-DBI %s\n", ((onoff == DBI_ON) ? "on" : "off")));
+}
+#if ENABLE_READ_DBI
+void SetDramModeRegForReadDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff)
+{
+#if MRW_CHECK_ONLY
+    mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+#endif
+    //mcSHOW_DBG_MSG(("--Fsp%d --\n", p->dram_fsp));
+
+    //DRAM MR3[6] read-DBI On/Off
+    u1MR03Value[u1fsp] = ((u1MR03Value[u1fsp] & 0xbf) | (onoff << 6));
+    DramcModeRegWriteByRank(p, p->rank, 3, u1MR03Value[u1fsp]);
+}
+#endif
+
+#if ENABLE_WRITE_DBI
+void SetDramModeRegForWriteDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff)
+{
+#if MRW_CHECK_ONLY
+    mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+#endif
+    //DRAM MR3[7] write-DBI On/Off
+    u1MR03Value[u1fsp] = ((u1MR03Value[u1fsp] & 0x7F) | (onoff << 7));
+    DramcModeRegWriteByRank(p, p->rank, 3, u1MR03Value[u1fsp]);
+}
+#endif
+
+#if 0
+static void AutoRefreshCKEOff(DRAMC_CTX_T *p)
+{
+    U32 u4backup_broadcast= GetDramcBroadcast();
+
+    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
+
+    mcSHOW_DBG_MSG(("AutoRefreshCKEOff AutoREF OFF\n"));
+    vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0x1, REFCTRL0_REFDIS);
+    mcDELAY_US(3);
+    mcSHOW_DBG_MSG(("DDRPhyPLLSetting-CKEOFF\n"));
+
+    CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXOFF, TO_ALL_CHANNEL);
+
+    mcDELAY_US(1);
+
+    //restore broadcast on/off
+    DramcBroadcastOnOff(u4backup_broadcast);
+}
+#endif
+void DramCLKAlwaysOnOff(DRAMC_CTX_T *p, U8 option, CHANNEL_RANK_SEL_T WriteChannelNUM)
+{
+    if (WriteChannelNUM == TO_ALL_CHANNEL) {
+        vIO32WriteFldMulti_All(DRAMC_REG_DRAMC_PD_CTRL,
+                P_Fld(option, DRAMC_PD_CTRL_APHYCKCG_FIXOFF) |
+                P_Fld(option, DRAMC_PD_CTRL_TCKFIXON));
+    } else {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL),
+                P_Fld(option, DRAMC_PD_CTRL_APHYCKCG_FIXOFF) |
+                P_Fld(option, DRAMC_PD_CTRL_TCKFIXON));
+    }
+}
+
+void CKEFixOnOff(DRAMC_CTX_T *p, U8 u1RankIdx, CKE_FIX_OPTION option, CHANNEL_RANK_SEL_T WriteChannelNUM)
+{
+    U8 u1CKEOn, u1CKEOff;
+
+    if (option == CKE_DYNAMIC) //if CKE is dynamic, set both CKE fix On and Off as 0
+    {                          //After CKE FIX on/off, CKE should be returned to dynamic (control by HW)
+        u1CKEOn = u1CKEOff = 0;
+    }
+    else //if CKE fix on is set as 1, CKE fix off should also be set as 0; vice versa
+    {
+        u1CKEOn = option;
+        u1CKEOff = (1 - option);
+    }
+
+    if (WriteChannelNUM == TO_ALL_CHANNEL) //write register to all channel
+    {
+        if((u1RankIdx == RANK_0)||(u1RankIdx == TO_ALL_RANK))
+        {
+            vIO32WriteFldMulti_All(DRAMC_REG_CKECTRL, P_Fld(u1CKEOff, CKECTRL_CKEFIXOFF)
+                                                    | P_Fld(u1CKEOn, CKECTRL_CKEFIXON));
+        }
+
+        if(u1RankIdx == RANK_1||((u1RankIdx == TO_ALL_RANK) && (p->support_rank_num == RANK_DUAL)))
+        {
+            vIO32WriteFldMulti_All(DRAMC_REG_CKECTRL, P_Fld(u1CKEOff, CKECTRL_CKE1FIXOFF)
+                                                    | P_Fld(u1CKEOn, CKECTRL_CKE1FIXON));
+        }
+    }
+    else
+    {
+        if((u1RankIdx == RANK_0) || (u1RankIdx == TO_ALL_RANK))
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), P_Fld(u1CKEOff, CKECTRL_CKEFIXOFF)
+                                                                | P_Fld(u1CKEOn, CKECTRL_CKEFIXON));
+        }
+
+        if((u1RankIdx == RANK_1) ||((u1RankIdx == TO_ALL_RANK) && (p->support_rank_num == RANK_DUAL)))
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), P_Fld(u1CKEOff, CKECTRL_CKE1FIXOFF)
+                                                                | P_Fld(u1CKEOn, CKECTRL_CKE1FIXON));
+        }
+    }
+}
+
+
+void vAutoRefreshSwitch(DRAMC_CTX_T *p, U8 option)
+{
+    if (option == ENABLE)
+    {
+        //enable autorefresh
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 0, REFCTRL0_REFDIS);      //REFDIS=0, enable auto refresh
+    }
+    else    // DISABLE
+    {
+        //disable autorefresh
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 1, REFCTRL0_REFDIS);      //REFDIS=1, disable auto refresh
+
+        //because HW will actually disable autorefresh after refresh_queue empty, so we need to wait quene empty.
+        mcDELAY_US(u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_REFRESH_QUEUE_CNT) * 4);   //wait refresh_queue_cnt * 3.9us
+    }
+}
+
+
+//-------------------------------------------------------------------------
+/** vCKERankCtrl
+ *  Control CKE toggle mode (toggle both ranks 1. at the same time (CKE_RANK_DEPENDENT) 2. individually (CKE_RANK_INDEPENDENT))
+ *  Note: Sets CKE toggle mode for all channels
+ *  @param p                Pointer of context created by DramcCtxCreate.
+ *  @param CKECtrlMode      Indicates
+ */
+//-------------------------------------------------------------------------
+void vCKERankCtrl(DRAMC_CTX_T *p, CKE_CTRL_MODE_T CKECtrlMode)
+{
+    /* Struct indicating all register fields mentioned in "multi rank CKE control" */
+    typedef struct
+    {
+        U8 u1CKE2Rank: Fld_wid(RKCFG_CKE2RANK);
+        U8 u1CKE2Rank_Opt :Fld_wid(CKECTRL_CKE2RANK_OPT);
+        U8 u1CKE2Rank_Opt2 :Fld_wid(CKECTRL_CKE2RANK_OPT2);
+        U8 u1CKE2Rank_Opt3: Fld_wid(CKECTRL_CKE2RANK_OPT3);
+        U8 u1CKE2Rank_Opt5: Fld_wid(CKECTRL_CKE2RANK_OPT5);
+        U8 u1CKE2Rank_Opt6: Fld_wid(CKECTRL_CKE2RANK_OPT6);
+        U8 u1CKE2Rank_Opt7: Fld_wid(CKECTRL_CKE2RANK_OPT7);
+        U8 u1CKE2Rank_Opt8: Fld_wid(CKECTRL_CKE2RANK_OPT8);
+        U8 u1CKETimer_Sel: Fld_wid(CKECTRL_CKETIMER_SEL);
+        U8 u1FASTWake: Fld_wid(SHU_DCM_CTRL0_FASTWAKE);
+        U8 u1FASTWake2: Fld_wid(SHU_DCM_CTRL0_FASTWAKE2);
+        U8 u1FastWake_Sel: Fld_wid(CKECTRL_FASTWAKE_SEL);
+        U8 u1CKEWake_Sel: Fld_wid(CKECTRL_CKEWAKE_SEL);
+        U8 u1ClkWiTrfc: Fld_wid(ACTIMING_CTRL_CLKWITRFC);
+    } CKE_CTRL_T;
+
+    /* CKE_Rank dependent/independent mode register setting values */
+    CKE_CTRL_T CKE_Mode, CKE_Rank_Independent = { .u1CKE2Rank = 0, .u1CKE2Rank_Opt3 = 0, .u1CKE2Rank_Opt2 = 1,
+                                                  .u1CKE2Rank_Opt5 = 0, .u1CKE2Rank_Opt6 = 0, .u1CKE2Rank_Opt7 = 1, .u1CKE2Rank_Opt8 = 0,
+                                                  .u1CKETimer_Sel = 0, .u1FASTWake = 1, .u1FASTWake2 = 1, .u1FastWake_Sel = 1, .u1CKEWake_Sel = 0, .u1ClkWiTrfc = 0
+                                                },
+                         CKE_Rank_Dependent = { .u1CKE2Rank = 1, .u1CKE2Rank_Opt3 = 0,
+                                                .u1CKE2Rank_Opt5 = 0, .u1CKE2Rank_Opt6 = 0, .u1CKE2Rank_Opt7 = 0, .u1CKE2Rank_Opt8 = 0, .u1CKETimer_Sel = 1,
+                                                .u1FASTWake = 1, .u1FASTWake2 = 0, .u1FastWake_Sel = 0, .u1CKEWake_Sel = 0, .u1ClkWiTrfc = 0
+                                              };
+    //Select CKE control mode
+    CKE_Mode = (CKECtrlMode == CKE_RANK_INDEPENDENT)? CKE_Rank_Independent: CKE_Rank_Dependent;
+
+    //Apply CKE control mode register settings
+    vIO32WriteFldAlign_All(DRAMC_REG_RKCFG, CKE_Mode.u1CKE2Rank, RKCFG_CKE2RANK);
+    vIO32WriteFldMulti_All(DRAMC_REG_CKECTRL, P_Fld(CKE_Mode.u1CKE2Rank_Opt3, CKECTRL_CKE2RANK_OPT3)
+                    | P_Fld(CKE_Mode.u1CKE2Rank_Opt, CKECTRL_CKE2RANK_OPT)
+                    | P_Fld(CKE_Mode.u1CKE2Rank_Opt2, CKECTRL_CKE2RANK_OPT2)
+                    | P_Fld(CKE_Mode.u1CKE2Rank_Opt5, CKECTRL_CKE2RANK_OPT5)
+                    | P_Fld(CKE_Mode.u1CKE2Rank_Opt6, CKECTRL_CKE2RANK_OPT6)
+                    | P_Fld(CKE_Mode.u1CKE2Rank_Opt7, CKECTRL_CKE2RANK_OPT7)
+                    | P_Fld(CKE_Mode.u1CKE2Rank_Opt8, CKECTRL_CKE2RANK_OPT8)
+                    | P_Fld(CKE_Mode.u1CKETimer_Sel, CKECTRL_CKETIMER_SEL)
+                    | P_Fld(CKE_Mode.u1FastWake_Sel, CKECTRL_FASTWAKE_SEL)
+                    | P_Fld(CKE_Mode.u1CKEWake_Sel, CKECTRL_CKEWAKE_SEL));
+
+    vIO32WriteFldMulti_All(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(CKE_Mode.u1FASTWake, SHU_DCM_CTRL0_FASTWAKE) | P_Fld(CKE_Mode.u1FASTWake2, SHU_DCM_CTRL0_FASTWAKE2));
+
+    vIO32WriteFldAlign_All(DRAMC_REG_ACTIMING_CTRL, CKE_Mode.u1ClkWiTrfc, ACTIMING_CTRL_CLKWITRFC);
+}
+
+
+#define MAX_CMP_CPT_WAIT_LOOP 100000   // max loop
+static void DramcSetRWOFOEN(DRAMC_CTX_T *p, U8 u1onoff)
+{
+    U32 u4loop_count = 0;
+
+    {
+        while(u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_REQQ_EMPTY) != 1)
+        {
+            mcDELAY_US(1);
+            u4loop_count ++;
+
+            if(u4loop_count > MAX_CMP_CPT_WAIT_LOOP)
+            {
+                mcSHOW_ERR_MSG(("RWOFOEN timout! queue is not empty\n"));
+            #if __ETT__
+                while(1);
+            #else
+                break;
+            #endif
+            }
+        }
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SCHEDULER_COM), u1onoff, SCHEDULER_COM_RWOFOEN);
+    }
+}
+
+
+//static void DramcEngine2CleanWorstSiPattern(DRAMC_CTX_T *p)
+//{
+//    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
+//            P_Fld(0, TEST2_A3_AUTO_GEN_PAT) |
+//            P_Fld(0, TEST2_A3_HFIDPAT) |
+//            P_Fld(0, TEST2_A3_TEST_AID_EN));
+//}
+
+
+static void DramcEngine2SetUiShift(DRAMC_CTX_T *p, U8 option)//UI shift function
+{
+    if(option == ENABLE)
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0),
+                P_Fld(1, TEST2_A0_TA2_LOOP_EN) |
+                P_Fld(3, TEST2_A0_LOOP_CNT_INDEX));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
+                P_Fld(1, TEST2_A3_TEST2_PAT_SHIFT) |
+                P_Fld(0, TEST2_A3_PAT_SHIFT_SW_EN));
+    }
+    else
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0),
+                P_Fld(0, TEST2_A0_TA2_LOOP_EN) |
+                P_Fld(0, TEST2_A0_LOOP_CNT_INDEX));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
+                P_Fld(0, TEST2_A3_TEST2_PAT_SHIFT));
+    }
+}
+
+
+void DramcSetRankEngine2(DRAMC_CTX_T *p, U8 u1RankSel)
+{
+    //LPDDR2_3_ADRDECEN_TARKMODE =0, always rank0
+    /* ADRDECEN_TARKMODE: rank input selection
+     *   1'b1 select CTO_AGENT1_RANK, 1'b0 rank by address decode
+     */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), 1, TEST2_A3_ADRDECEN_TARKMODE);
+
+    // DUMMY_TESTAGENTRKSEL =0, select rank according to CATRAIN_TESTAGENTRK
+    /* TESTAGENTRKSEL: Test agent access rank mode selection
+     * 2'b00: rank selection by TESTAGENTRK,           2'b01: rank selection by CTO_AGENT_1_BK_ADR[0]
+     * 2'b10: rank selection by CTO_AGENT1_COL_ADR[3], 2'b11: rank selection by CTO_AGENT1_COL_ADR[4]
+     */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), 0, TEST2_A4_TESTAGENTRKSEL);
+
+    //CATRAIN_TESTAGENTRK = u1RankSel
+    /* TESTAGENTRK: Specify test agent rank
+     * 2'b00 rank 0, 2'b01 rank 1, 2'b10 rank 2
+     */
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), u1RankSel, TEST2_A4_TESTAGENTRK);
+}
+
+
+void DramcEngine2SetPat(DRAMC_CTX_T *p, U8 u1TestPat, U8 u1LoopCnt, U8 u1Len1Flag, U8 u1EnableUiShift) //u1LoopCnt is related to rank
+{
+
+    if ((u1TestPat == TEST_XTALK_PATTERN) || (u1TestPat == TEST_SSOXTALK_PATTERN)) //xtalk or SSO+XTALK
+    {
+        //TEST_REQ_LEN1=1 is new feature, hope to make dq bus continously.
+        //but DV simulation will got problem of compare err
+        //so go back to use old way
+        //TEST_REQ_LEN1=0, R_DMRWOFOEN=1
+        if (u1Len1Flag != 0)
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
+                    P_Fld(1, TEST2_A4_TEST_REQ_LEN1)); //test agent 2 with cmd length = 0, LEN1 of 256bits data
+            DramcSetRWOFOEN(p, 0); //@IPM will fix for LEN1=1 issue
+
+        }
+        else
+        {
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
+                    P_Fld(0, TEST2_A4_TEST_REQ_LEN1)); //test agent 2 with cmd length = 0
+            DramcSetRWOFOEN(p, 1);
+        }
+
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
+                P_Fld(0, TEST2_A3_AUTO_GEN_PAT) |
+                P_Fld(0, TEST2_A3_HFIDPAT) |
+                P_Fld(0, TEST2_A3_TEST_AID_EN) |
+                P_Fld(0, TEST2_A3_TESTAUDPAT) |
+                P_Fld(u1LoopCnt, TEST2_A3_TESTCNT)); //dont use audio pattern
+
+        if (u1TestPat == TEST_SSOXTALK_PATTERN)
+        {
+            //set addr 0x48[16] to 1, TESTXTALKPAT = 1
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
+                    P_Fld(1, TEST2_A4_TESTXTALKPAT) |
+                    P_Fld(0, TEST2_A4_TESTAUDMODE) |
+                    P_Fld(0, TEST2_A4_TESTAUDBITINV)); //use XTALK pattern, dont use audio pattern
+
+            //R_DMTESTSSOPAT=0, R_DMTESTSSOXTALKPAT=0
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
+                    P_Fld(1, TEST2_A4_TESTSSOPAT) |
+                    P_Fld(0, TEST2_A4_TESTSSOXTALKPAT)); //dont use sso, sso+xtalk pattern
+        }
+        else //select XTALK pattern
+        {
+            //set addr 0x48[16] to 1, TESTXTALKPAT = 1
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
+                    P_Fld(1, TEST2_A4_TESTXTALKPAT) |
+                    P_Fld(0, TEST2_A4_TESTAUDMODE) |
+                    P_Fld(0, TEST2_A4_TESTAUDBITINV)); //use XTALK pattern, dont use audio pattern
+
+            //R_DMTESTSSOPAT=0, R_DMTESTSSOXTALKPAT=0
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
+                    P_Fld(0, TEST2_A4_TESTSSOPAT) |
+                    P_Fld(0, TEST2_A4_TESTSSOXTALKPAT)); //dont use sso, sso+xtalk pattern
+        }
+    }
+    else if (u1TestPat == TEST_AUDIO_PATTERN) //AUDIO
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
+                P_Fld(0, TEST2_A4_TEST_REQ_LEN1));   //test agent 2 with cmd length = 0
+        // set AUDINIT=0x11 AUDINC=0x0d AUDBITINV=1 AUDMODE=1(1:read only(address fix), 0: write/read address change)
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
+                P_Fld(0x00000011, TEST2_A4_TESTAUDINIT) |
+                P_Fld(0x0000000d, TEST2_A4_TESTAUDINC) |
+                P_Fld(0, TEST2_A4_TESTXTALKPAT) |
+                P_Fld(0, TEST2_A4_TESTAUDMODE) |
+                P_Fld(1, TEST2_A4_TESTAUDBITINV));
+
+        // set addr 0x044 [7] to 1 ,select audio pattern
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
+                P_Fld(0, TEST2_A3_AUTO_GEN_PAT) |
+                P_Fld(0, TEST2_A3_HFIDPAT) |
+                P_Fld(0, TEST2_A3_TEST_AID_EN) |
+                P_Fld(1, TEST2_A3_TESTAUDPAT) |
+                P_Fld(u1LoopCnt, TEST2_A3_TESTCNT));
+    }
+    else if (u1TestPat == TEST_WORST_SI_PATTERN) //TEST2_OFF > 'h56
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
+                P_Fld(u1Len1Flag, TEST2_A4_TEST_REQ_LEN1)|
+                P_Fld(0, TEST2_A4_TESTAUDINIT) |
+                P_Fld(0, TEST2_A4_TESTAUDINC) |
+                P_Fld(0, TEST2_A4_TESTXTALKPAT) |
+                P_Fld(0, TEST2_A4_TESTSSOPAT)
+                );
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
+                P_Fld(0, TEST2_A3_TESTAUDPAT) |
+                P_Fld(1, TEST2_A3_AUTO_GEN_PAT) |
+                P_Fld(1, TEST2_A3_HFIDPAT) |
+                P_Fld(1, TEST2_A3_TEST_AID_EN) |
+                P_Fld(u1LoopCnt, TEST2_A3_TESTCNT)
+                );
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x56, TEST2_A2_TEST2_OFF);//Set to min value to save time;
+    }
+    else //ISI
+    {
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
+                P_Fld(0, TEST2_A4_TEST_REQ_LEN1)); //test agent 2 with cmd length = 0
+
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
+                P_Fld(0, TEST2_A3_AUTO_GEN_PAT) |
+                P_Fld(0, TEST2_A3_HFIDPAT) |
+                P_Fld(0, TEST2_A3_TEST_AID_EN) |
+                P_Fld(0, TEST2_A3_TESTAUDPAT) |
+                P_Fld(u1LoopCnt, TEST2_A3_TESTCNT));
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), 0, TEST2_A4_TESTXTALKPAT);
+    }
+
+    DramcEngine2SetUiShift(p, u1EnableUiShift); //Enalbe/Disable UI shift
+}
+
+#define CMP_CPT_POLLING_PERIOD 1       // timeout for TE2: (CMP_CPT_POLLING_PERIOD X MAX_CMP_CPT_WAIT_LOOP)
+#define MAX_CMP_CPT_WAIT_LOOP 100000   // max loop
+static void DramcEngine2CheckComplete(DRAMC_CTX_T *p, U8 u1status)
+{
+    U32 u4loop_count = 0;
+    U32 u4Ta2_loop_count = 0;
+    U32 u4ShiftUiFlag = 0;//Use TEST_WORST_SI_PATTERN_UI_SHIFT
+
+    while ((u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) & u1status) != u1status)
+    {
+        mcDELAY_US(CMP_CPT_POLLING_PERIOD);
+        u4loop_count++;
+        if ((u4loop_count > 3) && (u4loop_count <= MAX_CMP_CPT_WAIT_LOOP))
+        {
+            //mcSHOW_ERR_MSG(("TESTRPT_DM_CMP_CPT: %d\n", u4loop_count));
+        }
+        else if (u4loop_count > MAX_CMP_CPT_WAIT_LOOP)
+        {
+            /*TINFO="fcWAVEFORM_MEASURE_A %d: time out\n", u4loop_count*/
+            mcSHOW_ERR_MSG(("fcWAVEFORM_MEASURE_A %d :time out, [22:20]=0x%x\n", u4loop_count, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT)));
+
+            //mcFPRINTF((fp_A60501, "fcWAVEFORM_MEASURE_A %d: time out\n", u4loop_count));
+
+            break;
+        }
+    }
+
+    u4loop_count = 0;
+    u4ShiftUiFlag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), TEST2_A3_TEST2_PAT_SHIFT);
+    if(u4ShiftUiFlag)//Use TEST_WORST_SI_PATTERN_UI_SHIFT
+    {
+        while ((u4Ta2_loop_count = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_LOOP_CNT))) != 8)
+        {
+            u4loop_count++;
+            if(u4loop_count > MAX_CMP_CPT_WAIT_LOOP)
+            {
+                mcSHOW_ERR_MSG(("over MAX_CMP_CPT_WAIT_LOOP[%d] TEST_LOOP_CNT[%d]\n", u4loop_count, u4Ta2_loop_count));
+                break;
+            }
+        }
+    }
+}
+
+static U32 DramcEngine2Compare(DRAMC_CTX_T *p, DRAM_TE_OP_T wr)
+{
+    U32 u4result = 0xffffffff;
+    U32 u4loopcount;
+    U8  u1status = 1; //RK0
+    U32 u4ShiftUiFlag = 0;
+
+    u4loopcount = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), TEST2_A3_TESTCNT);
+    if (u4loopcount == 1)
+        u1status = 3; //RK0/1
+
+    u4ShiftUiFlag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), TEST2_A3_TEST2_PAT_SHIFT);
+
+    if (wr == TE_OP_WRITE_READ_CHECK)
+    {
+        if(!u4ShiftUiFlag)//Could not use while UI shift is open
+        {
+            // read data compare ready check
+            DramcEngine2CheckComplete(p, u1status);
+
+            // disable write
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
+                    P_Fld(0, TEST2_A3_TEST2W) |
+                    P_Fld(0, TEST2_A3_TEST2R) |
+                    P_Fld(0, TEST2_A3_TEST1));
+
+            mcDELAY_US(1);
+
+            // enable read
+            vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
+                    P_Fld(0, TEST2_A3_TEST2W) |
+                    P_Fld(1, TEST2_A3_TEST2R) |
+                    P_Fld(0, TEST2_A3_TEST1));
+        }
+    }
+
+    // 5
+    // read data compare ready check
+    DramcEngine2CheckComplete(p, u1status);
+
+    // delay 10ns after ready check from DE suggestion (1ms here)
+    //mcDELAY_US(1);
+
+    u4result = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) >> 4) & u1status; //CMP_ERR_RK0/1
+
+    return u4result;
+}
+
+//-------------------------------------------------------------------------
+/** DramcEngine2
+ *  start the self test engine 2 inside dramc to test dram w/r.
+ *  @param p                Pointer of context created by DramcCtxCreate.
+ *  @param  wr              (DRAM_TE_OP_T): TE operation
+ *  @param  test2_1         (U32): 28bits,base address[27:0].
+ *  @param  test2_2         (U32): 28bits,offset address[27:0]. (unit is 16-byte, i.e: 0x100 is 0x1000).
+ *  @param  loopforever     (S16): 0    read\write one time ,then exit
+ *                                >0 enable eingie2, after "loopforever" second ,write log and exit
+ *                                -1 loop forever to read\write, every "period" seconds ,check result ,only when we find error,write log and exit
+ *                                -2 loop forever to read\write, every "period" seconds ,write log ,only when we find error,write log and exit
+ *                                -3 just enable loop forever ,then exit
+ *  @param period           (U8):  it is valid only when loopforever <0; period should greater than 0
+ *  @param u1LoopCnt    (U8): test loop number of test agent2 loop number =2^(u1LoopCnt) ,0 one time
+ *  @retval status          (U32): return the value of DM_CMP_ERR  ,0  is ok ,others mean  error
+ */
+//-------------------------------------------------------------------------
+static U32 uiReg0D0h;
+DRAM_STATUS_T DramcEngine2Init(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1TestPat, U8 u1LoopCnt, U8 u1EnableUiShift)
+{
+    U8 u1Len1Flag;
+
+    // error handling
+    if (!p)
+    {
+        mcSHOW_ERR_MSG(("context is NULL\n"));
+        return DRAM_FAIL;
+    }
+
+    // check loop number validness
+//    if ((u1LoopCnt > 15) || (u1LoopCnt < 0))      // U8 >=0 always.
+    if (u1LoopCnt > 15)
+    {
+        mcSHOW_ERR_MSG(("wrong param: u1LoopCnt > 15\n"));
+        return DRAM_FAIL;
+    }
+
+    u1Len1Flag = (u1TestPat & 0x80) >> 7;
+    u1TestPat = u1TestPat & 0x7f;
+
+    DramcSetRankEngine2(p, p->rank);
+
+    uiReg0D0h = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD),
+            P_Fld(0, DUMMY_RD_DQSG_DMYRD_EN) |
+            P_Fld(0, DUMMY_RD_DQSG_DMYWR_EN) |
+            P_Fld(0, DUMMY_RD_DUMMY_RD_EN) |
+            P_Fld(0, DUMMY_RD_SREF_DMYRD_EN) |
+            P_Fld(0, DUMMY_RD_DMY_RD_DBG) |
+            P_Fld(0, DUMMY_RD_DMY_WR_DBG));  //must close dummy read when do test agent
+
+    //fixme-zj vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTCHIP_DMA1), 0, TESTCHIP_DMA1_DMA_LP4MATAB_OPT);
+
+    // disable self test engine1 and self test engine2
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
+            P_Fld(0, TEST2_A3_TEST2W) |
+            P_Fld(0, TEST2_A3_TEST2R) |
+            P_Fld(0, TEST2_A3_TEST1));
+
+    // 1.set pattern ,base address ,offset address
+    // 2.select  ISI pattern or audio pattern or xtalk pattern
+    // 3.set loop number
+    // 4.enable read or write
+    // 5.loop to check DM_CMP_CPT
+    // 6.return CMP_ERR
+    // currently only implement ucengine_status = 1, others are left for future extension
+
+    // 1
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0),
+            P_Fld(test2_1 >> 24, TEST2_A0_TEST2_PAT0) |
+            P_Fld(test2_2 >> 24, TEST2_A0_TEST2_PAT1));
+
+#if (__LP5_COMBO__ == TRUE)
+    if (TRUE == is_lp5_family(p))
+    {
+        // LP5 TA2 base: 0x0
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1),
+                test2_1 & 0x00ffffff, RK_TEST2_A1_TEST2_BASE);
+    }
+    else
+#endif
+    {
+        // LP4 TA2 base: 0x10000. It's only TBA constrain, but not HW.
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1),
+                (test2_1 + 0x10000) & 0x00ffffff, RK_TEST2_A1_TEST2_BASE);
+    }
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2),
+            test2_2 & 0x00ffffff, TEST2_A2_TEST2_OFF);
+
+    // 2 & 3
+    // (TESTXTALKPAT, TESTAUDPAT) = 00 (ISI), 01 (AUD), 10 (XTALK), 11 (UNKNOWN)
+    DramcEngine2SetPat(p, u1TestPat, u1LoopCnt, u1Len1Flag, u1EnableUiShift);
+
+    return DRAM_OK;
+}
+
+
+U32 DramcEngine2Run(DRAMC_CTX_T *p, DRAM_TE_OP_T wr, U8 u1TestPat)
+{
+    U32 u4result = 0xffffffff;
+
+    // 4
+    if (wr == TE_OP_READ_CHECK)
+    {
+        if ((u1TestPat == 1) || (u1TestPat == 2))
+        {
+            //if audio pattern, enable read only (disable write after read), AUDMODE=0x48[15]=0
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), 0, TEST2_A4_TESTAUDMODE);
+        }
+
+        // enable read, 0x008[31:29]
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
+                P_Fld(0, TEST2_A3_TEST2W) |
+                P_Fld(1, TEST2_A3_TEST2R) |
+                P_Fld(0, TEST2_A3_TEST1));
+    }
+    else if (wr == TE_OP_WRITE_READ_CHECK)
+    {
+        // enable write
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
+                P_Fld(1, TEST2_A3_TEST2W) |
+                P_Fld(0, TEST2_A3_TEST2R) |
+                P_Fld(0, TEST2_A3_TEST1));
+    }
+    DramcEngine2Compare(p, wr);
+
+    // delay 10ns after ready check from DE suggestion (1ms here)
+    mcDELAY_US(1);
+
+    // 6
+    // return CMP_ERR, 0 is ok ,others are fail,diable test2w or test2r
+    // get result
+    // or all result
+    u4result = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR)));
+
+    // disable read
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3),
+            P_Fld(0, TEST2_A3_TEST2W) |
+            P_Fld(0, TEST2_A3_TEST2R) |
+            P_Fld(0, TEST2_A3_TEST1));
+
+    return u4result;
+}
+
+void DramcEngine2End(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4),
+            P_Fld(0, TEST2_A4_TEST_REQ_LEN1));   //test agent 2 with cmd length = 0
+    DramcSetRWOFOEN(p, 1);
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), uiReg0D0h);
+}
+#if 0
+// Full set of usage test engine 2, including of DramcEngine2Init->DramcEngine2Run->DramcEngine2End
+// if you don't care the performance, and just for convinent, you may use this API (TestEngineCompare)
+static U32 TestEngineCompare(DRAMC_CTX_T *p)
+{
+    U8 jj;
+    U32 u4err_value;
+
+    if (p->test_pattern <= TEST_XTALK_PATTERN)
+    {
+        DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern, 0, TE_NO_UI_SHIFT);
+        u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, p->test_pattern);
+        DramcEngine2End(p);
+    }
+    else if (p->test_pattern == TEST_MIX_PATTERN)
+    {
+        DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_AUDIO_PATTERN, 0, TE_NO_UI_SHIFT);
+        u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN);
+        DramcEngine2End(p);
+
+        DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT);
+        u4err_value |= DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN);
+        DramcEngine2End(p);
+    }
+    else
+    {
+        mcSHOW_ERR_MSG(("Test pattern error! Using default xtalk pattern\n"));
+        DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT);
+        u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN);
+        DramcEngine2End(p);
+    }
+    return u4err_value;
+}
+#endif
+#if (fcFOR_CHIP_ID == fcA60868)
+    #define EMI_APB_BASE    0x10219000
+#elif (fcFOR_CHIP_ID == fc8195)
+    #define EMI_APB_BASE    0x10219000///TODO:Darren confirm
+    //#define SUB_EMI_APB_BASE    0x1021D000
+    // 0x10219000 for CH0/1
+    // 0x1021D000 for CH2/3
+#endif
+
+U8 u1MaType = 0x2; // for DV sim
+void TA2_Test_Run_Time_HW_Set_Column_Num(DRAMC_CTX_T * p)
+{
+    U8 u1ChannelIdx = 0;
+    U8 u1EmiChIdx = 0;
+    U32 u4matypeR0 = 0, u4matypeR1 = 0;
+    U32 u4matype = 0;
+    U32 u4EmiOffset = 0;
+    DRAM_CHANNEL_T eOriChannel = p->channel;
+
+    for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1ChannelIdx);
+
+        u4EmiOffset = 0;
+        u1EmiChIdx = u1ChannelIdx;
+#if (CHANNEL_NUM > 2)
+	if (channel_num_auxadc > 2) {
+        if (u1ChannelIdx >= CHANNEL_C)
+        {
+            u4EmiOffset = 0x4000; // 0x1021D000 for CH2/3
+            u1EmiChIdx = u1ChannelIdx-2;
+        }
+		}
+#endif
+
+        u4matype = u4IO32Read4B(EMI_APB_BASE + u4EmiOffset);
+        u4matypeR0 = ((u4matype >> (4 + u1EmiChIdx * 16)) & 0x3) + 1; //refer to init_ta2_single_channel()
+        u4matypeR1 = ((u4matype >> (6 + u1EmiChIdx * 16)) & 0x3) + 1; //refer to init_ta2_single_channel()
+
+        if(p->support_rank_num==RANK_SINGLE)
+        {
+            u4matype = u4matypeR0;
+        }
+        else
+        {
+            u4matype = (u4matypeR0 > u4matypeR1) ? u4matypeR1 : u4matypeR0; //get min value
+        }
+        //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MATYPE), u4matype, MATYPE_MATYPE);
+    }
+    vSetPHY2ChannelMapping(p, eOriChannel);
+    u1MaType = u4matype;
+
+    return;
+}
+
+/* ----------------------------------------------------------------------
+ * LP4 RG Address
+ * bit:   3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
+ *        1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ *        ---------------------------------------------------------------
+ * RG:    - - R R R R R R R R R R R R R R R R R R|B B B|C C C C C C - - -
+ * 2_BASE     1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0|A A A|9 8 7 6 5 4
+ *            7 6 5 4 3 2 1 0                    |2 1 0|
+ * AXI    ---------------------------------------------------------------
+ * Addr:    R R R R R R R R R R R R R R R R|B B B|C C C|C|C C C C C C C -
+ *          1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0|A A A|9 8 7|H|6 5 4 3 2 1 0
+ *          5 4 3 2 1 0                    |2 1 0|     | |
+ * ----------------------------------------------------------------------
+ */
+#define TA2_RANK0_ADDRESS   (0x40200000)
+#define AXI_CHAN_BIT_WIDTH 1 //2: 4_channel 1: 2_channel
+#define OFFSET_OF_RG_BASE_AND_AXI 2
+#define LEN1_INTRINSIC_OFFSET 2
+#if FOR_DV_SIMULATION_USED
+#define TRANSFER_DRAM_ADDR_BY_EMI_API 0 // @ tg add to fix simulation compile error
+#else
+#define TRANSFER_DRAM_ADDR_BY_EMI_API 1 //1: by emi API 0: by above table
+#endif
+void TA2_Test_Run_Time_HW_Presetting(DRAMC_CTX_T * p, U32 len, TA2_RKSEL_TYPE_T rksel_mode)/* Should call after TA2_Test_Run_Time_Pat_Setting() */
+{
+    DRAM_CHANNEL_T eOriChannel = p->channel;
+    DRAM_RANK_T eOriRank = p->rank;
+    U32 u4BaseR0, u4BaseR1, u4Offset, u4Addr;
+    U32 u4matypeR0, u4matypeR1, u4LEN1;
+    U8 u1ChannelIdx, uiRWOFOEN, u1RkIdx;
+
+    u4Addr = TA2_RANK0_ADDRESS & 0x1fffffff;
+    if (u1IsLP4Family(p->dram_type))
+    {
+#if TRANSFER_DRAM_ADDR_BY_EMI_API
+        {
+            dram_addr_t dram_addr;
+            unsigned long long ull_axi_addr = TA2_RANK0_ADDRESS;
+
+            memset(&dram_addr, 0, sizeof(dram_addr));
+            phy_addr_to_dram_addr(&dram_addr, ull_axi_addr); //Make sure row. bank. column are correct
+            u4BaseR0 = ((dram_addr.row << 12) | (dram_addr.bk << 9) | (dram_addr.col >> 1)) >> 3;// >>1: RG C4 @3th bit >>3: RG start with bit 3
+        }
+#else
+        // >>AXI_CHAN_BIT_WIDTH: drop bit8; >>OFFSET_OF_RG_BASE_AND_AXI: align with RG row; >>3: RG start with bit 3
+        u4BaseR0 = (((u4Addr & ~0x1ff) >> AXI_CHAN_BIT_WIDTH) | (u4Addr & 0xff)) >> (OFFSET_OF_RG_BASE_AND_AXI + 3);
+#endif
+        //mcSHOW_DBG_MSG(("===u4BaseR0 = 0x%x\n", u4BaseR0));
+
+        u4Offset = len >> (AXI_CHAN_BIT_WIDTH + 5);//5:0x20 bytes(256 bits) address coverage per pattern(128 bits data + 128 bits bubble); offset should bigger than 0xFF
+    }
+    else
+    {
+        u4BaseR0 = u4Addr >> 4;
+        if (rksel_mode == TA2_RKSEL_XRT)
+        {
+            u4Offset = len >> 4;//16B per pattern
+        }
+        else
+        {
+            u4Offset = (len >> 4) >> 1;//16B per pattern //len should be >>2 or test engine will time out
+        }
+    }
+    u4BaseR1 = u4BaseR0;
+
+    u4matypeR0 = ((u4IO32Read4B(EMI_APB_BASE) >> 4) & 0x3) + 1;
+    u4matypeR1 = ((u4IO32Read4B(EMI_APB_BASE) >> 6) & 0x3) + 1;
+    if (u4matypeR0 != u4matypeR1)//R0 R1 mix mode
+    {
+        (u4matypeR0 > u4matypeR1)? (u4BaseR0 >>= 1): (u4BaseR1 >>= 1);//set the correct start address, refer to mapping table
+        u4Offset >>= 1;//set min value
+    }
+
+    u4Offset = (u4Offset == 0) ? 1 : u4Offset; //halt if u4Offset = 0
+
+    u4LEN1 = u4IO32ReadFldAlign(DRAMC_REG_TEST2_A4, TEST2_A4_TEST_REQ_LEN1);
+    if(u4LEN1)
+    {
+        u4Offset = u4Offset - LEN1_INTRINSIC_OFFSET;
+    }
+
+#if ENABLE_EMI_LPBK_TEST && EMI_USE_TA2
+    if (gEmiLpbkTest)
+    {
+        u4matypeR0 = 2;
+        u4matypeR1 = 2;
+        u4Offset = 3;
+        //u4Offset = 6;//3; //6: for emilpbk_dq_dvs_leadlag_toggle_ringcnt
+    }
+#endif
+
+    if (TA2_RKSEL_XRT == rksel_mode)
+    {
+        // In order to enhance XRT R2R/W2W probability, use TEST2_4_TESTAGENTRKSEL=3, PERFCTL0_RWOFOEN=0 mode
+        uiRWOFOEN = 0;
+        mcSHOW_DBG_MSG2(("=== TA2 XRT R2R/W2W\n"));
+    }
+    else
+    {
+        uiRWOFOEN = 1;
+#if !ENABLE_EMI_LPBK_TEST
+        mcSHOW_DBG_MSG2(("=== TA2 HW\n"));
+#endif
+    }
+#if !ENABLE_EMI_LPBK_TEST
+    mcSHOW_DBG_MSG2(("=== OFFSET:0x%x\n", u4Offset));
+#endif
+    for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
+    {
+        p->channel = (DRAM_CHANNEL_T)u1ChannelIdx;
+
+        for(u1RkIdx = 0; u1RkIdx < p->support_rank_num; u1RkIdx++)
+        {
+            p->rank = (DRAM_RANK_T)u1RkIdx;
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), u4BaseR0, RK_TEST2_A1_TEST2_BASE);//fill based on RG table for Rank 0
+        }
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), u4Offset, TEST2_A2_TEST2_OFF);//128 bits data length per offest
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), rksel_mode, TEST2_A4_TESTAGENTRKSEL);
+        DramcSetRWOFOEN(p, uiRWOFOEN);
+    }
+    p->channel = eOriChannel;
+    p->rank = eOriRank;
+    //TA2_Test_Run_Time_HW_Set_Column_Num(p);
+
+    return;
+}
+#if ETT_MINI_STRESS_USE_TA2_LOOP_MODE
+#define TA2_PAT TEST_WORST_SI_PATTERN
+#else
+#define TA2_PAT TEST_XTALK_PATTERN
+#endif
+
+void TA2_Test_Run_Time_Pat_Setting(DRAMC_CTX_T *p, U8 PatSwitch)
+{
+    static U8 u1Pat = TA2_PAT;
+    U8 u1ChannelIdx = 0;
+    DRAM_CHANNEL_T eOriChannel = p->channel;
+
+#if !ENABLE_EMI_LPBK_TEST
+    mcSHOW_DBG_MSG2(("TA2 PAT: %d\n", u1Pat));
+#endif
+    for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
+    {
+        p->channel = (DRAM_CHANNEL_T)u1ChannelIdx;
+        DramcEngine2SetPat(p, u1Pat, p->support_rank_num - 1, 0, TE_NO_UI_SHIFT);
+    }
+    p->channel = eOriChannel;
+
+    #if !ETT_MINI_STRESS_USE_TA2_LOOP_MODE
+    {
+        U32 u4Value = 0;
+        u4Value = (u1Pat == TEST_WORST_SI_PATTERN) ? 1 : 0; //Worst SI pattern + loop mode + LEN1
+        vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, u4Value, TEST2_A0_TA2_LOOP_EN);
+        vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, u4Value, TEST2_A0_LOOP_NV_END);
+        vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, u4Value, TEST2_A0_ERR_BREAK_EN);
+        vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, u4Value, TEST2_A4_TEST_REQ_LEN1);
+    }
+    #endif
+
+    if (PatSwitch)
+        u1Pat = (u1Pat + 1) % 4;
+
+    return;
+}
+#if 0
+static void TA2_Test_Run_Time_HW_Read(DRAMC_CTX_T * p, U8 u1Enable)
+{
+    DRAM_CHANNEL_T eOriChannel = p->channel;
+    U8 u1ChannelIdx;
+
+    mcSHOW_DBG_MSG2(("\nTA2 Trigger Read\n"));
+    for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
+    {
+        p->channel = (DRAM_CHANNEL_T)u1ChannelIdx;
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), u1Enable, TEST2_A3_TEST2R);
+    }
+    p->channel = eOriChannel;
+    return;
+}
+#endif
+void TA2_Test_Run_Time_HW_Write(DRAMC_CTX_T * p, U8 u1Enable)
+{
+    DRAM_CHANNEL_T eOriChannel = p->channel;
+    U8 u1ChannelIdx;
+
+#if !ENABLE_EMI_LPBK_TEST
+    mcSHOW_DBG_MSG2(("\nTA2 Trigger Write\n"));
+#endif
+    for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
+    {
+        p->channel = (DRAM_CHANNEL_T)u1ChannelIdx;
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), u1Enable, TEST2_A3_TEST2W);
+    }
+    p->channel = eOriChannel;
+    return;
+}
+
+#if defined(RELEASE) && defined(DEVIATION)
+#undef mcSHOW_JV_LOG_MSG
+#define mcSHOW_JV_LOG_MSG(_x_)	opt_print _x_
+#endif
+static void TA2_Show_Cnt(DRAMC_CTX_T * p, U32 u4ErrorValue)
+{
+    static U32 err_count = 0;
+    static U32 pass_count = 0;
+    U8 u1RankIdx = 0;
+
+    for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)
+    {
+        if (u4ErrorValue & (1 << u1RankIdx))
+        {
+            err_count++;
+            mcSHOW_DBG_MSG2(("HW channel(%d) Rank(%d), TA2 failed, pass_cnt:%d, err_cnt:%d, err_bit:0x%x\n", p->channel, u1RankIdx, pass_count, err_count, u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR))));
+        }
+        else
+        {
+            pass_count++;
+            mcSHOW_DBG_MSG2(("HW channel(%d) Rank(%d), TA2 pass, pass_cnt:%d, err_cnt:%d\n", p->channel, u1RankIdx, pass_count, err_count));
+        }
+    }
+}
+
+
+#if ETT_MINI_STRESS_USE_TA2_LOOP_MODE
+#if 0
+static void TA2_Test_Run_Time_Stop_Loop_Mode(DRAMC_CTX_T * p)
+{
+    U8 u1ChannelIdx = 0;
+    U8 u1status = (p->support_rank_num == 2) ? 3 : 1; //3: 2 ranks; 1: 1 rank
+    U32 u4loop_count = 0;
+    DRAM_CHANNEL_T eOriChannel = p->channel;
+
+    for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1ChannelIdx);
+
+        //Step 1: set LOOP_NV_END=0
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), 0, TEST2_A0_LOOP_NV_END);
+
+        //Step 2: check TA2 status
+        while (((u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) & u1status) != u1status) || (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT)))
+        {
+            mcDELAY_US(CMP_CPT_POLLING_PERIOD);
+            u4loop_count++;
+            if ((u4loop_count > 3) && (u4loop_count <= MAX_CMP_CPT_WAIT_LOOP))
+            {
+                //mcSHOW_ERR_MSG(("TESTRPT_DM_CMP_CPT: %d\n", u4loop_count));
+            }
+            else if (u4loop_count > MAX_CMP_CPT_WAIT_LOOP)
+            {
+                mcSHOW_ERR_MSG(("fcWAVEFORM_MEASURE_A %d :time out, [22:20]=0x%x\n", u4loop_count, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT)));
+                break;
+            }
+        }
+
+        //Step 3: set TEST2W/TEST2R=0 and RG_TA2_LOOP_EN=0
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | P_Fld(0, TEST2_A3_TEST1));
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), 0, TEST2_A0_TA2_LOOP_EN);
+    }
+    vSetPHY2ChannelMapping(p, eOriChannel);
+}
+
+static void TA2_Test_Run_Time_Start_Loop_Mode(DRAMC_CTX_T *p)
+{
+    vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, 1, TEST2_A0_TA2_LOOP_EN);
+    vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, 1, TEST2_A0_LOOP_NV_END);
+    vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, 1, TEST2_A0_ERR_BREAK_EN);
+    vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 1, TEST2_A4_TEST_REQ_LEN1);
+}
+
+static U32 TA2_Test_Run_Time_Err_Status(DRAMC_CTX_T *p)
+{
+    static U32 err_count = 0;
+    static U32 pass_count = 0;
+    U32 u4Value = 0xffffffff;
+    U32 u4ErrorValue = 0;
+    U32 u4AllErrorValue = 0;
+    U8 u1ChannelIdx = 0;
+    DRAM_CHANNEL_T bkchannel = p->channel;
+
+    for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<(p->support_channel_num); u1ChannelIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1ChannelIdx);
+        u4ErrorValue = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) >> 4) & 0x3; //CMP_ERR_RK0/1
+        //mcSHOW_DBG_MSG(("CMP_ERR_RK0/1:0x%x ", u4ErrorValue));
+        TA2_Show_Cnt(p, u4ErrorValue);
+        u4AllErrorValue |= u4ErrorValue;
+
+        u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_LOOP_CNT)); //loop counter
+        mcSHOW_DBG_MSG2(("CH[%d] LOOP_CNT:0x%x \n", u1ChannelIdx, u4Value));
+    }
+    vSetPHY2ChannelMapping(p, bkchannel);
+    return u4AllErrorValue;
+}
+#endif
+U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p)
+{
+    U8 u1ChannelIdx = 0;
+    U32 u4ErrorValue = 0;
+    U32 bit_error = 0;
+    DRAM_CHANNEL_T eOriChannel = p->channel;
+
+    for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1ChannelIdx);
+        u4ErrorValue = DramcEngine2Compare(p, TE_OP_WRITE_READ_CHECK);
+
+        if (u4ErrorValue & 0x3) //RK0 or RK1 test fail
+        {
+            mcSHOW_DBG_MSG2(("=== HW channel(%d) u4ErrorValue: 0x%x, bit error: 0x%x\n", u1ChannelIdx, u4ErrorValue, u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR))));
+#if defined(SLT)
+            mcSHOW_ERR_MSG(("[dramc] DRAM_FATAL_ERR_FLAG = 0x00000001, line: %d\n",__LINE__));
+            while (1);
+#endif
+        }
+        TA2_Show_Cnt(p, u4ErrorValue);
+
+        bit_error |= u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | P_Fld(0, TEST2_A3_TEST1));
+    }
+    vSetPHY2ChannelMapping(p, eOriChannel);
+
+    return bit_error;
+}
+#else
+U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p)
+{
+    U8 u1ChannelIdx = 0;
+    U32 u4ErrorValue = 0;
+    U32 u4Ta2LoopEn = 0;
+    U32 u4loopcount = 0;
+    U8 u1status = 0;
+    U32 bit_error = 0;
+    static U32 err_count = 0;
+    static U32 pass_count = 0;
+    DRAM_CHANNEL_T eOriChannel = p->channel;
+
+    for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
+    {
+        vSetPHY2ChannelMapping(p, u1ChannelIdx);
+        u4Ta2LoopEn = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), TEST2_A0_TA2_LOOP_EN);
+        //mcSHOW_DBG_MSG(("### u4Ta2LoopEn:%d ### \n", u4Ta2LoopEn));
+
+        if(u4Ta2LoopEn)
+        {
+            u4loopcount = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), TEST2_A3_TESTCNT);
+            if (u4loopcount == 1)
+                u1status = 3; //RK0/1
+
+            vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), 0, TEST2_A0_LOOP_NV_END);//cancel NV_END
+            DramcEngine2CheckComplete(p, u1status);//Wait for complete
+            //mcSHOW_DBG_MSG(("TESTRPT_TESTSTAT:%x\n", u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT)));//check TESTRPT_TESTSTAT
+            u4ErrorValue = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) >> 4) & 0x3; //CMP_ERR_RK0/1
+        }
+        else
+            u4ErrorValue = DramcEngine2Compare(p, TE_OP_WRITE_READ_CHECK);
+
+        if (u4ErrorValue & 0x3) //RK0 or RK1 test fail
+        {
+            mcSHOW_DBG_MSG2(("=== HW channel(%d) u4ErrorValue: 0x%x, bit error: 0x%x\n", u1ChannelIdx, u4ErrorValue, u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR))));
+#if defined(SLT)
+            mcSHOW_ERR_MSG(("[dramc] DRAM_FATAL_ERR_FLAG = 0x00000001, line: %d\n",__LINE__));
+            while (1);
+#endif
+        }
+        TA2_Show_Cnt(p, u4ErrorValue);
+
+        bit_error |= u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | P_Fld(0, TEST2_A3_TEST1));
+    }
+    vSetPHY2ChannelMapping(p, eOriChannel);
+
+    return bit_error;
+}
+#endif
+#if defined(RELEASE) && defined(DEVIATION)
+#undef mcSHOW_JV_LOG_MSG
+#define mcSHOW_JV_LOG_MSG(_x_)
+#endif
+
+
+void TA2_Test_Run_Time_HW(DRAMC_CTX_T * p)
+{
+    DRAM_CHANNEL_T channel_bak = p->channel;
+    DRAM_RANK_T rank_bak = p->rank;
+
+    TA2_Test_Run_Time_HW_Presetting(p, 0x10000, TA2_RKSEL_HW);  //TEST2_2_TEST2_OFF = 0x400
+    TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_OFF);
+    TA2_Test_Run_Time_HW_Write(p, ENABLE);
+    //mcDELAY_MS(1);
+    TA2_Test_Run_Time_HW_Status(p);
+
+    p->channel = channel_bak;
+    p->rank = rank_bak;
+    return;
+}
+
+void Temp_TA2_Test_After_K(DRAMC_CTX_T * p)
+{
+    DRAM_CHANNEL_T channel_bak = p->channel;
+    DRAM_RANK_T rank_bak = p->rank;
+
+    do {
+        TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_ON);
+        TA2_Test_Run_Time_HW_Presetting(p, 0x200000, TA2_RKSEL_HW);
+        TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W
+        TA2_Test_Run_Time_HW_Status(p);
+       }while(1);
+
+    p->channel = channel_bak;
+    p->rank = rank_bak;
+    return;
+}
+
+static U8 *DramcFetchGlobalMR(DRAMC_CTX_T *p, U8 mr_idx)
+{
+    U8 *pMRGlobalValue = NULL;
+
+    switch (mr_idx)
+    {
+        case 13: pMRGlobalValue = &u1MR13Value[p->rank]; break;
+        case 26: pMRGlobalValue = &u1MR26Value[p->rank]; break;
+        case 30: pMRGlobalValue = &u1MR30Value[p->rank]; break;
+        default:
+            mcSHOW_ERR_MSG(("%s NULL\n", __func__));
+            #if __ETT__
+            while(1);
+            #endif
+            break;
+    }
+
+    return pMRGlobalValue;
+}
+
+#if MRW_BACKUP
+U8 DramcMRWriteBackup(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Rank)
+{
+    U8 u1Value=0xff;
+    U8 u1Fsp;
+    U8 u1MRBackup_ERR_Flag=0, u1backupRK=p->rank;
+    U16 u2Offset=0x0;
+    REG_TRANSFER_T TransferReg;
+
+    u1Fsp = FSP_0;
+
+#if (__LP5_COMBO__ == TRUE)
+    if (is_lp5_family(p))
+    {
+        switch (u1MRIdx)
+        {
+            case 1:
+            case 2:
+            case 3:
+            case 10:
+            case 11:
+            case 12:
+            case 14:
+            case 15:
+            case 17:
+            case 18:
+            case 19:
+            case 20:
+            case 24:
+            case 30:
+            case 41:
+                u1Fsp = gFSPWR_Flag[u1Rank];
+                break;
+        }
+    }
+    else
+#endif
+    {
+        switch (u1MRIdx)
+        {
+            case 1:
+            case 2:
+            case 3:
+            case 11:
+            case 12:
+            case 14:
+            case 22:
+                u1Fsp = gFSPWR_Flag[u1Rank];
+                break;
+        }
+    }
+
+    if (u1Fsp == FSP_0) /* All MR */
+    {
+        switch (u1MRIdx)
+        {
+            case 1:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_00_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR1;
+                break;
+            case 2:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_00_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR2;
+                break;
+            case 3:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_00_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR3;
+                break;
+            case 4:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_00_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR4;
+                break;
+            case 9:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_01_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR9;
+                break;
+            case 10:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_01_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR10;
+                break;
+            case 11:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_01_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR11;
+                break;
+            case 12:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_01_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR12;
+                break;
+            case 13:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_02_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR13;
+                break;
+            case 14:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_02_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR14;
+                break;
+            case 15:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_02_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR15;
+                break;
+            case 16:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_02_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR16;
+                break;
+            case 17:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR17;
+                break;
+            case 18:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR18;
+                break;
+            case 19:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR19;
+                break;
+            case 20:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR20;
+                break;
+            case 21:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_04_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR21;
+                break;
+            case 22:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_04_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR22;
+                break;
+            case 23:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_04_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR23;
+                break;
+            case 24:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_04_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR24;
+                break;
+            case 25:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_05_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR25;
+                break;
+            case 26:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_05_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR26;
+                break;
+            case 27:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_05_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR27;
+                break;
+            case 28:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_05_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR28;
+                break;
+            case 30:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_06_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR30;
+                break;
+            case 31:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_06_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR31;
+                break;
+            case 32:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_06_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR32;
+                break;
+            case 33:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_06_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR33;
+                break;
+            case 34:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_07_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR34;
+                break;
+            case 37:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_07_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR37;
+                break;
+            case 39:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_07_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR39;
+                break;
+            case 40:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_07_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR40;
+                break;
+            case 41:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_08_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR41;
+                break;
+            case 42:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_08_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR42;
+                break;
+            case 46:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_08_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR46;
+                break;
+            case 48:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_08_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR48;
+                break;
+            case 51:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_09_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_09_RK0_FSP0_MRWBK_RK0_FSP0_MR51;
+                break;
+            case 63:
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_09_RK0_FSP0;
+                TransferReg.u4Fld = MR_BACKUP_09_RK0_FSP0_MRWBK_RK0_FSP0_MR63;
+                break;
+        }
+    }
+    else if (u1MRIdx == 21 || u1MRIdx == 22) /* MR only in FSP0/FSP1 */
+    {
+        if (u1MRIdx == 21)
+        {
+            TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_04_RK0_FSP1;
+            TransferReg.u4Fld = MR_BACKUP_04_RK0_FSP1_MRWBK_RK0_FSP1_MR21;
+        }
+        else
+        {
+            TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP1;
+            TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR22;
+        }
+    }
+    else /* MR in FSP0/FSP1/FSP2 */
+    {
+        if (u1MRIdx <= 20)
+        {
+            if (u1MRIdx <= 10)
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_00_RK0_FSP1;
+            else if (u1MRIdx <= 15)
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_01_RK0_FSP1;
+            else
+                TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP1;
+
+            TransferReg.u4Addr += ((u1Fsp - FSP_1) * 0x30);
+
+            if (u1MRIdx == 1 || u1MRIdx == 11 || u1MRIdx == 17)
+                TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR1;
+            else if (u1MRIdx == 2 || u1MRIdx == 12 || u1MRIdx == 18)
+                TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR2;
+            else if (u1MRIdx == 3 || u1MRIdx == 14 || u1MRIdx == 19)
+                TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR3;
+            else
+                TransferReg.u4Fld = MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR10;
+        }
+        else if (u1Fsp == FSP_2 && u1MRIdx == 24)
+        {
+            TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP2;
+            TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP2_MRWBK_RK0_FSP2_MR24;
+        }
+        else if (u1Fsp == FSP_1 && u1MRIdx == 41)
+        {
+            TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP1;
+            TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR41;
+        }
+        else
+        {
+            TransferReg.u4Addr = DRAMC_REG_MR_BACKUP_03_RK0_FSP1 + ((u1Fsp - FSP_1) * 0x30);
+            if ((u1Fsp == FSP_1 && u1MRIdx == 24) || (u1Fsp == FSP_2 && u1MRIdx == 30))
+            {
+                TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR24;
+            }
+            else
+            {
+                TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR30;
+            }
+        }
+    }
+
+    vSetRank(p, u1Rank);
+
+    if (u1MRBackup_ERR_Flag==0)
+    {
+        u1Value=u4IO32ReadFldAlign(DRAMC_REG_ADDR(TransferReg.u4Addr), TransferReg.u4Fld);
+        mcSHOW_MRW_MSG(("  [MRW Backup] Rank%d FSP%d MR%d=0x%x\n",u1Rank, gFSPWR_Flag[u1Rank], u1MRIdx, u1Value));
+    }
+    vSetRank(p, u1backupRK);
+
+    return u1Value;
+
+}
+#endif
+
+void DramcMRWriteFldMsk(DRAMC_CTX_T *p, U8 mr_idx, U8 listVal8, U8 msk8, U8 UpdateMode)
+{
+    U8 *pMRGlobalValue = DramcFetchGlobalMR(p, mr_idx);
+
+    // ASSERT (pMRGlobalValue != NULL)
+
+    *pMRGlobalValue = ((*pMRGlobalValue & ~msk8) | listVal8);
+
+    if (UpdateMode == TO_MR)
+        DramcModeRegWriteByRank(p, p->rank, mr_idx, *pMRGlobalValue);
+}
+
+void DramcMRWriteFldAlign(DRAMC_CTX_T *p, U8 mr_idx, U8 value, U32 mr_fld, U8 UpdateMode)
+{
+    U8 *pMRGlobalValue = DramcFetchGlobalMR(p, mr_idx);
+
+    // ASSERT (pMRGlobalValue != NULL)
+
+    *pMRGlobalValue &= ~(Fld2Msk32(mr_fld));
+    *pMRGlobalValue |= (value << Fld_shft(mr_fld));
+
+    if (UpdateMode == TO_MR)
+        DramcModeRegWriteByRank(p, p->rank, mr_idx, *pMRGlobalValue);
+}
+
+void DramcModeRegRead(DRAMC_CTX_T *p, U8 u1MRIdx, U16 *u2pValue)
+{
+    U32 u4MRValue;
+#ifdef DUMP_INIT_RG_LOG_TO_DE
+    gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag=0;
+#endif
+    //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), p->rank, SWCMD_CTRL0_MRRRK);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1MRIdx, SWCMD_CTRL0_MRSMA);
+
+    // MRR command will be fired when MRREN 0->1
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_MRREN);
+
+    // wait MRR command fired.
+    while (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRR_RESPONSE) == 0)
+    {
+        mcDELAY_US(1);
+    }
+
+    // Since LP3 does not support CG condition, LP3 can not use MRR_STATUS_MRR_SW_REG to do sw mrr.
+    // After fix HW CG condition, LP3 will use MRR_STATUS_MRR_SW_REG to do sw mrr.
+    U32 u4MRRReg;
+    if (u1IsLP4Family(p->dram_type))
+        u4MRRReg = MRR_STATUS_MRR_SW_REG;
+    else
+        u4MRRReg = MRR_STATUS_MRR_REG;
+
+    // Read out mode register value
+    u4MRValue = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS), u4MRRReg);
+    *u2pValue = (U16)u4MRValue;
+
+    // Set MRREN =0 for next time MRR.
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_MRREN);
+
+#ifdef DUMP_INIT_RG_LOG_TO_DE
+    gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag=1;
+#endif
+
+    mcSHOW_DBG_MSG4(("Read MR%d =0x%x\n", u1MRIdx, u4MRValue));
+}
+
+
+void DramcModeRegReadByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U16 *u2pValue)
+{
+    U16 u2Value = 0;
+    U8 u1RankBak;
+
+    /* Since, TMRRI design changed (2 kinds of modes depending on value of R_DMRK_SCINPUT_OPT)
+     * DE: Jouling, Berson
+     * To specify SW_MRR rank -> new mode(scinput_opt == 0): MRSRK
+     *                           old mode(scinput_opt == 1): MRRRK
+     * Note: MPCRK is not used by SW to control rank anymore
+     */
+    //Backup & set rank
+    u1RankBak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), SWCMD_CTRL0_MRSRK); //backup rank
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Rank, SWCMD_CTRL0_MRSRK); //set rank
+
+    //Mode reg read
+    DramcModeRegRead(p, u1MRIdx, &u2Value);
+    *u2pValue = u2Value;
+
+    //Restore rank
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1RankBak, SWCMD_CTRL0_MRSRK);
+
+}
+
+void DramcModeRegWriteByRank_RTMRW(DRAMC_CTX_T *p, U8 *u1Rank, U8 *u1MRIdx, U8 *u1Value, U8 u1Len)
+{
+    U32 u4Response, u4TimeCnt, ii;
+    U8 u1MRRK[6] = {0}, u1MRMA[6] = {0}, u1MROP[6] = {0};
+
+    if (u1Len > 6 || u1Len == 0)
+        return;
+
+    for (ii = 0;ii < u1Len;ii++)
+    {
+        u1MRRK[ii] = u1Rank[ii];
+        u1MRMA[ii] = u1MRIdx[ii];
+        u1MROP[ii] = u1Value[ii];
+    }
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL0),
+            P_Fld(3, RTMRW_CTRL0_RTMRW_LAT) |
+            P_Fld(0x20, RTMRW_CTRL0_RTMRW_AGE) |
+            P_Fld(u1Len - 1, RTMRW_CTRL0_RTMRW_LEN) |
+            P_Fld(u1MRRK[0], RTMRW_CTRL0_RTMRW0_RK) |
+            P_Fld(u1MRRK[1], RTMRW_CTRL0_RTMRW1_RK) |
+            P_Fld(u1MRRK[2], RTMRW_CTRL0_RTMRW2_RK) |
+            P_Fld(u1MRRK[3], RTMRW_CTRL0_RTMRW3_RK) |
+            P_Fld(u1MRRK[4], RTMRW_CTRL0_RTMRW4_RK) |
+            P_Fld(u1MRRK[5], RTMRW_CTRL0_RTMRW5_RK));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL1),
+            P_Fld(u1MRMA[0], RTMRW_CTRL1_RTMRW0_MA) |
+            P_Fld(u1MRMA[1], RTMRW_CTRL1_RTMRW1_MA) |
+            P_Fld(u1MRMA[2], RTMRW_CTRL1_RTMRW2_MA) |
+            P_Fld(u1MRMA[3], RTMRW_CTRL1_RTMRW3_MA));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL2),
+            P_Fld(u1MROP[0], RTMRW_CTRL2_RTMRW0_OP) |
+            P_Fld(u1MROP[1], RTMRW_CTRL2_RTMRW1_OP) |
+            P_Fld(u1MROP[2], RTMRW_CTRL2_RTMRW2_OP) |
+            P_Fld(u1MROP[3], RTMRW_CTRL2_RTMRW3_OP));
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL3),
+            P_Fld(u1MRMA[4], RTMRW_CTRL3_RTMRW4_MA) |
+            P_Fld(u1MRMA[5], RTMRW_CTRL3_RTMRW5_MA) |
+            P_Fld(u1MROP[4], RTMRW_CTRL3_RTMRW4_OP) |
+            P_Fld(u1MROP[5], RTMRW_CTRL3_RTMRW5_OP));
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL),
+            1, MPC_CTRL_RTMRW_HPRI_EN);
+    mcDELAY_US(5);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
+            1, SWCMD_EN_RTMRWEN);
+
+#if __LP5_COMBO__
+#if WORKAROUND_LP5_HEFF
+    if (is_heff_mode(p))
+    {
+        mcDELAY_US(1);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
+                1, CKECTRL_CKE2RANK_OPT6);
+    }
+#endif
+#endif
+
+    u4TimeCnt = TIME_OUT_CNT;
+
+    do {
+        u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP),
+                SPCMDRESP_RTMRW_RESPONSE);
+        u4TimeCnt--;
+        mcDELAY_US(5);
+    } while ((u4Response == 0) && (u4TimeCnt > 0));
+
+    if (u4TimeCnt == 0)//time out
+    {
+        mcSHOW_ERR_MSG(("[LP5 RT MRW ] Resp fail (time out) Rank=%d, MR%d=0x%x\n", u1Rank[0], u1MRIdx[0], u1Value[0]));
+    }
+
+#if __LP5_COMBO__
+#if WORKAROUND_LP5_HEFF
+    if (is_heff_mode(p))
+    {
+        mcDELAY_US(1);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
+                0, CKECTRL_CKE2RANK_OPT6);
+    }
+#endif
+#endif
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
+            0, SWCMD_EN_RTMRWEN);
+}
+#if 0
+static void DramcModeRegWriteByRank_RTSWCMD_MRW(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
+{
+    U32 u4Response, u4TimeCnt;
+
+    vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2),
+            P_Fld(0, SWCMD_CTRL2_RTSWCMD_AGE) |
+            P_Fld(u1Rank, SWCMD_CTRL2_RTSWCMD_RK) |
+            P_Fld(u1MRIdx, SWCMD_CTRL2_RTSWCMD_MA) |
+            P_Fld(u1Value, SWCMD_CTRL2_RTSWCMD_OP));
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL),
+            1, MPC_CTRL_RTSWCMD_HPRI_EN);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT),
+            0x2a, RTSWCMD_CNT_RTSWCMD_CNT);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
+            4, SWCMD_EN_RTSWCMD_SEL);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
+            1, SWCMD_EN_RTSWCMDEN);
+
+#if __LP5_COMBO__
+#if WORKAROUND_LP5_HEFF
+    if (is_heff_mode(p))
+    {
+        mcDELAY_US(1);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
+                1, CKECTRL_CKE2RANK_OPT6);
+    }
+#endif
+#endif
+
+    u4TimeCnt = TIME_OUT_CNT;
+
+    do {
+        u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3),
+                SPCMDRESP3_RTSWCMD_RESPONSE);
+        u4TimeCnt--;
+        mcDELAY_US(5);
+    } while ((u4Response == 0) && (u4TimeCnt > 0));
+
+    if (u4TimeCnt == 0)//time out
+    {
+        mcSHOW_ERR_MSG(("[LP5 RT SW Cmd MRW ] Resp fail (time out) Rank=%d, MR%d=0x%x\n", u1Rank, u1MRIdx, u1Value));
+    }
+
+#if __LP5_COMBO__
+#if WORKAROUND_LP5_HEFF
+    if (is_heff_mode(p))
+    {
+        mcDELAY_US(1);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
+                0, CKECTRL_CKE2RANK_OPT6);
+    }
+#endif
+#endif
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
+            0, SWCMD_EN_RTSWCMDEN);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL),
+            0, MPC_CTRL_RTSWCMD_HPRI_EN);
+}
+#endif
+static void DramcModeRegWriteByRank_SCSM(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
+{
+    U32 counter = 0;
+    U32 u4RabnkBackup;
+    U32 u4register_024;
+
+    // backup rank
+    u4RabnkBackup = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), SWCMD_CTRL0_MRSRK);
+
+    //backup register of CKE fix on/off
+    u4register_024 = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL));
+
+    // set rank
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Rank, SWCMD_CTRL0_MRSRK);
+
+    //CKE must be fix on when doing MRW
+    CKEFixOnOff(p, u1Rank, CKE_FIXON, TO_ONE_CHANNEL);
+
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1MRIdx, SWCMD_CTRL0_MRSMA);
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Value, SWCMD_CTRL0_MRSOP);
+
+    // MRW command will be fired when MRWEN 0->1
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_MRWEN);
+
+    // wait MRW command fired.
+    while (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRW_RESPONSE) == 0)
+    {
+        counter++;
+        mcSHOW_DBG_MSG2(("wait MRW command Rank%d MR%d =0x%x fired (%d)\n", u1Rank, u1MRIdx, u1Value, counter));
+        mcDELAY_US(1);
+    }
+
+    // Set MRWEN =0 for next time MRW.
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_MRWEN);
+
+    // restore CKEFIXON value
+    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4register_024);
+
+    // restore rank
+    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u4RabnkBackup, SWCMD_CTRL0_MRSRK);
+}
+
+void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
+{
+    mcSHOW_DBG_MSG2(("MRW RK%d MR#%d = 0x%x\n", u1Rank,u1MRIdx, u1Value));
+
+    #if (fcFOR_CHIP_ID == fcA60868)
+    // RTMRW & RTSWCMD-MRW can not be used in runtime
+
+        if (u1EnterRuntime)
+        {
+            DramcModeRegWriteByRank_SCSM(p, u1Rank, u1MRIdx, u1Value);
+        }
+    else
+#endif
+        {
+        #if (__LP5_COMBO__ == TRUE)
+            if (is_lp5_family(p))
+            {
+            #if ENABLE_RUNTIME_MRW_FOR_LP5
+                DramcModeRegWriteByRank_RTMRW(p, &u1Rank, &u1MRIdx, &u1Value, 1);
+            #else
+                DramcModeRegWriteByRank_RTSWCMD_MRW(p, u1Rank, u1MRIdx, u1Value);
+            #endif
+            }
+            else
+        #endif
+            {
+                DramcModeRegWriteByRank_SCSM(p, u1Rank, u1MRIdx, u1Value);
+            }
+        }
+
+    #if MRW_CHECK_ONLY
+    u1PrintModeRegWrite = 1;
+    U8 u1Backup_Rank;
+    U8 u1RankIdx, u1RankNum, u1RankStart;
+    U8 u1FSPMRIdx;
+
+    u1Backup_Rank=p->rank;
+
+    if (u1Rank==3)
+    {
+        u1RankNum = 2;
+        u1RankStart = 0;
+    }
+    else
+    {
+        u1RankNum = 1;
+        u1RankStart = u1Rank;
+    }
+
+    #if (__LP5_COMBO__ == TRUE)
+    if (is_lp5_family(p))
+        u1FSPMRIdx=16;
+    else
+    #endif
+        u1FSPMRIdx=13;
+
+    for (u1RankIdx=u1RankStart;u1RankIdx<u1RankStart+u1RankNum;u1RankIdx++)
+    {
+        vSetRank(p, u1RankIdx);
+        if (u1MRIdx==u1FSPMRIdx)
+        {
+            u2MRRecord[p->channel][u1RankIdx][FSP_0][u1FSPMRIdx] =u1Value;
+            u2MRRecord[p->channel][u1RankIdx][FSP_1][u1FSPMRIdx] =u1Value;
+        }
+        else
+            u2MRRecord[p->channel][u1RankIdx][gFSPWR_Flag[u1RankIdx]][u1MRIdx] = u1Value;
+
+        if(u1PrintModeRegWrite)
+        {
+            #if VENDER_JV_LOG
+            mcSHOW_JV_LOG_MSG(("Write Rank%d MR%d =0x%x\n", u1RankIdx, u1MRIdx, u1Value));
+            #endif
+            #if MRW_CHECK_ONLY
+            mcSHOW_MRW_MSG(("MRW CH%d Rank%d FSP%d MR%d =0x%x\n", p->channel, u1RankIdx, gFSPWR_Flag[u1RankIdx], u1MRIdx, u1Value));
+            #endif
+            mcSHOW_DBG_MSG2(("Write Rank%d MR%d =0x%x\n", u1RankIdx, u1MRIdx, u1Value));
+            //mcDUMP_REG_MSG(("Write Rank%d MR%d =0x%x\n", u1RankIdx, u1MRIdx, u1Value));
+        }
+        #if MRW_BACKUP
+        U8 MR_backup;
+
+        MR_backup=DramcMRWriteBackup(p, u1MRIdx, u1RankIdx);
+        if (MR_backup!=0xff)
+            mcSHOW_MRW_MSG(("  [MRW Check] Rank%d FSP%d Backup_MR%d= 0x%x MR%d= 0x%x ==>%s\n", u1RankIdx, gFSPWR_Flag[u1RankIdx], u1MRIdx, MR_backup, u1MRIdx, u1Value, (u1Value==MR_backup?"PASS":"FAIL")));
+        #endif
+
+        #if (__LP5_COMBO__ == TRUE)
+            if (is_lp5_family(p))
+            {
+                if (u1MRIdx==u1FSPMRIdx)
+                    gFSPWR_Flag[u1RankIdx] = u1Value & 0x3;
+            }
+            else
+        #endif
+            {
+                if (u1MRIdx==u1FSPMRIdx)
+                    gFSPWR_Flag[u1RankIdx] = (u1Value>> 6) & 0x1;
+            }
+    }
+    vSetRank(p, u1Backup_Rank);
+    #endif
+}
+
+#if __ETT__
+static U8 u1gpRegBackup;
+#endif
+U32 u4gpRegBackupVlaue[100];
+void DramcBackupRegisters(DRAMC_CTX_T *p, U32 *backup_addr, U32 backup_num)
+{
+    U32 u4RegIdx;
+
+#if __ETT__
+    if (backup_num > 100 || u1gpRegBackup)
+    {
+        mcSHOW_ERR_MSG(("[DramcBackupRegisters] backup number over 64!!!\n"));
+        while (1);
+    }
+
+    u1gpRegBackup++;
+#endif
+
+    for (u4RegIdx = 0; u4RegIdx < backup_num; u4RegIdx++)
+    {
+        u4gpRegBackupVlaue[u4RegIdx] = u4IO32Read4B(backup_addr[u4RegIdx]);
+        //mcSHOW_DBG_MSG(("Backup Reg(0x%X) = 0x%X\n", backup_addr[u4RegIdx], u4gpRegBackupVlaue[u4RegIdx]));
+    }
+}
+
+void DramcRestoreRegisters(DRAMC_CTX_T *p, U32 *restore_addr, U32 restore_num)
+{
+    U32 u4RegIdx;
+
+#if __ETT__
+    if (u1gpRegBackup == 0)
+    {
+        mcSHOW_ERR_MSG(("[DramcRestoreRegisters] Need to call backup first\n"));
+    }
+
+    u1gpRegBackup--;
+#endif
+
+    for (u4RegIdx = 0; u4RegIdx < restore_num; u4RegIdx++)
+    {
+        vIO32Write4B(restore_addr[u4RegIdx], u4gpRegBackupVlaue[u4RegIdx]);
+        //mcSHOW_DBG_MSG(("Restore Reg(0x%X) = 0x%X\n", restore_addr[u4RegIdx], u4gpRegBackupVlaue[u4RegIdx]));
+    }
+}
+
+
+U8 u1GetMR4RefreshRate(DRAMC_CTX_T *p, DRAM_CHANNEL_T channel)
+{
+    U8 u1RefreshRate; //u1Dummy
+
+    //vSetPHY2ChannelMapping(p, channel);
+
+    //DramcModeRegRead(p, 4, &u1Dummy);
+    //mcSHOW_DBG_MSG(("[u2GetRefreshRate] MR4 0x%x,  u1RefreshRate= 0x%x\n", u1Dummy, u1RefreshRate));
+    u1RefreshRate = (U8)u4IO32ReadFldAlign((DRAMC_REG_MISC_STATUSA) + (channel << POS_BANK_NUM), MISC_STATUSA_REFRESH_RATE);
+    //mcSHOW_DBG_MSG(("[u2GetRefreshRate] channel = %d, u1RefreshRate= 0x%x\n", channel, u1RefreshRate));
+
+    return u1RefreshRate;
+}
+
+#if 0
+//#if defined(DDR_INIT_TIME_PROFILING) || (__ETT__ && SUPPORT_SAVE_TIME_FOR_CALIBRATION)
+void DramcConfInfraReset(DRAMC_CTX_T *p)
+{
+#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
+        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CLK_CTRL, P_Fld(0, MISC_CLK_CTRL_DVFS_CLK_MEM_SEL)
+                                                    | P_Fld(0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN));
+
+        vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), P_Fld(0, MISC_CG_CTRL0_CLK_MEM_SEL)
+                                                                | P_Fld(1, MISC_CG_CTRL0_W_CHG_MEM));
+        mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK
+        vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), 0, MISC_CG_CTRL0_W_CHG_MEM);
+
+#if (fcFOR_CHIP_ID == fcLafite)
+        // 26M
+        vIO32WriteFldMulti_All(DDRPHY_CKMUX_SEL, P_Fld(0x1, CKMUX_SEL_R_PHYCTRLMUX)  //move CKMUX_SEL_R_PHYCTRLMUX to here (it was originally between MISC_CG_CTRL0_CLK_MEM_SEL and MISC_CTRL0_R_DMRDSEL_DIV2_OPT)
+                                    | P_Fld(0x1, CKMUX_SEL_R_PHYCTRLDCM)); // PHYCTRLDCM 1: follow DDRPHY_conf DCM settings, 0: follow infra DCM settings
+        vIO32WriteFldMulti_All(DDRPHY_MISC_CG_CTRL0, P_Fld(0, MISC_CG_CTRL0_W_CHG_MEM)
+                    | P_Fld(0, MISC_CG_CTRL0_CLK_MEM_SEL));//[5:4] mem_ck mux: 2'b00: 26MHz, [0]: change memory clock
+        vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 1, MISC_CG_CTRL0_W_CHG_MEM);//change clock freq
+        mcDELAY_US(1);
+        vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_W_CHG_MEM);//disable memory clock change
+
+        // dramc conf reset
+        //mcSHOW_TIME_MSG(("Before infra reset, 0x10001148:%x\n", *(volatile unsigned *)(0x10001148)));
+        *(volatile unsigned *)(0x10001140) = (0x1 << 15);
+        //mcSHOW_TIME_MSG(("After infra reset, 0x10001148:%x\n",  *(volatile unsigned *)(0x10001148)));
+        __asm__ __volatile__ ("dsb" : : : "memory");
+        mcDELAY_US(200);
+        //mcSHOW_TIME_MSG(("Before infra clear, 0x10001148:%x\n",  *(volatile unsigned *)(0x10001148)));
+        *(volatile unsigned *)(0x10001144) = (0x1 << 15);
+        //mcSHOW_TIME_MSG(("After infra clear, 0x10001148:%x\n",  *(volatile unsigned *)(0x10001148)));
+
+        #if 0
+        mcDELAY_US(200);
+        *(volatile unsigned *)(0x10007018) = 0x88000040;
+        mcDELAY_US(200);
+        *(volatile unsigned *)(0x10007018) = 0x88000000;
+        mcDELAY_US(200);
+        #endif
+
+        //DDRPHY Reset
+        vIO32WriteFldAlign_All(DDRPHY_B0_DQ3, 0x0, B0_DQ3_RG_ARDQ_RESETB_B0);
+        vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0x0, B0_DLL_ARPI0_RG_ARPI_RESETB_B0);
+        vIO32WriteFldAlign_All(DDRPHY_B1_DQ3, 0x0, B1_DQ3_RG_ARDQ_RESETB_B1);
+        vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0x0, B1_DLL_ARPI0_RG_ARPI_RESETB_B1);
+        vIO32WriteFldAlign_All(DDRPHY_CA_CMD3, 0x0, CA_CMD3_RG_ARCMD_RESETB);
+        vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0x0, CA_DLL_ARPI0_RG_ARPI_RESETB_CA);
+        vIO32WriteFldAlign(DDRPHY_PLL4, 0x0, PLL4_RG_RPHYPLL_RESETB);//Since there is only 1 PLL, only control CHA
+        mcDELAY_US(200);
+        vIO32WriteFldAlign_All(DDRPHY_B0_DQ3, 0x1, B0_DQ3_RG_ARDQ_RESETB_B0);
+        vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0x1, B0_DLL_ARPI0_RG_ARPI_RESETB_B0);
+        vIO32WriteFldAlign_All(DDRPHY_B1_DQ3, 0x1, B1_DQ3_RG_ARDQ_RESETB_B1);
+        vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0x1, B1_DLL_ARPI0_RG_ARPI_RESETB_B1);
+        vIO32WriteFldAlign_All(DDRPHY_CA_CMD3, 0x1, CA_CMD3_RG_ARCMD_RESETB);
+        vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0x1, CA_DLL_ARPI0_RG_ARPI_RESETB_CA);
+        vIO32WriteFldAlign(DDRPHY_PLL4, 0x1, PLL4_RG_RPHYPLL_RESETB);//Since there is only 1 PLL, only control CHA
+
+        //Disable SPM control
+        vIO32WriteFldMulti(SPM_POWERON_CONFIG_EN, P_Fld(0xB16, POWERON_CONFIG_EN_PROJECT_CODE) | P_Fld(0, POWERON_CONFIG_EN_BCLK_CG_EN));
+
+        //For FMeter after dcm enable
+        vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL2, 0x0, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN);
+        vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL2, 0x1, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON);
+#endif
+#endif
+}
+#endif
+
+#if 0
+#define PATTERN1 0x5A5A5A5A
+#define PATTERN2 0xA5A5A5A5
+int dramc_complex_mem_test (unsigned int start, unsigned int len)
+{
+    unsigned char *MEM8_BASE = (unsigned char *) start;
+    unsigned short *MEM16_BASE = (unsigned short *) start;
+    unsigned int *MEM32_BASE = (unsigned int *) start;
+    unsigned int *MEM_BASE = (unsigned int *) start;
+    unsigned char pattern8;
+    unsigned short pattern16;
+    unsigned int i, j, size, pattern32;
+    unsigned int value;
+
+    size = len >> 2;
+
+    /* === Verify the tied bits (tied high) === */
+    for (i = 0; i < size; i++)
+    {
+        MEM32_BASE[i] = 0;
+    }
+
+    for (i = 0; i < size; i++)
+    {
+        if (MEM32_BASE[i] != 0)
+        {
+            return -1;
+        }
+        else
+        {
+            MEM32_BASE[i] = 0xffffffff;
+        }
+    }
+
+    /* === Verify the tied bits (tied low) === */
+    for (i = 0; i < size; i++)
+    {
+        if (MEM32_BASE[i] != 0xffffffff)
+        {
+            return -2;
+        }
+        else
+            MEM32_BASE[i] = 0x00;
+    }
+
+    /* === Verify pattern 1 (0x00~0xff) === */
+    pattern8 = 0x00;
+    for (i = 0; i < len; i++)
+        MEM8_BASE[i] = pattern8++;
+    pattern8 = 0x00;
+    for (i = 0; i < len; i++)
+    {
+        if (MEM8_BASE[i] != pattern8++)
+        {
+            return -3;
+        }
+    }
+
+    /* === Verify pattern 2 (0x00~0xff) === */
+    pattern8 = 0x00;
+    for (i = j = 0; i < len; i += 2, j++)
+    {
+        if (MEM8_BASE[i] == pattern8)
+            MEM16_BASE[j] = pattern8;
+        if (MEM16_BASE[j] != pattern8)
+        {
+            return -4;
+        }
+        pattern8 += 2;
+    }
+
+    /* === Verify pattern 3 (0x00~0xffff) === */
+    pattern16 = 0x00;
+    for (i = 0; i < (len >> 1); i++)
+        MEM16_BASE[i] = pattern16++;
+    pattern16 = 0x00;
+    for (i = 0; i < (len >> 1); i++)
+    {
+        if (MEM16_BASE[i] != pattern16++)
+        {
+            return -5;
+        }
+    }
+
+    /* === Verify pattern 4 (0x00~0xffffffff) === */
+    pattern32 = 0x00;
+    for (i = 0; i < (len >> 2); i++)
+        MEM32_BASE[i] = pattern32++;
+    pattern32 = 0x00;
+    for (i = 0; i < (len >> 2); i++)
+    {
+        if (MEM32_BASE[i] != pattern32++)
+        {
+            return -6;
+        }
+    }
+
+    /* === Pattern 5: Filling memory range with 0x44332211 === */
+    for (i = 0; i < size; i++)
+        MEM32_BASE[i] = 0x44332211;
+
+    /* === Read Check then Fill Memory with a5a5a5a5 Pattern === */
+    for (i = 0; i < size; i++)
+    {
+        if (MEM32_BASE[i] != 0x44332211)
+        {
+            return -7;
+        }
+        else
+        {
+            MEM32_BASE[i] = 0xa5a5a5a5;
+        }
+    }
+
+    /* === Read Check then Fill Memory with 00 Byte Pattern at offset 0h === */
+    for (i = 0; i < size; i++)
+    {
+        if (MEM32_BASE[i] != 0xa5a5a5a5)
+        {
+            return -8;
+        }
+        else
+        {
+            MEM8_BASE[i * 4] = 0x00;
+        }
+    }
+
+    /* === Read Check then Fill Memory with 00 Byte Pattern at offset 2h === */
+    for (i = 0; i < size; i++)
+    {
+        if (MEM32_BASE[i] != 0xa5a5a500)
+        {
+            return -9;
+        }
+        else
+        {
+            MEM8_BASE[i * 4 + 2] = 0x00;
+        }
+    }
+
+    /* === Read Check then Fill Memory with 00 Byte Pattern at offset 1h === */
+    for (i = 0; i < size; i++)
+    {
+        if (MEM32_BASE[i] != 0xa500a500)
+        {
+            return -10;
+        }
+        else
+        {
+            MEM8_BASE[i * 4 + 1] = 0x00;
+        }
+    }
+
+    /* === Read Check then Fill Memory with 00 Byte Pattern at offset 3h === */
+    for (i = 0; i < size; i++)
+    {
+        if (MEM32_BASE[i] != 0xa5000000)
+        {
+            return -11;
+        }
+        else
+        {
+            MEM8_BASE[i * 4 + 3] = 0x00;
+        }
+    }
+
+    /* === Read Check then Fill Memory with ffff Word Pattern at offset 1h == */
+    for (i = 0; i < size; i++)
+    {
+        if (MEM32_BASE[i] != 0x00000000)
+        {
+            return -12;
+        }
+        else
+        {
+            MEM16_BASE[i * 2 + 1] = 0xffff;
+        }
+    }
+
+    /* === Read Check then Fill Memory with ffff Word Pattern at offset 0h == */
+    for (i = 0; i < size; i++)
+    {
+        if (MEM32_BASE[i] != 0xffff0000)
+        {
+            return -13;
+        }
+        else
+        {
+            MEM16_BASE[i * 2] = 0xffff;
+        }
+    }
+
+    /*===  Read Check === */
+    for (i = 0; i < size; i++)
+    {
+        if (MEM32_BASE[i] != 0xffffffff)
+        {
+            return -14;
+        }
+    }
+
+    /************************************************
+    * Additional verification
+    ************************************************/
+    /* === stage 1 => write 0 === */
+
+    for (i = 0; i < size; i++)
+    {
+        MEM_BASE[i] = PATTERN1;
+    }
+
+    /* === stage 2 => read 0, write 0xF === */
+    for (i = 0; i < size; i++)
+    {
+        value = MEM_BASE[i];
+
+        if (value != PATTERN1)
+        {
+            return -15;
+        }
+        MEM_BASE[i] = PATTERN2;
+    }
+
+    /* === stage 3 => read 0xF, write 0 === */
+    for (i = 0; i < size; i++)
+    {
+        value = MEM_BASE[i];
+        if (value != PATTERN2)
+        {
+            return -16;
+        }
+        MEM_BASE[i] = PATTERN1;
+    }
+
+
+    /* === stage 4 => read 0, write 0xF === */
+    for (i = 0; i < size; i++)
+    {
+        value = MEM_BASE[i];
+        if (value != PATTERN1)
+        {
+            return -17;
+        }
+        MEM_BASE[i] = PATTERN2;
+    }
+
+    /* === stage 5 => read 0xF, write 0 === */
+    for (i = 0; i < size; i++)
+    {
+        value = MEM_BASE[i];
+        if (value != PATTERN2)
+        {
+            return -18;
+        }
+        MEM_BASE[i] = PATTERN1;
+    }
+
+    /* === stage 6 => read 0 === */
+    for (i = 0; i < size; i++)
+    {
+        value = MEM_BASE[i];
+        if (value != PATTERN1)
+        {
+            return -19;
+        }
+    }
+
+#if 1
+    /* === 1/2/4-byte combination test === */
+    i = (unsigned int) MEM_BASE;
+
+    while (i < (unsigned int) MEM_BASE + (size << 2))
+    {
+        *((unsigned char *) i) = 0x78;
+        i += 1;
+        *((unsigned char *) i) = 0x56;
+        i += 1;
+        *((unsigned short *) i) = 0x1234;
+        i += 2;
+        *((unsigned int *) i) = 0x12345678;
+        i += 4;
+        *((unsigned short *) i) = 0x5678;
+        i += 2;
+        *((unsigned char *) i) = 0x34;
+        i += 1;
+        *((unsigned char *) i) = 0x12;
+        i += 1;
+        *((unsigned int *) i) = 0x12345678;
+        i += 4;
+        *((unsigned char *) i) = 0x78;
+        i += 1;
+        *((unsigned char *) i) = 0x56;
+        i += 1;
+        *((unsigned short *) i) = 0x1234;
+        i += 2;
+        *((unsigned int *) i) = 0x12345678;
+        i += 4;
+        *((unsigned short *) i) = 0x5678;
+        i += 2;
+        *((unsigned char *) i) = 0x34;
+        i += 1;
+        *((unsigned char *) i) = 0x12;
+        i += 1;
+        *((unsigned int *) i) = 0x12345678;
+        i += 4;
+    }
+    for (i = 0; i < size; i++)
+    {
+        value = MEM_BASE[i];
+        if (value != 0x12345678)
+        {
+            return -20;
+        }
+    }
+#endif
+
+    /* === Verify pattern 1 (0x00~0xff) === */
+    pattern8 = 0x00;
+    MEM8_BASE[0] = pattern8;
+    for (i = 0; i < size * 4; i++)
+    {
+        unsigned char waddr8, raddr8;
+        waddr8 = i + 1;
+        raddr8 = i;
+        if (i < size * 4 - 1)
+            MEM8_BASE[waddr8] = pattern8 + 1;
+        if (MEM8_BASE[raddr8] != pattern8)
+        {
+            return -21;
+        }
+        pattern8++;
+    }
+
+    /* === Verify pattern 2 (0x00~0xffff) === */
+    pattern16 = 0x00;
+    MEM16_BASE[0] = pattern16;
+    for (i = 0; i < size * 2; i++)
+    {
+        if (i < size * 2 - 1)
+            MEM16_BASE[i + 1] = pattern16 + 1;
+        if (MEM16_BASE[i] != pattern16)
+        {
+            return -22;
+        }
+        pattern16++;
+    }
+
+    /* === Verify pattern 3 (0x00~0xffffffff) === */
+    pattern32 = 0x00;
+    MEM32_BASE[0] = pattern32;
+    for (i = 0; i < size; i++)
+    {
+        if (i < size - 1)
+            MEM32_BASE[i + 1] = pattern32 + 1;
+        if (MEM32_BASE[i] != pattern32)
+        {
+            return -23;
+        }
+        pattern32++;
+    }
+    return 0;
+}
+#endif
+
+#if defined(DDR_INIT_TIME_PROFILING) || ENABLE_APB_MASK_WRITE
+static PROFILING_TIME_T prof_tick0;
+
+void TimeProfileGetTick(PROFILING_TIME_T *ptime)
+{
+#if __ETT__
+    ptime->u4TickLow = GPT_GetTickCount(&ptime->u4TickHigh);
+#else
+    ptime->u4TickHigh = 0;
+    ptime->u4TickLow = get_timer(0);
+#endif
+}
+
+U32 TimeProfileDiffUS(PROFILING_TIME_T *base)
+{
+    U32 u4Diff;
+
+#if __ETT__
+    const U32 u4TsMax = 0xFFFFFFFFUL;
+    const U32 u4NsPerTick = 76;
+    const U32 u4OV = u4TsMax / u4NsPerTick;
+    U32 u4Acc;
+    PROFILING_TIME_T end;
+
+    u4Acc = 0;
+    TimeProfileGetTick(&end);
+
+    /* temporary patch for overflow */
+        u4Diff = end.u4TickLow - base->u4TickLow;
+    if (end.u4TickLow > base->u4TickLow)
+    {
+        u4Diff = end.u4TickLow - base->u4TickLow;
+    }
+    else
+    {
+        u4Diff = u4TsMax - base->u4TickLow + end.u4TickLow;
+        mcSHOW_TIME_MSG(("%s(): overflow detected\n", __func__));
+    }
+
+    while (u4Diff >= u4OV)
+    {
+        u4Acc++;
+        u4Diff -= u4OV;
+    }
+
+    u4Diff = u4Diff * u4NsPerTick / 1000;
+    u4Diff += u4Acc * (u4TsMax / 1000);
+#else
+    u4Diff = get_timer(base->u4TickLow) * 1000;
+#endif
+
+    return u4Diff;
+}
+
+void TimeProfileBegin(void)
+{
+    TimeProfileGetTick(&prof_tick0);
+}
+
+U32 TimeProfileEnd(void)
+{
+    return TimeProfileDiffUS(&prof_tick0);
+}
+#endif
+
+#if QT_GUI_Tool
+void TA2_Test_Run_Time_SW_Presetting(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1TestPat, U8 u1LoopCnt)
+{
+        u1TestPat = u1TestPat & 0x7f;
+
+        DramcSetRankEngine2(p, p->rank);
+
+        uiReg0D0h=u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD));
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), P_Fld(0, DUMMY_RD_DQSG_DMYRD_EN) | P_Fld(0, DUMMY_RD_DQSG_DMYWR_EN) | P_Fld(0, DUMMY_RD_DUMMY_RD_EN) | P_Fld(0, DUMMY_RD_SREF_DMYRD_EN) | P_Fld(0, DUMMY_RD_DMY_RD_DBG) | P_Fld(0, DUMMY_RD_DMY_WR_DBG));  //must close dummy read when do test agent
+
+        //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTCHIP_DMA1), 0, TESTCHIP_DMA1_DMA_LP4MATAB_OPT);//Eddie
+        // disable self test engine1 and self test engine2
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | P_Fld(0, TEST2_A3_TEST1));
+
+        // 1.set pattern ,base address ,offset address
+        // 2.select  ISI pattern or audio pattern or xtalk pattern
+        // 3.set loop number
+        // 4.enable read or write
+        // 5.loop to check DM_CMP_CPT
+        // 6.return CMP_ERR
+        // currently only implement ucengine_status = 1, others are left for future extension
+
+        // 1
+        vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), P_Fld(test2_1>>24,TEST2_A0_TEST2_PAT0)|P_Fld(test2_2>>24,TEST2_A0_TEST2_PAT1));
+
+    #if (FOR_DV_SIMULATION_USED==1 || SW_CHANGE_FOR_SIMULATION==1)
+        //DV sim memory 0~0x100 has values, can't used
+        //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A1), (test2_1+0x100) & 0x00ffffff, TEST2_A1_TEST2_BASE);
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1),  0x10000, RK_TEST2_A1_TEST2_BASE); //LPDDR4 Setting
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1),  0x0, RK_TEST2_A1_TEST2_BASE); //Eddie Change to 0 for LP5
+    #else
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), 0, RK_TEST2_A1_TEST2_BASE);
+    #endif
+        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x2, TEST2_A2_TEST2_OFF);//Eddie
+
+    return;
+}
+#endif
diff --git a/src/vendorcode/mediatek/mt8195/dramc/emi.c b/src/vendorcode/mediatek/mt8195/dramc/emi.c
new file mode 100644
index 000000000000..36ce7b24a536
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/dramc/emi.c
@@ -0,0 +1,1123 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2010. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("Media Tek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+#include <emi_mpu_mt.h>
+#include <mt8195.h>
+
+#include <emi_hw.h>
+#include <emi.h>
+
+#define EMI_APB_BASE EMI_BASE
+#define EMI_CHANNEL_APB_BASE CHN0_EMI_BASE
+
+
+#if DRAM_AUXADC_CONFIG
+#include <mtk_auxadc_sw.h>
+#endif
+
+#ifdef LAST_EMI
+static LAST_EMI_INFO_T* last_emi_info_ptr;
+#endif
+
+static inline unsigned int mt_emi_sync_read(unsigned long long addr)
+{
+	dsb();
+	return *((volatile unsigned int *)addr);
+}
+
+#define mt_emi_sync_write(addr, value)				\
+	do {							\
+		*((volatile unsigned int *)(addr)) = value;	\
+		dsb();						\
+	} while (0)
+
+#define mt_emi_sync_write_or(addr, or_value)			\
+	do {							\
+		mt_emi_sync_write(addr,				\
+			mt_emi_sync_read(addr) | or_value);	\
+	} while (0)
+
+static void emi_cen_config(void)  {
+
+#ifndef ONE_CH
+  #ifdef RANK_512MB  // => 2channel , dual rank , total=2G
+    mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xa053a154);
+  #else
+    #ifdef RANK_1GB  //RANK_1G  => 2channel , dual rank , total=4G
+      mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xf053f154);
+    #else  // RANK_2G => 2channel , dual rank , total=8G
+      #ifdef RANK_2GB
+        mt_emi_sync_write(EMI_APB_BASE+0x00000000,0x00530154);
+      #endif
+    #endif 
+  #endif
+#else
+  #ifdef RANK_512MB
+    mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xa053a054);
+  #else
+    mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xf053f054);
+  #endif
+#endif
+
+  // overhead: 20190821 item1 - synced
+  mt_emi_sync_write(EMI_APB_BASE+0x00000004,0x182e2d33); //3733 (1:8) r4  - r1  overhead  // TBD - change to 4266
+  mt_emi_sync_write(EMI_APB_BASE+0x00000008,0x0f251025); //3733 (1:8) r8  - r5  overhead  // TBD - change to 4266
+  mt_emi_sync_write(EMI_APB_BASE+0x0000000c,0x122a1027); //3733 (1:8) r12 - r9  overhead  // TBD - change to 4266
+  mt_emi_sync_write(EMI_APB_BASE+0x00000010,0x1a31162d); //3733 (1:8) r16 - r13 overhead  // TBD - change to 4266
+  mt_emi_sync_write(EMI_APB_BASE+0x000008b0,0x182e2d33); //3200 (1:8) r4  - r1  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x000008b4,0x0f251025); //3200 (1:8) r8  - r5  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x0000001c,0x122a1027); //3200 (1:8) r12 - r9  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000024,0x1a31162d); //3200 (1:8) r16 - r13 overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000034,0x1024202c); //2400 (1:8) r4  - r1  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x0000006c,0x0b210c21); //2400 (1:8) r8  - r5  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x0000013c,0x0f250d23); //2400 (1:8) r12 - r9  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000640,0x152b1228); //2400 (1:8) r16 - r13 overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000044,0x0c201a28); //1866 (1:8) r4  - r1  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000074,0x0d230a20); //1866 (1:8) r8  - r5  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x000001e0,0x0e260d24); //1866 (1:8) r12 - r9  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000644,0x132d1229); //1866 (1:8) r16 - r13 overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x0000004c,0x0c201a28); //1600 (1:8) r4  - r1  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000084,0x0d230a20); //1600 (1:8) r8  - r5  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x000001e4,0x0e260d24); //1600 (1:8) r12 - r9  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000648,0x132d1229); //1600 (1:8) r16 - r13 overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000054,0x0c201a28); //1200 (1:8) r4  - r1  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x0000008c,0x0d230a20); //1200 (1:8) r8  - r5  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x000001e8,0x0e260d24); //1200 (1:8) r12 - r9  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x0000064c,0x132d1229); //1200 (1:8) r16 - r13 overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x0000005c,0x0e290e28); //800  (1:4) r12 - r9  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000094,0x091e1322); //800  (1:4) r4  - r1  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x000001c8,0x0f29112a); //800  (1:4) r16 - r13 overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000660,0x0c240a1f); //800  (1:4) r8  - r5  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000064,0x0e290e28); //800  (1:4) r12 - r9  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x0000009c,0x091e1322); //800  (1:4) r4  - r1  overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x000001f4,0x0f29112a); //800  (1:4) r16 - r13 overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000664,0x0c240a1f); //800  (1:4) r8  - r5  overhead
+
+  mt_emi_sync_write(EMI_APB_BASE+0x00000030,0x37373a57); //3733 (1:8) r8  - r2  non-align overhead  // TBD - change to 4266
+  mt_emi_sync_write(EMI_APB_BASE+0x00000014,0x3f3f3c39); //3733 (1:8) r16 - r10 non-align overhead  // TBD - change to 4266
+  mt_emi_sync_write(EMI_APB_BASE+0x000008b8,0x3836374e); //3200 (1:8) r8  - r2  non-align overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x0000002c,0x41413d3a); //3200 (1:8) r16 - r10 non-align overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x000000c4,0x33313241); //2400 (1:8) r8  - r2  non-align overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000668,0x3a3a3835); //2400 (1:8) r16 - r10 non-align overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x000000c8,0x34343542); //1866 (1:8) r8  - r2  non-align overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x0000066c,0x3b3b3835); //1866 (1:8) r16 - r10 non-align overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x000000cc,0x34343542); //1600 (1:8) r8  - r2  non-align overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000694,0x3b3b3835); //1600 (1:8) r16 - r10 non-align overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x000000e4,0x34343542); //1200 (1:8) r8  - r2  non-align overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000708,0x3b3b3835); //1200 (1:8) r16 - r10 non-align overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x000000f4,0x37333034); //800  (1:4) r8  - r2  non-align overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x0000070c,0x39393a39); //800  (1:4) r16 - r10 non-align overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x0000012c,0x37333034); //800  (1:4) r8  - r2  non-align overhead
+  mt_emi_sync_write(EMI_APB_BASE+0x00000748,0x39393a39); //800  (1:4) r16 - r10 non-align overhead
+
+  //
+  mt_emi_sync_write(EMI_APB_BASE+0x00000018,0x3657587a);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000020,0x0000c042);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000028,0x08421000);
+  #ifdef RANK_2GB
+    mt_emi_sync_write(EMI_APB_BASE+0x00000038,0x000000b3);
+  #else
+    mt_emi_sync_write(EMI_APB_BASE+0x00000038,0x00000083);
+  #endif
+  mt_emi_sync_write(EMI_APB_BASE+0x0000003c,0x00073210);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000040,0x00008802);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000048,0x00000000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000060,0x007812ff); // reserved buffer to normal read/write :8/7
+  mt_emi_sync_write(EMI_APB_BASE+0x00000068,0x00000000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000078,0x11120c1f);  //22:20=ultra_w=1
+  mt_emi_sync_write(EMI_APB_BASE+0x00000710,0x11120c1f);  //22:20=ultra_w=1
+  mt_emi_sync_write(EMI_APB_BASE+0x0000007c,0x00001123);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000718,0x00001123);
+  mt_emi_sync_write(EMI_APB_BASE+0x000000d0,0xa8a8a8a8);
+  mt_emi_sync_write(EMI_APB_BASE+0x000000d4,0x25252525);
+  mt_emi_sync_write(EMI_APB_BASE+0x000000d8,0xa8a8a8a8);
+  mt_emi_sync_write(EMI_APB_BASE+0x000000dc,0x25252525);
+  mt_emi_sync_write(EMI_APB_BASE+0x000000e8,0x00060037); // initial starvation counter div2, [4]=1
+  mt_emi_sync_write(EMI_APB_BASE+0x000000f0,0x384a0014);
+  mt_emi_sync_write(EMI_APB_BASE+0x000000f8,0xa0000000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000100,0x20107244);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000108,0x10107044);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000110,0x343450df);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000118,0x0000f0d0);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000120,0x10106048);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000128,0x343450df);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000130,0x83837044);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000138,0x83837044);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000140,0x00007108);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000144,0x00007108);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000150,0x090a0000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000158,0xff0bff00);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000400,0x00ff0001); //[27:20] enable monitor
+  mt_emi_sync_write(EMI_APB_BASE+0x0000071c,0x10000008);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000800,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000820,0x24240101);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000824,0x01012424);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000828,0x50500101);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000082c,0x01015050);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000830,0x0fc39a30); // [6] MD_HRT_URGENT_MASK, if 1 -> mask MD_HRT_URGENT,
+  mt_emi_sync_write(EMI_APB_BASE+0x00000834,0x05050003);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000838,0x254dffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000083c,0x465a788c); //update
+  mt_emi_sync_write(EMI_APB_BASE+0x00000840,0x000003e8);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000844,0x0000036b);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000848,0x00000290);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000084c,0x00000200);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000850,0x00000000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000854,0x00000000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000858,0x02531cff); //ignore rff threshold
+  mt_emi_sync_write(EMI_APB_BASE+0x0000085c,0x00002785); //disable internal MD latency urgent mask
+  mt_emi_sync_write(EMI_APB_BASE+0x00000874,0x000001b5);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000878,0x003c0000); //update
+  mt_emi_sync_write(EMI_APB_BASE+0x0000087c,0x0255250d);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000890,0xffff3c59);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000894,0xffff00ff);
+  mt_emi_sync_write(EMI_APB_BASE+0x000008a0,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x000008a4,0x0000ffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x000008c0,0x0000014b);
+  mt_emi_sync_write(EMI_APB_BASE+0x000008c4,0x002d0000); //update
+  mt_emi_sync_write(EMI_APB_BASE+0x000008c8,0x00000185);
+  mt_emi_sync_write(EMI_APB_BASE+0x000008cc,0x003c0000); //update
+  mt_emi_sync_write(EMI_APB_BASE+0x000008d0,0x00000185);
+  mt_emi_sync_write(EMI_APB_BASE+0x000008d4,0x003c0000); //update
+  mt_emi_sync_write(EMI_APB_BASE+0x000008e0,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x000008e4,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x000008e8,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000920,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000924,0x0000ffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000930,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000934,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000938,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x000009f0,0x41547082);
+  mt_emi_sync_write(EMI_APB_BASE+0x000009f4,0x38382a38);
+  mt_emi_sync_write(EMI_APB_BASE+0x000009f8,0x000001d4);
+  mt_emi_sync_write(EMI_APB_BASE+0x000009fc,0x00000190);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000b00,0x0000012c);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000b04,0x000000ed);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000b08,0x000000c8);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000b0c,0x00000096);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000b10,0x000000c8);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000b14,0x000000c8);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000b28,0x26304048);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000b2c,0x20201820);
+
+  mt_emi_sync_write(EMI_APB_BASE+0x00000b60,0x181e282f);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000b64,0x14140f18);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000b98,0x7496c8ea);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000b9c,0x64644b64);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000bd0,0x01010101);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000bd4,0x01010101);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000c08,0x7496c8ea);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000c0c,0x64644b64);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000c40,0x01010101);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000c44,0x01010101);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000c4c,0x300ff025);	//ignore wff threshold
+  mt_emi_sync_write(EMI_APB_BASE+0x00000c80,0x000003e8);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000c84,0x0000036b);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000c88,0x00000290);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000c8c,0x00000200);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000c90,0x000001b5);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000c94,0x0000014b);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000c98,0x00000185);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000c9c,0x00000185);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000cb0,0x52698ca0);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000cb4,0x46463546);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000cf8,0x01010101);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000cfc,0x01010101);
+
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d04,0x00000009); //MDR shf0 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d0c,0x00000000); //MDR shf1 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d14,0x00730000); //MDR shf0
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d18,0x00000808); //MDR shf1
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d1c,0x00000028); //MDW shf0 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d24,0x00000000); //MDW shf1 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d2c,0x00730000); //MDW shf0
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d30,0x00000808); //MDW shf1
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d34,0x00000080); //APR shf0 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d3c,0x00000000); //APR shf1 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d44,0x30201008); //APR shf0/shf1
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d48,0x00000800); //APW shf0 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d50,0x00000000); //APW shf1 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d58,0x00008000); //MMR shf0 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d60,0x00020000); //MMR shf1 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d64,0x00001000); //MMR shf1 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d68,0x00010000); //MMR shf2 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d6c,0x00000800); //MMR shf2 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d70,0x08080000); //MMR shf0
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d74,0x00073030); //MMR shf1
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d78,0x00040000); //MMW shf0 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d80,0x00100000); //MMW shf1 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d84,0x00004000); //MMW shf1 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d88,0x00080000); //MMW shf2 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d8c,0x00002000); //MMW shf2 event selet
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d90,0x08080000); //MMW shf0
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d94,0x00074040); //MMW shf1
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d98,0x00400000); //MDHWR sh0 event select
+  mt_emi_sync_write(EMI_APB_BASE+0x00000da0,0x00200000); //MDHWR sh1 event select
+  mt_emi_sync_write(EMI_APB_BASE+0x00000da8,0x10100404); //MDHWWR sh
+  mt_emi_sync_write(EMI_APB_BASE+0x00000dac,0x01000000); //MDHWW sh0 event select
+  mt_emi_sync_write(EMI_APB_BASE+0x00000db4,0x00800000); //MDHWW sh1 event select
+  mt_emi_sync_write(EMI_APB_BASE+0x00000dbc,0x04000000); //GPUR sh0 event select
+  mt_emi_sync_write(EMI_APB_BASE+0x00000dc4,0x02000000); //GPUR sh1 event select
+  mt_emi_sync_write(EMI_APB_BASE+0x00000dcc,0x60602010); //GPUR
+  mt_emi_sync_write(EMI_APB_BASE+0x00000dd0,0x10000000); //GPUW sh0 event select
+  mt_emi_sync_write(EMI_APB_BASE+0x00000dd8,0x08000000); //GPUW sh1 event select
+  mt_emi_sync_write(EMI_APB_BASE+0x00000de0,0x00000009); //ARBR sh0 event select
+  mt_emi_sync_write(EMI_APB_BASE+0x00000de8,0x04400080); //ARBR sh1 event select
+  mt_emi_sync_write(EMI_APB_BASE+0x00000df0,0x0f170f11); //ARB
+  mt_emi_sync_write(EMI_APB_BASE+0x00000df4,0x0303f7f7); //QOS control
+  mt_emi_sync_write(EMI_APB_BASE+0x00000e04,0x00000166);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000e08,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000e0c,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000e14,0x00400166);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000e18,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000e1c,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000e24,0x00000266);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000e28,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000e2c,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000e34,0x00400266);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000e38,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000e3c,0xffffffff);
+
+  // Added by Wei-Lun - START
+  // prtcl chker - golden setting
+  mt_emi_sync_write(EMI_APB_BASE+0x00000304,0xffffffff); // cyc
+  mt_emi_sync_write(EMI_APB_BASE+0x0000030c,0x001ffc85); // ctl
+  mt_emi_sync_write(EMI_APB_BASE+0x00000314,0xffffffff); // msk
+
+  mt_emi_sync_write(EMI_APB_BASE+0x0000034c,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000354,0x001ffc85);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000035c,0xffffffff); // msk
+
+  mt_emi_sync_write(EMI_APB_BASE+0x00000394,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000039c,0x001ffc85);
+  mt_emi_sync_write(EMI_APB_BASE+0x000003a4,0xffffffff); // msk
+
+  mt_emi_sync_write(EMI_APB_BASE+0x000003d8,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x000003dc,0x001ffc85);
+  mt_emi_sync_write(EMI_APB_BASE+0x000003e0,0xffffffff); // msk
+
+  mt_emi_sync_write(EMI_APB_BASE+0x000003fc,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000040c,0x001ffc85);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000414,0xffffffff); // msk
+
+  mt_emi_sync_write(EMI_APB_BASE+0x0000044c,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000454,0x001ffc85);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000045c,0xffffffff); // msk
+
+  mt_emi_sync_write(EMI_APB_BASE+0x0000049c,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x000004a4,0x001ffc85);
+  mt_emi_sync_write(EMI_APB_BASE+0x000004ac,0xffffffff); // msk
+
+  mt_emi_sync_write(EMI_APB_BASE+0x0000050c,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000514,0x001ffc85);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000051c,0xffffffff); // msk
+
+  //weilun for new feature
+  mt_emi_sync_write(EMI_APB_BASE+0x00000714,0x00000000); // dvfs level setting for chn_emi rw switching shf
+
+  // cen_emi timeout value
+  mt_emi_sync_write(EMI_APB_BASE+0x00000628,0x60606060);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000062c,0x60606060);
+
+  // fine-grained qos
+  mt_emi_sync_write(EMI_APB_BASE+0x00000050,0x00000000);
+
+  // ostd->bw
+  mt_emi_sync_write(EMI_APB_BASE+0x0000061c,0x08ffbbff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000624,0xffff5b3c);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000774,0xffff00ff);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000077c,0x00ffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000784,0xffff00ff);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000078c,0x00ffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000958,0x00000000);
+
+  // hash rule
+  //mt_emi_sync_write(EMI_APB_BASE+0x000007a4,0xC0000000);
+}
+
+static void emi_chn_config(void)  {
+
+#ifdef RANK_512MB  // => 2channel , dual rank , total=2G
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x0400a051);
+#else
+  #ifdef RANK_1GB //RANK_1G  => 2channel , dual rank , total=4G
+    mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x0400f051);
+  #else
+    #ifdef RANK_2GB
+      mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x0400005D);
+    #endif
+  #endif
+#endif
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000008,0x00ff6048);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000010,0x00000004);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000018,0x99f08c03);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000710,0x9a508c17); // [24:20] = 0x2 : bank throttling (default=0x01f00000)
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000048,0x00038137); //RD_INORDER_THR[20:16]=2
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000050,0x38460002); // [1] : MD_RD_AFT_WR_EN
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000058,0x00000000);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000090,0x000002ff);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000098,0x00003111); //mw2
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000140,0x22607188);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000144,0x22607188);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000148,0x3719595e); // chuan
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000014c,0x2719595e); // chuan
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000150,0x64f3ff79);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000154,0x64f3ff79); // update timeout setting: bit 12~15
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000158,0x011b0868);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000015c,0xa7414222); // Stop urgent read first when write command buffer remain < 7, [31] ultra_read_first, [30:28] wr_rsv_thr_l, [27:    24] wr_rsv_thr_h, 
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000016c,0x0000f801);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000170,0x40000000);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0,0x000c802f); // Rank-Aware arbitration
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b4,0xbd3f3f7e); // Rank-Aware arbitration
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b8,0x7e003d7e); // Rank-Aware arbitration
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000003fc,0x00000000); // Write M17_toggle_mask = 0
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000080,0xaa0148ff);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000088,0xaa6168ff);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000404,0xaa516cff);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000408,0xaa0140ff);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000040c,0x9f658633);
+}
+
+static void emi_sw_setting(void)
+{
+	//int emi_isu;
+	int emi_dcm;
+	//char *str;
+
+	enable_infra_emi_broadcast(1);
+
+	/* mpu irq settings. separate emi mpu and devmpu irq */
+	*((volatile unsigned int *) EMI_CONH) = *((volatile unsigned int *) EMI_CONH) | 0xC0;
+
+	/* for DVFS BW monitor */
+	*((volatile unsigned int *) EMI_BWCT0) = 0x05000305;
+	*((volatile unsigned int *) EMI_BWCT0_6TH) = 0x08FF0705;
+	*((volatile unsigned int *) EMI_BWCT0_3RD) = 0x0DFF0A05;
+	*((volatile unsigned int *) EMI_BWCT0_4TH) = 0x7FFF0F05;
+
+	enable_infra_emi_broadcast(0);
+
+#ifdef LAST_EMI
+	last_emi_info_ptr = (LAST_EMI_INFO_T *) get_dbg_info_base(KEY_LAST_EMI);
+	if (last_emi_info_ptr->isu_magic != LAST_EMI_MAGIC_PATTERN) {
+		last_emi_info_ptr->isu_magic = LAST_EMI_MAGIC_PATTERN;
+		last_emi_info_ptr->isu_version = 0xFFFFFFFF;
+		last_emi_info_ptr->isu_dram_type = 0;
+		last_emi_info_ptr->isu_diff_us = 0;
+		last_emi_info_ptr->os_flag_sspm = 0;
+		last_emi_info_ptr->os_flag_ap = 0;
+	}
+
+	str = dconfig_getenv("emi_isu");
+	emi_isu = (str) ? atoi(str) : 0;
+	emi_log("[EMI DOE] emi_isu %d\n", emi_isu);
+	if (emi_isu == 1)
+		last_emi_info_ptr->isu_ctrl = 0xDECDDECD;
+	else if (emi_isu == 2)
+		last_emi_info_ptr->isu_ctrl = 0xDEC0DEC0;
+	else {
+#if CFG_LAST_EMI_BW_DUMP
+		last_emi_info_ptr->isu_ctrl = 0xDECDDECD;
+#else
+		last_emi_info_ptr->isu_ctrl = 0xDEC0DEC0;
+#endif
+	}
+#endif
+
+	/* align urgent monitor countrol to bus monitor */
+	*((volatile unsigned int *)0x10219858) |= 0x1 << 11;
+
+	/* EMI doeapp for DCM */
+	emi_dcm = 0;
+	emi_log("[EMI DOE] emi_dcm %d\n", emi_dcm);
+	if (emi_dcm == 1) {
+		*((volatile unsigned int *)EMI_CONM) &= ~0xFF000000;
+		*((volatile unsigned int *)EMI_CONN) &= ~0xFF000000;
+	} else if (emi_dcm == 2) {
+		*((volatile unsigned int *)EMI_CONM) |= 0xFF000000;
+		*((volatile unsigned int *)EMI_CONN) |= 0xFF000000;
+	}
+
+	dsb();
+}
+
+void emi_init(void)
+{
+	//unsigned int emi_mpu_slverr = 0;
+	//unsigned int domain = 0;
+	//char *str;
+
+	mt_emi_sync_write(EMI_BASE+0x000007a4, 0xC0000000);     // config emi for 2+2CH
+#ifdef SUB_EMI_BASE
+	mt_emi_sync_write(SUB_EMI_BASE+0x000007a4, 0xD0000000); // config sub emi for 2+2CH
+#endif
+
+	enable_infra_emi_broadcast(1);
+ 
+   emi_cen_config();
+   emi_chn_config();
+ 
+	enable_infra_emi_broadcast(0);
+}
+
+void emi_init2(void)
+{
+  unsigned int emi_temp_data;
+
+  enable_infra_emi_broadcast(1);
+
+  mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000010, 0x00000001);   // [0] EMI enable
+  mt_emi_sync_write_or(EMI_BASE+0x00000060, 0x00000400);        //[10] EMI enable
+
+  #ifdef REAL_CHIP_EMI_GOLDEN_SETTING
+
+
+  mt_emi_sync_write_or(EMI_MPU_BASE+0x00000000,0x00000010); // [4] Disable emi_mpu_reg interrupt
+
+  // Clear rank_arb_en
+  emi_temp_data = mt_emi_sync_read(EMI_CHANNEL_APB_BASE+0x000001b0); // read ch0
+  emi_temp_data = emi_temp_data & ~(0x1);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0, emi_temp_data); // broadcast to all channel
+  // auto-config rank_arb_en according to dual_rank_en setting
+  // assume all channel with same configuration
+  emi_temp_data = mt_emi_sync_read(EMI_CHANNEL_APB_BASE+0x00000000); // read ch0
+  emi_temp_data = emi_temp_data & 0x1;
+  mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x000001b0, emi_temp_data); // broadcast to all channel
+
+  enable_infra_emi_broadcast(0);
+
+  // ----- from dcm_setting.c -----
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x100, 0xFFFFFFFF);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x104, 0xFFFFFFFF);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x108, 0xFFFFFFFF);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x10C, 0xFFFFFFFF);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x110, 0x06000003);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x114, 0x40000000);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x118, 0xC0201800);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x11C, 0x00000000);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x120, 0x180003FC);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x124, 0x80000000);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x128, 0x06000001);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x12C, 0x00000600);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x130, 0x20003C00);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x134, 0x00000000);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x138, 0x00080000);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x13C, 0x00000000);
+  //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x140, 0x60003C00);
+  //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x144, 0x10000006);
+  //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x148, 0x00090000);
+  //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x14C, 0x02100800);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x150, 0x80FF8000);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x154, 0x00000001);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x158, 0x3000E018);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x15C, 0x0106019F);
+  //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x160, 0x00000000);
+  //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x164, 0x011FFFF8);
+  //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x168, 0x084007E0);
+  //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x16C, 0x00600006);
+  //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x170, 0x00000000);
+  //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x174, 0x00000000);
+  //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x178, 0x000001A0);
+  //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x17C, 0x1C800000);
+
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x020, 0xFFFFFFFF);
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x024, 0xFFFFFFFF);
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x210, 0x00000000);
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x214, 0x06007FE0);
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x218, 0x0000003F);
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x21C, 0x0003000C);
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x220, 0x00000380);
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x224, 0x00000000);
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x228, 0x00C08000);
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x22C, 0x01000000);
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x230, 0xCF3F3000);
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x234, 0x30008013);
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x238, 0x00000000);
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x23C, 0x00000000);
+
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x028, 0x0018002F);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x02C, 0x40000000);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x030, 0x00000044);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x034, 0x00000000);
+
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x028, 0x000D007F);
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x02C, 0x40000000);
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x030, 0x00000044);
+  mt_emi_sync_write(SUB_INFRACFG_AO_MEM_BASE+0x034, 0x00000000);
+
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x038, 0xA00001FF);
+
+  mt_emi_sync_write_or(INFRACFG_AO_BASE+0x00000078, 0x08000000); // enable infra_local_cg
+
+  #ifdef EMI_MP_SETTING
+  // Enable rdata_prty_gen & wdata_prty_chk
+  mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00400000);  // enable cen_emi parity (w)
+
+  // emi bus parity workaround
+  emi_temp_data = mt_emi_sync_read(0x40000000);
+  mt_emi_sync_write(0x40000000, emi_temp_data);
+  emi_temp_data = mt_emi_sync_read(0x40000100);
+  mt_emi_sync_write(0x40000100, emi_temp_data);
+  emi_temp_data = mt_emi_sync_read(0x40000200);
+  mt_emi_sync_write(0x40000200, emi_temp_data);
+  emi_temp_data = mt_emi_sync_read(0x40000300);
+  mt_emi_sync_write(0x40000300, emi_temp_data);
+
+  mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x00000050,0x00000004); // enable chn_emi parity
+
+  //// Enable APMCU Early CKE
+  //// set reg_chn_en
+  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
+  //emi_temp_data = (emi_temp_data >>  6) & (0x1<<2);
+  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
+  //// set reg_chn_pos
+  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
+  //emi_temp_data = (emi_temp_data <<  2) & (0x3<<4);
+  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
+  //// set reg_chn_loc
+  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
+  //emi_temp_data = (emi_temp_data >>  4) & (0x1<<6);
+  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
+  //// set reg_dual_rank_en
+  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
+  //emi_temp_data = (emi_temp_data >> 10) & (0x1<<7);
+  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
+  //// set reg_cas_size[1:0]
+  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
+  //emi_temp_data = (emi_temp_data >>  9) & (0x3<<9);
+  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
+  //// set reg_cas_size[2]
+  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
+  //emi_temp_data = (emi_temp_data << 11) & (0x1<<11);
+  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
+  //// set reg_cas_size[3]
+  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
+  //emi_temp_data = (emi_temp_data >> 14) & (0x1<<12);
+  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
+  //// set reg_remap_shift
+  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, 0x00006000);
+  //// set reg_rank_dec0
+  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000038);
+  //emi_temp_data = (emi_temp_data <<  2) & (0x1f<<18);
+  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
+  //// set reg_rank_cke_ext and reg_enable
+  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, 0x11000001);
+  //// set to mcusys
+  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x000007f4);
+  //mt_emi_sync_write(MCUSYS_PAR_WRAP_BASE+0x0000a490, emi_temp_data);
+
+  /*TINFO="program hash rule"*/
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000021);
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000021); // set disph_chg_en = 0x1
+
+  /*TINFO="read emi_reg_pd then write apmcu config reg"*/
+  emi_temp_data = mt_emi_sync_read(INFRACFG_AO_MEM_BASE+0x050);
+  emi_temp_data = emi_temp_data & 0xf;
+  mt_emi_sync_write_or(EMI_BASE+0x07A4, emi_temp_data);
+
+  /*TINFO="Enable EMI wdata bus encode function"*/
+  mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00200000); // enable cen_emi wdata bus encode          // *EMI_CONN |= (0x1 << 21);
+  mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x00000050,0x00000010); // enable chn_emi wdata bus encode  // *CHN0_EMI_CHN_EMI_DFTC |= (0x1 <<4);
+  #else
+  // MP_dsim_v02 test (from v01) - all fr
+  //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x028, 0x003F0000);
+  //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x02C, 0xA0000000);
+  #endif
+
+  #endif
+
+
+  /*TINFO="program hash rule"*/
+  if (channel_num_auxadc == CHANNEL_FOURTH)
+  	{
+      mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000021);
+      mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000021); // set disph_chg_en = 0x1
+  	}
+  else /* CHANNEL_DUAL */
+  	{
+      mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000007);
+      mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000007); // set disph_chg_en = 0x1
+  	}
+
+
+  /*TINFO="read emi_reg_pd then write apmcu config reg"*/
+  emi_temp_data = mt_emi_sync_read(INFRACFG_AO_MEM_BASE+0x050);
+  emi_temp_data = emi_temp_data & 0xf;
+
+  enable_infra_emi_broadcast(1);
+  mt_emi_sync_write_or(EMI_BASE+0x07A4, emi_temp_data);
+
+  mt_emi_sync_write(CHN0_EMI_BASE+0x0020, 0x00000040); // disable EBG
+  enable_infra_emi_broadcast(0);
+
+  emi_sw_setting();
+}
+
+int get_row_width_by_emi(unsigned int rank)
+{
+	unsigned int emi_cona;
+	unsigned int shift_row, shift_ext;
+	int row_width;
+
+	if (rank == 0) {
+		shift_row = 12;
+		shift_ext = 22;
+	} else if (rank == 1) {
+		shift_row = 14;
+		shift_ext = 23;
+	} else
+		return -1;
+
+	emi_cona = mt_emi_sync_read(EMI_CONA);
+	row_width =
+		((emi_cona >> shift_row) & 0x3) |
+		((emi_cona >> shift_ext) & 0x4);
+
+	return (row_width + 13);
+}
+
+int get_channel_nr_by_emi(void)
+{
+	int channel_nr;
+
+	channel_nr = 0x1 << ((mt_emi_sync_read(EMI_CONA) >> 8) & 0x3);
+
+#ifdef SUB_EMI_BASE
+	channel_nr *= 2;
+#endif
+#if DRAM_AUXADC_CONFIG
+	U32 ret = 0, voltage = 0;
+	ret = iio_read_channel_processed(5, &voltage);
+	if (ret == 0)
+		if (voltage < 700)
+			channel_nr = CHANNEL_FOURTH;
+		else
+			channel_nr = CHANNEL_DUAL;
+	else
+		emi_log("Error! Read AUXADC value fail\n");
+#endif
+
+	return channel_nr;
+}
+
+int get_rank_nr_by_emi(void)
+{
+	unsigned int cen_emi_cona = mt_emi_sync_read(EMI_CONA);
+
+	if (cen_emi_cona & (0x3 << 16))
+		return 2;
+	else
+		return 1;
+}
+
+_Static_assert(DRAMC_MAX_RK > 1, "rank number is violated");
+void get_rank_size_by_emi(unsigned long long dram_rank_size[DRAMC_MAX_RK])
+{
+	//int i;
+	unsigned int quad_ch_ratio;
+	//unsigned int col_bit, row_bit;
+	unsigned long long ch0_rank0_size, ch0_rank1_size;
+	unsigned long long ch1_rank0_size, ch1_rank1_size;
+	unsigned int cen_emi_conh = mt_emi_sync_read(EMI_CONH);
+	unsigned long long dq_width;
+
+	switch (mt_get_dram_type_from_hw_trap()) {
+		case TYPE_LPDDR4X:
+		case TYPE_LPDDR4:
+			dq_width = 2;
+			break;
+		default:
+			ASSERT(0);
+	}
+
+	dram_rank_size[0] = 0;
+	dram_rank_size[1] = 0;
+
+	ch0_rank0_size = (cen_emi_conh >> 16) & 0xF;
+	ch0_rank1_size = (cen_emi_conh >> 20) & 0xF;
+	ch1_rank0_size = (cen_emi_conh >> 24) & 0xF;
+	ch1_rank1_size = (cen_emi_conh >> 28) & 0xF;
+
+	quad_ch_ratio = (get_channel_nr_by_emi() == 4)? 2 : 1;
+
+	ch0_rank0_size = (ch0_rank0_size * quad_ch_ratio) << 28;
+	ch0_rank1_size = (ch0_rank1_size * quad_ch_ratio) << 28;
+	ch1_rank0_size = (ch1_rank0_size * quad_ch_ratio) << 28;
+	ch1_rank1_size = (ch1_rank1_size * quad_ch_ratio) << 28;
+
+	if(ch0_rank0_size == 0) {
+		emi_log("[EMI] undefined CONH for CH0 RANK0\n");
+		ASSERT(0);
+	}
+	dram_rank_size[0] += ch0_rank0_size;
+
+	if (get_rank_nr_by_emi() > 1) {
+		if(ch0_rank1_size == 0) {
+			emi_log("[EMI] undefined CONH for CH0 RANK1\n");
+			ASSERT(0);
+		}
+		dram_rank_size[1] += ch0_rank1_size;
+	}
+
+	if(get_channel_nr_by_emi() > 1) {
+		if(ch1_rank0_size == 0) {
+			emi_log("[EMI] undefined CONH for CH1 RANK0\n");
+			ASSERT(0);
+		}
+		dram_rank_size[0] += ch1_rank0_size;
+
+		if (get_rank_nr_by_emi() > 1) {
+			if(ch1_rank1_size == 0) {
+				emi_log("[EMI] undefined CONH for CH1 RANK1\n");
+				ASSERT(0);
+			}
+			dram_rank_size[1] += ch1_rank1_size;
+		}
+	}
+
+	emi_log("DRAM rank0 size:0x%llx,\nDRAM rank1 size=0x%llx\n",
+			dram_rank_size[0], dram_rank_size[1]);
+}
+
+void set_cen_emi_cona(unsigned int cona_val)
+{
+	mt_emi_sync_write(EMI_CONA, cona_val);
+}
+
+void set_cen_emi_conf(unsigned int conf_val)
+{
+	mt_emi_sync_write(EMI_CONF, conf_val);
+}
+
+void set_cen_emi_conh(unsigned int conh_val)
+{
+	mt_emi_sync_write(EMI_CONH, conh_val);
+}
+
+void set_chn_emi_cona(unsigned int cona_val)
+{
+	mt_emi_sync_write(CHN_EMI_CONA(CHN0_EMI_BASE), cona_val);
+	mt_emi_sync_write(CHN_EMI_CONA(CHN1_EMI_BASE), cona_val);
+}
+
+void set_chn_emi_conc(unsigned int conc_val)
+{
+	mt_emi_sync_write(CHN_EMI_CONC(CHN0_EMI_BASE), conc_val);
+	mt_emi_sync_write(CHN_EMI_CONC(CHN1_EMI_BASE), conc_val);
+}
+
+void enable_infra_emi_broadcast(unsigned int enable)
+{
+	if (enable)
+		mt_emi_sync_write(INFRA_DRAMC_REG_CONFIG, 0x00027f7f);
+	else
+		mt_emi_sync_write(INFRA_DRAMC_REG_CONFIG, 0x00000000);
+}
+
+unsigned int get_cen_emi_cona(void)
+{
+	return mt_emi_sync_read(EMI_CONA);
+}
+
+/* assume all chn emi setting are the same */
+unsigned int get_chn_emi_cona(void)
+{
+	unsigned int ch0_emi_cona;
+
+	ch0_emi_cona = mt_emi_sync_read(CHN0_EMI_BASE);
+
+	return ch0_emi_cona;
+}
+
+void phy_addr_to_dram_addr(dram_addr_t *dram_addr, unsigned long long phy_addr)
+{
+	unsigned int cen_emi_cona, cen_emi_conf;
+	unsigned long long rank_size[DRAMC_MAX_RK];
+	unsigned int channel_num, rank_num;
+	unsigned int bit_scramble, bit_xor, bit_shift, channel_pos, channel_width;
+	unsigned int temp;
+	unsigned int index;
+
+	cen_emi_cona = mt_emi_sync_read(EMI_CONA);
+	cen_emi_conf = mt_emi_sync_read(EMI_CONF) >> 8;
+	get_rank_size_by_emi(rank_size);
+	rank_num = (unsigned int) get_rank_nr_by_emi();
+	channel_num = (unsigned int) get_channel_nr_by_emi();
+
+	phy_addr -= 0x40000000;
+	for (index = 0; index < rank_num; index++) {
+		if (phy_addr >= rank_size[index])
+			phy_addr -= rank_size[index];
+		else
+			break;
+	}
+
+	for (bit_scramble = 11; bit_scramble < 17; bit_scramble++) {
+		bit_xor = (cen_emi_conf >> (4 * (bit_scramble - 11))) & 0xf;
+		bit_xor &= phy_addr >> 16;
+		for (bit_shift = 0; bit_shift < 4; bit_shift++)
+			phy_addr ^= ((bit_xor>>bit_shift)&0x1) << bit_scramble;
+	}
+
+	if (channel_num > 1) {
+		channel_pos = ((cen_emi_cona >> 2) & 0x3) + 7;
+
+		for (channel_width = bit_shift = 0; bit_shift < 4; bit_shift++) {
+			if ((unsigned int)(1 << bit_shift) >= channel_num)
+				break;
+			channel_width++;
+		}
+
+		switch (channel_width) {
+		case 2:
+			dram_addr->addr = ((phy_addr & ~(((0x1 << 2) << channel_pos) - 1)) >> 2);
+			break;
+		default:
+			dram_addr->addr = ((phy_addr & ~(((0x1 << 1) << channel_pos) - 1)) >> 1);
+			break;
+		}
+		dram_addr->addr |= (phy_addr & ((0x1 << channel_pos) - 1));
+	}
+
+	temp = dram_addr->addr >> 1;
+	switch ((cen_emi_cona >> 4) & 0x3) {
+	case 0:
+		dram_addr->col = temp & 0x1FF;
+		temp = temp >> 9;
+		break;
+	case 1:
+		dram_addr->col = temp & 0x3FF;
+		temp = temp >> 10;
+		break;
+	case 2:
+	default:
+		dram_addr->col = temp & 0x7FF;
+		temp = temp >> 11;
+		break;
+	}
+	dram_addr->bk = temp & 0x7;
+	temp = temp >> 3;
+
+	dram_addr->row = temp;
+
+	emi_log("[EMI] ch%d, rk%d, dram addr: %x\n", dram_addr->ch, dram_addr->rk, dram_addr->addr);
+	emi_log("[EMI] bk%x, row%x, col%x\n", dram_addr->bk, dram_addr->row, dram_addr->col);
+}
+
+static unsigned int cen_emi_conh_backup = 0;
+static unsigned int chn_emi_cona_backup = 0;
+
+/* return the start address of rank1 */
+unsigned int set_emi_before_rank1_mem_test(void)
+{
+	cen_emi_conh_backup = mt_emi_sync_read(EMI_CONH);
+	chn_emi_cona_backup = get_chn_emi_cona();
+
+	enable_infra_emi_broadcast(1);
+	if (get_rank_nr_by_emi() == 2) {
+		/* set the rank size to 1GB for 2 channels */
+		mt_emi_sync_write(EMI_CONH,
+			(cen_emi_conh_backup & 0x0000ffff) | 0x22220000);
+		set_chn_emi_cona(
+			(chn_emi_cona_backup & 0xff00ffff) | 0x00220000);
+	} else {
+		/* set the rank size to 1GB for 1 channel */
+		mt_emi_sync_write(EMI_CONH,
+			(cen_emi_conh_backup & 0x0000ffff) | 0x44440000);
+		set_chn_emi_cona(
+			(chn_emi_cona_backup & 0xff00ffff) | 0x00440000);
+	}
+	enable_infra_emi_broadcast(0);
+
+	return 0x40000000;
+}
+
+void restore_emi_after_rank1_mem_test(void)
+{
+	enable_infra_emi_broadcast(1);
+	mt_emi_sync_write(EMI_CONH, cen_emi_conh_backup);
+	set_chn_emi_cona(chn_emi_cona_backup);
+	enable_infra_emi_broadcast(0);
+}
+
+void get_emi_isu_info(struct isu_info_t *isu_info_ptr)
+{
+#ifdef LAST_EMI
+	last_emi_info_ptr = (LAST_EMI_INFO_T *) get_dbg_info_base(KEY_LAST_EMI);
+	isu_info_ptr->buf_size = EMI_ISU_BUF_SIZE;
+	isu_info_ptr->buf_addr = (unsigned long long)last_emi_info_ptr->isu_buf_h;
+	isu_info_ptr->buf_addr <<= 32;
+	isu_info_ptr->buf_addr += (unsigned long long)last_emi_info_ptr->isu_buf_l;
+	isu_info_ptr->ver_addr = (unsigned long long)(&(last_emi_info_ptr->isu_version));
+	isu_info_ptr->con_addr = (unsigned long long)(&(last_emi_info_ptr->isu_ctrl));
+#endif
+}
+
+void clr_emi_mpu_prot(void)
+{
+}
+
+void dis_emi_apb_prot(void)
+{
+	mt_emi_sync_write(EMI_MPU_CTRL, 0xFFFFFFFE);
+
+	emi_log("[EMI] EMI_MPU_CTRL 0x%x\n", mt_emi_sync_read(EMI_MPU_CTRL));
+}
+
+int update_emi_setting(EMI_SETTINGS *default_emi_setting, EMI_INFO_T *emi_info)
+{
+	unsigned int ddr_type;
+	unsigned int cen_cona_val, cen_conf_val, cen_conh_val, cen_conk_val;
+	unsigned int chn_cona_val;
+	unsigned int cen_conf_shf;
+	unsigned int col, row, row_ext, rk_size, rk_size_ext, rk_size_chn_ext;
+	unsigned int temp_val;
+	int i;
+
+	ddr_type = default_emi_setting->type & 0xFF;
+	cen_conh_val = 0x00000003;
+	cen_conk_val = mt_emi_sync_read(EMI_CONK) & 0x0000FFFF;
+	if (u1IsLP4Family(ddr_type)) {
+		cen_cona_val = 0x00000104;
+		chn_cona_val = 0x04000000;
+	} else {
+		cen_cona_val = 0x00000006;
+		chn_cona_val = 0x00000002;
+	}
+
+	for (i = 0; i < emi_info->rk_num; i++) {
+		row = emi_info->row_width[i] - 13;
+		row_ext = row >> 2;
+		row &= 0x3;
+
+		col = emi_info->col_width[i] - 9;
+
+		rk_size = emi_info->rank_size[i] >> 28;
+		if (u1IsLP4Family(ddr_type))
+			rk_size >>= 1;
+		rk_size_ext = rk_size >> 4;
+		rk_size_chn_ext = rk_size_ext & 0x1;
+		rk_size &= 0xF;
+
+		if (i == 1) {
+			col <<= 2;
+			row <<= 2;
+			row_ext <<= 1;
+			rk_size <<= 4;
+			rk_size_ext <<= 4;
+			rk_size_chn_ext <<= 1;
+			cen_cona_val |= 0x00030000;
+			chn_cona_val |= 0x00000001;
+		}
+
+		cen_cona_val |=
+			(col << 4) | (row << 12) | (col << 20) |
+			(row_ext << 24) | (row << 28);
+		cen_conh_val |=
+			(row_ext << 4) | (rk_size << 16) | (rk_size << 24);
+		cen_conk_val |=
+			(rk_size_ext << 16) | (rk_size_ext << 24);
+		chn_cona_val |=
+			(row_ext << 2) | (col << 4) | (row << 12) |
+			(rk_size << 16) | (rk_size_chn_ext << 8);
+	}
+
+	cen_conf_shf = 0;
+	for (i = 0; i < emi_info->rk_num; i++) {
+		temp_val = 2 + emi_info->col_width[i];
+		if (cen_conf_shf < temp_val)
+			cen_conf_shf = temp_val;
+	}
+
+	if (((cen_conf_shf - 9) * 4) < 21)
+		cen_conf_val = 0x421 << ((cen_conf_shf - 9) * 4);
+	else
+		return -1;
+
+	emi_log("[EMI] %s(0x%x),%s(0x%x),%s(0x%x),%s(0x%x),%s(0x%x)\n",
+			"CEN_CONA", cen_cona_val,
+			"CEN_CONF", cen_conf_val,
+			"CEN_CONH", cen_conh_val,
+			"CEN_CONK", cen_conk_val,
+			"CHN_CONA", chn_cona_val);
+
+	default_emi_setting->EMI_CONA_VAL = cen_cona_val;
+	default_emi_setting->EMI_CONF_VAL = cen_conf_val;
+	default_emi_setting->EMI_CONH_VAL = cen_conh_val;
+	default_emi_setting->EMI_CONK_VAL = cen_conk_val;
+	default_emi_setting->CHN0_EMI_CONA_VAL = chn_cona_val;
+	default_emi_setting->CHN1_EMI_CONA_VAL = chn_cona_val;
+
+	return 0;
+}
+
+#if !__ETT__
+void record_emi_snst(void)
+{
+#ifdef LAST_EMI
+	if (!last_emi_info_ptr)
+		last_emi_info_ptr =
+			(LAST_EMI_INFO_T *) get_dbg_info_base(KEY_LAST_EMI);
+
+	last_emi_info_ptr->snst_past = last_emi_info_ptr->snst_last;
+	last_emi_info_ptr->snst_last = mt_emi_sync_read(EMI_SNST);
+	emi_log("[EMI] SNST: 0x%x\n", last_emi_info_ptr->snst_last);
+
+	/* clear EMI_SNST and set target master to M5 */
+	mt_emi_sync_write(EMI_SNST, 0x85000000);
+#endif
+}
+
+unsigned long long platform_memory_size(void)
+{
+	static unsigned long long mem_size = 0;
+	int nr_rank;
+	int i;
+	unsigned long long rank_size[DRAMC_MAX_RK] = {0};
+
+	if (!mem_size) {
+		nr_rank = get_dram_rank_nr();
+
+		get_dram_rank_size(rank_size);
+
+		for (i = 0; i < nr_rank; i++)
+			mem_size += rank_size[i];
+	}
+
+	return mem_size;
+}
+#endif
+
diff --git a/src/vendorcode/mediatek/mt8195/include/8195_Register_DDRPHY_AO.h b/src/vendorcode/mediatek/mt8195/include/8195_Register_DDRPHY_AO.h
new file mode 100644
index 000000000000..5ea25dff9702
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/8195_Register_DDRPHY_AO.h
@@ -0,0 +1,3686 @@
+#ifndef __DDRPHY_AO_REGS_H__
+#define __DDRPHY_AO_REGS_H__
+
+#define Channel_A_DDRPHY_AO_BASE_ADDRESS    0x10238000
+#define Channel_B_DDRPHY_AO_BASE_ADDRESS    0x10248000
+
+#define DDRPHY_AO_BASE_ADDRESS     Channel_A_DDRPHY_AO_BASE_VIRTUAL
+
+#define DDRPHY_REG_PHYPLL0                                     (DDRPHY_AO_BASE_ADDRESS + 0x0000)
+    #define PHYPLL0_RG_RPHYPLL_SDM_SSC_EN                      Fld(1, 2) //[2:2]
+    #define PHYPLL0_RG_RPHYPLL_EN                              Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_PHYPLL1                                     (DDRPHY_AO_BASE_ADDRESS + 0x0004)
+    #define PHYPLL1_RG_RPHYPLL_TSTOP_EN                        Fld(1, 0) //[0:0]
+    #define PHYPLL1_RG_RPHYPLL_TSTOD_EN                        Fld(1, 1) //[1:1]
+    #define PHYPLL1_RG_RPHYPLL_TSTFM_EN                        Fld(1, 2) //[2:2]
+    #define PHYPLL1_RG_RPHYPLL_TSTCK_EN                        Fld(1, 3) //[3:3]
+    #define PHYPLL1_RG_RPHYPLL_TST_EN                          Fld(1, 4) //[4:4]
+    #define PHYPLL1_RG_RPHYPLL_TSTLVROD_EN                     Fld(1, 5) //[5:5]
+    #define PHYPLL1_RG_RPHYPLL_TST_SEL                         Fld(4, 8) //[11:8]
+
+#define DDRPHY_REG_PHYPLL2                                     (DDRPHY_AO_BASE_ADDRESS + 0x0008)
+    #define PHYPLL2_RG_RPHYPLL_RESETB                          Fld(1, 16) //[16:16]
+    #define PHYPLL2_RG_RPHYPLL_ATPG_EN                         Fld(1, 17) //[17:17]
+    #define PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN                     Fld(1, 21) //[21:21]
+    #define PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN                    Fld(1, 22) //[22:22]
+
+#define DDRPHY_REG_CLRPLL0                                     (DDRPHY_AO_BASE_ADDRESS + 0x0020)
+    #define CLRPLL0_RG_RCLRPLL_SDM_SSC_EN                      Fld(1, 2) //[2:2]
+    #define CLRPLL0_RG_RCLRPLL_EN                              Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_RK_B0_RXDVS0                                (DDRPHY_AO_BASE_ADDRESS + 0x0060)
+    #define RK_B0_RXDVS0_R_RK0_B0_DVS_LEAD_LAG_CNT_CLR         Fld(1, 26) //[26:26]
+    #define RK_B0_RXDVS0_R_RK0_B0_DVS_SW_CNT_CLR               Fld(1, 27) //[27:27]
+    #define RK_B0_RXDVS0_R_RK0_B0_DVS_SW_CNT_ENA               Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_RK_B0_RXDVS1                                (DDRPHY_AO_BASE_ADDRESS + 0x0064)
+    #define RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG                   Fld(16, 0) //[15:0]
+    #define RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD                  Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_RK_B0_RXDVS2                                (DDRPHY_AO_BASE_ADDRESS + 0x0068)
+    #define RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0         Fld(2, 16) //[17:16]
+    #define RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0          Fld(2, 18) //[19:18]
+    #define RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0    Fld(1, 23) //[23:23]
+    #define RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0         Fld(2, 24) //[25:24]
+    #define RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0          Fld(2, 26) //[27:26]
+    #define RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0    Fld(1, 28) //[28:28]
+    #define RK_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0                Fld(1, 29) //[29:29]
+    #define RK_B0_RXDVS2_R_RK0_DVS_MODE_B0                     Fld(2, 30) //[31:30]
+
+#define DDRPHY_REG_RK_B0_RXDVS3                                (DDRPHY_AO_BASE_ADDRESS + 0x006C)
+    #define RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0                Fld(8, 0) //[7:0]
+    #define RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0                Fld(8, 8) //[15:8]
+
+#define DDRPHY_REG_RK_B0_RXDVS4                                (DDRPHY_AO_BASE_ADDRESS + 0x0070)
+    #define RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0              Fld(9, 0) //[8:0]
+    #define RK_B0_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B0              Fld(9, 16) //[24:16]
+
+#define DDRPHY_REG_B0_LP_CTRL0                                 (DDRPHY_AO_BASE_ADDRESS + 0x0160)
+    #define B0_LP_CTRL0_RG_ARDMSUS_10_B0                       Fld(1, 0) //[0:0]
+    #define B0_LP_CTRL0_RESERVED_B0_LP_CTRL0_3_1               Fld(3, 1) //[3:1]
+    #define B0_LP_CTRL0_RG_ARDMSUS_10_B0_LP_SEL                Fld(1, 4) //[4:4]
+    #define B0_LP_CTRL0_RG_DA_PICG_B0_CTRL_LOW_BY_LPC          Fld(1, 5) //[5:5]
+    #define B0_LP_CTRL0_RESERVED_B0_LP_CTRL0_6_6               Fld(1, 6) //[6:6]
+    #define B0_LP_CTRL0_RG_TX_ARDQ_RESETB_B0_LP_SEL            Fld(1, 7) //[7:7]
+    #define B0_LP_CTRL0_RG_ARDQ_RESETB_B0_LP_SEL               Fld(1, 8) //[8:8]
+    #define B0_LP_CTRL0_RG_ARPI_RESETB_B0_LP_SEL               Fld(1, 9) //[9:9]
+    #define B0_LP_CTRL0_RESERVED_B0_LP_CTRL0_11_10             Fld(2, 10) //[11:10]
+    #define B0_LP_CTRL0_RG_B0_MS_SLV_LP_SEL                    Fld(1, 12) //[12:12]
+    #define B0_LP_CTRL0_RG_ARDLL_PHDET_EN_B0_LP_SEL            Fld(1, 13) //[13:13]
+    #define B0_LP_CTRL0_RG_B0_DLL_EN_OP_SEQ_LP_SEL             Fld(1, 14) //[14:14]
+    #define B0_LP_CTRL0_RESERVED_B0_LP_CTRL0_15                Fld(1, 15) //[15:15]
+    #define B0_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B0_LP_SEL           Fld(1, 16) //[16:16]
+    #define B0_LP_CTRL0_DA_ARPI_CG_MCK_B0_LP_SEL               Fld(1, 17) //[17:17]
+    #define B0_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B0_LP_SEL        Fld(1, 18) //[18:18]
+    #define B0_LP_CTRL0_DA_ARPI_CG_MCTL_B0_LP_SEL              Fld(1, 19) //[19:19]
+    #define B0_LP_CTRL0_DA_ARPI_CG_FB_B0_LP_SEL                Fld(1, 20) //[20:20]
+    #define B0_LP_CTRL0_DA_ARPI_CG_DQ_B0_LP_SEL                Fld(1, 21) //[21:21]
+    #define B0_LP_CTRL0_DA_ARPI_CG_DQM_B0_LP_SEL               Fld(1, 22) //[22:22]
+    #define B0_LP_CTRL0_DA_ARPI_CG_DQS_B0_LP_SEL               Fld(1, 23) //[23:23]
+    #define B0_LP_CTRL0_DA_ARPI_CG_DQSIEN_B0_LP_SEL            Fld(1, 24) //[24:24]
+    #define B0_LP_CTRL0_DA_ARPI_MPDIV_CG_B0_LP_SEL             Fld(1, 25) //[25:25]
+    #define B0_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B0_LP_SEL           Fld(1, 26) //[26:26]
+    #define B0_LP_CTRL0_DA_ARPI_MIDPI_EN_B0_LP_SEL             Fld(1, 27) //[27:27]
+    #define B0_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B0_LP_SEL      Fld(1, 28) //[28:28]
+    #define B0_LP_CTRL0_RG_ARPI_DDR400_EN_B0_LP_SEL            Fld(1, 29) //[29:29]
+    #define B0_LP_CTRL0_RG_MIDPI_EN_B0_OP_LP_SEL               Fld(1, 30) //[30:30]
+    #define B0_LP_CTRL0_RG_MIDPI_CKDIV4_EN_B0_OP_LP_SEL        Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_B0_RXDVS0                                   (DDRPHY_AO_BASE_ADDRESS + 0x0164)
+    #define B0_RXDVS0_R_RX_RANKINSEL_B0                        Fld(1, 0) //[0:0]
+    #define B0_RXDVS0_B0_RXDVS0_RFU                            Fld(3, 1) //[3:1]
+    #define B0_RXDVS0_R_RX_RANKINCTL_B0                        Fld(4, 4) //[7:4]
+    #define B0_RXDVS0_R_DVS_SW_UP_B0                           Fld(1, 8) //[8:8]
+    #define B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0                Fld(1, 9) //[9:9]
+    #define B0_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_B0              Fld(1, 10) //[10:10]
+    #define B0_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_B0               Fld(1, 11) //[11:11]
+    #define B0_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_B0               Fld(2, 12) //[13:12]
+    #define B0_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_B0              Fld(3, 16) //[18:16]
+    #define B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0                  Fld(1, 19) //[19:19]
+    #define B0_RXDVS0_R_RX_DLY_RK_OPT_B0                       Fld(2, 20) //[21:20]
+    #define B0_RXDVS0_R_HWRESTORE_ENA_B0                       Fld(1, 22) //[22:22]
+    #define B0_RXDVS0_R_HWSAVE_MODE_ENA_B0                     Fld(1, 24) //[24:24]
+    #define B0_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_B0            Fld(1, 26) //[26:26]
+    #define B0_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_B0        Fld(1, 27) //[27:27]
+    #define B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0                  Fld(1, 28) //[28:28]
+    #define B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0               Fld(1, 29) //[29:29]
+    #define B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0                    Fld(1, 30) //[30:30]
+    #define B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0                    Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_B0_RXDVS1                                   (DDRPHY_AO_BASE_ADDRESS + 0x0168)
+    #define B0_RXDVS1_B0_RXDVS1_RFU                            Fld(15, 0) //[14:0]
+    #define B0_RXDVS1_F_LEADLAG_TRACK_B0                       Fld(1, 15) //[15:15]
+    #define B0_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_B0                 Fld(1, 16) //[16:16]
+    #define B0_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B0                Fld(1, 17) //[17:17]
+
+#define DDRPHY_REG_B0_DLL_ARPI0                                (DDRPHY_AO_BASE_ADDRESS + 0x016C)
+    #define B0_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B0                Fld(1, 1) //[1:1]
+    #define B0_DLL_ARPI0_RG_ARPI_RESETB_B0                     Fld(1, 3) //[3:3]
+    #define B0_DLL_ARPI0_RG_ARPI_LS_EN_B0                      Fld(1, 4) //[4:4]
+    #define B0_DLL_ARPI0_RG_ARPI_LS_SEL_B0                     Fld(1, 5) //[5:5]
+    #define B0_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B0                  Fld(1, 6) //[6:6]
+
+#define DDRPHY_REG_B0_DLL_ARPI1                                (DDRPHY_AO_BASE_ADDRESS + 0x0170)
+    #define B0_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B0             Fld(1, 11) //[11:11]
+    #define B0_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B0                 Fld(1, 13) //[13:13]
+    #define B0_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B0                Fld(1, 14) //[14:14]
+    #define B0_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B0                Fld(1, 15) //[15:15]
+    #define B0_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B0                 Fld(1, 17) //[17:17]
+    #define B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0               Fld(1, 19) //[19:19]
+    #define B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT          Fld(1, 20) //[20:20]
+    #define B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0                  Fld(1, 21) //[21:21]
+    #define B0_DLL_ARPI1_RG_ARPI_SET_UPDN_B0                   Fld(3, 28) //[30:28]
+
+#define DDRPHY_REG_B0_DLL_ARPI4                                (DDRPHY_AO_BASE_ADDRESS + 0x0174)
+    #define B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B0               Fld(1, 8) //[8:8]
+    #define B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B0              Fld(1, 9) //[9:9]
+    #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQSIEN_B0              Fld(1, 11) //[11:11]
+    #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQ_B0                  Fld(1, 13) //[13:13]
+    #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQM_B0                 Fld(1, 14) //[14:14]
+    #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQS_B0                 Fld(1, 15) //[15:15]
+    #define B0_DLL_ARPI4_RG_ARPI_BYPASS_FB_B0                  Fld(1, 17) //[17:17]
+    #define B0_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_B0                Fld(1, 19) //[19:19]
+
+#define DDRPHY_REG_B0_DLL_ARPI5                                (DDRPHY_AO_BASE_ADDRESS + 0x0178)
+    #define B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0                   Fld(4, 4) //[7:4]
+    #define B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0                   Fld(1, 8) //[8:8]
+    #define B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0           Fld(1, 25) //[25:25]
+    #define B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0               Fld(1, 26) //[26:26]
+    #define B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0                   Fld(1, 28) //[28:28]
+    #define B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0                   Fld(3, 29) //[31:29]
+
+#define DDRPHY_REG_B0_DQ2                                      (DDRPHY_AO_BASE_ADDRESS + 0x017C)
+    #define B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0                   Fld(1, 0) //[0:0]
+    #define B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0                      Fld(1, 1) //[1:1]
+    #define B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0                   Fld(1, 2) //[2:2]
+    #define B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0                    Fld(1, 3) //[3:3]
+    #define B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0                   Fld(1, 8) //[8:8]
+    #define B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0                    Fld(1, 9) //[9:9]
+    #define B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0                  Fld(1, 10) //[10:10]
+    #define B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0                   Fld(1, 11) //[11:11]
+    #define B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B0                   Fld(1, 12) //[12:12]
+    #define B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0                      Fld(1, 13) //[13:13]
+    #define B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0                   Fld(1, 14) //[14:14]
+    #define B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0                    Fld(1, 15) //[15:15]
+    #define B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0                     Fld(1, 20) //[20:20]
+    #define B0_DQ2_RG_TX_ARDQ_OE_DIS_B0                        Fld(1, 21) //[21:21]
+    #define B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0                    Fld(1, 22) //[22:22]
+    #define B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0                     Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_B0_DQ3                                      (DDRPHY_AO_BASE_ADDRESS + 0x0180)
+    #define B0_DQ3_RG_ARDQ_ATPG_EN_B0                          Fld(1, 0) //[0:0]
+    #define B0_DQ3_RG_RX_ARDQ_SMT_EN_B0                        Fld(1, 1) //[1:1]
+    #define B0_DQ3_RG_TX_ARDQ_EN_B0                            Fld(1, 2) //[2:2]
+    #define B0_DQ3_RG_ARDQ_RESETB_B0                           Fld(1, 3) //[3:3]
+    #define B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0                  Fld(1, 5) //[5:5]
+    #define B0_DQ3_RG_RX_ARDQM0_IN_BUFF_EN_B0                  Fld(1, 6) //[6:6]
+    #define B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0                    Fld(1, 7) //[7:7]
+    #define B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0                   Fld(1, 10) //[10:10]
+    #define B0_DQ3_RG_RX_ARDQ_OFFC_EN_B0                       Fld(1, 11) //[11:11]
+    #define B0_DQ3_RG_RX_ARDQS0_SWAP_EN_B0                     Fld(1, 15) //[15:15]
+    #define B0_DQ3_RG_ARPI_ASYNC_EN_B0                         Fld(1, 23) //[23:23]
+    #define B0_DQ3_RG_ARPI_LAT_EN_B0                           Fld(1, 24) //[24:24]
+    #define B0_DQ3_RG_ARPI_MCK_FB_SEL_B0                       Fld(2, 26) //[27:26]
+
+#define DDRPHY_REG_B0_DQ4                                      (DDRPHY_AO_BASE_ADDRESS + 0x0184)
+    #define B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0                    Fld(7, 0) //[6:0]
+    #define B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0                    Fld(7, 8) //[14:8]
+    #define B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0                     Fld(6, 16) //[21:16]
+    #define B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0                     Fld(6, 24) //[29:24]
+
+#define DDRPHY_REG_B0_DQ5                                      (DDRPHY_AO_BASE_ADDRESS + 0x0188)
+    #define B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0                  Fld(6, 8) //[13:8]
+    #define B0_DQ5_RG_RX_ARDQ_VREF_EN_B0                       Fld(1, 16) //[16:16]
+    #define B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0                   Fld(1, 17) //[17:17]
+    #define B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0                       Fld(4, 20) //[23:20]
+    #define B0_DQ5_RG_RX_ARDQ_EYE_EN_B0                        Fld(1, 24) //[24:24]
+    #define B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0              Fld(1, 25) //[25:25]
+    #define B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0                      Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_B0_DQ6                                      (DDRPHY_AO_BASE_ADDRESS + 0x018C)
+    #define B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0                       Fld(2, 0) //[1:0]
+    #define B0_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B0                    Fld(1, 2) //[2:2]
+    #define B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0                 Fld(1, 3) //[3:3]
+    #define B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0                   Fld(1, 5) //[5:5]
+    #define B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0                   Fld(1, 6) //[6:6]
+    #define B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0                 Fld(1, 7) //[7:7]
+    #define B0_DQ6_RG_RX_ARDQ_LPBK_EN_B0                       Fld(1, 8) //[8:8]
+    #define B0_DQ6_RG_RX_ARDQ_O1_SEL_B0                        Fld(1, 9) //[9:9]
+    #define B0_DQ6_RG_RX_ARDQ_JM_SEL_B0                        Fld(1, 11) //[11:11]
+    #define B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0                       Fld(1, 12) //[12:12]
+    #define B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0                 Fld(2, 14) //[15:14]
+    #define B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0                      Fld(1, 16) //[16:16]
+    #define B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0                      Fld(1, 17) //[17:17]
+    #define B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0                      Fld(1, 18) //[18:18]
+    #define B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0                      Fld(1, 19) //[19:19]
+    #define B0_DQ6_RG_TX_ARDQ_LP5_SEL_B0                       Fld(1, 20) //[20:20]
+    #define B0_DQ6_RG_TX_ARDQ_LP4_SEL_B0                       Fld(1, 21) //[21:21]
+    #define B0_DQ6_RG_TX_ARDQ_CAP_EN_B0                        Fld(1, 24) //[24:24]
+    #define B0_DQ6_RG_TX_ARDQ_DATA_SWAP_EN_B0                  Fld(1, 25) //[25:25]
+    #define B0_DQ6_RG_TX_ARDQ_DATA_SWAP_B0                     Fld(2, 26) //[27:26]
+    #define B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0            Fld(1, 28) //[28:28]
+    #define B0_DQ6_RG_RX_ARDQ_EYE_OE_GATE_EN_B0                Fld(1, 29) //[29:29]
+    #define B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0                 Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_B0_DQ7                                      (DDRPHY_AO_BASE_ADDRESS + 0x0190)
+    #define B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0                    Fld(1, 0) //[0:0]
+    #define B0_DQ7_RG_TX_ARDQS0B_PULL_UP_B0                    Fld(1, 1) //[1:1]
+    #define B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0                     Fld(1, 2) //[2:2]
+    #define B0_DQ7_RG_TX_ARDQS0_PULL_UP_B0                     Fld(1, 3) //[3:3]
+    #define B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0                     Fld(1, 4) //[4:4]
+    #define B0_DQ7_RG_TX_ARDQM0_PULL_UP_B0                     Fld(1, 5) //[5:5]
+    #define B0_DQ7_RG_TX_ARDQ_PULL_DN_B0                       Fld(1, 6) //[6:6]
+    #define B0_DQ7_RG_TX_ARDQ_PULL_UP_B0                       Fld(1, 7) //[7:7]
+    #define B0_DQ7_RG_TX_ARWCKB_PULL_DN_B0                     Fld(1, 8) //[8:8]
+    #define B0_DQ7_RG_TX_ARWCKB_PULL_UP_B0                     Fld(1, 9) //[9:9]
+    #define B0_DQ7_RG_TX_ARWCK_PULL_DN_B0                      Fld(1, 10) //[10:10]
+    #define B0_DQ7_RG_TX_ARWCK_PULL_UP_B0                      Fld(1, 11) //[11:11]
+    #define B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y               Fld(1, 16) //[16:16]
+
+#define DDRPHY_REG_B0_DQ8                                      (DDRPHY_AO_BASE_ADDRESS + 0x0194)
+    #define B0_DQ8_RG_TX_ARDQ_EN_LP4P_B0                       Fld(1, 0) //[0:0]
+    #define B0_DQ8_RG_TX_ARDQ_EN_CAP_LP4P_B0                   Fld(1, 1) //[1:1]
+    #define B0_DQ8_RG_TX_ARDQ_CAP_DET_B0                       Fld(1, 2) //[2:2]
+    #define B0_DQ8_RG_TX_ARDQ_CKE_MCK4X_SEL_B0                 Fld(2, 3) //[4:3]
+    #define B0_DQ8_RG_RX_ARDQS_BURST_E1_EN_B0                  Fld(1, 8) //[8:8]
+    #define B0_DQ8_RG_RX_ARDQS_BURST_E2_EN_B0                  Fld(1, 9) //[9:9]
+    #define B0_DQ8_RG_RX_ARDQS_GATE_EN_MODE_B0                 Fld(1, 12) //[12:12]
+    #define B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0                 Fld(1, 13) //[13:13]
+    #define B0_DQ8_RG_ARDLL_RESETB_B0                          Fld(1, 15) //[15:15]
+
+#define DDRPHY_REG_B0_DQ9                                      (DDRPHY_AO_BASE_ADDRESS + 0x0198)
+    #define B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0                  Fld(1, 0) //[0:0]
+    #define B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0                Fld(1, 4) //[4:4]
+    #define B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0                  Fld(1, 5) //[5:5]
+    #define B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0                 Fld(1, 6) //[6:6]
+    #define B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0                   Fld(1, 7) //[7:7]
+    #define B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0                     Fld(8, 8) //[15:8]
+    #define B0_DQ9_R_DMDQSIEN_VALID_LAT_B0                     Fld(3, 16) //[18:16]
+    #define B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0                     Fld(3, 20) //[22:20]
+    #define B0_DQ9_R_DMRXDVS_VALID_LAT_B0                      Fld(3, 24) //[26:24]
+    #define B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0                      Fld(3, 28) //[30:28]
+
+#define DDRPHY_REG_B0_DQ10                                     (DDRPHY_AO_BASE_ADDRESS + 0x019C)
+    #define B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0                     Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_B0_DQ11                                     (DDRPHY_AO_BASE_ADDRESS + 0x01A0)
+    #define B0_DQ11_DMY_DQ11_B0                                Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_B0_PHY2                                     (DDRPHY_AO_BASE_ADDRESS + 0x01A4)
+    #define B0_PHY2_RG_RX_ARDQS_SE_SWAP_EN_B0                  Fld(1, 0) //[0:0]
+    #define B0_PHY2_RG_RX_ARDQS_JM_SEL_B0                      Fld(4, 4) //[7:4]
+    #define B0_PHY2_RG_RX_ARDQS_JM_EN_B0                       Fld(1, 8) //[8:8]
+    #define B0_PHY2_RG_RX_ARDQS_JM_DLY_B0                      Fld(9, 16) //[24:16]
+    #define B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0       Fld(1, 28) //[28:28]
+    #define B0_PHY2_RG_RX_ARDQS_DQSIEN_TIE_GATE_EN_B0          Fld(1, 29) //[29:29]
+    #define B0_PHY2_RG_RX_ARDQSB_SE_SWAP_EN_B0                 Fld(1, 30) //[30:30]
+
+#define DDRPHY_REG_B0_PHY3                                     (DDRPHY_AO_BASE_ADDRESS + 0x01A8)
+    #define B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_VREF_SEL_B0           Fld(7, 8) //[14:8]
+    #define B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B0            Fld(4, 16) //[19:16]
+    #define B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_EN_B0                 Fld(1, 20) //[20:20]
+    #define B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_CLK_SEL_B0            Fld(2, 24) //[25:24]
+    #define B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_CLK_RC_SEL_B0         Fld(2, 26) //[27:26]
+    #define B0_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B0                  Fld(1, 28) //[28:28]
+
+#define DDRPHY_REG_B0_TX_MCK                                   (DDRPHY_AO_BASE_ADDRESS + 0x01AC)
+    #define B0_TX_MCK_DMY_TX_MCK_B0                            Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_B0_PHY4                                     (DDRPHY_AO_BASE_ADDRESS + 0x01B0)
+    #define B0_PHY4_RG_ARPI_SUM_MON_SEL_B0                     Fld(3, 0) //[2:0]
+    #define B0_PHY4_RG_RX_ARDQ_INB_BIAS_SEL_B0                 Fld(1, 4) //[4:4]
+
+#define DDRPHY_REG_RK_B1_RXDVS0                                (DDRPHY_AO_BASE_ADDRESS + 0x01E0)
+    #define RK_B1_RXDVS0_R_RK0_B1_DVS_LEAD_LAG_CNT_CLR         Fld(1, 26) //[26:26]
+    #define RK_B1_RXDVS0_R_RK0_B1_DVS_SW_CNT_CLR               Fld(1, 27) //[27:27]
+    #define RK_B1_RXDVS0_R_RK0_B1_DVS_SW_CNT_ENA               Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_RK_B1_RXDVS1                                (DDRPHY_AO_BASE_ADDRESS + 0x01E4)
+    #define RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG                   Fld(16, 0) //[15:0]
+    #define RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD                  Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_RK_B1_RXDVS2                                (DDRPHY_AO_BASE_ADDRESS + 0x01E8)
+    #define RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1         Fld(2, 16) //[17:16]
+    #define RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1          Fld(2, 18) //[19:18]
+    #define RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1    Fld(1, 23) //[23:23]
+    #define RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1         Fld(2, 24) //[25:24]
+    #define RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1          Fld(2, 26) //[27:26]
+    #define RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1    Fld(1, 28) //[28:28]
+    #define RK_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1                Fld(1, 29) //[29:29]
+    #define RK_B1_RXDVS2_R_RK0_DVS_MODE_B1                     Fld(2, 30) //[31:30]
+
+#define DDRPHY_REG_RK_B1_RXDVS3                                (DDRPHY_AO_BASE_ADDRESS + 0x01EC)
+    #define RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1                Fld(8, 0) //[7:0]
+    #define RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1                Fld(8, 8) //[15:8]
+
+#define DDRPHY_REG_RK_B1_RXDVS4                                (DDRPHY_AO_BASE_ADDRESS + 0x01F0)
+    #define RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1              Fld(9, 0) //[8:0]
+    #define RK_B1_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B1              Fld(9, 16) //[24:16]
+
+#define DDRPHY_REG_B1_LP_CTRL0                                 (DDRPHY_AO_BASE_ADDRESS + 0x02E0)
+    #define B1_LP_CTRL0_RG_ARDMSUS_10_B1                       Fld(1, 0) //[0:0]
+    #define B1_LP_CTRL0_RESERVED_B1_LP_CTRL0_3_1               Fld(3, 1) //[3:1]
+    #define B1_LP_CTRL0_RG_ARDMSUS_10_B1_LP_SEL                Fld(1, 4) //[4:4]
+    #define B1_LP_CTRL0_RG_DA_PICG_B1_CTRL_LOW_BY_LPC          Fld(1, 5) //[5:5]
+    #define B1_LP_CTRL0_RESERVED_B1_LP_CTRL0_6_6               Fld(1, 6) //[6:6]
+    #define B1_LP_CTRL0_RG_TX_ARDQ_RESETB_B1_LP_SEL            Fld(1, 7) //[7:7]
+    #define B1_LP_CTRL0_RG_ARDQ_RESETB_B1_LP_SEL               Fld(1, 8) //[8:8]
+    #define B1_LP_CTRL0_RG_ARPI_RESETB_B1_LP_SEL               Fld(1, 9) //[9:9]
+    #define B1_LP_CTRL0_RESERVED_B1_LP_CTRL0_11_10             Fld(2, 10) //[11:10]
+    #define B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL                    Fld(1, 12) //[12:12]
+    #define B1_LP_CTRL0_RG_ARDLL_PHDET_EN_B1_LP_SEL            Fld(1, 13) //[13:13]
+    #define B1_LP_CTRL0_RG_B1_DLL_EN_OP_SEQ_LP_SEL             Fld(1, 14) //[14:14]
+    #define B1_LP_CTRL0_RESERVED_B1_LP_CTRL0_15                Fld(1, 15) //[15:15]
+    #define B1_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B1_LP_SEL           Fld(1, 16) //[16:16]
+    #define B1_LP_CTRL0_DA_ARPI_CG_MCK_B1_LP_SEL               Fld(1, 17) //[17:17]
+    #define B1_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B1_LP_SEL        Fld(1, 18) //[18:18]
+    #define B1_LP_CTRL0_DA_ARPI_CG_MCTL_B1_LP_SEL              Fld(1, 19) //[19:19]
+    #define B1_LP_CTRL0_DA_ARPI_CG_FB_B1_LP_SEL                Fld(1, 20) //[20:20]
+    #define B1_LP_CTRL0_DA_ARPI_CG_DQ_B1_LP_SEL                Fld(1, 21) //[21:21]
+    #define B1_LP_CTRL0_DA_ARPI_CG_DQM_B1_LP_SEL               Fld(1, 22) //[22:22]
+    #define B1_LP_CTRL0_DA_ARPI_CG_DQS_B1_LP_SEL               Fld(1, 23) //[23:23]
+    #define B1_LP_CTRL0_DA_ARPI_CG_DQSIEN_B1_LP_SEL            Fld(1, 24) //[24:24]
+    #define B1_LP_CTRL0_DA_ARPI_MPDIV_CG_B1_LP_SEL             Fld(1, 25) //[25:25]
+    #define B1_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B1_LP_SEL           Fld(1, 26) //[26:26]
+    #define B1_LP_CTRL0_DA_ARPI_MIDPI_EN_B1_LP_SEL             Fld(1, 27) //[27:27]
+    #define B1_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B1_LP_SEL      Fld(1, 28) //[28:28]
+    #define B1_LP_CTRL0_RG_ARPI_DDR400_EN_B1_LP_SEL            Fld(1, 29) //[29:29]
+    #define B1_LP_CTRL0_RG_MIDPI_EN_B1_OP_LP_SEL               Fld(1, 30) //[30:30]
+    #define B1_LP_CTRL0_RG_MIDPI_CKDIV4_EN_B1_OP_LP_SEL        Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_B1_RXDVS0                                   (DDRPHY_AO_BASE_ADDRESS + 0x02E4)
+    #define B1_RXDVS0_R_RX_RANKINSEL_B1                        Fld(1, 0) //[0:0]
+    #define B1_RXDVS0_B1_RXDVS0_RFU                            Fld(3, 1) //[3:1]
+    #define B1_RXDVS0_R_RX_RANKINCTL_B1                        Fld(4, 4) //[7:4]
+    #define B1_RXDVS0_R_DVS_SW_UP_B1                           Fld(1, 8) //[8:8]
+    #define B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1                Fld(1, 9) //[9:9]
+    #define B1_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_B1              Fld(1, 10) //[10:10]
+    #define B1_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_B1               Fld(1, 11) //[11:11]
+    #define B1_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_B1               Fld(2, 12) //[13:12]
+    #define B1_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_B1              Fld(3, 16) //[18:16]
+    #define B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1                  Fld(1, 19) //[19:19]
+    #define B1_RXDVS0_R_RX_DLY_RK_OPT_B1                       Fld(2, 20) //[21:20]
+    #define B1_RXDVS0_R_HWRESTORE_ENA_B1                       Fld(1, 22) //[22:22]
+    #define B1_RXDVS0_R_HWSAVE_MODE_ENA_B1                     Fld(1, 24) //[24:24]
+    #define B1_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_B1            Fld(1, 26) //[26:26]
+    #define B1_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_B1        Fld(1, 27) //[27:27]
+    #define B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1                  Fld(1, 28) //[28:28]
+    #define B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1               Fld(1, 29) //[29:29]
+    #define B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1                    Fld(1, 30) //[30:30]
+    #define B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1                    Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_B1_RXDVS1                                   (DDRPHY_AO_BASE_ADDRESS + 0x02E8)
+    #define B1_RXDVS1_B1_RXDVS1_RFU                            Fld(15, 0) //[14:0]
+    #define B1_RXDVS1_F_LEADLAG_TRACK_B1                       Fld(1, 15) //[15:15]
+    #define B1_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_B1                 Fld(1, 16) //[16:16]
+    #define B1_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B1                Fld(1, 17) //[17:17]
+
+#define DDRPHY_REG_B1_DLL_ARPI0                                (DDRPHY_AO_BASE_ADDRESS + 0x02EC)
+    #define B1_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B1                Fld(1, 1) //[1:1]
+    #define B1_DLL_ARPI0_RG_ARPI_RESETB_B1                     Fld(1, 3) //[3:3]
+    #define B1_DLL_ARPI0_RG_ARPI_LS_EN_B1                      Fld(1, 4) //[4:4]
+    #define B1_DLL_ARPI0_RG_ARPI_LS_SEL_B1                     Fld(1, 5) //[5:5]
+    #define B1_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B1                  Fld(1, 6) //[6:6]
+
+#define DDRPHY_REG_B1_DLL_ARPI1                                (DDRPHY_AO_BASE_ADDRESS + 0x02F0)
+    #define B1_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B1             Fld(1, 11) //[11:11]
+    #define B1_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B1                 Fld(1, 13) //[13:13]
+    #define B1_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B1                Fld(1, 14) //[14:14]
+    #define B1_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B1                Fld(1, 15) //[15:15]
+    #define B1_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B1                 Fld(1, 17) //[17:17]
+    #define B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1               Fld(1, 19) //[19:19]
+    #define B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT          Fld(1, 20) //[20:20]
+    #define B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1                  Fld(1, 21) //[21:21]
+    #define B1_DLL_ARPI1_RG_ARPI_SET_UPDN_B1                   Fld(3, 28) //[30:28]
+
+#define DDRPHY_REG_B1_DLL_ARPI4                                (DDRPHY_AO_BASE_ADDRESS + 0x02F4)
+    #define B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B1               Fld(1, 8) //[8:8]
+    #define B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B1              Fld(1, 9) //[9:9]
+    #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQSIEN_B1              Fld(1, 11) //[11:11]
+    #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQ_B1                  Fld(1, 13) //[13:13]
+    #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQM_B1                 Fld(1, 14) //[14:14]
+    #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQS_B1                 Fld(1, 15) //[15:15]
+    #define B1_DLL_ARPI4_RG_ARPI_BYPASS_FB_B1                  Fld(1, 17) //[17:17]
+    #define B1_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_B1                Fld(1, 19) //[19:19]
+
+#define DDRPHY_REG_B1_DLL_ARPI5                                (DDRPHY_AO_BASE_ADDRESS + 0x02F8)
+    #define B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1                   Fld(4, 4) //[7:4]
+    #define B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1                   Fld(1, 8) //[8:8]
+    #define B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1           Fld(1, 25) //[25:25]
+    #define B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1               Fld(1, 26) //[26:26]
+    #define B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1                   Fld(1, 28) //[28:28]
+    #define B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1                   Fld(3, 29) //[31:29]
+
+#define DDRPHY_REG_B1_DQ2                                      (DDRPHY_AO_BASE_ADDRESS + 0x02FC)
+    #define B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1                   Fld(1, 0) //[0:0]
+    #define B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1                      Fld(1, 1) //[1:1]
+    #define B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1                   Fld(1, 2) //[2:2]
+    #define B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1                    Fld(1, 3) //[3:3]
+    #define B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1                   Fld(1, 8) //[8:8]
+    #define B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1                    Fld(1, 9) //[9:9]
+    #define B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1                  Fld(1, 10) //[10:10]
+    #define B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1                   Fld(1, 11) //[11:11]
+    #define B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1                   Fld(1, 12) //[12:12]
+    #define B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1                      Fld(1, 13) //[13:13]
+    #define B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1                   Fld(1, 14) //[14:14]
+    #define B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1                    Fld(1, 15) //[15:15]
+    #define B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1                     Fld(1, 20) //[20:20]
+    #define B1_DQ2_RG_TX_ARDQ_OE_DIS_B1                        Fld(1, 21) //[21:21]
+    #define B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1                    Fld(1, 22) //[22:22]
+    #define B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1                     Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_B1_DQ3                                      (DDRPHY_AO_BASE_ADDRESS + 0x0300)
+    #define B1_DQ3_RG_ARDQ_ATPG_EN_B1                          Fld(1, 0) //[0:0]
+    #define B1_DQ3_RG_RX_ARDQ_SMT_EN_B1                        Fld(1, 1) //[1:1]
+    #define B1_DQ3_RG_TX_ARDQ_EN_B1                            Fld(1, 2) //[2:2]
+    #define B1_DQ3_RG_ARDQ_RESETB_B1                           Fld(1, 3) //[3:3]
+    #define B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1                  Fld(1, 5) //[5:5]
+    #define B1_DQ3_RG_RX_ARDQM0_IN_BUFF_EN_B1                  Fld(1, 6) //[6:6]
+    #define B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1                    Fld(1, 7) //[7:7]
+    #define B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1                   Fld(1, 10) //[10:10]
+    #define B1_DQ3_RG_RX_ARDQ_OFFC_EN_B1                       Fld(1, 11) //[11:11]
+    #define B1_DQ3_RG_RX_ARDQS0_SWAP_EN_B1                     Fld(1, 15) //[15:15]
+    #define B1_DQ3_RG_ARPI_ASYNC_EN_B1                         Fld(1, 23) //[23:23]
+    #define B1_DQ3_RG_ARPI_LAT_EN_B1                           Fld(1, 24) //[24:24]
+    #define B1_DQ3_RG_ARPI_MCK_FB_SEL_B1                       Fld(2, 26) //[27:26]
+
+#define DDRPHY_REG_B1_DQ4                                      (DDRPHY_AO_BASE_ADDRESS + 0x0304)
+    #define B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1                    Fld(7, 0) //[6:0]
+    #define B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1                    Fld(7, 8) //[14:8]
+    #define B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1                     Fld(6, 16) //[21:16]
+    #define B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1                     Fld(6, 24) //[29:24]
+
+#define DDRPHY_REG_B1_DQ5                                      (DDRPHY_AO_BASE_ADDRESS + 0x0308)
+    #define B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1                  Fld(6, 8) //[13:8]
+    #define B1_DQ5_RG_RX_ARDQ_VREF_EN_B1                       Fld(1, 16) //[16:16]
+    #define B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1                   Fld(1, 17) //[17:17]
+    #define B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1                       Fld(4, 20) //[23:20]
+    #define B1_DQ5_RG_RX_ARDQ_EYE_EN_B1                        Fld(1, 24) //[24:24]
+    #define B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1              Fld(1, 25) //[25:25]
+    #define B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1                      Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_B1_DQ6                                      (DDRPHY_AO_BASE_ADDRESS + 0x030C)
+    #define B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1                       Fld(2, 0) //[1:0]
+    #define B1_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B1                    Fld(1, 2) //[2:2]
+    #define B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1                 Fld(1, 3) //[3:3]
+    #define B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1                   Fld(1, 5) //[5:5]
+    #define B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1                   Fld(1, 6) //[6:6]
+    #define B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1                 Fld(1, 7) //[7:7]
+    #define B1_DQ6_RG_RX_ARDQ_LPBK_EN_B1                       Fld(1, 8) //[8:8]
+    #define B1_DQ6_RG_RX_ARDQ_O1_SEL_B1                        Fld(1, 9) //[9:9]
+    #define B1_DQ6_RG_RX_ARDQ_JM_SEL_B1                        Fld(1, 11) //[11:11]
+    #define B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1                       Fld(1, 12) //[12:12]
+    #define B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1                 Fld(2, 14) //[15:14]
+    #define B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1                      Fld(1, 16) //[16:16]
+    #define B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1                      Fld(1, 17) //[17:17]
+    #define B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1                      Fld(1, 18) //[18:18]
+    #define B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1                      Fld(1, 19) //[19:19]
+    #define B1_DQ6_RG_TX_ARDQ_LP5_SEL_B1                       Fld(1, 20) //[20:20]
+    #define B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1                       Fld(1, 21) //[21:21]
+    #define B1_DQ6_RG_TX_ARDQ_CAP_EN_B1                        Fld(1, 24) //[24:24]
+    #define B1_DQ6_RG_TX_ARDQ_DATA_SWAP_EN_B1                  Fld(1, 25) //[25:25]
+    #define B1_DQ6_RG_TX_ARDQ_DATA_SWAP_B1                     Fld(2, 26) //[27:26]
+    #define B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1            Fld(1, 28) //[28:28]
+    #define B1_DQ6_RG_RX_ARDQ_EYE_OE_GATE_EN_B1                Fld(1, 29) //[29:29]
+    #define B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1                 Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_B1_DQ7                                      (DDRPHY_AO_BASE_ADDRESS + 0x0310)
+    #define B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1                    Fld(1, 0) //[0:0]
+    #define B1_DQ7_RG_TX_ARDQS0B_PULL_UP_B1                    Fld(1, 1) //[1:1]
+    #define B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1                     Fld(1, 2) //[2:2]
+    #define B1_DQ7_RG_TX_ARDQS0_PULL_UP_B1                     Fld(1, 3) //[3:3]
+    #define B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1                     Fld(1, 4) //[4:4]
+    #define B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1                     Fld(1, 5) //[5:5]
+    #define B1_DQ7_RG_TX_ARDQ_PULL_DN_B1                       Fld(1, 6) //[6:6]
+    #define B1_DQ7_RG_TX_ARDQ_PULL_UP_B1                       Fld(1, 7) //[7:7]
+    #define B1_DQ7_RG_TX_ARWCKB_PULL_DN_B1                     Fld(1, 8) //[8:8]
+    #define B1_DQ7_RG_TX_ARWCKB_PULL_UP_B1                     Fld(1, 9) //[9:9]
+    #define B1_DQ7_RG_TX_ARWCK_PULL_DN_B1                      Fld(1, 10) //[10:10]
+    #define B1_DQ7_RG_TX_ARWCK_PULL_UP_B1                      Fld(1, 11) //[11:11]
+    #define B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y               Fld(1, 16) //[16:16]
+
+#define DDRPHY_REG_B1_DQ8                                      (DDRPHY_AO_BASE_ADDRESS + 0x0314)
+    #define B1_DQ8_RG_TX_ARDQ_EN_LP4P_B1                       Fld(1, 0) //[0:0]
+    #define B1_DQ8_RG_TX_ARDQ_EN_CAP_LP4P_B1                   Fld(1, 1) //[1:1]
+    #define B1_DQ8_RG_TX_ARDQ_CAP_DET_B1                       Fld(1, 2) //[2:2]
+    #define B1_DQ8_RG_TX_ARDQ_CKE_MCK4X_SEL_B1                 Fld(2, 3) //[4:3]
+    #define B1_DQ8_RG_RX_ARDQS_BURST_E1_EN_B1                  Fld(1, 8) //[8:8]
+    #define B1_DQ8_RG_RX_ARDQS_BURST_E2_EN_B1                  Fld(1, 9) //[9:9]
+    #define B1_DQ8_RG_RX_ARDQS_GATE_EN_MODE_B1                 Fld(1, 12) //[12:12]
+    #define B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1                 Fld(1, 13) //[13:13]
+    #define B1_DQ8_RG_ARDLL_RESETB_B1                          Fld(1, 15) //[15:15]
+
+#define DDRPHY_REG_B1_DQ9                                      (DDRPHY_AO_BASE_ADDRESS + 0x0318)
+    #define B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1                  Fld(1, 0) //[0:0]
+    #define B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1                Fld(1, 4) //[4:4]
+    #define B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1                  Fld(1, 5) //[5:5]
+    #define B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1                 Fld(1, 6) //[6:6]
+    #define B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1                   Fld(1, 7) //[7:7]
+    #define B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1                     Fld(8, 8) //[15:8]
+    #define B1_DQ9_R_DMDQSIEN_VALID_LAT_B1                     Fld(3, 16) //[18:16]
+    #define B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1                     Fld(3, 20) //[22:20]
+    #define B1_DQ9_R_DMRXDVS_VALID_LAT_B1                      Fld(3, 24) //[26:24]
+    #define B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1                      Fld(3, 28) //[30:28]
+
+#define DDRPHY_REG_B1_DQ10                                     (DDRPHY_AO_BASE_ADDRESS + 0x031C)
+    #define B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1                     Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_B1_DQ11                                     (DDRPHY_AO_BASE_ADDRESS + 0x0320)
+    #define B1_DQ11_DMY_DQ11_B1                                Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_B1_PHY2                                     (DDRPHY_AO_BASE_ADDRESS + 0x0324)
+    #define B1_PHY2_RG_RX_ARDQS_SE_SWAP_EN_B1                  Fld(1, 0) //[0:0]
+    #define B1_PHY2_RG_RX_ARDQS_JM_SEL_B1                      Fld(4, 4) //[7:4]
+    #define B1_PHY2_RG_RX_ARDQS_JM_EN_B1                       Fld(1, 8) //[8:8]
+    #define B1_PHY2_RG_RX_ARDQS_JM_DLY_B1                      Fld(9, 16) //[24:16]
+    #define B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1       Fld(1, 28) //[28:28]
+    #define B1_PHY2_RG_RX_ARDQS_DQSIEN_TIE_GATE_EN_B1          Fld(1, 29) //[29:29]
+    #define B1_PHY2_RG_RX_ARDQSB_SE_SWAP_EN_B1                 Fld(1, 30) //[30:30]
+
+#define DDRPHY_REG_B1_PHY3                                     (DDRPHY_AO_BASE_ADDRESS + 0x0328)
+    #define B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_VREF_SEL_B1           Fld(7, 8) //[14:8]
+    #define B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B1            Fld(4, 16) //[19:16]
+    #define B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_EN_B1                 Fld(1, 20) //[20:20]
+    #define B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_CLK_SEL_B1            Fld(2, 24) //[25:24]
+    #define B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_CLK_RC_SEL_B1         Fld(2, 26) //[27:26]
+    #define B1_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B1                  Fld(1, 28) //[28:28]
+
+#define DDRPHY_REG_B1_TX_MCK                                   (DDRPHY_AO_BASE_ADDRESS + 0x032C)
+    #define B1_TX_MCK_DMY_TX_MCK_B1                            Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_B1_PHY4                                     (DDRPHY_AO_BASE_ADDRESS + 0x0330)
+    #define B1_PHY4_RG_ARPI_SUM_MON_SEL_B1                     Fld(3, 0) //[2:0]
+    #define B1_PHY4_RG_RX_ARDQ_INB_BIAS_SEL_B1                 Fld(1, 4) //[4:4]
+
+#define DDRPHY_REG_B1_TX_CKE_CTRL                              (DDRPHY_AO_BASE_ADDRESS + 0x0334)
+    #define B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_EN_B1            Fld(1, 0) //[0:0]
+    #define B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_SEL_B1           Fld(1, 1) //[1:1]
+    #define B1_TX_CKE_CTRL_RG_TX_ARCKE0_PULL_DN_B1             Fld(1, 2) //[2:2]
+    #define B1_TX_CKE_CTRL_RG_TX_ARCKE0_PULL_UP_B1             Fld(1, 3) //[3:3]
+    #define B1_TX_CKE_CTRL_RG_TX_ARCKE1_PULL_DN_B1             Fld(1, 4) //[4:4]
+    #define B1_TX_CKE_CTRL_RG_TX_ARCKE1_PULL_UP_B1             Fld(1, 5) //[5:5]
+    #define B1_TX_CKE_CTRL_RG_TX_ARCS1_OE_TIE_EN_B1            Fld(1, 6) //[6:6]
+
+#define DDRPHY_REG_RK_CA_RXDVS0                                (DDRPHY_AO_BASE_ADDRESS + 0x0360)
+    #define RK_CA_RXDVS0_R_RK0_CA_DVS_LEAD_LAG_CNT_CLR         Fld(1, 26) //[26:26]
+    #define RK_CA_RXDVS0_R_RK0_CA_DVS_SW_CNT_CLR               Fld(1, 27) //[27:27]
+    #define RK_CA_RXDVS0_R_RK0_CA_DVS_SW_CNT_ENA               Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_RK_CA_RXDVS1                                (DDRPHY_AO_BASE_ADDRESS + 0x0364)
+    #define RK_CA_RXDVS1_R_RK0_CA_DVS_TH_LAG                   Fld(16, 0) //[15:0]
+    #define RK_CA_RXDVS1_R_RK0_CA_DVS_TH_LEAD                  Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_RK_CA_RXDVS2                                (DDRPHY_AO_BASE_ADDRESS + 0x0368)
+    #define RK_CA_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_CA         Fld(2, 16) //[17:16]
+    #define RK_CA_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_CA          Fld(2, 18) //[19:18]
+    #define RK_CA_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_CA    Fld(1, 23) //[23:23]
+    #define RK_CA_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_CA         Fld(2, 24) //[25:24]
+    #define RK_CA_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_CA          Fld(2, 26) //[27:26]
+    #define RK_CA_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_CA    Fld(1, 28) //[28:28]
+    #define RK_CA_RXDVS2_R_RK0_DVS_FDLY_MODE_CA                Fld(1, 29) //[29:29]
+    #define RK_CA_RXDVS2_R_RK0_DVS_MODE_CA                     Fld(2, 30) //[31:30]
+
+#define DDRPHY_REG_RK_CA_RXDVS3                                (DDRPHY_AO_BASE_ADDRESS + 0x036C)
+    #define RK_CA_RXDVS3_RG_RK0_ARCMD_MIN_DLY                  Fld(6, 0) //[5:0]
+    #define RK_CA_RXDVS3_RG_RK0_ARCMD_MIN_DLY_RFU              Fld(2, 6) //[7:6]
+    #define RK_CA_RXDVS3_RG_RK0_ARCMD_MAX_DLY                  Fld(6, 8) //[13:8]
+    #define RK_CA_RXDVS3_RG_RK0_ARCMD_MAX_DLY_RFU              Fld(2, 14) //[15:14]
+
+#define DDRPHY_REG_RK_CA_RXDVS4                                (DDRPHY_AO_BASE_ADDRESS + 0x0370)
+    #define RK_CA_RXDVS4_RG_RK0_ARCLK_MIN_DLY                  Fld(7, 0) //[6:0]
+    #define RK_CA_RXDVS4_RG_RK0_ARCLK_MIN_DLY_RFU              Fld(1, 7) //[7:7]
+    #define RK_CA_RXDVS4_RG_RK0_ARCLK_MAX_DLY                  Fld(7, 8) //[14:8]
+    #define RK_CA_RXDVS4_RG_RK0_ARCLK_MAX_DLY_RFU              Fld(1, 15) //[15:15]
+
+#define DDRPHY_REG_CA_LP_CTRL0                                 (DDRPHY_AO_BASE_ADDRESS + 0x0460)
+    #define CA_LP_CTRL0_RG_ARDMSUS_10_CA                       Fld(1, 0) //[0:0]
+    #define CA_LP_CTRL0_RG_TX_ARCA_PULL_DN_LP_SEL              Fld(1, 1) //[1:1]
+    #define CA_LP_CTRL0_RG_TX_ARCA_PULL_UP_LP_SEL              Fld(1, 2) //[2:2]
+    #define CA_LP_CTRL0_RG_TX_ARCS_PULL_DN_LP_SEL              Fld(1, 3) //[3:3]
+    #define CA_LP_CTRL0_RG_ARDMSUS_10_CA_LP_SEL                Fld(1, 4) //[4:4]
+    #define CA_LP_CTRL0_RG_DA_PICG_CA_CTRL_LOW_BY_LPC          Fld(1, 5) //[5:5]
+    #define CA_LP_CTRL0_RESERVED_CA_LP_CTRL0_6_6               Fld(1, 6) //[6:6]
+    #define CA_LP_CTRL0_RG_TX_ARCMD_RESETB_LP_SEL              Fld(1, 7) //[7:7]
+    #define CA_LP_CTRL0_RG_ARCMD_RESETB_LP_SEL                 Fld(1, 8) //[8:8]
+    #define CA_LP_CTRL0_RG_ARPI_RESETB_CA_LP_SEL               Fld(1, 9) //[9:9]
+    #define CA_LP_CTRL0_RESERVED_CA_LP_CTRL0_11_10             Fld(2, 10) //[11:10]
+    #define CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL                    Fld(1, 12) //[12:12]
+    #define CA_LP_CTRL0_RG_ARDLL_PHDET_EN_CA_LP_SEL            Fld(1, 13) //[13:13]
+    #define CA_LP_CTRL0_RG_CA_DLL_EN_OP_SEQ_LP_SEL             Fld(1, 14) //[14:14]
+    #define CA_LP_CTRL0_RG_TX_ARCS_PULL_UP_LP_SEL              Fld(1, 15) //[15:15]
+    #define CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL             Fld(1, 16) //[16:16]
+    #define CA_LP_CTRL0_DA_ARPI_CG_MCK_CA_LP_SEL               Fld(1, 17) //[17:17]
+    #define CA_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_CA_LP_SEL        Fld(1, 18) //[18:18]
+    #define CA_LP_CTRL0_DA_ARPI_CG_MCTL_CA_LP_SEL              Fld(1, 19) //[19:19]
+    #define CA_LP_CTRL0_DA_ARPI_CG_FB_CA_LP_SEL                Fld(1, 20) //[20:20]
+    #define CA_LP_CTRL0_DA_ARPI_CG_CS_LP_SEL                   Fld(1, 21) //[21:21]
+    #define CA_LP_CTRL0_DA_ARPI_CG_CLK_LP_SEL                  Fld(1, 22) //[22:22]
+    #define CA_LP_CTRL0_DA_ARPI_CG_CMD_LP_SEL                  Fld(1, 23) //[23:23]
+    #define CA_LP_CTRL0_DA_ARPI_CG_CLKIEN_LP_SEL               Fld(1, 24) //[24:24]
+    #define CA_LP_CTRL0_DA_ARPI_MPDIV_CG_CA_LP_SEL             Fld(1, 25) //[25:25]
+    #define CA_LP_CTRL0_RG_RX_ARCMD_VREF_EN_LP_SEL             Fld(1, 26) //[26:26]
+    #define CA_LP_CTRL0_DA_ARPI_MIDPI_EN_CA_LP_SEL             Fld(1, 27) //[27:27]
+    #define CA_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_CA_LP_SEL      Fld(1, 28) //[28:28]
+    #define CA_LP_CTRL0_RG_ARPI_DDR400_EN_CA_LP_SEL            Fld(1, 29) //[29:29]
+    #define CA_LP_CTRL0_RG_MIDPI_EN_CA_OP_LP_SEL               Fld(1, 30) //[30:30]
+    #define CA_LP_CTRL0_RG_MIDPI_CKDIV4_EN_CA_OP_LP_SEL        Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_CA_RXDVS0                                   (DDRPHY_AO_BASE_ADDRESS + 0x0464)
+    #define CA_RXDVS0_R_RX_RANKINSEL_CA                        Fld(1, 0) //[0:0]
+    #define CA_RXDVS0_CA_RXDVS0_RFU                            Fld(3, 1) //[3:1]
+    #define CA_RXDVS0_R_RX_RANKINCTL_CA                        Fld(4, 4) //[7:4]
+    #define CA_RXDVS0_R_DVS_SW_UP_CA                           Fld(1, 8) //[8:8]
+    #define CA_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_CA                Fld(1, 9) //[9:9]
+    #define CA_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_CA              Fld(1, 10) //[10:10]
+    #define CA_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_CA               Fld(1, 11) //[11:11]
+    #define CA_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_CA               Fld(2, 12) //[13:12]
+    #define CA_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_CA              Fld(3, 16) //[18:16]
+    #define CA_RXDVS0_R_DMRXDVS_CNTCMP_OPT_CA                  Fld(1, 19) //[19:19]
+    #define CA_RXDVS0_R_RX_DLY_RK_OPT_CA                       Fld(2, 20) //[21:20]
+    #define CA_RXDVS0_R_HWRESTORE_ENA_CA                       Fld(1, 22) //[22:22]
+    #define CA_RXDVS0_R_HWSAVE_MODE_ENA_CA                     Fld(1, 24) //[24:24]
+    #define CA_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_CA            Fld(1, 26) //[26:26]
+    #define CA_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_CA        Fld(1, 27) //[27:27]
+    #define CA_RXDVS0_R_RX_DLY_TRACK_CG_EN_CA                  Fld(1, 28) //[28:28]
+    #define CA_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_CA               Fld(1, 29) //[29:29]
+    #define CA_RXDVS0_R_RX_DLY_TRACK_CLR_CA                    Fld(1, 30) //[30:30]
+    #define CA_RXDVS0_R_RX_DLY_TRACK_ENA_CA                    Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_CA_RXDVS1                                   (DDRPHY_AO_BASE_ADDRESS + 0x0468)
+    #define CA_RXDVS1_CA_RXDVS1_RFU                            Fld(16, 0) //[15:0]
+    #define CA_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_CA                 Fld(1, 16) //[16:16]
+    #define CA_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_CA                Fld(1, 17) //[17:17]
+
+#define DDRPHY_REG_CA_DLL_ARPI0                                (DDRPHY_AO_BASE_ADDRESS + 0x046C)
+    #define CA_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_CA                Fld(1, 1) //[1:1]
+    #define CA_DLL_ARPI0_RG_ARPI_RESETB_CA                     Fld(1, 3) //[3:3]
+    #define CA_DLL_ARPI0_RG_ARPI_LS_EN_CA                      Fld(1, 4) //[4:4]
+    #define CA_DLL_ARPI0_RG_ARPI_LS_SEL_CA                     Fld(1, 5) //[5:5]
+    #define CA_DLL_ARPI0_RG_ARPI_MCK8X_SEL_CA                  Fld(1, 6) //[6:6]
+
+#define DDRPHY_REG_CA_DLL_ARPI1                                (DDRPHY_AO_BASE_ADDRESS + 0x0470)
+    #define CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN                Fld(1, 11) //[11:11]
+    #define CA_DLL_ARPI1_RG_ARPI_CMD_JUMP_EN                   Fld(1, 13) //[13:13]
+    #define CA_DLL_ARPI1_RG_ARPI_CLK_JUMP_EN                   Fld(1, 15) //[15:15]
+    #define CA_DLL_ARPI1_RG_ARPI_CS_JUMP_EN                    Fld(1, 16) //[16:16]
+    #define CA_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_CA                 Fld(1, 17) //[17:17]
+    #define CA_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_CA               Fld(1, 19) //[19:19]
+    #define CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT          Fld(1, 20) //[20:20]
+    #define CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA                  Fld(1, 21) //[21:21]
+    #define CA_DLL_ARPI1_RG_ARPI_SET_UPDN_CA                   Fld(3, 28) //[30:28]
+
+#define DDRPHY_REG_CA_DLL_ARPI4                                (DDRPHY_AO_BASE_ADDRESS + 0x0474)
+    #define CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CA_CA               Fld(1, 8) //[8:8]
+    #define CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CLK_CA              Fld(1, 9) //[9:9]
+    #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CLKIEN                 Fld(1, 11) //[11:11]
+    #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CMD                    Fld(1, 13) //[13:13]
+    #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CLK                    Fld(1, 15) //[15:15]
+    #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CS                     Fld(1, 16) //[16:16]
+    #define CA_DLL_ARPI4_RG_ARPI_BYPASS_FB_CA                  Fld(1, 17) //[17:17]
+    #define CA_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_CA                Fld(1, 19) //[19:19]
+
+#define DDRPHY_REG_CA_DLL_ARPI5                                (DDRPHY_AO_BASE_ADDRESS + 0x0478)
+    #define CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA                   Fld(4, 4) //[7:4]
+    #define CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA                   Fld(1, 8) //[8:8]
+    #define CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA           Fld(1, 25) //[25:25]
+    #define CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA               Fld(1, 26) //[26:26]
+    #define CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA                   Fld(1, 28) //[28:28]
+    #define CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA                   Fld(3, 29) //[31:29]
+
+#define DDRPHY_REG_CA_CMD2                                     (DDRPHY_AO_BASE_ADDRESS + 0x047C)
+    #define CA_CMD2_RG_TX_ARCLK_ODTEN_DIS_CA                   Fld(1, 0) //[0:0]
+    #define CA_CMD2_RG_TX_ARCLK_OE_DIS_CA                      Fld(1, 1) //[1:1]
+    #define CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA                  Fld(1, 2) //[2:2]
+    #define CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA                   Fld(1, 3) //[3:3]
+    #define CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA                   Fld(1, 14) //[14:14]
+    #define CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA                    Fld(1, 15) //[15:15]
+    #define CA_CMD2_RG_TX_ARCMD_ODTEN_DIS_CA                   Fld(1, 20) //[20:20]
+    #define CA_CMD2_RG_TX_ARCMD_OE_DIS_CA                      Fld(1, 21) //[21:21]
+    #define CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA                   Fld(1, 22) //[22:22]
+    #define CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA                    Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_CA_CMD3                                     (DDRPHY_AO_BASE_ADDRESS + 0x0480)
+    #define CA_CMD3_RG_ARCMD_ATPG_EN                           Fld(1, 0) //[0:0]
+    #define CA_CMD3_RG_RX_ARCMD_SMT_EN                         Fld(1, 1) //[1:1]
+    #define CA_CMD3_RG_TX_ARCMD_EN                             Fld(1, 2) //[2:2]
+    #define CA_CMD3_RG_ARCMD_RESETB                            Fld(1, 3) //[3:3]
+    #define CA_CMD3_RG_RX_ARCLK_IN_BUFF_EN                     Fld(1, 5) //[5:5]
+    #define CA_CMD3_RG_RX_ARCMD_IN_BUFF_EN                     Fld(1, 7) //[7:7]
+    #define CA_CMD3_RG_RX_ARCMD_STBENCMP_EN                    Fld(1, 10) //[10:10]
+    #define CA_CMD3_RG_RX_ARCMD_OFFC_EN                        Fld(1, 11) //[11:11]
+    #define CA_CMD3_RG_RX_ARCLK_SWAP_EN                        Fld(1, 15) //[15:15]
+    #define CA_CMD3_RG_ARPI_ASYNC_EN_CA                        Fld(1, 23) //[23:23]
+    #define CA_CMD3_RG_ARPI_LAT_EN_CA                          Fld(1, 24) //[24:24]
+    #define CA_CMD3_RG_ARPI_MCK_FB_SEL_CA                      Fld(2, 26) //[27:26]
+
+#define DDRPHY_REG_CA_CMD4                                     (DDRPHY_AO_BASE_ADDRESS + 0x0484)
+    #define CA_CMD4_RG_RX_ARCLK_EYE_R_DLY                      Fld(7, 0) //[6:0]
+    #define CA_CMD4_RG_RX_ARCLK_EYE_F_DLY                      Fld(7, 8) //[14:8]
+    #define CA_CMD4_RG_RX_ARCMD_EYE_R_DLY                      Fld(6, 16) //[21:16]
+    #define CA_CMD4_RG_RX_ARCMD_EYE_F_DLY                      Fld(6, 24) //[29:24]
+
+#define DDRPHY_REG_CA_CMD5                                     (DDRPHY_AO_BASE_ADDRESS + 0x0488)
+    #define CA_CMD5_RG_RX_ARCMD_EYE_VREF_SEL                   Fld(6, 8) //[13:8]
+    #define CA_CMD5_RG_RX_ARCMD_VREF_EN                        Fld(1, 16) //[16:16]
+    #define CA_CMD5_RG_RX_ARCMD_EYE_VREF_EN                    Fld(1, 17) //[17:17]
+    #define CA_CMD5_RG_RX_ARCMD_EYE_SEL                        Fld(4, 20) //[23:20]
+    #define CA_CMD5_RG_RX_ARCMD_EYE_EN                         Fld(1, 24) //[24:24]
+    #define CA_CMD5_RG_RX_ARCMD_EYE_STBEN_RESETB               Fld(1, 25) //[25:25]
+    #define CA_CMD5_RG_RX_ARCLK_DVS_EN                         Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_CA_CMD6                                     (DDRPHY_AO_BASE_ADDRESS + 0x048C)
+    #define CA_CMD6_RG_RX_ARCMD_BIAS_PS                        Fld(2, 0) //[1:0]
+    #define CA_CMD6_RG_TX_ARCMD_OE_EXT_DIS                     Fld(1, 2) //[2:2]
+    #define CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS                  Fld(1, 3) //[3:3]
+    #define CA_CMD6_RG_RX_ARCMD_RPRE_TOG_EN                    Fld(1, 5) //[5:5]
+    #define CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN                    Fld(1, 6) //[6:6]
+    #define CA_CMD6_RG_RX_ARCMD_OP_BIAS_SW_EN                  Fld(1, 7) //[7:7]
+    #define CA_CMD6_RG_RX_ARCMD_LPBK_EN                        Fld(1, 8) //[8:8]
+    #define CA_CMD6_RG_RX_ARCMD_O1_SEL                         Fld(1, 9) //[9:9]
+    #define CA_CMD6_RG_RX_ARCMD_JM_SEL                         Fld(1, 11) //[11:11]
+    #define CA_CMD6_RG_RX_ARCMD_BIAS_EN                        Fld(1, 12) //[12:12]
+    #define CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL                  Fld(2, 14) //[15:14]
+    #define CA_CMD6_RG_RX_ARCMD_DDR4_SEL                       Fld(1, 16) //[16:16]
+    #define CA_CMD6_RG_TX_ARCMD_DDR4_SEL                       Fld(1, 17) //[17:17]
+    #define CA_CMD6_RG_RX_ARCMD_DDR3_SEL                       Fld(1, 18) //[18:18]
+    #define CA_CMD6_RG_TX_ARCMD_DDR3_SEL                       Fld(1, 19) //[19:19]
+    #define CA_CMD6_RG_TX_ARCMD_LP5_SEL                        Fld(1, 20) //[20:20]
+    #define CA_CMD6_RG_TX_ARCMD_LP4_SEL                        Fld(1, 21) //[21:21]
+    #define CA_CMD6_RG_TX_ARCMD_CAP_EN                         Fld(1, 24) //[24:24]
+    #define CA_CMD6_RG_TX_ARCMD_DATA_SWAP_EN                   Fld(1, 25) //[25:25]
+    #define CA_CMD6_RG_TX_ARCMD_DATA_SWAP                      Fld(2, 26) //[27:26]
+    #define CA_CMD6_RG_RX_ARCMD_EYE_DLY_DQS_BYPASS             Fld(1, 28) //[28:28]
+    #define CA_CMD6_RG_RX_ARCMD_EYE_OE_GATE_EN                 Fld(1, 29) //[29:29]
+    #define CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL                  Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_CA_CMD7                                     (DDRPHY_AO_BASE_ADDRESS + 0x0490)
+    #define CA_CMD7_RG_TX_ARCLKB_PULL_DN                       Fld(1, 0) //[0:0]
+    #define CA_CMD7_RG_TX_ARCLKB_PULL_UP                       Fld(1, 1) //[1:1]
+    #define CA_CMD7_RG_TX_ARCLK_PULL_DN                        Fld(1, 2) //[2:2]
+    #define CA_CMD7_RG_TX_ARCLK_PULL_UP                        Fld(1, 3) //[3:3]
+    #define CA_CMD7_RG_TX_ARCS0_PULL_DN                        Fld(1, 4) //[4:4]
+    #define CA_CMD7_RG_TX_ARCS0_PULL_UP                        Fld(1, 5) //[5:5]
+    #define CA_CMD7_RG_TX_ARCMD_PULL_DN                        Fld(1, 6) //[6:6]
+    #define CA_CMD7_RG_TX_ARCMD_PULL_UP                        Fld(1, 7) //[7:7]
+    #define CA_CMD7_RG_TX_ARCS1_PULL_DN                        Fld(1, 8) //[8:8]
+    #define CA_CMD7_RG_TX_ARCS1_PULL_UP                        Fld(1, 9) //[9:9]
+    #define CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y                  Fld(1, 16) //[16:16]
+
+#define DDRPHY_REG_CA_CMD8                                     (DDRPHY_AO_BASE_ADDRESS + 0x0494)
+    #define CA_CMD8_RG_TX_ARCMD_EN_LP4P                        Fld(1, 0) //[0:0]
+    #define CA_CMD8_RG_TX_ARCMD_EN_CAP_LP4P                    Fld(1, 1) //[1:1]
+    #define CA_CMD8_RG_TX_ARCMD_CAP_DET                        Fld(1, 2) //[2:2]
+    #define CA_CMD8_RG_TX_ARCMD_CKE_MCK4X_SEL                  Fld(2, 3) //[4:3]
+    #define CA_CMD8_RG_RX_ARCLK_DQSIEN_BURST_E1_EN             Fld(1, 8) //[8:8]
+    #define CA_CMD8_RG_RX_ARCLK_DQSIEN_BURST_E2_EN             Fld(1, 9) //[9:9]
+    #define CA_CMD8_RG_RX_ARCLK_GATE_EN_MODE                   Fld(1, 12) //[12:12]
+    #define CA_CMD8_RG_RX_ARCLK_SER_RST_MODE                   Fld(1, 13) //[13:13]
+    #define CA_CMD8_RG_ARDLL_RESETB_CA                         Fld(1, 15) //[15:15]
+    #define CA_CMD8_RG_TX_ARCMD_LP3_CKE_SEL                    Fld(1, 16) //[16:16]
+    #define CA_CMD8_RG_TX_ARCMD_LP4_CKE_SEL                    Fld(1, 17) //[17:17]
+    #define CA_CMD8_RG_TX_ARCMD_LP4X_CKE_SEL                   Fld(1, 18) //[18:18]
+    #define CA_CMD8_RG_TX_ARCMD_LSH_DQM_CG_EN                  Fld(1, 20) //[20:20]
+    #define CA_CMD8_RG_TX_ARCMD_LSH_DQS_CG_EN                  Fld(1, 21) //[21:21]
+    #define CA_CMD8_RG_TX_ARCMD_LSH_DQ_CG_EN                   Fld(1, 22) //[22:22]
+    #define CA_CMD8_RG_TX_ARCMD_OE_SUS_EN                      Fld(1, 24) //[24:24]
+    #define CA_CMD8_RG_TX_ARCMD_ODTEN_OE_SUS_EN                Fld(1, 25) //[25:25]
+
+#define DDRPHY_REG_CA_CMD9                                     (DDRPHY_AO_BASE_ADDRESS + 0x0498)
+    #define CA_CMD9_RG_RX_ARCMD_STBEN_RESETB                   Fld(1, 0) //[0:0]
+    #define CA_CMD9_RG_RX_ARCLK_STBEN_RESETB                   Fld(1, 4) //[4:4]
+    #define CA_CMD9_RG_RX_ARCLK_DQSIENMODE                     Fld(1, 5) //[5:5]
+    #define CA_CMD9_R_DMRXDVS_R_F_DLY_RK_OPT                   Fld(1, 6) //[6:6]
+    #define CA_CMD9_R_DMRXFIFO_STBENCMP_EN_CA                  Fld(1, 7) //[7:7]
+    #define CA_CMD9_R_IN_GATE_EN_LOW_OPT_CA                    Fld(8, 8) //[15:8]
+    #define CA_CMD9_R_DMDQSIEN_VALID_LAT_CA                    Fld(3, 16) //[18:16]
+    #define CA_CMD9_R_DMDQSIEN_RDSEL_LAT_CA                    Fld(3, 20) //[22:20]
+    #define CA_CMD9_R_DMRXDVS_VALID_LAT_CA                     Fld(3, 24) //[26:24]
+    #define CA_CMD9_R_DMRXDVS_RDSEL_LAT_CA                     Fld(3, 28) //[30:28]
+
+#define DDRPHY_REG_CA_CMD10                                    (DDRPHY_AO_BASE_ADDRESS + 0x049C)
+    #define CA_CMD10_ARPI_CG_RK1_SRC_SEL_CA                    Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_CA_CMD11                                    (DDRPHY_AO_BASE_ADDRESS + 0x04A0)
+    #define CA_CMD11_RG_RRESETB_DRVP                           Fld(5, 0) //[4:0]
+    #define CA_CMD11_RG_RRESETB_DRVN                           Fld(5, 8) //[12:8]
+    #define CA_CMD11_RG_RX_RRESETB_SMT_EN                      Fld(1, 16) //[16:16]
+    #define CA_CMD11_RG_TX_RRESETB_SCAN_IN_EN                  Fld(1, 17) //[17:17]
+    #define CA_CMD11_RG_TX_RRESETB_DDR4_SEL                    Fld(1, 18) //[18:18]
+    #define CA_CMD11_RG_TX_RRESETB_DDR3_SEL                    Fld(1, 19) //[19:19]
+    #define CA_CMD11_RG_TX_RRESETB_PULL_DN                     Fld(1, 20) //[20:20]
+    #define CA_CMD11_RG_TX_RRESETB_PULL_UP                     Fld(1, 21) //[21:21]
+    #define CA_CMD11_RG_RRESETB_OPEN_DRAIN_EN                  Fld(1, 22) //[22:22]
+
+#define DDRPHY_REG_CA_PHY2                                     (DDRPHY_AO_BASE_ADDRESS + 0x04A4)
+    #define CA_PHY2_RG_RX_ARCLK_SE_SWAP_EN_CA                  Fld(1, 0) //[0:0]
+    #define CA_PHY2_RG_RX_ARCLK_JM_SEL_CA                      Fld(4, 4) //[7:4]
+    #define CA_PHY2_RG_RX_ARCLK_JM_EN_CA                       Fld(1, 8) //[8:8]
+    #define CA_PHY2_RG_RX_ARCLK_JM_DLY_CA                      Fld(9, 16) //[24:16]
+    #define CA_PHY2_RG_RX_ARCLK_DQSIEN_UI_LEAD_LAG_EN_CA       Fld(1, 28) //[28:28]
+    #define CA_PHY2_RG_RX_ARCLK_DQSIEN_TIE_GATE_EN_CA          Fld(1, 29) //[29:29]
+    #define CA_PHY2_RG_RX_ARCLKB_SE_SWAP_EN_CA                 Fld(1, 30) //[30:30]
+
+#define DDRPHY_REG_CA_PHY3                                     (DDRPHY_AO_BASE_ADDRESS + 0x04A8)
+    #define CA_PHY3_RG_RX_ARCA_DUTY_VCAL_VREF_SEL_CA           Fld(7, 8) //[14:8]
+    #define CA_PHY3_RG_RX_ARCA_DUTY_VCAL_OFFSETC_CA            Fld(4, 16) //[19:16]
+    #define CA_PHY3_RG_RX_ARCA_DUTY_VCAL_EN_CA                 Fld(1, 20) //[20:20]
+    #define CA_PHY3_RG_RX_ARCA_DUTY_VCAL_CLK_SEL_CA            Fld(2, 24) //[25:24]
+    #define CA_PHY3_RG_RX_ARCA_DUTY_VCAL_CLK_RC_SEL_CA         Fld(2, 26) //[27:26]
+    #define CA_PHY3_RG_RX_ARCA_BUFF_EN_SEL_CA                  Fld(1, 28) //[28:28]
+
+#define DDRPHY_REG_CA_TX_MCK                                   (DDRPHY_AO_BASE_ADDRESS + 0x04AC)
+    #define CA_TX_MCK_R_DMRESETB_DRVP_FRPHY                    Fld(5, 21) //[25:21]
+    #define CA_TX_MCK_R_DMRESETB_DRVN_FRPHY                    Fld(5, 26) //[30:26]
+    #define CA_TX_MCK_R_DMRESET_FRPHY_OPT                      Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_CA_PHY4                                     (DDRPHY_AO_BASE_ADDRESS + 0x04B0)
+    #define CA_PHY4_RG_ARPI_SUM_MON_SEL_C0                     Fld(3, 0) //[2:0]
+    #define CA_PHY4_RG_RX_ARCA_INB_BIAS_SEL_C0                 Fld(1, 4) //[4:4]
+
+#define DDRPHY_REG_CA_TX_ARCS_CTRL                             (DDRPHY_AO_BASE_ADDRESS + 0x04B4)
+    #define CA_TX_ARCS_CTRL_RG_TX_ARCS_OE_TIE_SEL_C0           Fld(1, 0) //[0:0]
+    #define CA_TX_ARCS_CTRL_RG_TX_ARCS_PULL_DN_C0              Fld(1, 1) //[1:1]
+    #define CA_TX_ARCS_CTRL_RG_TX_ARCS_PULL_UP_C0              Fld(1, 2) //[2:2]
+
+#define DDRPHY_REG_CA_TX_ARDQ_CTRL                             (DDRPHY_AO_BASE_ADDRESS + 0x04B8)
+    #define CA_TX_ARDQ_CTRL_RG_TX_ARDQ6_OE_TIE_EN_C0           Fld(1, 0) //[0:0]
+    #define CA_TX_ARDQ_CTRL_RG_TX_ARDQ7_OE_TIE_EN_C0           Fld(1, 1) //[1:1]
+
+#define DDRPHY_REG_MISC_STBCAL                                 (DDRPHY_AO_BASE_ADDRESS + 0x04E0)
+    #define MISC_STBCAL_PIMASK_RKCHG_OPT                       Fld(1, 0) //[0:0]
+    #define MISC_STBCAL_PIMASK_RKCHG_EXT                       Fld(3, 1) //[3:1]
+    #define MISC_STBCAL_STBDLELAST_OPT                         Fld(1, 4) //[4:4]
+    #define MISC_STBCAL_STBDLELAST_PULSE                       Fld(4, 8) //[11:8]
+    #define MISC_STBCAL_STBDLELAST_FILTER                      Fld(1, 12) //[12:12]
+    #define MISC_STBCAL_STBUPDSTOP                             Fld(1, 13) //[13:13]
+    #define MISC_STBCAL_CG_RKEN                                Fld(1, 14) //[14:14]
+    #define MISC_STBCAL_STBSTATE_OPT                           Fld(1, 15) //[15:15]
+    #define MISC_STBCAL_PHYVALID_IG                            Fld(1, 16) //[16:16]
+    #define MISC_STBCAL_SREF_DQSGUPD                           Fld(1, 17) //[17:17]
+    #define MISC_STBCAL_RKCHGMASKDIS                           Fld(1, 19) //[19:19]
+    #define MISC_STBCAL_PICGEN                                 Fld(1, 20) //[20:20]
+    #define MISC_STBCAL_REFUICHG                               Fld(1, 21) //[21:21]
+    #define MISC_STBCAL_STBCAL2R                               Fld(1, 23) //[23:23]
+    #define MISC_STBCAL_STBDLYOUT_OPT                          Fld(1, 25) //[25:25]
+    #define MISC_STBCAL_PICHGBLOCK_NORD                        Fld(1, 26) //[26:26]
+    #define MISC_STBCAL_STB_DQIEN_IG                           Fld(1, 27) //[27:27]
+    #define MISC_STBCAL_DQSIENCG_CHG_EN                        Fld(1, 28) //[28:28]
+    #define MISC_STBCAL_DQSIENCG_NORMAL_EN                     Fld(1, 29) //[29:29]
+    #define MISC_STBCAL_DQSIENMODE                             Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_STBCAL1                                (DDRPHY_AO_BASE_ADDRESS + 0x04E4)
+    #define MISC_STBCAL1_STBCNT_SHU_RST_EN                     Fld(1, 0) //[0:0]
+    #define MISC_STBCAL1_RKUICHG_EN                            Fld(1, 1) //[1:1]
+    #define MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD                Fld(1, 2) //[2:2]
+    #define MISC_STBCAL1_STBCNT_MODESEL                        Fld(1, 4) //[4:4]
+    #define MISC_STBCAL1_DQSIEN_7UI_EN                         Fld(1, 5) //[5:5]
+    #define MISC_STBCAL1_STB_SHIFT_DTCOUT_IG                   Fld(1, 6) //[6:6]
+    #define MISC_STBCAL1_STB_FLAGCLR_OPT                       Fld(1, 8) //[8:8]
+    #define MISC_STBCAL1_STB_DLLFRZ_IG                         Fld(1, 9) //[9:9]
+    #define MISC_STBCAL1_STBCNT_SW_RST                         Fld(1, 15) //[15:15]
+    #define MISC_STBCAL1_STBCAL_FILTER                         Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_MISC_STBCAL2                                (DDRPHY_AO_BASE_ADDRESS + 0x04E8)
+    #define MISC_STBCAL2_STB_PIDLYCG_IG                        Fld(1, 0) //[0:0]
+    #define MISC_STBCAL2_STB_UIDLYCG_IG                        Fld(1, 1) //[1:1]
+    #define MISC_STBCAL2_STBENCMPEN                            Fld(1, 2) //[2:2]
+    #define MISC_STBCAL2_STB_DBG_EN                            Fld(4, 4) //[7:4]
+    #define MISC_STBCAL2_STB_DBG_CG_AO                         Fld(1, 8) //[8:8]
+    #define MISC_STBCAL2_STB_DBG_UIPI_UPD_OPT                  Fld(1, 9) //[9:9]
+    #define MISC_STBCAL2_DQSGCNT_BYP_REF                       Fld(1, 10) //[10:10]
+    #define MISC_STBCAL2_STB_DRS_MASK_HW_SAVE                  Fld(1, 12) //[12:12]
+    #define MISC_STBCAL2_STB_DRS_RK1_FLAG_SYNC_RK0_EN          Fld(1, 13) //[13:13]
+    #define MISC_STBCAL2_STB_PICG_EARLY_1T_EN                  Fld(1, 16) //[16:16]
+    #define MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN              Fld(1, 17) //[17:17]
+    #define MISC_STBCAL2_STB_IG_XRANK_CG_RST                   Fld(1, 18) //[18:18]
+    #define MISC_STBCAL2_STB_RST_BY_RANK                       Fld(1, 19) //[19:19]
+    #define MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN               Fld(1, 20) //[20:20]
+    #define MISC_STBCAL2_DQSG_CNT_EN                           Fld(1, 21) //[21:21]
+    #define MISC_STBCAL2_DQSG_CNT_RST                          Fld(1, 22) //[22:22]
+    #define MISC_STBCAL2_STB_DBG_STATUS                        Fld(4, 24) //[27:24]
+    #define MISC_STBCAL2_STB_GERRSTOP                          Fld(1, 28) //[28:28]
+    #define MISC_STBCAL2_STB_GERR_RST                          Fld(1, 29) //[29:29]
+    #define MISC_STBCAL2_STB_GERR_B01                          Fld(1, 30) //[30:30]
+    #define MISC_STBCAL2_STB_GERR_B23                          Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_CG_CTRL0                               (DDRPHY_AO_BASE_ADDRESS + 0x04EC)
+    #define MISC_CG_CTRL0_W_CHG_MEM                            Fld(1, 0) //[0:0]
+    #define MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1        Fld(3, 1) //[3:1]
+    #define MISC_CG_CTRL0_CLK_MEM_SEL                          Fld(2, 4) //[5:4]
+    #define MISC_CG_CTRL0_CLK_MEM_INV                          Fld(1, 6) //[6:6]
+    #define MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT7          Fld(1, 7) //[7:7]
+    #define MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE                Fld(1, 8) //[8:8]
+    #define MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE              Fld(1, 9) //[9:9]
+    #define MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE                 Fld(1, 10) //[10:10]
+    #define MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE               Fld(1, 11) //[11:11]
+    #define MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE                Fld(1, 12) //[12:12]
+    #define MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE              Fld(1, 13) //[13:13]
+    #define MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE              Fld(1, 14) //[14:14]
+    #define MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE             Fld(1, 15) //[15:15]
+    #define MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE           Fld(1, 16) //[16:16]
+    #define MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE           Fld(1, 17) //[17:17]
+    #define MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN                   Fld(1, 18) //[18:18]
+    #define MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE              Fld(1, 19) //[19:19]
+    #define MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF                   Fld(1, 20) //[20:20]
+    #define MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT21         Fld(1, 21) //[21:21]
+    #define MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF                  Fld(1, 22) //[22:22]
+    #define MISC_CG_CTRL0_RG_DBG_OUT_SEL                       Fld(2, 23) //[24:23]
+    #define MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE   Fld(1, 25) //[25:25]
+    #define MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE   Fld(1, 26) //[26:26]
+    #define MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT27         Fld(1, 27) //[27:27]
+    #define MISC_CG_CTRL0_RG_DA_RREF_CK_SEL                    Fld(1, 28) //[28:28]
+    #define MISC_CG_CTRL0_RG_FREERUN_MCK_CG                    Fld(1, 29) //[29:29]
+    #define MISC_CG_CTRL0_RG_FREERUN_MCK_SEL                   Fld(1, 30) //[30:30]
+    #define MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT31         Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_CG_CTRL1                               (DDRPHY_AO_BASE_ADDRESS + 0x04F0)
+    #define MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_CG_CTRL2                               (DDRPHY_AO_BASE_ADDRESS + 0x04F4)
+    #define MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG                   Fld(1, 0) //[0:0]
+    #define MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL                   Fld(5, 1) //[5:1]
+    #define MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON                  Fld(1, 6) //[6:6]
+    #define MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN                    Fld(1, 7) //[7:7]
+    #define MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN                    Fld(1, 8) //[8:8]
+    #define MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT                   Fld(7, 9) //[15:9]
+    #define MISC_CG_CTRL2_RG_MEM_DCM_FSEL                      Fld(5, 16) //[20:16]
+    #define MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL                 Fld(5, 21) //[25:21]
+    #define MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF                 Fld(1, 26) //[26:26]
+    #define MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27         Fld(1, 27) //[27:27]
+    #define MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE                Fld(1, 28) //[28:28]
+    #define MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE              Fld(1, 29) //[29:29]
+    #define MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30         Fld(1, 30) //[30:30]
+    #define MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE            Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_CG_CTRL3                               (DDRPHY_AO_BASE_ADDRESS + 0x04F8)
+    #define MISC_CG_CTRL3_R_LBK_CG_CTRL                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_CG_CTRL5                               (DDRPHY_AO_BASE_ADDRESS + 0x0500)
+    #define MISC_CG_CTRL5_RESERVE                              Fld(16, 0) //[15:0]
+    #define MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN                     Fld(1, 16) //[16:16]
+    #define MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN                     Fld(1, 17) //[17:17]
+    #define MISC_CG_CTRL5_R_CA_DLY_DCM_EN                      Fld(1, 18) //[18:18]
+    #define MISC_CG_CTRL5_R_DQ1_PI_DCM_EN                      Fld(1, 20) //[20:20]
+    #define MISC_CG_CTRL5_R_DQ0_PI_DCM_EN                      Fld(1, 21) //[21:21]
+    #define MISC_CG_CTRL5_R_CA_PI_DCM_EN                       Fld(1, 22) //[22:22]
+    #define MISC_CG_CTRL5_R_PICG_MON_CLR                       Fld(1, 23) //[23:23]
+    #define MISC_CG_CTRL5_R_PICG_MON_EN                        Fld(1, 24) //[24:24]
+
+#define DDRPHY_REG_MISC_CG_CTRL7                               (DDRPHY_AO_BASE_ADDRESS + 0x0504)
+    #define MISC_CG_CTRL7_RESERVED_MISC_CG_CTRL7_BIT3_0        Fld(4, 0) //[3:0]
+    #define MISC_CG_CTRL7_FMEM_CK_CG_PINMUX                    Fld(2, 4) //[5:4]
+    #define MISC_CG_CTRL7_RESERVED_MISC_CG_CTRL7_BIT10_6       Fld(5, 6) //[10:6]
+    #define MISC_CG_CTRL7_CK_BFE_DCM_EN                        Fld(1, 11) //[11:11]
+    #define MISC_CG_CTRL7_RESERVED_MISC_CG_CTRL7_BIT15_12      Fld(4, 12) //[15:12]
+    #define MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL                 Fld(1, 16) //[16:16]
+    #define MISC_CG_CTRL7_RESERVED_MISC_CG_CTRL7_BIT31_17      Fld(15, 17) //[31:17]
+
+#define DDRPHY_REG_MISC_CG_CTRL9                               (DDRPHY_AO_BASE_ADDRESS + 0x0508)
+    #define MISC_CG_CTRL9_RESERVED_MISC_CG_CTRL9_BIT3_0        Fld(4, 0) //[3:0]
+    #define MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN             Fld(1, 4) //[4:4]
+    #define MISC_CG_CTRL9_RESERVED_MISC_CG_CTRL9_BIT7_5        Fld(3, 5) //[7:5]
+    #define MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN          Fld(1, 8) //[8:8]
+    #define MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF             Fld(1, 9) //[9:9]
+    #define MISC_CG_CTRL9_RG_DDR400_MCK4X_I_FORCE_ON           Fld(1, 10) //[10:10]
+    #define MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF              Fld(1, 11) //[11:11]
+    #define MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN          Fld(1, 12) //[12:12]
+    #define MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF             Fld(1, 13) //[13:13]
+    #define MISC_CG_CTRL9_RG_DDR400_MCK4X_Q_FORCE_ON           Fld(1, 14) //[14:14]
+    #define MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF              Fld(1, 15) //[15:15]
+    #define MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN          Fld(1, 16) //[16:16]
+    #define MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF             Fld(1, 17) //[17:17]
+    #define MISC_CG_CTRL9_RG_DDR400_MCK4X_O_FORCE_ON           Fld(1, 18) //[18:18]
+    #define MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF              Fld(1, 19) //[19:19]
+    #define MISC_CG_CTRL9_RESERVED_MISC_CG_CTRL9_BIT31_20      Fld(12, 20) //[31:20]
+
+#define DDRPHY_REG_MISC_CG_CTRL10                              (DDRPHY_AO_BASE_ADDRESS + 0x050C)
+    #define MISC_CG_CTRL10_RESERVED_MISC_CG_CTRL10_BIT31_0     Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DVFSCTL                                (DDRPHY_AO_BASE_ADDRESS + 0x0510)
+    #define MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW                Fld(4, 0) //[3:0]
+    #define MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW               Fld(4, 4) //[7:4]
+    #define MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW               Fld(4, 8) //[11:8]
+    #define MISC_DVFSCTL_R_DVFS_PICG_MARGIN4_NEW               Fld(4, 12) //[15:12]
+    #define MISC_DVFSCTL_R_DVFS_MCK_CG_EN_FT_EN                Fld(1, 16) //[16:16]
+    #define MISC_DVFSCTL_R_DVFS_MCK_CG_EN_FT_IN                Fld(1, 17) //[17:17]
+    #define MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT           Fld(1, 18) //[18:18]
+    #define MISC_DVFSCTL_R_NEW_SHU_MUX_SPM                     Fld(1, 19) //[19:19]
+    #define MISC_DVFSCTL_R_MPDIV_SHU_GP                        Fld(3, 20) //[22:20]
+    #define MISC_DVFSCTL_R_OTHER_SHU_GP                        Fld(2, 24) //[25:24]
+    #define MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE             Fld(1, 26) //[26:26]
+    #define MISC_DVFSCTL_R_DVFS_PICG_POSTPONE                  Fld(1, 27) //[27:27]
+    #define MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN                   Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_DVFSCTL2                               (DDRPHY_AO_BASE_ADDRESS + 0x0514)
+    #define MISC_DVFSCTL2_DLL_LOCK_SHU_EN                      Fld(1, 0) //[0:0]
+    #define MISC_DVFSCTL2_RG_IGNORE_PHY_SH_CHG_CLK_RDY_CHA     Fld(1, 1) //[1:1]
+    #define MISC_DVFSCTL2_RG_IGNORE_PHY_SH_CHG_CLK_RDY_CHB     Fld(1, 2) //[2:2]
+    #define MISC_DVFSCTL2_RG_TOPCK_FMEM_CK_BLOCK_DURING_DFS    Fld(1, 3) //[3:3]
+    #define MISC_DVFSCTL2_RG_DLL_SHUFFLE                       Fld(1, 4) //[4:4]
+    #define MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE              Fld(1, 5) //[5:5]
+    #define MISC_DVFSCTL2_R_DVFS_DDRPHY_FSM_CLR                Fld(1, 7) //[7:7]
+    #define MISC_DVFSCTL2_RG_MRW_AFTER_DFS                     Fld(1, 8) //[8:8]
+    #define MISC_DVFSCTL2_R_DVFS_CDC_OPTION                    Fld(1, 9) //[9:9]
+    #define MISC_DVFSCTL2_R_DVFS_PICG_MARGIN                   Fld(2, 10) //[11:10]
+    #define MISC_DVFSCTL2_R_DVFS_DLL_CHA                       Fld(1, 12) //[12:12]
+    #define MISC_DVFSCTL2_R_CDC_MUX_SEL_OPTION                 Fld(1, 13) //[13:13]
+    #define MISC_DVFSCTL2_R_DVFS_PARK_N                        Fld(1, 14) //[14:14]
+    #define MISC_DVFSCTL2_R_DVFS_OPTION                        Fld(1, 15) //[15:15]
+    #define MISC_DVFSCTL2_RG_PHY_ST_DELAY_BYPASS_CK_CHG_TO_MCLK Fld(1, 16) //[16:16]
+    #define MISC_DVFSCTL2_RG_PHY_ST_DELAY_BYPASS_CK_CHG_TO_BCLK Fld(1, 17) //[17:17]
+    #define MISC_DVFSCTL2_RG_PS_CLK_FREERUN                    Fld(1, 18) //[18:18]
+    #define MISC_DVFSCTL2_DVFS_SYNC_MASK_FOR_PHY               Fld(1, 19) //[19:19]
+    #define MISC_DVFSCTL2_GT_SYNC_MASK_FOR_PHY                 Fld(1, 20) //[20:20]
+    #define MISC_DVFSCTL2_GTDMW_SYNC_MASK_FOR_PHY              Fld(1, 21) //[21:21]
+    #define MISC_DVFSCTL2_R_DVFS_RG_CDC_TX_SEL                 Fld(1, 26) //[26:26]
+    #define MISC_DVFSCTL2_R_DVFS_RG_CDC_SYNC_ENABLE            Fld(1, 27) //[27:27]
+    #define MISC_DVFSCTL2_R_SHU_RESTORE                        Fld(1, 28) //[28:28]
+    #define MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL                Fld(1, 29) //[29:29]
+    #define MISC_DVFSCTL2_R_DVFS_SYNC_MODULE_RST_SEL           Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_DVFSCTL3                               (DDRPHY_AO_BASE_ADDRESS + 0x0518)
+    #define MISC_DVFSCTL3_RG_DFS_BEF_PHY_SHU_DBG_EN            Fld(1, 0) //[0:0]
+    #define MISC_DVFSCTL3_RG_DFS_AFT_PHY_SHU_DBG_EN            Fld(1, 1) //[1:1]
+    #define MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_MCLK_BY_LPC_EN      Fld(1, 2) //[2:2]
+    #define MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_BCLK_BY_LPC_EN      Fld(1, 3) //[3:3]
+    #define MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK      Fld(1, 4) //[4:4]
+    #define MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_MCLK      Fld(1, 5) //[5:5]
+    #define MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_BCLK      Fld(1, 6) //[6:6]
+    #define MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK      Fld(1, 7) //[7:7]
+    #define MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI             Fld(2, 8) //[9:8]
+    #define MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE            Fld(2, 10) //[11:10]
+    #define MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_MCLK  Fld(6, 12) //[17:12]
+    #define MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_MCLK  Fld(4, 18) //[21:18]
+    #define MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK  Fld(6, 22) //[27:22]
+    #define MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK  Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_CKMUX_SEL                              (DDRPHY_AO_BASE_ADDRESS + 0x051C)
+    #define MISC_CKMUX_SEL_R_PHYCTRLMUX                        Fld(1, 0) //[0:0]
+    #define MISC_CKMUX_SEL_R_PHYCTRLDCM                        Fld(1, 1) //[1:1]
+    #define MISC_CKMUX_SEL_R_DMMCTLPLL_CKSEL                   Fld(2, 4) //[5:4]
+    #define MISC_CKMUX_SEL_BCLK_SHU_SEL                        Fld(1, 8) //[8:8]
+    #define MISC_CKMUX_SEL_RG_52M_104M_SEL                     Fld(1, 12) //[12:12]
+    #define MISC_CKMUX_SEL_RG_104M_208M_SEL                    Fld(1, 13) //[13:13]
+    #define MISC_CKMUX_SEL_RG_FMEM_CK_OCC_FRC_EN               Fld(1, 14) //[14:14]
+    #define MISC_CKMUX_SEL_RG_MEM_CLKMUX_REFCLK_SEL            Fld(1, 15) //[15:15]
+    #define MISC_CKMUX_SEL_FB_CK_MUX                           Fld(2, 16) //[17:16]
+    #define MISC_CKMUX_SEL_FMEM_CK_MUX                         Fld(2, 18) //[19:18]
+
+#define DDRPHY_REG_MISC_CLK_CTRL                               (DDRPHY_AO_BASE_ADDRESS + 0x0520)
+    #define MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN            Fld(1, 0) //[0:0]
+    #define MISC_CLK_CTRL_DVFS_CLK_MEM_SEL                     Fld(1, 1) //[1:1]
+    #define MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE               Fld(1, 8) //[8:8]
+    #define MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL                  Fld(2, 9) //[10:9]
+    #define MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE             Fld(2, 12) //[13:12]
+    #define MISC_CLK_CTRL_RESERVED_MISC_CLK_CTRL_BIT31_4       Fld(18, 14) //[31:14]
+
+#define DDRPHY_REG_MISC_DQSG_RETRY1                            (DDRPHY_AO_BASE_ADDRESS + 0x0524)
+    #define MISC_DQSG_RETRY1_R_RETRY_SAV_MSK                   Fld(1, 24) //[24:24]
+    #define MISC_DQSG_RETRY1_RETRY_DEBUG_RANK_SEL              Fld(2, 28) //[29:28]
+    #define MISC_DQSG_RETRY1_RETRY_DEBUG_BYTE_SEL              Fld(2, 30) //[31:30]
+
+#define DDRPHY_REG_MISC_RDSEL_TRACK                            (DDRPHY_AO_BASE_ADDRESS + 0x0528)
+    #define MISC_RDSEL_TRACK_RDSEL_SW_RST                      Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_MISC_PRE_TDQSCK1                            (DDRPHY_AO_BASE_ADDRESS + 0x052C)
+    #define MISC_PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL               Fld(1, 22) //[22:22]
+    #define MISC_PRE_TDQSCK1_TDQSCK_SW_UP_CASE                 Fld(1, 23) //[23:23]
+    #define MISC_PRE_TDQSCK1_TDQSCK_SW_SAVE                    Fld(1, 24) //[24:24]
+    #define MISC_PRE_TDQSCK1_TDQSCK_REG_DVFS                   Fld(1, 25) //[25:25]
+    #define MISC_PRE_TDQSCK1_TDQSCK_PRECAL_HW                  Fld(1, 26) //[26:26]
+    #define MISC_PRE_TDQSCK1_TDQSCK_PRECAL_START               Fld(1, 27) //[27:27]
+
+#define DDRPHY_REG_MISC_CDC_CTRL                               (DDRPHY_AO_BASE_ADDRESS + 0x0530)
+    #define MISC_CDC_CTRL_RESERVED_MISC_CDC_CTRL_30_0          Fld(31, 0) //[30:0]
+    #define MISC_CDC_CTRL_REG_CDC_BYPASS_DBG                   Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_LP_CTRL                                (DDRPHY_AO_BASE_ADDRESS + 0x0534)
+    #define MISC_LP_CTRL_RG_ARDMSUS_10                         Fld(1, 0) //[0:0]
+    #define MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL                  Fld(1, 1) //[1:1]
+    #define MISC_LP_CTRL_RG_RIMP_DMSUS_10                      Fld(1, 2) //[2:2]
+    #define MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL               Fld(1, 3) //[3:3]
+    #define MISC_LP_CTRL_RG_RRESETB_LP_SEL                     Fld(1, 4) //[4:4]
+    #define MISC_LP_CTRL_RG_RPHYPLL_RESETB_LP_SEL              Fld(1, 5) //[5:5]
+    #define MISC_LP_CTRL_RG_RPHYPLL_EN_LP_SEL                  Fld(1, 6) //[6:6]
+    #define MISC_LP_CTRL_RG_RCLRPLL_EN_LP_SEL                  Fld(1, 7) //[7:7]
+    #define MISC_LP_CTRL_RG_RPHYPLL_ADA_MCK8X_EN_LP_SEL        Fld(1, 8) //[8:8]
+    #define MISC_LP_CTRL_RG_RPHYPLL_AD_MCK8X_EN_LP_SEL         Fld(1, 9) //[9:9]
+    #define MISC_LP_CTRL_RG_RPHYPLL_TOP_REV_0_LP_SEL           Fld(1, 10) //[10:10]
+    #define MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL       Fld(1, 11) //[11:11]
+    #define MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL            Fld(1, 12) //[12:12]
+    #define MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL             Fld(1, 13) //[13:13]
+    #define MISC_LP_CTRL_RG_ADA_MCK8X_OP_LP_SEL                Fld(1, 14) //[14:14]
+    #define MISC_LP_CTRL_RG_AD_MCK8X_OP_LP_SEL                 Fld(1, 15) //[15:15]
+    #define MISC_LP_CTRL_RG_RPHYPLL_DDR400_EN_LP_SEL           Fld(1, 16) //[16:16]
+    #define MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL             Fld(1, 17) //[17:17]
+    #define MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL      Fld(1, 18) //[18:18]
+    #define MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL                Fld(1, 19) //[19:19]
+    #define MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL            Fld(1, 20) //[20:20]
+    #define MISC_LP_CTRL_RG_TX_RESETB_CTRL_OPT                 Fld(1, 21) //[21:21]
+    #define MISC_LP_CTRL_RESERVED_MISC_LP_CTRL_31_20           Fld(10, 22) //[31:22]
+
+#define DDRPHY_REG_MISC_RG_DFS_CTRL                            (DDRPHY_AO_BASE_ADDRESS + 0x0538)
+    #define MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL              Fld(1, 0) //[0:0]
+    #define MISC_RG_DFS_CTRL_RG_TX_TRACKING_DIS                Fld(1, 1) //[1:1]
+    #define MISC_RG_DFS_CTRL_RG_DPY_RXDLY_TRACK_EN             Fld(1, 2) //[2:2]
+    #define MISC_RG_DFS_CTRL_RG_DPY_PRECAL_UP                  Fld(1, 3) //[3:3]
+    #define MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM              Fld(4, 4) //[7:4]
+    #define MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE                Fld(1, 8) //[8:8]
+    #define MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH        Fld(1, 9) //[9:9]
+    #define MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD                   Fld(1, 10) //[10:10]
+    #define MISC_RG_DFS_CTRL_RESERVED_MISC_RG_DFS_CTRL_11_11   Fld(1, 11) //[11:11]
+    #define MISC_RG_DFS_CTRL_RG_DPHY_RESERVED                  Fld(4, 12) //[15:12]
+    #define MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL                   Fld(2, 16) //[17:16]
+    #define MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN                  Fld(1, 18) //[18:18]
+    #define MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN                 Fld(1, 19) //[19:19]
+    #define MISC_RG_DFS_CTRL_RG_PHYPLL_MODE_SW                 Fld(1, 20) //[20:20]
+    #define MISC_RG_DFS_CTRL_RG_PHYPLL2_MODE_SW                Fld(1, 21) //[21:21]
+    #define MISC_RG_DFS_CTRL_RG_DR_SHORT_QUEUE                 Fld(1, 22) //[22:22]
+    #define MISC_RG_DFS_CTRL_RG_DR_SHU_EN                      Fld(1, 23) //[23:23]
+    #define MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN                Fld(1, 24) //[24:24]
+    #define MISC_RG_DFS_CTRL_RG_TX_TRACKING_RETRY_EN           Fld(1, 25) //[25:25]
+    #define MISC_RG_DFS_CTRL_RG_RX_GATING_RETRY_EN             Fld(1, 26) //[26:26]
+    #define MISC_RG_DFS_CTRL_RESERVED_MISC_RG_DFS_CTRL_31_27   Fld(5, 27) //[31:27]
+
+#define DDRPHY_REG_MISC_DDR_RESERVE                            (DDRPHY_AO_BASE_ADDRESS + 0x053C)
+    #define MISC_DDR_RESERVE_WDT_CONF_ISO_CNT                  Fld(8, 0) //[7:0]
+    #define MISC_DDR_RESERVE_WDT_ISO_CNT                       Fld(8, 8) //[15:8]
+    #define MISC_DDR_RESERVE_WDT_SREF_CNT                      Fld(8, 16) //[23:16]
+    #define MISC_DDR_RESERVE_WDT_SM_CLR                        Fld(1, 24) //[24:24]
+    #define MISC_DDR_RESERVE_WDT_LITE_EN                       Fld(1, 25) //[25:25]
+
+#define DDRPHY_REG_MISC_IMP_CTRL1                              (DDRPHY_AO_BASE_ADDRESS + 0x0540)
+    #define MISC_IMP_CTRL1_RG_IMP_OCD_PUCMP_EN                 Fld(1, 0) //[0:0]
+    #define MISC_IMP_CTRL1_RG_IMP_EN                           Fld(1, 1) //[1:1]
+    #define MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL                    Fld(1, 2) //[2:2]
+    #define MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL                    Fld(1, 3) //[3:3]
+    #define MISC_IMP_CTRL1_RG_RIMP_BIAS_EN                     Fld(1, 4) //[4:4]
+    #define MISC_IMP_CTRL1_RG_RIMP_ODT_EN                      Fld(1, 5) //[5:5]
+    #define MISC_IMP_CTRL1_RG_RIMP_PRE_EN                      Fld(1, 6) //[6:6]
+    #define MISC_IMP_CTRL1_RG_RIMP_VREF_EN                     Fld(1, 7) //[7:7]
+    #define MISC_IMP_CTRL1_IMP_DIFF_THD                        Fld(5, 8) //[12:8]
+    #define MISC_IMP_CTRL1_IMP_ABN_LAT_CLR                     Fld(1, 14) //[14:14]
+    #define MISC_IMP_CTRL1_IMP_ABN_LAT_EN                      Fld(1, 15) //[15:15]
+    #define MISC_IMP_CTRL1_IMP_ABN_PRD                         Fld(12, 16) //[27:16]
+    #define MISC_IMP_CTRL1_IMP_CG_EN                           Fld(1, 30) //[30:30]
+    #define MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT                 Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_IMPCAL                                 (DDRPHY_AO_BASE_ADDRESS + 0x0544)
+    #define MISC_IMPCAL_DRVCGWREF                              Fld(1, 2) //[2:2]
+    #define MISC_IMPCAL_DQDRVSWUPD                             Fld(1, 3) //[3:3]
+    #define MISC_IMPCAL_IMPSRCEXT                              Fld(1, 4) //[4:4]
+    #define MISC_IMPCAL_IMPBINARY                              Fld(1, 5) //[5:5]
+    #define MISC_IMPCAL_DRV_ECO_OPT                            Fld(1, 10) //[10:10]
+    #define MISC_IMPCAL_IMPCAL_CHGDRV_ECO_OPT                  Fld(1, 11) //[11:11]
+    #define MISC_IMPCAL_IMPCAL_SM_ECO_OPT                      Fld(1, 12) //[12:12]
+    #define MISC_IMPCAL_IMPCAL_ECO_OPT                         Fld(1, 13) //[13:13]
+    #define MISC_IMPCAL_DIS_SUS_CH1_DRV                        Fld(1, 14) //[14:14]
+    #define MISC_IMPCAL_DIS_SUS_CH0_DRV                        Fld(1, 15) //[15:15]
+    #define MISC_IMPCAL_DIS_SHU_DRV                            Fld(1, 16) //[16:16]
+    #define MISC_IMPCAL_IMPCAL_DRVUPDOPT                       Fld(1, 17) //[17:17]
+    #define MISC_IMPCAL_IMPCAL_USING_SYNC                      Fld(1, 18) //[18:18]
+    #define MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV                Fld(1, 19) //[19:19]
+    #define MISC_IMPCAL_IMPCAL_HWSAVE_EN                       Fld(1, 20) //[20:20]
+    #define MISC_IMPCAL_IMPCAL_CALI_ENN                        Fld(1, 21) //[21:21]
+    #define MISC_IMPCAL_IMPCAL_CALI_ENP                        Fld(1, 22) //[22:22]
+    #define MISC_IMPCAL_IMPCAL_CALI_EN                         Fld(1, 23) //[23:23]
+    #define MISC_IMPCAL_IMPCAL_IMPPDN                          Fld(1, 24) //[24:24]
+    #define MISC_IMPCAL_IMPCAL_IMPPDP                          Fld(1, 25) //[25:25]
+    #define MISC_IMPCAL_IMPCAL_NEW_OLD_SL                      Fld(1, 26) //[26:26]
+    #define MISC_IMPCAL_IMPCAL_CMP_DIREC                       Fld(2, 27) //[28:27]
+    #define MISC_IMPCAL_IMPCAL_SWVALUE_EN                      Fld(1, 29) //[29:29]
+    #define MISC_IMPCAL_IMPCAL_EN                              Fld(1, 30) //[30:30]
+    #define MISC_IMPCAL_IMPCAL_HW                              Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_IMPCAL1                                (DDRPHY_AO_BASE_ADDRESS + 0x0548)
+    #define MISC_IMPCAL1_IMPCAL_RSV                            Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_IMPEDAMCE_CTRL1                        (DDRPHY_AO_BASE_ADDRESS + 0x054C)
+    #define MISC_IMPEDAMCE_CTRL1_DQS1_OFF                      Fld(10, 0) //[9:0]
+    #define MISC_IMPEDAMCE_CTRL1_DOS2_OFF                      Fld(10, 10) //[19:10]
+    #define MISC_IMPEDAMCE_CTRL1_DQS1_OFF_SUB                  Fld(2, 28) //[29:28]
+    #define MISC_IMPEDAMCE_CTRL1_DQS2_OFF_SUB                  Fld(2, 30) //[31:30]
+
+#define DDRPHY_REG_MISC_IMPEDAMCE_CTRL2                        (DDRPHY_AO_BASE_ADDRESS + 0x0550)
+    #define MISC_IMPEDAMCE_CTRL2_DQ1_OFF                       Fld(10, 0) //[9:0]
+    #define MISC_IMPEDAMCE_CTRL2_DQ2_OFF                       Fld(10, 10) //[19:10]
+    #define MISC_IMPEDAMCE_CTRL2_DQ1_OFF_SUB                   Fld(2, 28) //[29:28]
+    #define MISC_IMPEDAMCE_CTRL2_DQ2_OFF_SUB                   Fld(2, 30) //[31:30]
+
+#define DDRPHY_REG_MISC_IMPEDAMCE_CTRL3                        (DDRPHY_AO_BASE_ADDRESS + 0x0554)
+    #define MISC_IMPEDAMCE_CTRL3_CMD1_OFF                      Fld(10, 0) //[9:0]
+    #define MISC_IMPEDAMCE_CTRL3_CMD2_OFF                      Fld(10, 10) //[19:10]
+    #define MISC_IMPEDAMCE_CTRL3_CMD1_OFF_SUB                  Fld(2, 28) //[29:28]
+    #define MISC_IMPEDAMCE_CTRL3_CMD2_OFF_SUB                  Fld(2, 30) //[31:30]
+
+#define DDRPHY_REG_MISC_IMPEDAMCE_CTRL4                        (DDRPHY_AO_BASE_ADDRESS + 0x0558)
+    #define MISC_IMPEDAMCE_CTRL4_DQC1_OFF                      Fld(10, 0) //[9:0]
+    #define MISC_IMPEDAMCE_CTRL4_DQC2_OFF                      Fld(10, 10) //[19:10]
+    #define MISC_IMPEDAMCE_CTRL4_DQC1_OFF_SUB                  Fld(2, 28) //[29:28]
+    #define MISC_IMPEDAMCE_CTRL4_DQC2_OFF_SUB                  Fld(2, 30) //[31:30]
+
+#define DDRPHY_REG_MISC_PERIPHER_CTRL2                         (DDRPHY_AO_BASE_ADDRESS + 0x055C)
+    #define MISC_PERIPHER_CTRL2_APB_WRITE_MASK_EN              Fld(1, 0) //[0:0]
+    #define MISC_PERIPHER_CTRL2_R_SW_RXFIFO_RDSEL_BUS          Fld(4, 27) //[30:27]
+    #define MISC_PERIPHER_CTRL2_R_SW_RXFIFO_RDSEL_EN           Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_APB                                    (DDRPHY_AO_BASE_ADDRESS + 0x0560)
+    #define MISC_APB_APB_ARB_SW_KEEP                           Fld(1, 30) //[30:30]
+    #define MISC_APB_SRAM_ARB_SW_KEEP                          Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_EXTLB0                                 (DDRPHY_AO_BASE_ADDRESS + 0x0564)
+    #define MISC_EXTLB0_EXTLB_LFSR_INI_1                       Fld(16, 16) //[31:16]
+    #define MISC_EXTLB0_EXTLB_LFSR_INI_0                       Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB1                                 (DDRPHY_AO_BASE_ADDRESS + 0x0568)
+    #define MISC_EXTLB1_EXTLB_LFSR_INI_3                       Fld(16, 16) //[31:16]
+    #define MISC_EXTLB1_EXTLB_LFSR_INI_2                       Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB2                                 (DDRPHY_AO_BASE_ADDRESS + 0x056C)
+    #define MISC_EXTLB2_EXTLB_LFSR_INI_5                       Fld(16, 16) //[31:16]
+    #define MISC_EXTLB2_EXTLB_LFSR_INI_4                       Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB3                                 (DDRPHY_AO_BASE_ADDRESS + 0x0570)
+    #define MISC_EXTLB3_EXTLB_LFSR_INI_7                       Fld(16, 16) //[31:16]
+    #define MISC_EXTLB3_EXTLB_LFSR_INI_6                       Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB4                                 (DDRPHY_AO_BASE_ADDRESS + 0x0574)
+    #define MISC_EXTLB4_EXTLB_LFSR_INI_9                       Fld(16, 16) //[31:16]
+    #define MISC_EXTLB4_EXTLB_LFSR_INI_8                       Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB5                                 (DDRPHY_AO_BASE_ADDRESS + 0x0578)
+    #define MISC_EXTLB5_EXTLB_LFSR_INI_11                      Fld(16, 16) //[31:16]
+    #define MISC_EXTLB5_EXTLB_LFSR_INI_10                      Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB6                                 (DDRPHY_AO_BASE_ADDRESS + 0x057C)
+    #define MISC_EXTLB6_EXTLB_LFSR_INI_13                      Fld(16, 16) //[31:16]
+    #define MISC_EXTLB6_EXTLB_LFSR_INI_12                      Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB7                                 (DDRPHY_AO_BASE_ADDRESS + 0x0580)
+    #define MISC_EXTLB7_EXTLB_LFSR_INI_15                      Fld(16, 16) //[31:16]
+    #define MISC_EXTLB7_EXTLB_LFSR_INI_14                      Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB8                                 (DDRPHY_AO_BASE_ADDRESS + 0x0584)
+    #define MISC_EXTLB8_EXTLB_LFSR_INI_17                      Fld(16, 16) //[31:16]
+    #define MISC_EXTLB8_EXTLB_LFSR_INI_16                      Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB9                                 (DDRPHY_AO_BASE_ADDRESS + 0x0588)
+    #define MISC_EXTLB9_EXTLB_LFSR_INI_19                      Fld(16, 16) //[31:16]
+    #define MISC_EXTLB9_EXTLB_LFSR_INI_18                      Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB10                                (DDRPHY_AO_BASE_ADDRESS + 0x058C)
+    #define MISC_EXTLB10_EXTLB_LFSR_INI_21                     Fld(16, 16) //[31:16]
+    #define MISC_EXTLB10_EXTLB_LFSR_INI_20                     Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB11                                (DDRPHY_AO_BASE_ADDRESS + 0x0590)
+    #define MISC_EXTLB11_EXTLB_LFSR_INI_23                     Fld(16, 16) //[31:16]
+    #define MISC_EXTLB11_EXTLB_LFSR_INI_22                     Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB12                                (DDRPHY_AO_BASE_ADDRESS + 0x0594)
+    #define MISC_EXTLB12_EXTLB_LFSR_INI_25                     Fld(16, 16) //[31:16]
+    #define MISC_EXTLB12_EXTLB_LFSR_INI_24                     Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB13                                (DDRPHY_AO_BASE_ADDRESS + 0x0598)
+    #define MISC_EXTLB13_EXTLB_LFSR_INI_27                     Fld(16, 16) //[31:16]
+    #define MISC_EXTLB13_EXTLB_LFSR_INI_26                     Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB14                                (DDRPHY_AO_BASE_ADDRESS + 0x059C)
+    #define MISC_EXTLB14_EXTLB_LFSR_INI_29                     Fld(16, 16) //[31:16]
+    #define MISC_EXTLB14_EXTLB_LFSR_INI_28                     Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB15                                (DDRPHY_AO_BASE_ADDRESS + 0x05A0)
+    #define MISC_EXTLB15_EXTLB_LFSR_INI_30                     Fld(16, 0) //[15:0]
+    #define MISC_EXTLB15_EXTLB_LFSR_INI_31                     Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_MISC_EXTLB16                                (DDRPHY_AO_BASE_ADDRESS + 0x05A4)
+    #define MISC_EXTLB16_EXTLB_ODTEN_DQS1_ON                   Fld(1, 27) //[27:27]
+    #define MISC_EXTLB16_EXTLB_ODTEN_DQM1_ON                   Fld(1, 26) //[26:26]
+    #define MISC_EXTLB16_EXTLB_ODTEN_DQB1_ON                   Fld(1, 25) //[25:25]
+    #define MISC_EXTLB16_EXTLB_ODTEN_DQS0_ON                   Fld(1, 24) //[24:24]
+    #define MISC_EXTLB16_EXTLB_ODTEN_DQM0_ON                   Fld(1, 23) //[23:23]
+    #define MISC_EXTLB16_EXTLB_ODTEN_DQB0_ON                   Fld(1, 22) //[22:22]
+    #define MISC_EXTLB16_EXTLB_OE_DQS1_ON                      Fld(1, 21) //[21:21]
+    #define MISC_EXTLB16_EXTLB_OE_DQM1_ON                      Fld(1, 20) //[20:20]
+    #define MISC_EXTLB16_EXTLB_OE_DQB1_ON                      Fld(1, 19) //[19:19]
+    #define MISC_EXTLB16_EXTLB_OE_DQS0_ON                      Fld(1, 18) //[18:18]
+    #define MISC_EXTLB16_EXTLB_OE_DQM0_ON                      Fld(1, 17) //[17:17]
+    #define MISC_EXTLB16_EXTLB_OE_DQB0_ON                      Fld(1, 16) //[16:16]
+    #define MISC_EXTLB16_EXTLB_LFSR_TAP                        Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB17                                (DDRPHY_AO_BASE_ADDRESS + 0x05A8)
+    #define MISC_EXTLB17_EXTLB_RX_LENGTH_M1                    Fld(24, 8) //[31:8]
+    #define MISC_EXTLB17_EXTLB_TX_PRE_ON                       Fld(1, 7) //[7:7]
+    #define MISC_EXTLB17_INTLB_DRDF_CA_MUXSEL                  Fld(1, 5) //[5:5]
+    #define MISC_EXTLB17_INTLB_ARCLK_MUXSEL                    Fld(1, 4) //[4:4]
+    #define MISC_EXTLB17_EXTLB_TX_EN_OTHERCH_SEL               Fld(1, 3) //[3:3]
+    #define MISC_EXTLB17_EXTLB_TX_EN                           Fld(1, 2) //[2:2]
+    #define MISC_EXTLB17_EXTLB_RX_SWRST                        Fld(1, 1) //[1:1]
+    #define MISC_EXTLB17_EXTLB                                 Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_MISC_EXTLB18                                (DDRPHY_AO_BASE_ADDRESS + 0x05AC)
+    #define MISC_EXTLB18_TX_EN_SRC_SEL                         Fld(1, 0) //[0:0]
+    #define MISC_EXTLB18_OTH_TX_EN_SRC_SEL                     Fld(1, 1) //[1:1]
+    #define MISC_EXTLB18_LPBK_DQ_MODE_FOCA                     Fld(1, 3) //[3:3]
+    #define MISC_EXTLB18_LPBK_DQ_TX_MODE                       Fld(1, 4) //[4:4]
+    #define MISC_EXTLB18_LPBK_CA_TX_MODE                       Fld(1, 5) //[5:5]
+    #define MISC_EXTLB18_LPBK_DQ_RX_MODE                       Fld(1, 8) //[8:8]
+    #define MISC_EXTLB18_LPBK_CA_RX_MODE                       Fld(1, 9) //[9:9]
+    #define MISC_EXTLB18_TX_TRIG_SRC_SEL                       Fld(4, 16) //[19:16]
+    #define MISC_EXTLB18_OTH_TX_TRIG_SRC_SEL                   Fld(4, 20) //[23:20]
+
+#define DDRPHY_REG_MISC_EXTLB19                                (DDRPHY_AO_BASE_ADDRESS + 0x05B0)
+    #define MISC_EXTLB19_EXTLB_LFSR_ENABLE                     Fld(1, 0) //[0:0]
+    #define MISC_EXTLB19_EXTLB_SSO_ENABLE                      Fld(1, 1) //[1:1]
+    #define MISC_EXTLB19_EXTLB_XTALK_ENABLE                    Fld(1, 2) //[2:2]
+    #define MISC_EXTLB19_EXTLB_LEADLAG_DBG_ENABLE              Fld(1, 3) //[3:3]
+    #define MISC_EXTLB19_EXTLB_DBG_SEL                         Fld(5, 16) //[20:16]
+    #define MISC_EXTLB19_EXTLB_LFSR_EXTEND_INV                 Fld(1, 21) //[21:21]
+    #define MISC_EXTLB19_LPBK_DC_TOG_MODE                      Fld(1, 23) //[23:23]
+    #define MISC_EXTLB19_LPBK_DC_TOG_TIMER                     Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_EXTLB20                                (DDRPHY_AO_BASE_ADDRESS + 0x05B4)
+    #define MISC_EXTLB20_XTALK_TX_00_TOG_CYCLE                 Fld(4, 0) //[3:0]
+    #define MISC_EXTLB20_XTALK_TX_01_TOG_CYCLE                 Fld(4, 4) //[7:4]
+    #define MISC_EXTLB20_XTALK_TX_02_TOG_CYCLE                 Fld(4, 8) //[11:8]
+    #define MISC_EXTLB20_XTALK_TX_03_TOG_CYCLE                 Fld(4, 12) //[15:12]
+    #define MISC_EXTLB20_XTALK_TX_04_TOG_CYCLE                 Fld(4, 16) //[19:16]
+    #define MISC_EXTLB20_XTALK_TX_05_TOG_CYCLE                 Fld(4, 20) //[23:20]
+    #define MISC_EXTLB20_XTALK_TX_06_TOG_CYCLE                 Fld(4, 24) //[27:24]
+    #define MISC_EXTLB20_XTALK_TX_07_TOG_CYCLE                 Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_EXTLB21                                (DDRPHY_AO_BASE_ADDRESS + 0x05B8)
+    #define MISC_EXTLB21_XTALK_TX_08_TOG_CYCLE                 Fld(4, 0) //[3:0]
+    #define MISC_EXTLB21_XTALK_TX_09_TOG_CYCLE                 Fld(4, 4) //[7:4]
+    #define MISC_EXTLB21_XTALK_TX_10_TOG_CYCLE                 Fld(4, 8) //[11:8]
+    #define MISC_EXTLB21_XTALK_TX_11_TOG_CYCLE                 Fld(4, 12) //[15:12]
+    #define MISC_EXTLB21_XTALK_TX_12_TOG_CYCLE                 Fld(4, 16) //[19:16]
+    #define MISC_EXTLB21_XTALK_TX_13_TOG_CYCLE                 Fld(4, 20) //[23:20]
+    #define MISC_EXTLB21_XTALK_TX_14_TOG_CYCLE                 Fld(4, 24) //[27:24]
+    #define MISC_EXTLB21_XTALK_TX_15_TOG_CYCLE                 Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_EXTLB22                                (DDRPHY_AO_BASE_ADDRESS + 0x05BC)
+    #define MISC_EXTLB22_XTALK_TX_16_TOG_CYCLE                 Fld(4, 0) //[3:0]
+    #define MISC_EXTLB22_XTALK_TX_17_TOG_CYCLE                 Fld(4, 4) //[7:4]
+    #define MISC_EXTLB22_XTALK_TX_18_TOG_CYCLE                 Fld(4, 8) //[11:8]
+    #define MISC_EXTLB22_XTALK_TX_19_TOG_CYCLE                 Fld(4, 12) //[15:12]
+    #define MISC_EXTLB22_XTALK_TX_20_TOG_CYCLE                 Fld(4, 16) //[19:16]
+    #define MISC_EXTLB22_XTALK_TX_21_TOG_CYCLE                 Fld(4, 20) //[23:20]
+    #define MISC_EXTLB22_XTALK_TX_22_TOG_CYCLE                 Fld(4, 24) //[27:24]
+    #define MISC_EXTLB22_XTALK_TX_23_TOG_CYCLE                 Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_EXTLB23                                (DDRPHY_AO_BASE_ADDRESS + 0x05C0)
+    #define MISC_EXTLB23_XTALK_TX_24_TOG_CYCLE                 Fld(4, 0) //[3:0]
+    #define MISC_EXTLB23_XTALK_TX_25_TOG_CYCLE                 Fld(4, 4) //[7:4]
+    #define MISC_EXTLB23_XTALK_TX_26_TOG_CYCLE                 Fld(4, 8) //[11:8]
+    #define MISC_EXTLB23_XTALK_TX_27_TOG_CYCLE                 Fld(4, 12) //[15:12]
+    #define MISC_EXTLB23_XTALK_TX_28_TOG_CYCLE                 Fld(4, 16) //[19:16]
+    #define MISC_EXTLB23_XTALK_TX_29_TOG_CYCLE                 Fld(4, 20) //[23:20]
+    #define MISC_EXTLB23_XTALK_TX_30_TOG_CYCLE                 Fld(4, 24) //[27:24]
+    #define MISC_EXTLB23_XTALK_TX_31_TOG_CYCLE                 Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_EXTLB_RX0                              (DDRPHY_AO_BASE_ADDRESS + 0x05C4)
+    #define MISC_EXTLB_RX0_EXTLB_LFSR_RX_INI_1                 Fld(16, 16) //[31:16]
+    #define MISC_EXTLB_RX0_EXTLB_LFSR_RX_INI_0                 Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB_RX1                              (DDRPHY_AO_BASE_ADDRESS + 0x05C8)
+    #define MISC_EXTLB_RX1_EXTLB_LFSR_RX_INI_3                 Fld(16, 16) //[31:16]
+    #define MISC_EXTLB_RX1_EXTLB_LFSR_RX_INI_2                 Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB_RX2                              (DDRPHY_AO_BASE_ADDRESS + 0x05CC)
+    #define MISC_EXTLB_RX2_EXTLB_LFSR_RX_INI_5                 Fld(16, 16) //[31:16]
+    #define MISC_EXTLB_RX2_EXTLB_LFSR_RX_INI_4                 Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB_RX3                              (DDRPHY_AO_BASE_ADDRESS + 0x05D0)
+    #define MISC_EXTLB_RX3_EXTLB_LFSR_RX_INI_7                 Fld(16, 16) //[31:16]
+    #define MISC_EXTLB_RX3_EXTLB_LFSR_RX_INI_6                 Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB_RX4                              (DDRPHY_AO_BASE_ADDRESS + 0x05D4)
+    #define MISC_EXTLB_RX4_EXTLB_LFSR_RX_INI_9                 Fld(16, 16) //[31:16]
+    #define MISC_EXTLB_RX4_EXTLB_LFSR_RX_INI_8                 Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB_RX5                              (DDRPHY_AO_BASE_ADDRESS + 0x05D8)
+    #define MISC_EXTLB_RX5_EXTLB_LFSR_RX_INI_11                Fld(16, 16) //[31:16]
+    #define MISC_EXTLB_RX5_EXTLB_LFSR_RX_INI_10                Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB_RX6                              (DDRPHY_AO_BASE_ADDRESS + 0x05DC)
+    #define MISC_EXTLB_RX6_EXTLB_LFSR_RX_INI_13                Fld(16, 16) //[31:16]
+    #define MISC_EXTLB_RX6_EXTLB_LFSR_RX_INI_12                Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB_RX7                              (DDRPHY_AO_BASE_ADDRESS + 0x05E0)
+    #define MISC_EXTLB_RX7_EXTLB_LFSR_RX_INI_15                Fld(16, 16) //[31:16]
+    #define MISC_EXTLB_RX7_EXTLB_LFSR_RX_INI_14                Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB_RX8                              (DDRPHY_AO_BASE_ADDRESS + 0x05E4)
+    #define MISC_EXTLB_RX8_EXTLB_LFSR_RX_INI_17                Fld(16, 16) //[31:16]
+    #define MISC_EXTLB_RX8_EXTLB_LFSR_RX_INI_16                Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB_RX9                              (DDRPHY_AO_BASE_ADDRESS + 0x05E8)
+    #define MISC_EXTLB_RX9_EXTLB_LFSR_RX_INI_19                Fld(16, 16) //[31:16]
+    #define MISC_EXTLB_RX9_EXTLB_LFSR_RX_INI_18                Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB_RX10                             (DDRPHY_AO_BASE_ADDRESS + 0x05EC)
+    #define MISC_EXTLB_RX10_EXTLB_LFSR_RX_INI_21               Fld(16, 16) //[31:16]
+    #define MISC_EXTLB_RX10_EXTLB_LFSR_RX_INI_20               Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB_RX11                             (DDRPHY_AO_BASE_ADDRESS + 0x05F0)
+    #define MISC_EXTLB_RX11_EXTLB_LFSR_RX_INI_23               Fld(16, 16) //[31:16]
+    #define MISC_EXTLB_RX11_EXTLB_LFSR_RX_INI_22               Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB_RX12                             (DDRPHY_AO_BASE_ADDRESS + 0x05F4)
+    #define MISC_EXTLB_RX12_EXTLB_LFSR_RX_INI_25               Fld(16, 16) //[31:16]
+    #define MISC_EXTLB_RX12_EXTLB_LFSR_RX_INI_24               Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB_RX13                             (DDRPHY_AO_BASE_ADDRESS + 0x05F8)
+    #define MISC_EXTLB_RX13_EXTLB_LFSR_RX_INI_27               Fld(16, 16) //[31:16]
+    #define MISC_EXTLB_RX13_EXTLB_LFSR_RX_INI_26               Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB_RX14                             (DDRPHY_AO_BASE_ADDRESS + 0x05FC)
+    #define MISC_EXTLB_RX14_EXTLB_LFSR_RX_INI_29               Fld(16, 16) //[31:16]
+    #define MISC_EXTLB_RX14_EXTLB_LFSR_RX_INI_28               Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_EXTLB_RX15                             (DDRPHY_AO_BASE_ADDRESS + 0x0600)
+    #define MISC_EXTLB_RX15_EXTLB_LFSR_RX_INI_30               Fld(16, 0) //[15:0]
+    #define MISC_EXTLB_RX15_EXTLB_LFSR_RX_INI_31               Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_MISC_EXTLB_RX16                             (DDRPHY_AO_BASE_ADDRESS + 0x0604)
+    #define MISC_EXTLB_RX16_EXTLB_RX_GATE_DELSEL_DQB0          Fld(7, 0) //[6:0]
+    #define MISC_EXTLB_RX16_EXTLB_RX_GATE_DELSEL_DQB1          Fld(7, 8) //[14:8]
+    #define MISC_EXTLB_RX16_EXTLB_RX_GATE_DELSEL_CA            Fld(7, 16) //[22:16]
+
+#define DDRPHY_REG_MISC_EXTLB_RX17                             (DDRPHY_AO_BASE_ADDRESS + 0x0608)
+    #define MISC_EXTLB_RX17_XTALK_RX_00_TOG_CYCLE              Fld(4, 0) //[3:0]
+    #define MISC_EXTLB_RX17_XTALK_RX_01_TOG_CYCLE              Fld(4, 4) //[7:4]
+    #define MISC_EXTLB_RX17_XTALK_RX_02_TOG_CYCLE              Fld(4, 8) //[11:8]
+    #define MISC_EXTLB_RX17_XTALK_RX_03_TOG_CYCLE              Fld(4, 12) //[15:12]
+    #define MISC_EXTLB_RX17_XTALK_RX_04_TOG_CYCLE              Fld(4, 16) //[19:16]
+    #define MISC_EXTLB_RX17_XTALK_RX_05_TOG_CYCLE              Fld(4, 20) //[23:20]
+    #define MISC_EXTLB_RX17_XTALK_RX_06_TOG_CYCLE              Fld(4, 24) //[27:24]
+    #define MISC_EXTLB_RX17_XTALK_RX_07_TOG_CYCLE              Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_EXTLB_RX18                             (DDRPHY_AO_BASE_ADDRESS + 0x060C)
+    #define MISC_EXTLB_RX18_XTALK_RX_08_TOG_CYCLE              Fld(4, 0) //[3:0]
+    #define MISC_EXTLB_RX18_XTALK_RX_09_TOG_CYCLE              Fld(4, 4) //[7:4]
+    #define MISC_EXTLB_RX18_XTALK_RX_10_TOG_CYCLE              Fld(4, 8) //[11:8]
+    #define MISC_EXTLB_RX18_XTALK_RX_11_TOG_CYCLE              Fld(4, 12) //[15:12]
+    #define MISC_EXTLB_RX18_XTALK_RX_12_TOG_CYCLE              Fld(4, 16) //[19:16]
+    #define MISC_EXTLB_RX18_XTALK_RX_13_TOG_CYCLE              Fld(4, 20) //[23:20]
+    #define MISC_EXTLB_RX18_XTALK_RX_14_TOG_CYCLE              Fld(4, 24) //[27:24]
+    #define MISC_EXTLB_RX18_XTALK_RX_15_TOG_CYCLE              Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_EXTLB_RX19                             (DDRPHY_AO_BASE_ADDRESS + 0x0610)
+    #define MISC_EXTLB_RX19_XTALK_RX_16_TOG_CYCLE              Fld(4, 0) //[3:0]
+    #define MISC_EXTLB_RX19_XTALK_RX_17_TOG_CYCLE              Fld(4, 4) //[7:4]
+    #define MISC_EXTLB_RX19_XTALK_RX_18_TOG_CYCLE              Fld(4, 8) //[11:8]
+    #define MISC_EXTLB_RX19_XTALK_RX_19_TOG_CYCLE              Fld(4, 12) //[15:12]
+    #define MISC_EXTLB_RX19_XTALK_RX_20_TOG_CYCLE              Fld(4, 16) //[19:16]
+    #define MISC_EXTLB_RX19_XTALK_RX_21_TOG_CYCLE              Fld(4, 20) //[23:20]
+    #define MISC_EXTLB_RX19_XTALK_RX_22_TOG_CYCLE              Fld(4, 24) //[27:24]
+    #define MISC_EXTLB_RX19_XTALK_RX_23_TOG_CYCLE              Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_EXTLB_RX20                             (DDRPHY_AO_BASE_ADDRESS + 0x0614)
+    #define MISC_EXTLB_RX20_XTALK_RX_24_TOG_CYCLE              Fld(4, 0) //[3:0]
+    #define MISC_EXTLB_RX20_XTALK_RX_25_TOG_CYCLE              Fld(4, 4) //[7:4]
+    #define MISC_EXTLB_RX20_XTALK_RX_26_TOG_CYCLE              Fld(4, 8) //[11:8]
+    #define MISC_EXTLB_RX20_XTALK_RX_27_TOG_CYCLE              Fld(4, 12) //[15:12]
+    #define MISC_EXTLB_RX20_XTALK_RX_28_TOG_CYCLE              Fld(4, 16) //[19:16]
+    #define MISC_EXTLB_RX20_XTALK_RX_29_TOG_CYCLE              Fld(4, 20) //[23:20]
+    #define MISC_EXTLB_RX20_XTALK_RX_30_TOG_CYCLE              Fld(4, 24) //[27:24]
+    #define MISC_EXTLB_RX20_XTALK_RX_31_TOG_CYCLE              Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_SRAM_DMA0                              (DDRPHY_AO_BASE_ADDRESS + 0x0618)
+    #define MISC_SRAM_DMA0_SW_DMA_FIRE                         Fld(1, 0) //[0:0]
+    #define MISC_SRAM_DMA0_SW_MODE                             Fld(1, 1) //[1:1]
+    #define MISC_SRAM_DMA0_APB_WR_MODE                         Fld(1, 2) //[2:2]
+    #define MISC_SRAM_DMA0_SRAM_WR_MODE                        Fld(1, 3) //[3:3]
+    #define MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM                   Fld(4, 4) //[7:4]
+    #define MISC_SRAM_DMA0_SW_SHU_LEVEL_APB                    Fld(4, 8) //[11:8]
+    #define MISC_SRAM_DMA0_PENABLE_LAT_RD                      Fld(2, 12) //[13:12]
+    #define MISC_SRAM_DMA0_PENABLE_LAT_WR                      Fld(2, 14) //[15:14]
+    #define MISC_SRAM_DMA0_KEEP_SRAM_ARB_ENA                   Fld(1, 16) //[16:16]
+    #define MISC_SRAM_DMA0_KEEP_APB_ARB_ENA                    Fld(1, 17) //[17:17]
+    #define MISC_SRAM_DMA0_DMA_TIMER_EN                        Fld(1, 18) //[18:18]
+    #define MISC_SRAM_DMA0_EARLY_ACK_ENA                       Fld(1, 20) //[20:20]
+    #define MISC_SRAM_DMA0_SPM_CTR_APB_LEVEL                   Fld(1, 21) //[21:21]
+    #define MISC_SRAM_DMA0_SPM_CTR_RESTORE                     Fld(1, 22) //[22:22]
+    #define MISC_SRAM_DMA0_SW_STEP_EN_MODE                     Fld(1, 23) //[23:23]
+    #define MISC_SRAM_DMA0_DMA_CLK_FORCE_ON                    Fld(1, 24) //[24:24]
+    #define MISC_SRAM_DMA0_DMA_CLK_FORCE_OFF                   Fld(1, 25) //[25:25]
+    #define MISC_SRAM_DMA0_APB_SLV_SEL                         Fld(2, 28) //[29:28]
+
+#define DDRPHY_REG_MISC_SRAM_DMA1                              (DDRPHY_AO_BASE_ADDRESS + 0x061C)
+    #define MISC_SRAM_DMA1_SPM_RESTORE_STEP_EN                 Fld(17, 0) //[16:0]
+    #define MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS                Fld(1, 19) //[19:19]
+    #define MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL                 Fld(4, 20) //[23:20]
+    #define MISC_SRAM_DMA1_PLL_REG_LENGTH                      Fld(7, 24) //[30:24]
+
+#define DDRPHY_REG_MISC_SRAM_DMA2                              (DDRPHY_AO_BASE_ADDRESS + 0x0620)
+    #define MISC_SRAM_DMA2_SW_DMA_STEP_EN                      Fld(17, 0) //[16:0]
+
+#define DDRPHY_REG_MISC_DUTYSCAN1                              (DDRPHY_AO_BASE_ADDRESS + 0x0624)
+    #define MISC_DUTYSCAN1_REG_SW_RST                          Fld(1, 0) //[0:0]
+    #define MISC_DUTYSCAN1_RX_EYE_SCAN_EN                      Fld(1, 1) //[1:1]
+    #define MISC_DUTYSCAN1_RX_MIOCK_JIT_EN                     Fld(1, 2) //[2:2]
+    #define MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN                   Fld(1, 3) //[3:3]
+    #define MISC_DUTYSCAN1_EYESCAN_RD_SEL_OPT                  Fld(1, 4) //[4:4]
+    #define MISC_DUTYSCAN1_DMDQ4BMUX                           Fld(1, 5) //[5:5]
+    #define MISC_DUTYSCAN1_EYESCAN_CHK_OPT                     Fld(1, 6) //[6:6]
+    #define MISC_DUTYSCAN1_EYESCAN_TOG_OPT                     Fld(1, 7) //[7:7]
+    #define MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN                  Fld(1, 8) //[8:8]
+    #define MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN              Fld(1, 9) //[9:9]
+    #define MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN                 Fld(1, 10) //[10:10]
+    #define MISC_DUTYSCAN1_EYESCAN_DQS_OPT                     Fld(1, 11) //[11:11]
+    #define MISC_DUTYSCAN1_DCBLNCEN                            Fld(1, 12) //[12:12]
+    #define MISC_DUTYSCAN1_DCBLNCINS                           Fld(1, 13) //[13:13]
+    #define MISC_DUTYSCAN1_DQSERRCNT_DIS                       Fld(1, 14) //[14:14]
+    #define MISC_DUTYSCAN1_RX_DQ_EYE_SEL                       Fld(4, 16) //[19:16]
+    #define MISC_DUTYSCAN1_RX_DQ_EYE_SEL_B1                    Fld(4, 20) //[23:20]
+    #define MISC_DUTYSCAN1_RX_DQ_EYE_SEL_B2                    Fld(4, 24) //[27:24]
+    #define MISC_DUTYSCAN1_RX_DQ_EYE_SEL_B3                    Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_MIOCK_JIT_MTR                          (DDRPHY_AO_BASE_ADDRESS + 0x0628)
+    #define MISC_MIOCK_JIT_MTR_RX_MIOCK_JIT_LIMIT              Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_JMETER                                 (DDRPHY_AO_BASE_ADDRESS + 0x062C)
+    #define MISC_JMETER_JMTR_EN                                Fld(1, 0) //[0:0]
+    #define MISC_JMETER_JMTRCNT                                Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_MISC_DVFS_EMI_CLK                           (DDRPHY_AO_BASE_ADDRESS + 0x0630)
+    #define MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY            Fld(1, 24) //[24:24]
+    #define MISC_DVFS_EMI_CLK_GATING_EMI_NEW                   Fld(2, 30) //[31:30]
+
+#define DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL                     (DDRPHY_AO_BASE_ADDRESS + 0x0634)
+    #define MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT          Fld(1, 0) //[0:0]
+    #define MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN     Fld(1, 1) //[1:1]
+    #define MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN             Fld(4, 8) //[11:8]
+    #define MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN             Fld(4, 12) //[15:12]
+
+#define DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL                     (DDRPHY_AO_BASE_ADDRESS + 0x0638)
+    #define MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT          Fld(1, 0) //[0:0]
+    #define MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN     Fld(1, 1) //[1:1]
+    #define MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN             Fld(4, 8) //[11:8]
+    #define MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN             Fld(4, 12) //[15:12]
+
+#define DDRPHY_REG_MISC_CTRL0                                  (DDRPHY_AO_BASE_ADDRESS + 0x063C)
+    #define MISC_CTRL0_R_DMDQSIEN_FIFO_EN                      Fld(1, 0) //[0:0]
+    #define MISC_CTRL0_R_DMDQSIEN_DEPTH_HALF                   Fld(1, 1) //[1:1]
+    #define MISC_CTRL0_R_DMSTBEN_SYNCOPT                       Fld(1, 2) //[2:2]
+    #define MISC_CTRL0_R_DMVALID_DLY_OPT                       Fld(1, 4) //[4:4]
+    #define MISC_CTRL0_R_DMVALID_NARROW_IG                     Fld(1, 5) //[5:5]
+    #define MISC_CTRL0_R_DMVALID_DLY                           Fld(3, 8) //[10:8]
+    #define MISC_CTRL0_IMPCAL_CHAB_EN                          Fld(1, 12) //[12:12]
+    #define MISC_CTRL0_IMPCAL_TRACK_DISABLE                    Fld(1, 13) //[13:13]
+    #define MISC_CTRL0_IMPCAL_LP_ECO_OPT                       Fld(1, 18) //[18:18]
+    #define MISC_CTRL0_IMPCAL_CDC_ECO_OPT                      Fld(1, 19) //[19:19]
+    #define MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT                Fld(1, 20) //[20:20]
+    #define MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF                 Fld(1, 27) //[27:27]
+    #define MISC_CTRL0_R_DQS0IEN_DIV4_CK_CG_CTRL               Fld(1, 28) //[28:28]
+    #define MISC_CTRL0_R_DQS1IEN_DIV4_CK_CG_CTRL               Fld(1, 29) //[29:29]
+    #define MISC_CTRL0_R_CLKIEN_DIV4_CK_CG_CTRL                Fld(1, 30) //[30:30]
+    #define MISC_CTRL0_R_STBENCMP_DIV4CK_EN                    Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_CTRL1                                  (DDRPHY_AO_BASE_ADDRESS + 0x0640)
+    #define MISC_CTRL1_R_RK_PINMUXSWAP_EN                      Fld(1, 0) //[0:0]
+    #define MISC_CTRL1_R_DMPHYRST                              Fld(1, 1) //[1:1]
+    #define MISC_CTRL1_R_DM_TX_ARCLK_OE                        Fld(1, 2) //[2:2]
+    #define MISC_CTRL1_R_DM_TX_ARCMD_OE                        Fld(1, 3) //[3:3]
+    #define MISC_CTRL1_R_DMMUXCA                               Fld(1, 6) //[6:6]
+    #define MISC_CTRL1_R_DMARPIDQ_SW                           Fld(1, 7) //[7:7]
+    #define MISC_CTRL1_R_DMPINMUX                              Fld(2, 8) //[9:8]
+    #define MISC_CTRL1_R_DMARPICA_SW_UPDX                      Fld(1, 10) //[10:10]
+    #define MISC_CTRL1_R_DMRRESETB_I_OPT                       Fld(1, 12) //[12:12]
+    #define MISC_CTRL1_R_DMDA_RRESETB_I                        Fld(1, 13) //[13:13]
+    #define MISC_CTRL1_R_DQ2DM_SWAP                            Fld(1, 15) //[15:15]
+    #define MISC_CTRL1_R_DMDRAMCLKEN0                          Fld(4, 16) //[19:16]
+    #define MISC_CTRL1_R_DMDRAMCLKEN1                          Fld(4, 20) //[23:20]
+    #define MISC_CTRL1_R_DMDQSIENCG_EN                         Fld(1, 24) //[24:24]
+    #define MISC_CTRL1_R_DMSTBENCMP_RK_OPT                     Fld(1, 25) //[25:25]
+    #define MISC_CTRL1_R_WL_DOWNSP                             Fld(1, 26) //[26:26]
+    #define MISC_CTRL1_R_DMODTDISOE_A                          Fld(1, 27) //[27:27]
+    #define MISC_CTRL1_R_DMODTDISOE_B                          Fld(1, 28) //[28:28]
+    #define MISC_CTRL1_R_DMODTDISOE_C                          Fld(1, 29) //[29:29]
+    #define MISC_CTRL1_R_DMDA_RRESETB_E                        Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_CTRL2                                  (DDRPHY_AO_BASE_ADDRESS + 0x0644)
+    #define MISC_CTRL2_CLRPLL_SHU_GP                           Fld(2, 0) //[1:0]
+    #define MISC_CTRL2_PHYPLL_SHU_GP                           Fld(2, 2) //[3:2]
+
+#define DDRPHY_REG_MISC_CTRL3                                  (DDRPHY_AO_BASE_ADDRESS + 0x0648)
+    #define MISC_CTRL3_ARPI_CG_CMD_OPT                         Fld(2, 0) //[1:0]
+    #define MISC_CTRL3_ARPI_CG_CLK_OPT                         Fld(2, 2) //[3:2]
+    #define MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT                    Fld(1, 4) //[4:4]
+    #define MISC_CTRL3_ARPI_CG_MCK_CA_OPT                      Fld(1, 5) //[5:5]
+    #define MISC_CTRL3_ARPI_CG_MCTL_CA_OPT                     Fld(1, 6) //[6:6]
+    #define MISC_CTRL3_DDRPHY_MCK_MPDIV_CG_CA_SEL              Fld(2, 8) //[9:8]
+    #define MISC_CTRL3_DRAM_CLK_NEW_CA_EN_SEL                  Fld(4, 12) //[15:12]
+    #define MISC_CTRL3_ARPI_CG_DQ_OPT                          Fld(2, 16) //[17:16]
+    #define MISC_CTRL3_ARPI_CG_DQS_OPT                         Fld(2, 18) //[19:18]
+    #define MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT                    Fld(1, 20) //[20:20]
+    #define MISC_CTRL3_ARPI_CG_MCK_DQ_OPT                      Fld(1, 21) //[21:21]
+    #define MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT                     Fld(1, 22) //[22:22]
+    #define MISC_CTRL3_DDRPHY_MCK_MPDIV_CG_DQ_SEL              Fld(2, 24) //[25:24]
+    #define MISC_CTRL3_R_DDRPHY_COMB_CG_IG                     Fld(1, 26) //[26:26]
+    #define MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG                  Fld(1, 27) //[27:27]
+    #define MISC_CTRL3_DRAM_CLK_NEW_DQ_EN_SEL                  Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_CTRL4                                  (DDRPHY_AO_BASE_ADDRESS + 0x064C)
+    #define MISC_CTRL4_R_OPT2_MPDIV_CG                         Fld(1, 0) //[0:0]
+    #define MISC_CTRL4_R_OPT2_CG_MCK                           Fld(1, 1) //[1:1]
+    #define MISC_CTRL4_R_OPT2_CG_DQM                           Fld(1, 2) //[2:2]
+    #define MISC_CTRL4_R_OPT2_CG_DQS                           Fld(1, 3) //[3:3]
+    #define MISC_CTRL4_R_OPT2_CG_DQ                            Fld(1, 4) //[4:4]
+    #define MISC_CTRL4_R_OPT2_CG_DQSIEN                        Fld(1, 5) //[5:5]
+    #define MISC_CTRL4_R_OPT2_CG_CMD                           Fld(1, 6) //[6:6]
+    #define MISC_CTRL4_R_OPT2_CG_CLK                           Fld(1, 7) //[7:7]
+    #define MISC_CTRL4_R_OPT2_CG_CS                            Fld(1, 8) //[8:8]
+
+#define DDRPHY_REG_MISC_CTRL5                                  (DDRPHY_AO_BASE_ADDRESS + 0x0650)
+    #define MISC_CTRL5_R_SRAM_DELSEL                           Fld(10, 0) //[9:0]
+    #define MISC_CTRL5_R_MBIST_RPREG_LOAD                      Fld(1, 10) //[10:10]
+    #define MISC_CTRL5_R_MBIST_RPREG_SEL                       Fld(1, 11) //[11:11]
+    #define MISC_CTRL5_R_MBIST_RPRSTB                          Fld(1, 12) //[12:12]
+    #define MISC_CTRL5_R_MBIST_MODE                            Fld(1, 13) //[13:13]
+    #define MISC_CTRL5_R_MBIST_BACKGROUND                      Fld(3, 14) //[16:14]
+    #define MISC_CTRL5_R_SLEEP_W                               Fld(1, 17) //[17:17]
+    #define MISC_CTRL5_R_SLEEP_R                               Fld(1, 18) //[18:18]
+    #define MISC_CTRL5_R_SLEEP_INV                             Fld(1, 19) //[19:19]
+    #define MISC_CTRL5_R_SLEEP_TEST                            Fld(1, 20) //[20:20]
+    #define MISC_CTRL5_R_MBIST_HOLDB                           Fld(1, 21) //[21:21]
+    #define MISC_CTRL5_R_CS_MARK                               Fld(1, 22) //[22:22]
+    #define MISC_CTRL5_MBIST_RSTB                              Fld(1, 23) //[23:23]
+    #define MISC_CTRL5_R_SPM_SRAM_SLP_MSK                      Fld(1, 24) //[24:24]
+    #define MISC_CTRL5_R_SRAM_HDEN                             Fld(1, 25) //[25:25]
+    #define MISC_CTRL5_R_SRAM_ISOINTB                          Fld(1, 26) //[26:26]
+    #define MISC_CTRL5_R_SRAM_SLEEPB                           Fld(1, 27) //[27:27]
+    #define MISC_CTRL5_R_USE_DEFAULT_DESLSEL                   Fld(1, 28) //[28:28]
+
+#define DDRPHY_REG_MISC_CTRL6                                  (DDRPHY_AO_BASE_ADDRESS + 0x0654)
+    #define MISC_CTRL6_RG_PHDET_EN_SHU_OPT                     Fld(1, 0) //[0:0]
+    #define MISC_CTRL6_RG_ADA_MCK8X_EN_SHU_OPT                 Fld(1, 1) //[1:1]
+    #define MISC_CTRL6_R_SRAM_DELSEL_1                         Fld(10, 16) //[25:16]
+
+#define DDRPHY_REG_MISC_VREF_CTRL                              (DDRPHY_AO_BASE_ADDRESS + 0x0658)
+    #define MISC_VREF_CTRL_VREF_CTRL_RFU                       Fld(15, 16) //[30:16]
+    #define MISC_VREF_CTRL_RG_RVREF_VREF_EN                    Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_SHU_OPT                                (DDRPHY_AO_BASE_ADDRESS + 0x065C)
+    #define MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN   Fld(1, 0) //[0:0]
+    #define MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN               Fld(2, 2) //[3:2]
+    #define MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN   Fld(1, 8) //[8:8]
+    #define MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN               Fld(2, 10) //[11:10]
+    #define MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN     Fld(1, 16) //[16:16]
+    #define MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN                 Fld(2, 18) //[19:18]
+
+#define DDRPHY_REG_MISC_RXDVS0                                 (DDRPHY_AO_BASE_ADDRESS + 0x0660)
+    #define MISC_RXDVS0_R_RX_DLY_TRACK_RO_SEL                  Fld(3, 0) //[2:0]
+    #define MISC_RXDVS0_R_DA_DQX_R_DLY_RO_SEL                  Fld(4, 8) //[11:8]
+    #define MISC_RXDVS0_R_DA_CAX_R_DLY_RO_SEL                  Fld(4, 12) //[15:12]
+
+#define DDRPHY_REG_MISC_RXDVS2                                 (DDRPHY_AO_BASE_ADDRESS + 0x0664)
+    #define MISC_RXDVS2_R_DMRXDVS_DEPTH_HALF                   Fld(1, 0) //[0:0]
+    #define MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG           Fld(1, 8) //[8:8]
+    #define MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN                   Fld(1, 16) //[16:16]
+    #define MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR                  Fld(1, 17) //[17:17]
+    #define MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN                 Fld(1, 18) //[18:18]
+
+#define DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0                      (DDRPHY_AO_BASE_ADDRESS + 0x0668)
+    #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_GO             Fld(1, 0) //[0:0]
+    #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_B0_EN          Fld(1, 1) //[1:1]
+    #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_B1_EN          Fld(1, 2) //[2:2]
+    #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_CA_EN          Fld(1, 3) //[3:3]
+    #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_DEBUG_MODE_EN  Fld(1, 4) //[4:4]
+    #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_EARLY_BREAK_EN Fld(1, 5) //[5:5]
+    #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_CUR_RANK       Fld(1, 6) //[6:6]
+    #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_PI_OFFSET      Fld(2, 8) //[9:8]
+    #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_BURST_LENGTH   Fld(2, 10) //[11:10]
+    #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_SW_RST         Fld(1, 12) //[12:12]
+    #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK0_SW_RST     Fld(1, 13) //[13:13]
+    #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK1_SW_RST     Fld(1, 14) //[14:14]
+    #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_END__UI        Fld(4, 16) //[19:16]
+    #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_END_MCK        Fld(4, 20) //[23:20]
+    #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_INI__UI        Fld(4, 24) //[27:24]
+    #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_INI_MCK        Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_DLINE_MON_CFG                          (DDRPHY_AO_BASE_ADDRESS + 0x066C)
+    #define MISC_DLINE_MON_CFG_DLINE_MON_TRACK_EN              Fld(1, 0) //[0:0]
+    #define MISC_DLINE_MON_CFG_FORCE_DLINE_MON_EN              Fld(1, 1) //[1:1]
+    #define MISC_DLINE_MON_CFG_FORCE_UDP_DLY_VAL               Fld(1, 2) //[2:2]
+    #define MISC_DLINE_MON_CFG_MON_DLY_OUT                     Fld(4, 4) //[7:4]
+    #define MISC_DLINE_MON_CFG_RX_UDP_EN                       Fld(1, 8) //[8:8]
+    #define MISC_DLINE_MON_CFG_TX_UDP_EN                       Fld(1, 9) //[9:9]
+    #define MISC_DLINE_MON_CFG_DLINE_MON_TRACK_CG_EN           Fld(1, 10) //[10:10]
+
+#define DDRPHY_REG_MISC_RX_AUTOK_CFG0                          (DDRPHY_AO_BASE_ADDRESS + 0x0670)
+    #define MISC_RX_AUTOK_CFG0_RX_CAL_START                    Fld(1, 0) //[0:0]
+    #define MISC_RX_AUTOK_CFG0_RX_CAL_BREAK                    Fld(1, 1) //[1:1]
+    #define MISC_RX_AUTOK_CFG0_RX_CAL_CLEAR                    Fld(1, 2) //[2:2]
+    #define MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN                    Fld(1, 3) //[3:3]
+    #define MISC_RX_AUTOK_CFG0_RX_CAL_BEGIN                    Fld(11, 4) //[14:4]
+    #define MISC_RX_AUTOK_CFG0_RX_CAL_LEN                      Fld(10, 16) //[25:16]
+    #define MISC_RX_AUTOK_CFG0_RX_CAL_STEP                     Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_RX_AUTOK_CFG1                          (DDRPHY_AO_BASE_ADDRESS + 0x0674)
+    #define MISC_RX_AUTOK_CFG1_RX_CAL_OUT_DBG_EN               Fld(1, 0) //[0:0]
+    #define MISC_RX_AUTOK_CFG1_RX_CAL_OUT_DBG_SEL              Fld(4, 4) //[7:4]
+
+#define DDRPHY_REG_MISC_DBG_IRQ_CTRL0                          (DDRPHY_AO_BASE_ADDRESS + 0x0680)
+    #define MISC_DBG_IRQ_CTRL0_DBG_DB_SW_RST                   Fld(1, 0) //[0:0]
+    #define MISC_DBG_IRQ_CTRL0_DBG_DB_IRQ_RST_EN               Fld(1, 1) //[1:1]
+    #define MISC_DBG_IRQ_CTRL0_IRQ_CK_FRUN                     Fld(1, 4) //[4:4]
+
+#define DDRPHY_REG_MISC_DBG_IRQ_CTRL1                          (DDRPHY_AO_BASE_ADDRESS + 0x0684)
+    #define MISC_DBG_IRQ_CTRL1_REFRATE_EN                      Fld(1, 0) //[0:0]
+    #define MISC_DBG_IRQ_CTRL1_REFPENDING_EN                   Fld(1, 1) //[1:1]
+    #define MISC_DBG_IRQ_CTRL1_PRE_REFRATE_EN                  Fld(1, 2) //[2:2]
+    #define MISC_DBG_IRQ_CTRL1_RTMRW_ABNORMAL_STOP_EN          Fld(1, 3) //[3:3]
+    #define MISC_DBG_IRQ_CTRL1_SREF_REQ_NO_ACK_EN              Fld(1, 6) //[6:6]
+    #define MISC_DBG_IRQ_CTRL1_SREF_REQ_SHORT_EN               Fld(1, 7) //[7:7]
+    #define MISC_DBG_IRQ_CTRL1_SREF_REQ_DTRIG_EN               Fld(1, 8) //[8:8]
+    #define MISC_DBG_IRQ_CTRL1_RTSWCMD_NONVALIDCMD_EN          Fld(1, 12) //[12:12]
+    #define MISC_DBG_IRQ_CTRL1_TX_TRACKING1_EN                 Fld(1, 16) //[16:16]
+    #define MISC_DBG_IRQ_CTRL1_TX_TRACKING2_EN                 Fld(1, 17) //[17:17]
+    #define MISC_DBG_IRQ_CTRL1_DBG_DRAMC_IRQ_EN_0              Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DBG_IRQ_CTRL2                          (DDRPHY_AO_BASE_ADDRESS + 0x0688)
+    #define MISC_DBG_IRQ_CTRL2_REFRATE_POL                     Fld(1, 0) //[0:0]
+    #define MISC_DBG_IRQ_CTRL2_REFPENDING_POL                  Fld(1, 1) //[1:1]
+    #define MISC_DBG_IRQ_CTRL2_PRE_REFRATE_POL                 Fld(1, 2) //[2:2]
+    #define MISC_DBG_IRQ_CTRL2_RTMRW_ABNORMAL_STOP_POL         Fld(1, 3) //[3:3]
+    #define MISC_DBG_IRQ_CTRL2_SREF_REQ_NO_ACK_POL             Fld(1, 6) //[6:6]
+    #define MISC_DBG_IRQ_CTRL2_SREF_REQ_SHORT_POL              Fld(1, 7) //[7:7]
+    #define MISC_DBG_IRQ_CTRL2_SREF_REQ_DTRIG_POL              Fld(1, 8) //[8:8]
+    #define MISC_DBG_IRQ_CTRL2_RTSWCMD_NONVALIDCMD_POL         Fld(1, 12) //[12:12]
+    #define MISC_DBG_IRQ_CTRL2_TX_TRACKING1_POL                Fld(1, 16) //[16:16]
+    #define MISC_DBG_IRQ_CTRL2_TX_TRACKING2_POL                Fld(1, 17) //[17:17]
+    #define MISC_DBG_IRQ_CTRL2_DBG_DRAMC_IRQ_POL_0             Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DBG_IRQ_CTRL3                          (DDRPHY_AO_BASE_ADDRESS + 0x068C)
+    #define MISC_DBG_IRQ_CTRL3_REFRATE_CLEAN                   Fld(1, 0) //[0:0]
+    #define MISC_DBG_IRQ_CTRL3_REFPENDING_CLEAN                Fld(1, 1) //[1:1]
+    #define MISC_DBG_IRQ_CTRL3_PRE_REFRATE_CLEAN               Fld(1, 2) //[2:2]
+    #define MISC_DBG_IRQ_CTRL3_RTMRW_ABNORMAL_STOP_CLEAN       Fld(1, 3) //[3:3]
+    #define MISC_DBG_IRQ_CTRL3_SREF_REQ_NO_ACK_CLEAN           Fld(1, 6) //[6:6]
+    #define MISC_DBG_IRQ_CTRL3_SREF_REQ_SHORT_CLEAN            Fld(1, 7) //[7:7]
+    #define MISC_DBG_IRQ_CTRL3_SREF_REQ_DTRIG_CLEAN            Fld(1, 8) //[8:8]
+    #define MISC_DBG_IRQ_CTRL3_RTSWCMD_NONVALIDCMD_CLEAN       Fld(1, 12) //[12:12]
+    #define MISC_DBG_IRQ_CTRL3_TX_TRACKING1_CLEAN              Fld(1, 16) //[16:16]
+    #define MISC_DBG_IRQ_CTRL3_TX_TRACKING2_CLEAN              Fld(1, 17) //[17:17]
+    #define MISC_DBG_IRQ_CTRL3_DBG_DRAMC_IRQ_CLEAN_0           Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DBG_IRQ_CTRL4                          (DDRPHY_AO_BASE_ADDRESS + 0x0690)
+    #define MISC_DBG_IRQ_CTRL4_DBG_DRAMC_IRQ_EN_1              Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DBG_IRQ_CTRL5                          (DDRPHY_AO_BASE_ADDRESS + 0x0694)
+    #define MISC_DBG_IRQ_CTRL5_DBG_DRAMC_IRQ_POL_1             Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DBG_IRQ_CTRL6                          (DDRPHY_AO_BASE_ADDRESS + 0x0698)
+    #define MISC_DBG_IRQ_CTRL6_DBG_DRAMC_IRQ_CLEAN_1           Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DBG_IRQ_CTRL7                          (DDRPHY_AO_BASE_ADDRESS + 0x069C)
+    #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK1_B0_EN            Fld(1, 0)  //[0:0]
+    #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK0_B0_EN            Fld(1, 1)  //[1:1]
+    #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK1_B1_EN            Fld(1, 2)  //[2:2]
+    #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK0_B1_EN            Fld(1, 3)  //[3:3]
+    #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK1_CA_EN            Fld(1, 4)  //[4:4]
+    #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK0_CA_EN            Fld(1, 5)  //[5:5]
+    #define MISC_DBG_IRQ_CTRL7_STB_GATTING_ERR_EN                   Fld(1, 7)  //[7:7]
+    #define MISC_DBG_IRQ_CTRL7_RX_ARDQ0_FIFO_STBEN_ERR_B0_EN        Fld(1, 8)  //[8:8]
+    #define MISC_DBG_IRQ_CTRL7_RX_ARDQ4_FIFO_STBEN_ERR_B0_EN        Fld(1, 9)  //[9:9]
+    #define MISC_DBG_IRQ_CTRL7_RX_ARDQ0_FIFO_STBEN_ERR_B1_EN        Fld(1, 10)  //[10:10]
+    #define MISC_DBG_IRQ_CTRL7_RX_ARDQ4_FIFO_STBEN_ERR_B1_EN        Fld(1, 11)  //[11:11]
+    #define MISC_DBG_IRQ_CTRL7_TRACKING_STATUS_ERR_RISING_R1_B1_EN  Fld(1, 12)  //[12:12]
+    #define MISC_DBG_IRQ_CTRL7_TRACKING_STATUS_ERR_RISING_R1_B0_EN  Fld(1, 13)  //[13:13]
+    #define MISC_DBG_IRQ_CTRL7_TRACKING_STATUS_ERR_RISING_R0_B1_EN  Fld(1, 14)  //[14:14]
+    #define MISC_DBG_IRQ_CTRL7_TRACKING_STATUS_ERR_RISING_R0_B0_EN  Fld(1, 15)  //[15:15]
+    #define MISC_DBG_IRQ_CTRL7_IMP_CLK_ERR_EN                       Fld(1, 24)  //[24:24]
+    #define MISC_DBG_IRQ_CTRL7_IMP_CMD_ERR_EN                       Fld(1, 25)  //[25:25]
+    #define MISC_DBG_IRQ_CTRL7_IMP_DQ1_ERR_EN                       Fld(1, 26)  //[26:26]
+    #define MISC_DBG_IRQ_CTRL7_IMP_DQ0_ERR_EN                       Fld(1, 27)  //[27:27]
+    #define MISC_DBG_IRQ_CTRL7_IMP_DQS_ERR_EN                       Fld(1, 28)  //[28:28]
+    #define MISC_DBG_IRQ_CTRL7_IMP_ODTN_ERR_EN                      Fld(1, 29)  //[29:29]
+    #define MISC_DBG_IRQ_CTRL7_IMP_DRVN_ERR_EN                      Fld(1, 30)  //[30:30]
+    #define MISC_DBG_IRQ_CTRL7_IMP_DRVP_ERR_EN                      Fld(1, 31)  //[31:31]
+    #define MISC_DBG_IRQ_CTRL7_DBG_DRAMP_IRQ_EN_0                   Fld(32, 0)  //[31:0]
+
+#define DDRPHY_REG_MISC_DBG_IRQ_CTRL8                          (DDRPHY_AO_BASE_ADDRESS + 0x06A0)
+    #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK1_B0_POL           Fld(1, 0)  //[0:0]
+    #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK0_B0_POL           Fld(1, 1)  //[1:1]
+    #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK1_B1_POL           Fld(1, 2)  //[2:2]
+    #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK0_B1_POL           Fld(1, 3)  //[3:3]
+    #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK1_CA_POL           Fld(1, 4)  //[4:4]
+    #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK0_CA_POL           Fld(1, 5)  //[5:5]
+    #define MISC_DBG_IRQ_CTRL8_STB_GATTING_ERR_POL                  Fld(1, 7)  //[7:7]
+    #define MISC_DBG_IRQ_CTRL8_RX_ARDQ0_FIFO_STBEN_ERR_B0_POL       Fld(1, 8)  //[8:8]
+    #define MISC_DBG_IRQ_CTRL8_RX_ARDQ4_FIFO_STBEN_ERR_B0_POL       Fld(1, 9)  //[9:9]
+    #define MISC_DBG_IRQ_CTRL8_RX_ARDQ0_FIFO_STBEN_ERR_B1_POL       Fld(1, 10)  //[10:10]
+    #define MISC_DBG_IRQ_CTRL8_RX_ARDQ4_FIFO_STBEN_ERR_B1_POL       Fld(1, 11)  //[11:11]
+    #define MISC_DBG_IRQ_CTRL8_TRACKING_STATUS_ERR_RISING_R1_B1_POL Fld(1, 12)  //[12:12]
+    #define MISC_DBG_IRQ_CTRL8_TRACKING_STATUS_ERR_RISING_R1_B0_POL Fld(1, 13)  //[13:13]
+    #define MISC_DBG_IRQ_CTRL8_TRACKING_STATUS_ERR_RISING_R0_B1_POL Fld(1, 14)  //[14:14]
+    #define MISC_DBG_IRQ_CTRL8_TRACKING_STATUS_ERR_RISING_R0_B0_POL Fld(1, 15)  //[15:15]
+    #define MISC_DBG_IRQ_CTRL8_IMP_CLK_ERR_POL                      Fld(1, 24)  //[24:24]
+    #define MISC_DBG_IRQ_CTRL8_IMP_CMD_ERR_POL                      Fld(1, 25)  //[25:25]
+    #define MISC_DBG_IRQ_CTRL8_IMP_DQ1_ERR_POL                      Fld(1, 26)  //[26:26]
+    #define MISC_DBG_IRQ_CTRL8_IMP_DQ0_ERR_POL                      Fld(1, 27)  //[27:27]
+    #define MISC_DBG_IRQ_CTRL8_IMP_DQS_ERR_POL                      Fld(1, 28)  //[28:28]
+    #define MISC_DBG_IRQ_CTRL8_IMP_ODTN_ERR_POL                     Fld(1, 29)  //[29:29]
+    #define MISC_DBG_IRQ_CTRL8_IMP_DRVN_ERR_POL                     Fld(1, 30)  //[30:30]
+    #define MISC_DBG_IRQ_CTRL8_IMP_DRVP_ERR_POL                     Fld(1, 31)  //[31:31]
+    #define MISC_DBG_IRQ_CTRL8_DBG_DRAMP_IRQ_POL_0                  Fld(32, 0)  //[31:0]
+
+#define DDRPHY_REG_MISC_DBG_IRQ_CTRL9                          (DDRPHY_AO_BASE_ADDRESS + 0x06A4)
+    #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK1_B0_CLEAN           Fld(1, 0)  //[0:0]
+    #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK0_B0_CLEAN           Fld(1, 1)  //[1:1]
+    #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK1_B1_CLEAN           Fld(1, 2)  //[2:2]
+    #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK0_B1_CLEAN           Fld(1, 3)  //[3:3]
+    #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK1_CA_CLEAN           Fld(1, 4)  //[4:4]
+    #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK0_CA_CLEAN           Fld(1, 5)  //[5:5]
+    #define MISC_DBG_IRQ_CTRL9_STB_GATTING_ERR_CLEAN                  Fld(1, 7)  //[7:7]
+    #define MISC_DBG_IRQ_CTRL9_RX_ARDQ0_FIFO_STBEN_ERR_B0_CLEAN       Fld(1, 8)  //[8:8]
+    #define MISC_DBG_IRQ_CTRL9_RX_ARDQ4_FIFO_STBEN_ERR_B0_CLEAN       Fld(1, 9)  //[9:9]
+    #define MISC_DBG_IRQ_CTRL9_RX_ARDQ0_FIFO_STBEN_ERR_B1_CLEAN       Fld(1, 10)  //[10:10]
+    #define MISC_DBG_IRQ_CTRL9_RX_ARDQ4_FIFO_STBEN_ERR_B1_CLEAN       Fld(1, 11)  //[11:11]
+    #define MISC_DBG_IRQ_CTRL9_TRACKING_STATUS_ERR_RISING_R1_B1_CLEAN Fld(1, 12)  //[12:12]
+    #define MISC_DBG_IRQ_CTRL9_TRACKING_STATUS_ERR_RISING_R1_B0_CLEAN Fld(1, 13)  //[13:13]
+    #define MISC_DBG_IRQ_CTRL9_TRACKING_STATUS_ERR_RISING_R0_B1_CLEAN Fld(1, 14)  //[14:14]
+    #define MISC_DBG_IRQ_CTRL9_TRACKING_STATUS_ERR_RISING_R0_B0_CLEAN Fld(1, 15)  //[15:15]
+    #define MISC_DBG_IRQ_CTRL9_IMP_CLK_ERR_CLEAN                      Fld(1, 24)  //[24:24]
+    #define MISC_DBG_IRQ_CTRL9_IMP_CMD_ERR_CLEAN                      Fld(1, 25)  //[25:25]
+    #define MISC_DBG_IRQ_CTRL9_IMP_DQ1_ERR_CLEAN                      Fld(1, 26)  //[26:26]
+    #define MISC_DBG_IRQ_CTRL9_IMP_DQ0_ERR_CLEAN                      Fld(1, 27)  //[27:27]
+    #define MISC_DBG_IRQ_CTRL9_IMP_DQS_ERR_CLEAN                      Fld(1, 28)  //[28:28]
+    #define MISC_DBG_IRQ_CTRL9_IMP_ODTN_ERR_CLEAN                     Fld(1, 29)  //[29:29]
+    #define MISC_DBG_IRQ_CTRL9_IMP_DRVN_ERR_CLEAN                     Fld(1, 30)  //[30:30]
+    #define MISC_DBG_IRQ_CTRL9_IMP_DRVP_ERR_CLEAN                     Fld(1, 31)  //[31:31]
+    #define MISC_DBG_IRQ_CTRL9_DBG_DRAMP_IRQ_CLEAN_0                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL0                     (DDRPHY_AO_BASE_ADDRESS + 0x06B0)
+    #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0          Fld(4, 0) //[3:0]
+    #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1          Fld(4, 4) //[7:4]
+    #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2          Fld(4, 8) //[11:8]
+    #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ3          Fld(4, 12) //[15:12]
+    #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ4          Fld(4, 16) //[19:16]
+    #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ5          Fld(4, 20) //[23:20]
+    #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ6          Fld(4, 24) //[27:24]
+    #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ7          Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL1                     (DDRPHY_AO_BASE_ADDRESS + 0x06B4)
+    #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ8          Fld(4, 0) //[3:0]
+    #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ9          Fld(4, 4) //[7:4]
+    #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ10         Fld(4, 8) //[11:8]
+    #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ11         Fld(4, 12) //[15:12]
+    #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ12         Fld(4, 16) //[19:16]
+    #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ13         Fld(4, 20) //[23:20]
+    #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ14         Fld(4, 24) //[27:24]
+    #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15         Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_BIST_LPBK_CTRL0                        (DDRPHY_AO_BASE_ADDRESS + 0x06C0)
+    #define MISC_BIST_LPBK_CTRL0_BIST_EN                       Fld(1, 0) //[0:0]
+    #define MISC_BIST_LPBK_CTRL0_BIST_TA2_LPBK_MODE            Fld(1, 1) //[1:1]
+    #define MISC_BIST_LPBK_CTRL0_BIST_RX_LPBK_MODE             Fld(1, 2) //[2:2]
+    #define MISC_BIST_LPBK_CTRL0_BIST_DSEL_MODE                Fld(1, 3) //[3:3]
+    #define MISC_BIST_LPBK_CTRL0_BIST_TX_DQSINCTL              Fld(4, 12) //[15:12]
+    #define MISC_BIST_LPBK_CTRL0_BIST_SEDA_LPBK_DSEL_RW        Fld(5, 16) //[20:16]
+    #define MISC_BIST_LPBK_CTRL0_BIST_SEDA_LPBK_DLE_RW         Fld(5, 24) //[28:24]
+
+#define DDRPHY_REG_SHU_PHYPLL0                                 (DDRPHY_AO_BASE_ADDRESS + 0x0700)
+    #define SHU_PHYPLL0_RG_RPHYPLL_RESERVED                    Fld(16, 0) //[15:0]
+    #define SHU_PHYPLL0_RG_RPHYPLL_FS                          Fld(2, 18) //[19:18]
+    #define SHU_PHYPLL0_RG_RPHYPLL_BW                          Fld(3, 20) //[22:20]
+    #define SHU_PHYPLL0_RG_RPHYPLL_ICHP                        Fld(2, 24) //[25:24]
+    #define SHU_PHYPLL0_RG_RPHYPLL_IBIAS                       Fld(2, 26) //[27:26]
+    #define SHU_PHYPLL0_RG_RPHYPLL_BLP                         Fld(1, 29) //[29:29]
+    #define SHU_PHYPLL0_RG_RPHYPLL_BR                          Fld(1, 30) //[30:30]
+    #define SHU_PHYPLL0_RG_RPHYPLL_BP                          Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_PHYPLL1                                 (DDRPHY_AO_BASE_ADDRESS + 0x0704)
+    #define SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN                  Fld(1, 0) //[0:0]
+    #define SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG                 Fld(1, 1) //[1:1]
+    #define SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW                     Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_SHU_PHYPLL2                                 (DDRPHY_AO_BASE_ADDRESS + 0x0708)
+    #define SHU_PHYPLL2_RG_RPHYPLL_POSDIV                      Fld(3, 0) //[2:0]
+    #define SHU_PHYPLL2_RG_RPHYPLL_PREDIV                      Fld(2, 18) //[19:18]
+
+#define DDRPHY_REG_SHU_PHYPLL3                                 (DDRPHY_AO_BASE_ADDRESS + 0x070C)
+    #define SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL                  Fld(1, 0) //[0:0]
+    #define SHU_PHYPLL3_RG_RPHYPLL_GLITCH_FREE_EN              Fld(1, 1) //[1:1]
+    #define SHU_PHYPLL3_RG_RPHYPLL_LVR_REFSEL                  Fld(2, 2) //[3:2]
+    #define SHU_PHYPLL3_RG_RPHYPLL_DIV3_EN                     Fld(1, 4) //[4:4]
+    #define SHU_PHYPLL3_RG_RPHYPLL_FS_EN                       Fld(1, 5) //[5:5]
+    #define SHU_PHYPLL3_RG_RPHYPLL_FBKSEL                      Fld(1, 6) //[6:6]
+    #define SHU_PHYPLL3_RG_RPHYPLL_RST_DLY                     Fld(2, 8) //[9:8]
+    #define SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN                    Fld(1, 12) //[12:12]
+    #define SHU_PHYPLL3_RG_RPHYPLL_MONREF_EN                   Fld(1, 13) //[13:13]
+    #define SHU_PHYPLL3_RG_RPHYPLL_MONVC_EN                    Fld(2, 14) //[15:14]
+    #define SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN                    Fld(1, 16) //[16:16]
+
+#define DDRPHY_REG_SHU_PHYPLL4                                 (DDRPHY_AO_BASE_ADDRESS + 0x0710)
+    #define SHU_PHYPLL4_RG_RPHYPLL_EXT_FBDIV                   Fld(6, 0) //[5:0]
+    #define SHU_PHYPLL4_RG_RPHYPLL_EXTFBDIV_EN                 Fld(1, 8) //[8:8]
+
+#define DDRPHY_REG_SHU_PHYPLL5                                 (DDRPHY_AO_BASE_ADDRESS + 0x0714)
+    #define SHU_PHYPLL5_RG_RPHYPLL_FB_DL                       Fld(6, 0) //[5:0]
+    #define SHU_PHYPLL5_RG_RPHYPLL_REF_DL                      Fld(6, 8) //[13:8]
+
+#define DDRPHY_REG_SHU_PHYPLL6                                 (DDRPHY_AO_BASE_ADDRESS + 0x0718)
+    #define SHU_PHYPLL6_RG_RPHYPLL_SDM_HREN                    Fld(1, 0) //[0:0]
+    #define SHU_PHYPLL6_RG_RPHYPLL_SDM_SSC_PH_INIT             Fld(1, 1) //[1:1]
+    #define SHU_PHYPLL6_RG_RPHYPLL_SDM_SSC_PRD                 Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_SHU_PHYPLL7                                 (DDRPHY_AO_BASE_ADDRESS + 0x071C)
+    #define SHU_PHYPLL7_RG_RPHYPLL_SDM_SSC_DELTA               Fld(16, 0) //[15:0]
+    #define SHU_PHYPLL7_RG_RPHYPLL_SDM_SSC_DELTA1              Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_SHU_CLRPLL0                                 (DDRPHY_AO_BASE_ADDRESS + 0x0720)
+    #define SHU_CLRPLL0_RG_RCLRPLL_RESERVED                    Fld(16, 0) //[15:0]
+    #define SHU_CLRPLL0_RG_RCLRPLL_FS                          Fld(2, 18) //[19:18]
+    #define SHU_CLRPLL0_RG_RCLRPLL_BW                          Fld(3, 20) //[22:20]
+    #define SHU_CLRPLL0_RG_RCLRPLL_ICHP                        Fld(2, 24) //[25:24]
+    #define SHU_CLRPLL0_RG_RCLRPLL_IBIAS                       Fld(2, 26) //[27:26]
+    #define SHU_CLRPLL0_RG_RCLRPLL_BLP                         Fld(1, 29) //[29:29]
+    #define SHU_CLRPLL0_RG_RCLRPLL_BR                          Fld(1, 30) //[30:30]
+    #define SHU_CLRPLL0_RG_RCLRPLL_BP                          Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_CLRPLL1                                 (DDRPHY_AO_BASE_ADDRESS + 0x0724)
+    #define SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN                  Fld(1, 0) //[0:0]
+    #define SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG                 Fld(1, 1) //[1:1]
+    #define SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW                     Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_SHU_CLRPLL2                                 (DDRPHY_AO_BASE_ADDRESS + 0x0728)
+    #define SHU_CLRPLL2_RG_RCLRPLL_POSDIV                      Fld(3, 0) //[2:0]
+    #define SHU_CLRPLL2_RG_RCLRPLL_PREDIV                      Fld(2, 18) //[19:18]
+
+#define DDRPHY_REG_SHU_CLRPLL3                                 (DDRPHY_AO_BASE_ADDRESS + 0x072C)
+    #define SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL                  Fld(1, 0) //[0:0]
+    #define SHU_CLRPLL3_RG_RCLRPLL_GLITCH_FREE_EN              Fld(1, 1) //[1:1]
+    #define SHU_CLRPLL3_RG_RCLRPLL_LVR_REFSEL                  Fld(2, 2) //[3:2]
+    #define SHU_CLRPLL3_RG_RCLRPLL_DIV3_EN                     Fld(1, 4) //[4:4]
+    #define SHU_CLRPLL3_RG_RCLRPLL_FS_EN                       Fld(1, 5) //[5:5]
+    #define SHU_CLRPLL3_RG_RCLRPLL_FBKSEL                      Fld(1, 6) //[6:6]
+    #define SHU_CLRPLL3_RG_RCLRPLL_RST_DLY                     Fld(2, 8) //[9:8]
+    #define SHU_CLRPLL3_RG_RCLRPLL_LVROD_EN                    Fld(1, 12) //[12:12]
+    #define SHU_CLRPLL3_RG_RCLRPLL_MONREF_EN                   Fld(1, 13) //[13:13]
+    #define SHU_CLRPLL3_RG_RCLRPLL_MONVC_EN                    Fld(2, 14) //[15:14]
+    #define SHU_CLRPLL3_RG_RCLRPLL_MONCK_EN                    Fld(1, 16) //[16:16]
+
+#define DDRPHY_REG_SHU_CLRPLL4                                 (DDRPHY_AO_BASE_ADDRESS + 0x0730)
+    #define SHU_CLRPLL4_RG_RCLRPLL_EXT_PODIV                   Fld(6, 0) //[5:0]
+    #define SHU_CLRPLL4_RG_RCLRPLL_BYPASS                      Fld(1, 8) //[8:8]
+    #define SHU_CLRPLL4_RG_RCLRPLL_EXTPODIV_EN                 Fld(1, 12) //[12:12]
+    #define SHU_CLRPLL4_RG_RCLRPLL_EXT_FBDIV                   Fld(6, 16) //[21:16]
+    #define SHU_CLRPLL4_RG_RCLRPLL_EXTFBDIV_EN                 Fld(1, 24) //[24:24]
+
+#define DDRPHY_REG_SHU_CLRPLL5                                 (DDRPHY_AO_BASE_ADDRESS + 0x0734)
+    #define SHU_CLRPLL5_RG_RCLRPLL_FB_DL                       Fld(6, 0) //[5:0]
+    #define SHU_CLRPLL5_RG_RCLRPLL_REF_DL                      Fld(6, 8) //[13:8]
+
+#define DDRPHY_REG_SHU_CLRPLL6                                 (DDRPHY_AO_BASE_ADDRESS + 0x0738)
+    #define SHU_CLRPLL6_RG_RCLRPLL_SDM_HREN                    Fld(1, 0) //[0:0]
+    #define SHU_CLRPLL6_RG_RCLRPLL_SDM_SSC_PH_INIT             Fld(1, 1) //[1:1]
+    #define SHU_CLRPLL6_RG_RCLRPLL_SDM_SSC_PRD                 Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_SHU_CLRPLL7                                 (DDRPHY_AO_BASE_ADDRESS + 0x073C)
+    #define SHU_CLRPLL7_RG_RCLRPLL_SDM_SSC_DELTA               Fld(16, 0) //[15:0]
+    #define SHU_CLRPLL7_RG_RCLRPLL_SDM_SSC_DELTA1              Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_SHU_PLL0                                    (DDRPHY_AO_BASE_ADDRESS + 0x0740)
+    #define SHU_PLL0_RG_RPHYPLL_TOP_REV                        Fld(16, 0) //[15:0]
+    #define SHU_PLL0_RG_RPLLGP_SOPEN_SER_MODE                  Fld(1, 16) //[16:16]
+    #define SHU_PLL0_RG_RPLLGP_SOPEN_PREDIV_EN                 Fld(1, 17) //[17:17]
+    #define SHU_PLL0_RG_RPLLGP_SOPEN_EN                        Fld(1, 18) //[18:18]
+    #define SHU_PLL0_RG_RPLLGP_DLINE_MON_TSHIFT                Fld(2, 20) //[21:20]
+    #define SHU_PLL0_RG_RPLLGP_DLINE_MON_DIV                   Fld(2, 22) //[23:22]
+    #define SHU_PLL0_RG_RPLLGP_DLINE_MON_DLY                   Fld(7, 24) //[30:24]
+    #define SHU_PLL0_RG_RPLLGP_DLINE_MON_EN                    Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_PLL1                                    (DDRPHY_AO_BASE_ADDRESS + 0x0744)
+    #define SHU_PLL1_RG_RPHYPLLGP_CK_SEL                       Fld(1, 0) //[0:0]
+    #define SHU_PLL1_RG_RPLLGP_PLLCK_VSEL                      Fld(1, 1) //[1:1]
+    #define SHU_PLL1_R_SHU_AUTO_PLL_MUX                        Fld(1, 4) //[4:4]
+    #define SHU_PLL1_RG_RPHYPLL_DDR400_EN                      Fld(1, 8) //[8:8]
+
+#define DDRPHY_REG_SHU_PLL2                                    (DDRPHY_AO_BASE_ADDRESS + 0x0748)
+    #define SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU               Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_SHU_R0_B0_TXDLY0                            (DDRPHY_AO_BASE_ADDRESS + 0x0760)
+    #define SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0                   Fld(8, 0) //[7:0]
+    #define SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0                   Fld(8, 8) //[15:8]
+    #define SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0                   Fld(8, 16) //[23:16]
+    #define SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0                   Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_B0_TXDLY1                            (DDRPHY_AO_BASE_ADDRESS + 0x0764)
+    #define SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0                   Fld(8, 0) //[7:0]
+    #define SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0                   Fld(8, 8) //[15:8]
+    #define SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0                   Fld(8, 16) //[23:16]
+    #define SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0                   Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_B0_TXDLY2                            (DDRPHY_AO_BASE_ADDRESS + 0x0768)
+    #define SHU_R0_B0_TXDLY2_TX_ARDQS0_DLYB_B0                 Fld(8, 0) //[7:0]
+    #define SHU_R0_B0_TXDLY2_TX_ARDQS0B_DLYB_B0                Fld(8, 8) //[15:8]
+    #define SHU_R0_B0_TXDLY2_TX_ARDQS0_DLY_B0                  Fld(8, 16) //[23:16]
+    #define SHU_R0_B0_TXDLY2_TX_ARDQS0B_DLY_B0                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_B0_TXDLY3                            (DDRPHY_AO_BASE_ADDRESS + 0x076C)
+    #define SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0                  Fld(8, 0) //[7:0]
+    #define SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0                   Fld(8, 16) //[23:16]
+    #define SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0                  Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_B0_TXDLY4                            (DDRPHY_AO_BASE_ADDRESS + 0x0770)
+    #define SHU_R0_B0_TXDLY4_DMY_TXDLY4_B0                     Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_SHU_R0_B0_RXDLY0                            (DDRPHY_AO_BASE_ADDRESS + 0x0774)
+    #define SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0                 Fld(8, 0) //[7:0]
+    #define SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0                 Fld(8, 8) //[15:8]
+    #define SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0                 Fld(8, 16) //[23:16]
+    #define SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_B0_RXDLY1                            (DDRPHY_AO_BASE_ADDRESS + 0x0778)
+    #define SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0                 Fld(8, 0) //[7:0]
+    #define SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0                 Fld(8, 8) //[15:8]
+    #define SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0                 Fld(8, 16) //[23:16]
+    #define SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_B0_RXDLY2                            (DDRPHY_AO_BASE_ADDRESS + 0x077C)
+    #define SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0                 Fld(8, 0) //[7:0]
+    #define SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0                 Fld(8, 8) //[15:8]
+    #define SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0                 Fld(8, 16) //[23:16]
+    #define SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_B0_RXDLY3                            (DDRPHY_AO_BASE_ADDRESS + 0x0780)
+    #define SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0                 Fld(8, 0) //[7:0]
+    #define SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0                 Fld(8, 8) //[15:8]
+    #define SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0                 Fld(8, 16) //[23:16]
+    #define SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_B0_RXDLY4                            (DDRPHY_AO_BASE_ADDRESS + 0x0784)
+    #define SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0                Fld(8, 0) //[7:0]
+    #define SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0                Fld(8, 8) //[15:8]
+
+#define DDRPHY_REG_SHU_R0_B0_RXDLY5                            (DDRPHY_AO_BASE_ADDRESS + 0x0788)
+    #define SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0                Fld(9, 0) //[8:0]
+    #define SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0                Fld(9, 16) //[24:16]
+
+#define DDRPHY_REG_SHU_R0_B0_RXDLY6                            (DDRPHY_AO_BASE_ADDRESS + 0x078C)
+    #define SHU_R0_B0_RXDLY6_DMY_RXDLY6_B0                     Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_SHU_R0_B0_RXDLY7                            (DDRPHY_AO_BASE_ADDRESS + 0x0790)
+    #define SHU_R0_B0_RXDLY7_DMY_RXDLY7_B0                     Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_SHU_R0_B0_DQ0                               (DDRPHY_AO_BASE_ADDRESS + 0x0794)
+    #define SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY              Fld(3, 0) //[2:0]
+    #define SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY              Fld(3, 4) //[6:4]
+    #define SHU_R0_B0_DQ0_SW_ARPI_DQ_B0                        Fld(6, 8) //[13:8]
+    #define SHU_R0_B0_DQ0_SW_ARPI_DQM_B0                       Fld(6, 16) //[21:16]
+    #define SHU_R0_B0_DQ0_ARPI_PBYTE_B0                        Fld(6, 24) //[29:24]
+    #define SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0          Fld(1, 30) //[30:30]
+    #define SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0          Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_R0_B0_INI_UIPI                          (DDRPHY_AO_BASE_ADDRESS + 0x0798)
+    #define SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0                  Fld(7, 0) //[6:0]
+    #define SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0                  Fld(8, 8) //[15:8]
+
+#define DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI                     (DDRPHY_AO_BASE_ADDRESS + 0x079C)
+    #define SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0             Fld(7, 0) //[6:0]
+    #define SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0             Fld(8, 8) //[15:8]
+    #define SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0          Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY                 (DDRPHY_AO_BASE_ADDRESS + 0x07A0)
+    #define SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0        Fld(4, 0) //[3:0]
+    #define SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0        Fld(4, 4) //[7:4]
+    #define SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0       Fld(4, 16) //[19:16]
+    #define SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0       Fld(4, 20) //[23:20]
+
+#define DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY                     (DDRPHY_AO_BASE_ADDRESS + 0x07A4)
+    #define SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0               Fld(7, 0) //[6:0]
+
+#define DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY                 (DDRPHY_AO_BASE_ADDRESS + 0x07A8)
+    #define SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0        Fld(3, 0) //[2:0]
+    #define SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0        Fld(3, 4) //[6:4]
+    #define SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0       Fld(3, 16) //[18:16]
+    #define SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0       Fld(3, 20) //[22:20]
+
+#define DDRPHY_REG_SHU_RK_B0_DQ0                               (DDRPHY_AO_BASE_ADDRESS + 0x07AC)
+    #define SHU_RK_B0_DQ0_RG_RX_ARDQ0_OFFC_B0                  Fld(4, 0) //[3:0]
+    #define SHU_RK_B0_DQ0_RG_RX_ARDQ1_OFFC_B0                  Fld(4, 4) //[7:4]
+    #define SHU_RK_B0_DQ0_RG_RX_ARDQ2_OFFC_B0                  Fld(4, 8) //[11:8]
+    #define SHU_RK_B0_DQ0_RG_RX_ARDQ3_OFFC_B0                  Fld(4, 12) //[15:12]
+    #define SHU_RK_B0_DQ0_RG_RX_ARDQ4_OFFC_B0                  Fld(4, 16) //[19:16]
+    #define SHU_RK_B0_DQ0_RG_RX_ARDQ5_OFFC_B0                  Fld(4, 20) //[23:20]
+    #define SHU_RK_B0_DQ0_RG_RX_ARDQ6_OFFC_B0                  Fld(4, 24) //[27:24]
+    #define SHU_RK_B0_DQ0_RG_RX_ARDQ7_OFFC_B0                  Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_SHU_RK_B0_DQ1                               (DDRPHY_AO_BASE_ADDRESS + 0x07B0)
+    #define SHU_RK_B0_DQ1_RG_RX_ARDQM0_OFFC_B0                 Fld(4, 0) //[3:0]
+
+#define DDRPHY_REG_SHU_B0_PHY_VREF_SEL                         (DDRPHY_AO_BASE_ADDRESS + 0x07B4)
+    #define SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0      Fld(7, 0) //[6:0]
+    #define SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0      Fld(7, 8) //[14:8]
+
+#define DDRPHY_REG_SHU_RK_B0_BIST_CTRL                         (DDRPHY_AO_BASE_ADDRESS + 0x07C0)
+    #define SHU_RK_B0_BIST_CTRL_BIST_TX_DQS_UI_DLY_B0          Fld(8, 0) //[7:0]
+
+#define DDRPHY_REG_SHU_B0_DQ0                                  (DDRPHY_AO_BASE_ADDRESS + 0x0860)
+    #define SHU_B0_DQ0_RG_TX_ARDQS0_PRE_EN_B0                  Fld(1, 4) //[4:4]
+    #define SHU_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0                Fld(3, 8) //[10:8]
+    #define SHU_B0_DQ0_RG_TX_ARDQS0_DRVN_PRE_B0                Fld(3, 12) //[14:12]
+    #define SHU_B0_DQ0_RG_TX_ARDQ_PRE_EN_B0                    Fld(1, 20) //[20:20]
+    #define SHU_B0_DQ0_RG_TX_ARDQ_DRVP_PRE_B0                  Fld(3, 24) //[26:24]
+    #define SHU_B0_DQ0_RG_TX_ARDQ_DRVN_PRE_B0                  Fld(3, 28) //[30:28]
+    #define SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0                    Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_B0_DQ3                                  (DDRPHY_AO_BASE_ADDRESS + 0x0864)
+    #define SHU_B0_DQ3_RG_TX_ARDQS0_PU_B0                      Fld(2, 0) //[1:0]
+    #define SHU_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0                  Fld(2, 2) //[3:2]
+    #define SHU_B0_DQ3_RG_TX_ARDQS0_PDB_B0                     Fld(2, 4) //[5:4]
+    #define SHU_B0_DQ3_RG_TX_ARDQS0_PDB_PRE_B0                 Fld(2, 6) //[7:6]
+    #define SHU_B0_DQ3_RG_TX_ARDQ_PU_B0                        Fld(2, 8) //[9:8]
+    #define SHU_B0_DQ3_RG_TX_ARDQ_PU_PRE_B0                    Fld(2, 10) //[11:10]
+    #define SHU_B0_DQ3_RG_TX_ARDQ_PDB_B0                       Fld(2, 12) //[13:12]
+    #define SHU_B0_DQ3_RG_TX_ARDQ_PDB_PRE_B0                   Fld(2, 14) //[15:14]
+    #define SHU_B0_DQ3_RG_ARDQ_DUTYREV_B0                      Fld(9, 23) //[31:23]
+
+#define DDRPHY_REG_SHU_B0_DQ4                                  (DDRPHY_AO_BASE_ADDRESS + 0x0868)
+    #define SHU_B0_DQ4_RG_ARPI_AA_MCK_DL_B0                    Fld(6, 0) //[5:0]
+    #define SHU_B0_DQ4_RG_ARPI_AA_MCK_FB_DL_B0                 Fld(6, 8) //[13:8]
+    #define SHU_B0_DQ4_RG_ARPI_DA_MCK_FB_DL_B0                 Fld(6, 16) //[21:16]
+
+#define DDRPHY_REG_SHU_B0_DQ5                                  (DDRPHY_AO_BASE_ADDRESS + 0x086C)
+    #define SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0                  Fld(6, 0) //[5:0]
+    #define SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0               Fld(1, 6) //[6:6]
+    #define SHU_B0_DQ5_RG_ARPI_FB_B0                           Fld(6, 8) //[13:8]
+    #define SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0              Fld(3, 16) //[18:16]
+    #define SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0            Fld(1, 19) //[19:19]
+    #define SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0                 Fld(4, 20) //[23:20]
+    #define SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0             Fld(3, 29) //[31:29]
+
+#define DDRPHY_REG_SHU_B0_DQ6                                  (DDRPHY_AO_BASE_ADDRESS + 0x0870)
+    #define SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0                Fld(6, 0) //[5:0]
+    #define SHU_B0_DQ6_RG_ARPI_OFFSET_MCTL_B0                  Fld(6, 6) //[11:6]
+    #define SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0                      Fld(7, 12) //[18:12]
+    #define SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0                     Fld(1, 20) //[20:20]
+    #define SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0                      Fld(1, 21) //[21:21]
+    #define SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0                     Fld(2, 22) //[23:22]
+    #define SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B0        Fld(1, 24) //[24:24]
+    #define SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B0       Fld(1, 25) //[25:25]
+    #define SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B0               Fld(1, 26) //[26:26]
+    #define SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B0              Fld(1, 27) //[27:27]
+    #define SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0                    Fld(1, 28) //[28:28]
+    #define SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0         Fld(1, 29) //[29:29]
+
+#define DDRPHY_REG_SHU_B0_DQ1                                  (DDRPHY_AO_BASE_ADDRESS + 0x0874)
+    #define SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0                     Fld(1, 0) //[0:0]
+    #define SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B0       Fld(1, 1) //[1:1]
+    #define SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0              Fld(1, 2) //[2:2]
+    #define SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0                Fld(5, 8) //[12:8]
+    #define SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0           Fld(2, 16) //[17:16]
+    #define SHU_B0_DQ1_RG_ARPI_MIDPI_CAP_SEL_B0                Fld(2, 22) //[23:22]
+    #define SHU_B0_DQ1_RG_ARPI_MIDPI_VTH_SEL_B0                Fld(2, 24) //[25:24]
+    #define SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0          Fld(1, 26) //[26:26]
+    #define SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0               Fld(1, 27) //[27:27]
+    #define SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0              Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_B0_DQ2                                  (DDRPHY_AO_BASE_ADDRESS + 0x0878)
+    #define SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0               Fld(1, 0) //[0:0]
+    #define SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0                  Fld(1, 4) //[4:4]
+    #define SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0                 Fld(1, 5) //[5:5]
+    #define SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0                 Fld(1, 6) //[6:6]
+    #define SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0         Fld(1, 8) //[8:8]
+    #define SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0          Fld(1, 9) //[9:9]
+    #define SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0        Fld(1, 10) //[10:10]
+    #define SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0       Fld(1, 11) //[11:11]
+    #define SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU                Fld(1, 12) //[12:12]
+    #define SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0                  Fld(1, 13) //[13:13]
+    #define SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0                Fld(1, 16) //[16:16]
+    #define SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0              Fld(1, 17) //[17:17]
+
+#define DDRPHY_REG_SHU_B0_DQ10                                 (DDRPHY_AO_BASE_ADDRESS + 0x087C)
+    #define SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0                   Fld(1, 0) //[0:0]
+    #define SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0            Fld(1, 1) //[1:1]
+    #define SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0  Fld(1, 2) //[2:2]
+    #define SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0         Fld(1, 3) //[3:3]
+    #define SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0       Fld(1, 4) //[4:4]
+    #define SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0             Fld(3, 8) //[10:8]
+    #define SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0              Fld(1, 15) //[15:15]
+    #define SHU_B0_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B0            Fld(1, 16) //[16:16]
+    #define SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0                  Fld(2, 18) //[19:18]
+
+#define DDRPHY_REG_SHU_B0_DQ11                                 (DDRPHY_AO_BASE_ADDRESS + 0x0880)
+    #define SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0          Fld(1, 0) //[0:0]
+    #define SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0          Fld(1, 1) //[1:1]
+    #define SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0           Fld(1, 2) //[2:2]
+    #define SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0               Fld(1, 3) //[3:3]
+    #define SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0          Fld(1, 4) //[4:4]
+    #define SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0                 Fld(1, 5) //[5:5]
+    #define SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0                   Fld(1, 6) //[6:6]
+    #define SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0                   Fld(1, 7) //[7:7]
+    #define SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0                  Fld(4, 8) //[11:8]
+    #define SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0                 Fld(2, 16) //[17:16]
+    #define SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0                   Fld(2, 18) //[19:18]
+
+#define DDRPHY_REG_SHU_B0_DQ7                                  (DDRPHY_AO_BASE_ADDRESS + 0x0884)
+    #define SHU_B0_DQ7_R_DMRANKRXDVS_B0                        Fld(4, 0) //[3:0]
+    #define SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0                   Fld(1, 6) //[6:6]
+    #define SHU_B0_DQ7_R_DMDQMDBI_SHU_B0                       Fld(1, 7) //[7:7]
+    #define SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0                Fld(4, 8) //[11:8]
+    #define SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0             Fld(1, 12) //[12:12]
+    #define SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0               Fld(1, 13) //[13:13]
+    #define SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0                   Fld(1, 14) //[14:14]
+    #define SHU_B0_DQ7_R_DMRODTEN_B0                           Fld(1, 15) //[15:15]
+    #define SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0            Fld(1, 16) //[16:16]
+    #define SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0                Fld(1, 17) //[17:17]
+    #define SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0               Fld(1, 18) //[18:18]
+    #define SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0               Fld(1, 19) //[19:19]
+    #define SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0                    Fld(1, 20) //[20:20]
+    #define SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0                     Fld(1, 24) //[24:24]
+    #define SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0                    Fld(3, 25) //[27:25]
+    #define SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0                    Fld(1, 28) //[28:28]
+    #define SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0                   Fld(3, 29) //[31:29]
+
+#define DDRPHY_REG_SHU_B0_DQ8                                  (DDRPHY_AO_BASE_ADDRESS + 0x0888)
+    #define SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0              Fld(15, 0) //[14:0]
+    #define SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0               Fld(1, 15) //[15:15]
+    #define SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0            Fld(1, 19) //[19:19]
+    #define SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0                     Fld(1, 20) //[20:20]
+    #define SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0                   Fld(1, 21) //[21:21]
+    #define SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0           Fld(1, 22) //[22:22]
+    #define SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0       Fld(1, 23) //[23:23]
+    #define SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0                      Fld(1, 24) //[24:24]
+    #define SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0           Fld(1, 26) //[26:26]
+    #define SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0           Fld(1, 27) //[27:27]
+    #define SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0          Fld(1, 28) //[28:28]
+    #define SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0      Fld(1, 29) //[29:29]
+    #define SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0                  Fld(1, 30) //[30:30]
+    #define SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0              Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_B0_DQ9                                  (DDRPHY_AO_BASE_ADDRESS + 0x088C)
+    #define SHU_B0_DQ9_RG_ARPI_RESERVE_B0                      Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_SHU_B0_DQ12                                 (DDRPHY_AO_BASE_ADDRESS + 0x0890)
+    #define SHU_B0_DQ12_DMY_DQ12_B0                            Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_SHU_B0_DLL0                                 (DDRPHY_AO_BASE_ADDRESS + 0x0894)
+    #define SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B0            Fld(3, 0) //[2:0]
+    #define SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B0            Fld(3, 4) //[6:4]
+    #define SHU_B0_DLL0_RG_ARDLL_LCK_DET_EN_B0                 Fld(1, 8) //[8:8]
+    #define SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0                    Fld(4, 12) //[15:12]
+    #define SHU_B0_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B0            Fld(1, 16) //[16:16]
+    #define SHU_B0_DLL0_RG_ARDLL_GAIN_BOOST_B0                 Fld(3, 17) //[19:17]
+    #define SHU_B0_DLL0_RG_ARDLL_GAIN_B0                       Fld(4, 20) //[23:20]
+    #define SHU_B0_DLL0_RG_ARDLL_FAST_DIV_EN_B0                Fld(1, 24) //[24:24]
+    #define SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0                  Fld(1, 25) //[25:25]
+    #define SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0              Fld(1, 26) //[26:26]
+    #define SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0                 Fld(1, 27) //[27:27]
+
+#define DDRPHY_REG_SHU_B0_DLL1                                 (DDRPHY_AO_BASE_ADDRESS + 0x0898)
+    #define SHU_B0_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B0              Fld(1, 0) //[0:0]
+    #define SHU_B0_DLL1_RG_ARDLL_DIV_MODE_B0                   Fld(2, 2) //[3:2]
+    #define SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0                    Fld(1, 4) //[4:4]
+    #define SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B0          Fld(1, 5) //[5:5]
+    #define SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0             Fld(1, 6) //[6:6]
+    #define SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B0        Fld(1, 7) //[7:7]
+    #define SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0                   Fld(2, 8) //[9:8]
+    #define SHU_B0_DLL1_RG_ARDLL_PS_EN_B0                      Fld(1, 10) //[10:10]
+    #define SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0                    Fld(1, 11) //[11:11]
+    #define SHU_B0_DLL1_RG_ARDLL_PHDIV_B0                      Fld(1, 12) //[12:12]
+    #define SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0              Fld(1, 13) //[13:13]
+    #define SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0              Fld(1, 14) //[14:14]
+    #define SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0                   Fld(1, 16) //[16:16]
+    #define SHU_B0_DLL1_RG_ARDLL_DIV_MCTL_B0                   Fld(2, 18) //[19:18]
+    #define SHU_B0_DLL1_RG_ARDLL_PGAIN_B0                      Fld(4, 20) //[23:20]
+    #define SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0                  Fld(1, 24) //[24:24]
+
+#define DDRPHY_REG_SHU_B0_DLL2                                 (DDRPHY_AO_BASE_ADDRESS + 0x089C)
+    #define SHU_B0_DLL2_RG_ARDQ_REV_B0                         Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_SHU_B0_RANK_SELPH_UI_DLY                    (DDRPHY_AO_BASE_ADDRESS + 0x08A0)
+    #define SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P0_B0      Fld(3, 0) //[2:0]
+    #define SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P1_B0      Fld(3, 4) //[6:4]
+    #define SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B0     Fld(3, 16) //[18:16]
+    #define SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B0     Fld(3, 20) //[22:20]
+
+#define DDRPHY_REG_SHU_B0_DLL_ARPI2                            (DDRPHY_AO_BASE_ADDRESS + 0x08A4)
+    #define SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0               Fld(1, 10) //[10:10]
+    #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0              Fld(1, 11) //[11:11]
+    #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0                  Fld(1, 13) //[13:13]
+    #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0                 Fld(1, 14) //[14:14]
+    #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0                 Fld(1, 15) //[15:15]
+    #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0                  Fld(1, 17) //[17:17]
+    #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0                Fld(1, 19) //[19:19]
+    #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0          Fld(1, 27) //[27:27]
+    #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0                 Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_B0_DLL_ARPI3                            (DDRPHY_AO_BASE_ADDRESS + 0x08A8)
+    #define SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0              Fld(1, 11) //[11:11]
+    #define SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0                  Fld(1, 13) //[13:13]
+    #define SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0                 Fld(1, 14) //[14:14]
+    #define SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0                 Fld(1, 15) //[15:15]
+    #define SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0                  Fld(1, 17) //[17:17]
+    #define SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0                Fld(1, 19) //[19:19]
+
+#define DDRPHY_REG_SHU_B0_TXDUTY                               (DDRPHY_AO_BASE_ADDRESS + 0x08AC)
+    #define SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0               Fld(6, 0) //[5:0]
+    #define SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0              Fld(6, 8) //[13:8]
+    #define SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0              Fld(6, 16) //[21:16]
+    #define SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0              Fld(6, 24) //[29:24]
+
+#define DDRPHY_REG_SHU_B0_VREF                                 (DDRPHY_AO_BASE_ADDRESS + 0x08B0)
+    #define SHU_B0_VREF_RG_RX_ARDQ_VREF_SEL_DQS_B0             Fld(7, 0) //[6:0]
+    #define SHU_B0_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B0         Fld(1, 16) //[16:16]
+    #define SHU_B0_VREF_RG_RX_ARDQ_VREF_EN_UB_RK1_B0           Fld(1, 17) //[17:17]
+    #define SHU_B0_VREF_RG_RX_ARDQ_VREF_EN_UB_RK0_B0           Fld(1, 18) //[18:18]
+    #define SHU_B0_VREF_RG_RX_ARDQ_VREF_EN_LB_RK1_B0           Fld(1, 19) //[19:19]
+    #define SHU_B0_VREF_RG_RX_ARDQ_VREF_EN_LB_RK0_B0           Fld(1, 20) //[20:20]
+    #define SHU_B0_VREF_RG_RX_ARDQ_VREF_EN_DQS_B0              Fld(1, 21) //[21:21]
+    #define SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0           Fld(1, 22) //[22:22]
+
+#define DDRPHY_REG_SHU_B0_DQ13                                 (DDRPHY_AO_BASE_ADDRESS + 0x08B4)
+    #define SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0               Fld(1, 0) //[0:0]
+    #define SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0                 Fld(1, 1) //[1:1]
+    #define SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0               Fld(1, 2) //[2:2]
+    #define SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0            Fld(1, 3) //[3:3]
+    #define SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0            Fld(1, 5) //[5:5]
+    #define SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0           Fld(1, 6) //[6:6]
+    #define SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0          Fld(1, 7) //[7:7]
+    #define SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0                Fld(1, 8) //[8:8]
+    #define SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0               Fld(2, 12) //[13:12]
+    #define SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0               Fld(1, 14) //[14:14]
+    #define SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0           Fld(1, 15) //[15:15]
+    #define SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0          Fld(1, 16) //[16:16]
+    #define SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0  Fld(1, 17) //[17:17]
+    #define SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0   Fld(1, 18) //[18:18]
+    #define SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0             Fld(1, 19) //[19:19]
+    #define SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0    Fld(1, 20) //[20:20]
+    #define SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0             Fld(1, 24) //[24:24]
+    #define SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0              Fld(1, 25) //[25:25]
+    #define SHU_B0_DQ13_RG_TX_ARDQS_SER_READ_BASE_EN_B0        Fld(1, 26) //[26:26]
+
+#define DDRPHY_REG_SHU_B0_DQ14                                 (DDRPHY_AO_BASE_ADDRESS + 0x08B8)
+    #define SHU_B0_DQ14_RG_TX_ARWCK_PRE_EN_B0                  Fld(1, 0) //[0:0]
+    #define SHU_B0_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B0            Fld(1, 1) //[1:1]
+    #define SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0               Fld(1, 2) //[2:2]
+    #define SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0                 Fld(2, 4) //[5:4]
+    #define SHU_B0_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B0             Fld(1, 6) //[6:6]
+    #define SHU_B0_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B0             Fld(1, 9) //[9:9]
+    #define SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B0            Fld(1, 10) //[10:10]
+    #define SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0           Fld(1, 11) //[11:11]
+    #define SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0                Fld(8, 16) //[23:16]
+
+#define DDRPHY_REG_B0_SHU_MIDPI_CTRL                           (DDRPHY_AO_BASE_ADDRESS + 0x08BC)
+    #define B0_SHU_MIDPI_CTRL_MIDPI_ENABLE_B0                  Fld(1, 0) //[0:0]
+    #define B0_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B0             Fld(1, 1) //[1:1]
+
+#define DDRPHY_REG_SHU_B0_LPBK_CTRL                            (DDRPHY_AO_BASE_ADDRESS + 0x08C0)
+    #define SHU_B0_LPBK_CTRL_RG_RX_ART2RLPBK_DQS_SEL_B0        Fld(2, 0) //[1:0]
+    #define SHU_B0_LPBK_CTRL_RG_TX_ARDQ_LPBK_SEL_B0            Fld(2, 2) //[3:2]
+    #define SHU_B0_LPBK_CTRL_RG_TX_ARDQS_LPBK_EN_B0            Fld(1, 4) //[4:4]
+
+#define DDRPHY_REG_SHU_B0_DQSIEN_CFG                           (DDRPHY_AO_BASE_ADDRESS + 0x08C4)
+    #define SHU_B0_DQSIEN_CFG_RG_RX_ARDQS_DQSIEN_FORCE_ON_EN_B0 Fld(1, 0) //[0:0]
+    #define SHU_B0_DQSIEN_CFG_RG_RX_ARDQS_DQSIEN_GLITCH_FREE_EN_B0 Fld(1, 1) //[1:1]
+
+#define DDRPHY_REG_SHU_R0_B1_TXDLY0                            (DDRPHY_AO_BASE_ADDRESS + 0x08E0)
+    #define SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1                   Fld(8, 0) //[7:0]
+    #define SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1                   Fld(8, 8) //[15:8]
+    #define SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1                   Fld(8, 16) //[23:16]
+    #define SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1                   Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_B1_TXDLY1                            (DDRPHY_AO_BASE_ADDRESS + 0x08E4)
+    #define SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1                   Fld(8, 0) //[7:0]
+    #define SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1                   Fld(8, 8) //[15:8]
+    #define SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1                   Fld(8, 16) //[23:16]
+    #define SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1                   Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_B1_TXDLY2                            (DDRPHY_AO_BASE_ADDRESS + 0x08E8)
+    #define SHU_R0_B1_TXDLY2_TX_ARDQS0_DLYB_B1                 Fld(8, 0) //[7:0]
+    #define SHU_R0_B1_TXDLY2_TX_ARDQS0B_DLYB_B1                Fld(8, 8) //[15:8]
+    #define SHU_R0_B1_TXDLY2_TX_ARDQS0_DLY_B1                  Fld(8, 16) //[23:16]
+    #define SHU_R0_B1_TXDLY2_TX_ARDQS0B_DLY_B1                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_B1_TXDLY3                            (DDRPHY_AO_BASE_ADDRESS + 0x08EC)
+    #define SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1                  Fld(8, 0) //[7:0]
+    #define SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1                   Fld(8, 16) //[23:16]
+    #define SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1                  Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_B1_TXDLY4                            (DDRPHY_AO_BASE_ADDRESS + 0x08F0)
+    #define SHU_R0_B1_TXDLY4_DMY_TXDLY4_B1                     Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_SHU_R0_B1_RXDLY0                            (DDRPHY_AO_BASE_ADDRESS + 0x08F4)
+    #define SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1                 Fld(8, 0) //[7:0]
+    #define SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1                 Fld(8, 8) //[15:8]
+    #define SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1                 Fld(8, 16) //[23:16]
+    #define SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_B1_RXDLY1                            (DDRPHY_AO_BASE_ADDRESS + 0x08F8)
+    #define SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1                 Fld(8, 0) //[7:0]
+    #define SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1                 Fld(8, 8) //[15:8]
+    #define SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1                 Fld(8, 16) //[23:16]
+    #define SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_B1_RXDLY2                            (DDRPHY_AO_BASE_ADDRESS + 0x08FC)
+    #define SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1                 Fld(8, 0) //[7:0]
+    #define SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1                 Fld(8, 8) //[15:8]
+    #define SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1                 Fld(8, 16) //[23:16]
+    #define SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_B1_RXDLY3                            (DDRPHY_AO_BASE_ADDRESS + 0x0900)
+    #define SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1                 Fld(8, 0) //[7:0]
+    #define SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1                 Fld(8, 8) //[15:8]
+    #define SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1                 Fld(8, 16) //[23:16]
+    #define SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_B1_RXDLY4                            (DDRPHY_AO_BASE_ADDRESS + 0x0904)
+    #define SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1                Fld(8, 0) //[7:0]
+    #define SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1                Fld(8, 8) //[15:8]
+
+#define DDRPHY_REG_SHU_R0_B1_RXDLY5                            (DDRPHY_AO_BASE_ADDRESS + 0x0908)
+    #define SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1                Fld(9, 0) //[8:0]
+    #define SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1                Fld(9, 16) //[24:16]
+
+#define DDRPHY_REG_SHU_R0_B1_RXDLY6                            (DDRPHY_AO_BASE_ADDRESS + 0x090C)
+    #define SHU_R0_B1_RXDLY6_DMY_RXDLY6_B1                     Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_SHU_R0_B1_RXDLY7                            (DDRPHY_AO_BASE_ADDRESS + 0x0910)
+    #define SHU_R0_B1_RXDLY7_DMY_RXDLY7_B1                     Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_SHU_R0_B1_DQ0                               (DDRPHY_AO_BASE_ADDRESS + 0x0914)
+    #define SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY              Fld(3, 0) //[2:0]
+    #define SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY              Fld(3, 4) //[6:4]
+    #define SHU_R0_B1_DQ0_SW_ARPI_DQ_B1                        Fld(6, 8) //[13:8]
+    #define SHU_R0_B1_DQ0_SW_ARPI_DQM_B1                       Fld(6, 16) //[21:16]
+    #define SHU_R0_B1_DQ0_ARPI_PBYTE_B1                        Fld(6, 24) //[29:24]
+    #define SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1          Fld(1, 30) //[30:30]
+    #define SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1          Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_R0_B1_INI_UIPI                          (DDRPHY_AO_BASE_ADDRESS + 0x0918)
+    #define SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1                  Fld(7, 0) //[6:0]
+    #define SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1                  Fld(8, 8) //[15:8]
+
+#define DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI                     (DDRPHY_AO_BASE_ADDRESS + 0x091C)
+    #define SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1             Fld(7, 0) //[6:0]
+    #define SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1             Fld(8, 8) //[15:8]
+    #define SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1          Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY                 (DDRPHY_AO_BASE_ADDRESS + 0x0920)
+    #define SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1        Fld(4, 0) //[3:0]
+    #define SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1        Fld(4, 4) //[7:4]
+    #define SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1       Fld(4, 16) //[19:16]
+    #define SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1       Fld(4, 20) //[23:20]
+
+#define DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY                     (DDRPHY_AO_BASE_ADDRESS + 0x0924)
+    #define SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1               Fld(7, 0) //[6:0]
+
+#define DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY                 (DDRPHY_AO_BASE_ADDRESS + 0x0928)
+    #define SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1        Fld(3, 0) //[2:0]
+    #define SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1        Fld(3, 4) //[6:4]
+    #define SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1       Fld(3, 16) //[18:16]
+    #define SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1       Fld(3, 20) //[22:20]
+
+#define DDRPHY_REG_SHU_RK_B1_DQ0                               (DDRPHY_AO_BASE_ADDRESS + 0x092C)
+    #define SHU_RK_B1_DQ0_RG_RX_ARDQ0_OFFC_B1                  Fld(4, 0) //[3:0]
+    #define SHU_RK_B1_DQ0_RG_RX_ARDQ1_OFFC_B1                  Fld(4, 4) //[7:4]
+    #define SHU_RK_B1_DQ0_RG_RX_ARDQ2_OFFC_B1                  Fld(4, 8) //[11:8]
+    #define SHU_RK_B1_DQ0_RG_RX_ARDQ3_OFFC_B1                  Fld(4, 12) //[15:12]
+    #define SHU_RK_B1_DQ0_RG_RX_ARDQ4_OFFC_B1                  Fld(4, 16) //[19:16]
+    #define SHU_RK_B1_DQ0_RG_RX_ARDQ5_OFFC_B1                  Fld(4, 20) //[23:20]
+    #define SHU_RK_B1_DQ0_RG_RX_ARDQ6_OFFC_B1                  Fld(4, 24) //[27:24]
+    #define SHU_RK_B1_DQ0_RG_RX_ARDQ7_OFFC_B1                  Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_SHU_RK_B1_DQ1                               (DDRPHY_AO_BASE_ADDRESS + 0x0930)
+    #define SHU_RK_B1_DQ1_RG_RX_ARDQM0_OFFC_B1                 Fld(4, 0) //[3:0]
+
+#define DDRPHY_REG_SHU_B1_PHY_VREF_SEL                         (DDRPHY_AO_BASE_ADDRESS + 0x0934)
+    #define SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1      Fld(7, 0) //[6:0]
+    #define SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B1      Fld(7, 8) //[14:8]
+
+#define DDRPHY_REG_SHU_RK_B1_BIST_CTRL                         (DDRPHY_AO_BASE_ADDRESS + 0x0940)
+    #define SHU_RK_B1_BIST_CTRL_BIST_TX_DQS_UI_DLY_B1          Fld(8, 0) //[7:0]
+
+#define DDRPHY_REG_SHU_RK_B1_CKE_OFFSET                        (DDRPHY_AO_BASE_ADDRESS + 0x0944)
+    #define SHU_RK_B1_CKE_OFFSET_RG_RX_ARCS1_OFFSETC_B1        Fld(4, 0) //[3:0]
+    #define SHU_RK_B1_CKE_OFFSET_RG_RX_ARCKE0_OFFSETC_B1       Fld(4, 4) //[7:4]
+    #define SHU_RK_B1_CKE_OFFSET_RG_RX_ARCKE1_OFFSETC_B1       Fld(4, 8) //[11:8]
+
+#define DDRPHY_REG_SHU_RK_B1_CKE_DLY                           (DDRPHY_AO_BASE_ADDRESS + 0x0948)
+    #define SHU_RK_B1_CKE_DLY_RG_RX_ARCS1_DLY_B1               Fld(8, 0) //[7:0]
+    #define SHU_RK_B1_CKE_DLY_RG_RX_ARCKE0_DLY_B1              Fld(8, 8) //[15:8]
+    #define SHU_RK_B1_CKE_DLY_RG_RX_ARCKE1_DLY_B1              Fld(8, 16) //[23:16]
+
+#define DDRPHY_REG_SHU_B1_DQ0                                  (DDRPHY_AO_BASE_ADDRESS + 0x09E0)
+    #define SHU_B1_DQ0_RG_TX_ARDQS0_PRE_EN_B1                  Fld(1, 4) //[4:4]
+    #define SHU_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1                Fld(3, 8) //[10:8]
+    #define SHU_B1_DQ0_RG_TX_ARDQS0_DRVN_PRE_B1                Fld(3, 12) //[14:12]
+    #define SHU_B1_DQ0_RG_TX_ARDQ_PRE_EN_B1                    Fld(1, 20) //[20:20]
+    #define SHU_B1_DQ0_RG_TX_ARDQ_DRVP_PRE_B1                  Fld(3, 24) //[26:24]
+    #define SHU_B1_DQ0_RG_TX_ARDQ_DRVN_PRE_B1                  Fld(3, 28) //[30:28]
+    #define SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1                    Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_B1_DQ3                                  (DDRPHY_AO_BASE_ADDRESS + 0x09E4)
+    #define SHU_B1_DQ3_RG_TX_ARDQS0_PU_B1                      Fld(2, 0) //[1:0]
+    #define SHU_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1                  Fld(2, 2) //[3:2]
+    #define SHU_B1_DQ3_RG_TX_ARDQS0_PDB_B1                     Fld(2, 4) //[5:4]
+    #define SHU_B1_DQ3_RG_TX_ARDQS0_PDB_PRE_B1                 Fld(2, 6) //[7:6]
+    #define SHU_B1_DQ3_RG_TX_ARDQ_PU_B1                        Fld(2, 8) //[9:8]
+    #define SHU_B1_DQ3_RG_TX_ARDQ_PU_PRE_B1                    Fld(2, 10) //[11:10]
+    #define SHU_B1_DQ3_RG_TX_ARDQ_PDB_B1                       Fld(2, 12) //[13:12]
+    #define SHU_B1_DQ3_RG_TX_ARDQ_PDB_PRE_B1                   Fld(2, 14) //[15:14]
+    #define SHU_B1_DQ3_RG_ARDQ_DUTYREV_B1                      Fld(9, 23) //[31:23]
+
+#define DDRPHY_REG_SHU_B1_DQ4                                  (DDRPHY_AO_BASE_ADDRESS + 0x09E8)
+    #define SHU_B1_DQ4_RG_ARPI_AA_MCK_DL_B1                    Fld(6, 0) //[5:0]
+    #define SHU_B1_DQ4_RG_ARPI_AA_MCK_FB_DL_B1                 Fld(6, 8) //[13:8]
+    #define SHU_B1_DQ4_RG_ARPI_DA_MCK_FB_DL_B1                 Fld(6, 16) //[21:16]
+
+#define DDRPHY_REG_SHU_B1_DQ5                                  (DDRPHY_AO_BASE_ADDRESS + 0x09EC)
+    #define SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1                  Fld(6, 0) //[5:0]
+    #define SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1               Fld(1, 6) //[6:6]
+    #define SHU_B1_DQ5_RG_ARPI_FB_B1                           Fld(6, 8) //[13:8]
+    #define SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1              Fld(3, 16) //[18:16]
+    #define SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1            Fld(1, 19) //[19:19]
+    #define SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1                 Fld(4, 20) //[23:20]
+    #define SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1             Fld(3, 29) //[31:29]
+
+#define DDRPHY_REG_SHU_B1_DQ6                                  (DDRPHY_AO_BASE_ADDRESS + 0x09F0)
+    #define SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1                Fld(6, 0) //[5:0]
+    #define SHU_B1_DQ6_RG_ARPI_OFFSET_MCTL_B1                  Fld(6, 6) //[11:6]
+    #define SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1                      Fld(7, 12) //[18:12]
+    #define SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1                     Fld(1, 20) //[20:20]
+    #define SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1                      Fld(1, 21) //[21:21]
+    #define SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1                     Fld(2, 22) //[23:22]
+    #define SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B1        Fld(1, 24) //[24:24]
+    #define SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B1       Fld(1, 25) //[25:25]
+    #define SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B1               Fld(1, 26) //[26:26]
+    #define SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B1              Fld(1, 27) //[27:27]
+    #define SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1                    Fld(1, 28) //[28:28]
+    #define SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1         Fld(1, 29) //[29:29]
+
+#define DDRPHY_REG_SHU_B1_DQ1                                  (DDRPHY_AO_BASE_ADDRESS + 0x09F4)
+    #define SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1                     Fld(1, 0) //[0:0]
+    #define SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1       Fld(1, 1) //[1:1]
+    #define SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1              Fld(1, 2) //[2:2]
+    #define SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1                Fld(5, 8) //[12:8]
+    #define SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1           Fld(2, 16) //[17:16]
+    #define SHU_B1_DQ1_RG_ARPI_MIDPI_CAP_SEL_B1                Fld(2, 22) //[23:22]
+    #define SHU_B1_DQ1_RG_ARPI_MIDPI_VTH_SEL_B1                Fld(2, 24) //[25:24]
+    #define SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1          Fld(1, 26) //[26:26]
+    #define SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1               Fld(1, 27) //[27:27]
+    #define SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1              Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_B1_DQ2                                  (DDRPHY_AO_BASE_ADDRESS + 0x09F8)
+    #define SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1               Fld(1, 0) //[0:0]
+    #define SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1                  Fld(1, 4) //[4:4]
+    #define SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1                 Fld(1, 5) //[5:5]
+    #define SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1                 Fld(1, 6) //[6:6]
+    #define SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1         Fld(1, 8) //[8:8]
+    #define SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1          Fld(1, 9) //[9:9]
+    #define SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1        Fld(1, 10) //[10:10]
+    #define SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1       Fld(1, 11) //[11:11]
+    #define SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU                Fld(1, 12) //[12:12]
+    #define SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1                  Fld(1, 13) //[13:13]
+    #define SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1                Fld(1, 16) //[16:16]
+    #define SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1              Fld(1, 17) //[17:17]
+
+#define DDRPHY_REG_SHU_B1_DQ10                                 (DDRPHY_AO_BASE_ADDRESS + 0x09FC)
+    #define SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1                   Fld(1, 0) //[0:0]
+    #define SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1            Fld(1, 1) //[1:1]
+    #define SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1  Fld(1, 2) //[2:2]
+    #define SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1         Fld(1, 3) //[3:3]
+    #define SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1       Fld(1, 4) //[4:4]
+    #define SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1             Fld(3, 8) //[10:8]
+    #define SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1              Fld(1, 15) //[15:15]
+    #define SHU_B1_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B1            Fld(1, 16) //[16:16]
+    #define SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1                  Fld(2, 18) //[19:18]
+
+#define DDRPHY_REG_SHU_B1_DQ11                                 (DDRPHY_AO_BASE_ADDRESS + 0x0A00)
+    #define SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1          Fld(1, 0) //[0:0]
+    #define SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1          Fld(1, 1) //[1:1]
+    #define SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1           Fld(1, 2) //[2:2]
+    #define SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1               Fld(1, 3) //[3:3]
+    #define SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1          Fld(1, 4) //[4:4]
+    #define SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1                 Fld(1, 5) //[5:5]
+    #define SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1                   Fld(1, 6) //[6:6]
+    #define SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1                   Fld(1, 7) //[7:7]
+    #define SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1                  Fld(4, 8) //[11:8]
+    #define SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1                 Fld(2, 16) //[17:16]
+    #define SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1                   Fld(2, 18) //[19:18]
+
+#define DDRPHY_REG_SHU_B1_DQ7                                  (DDRPHY_AO_BASE_ADDRESS + 0x0A04)
+    #define SHU_B1_DQ7_R_DMRANKRXDVS_B1                        Fld(4, 0) //[3:0]
+    #define SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1                   Fld(1, 6) //[6:6]
+    #define SHU_B1_DQ7_R_DMDQMDBI_SHU_B1                       Fld(1, 7) //[7:7]
+    #define SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1                Fld(4, 8) //[11:8]
+    #define SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1             Fld(1, 12) //[12:12]
+    #define SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1               Fld(1, 13) //[13:13]
+    #define SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1                   Fld(1, 14) //[14:14]
+    #define SHU_B1_DQ7_R_DMRODTEN_B1                           Fld(1, 15) //[15:15]
+    #define SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1            Fld(1, 16) //[16:16]
+    #define SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1                Fld(1, 17) //[17:17]
+    #define SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1               Fld(1, 18) //[18:18]
+    #define SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1               Fld(1, 19) //[19:19]
+    #define SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1                    Fld(1, 20) //[20:20]
+    #define SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1                     Fld(1, 24) //[24:24]
+    #define SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1                    Fld(3, 25) //[27:25]
+    #define SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1                    Fld(1, 28) //[28:28]
+    #define SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1                   Fld(3, 29) //[31:29]
+
+#define DDRPHY_REG_SHU_B1_DQ8                                  (DDRPHY_AO_BASE_ADDRESS + 0x0A08)
+    #define SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1              Fld(15, 0) //[14:0]
+    #define SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1               Fld(1, 15) //[15:15]
+    #define SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1            Fld(1, 19) //[19:19]
+    #define SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1                     Fld(1, 20) //[20:20]
+    #define SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1                   Fld(1, 21) //[21:21]
+    #define SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1           Fld(1, 22) //[22:22]
+    #define SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1       Fld(1, 23) //[23:23]
+    #define SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1                      Fld(1, 24) //[24:24]
+    #define SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1           Fld(1, 26) //[26:26]
+    #define SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1           Fld(1, 27) //[27:27]
+    #define SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1          Fld(1, 28) //[28:28]
+    #define SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1      Fld(1, 29) //[29:29]
+    #define SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1                  Fld(1, 30) //[30:30]
+    #define SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1              Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_B1_DQ9                                  (DDRPHY_AO_BASE_ADDRESS + 0x0A0C)
+    #define SHU_B1_DQ9_RG_ARPI_RESERVE_B1                      Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_SHU_B1_DQ12                                 (DDRPHY_AO_BASE_ADDRESS + 0x0A10)
+    #define SHU_B1_DQ12_DMY_DQ12_B1                            Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_SHU_B1_DLL0                                 (DDRPHY_AO_BASE_ADDRESS + 0x0A14)
+    #define SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B1            Fld(3, 0) //[2:0]
+    #define SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B1            Fld(3, 4) //[6:4]
+    #define SHU_B1_DLL0_RG_ARDLL_LCK_DET_EN_B1                 Fld(1, 8) //[8:8]
+    #define SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1                    Fld(4, 12) //[15:12]
+    #define SHU_B1_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B1            Fld(1, 16) //[16:16]
+    #define SHU_B1_DLL0_RG_ARDLL_GAIN_BOOST_B1                 Fld(3, 17) //[19:17]
+    #define SHU_B1_DLL0_RG_ARDLL_GAIN_B1                       Fld(4, 20) //[23:20]
+    #define SHU_B1_DLL0_RG_ARDLL_FAST_DIV_EN_B1                Fld(1, 24) //[24:24]
+    #define SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1                  Fld(1, 25) //[25:25]
+    #define SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1              Fld(1, 26) //[26:26]
+    #define SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1                 Fld(1, 27) //[27:27]
+
+#define DDRPHY_REG_SHU_B1_DLL1                                 (DDRPHY_AO_BASE_ADDRESS + 0x0A18)
+    #define SHU_B1_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B1              Fld(1, 0) //[0:0]
+    #define SHU_B1_DLL1_RG_ARDLL_DIV_MODE_B1                   Fld(2, 2) //[3:2]
+    #define SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1                    Fld(1, 4) //[4:4]
+    #define SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B1          Fld(1, 5) //[5:5]
+    #define SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1             Fld(1, 6) //[6:6]
+    #define SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B1        Fld(1, 7) //[7:7]
+    #define SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1                   Fld(2, 8) //[9:8]
+    #define SHU_B1_DLL1_RG_ARDLL_PS_EN_B1                      Fld(1, 10) //[10:10]
+    #define SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1                    Fld(1, 11) //[11:11]
+    #define SHU_B1_DLL1_RG_ARDLL_PHDIV_B1                      Fld(1, 12) //[12:12]
+    #define SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1              Fld(1, 13) //[13:13]
+    #define SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1              Fld(1, 14) //[14:14]
+    #define SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1                   Fld(1, 16) //[16:16]
+    #define SHU_B1_DLL1_RG_ARDLL_DIV_MCTL_B1                   Fld(2, 18) //[19:18]
+    #define SHU_B1_DLL1_RG_ARDLL_PGAIN_B1                      Fld(4, 20) //[23:20]
+    #define SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1                  Fld(1, 24) //[24:24]
+
+#define DDRPHY_REG_SHU_B1_DLL2                                 (DDRPHY_AO_BASE_ADDRESS + 0x0A1C)
+    #define SHU_B1_DLL2_RG_ARDQ_REV_B1                         Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_SHU_B1_RANK_SELPH_UI_DLY                    (DDRPHY_AO_BASE_ADDRESS + 0x0A20)
+    #define SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P0_B1      Fld(3, 0) //[2:0]
+    #define SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P1_B1      Fld(3, 4) //[6:4]
+    #define SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B1     Fld(3, 16) //[18:16]
+    #define SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B1     Fld(3, 20) //[22:20]
+
+#define DDRPHY_REG_SHU_B1_DLL_ARPI2                            (DDRPHY_AO_BASE_ADDRESS + 0x0A24)
+    #define SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1               Fld(1, 10) //[10:10]
+    #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1              Fld(1, 11) //[11:11]
+    #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1                  Fld(1, 13) //[13:13]
+    #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1                 Fld(1, 14) //[14:14]
+    #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1                 Fld(1, 15) //[15:15]
+    #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1                  Fld(1, 17) //[17:17]
+    #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1                Fld(1, 19) //[19:19]
+    #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1          Fld(1, 27) //[27:27]
+    #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1                 Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_B1_DLL_ARPI3                            (DDRPHY_AO_BASE_ADDRESS + 0x0A28)
+    #define SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1              Fld(1, 11) //[11:11]
+    #define SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1                  Fld(1, 13) //[13:13]
+    #define SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1                 Fld(1, 14) //[14:14]
+    #define SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1                 Fld(1, 15) //[15:15]
+    #define SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1                  Fld(1, 17) //[17:17]
+    #define SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1                Fld(1, 19) //[19:19]
+
+#define DDRPHY_REG_SHU_B1_TXDUTY                               (DDRPHY_AO_BASE_ADDRESS + 0x0A2C)
+    #define SHU_B1_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B1               Fld(6, 0) //[5:0]
+    #define SHU_B1_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B1              Fld(6, 8) //[13:8]
+    #define SHU_B1_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B1              Fld(6, 16) //[21:16]
+    #define SHU_B1_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B1              Fld(6, 24) //[29:24]
+
+#define DDRPHY_REG_SHU_B1_VREF                                 (DDRPHY_AO_BASE_ADDRESS + 0x0A30)
+    #define SHU_B1_VREF_RG_RX_ARDQ_VREF_SEL_DQS_B1             Fld(7, 0) //[6:0]
+    #define SHU_B1_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B1         Fld(1, 16) //[16:16]
+    #define SHU_B1_VREF_RG_RX_ARDQ_VREF_EN_UB_RK1_B1           Fld(1, 17) //[17:17]
+    #define SHU_B1_VREF_RG_RX_ARDQ_VREF_EN_UB_RK0_B1           Fld(1, 18) //[18:18]
+    #define SHU_B1_VREF_RG_RX_ARDQ_VREF_EN_LB_RK1_B1           Fld(1, 19) //[19:19]
+    #define SHU_B1_VREF_RG_RX_ARDQ_VREF_EN_LB_RK0_B1           Fld(1, 20) //[20:20]
+    #define SHU_B1_VREF_RG_RX_ARDQ_VREF_EN_DQS_B1              Fld(1, 21) //[21:21]
+    #define SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1           Fld(1, 22) //[22:22]
+
+#define DDRPHY_REG_SHU_B1_DQ13                                 (DDRPHY_AO_BASE_ADDRESS + 0x0A34)
+    #define SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1               Fld(1, 0) //[0:0]
+    #define SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1                 Fld(1, 1) //[1:1]
+    #define SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1               Fld(1, 2) //[2:2]
+    #define SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1            Fld(1, 3) //[3:3]
+    #define SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1            Fld(1, 5) //[5:5]
+    #define SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1           Fld(1, 6) //[6:6]
+    #define SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1          Fld(1, 7) //[7:7]
+    #define SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1                Fld(1, 8) //[8:8]
+    #define SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1               Fld(2, 12) //[13:12]
+    #define SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1               Fld(1, 14) //[14:14]
+    #define SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1           Fld(1, 15) //[15:15]
+    #define SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1          Fld(1, 16) //[16:16]
+    #define SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1  Fld(1, 17) //[17:17]
+    #define SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1   Fld(1, 18) //[18:18]
+    #define SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1             Fld(1, 19) //[19:19]
+    #define SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1    Fld(1, 20) //[20:20]
+    #define SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1             Fld(1, 24) //[24:24]
+    #define SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1              Fld(1, 25) //[25:25]
+    #define SHU_B1_DQ13_RG_TX_ARDQS_SER_READ_BASE_EN_B1        Fld(1, 26) //[26:26]
+
+#define DDRPHY_REG_SHU_B1_DQ14                                 (DDRPHY_AO_BASE_ADDRESS + 0x0A38)
+    #define SHU_B1_DQ14_RG_TX_ARWCK_PRE_EN_B1                  Fld(1, 0) //[0:0]
+    #define SHU_B1_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B1            Fld(1, 1) //[1:1]
+    #define SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1               Fld(1, 2) //[2:2]
+    #define SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1                 Fld(2, 4) //[5:4]
+    #define SHU_B1_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B1             Fld(1, 6) //[6:6]
+    #define SHU_B1_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B1             Fld(1, 9) //[9:9]
+    #define SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B1            Fld(1, 10) //[10:10]
+    #define SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1           Fld(1, 11) //[11:11]
+    #define SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1                Fld(8, 16) //[23:16]
+
+#define DDRPHY_REG_B1_SHU_MIDPI_CTRL                           (DDRPHY_AO_BASE_ADDRESS + 0x0A3C)
+    #define B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1                  Fld(1, 0) //[0:0]
+    #define B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1             Fld(1, 1) //[1:1]
+
+#define DDRPHY_REG_SHU_B1_LPBK_CTRL                            (DDRPHY_AO_BASE_ADDRESS + 0x0A40)
+    #define SHU_B1_LPBK_CTRL_RG_RX_ART2RLPBK_DQS_SEL_B1        Fld(2, 0) //[1:0]
+    #define SHU_B1_LPBK_CTRL_RG_TX_ARDQ_LPBK_SEL_B1            Fld(2, 2) //[3:2]
+    #define SHU_B1_LPBK_CTRL_RG_TX_ARDQS_LPBK_EN_B1            Fld(1, 4) //[4:4]
+
+#define DDRPHY_REG_SHU_B1_DQSIEN_CFG                           (DDRPHY_AO_BASE_ADDRESS + 0x0A44)
+    #define SHU_B1_DQSIEN_CFG_RG_RX_ARDQS_DQSIEN_FORCE_ON_EN_B1 Fld(1, 0) //[0:0]
+    #define SHU_B1_DQSIEN_CFG_RG_RX_ARDQS_DQSIEN_GLITCH_FREE_EN_B1 Fld(1, 1) //[1:1]
+
+#define DDRPHY_REG_SHU_B1_CKE_CTRL                             (DDRPHY_AO_BASE_ADDRESS + 0x0A48)
+    #define SHU_B1_CKE_CTRL_RG_TX_ARCKE_OE_ODTEN_CG_EN_B1      Fld(1, 0) //[0:0]
+    #define SHU_B1_CKE_CTRL_RG_TX_ARCKE_MCKIO_SEL_B1           Fld(1, 1) //[1:1]
+    #define SHU_B1_CKE_CTRL_RG_TX_ARCKE_DRVP_B1                Fld(5, 4) //[8:4]
+    #define SHU_B1_CKE_CTRL_RG_TX_ARCKE_DRVN_B1                Fld(5, 12) //[16:12]
+
+#define DDRPHY_REG_SHU_B1_CKE_DLY_CTRL                         (DDRPHY_AO_BASE_ADDRESS + 0x0A4C)
+    #define SHU_B1_CKE_DLY_CTRL_RG_TX_ARCKE0_DLY_B1            Fld(8, 0) //[7:0]
+    #define SHU_B1_CKE_DLY_CTRL_RG_TX_ARCKE1_DLY_B1            Fld(8, 8) //[15:8]
+    #define SHU_B1_CKE_DLY_CTRL_RG_TX_ARCS1_DLY_B1             Fld(8, 16) //[23:16]
+    #define SHU_B1_CKE_DLY_CTRL_RG_TX_ARCKE_DUTY_DLY_B1        Fld(6, 24) //[29:24]
+
+#define DDRPHY_REG_SHU_R0_CA_TXDLY0                            (DDRPHY_AO_BASE_ADDRESS + 0x0A60)
+    #define SHU_R0_CA_TXDLY0_TX_ARCA0_DLY                      Fld(8, 0) //[7:0]
+    #define SHU_R0_CA_TXDLY0_TX_ARCA1_DLY                      Fld(8, 8) //[15:8]
+    #define SHU_R0_CA_TXDLY0_TX_ARCA2_DLY                      Fld(8, 16) //[23:16]
+    #define SHU_R0_CA_TXDLY0_TX_ARCA3_DLY                      Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_CA_TXDLY1                            (DDRPHY_AO_BASE_ADDRESS + 0x0A64)
+    #define SHU_R0_CA_TXDLY1_TX_ARCA4_DLY                      Fld(8, 0) //[7:0]
+    #define SHU_R0_CA_TXDLY1_TX_ARCA5_DLY                      Fld(8, 8) //[15:8]
+    #define SHU_R0_CA_TXDLY1_TX_ARCA6_DLY                      Fld(8, 16) //[23:16]
+    #define SHU_R0_CA_TXDLY1_TX_ARCA7_DLY                      Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_CA_TXDLY2                            (DDRPHY_AO_BASE_ADDRESS + 0x0A68)
+    #define SHU_R0_CA_TXDLY2_TX_ARCKE0_DLY                     Fld(8, 0) //[7:0]
+    #define SHU_R0_CA_TXDLY2_TX_ARCKE1_DLY                     Fld(8, 8) //[15:8]
+    #define SHU_R0_CA_TXDLY2_TX_ARCKE2_DLY                     Fld(8, 16) //[23:16]
+    #define SHU_R0_CA_TXDLY2_TX_ARCS0_DLY                      Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_CA_TXDLY3                            (DDRPHY_AO_BASE_ADDRESS + 0x0A6C)
+    #define SHU_R0_CA_TXDLY3_TX_ARCS1_DLY                      Fld(8, 0) //[7:0]
+    #define SHU_R0_CA_TXDLY3_TX_ARCS2_DLY                      Fld(8, 8) //[15:8]
+    #define SHU_R0_CA_TXDLY3_TX_ARCLK_DLY                      Fld(8, 16) //[23:16]
+    #define SHU_R0_CA_TXDLY3_TX_ARCLKB_DLY                     Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_CA_TXDLY4                            (DDRPHY_AO_BASE_ADDRESS + 0x0A70)
+    #define SHU_R0_CA_TXDLY4_TX_ARCLK_DLYB                     Fld(8, 0) //[7:0]
+    #define SHU_R0_CA_TXDLY4_TX_ARCLKB_DLYB                    Fld(8, 8) //[15:8]
+
+#define DDRPHY_REG_SHU_R0_CA_RXDLY0                            (DDRPHY_AO_BASE_ADDRESS + 0x0A74)
+    #define SHU_R0_CA_RXDLY0_RG_RX_ARCA0_R_DLY                 Fld(8, 0) //[7:0]
+    #define SHU_R0_CA_RXDLY0_RG_RX_ARCA0_F_DLY                 Fld(8, 8) //[15:8]
+    #define SHU_R0_CA_RXDLY0_RG_RX_ARCA1_R_DLY                 Fld(8, 16) //[23:16]
+    #define SHU_R0_CA_RXDLY0_RG_RX_ARCA1_F_DLY                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_CA_RXDLY1                            (DDRPHY_AO_BASE_ADDRESS + 0x0A78)
+    #define SHU_R0_CA_RXDLY1_RG_RX_ARCA2_R_DLY                 Fld(8, 0) //[7:0]
+    #define SHU_R0_CA_RXDLY1_RG_RX_ARCA2_F_DLY                 Fld(8, 8) //[15:8]
+    #define SHU_R0_CA_RXDLY1_RG_RX_ARCA3_R_DLY                 Fld(8, 16) //[23:16]
+    #define SHU_R0_CA_RXDLY1_RG_RX_ARCA3_F_DLY                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_CA_RXDLY2                            (DDRPHY_AO_BASE_ADDRESS + 0x0A7C)
+    #define SHU_R0_CA_RXDLY2_RG_RX_ARCA4_R_DLY                 Fld(8, 0) //[7:0]
+    #define SHU_R0_CA_RXDLY2_RG_RX_ARCA4_F_DLY                 Fld(8, 8) //[15:8]
+    #define SHU_R0_CA_RXDLY2_RG_RX_ARCA5_R_DLY                 Fld(8, 16) //[23:16]
+    #define SHU_R0_CA_RXDLY2_RG_RX_ARCA5_F_DLY                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_CA_RXDLY6                            (DDRPHY_AO_BASE_ADDRESS + 0x0A80)
+    #define SHU_R0_CA_RXDLY6_RG_RX_ARCA6_R_DLY                 Fld(8, 0) //[7:0]
+    #define SHU_R0_CA_RXDLY6_RG_RX_ARCA6_F_DLY                 Fld(8, 8) //[15:8]
+    #define SHU_R0_CA_RXDLY6_RG_RX_ARCA7_R_DLY                 Fld(8, 16) //[23:16]
+    #define SHU_R0_CA_RXDLY6_RG_RX_ARCA7_F_DLY                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_CA_RXDLY3                            (DDRPHY_AO_BASE_ADDRESS + 0x0A84)
+    #define SHU_R0_CA_RXDLY3_RG_RX_ARCKE0_R_DLY                Fld(8, 0) //[7:0]
+    #define SHU_R0_CA_RXDLY3_RG_RX_ARCKE0_F_DLY                Fld(8, 8) //[15:8]
+    #define SHU_R0_CA_RXDLY3_RG_RX_ARCKE1_R_DLY                Fld(8, 16) //[23:16]
+    #define SHU_R0_CA_RXDLY3_RG_RX_ARCKE1_F_DLY                Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_CA_RXDLY4                            (DDRPHY_AO_BASE_ADDRESS + 0x0A88)
+    #define SHU_R0_CA_RXDLY4_RG_RX_ARCKE2_R_DLY                Fld(8, 0) //[7:0]
+    #define SHU_R0_CA_RXDLY4_RG_RX_ARCKE2_F_DLY                Fld(8, 8) //[15:8]
+    #define SHU_R0_CA_RXDLY4_RG_RX_ARCS0_R_DLY                 Fld(8, 16) //[23:16]
+    #define SHU_R0_CA_RXDLY4_RG_RX_ARCS0_F_DLY                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_CA_RXDLY5                            (DDRPHY_AO_BASE_ADDRESS + 0x0A8C)
+    #define SHU_R0_CA_RXDLY5_RG_RX_ARCS1_R_DLY                 Fld(8, 0) //[7:0]
+    #define SHU_R0_CA_RXDLY5_RG_RX_ARCS1_F_DLY                 Fld(8, 8) //[15:8]
+    #define SHU_R0_CA_RXDLY5_RG_RX_ARCS2_R_DLY                 Fld(8, 16) //[23:16]
+    #define SHU_R0_CA_RXDLY5_RG_RX_ARCS2_F_DLY                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_R0_CA_RXDLY7                            (DDRPHY_AO_BASE_ADDRESS + 0x0A90)
+    #define SHU_R0_CA_RXDLY7_RG_RX_ARCLK_R_DLY                 Fld(9, 0) //[8:0]
+    #define SHU_R0_CA_RXDLY7_RG_RX_ARCLK_F_DLY                 Fld(9, 16) //[24:16]
+
+#define DDRPHY_REG_SHU_R0_CA_CMD0                              (DDRPHY_AO_BASE_ADDRESS + 0x0A94)
+    #define SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY              Fld(3, 0) //[2:0]
+    #define SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY              Fld(3, 4) //[6:4]
+    #define SHU_R0_CA_CMD0_RG_ARPI_CS                          Fld(6, 8) //[13:8]
+    #define SHU_R0_CA_CMD0_RG_ARPI_CMD                         Fld(6, 16) //[21:16]
+    #define SHU_R0_CA_CMD0_RG_ARPI_CLK                         Fld(6, 24) //[29:24]
+    #define SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA         Fld(1, 30) //[30:30]
+    #define SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA         Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_R0_CA_INI_UIPI                          (DDRPHY_AO_BASE_ADDRESS + 0x0A98)
+    #define SHU_R0_CA_INI_UIPI_CURR_INI_PI_CA                  Fld(7, 0) //[6:0]
+    #define SHU_R0_CA_INI_UIPI_CURR_INI_UI_CA                  Fld(8, 8) //[15:8]
+
+#define DDRPHY_REG_SHU_R0_CA_NEXT_INI_UIPI                     (DDRPHY_AO_BASE_ADDRESS + 0x0A9C)
+    #define SHU_R0_CA_NEXT_INI_UIPI_NEXT_INI_PI_CA             Fld(7, 0) //[6:0]
+    #define SHU_R0_CA_NEXT_INI_UIPI_NEXT_INI_UI_CA             Fld(8, 8) //[15:8]
+    #define SHU_R0_CA_NEXT_INI_UIPI_NEXT_INI_UI_P1_CA          Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_SHU_RK_CA_DQSIEN_MCK_UI_DLY                 (DDRPHY_AO_BASE_ADDRESS + 0x0AA0)
+    #define SHU_RK_CA_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_CA        Fld(4, 0) //[3:0]
+    #define SHU_RK_CA_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_CA        Fld(4, 4) //[7:4]
+    #define SHU_RK_CA_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_CA       Fld(4, 16) //[19:16]
+    #define SHU_RK_CA_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_CA       Fld(4, 20) //[23:20]
+
+#define DDRPHY_REG_SHU_RK_CA_DQSIEN_PI_DLY                     (DDRPHY_AO_BASE_ADDRESS + 0x0AA4)
+    #define SHU_RK_CA_DQSIEN_PI_DLY_DQSIEN_PI_CA               Fld(7, 0) //[6:0]
+
+#define DDRPHY_REG_SHU_RK_CA_RODTEN_MCK_UI_DLY                 (DDRPHY_AO_BASE_ADDRESS + 0x0AA8)
+    #define SHU_RK_CA_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_CA        Fld(3, 0) //[2:0]
+    #define SHU_RK_CA_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_CA        Fld(3, 4) //[6:4]
+    #define SHU_RK_CA_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_CA       Fld(3, 16) //[18:16]
+    #define SHU_RK_CA_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_CA       Fld(3, 20) //[22:20]
+
+#define DDRPHY_REG_SHU_RK_CA_CMD0                              (DDRPHY_AO_BASE_ADDRESS + 0x0AAC)
+    #define SHU_RK_CA_CMD0_RG_RX_ARCA0_OFFC                    Fld(4, 0) //[3:0]
+    #define SHU_RK_CA_CMD0_RG_RX_ARCA1_OFFC                    Fld(4, 4) //[7:4]
+    #define SHU_RK_CA_CMD0_RG_RX_ARCA2_OFFC                    Fld(4, 8) //[11:8]
+    #define SHU_RK_CA_CMD0_RG_RX_ARCA3_OFFC                    Fld(4, 12) //[15:12]
+    #define SHU_RK_CA_CMD0_RG_RX_ARCA4_OFFC                    Fld(4, 16) //[19:16]
+    #define SHU_RK_CA_CMD0_RG_RX_ARCA5_OFFC                    Fld(4, 20) //[23:20]
+
+#define DDRPHY_REG_SHU_RK_CA_CMD1                              (DDRPHY_AO_BASE_ADDRESS + 0x0AB0)
+    #define SHU_RK_CA_CMD1_RG_RX_ARCS0_OFFC                    Fld(4, 0) //[3:0]
+    #define SHU_RK_CA_CMD1_RG_RX_ARCS1_OFFC                    Fld(4, 4) //[7:4]
+    #define SHU_RK_CA_CMD1_RG_RX_ARCS2_OFFC                    Fld(4, 8) //[11:8]
+    #define SHU_RK_CA_CMD1_RG_RX_ARCKE0_OFFC                   Fld(4, 12) //[15:12]
+    #define SHU_RK_CA_CMD1_RG_RX_ARCKE1_OFFC                   Fld(4, 16) //[19:16]
+    #define SHU_RK_CA_CMD1_RG_RX_ARCKE2_OFFC                   Fld(4, 20) //[23:20]
+
+#define DDRPHY_REG_SHU_CA_PHY_VREF_SEL                         (DDRPHY_AO_BASE_ADDRESS + 0x0AB4)
+    #define SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_LB         Fld(7, 0) //[6:0]
+    #define SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_UB         Fld(7, 8) //[14:8]
+
+#define DDRPHY_REG_SHU_RK_CA_DQ_OFFSET                         (DDRPHY_AO_BASE_ADDRESS + 0x0AB8)
+    #define SHU_RK_CA_DQ_OFFSET_RG_RX_ARDQ6_OFFSETC_C0         Fld(4, 0) //[3:0]
+    #define SHU_RK_CA_DQ_OFFSET_RG_RX_ARDQ7_OFFSETC_C0         Fld(4, 4) //[7:4]
+
+#define DDRPHY_REG_SHU_RK_CA_DQ_DLY                            (DDRPHY_AO_BASE_ADDRESS + 0x0ABC)
+    #define SHU_RK_CA_DQ_DLY_RG_RX_ARDQ6_DLY_RK0_C0            Fld(8, 0) //[7:0]
+    #define SHU_RK_CA_DQ_DLY_RG_RX_ARDQ7_DLY_RK0_C0            Fld(8, 8) //[15:8]
+
+#define DDRPHY_REG_SHU_CA_CMD0                                 (DDRPHY_AO_BASE_ADDRESS + 0x0B60)
+    #define SHU_CA_CMD0_RG_TX_ARCLK_PRE_EN                     Fld(1, 4) //[4:4]
+    #define SHU_CA_CMD0_RG_TX_ARCLK_DRVP_PRE                   Fld(3, 8) //[10:8]
+    #define SHU_CA_CMD0_RG_TX_ARCLK_DRVN_PRE                   Fld(3, 12) //[14:12]
+    #define SHU_CA_CMD0_RG_TX_ARCMD_PRE_EN                     Fld(1, 20) //[20:20]
+    #define SHU_CA_CMD0_RG_TX_ARCMD_DRVP_PRE                   Fld(3, 24) //[26:24]
+    #define SHU_CA_CMD0_RG_TX_ARCMD_DRVN_PRE                   Fld(3, 28) //[30:28]
+    #define SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK                    Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_CA_CMD3                                 (DDRPHY_AO_BASE_ADDRESS + 0x0B64)
+    #define SHU_CA_CMD3_RG_TX_ARCLK_PU                         Fld(2, 0) //[1:0]
+    #define SHU_CA_CMD3_RG_TX_ARCLK_PU_PRE                     Fld(2, 2) //[3:2]
+    #define SHU_CA_CMD3_RG_TX_ARCLK_PDB                        Fld(2, 4) //[5:4]
+    #define SHU_CA_CMD3_RG_TX_ARCLK_PDB_PRE                    Fld(2, 6) //[7:6]
+    #define SHU_CA_CMD3_RG_TX_ARCMD_PU                         Fld(2, 8) //[9:8]
+    #define SHU_CA_CMD3_RG_TX_ARCMD_PU_PRE                     Fld(2, 10) //[11:10]
+    #define SHU_CA_CMD3_RG_TX_ARCMD_PDB                        Fld(2, 12) //[13:12]
+    #define SHU_CA_CMD3_RG_TX_ARCMD_PDB_PRE                    Fld(2, 14) //[15:14]
+
+#define DDRPHY_REG_SHU_CA_CMD4                                 (DDRPHY_AO_BASE_ADDRESS + 0x0B68)
+    #define SHU_CA_CMD4_RG_ARPI_AA_MCK_DL_CA                   Fld(6, 0) //[5:0]
+    #define SHU_CA_CMD4_RG_ARPI_AA_MCK_FB_DL_CA                Fld(6, 8) //[13:8]
+    #define SHU_CA_CMD4_RG_ARPI_DA_MCK_FB_DL_CA                Fld(6, 16) //[21:16]
+
+#define DDRPHY_REG_SHU_CA_CMD5                                 (DDRPHY_AO_BASE_ADDRESS + 0x0B6C)
+    #define SHU_CA_CMD5_RG_RX_ARCMD_VREF_SEL                   Fld(6, 0) //[5:0]
+    #define SHU_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS                Fld(1, 6) //[6:6]
+    #define SHU_CA_CMD5_RG_ARPI_FB_CA                          Fld(6, 8) //[13:8]
+    #define SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY                 Fld(3, 16) //[18:16]
+    #define SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_RB_DLY              Fld(1, 19) //[19:19]
+    #define SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY                    Fld(4, 20) //[23:20]
+    #define SHU_CA_CMD5_RG_RX_ARCMD_FIFO_DQSI_DLY              Fld(3, 29) //[31:29]
+
+#define DDRPHY_REG_SHU_CA_CMD6                                 (DDRPHY_AO_BASE_ADDRESS + 0x0B70)
+    #define SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA               Fld(6, 0) //[5:0]
+    #define SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA                 Fld(6, 6) //[11:6]
+    #define SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA                     Fld(7, 12) //[18:12]
+    #define SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA                    Fld(1, 20) //[20:20]
+    #define SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA                     Fld(1, 21) //[21:21]
+    #define SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA                    Fld(2, 22) //[23:22]
+    #define SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CA_CA       Fld(1, 24) //[24:24]
+    #define SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CLK_CA      Fld(1, 25) //[25:25]
+    #define SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA              Fld(1, 26) //[26:26]
+    #define SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA             Fld(1, 27) //[27:27]
+    #define SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA                   Fld(1, 28) //[28:28]
+    #define SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE          Fld(1, 29) //[29:29]
+
+#define DDRPHY_REG_SHU_CA_CMD1                                 (DDRPHY_AO_BASE_ADDRESS + 0x0B74)
+    #define SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA                    Fld(1, 0) //[0:0]
+    #define SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA      Fld(1, 1) //[1:1]
+    #define SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA             Fld(1, 2) //[2:2]
+    #define SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA               Fld(5, 8) //[12:8]
+    #define SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA          Fld(2, 16) //[17:16]
+    #define SHU_CA_CMD1_RG_ARPI_MIDPI_CAP_SEL_CA               Fld(2, 22) //[23:22]
+    #define SHU_CA_CMD1_RG_ARPI_MIDPI_VTH_SEL_CA               Fld(2, 24) //[25:24]
+    #define SHU_CA_CMD1_RG_ARPI_8PHASE_XLATCH_FORCE_CA         Fld(1, 26) //[26:26]
+    #define SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA              Fld(1, 27) //[27:27]
+    #define SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA             Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_CA_CMD2                                 (DDRPHY_AO_BASE_ADDRESS + 0x0B78)
+    #define SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA              Fld(1, 0) //[0:0]
+    #define SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA                 Fld(1, 4) //[4:4]
+    #define SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA                Fld(1, 5) //[5:5]
+    #define SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA                 Fld(1, 6) //[6:6]
+    #define SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA        Fld(1, 8) //[8:8]
+    #define SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA         Fld(1, 9) //[9:9]
+    #define SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA       Fld(1, 10) //[10:10]
+    #define SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA      Fld(1, 11) //[11:11]
+    #define SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU               Fld(1, 12) //[12:12]
+    #define SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA                 Fld(1, 13) //[13:13]
+    #define SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA               Fld(1, 16) //[16:16]
+    #define SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA             Fld(1, 17) //[17:17]
+
+#define DDRPHY_REG_SHU_CA_CMD10                                (DDRPHY_AO_BASE_ADDRESS + 0x0B7C)
+    #define SHU_CA_CMD10_RG_RX_ARCLK_SE_EN_CA                  Fld(1, 0) //[0:0]
+    #define SHU_CA_CMD10_RG_RX_ARCLK_DQSSTB_CG_EN_CA           Fld(1, 1) //[1:1]
+    #define SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_RANK_SEL_LAT_EN_CA Fld(1, 2) //[2:2]
+    #define SHU_CA_CMD10_RG_RX_ARCLK_RANK_SEL_LAT_EN_CA        Fld(1, 3) //[3:3]
+    #define SHU_CA_CMD10_RG_RX_ARCLK_DQSSTB_RPST_HS_EN_CA      Fld(1, 4) //[4:4]
+    #define SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_MODE_CA            Fld(3, 8) //[10:8]
+    #define SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA             Fld(1, 15) //[15:15]
+    #define SHU_CA_CMD10_RG_RX_ARCLK_DIFF_SWAP_EN_CA           Fld(1, 16) //[16:16]
+    #define SHU_CA_CMD10_RG_RX_ARCLK_BW_SEL_CA                 Fld(2, 18) //[19:18]
+
+#define DDRPHY_REG_SHU_CA_CMD11                                (DDRPHY_AO_BASE_ADDRESS + 0x0B80)
+    #define SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA         Fld(1, 0) //[0:0]
+    #define SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA         Fld(1, 1) //[1:1]
+    #define SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA          Fld(1, 2) //[2:2]
+    #define SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA              Fld(1, 3) //[3:3]
+    #define SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA         Fld(1, 4) //[4:4]
+    #define SHU_CA_CMD11_RG_RX_ARCA_FRATE_EN_CA                Fld(1, 5) //[5:5]
+    #define SHU_CA_CMD11_RG_RX_ARCA_CDR_EN_CA                  Fld(1, 6) //[6:6]
+    #define SHU_CA_CMD11_RG_RX_ARCA_DVS_EN_CA                  Fld(1, 7) //[7:7]
+    #define SHU_CA_CMD11_RG_RX_ARCA_DVS_DLY_CA                 Fld(4, 8) //[11:8]
+    #define SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA                Fld(2, 16) //[17:16]
+    #define SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA                  Fld(2, 18) //[19:18]
+
+#define DDRPHY_REG_SHU_CA_CMD7                                 (DDRPHY_AO_BASE_ADDRESS + 0x0B84)
+    #define SHU_CA_CMD7_R_DMRANKRXDVS_CA                       Fld(4, 0) //[3:0]
+    #define SHU_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA            Fld(1, 12) //[12:12]
+    #define SHU_CA_CMD7_R_DMRODTEN_CA                          Fld(1, 15) //[15:15]
+    #define SHU_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA           Fld(1, 16) //[16:16]
+    #define SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW                 Fld(1, 17) //[17:17]
+    #define SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW                  Fld(1, 19) //[19:19]
+    #define SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK                    Fld(1, 20) //[20:20]
+    #define SHU_CA_CMD7_R_DMRXRANK_CMD_EN                      Fld(1, 24) //[24:24]
+    #define SHU_CA_CMD7_R_DMRXRANK_CMD_LAT                     Fld(3, 25) //[27:25]
+    #define SHU_CA_CMD7_R_DMRXRANK_CLK_EN                      Fld(1, 28) //[28:28]
+    #define SHU_CA_CMD7_R_DMRXRANK_CLK_LAT                     Fld(3, 29) //[31:29]
+
+#define DDRPHY_REG_SHU_CA_CMD8                                 (DDRPHY_AO_BASE_ADDRESS + 0x0B88)
+    #define SHU_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA             Fld(15, 0) //[14:0]
+    #define SHU_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA              Fld(1, 15) //[15:15]
+    #define SHU_CA_CMD8_R_DMRANK_RXDLY_PIPE_CG_IG_CA           Fld(1, 19) //[19:19]
+    #define SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA                    Fld(1, 20) //[20:20]
+    #define SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA                  Fld(1, 21) //[21:21]
+    #define SHU_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA          Fld(1, 22) //[22:22]
+    #define SHU_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA      Fld(1, 23) //[23:23]
+    #define SHU_CA_CMD8_R_DMRXDLY_CG_IG_CA                     Fld(1, 24) //[24:24]
+    #define SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA          Fld(1, 26) //[26:26]
+    #define SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA          Fld(1, 27) //[27:27]
+    #define SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA         Fld(1, 28) //[28:28]
+    #define SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA     Fld(1, 29) //[29:29]
+    #define SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA                 Fld(1, 30) //[30:30]
+    #define SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA             Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_CA_CMD9                                 (DDRPHY_AO_BASE_ADDRESS + 0x0B8C)
+    #define SHU_CA_CMD9_RG_ARPI_RESERVE_CA                     Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_SHU_CA_CMD12                                (DDRPHY_AO_BASE_ADDRESS + 0x0B90)
+    #define SHU_CA_CMD12_RG_RIMP_REV                           Fld(8, 0) //[7:0]
+    #define SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN                 Fld(7, 8) //[14:8]
+    #define SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN                 Fld(7, 16) //[22:16]
+    #define SHU_CA_CMD12_RG_RIMP_DRV05                         Fld(1, 23) //[23:23]
+    #define SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP                 Fld(7, 24) //[30:24]
+    #define SHU_CA_CMD12_RG_RIMP_UNTERM_EN                     Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_CA_DLL0                                 (DDRPHY_AO_BASE_ADDRESS + 0x0B94)
+    #define SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_CA            Fld(3, 0) //[2:0]
+    #define SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_CA            Fld(3, 4) //[6:4]
+    #define SHU_CA_DLL0_RG_ARDLL_LCK_DET_EN_CA                 Fld(1, 8) //[8:8]
+    #define SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA                    Fld(4, 12) //[15:12]
+    #define SHU_CA_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_CA            Fld(1, 16) //[16:16]
+    #define SHU_CA_DLL0_RG_ARDLL_GAIN_BOOST_CA                 Fld(3, 17) //[19:17]
+    #define SHU_CA_DLL0_RG_ARDLL_GAIN_CA                       Fld(4, 20) //[23:20]
+    #define SHU_CA_DLL0_RG_ARDLL_FAST_DIV_EN_CA                Fld(1, 24) //[24:24]
+    #define SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA                  Fld(1, 25) //[25:25]
+    #define SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA              Fld(1, 26) //[26:26]
+    #define SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA                 Fld(1, 27) //[27:27]
+
+#define DDRPHY_REG_SHU_CA_DLL1                                 (DDRPHY_AO_BASE_ADDRESS + 0x0B98)
+    #define SHU_CA_DLL1_RG_ARDLL_AD_ARFB_CK_EN_CA              Fld(1, 0) //[0:0]
+    #define SHU_CA_DLL1_RG_ARDLL_DIV_MODE_CA                   Fld(2, 2) //[3:2]
+    #define SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA                    Fld(1, 4) //[4:4]
+    #define SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_CA          Fld(1, 5) //[5:5]
+    #define SHU_CA_DLL1_RG_ARDLL_TRACKING_CA_EN_CA             Fld(1, 6) //[6:6]
+    #define SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_CA        Fld(1, 7) //[7:7]
+    #define SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA                   Fld(2, 8) //[9:8]
+    #define SHU_CA_DLL1_RG_ARDLL_PS_EN_CA                      Fld(1, 10) //[10:10]
+    #define SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA                    Fld(1, 11) //[11:11]
+    #define SHU_CA_DLL1_RG_ARDLL_PHDIV_CA                      Fld(1, 12) //[12:12]
+    #define SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA              Fld(1, 13) //[13:13]
+    #define SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA              Fld(1, 14) //[14:14]
+    #define SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA                   Fld(1, 16) //[16:16]
+    #define SHU_CA_DLL1_RG_ARDLL_DIV_MCTL_CA                   Fld(2, 18) //[19:18]
+    #define SHU_CA_DLL1_RG_ARDLL_PGAIN_CA                      Fld(4, 20) //[23:20]
+    #define SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA                  Fld(1, 24) //[24:24]
+
+#define DDRPHY_REG_SHU_CA_DLL2                                 (DDRPHY_AO_BASE_ADDRESS + 0x0B9C)
+    #define SHU_CA_DLL2_RG_ARCMD_REV                           Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_SHU_CA_RANK_SELPH_UI_DLY                    (DDRPHY_AO_BASE_ADDRESS + 0x0BA0)
+    #define SHU_CA_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P0_CA      Fld(3, 0) //[2:0]
+    #define SHU_CA_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P1_CA      Fld(3, 4) //[6:4]
+    #define SHU_CA_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_CA     Fld(3, 16) //[18:16]
+    #define SHU_CA_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_CA     Fld(3, 20) //[22:20]
+
+#define DDRPHY_REG_SHU_CA_DLL_ARPI2                            (DDRPHY_AO_BASE_ADDRESS + 0x0BA4)
+    #define SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA               Fld(1, 10) //[10:10]
+    #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN                 Fld(1, 11) //[11:11]
+    #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD                    Fld(1, 13) //[13:13]
+    #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK                    Fld(1, 15) //[15:15]
+    #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS                     Fld(1, 16) //[16:16]
+    #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA                  Fld(1, 17) //[17:17]
+    #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA                Fld(1, 19) //[19:19]
+    #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA          Fld(1, 27) //[27:27]
+    #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA                 Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_CA_DLL_ARPI3                            (DDRPHY_AO_BASE_ADDRESS + 0x0BA8)
+    #define SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN                 Fld(1, 11) //[11:11]
+    #define SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN                    Fld(1, 13) //[13:13]
+    #define SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN                    Fld(1, 15) //[15:15]
+    #define SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN                     Fld(1, 16) //[16:16]
+    #define SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA                  Fld(1, 17) //[17:17]
+    #define SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA                Fld(1, 19) //[19:19]
+
+#define DDRPHY_REG_SHU_CA_TXDUTY                               (DDRPHY_AO_BASE_ADDRESS + 0x0BAC)
+    #define SHU_CA_TXDUTY_DA_TX_ARCA_DUTY_DLY                  Fld(6, 0) //[5:0]
+    #define SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY                 Fld(6, 8) //[13:8]
+    #define SHU_CA_TXDUTY_DA_TX_ARCS_DUTY_DLY                  Fld(6, 16) //[21:16]
+
+#define DDRPHY_REG_SHU_CA_VREF                                 (DDRPHY_AO_BASE_ADDRESS + 0x0BB0)
+    #define SHU_CA_VREF_RG_RX_ARCA_VREF_SEL_CLK_CA             Fld(7, 0) //[6:0]
+    #define SHU_CA_VREF_RG_RX_ARCA_VREF_RANK_SEL_EN_CA         Fld(1, 16) //[16:16]
+    #define SHU_CA_VREF_RG_RX_ARCA_VREF_EN_UB_RK1_CA           Fld(1, 17) //[17:17]
+    #define SHU_CA_VREF_RG_RX_ARCA_VREF_EN_UB_RK0_CA           Fld(1, 18) //[18:18]
+    #define SHU_CA_VREF_RG_RX_ARCA_VREF_EN_LB_RK1_CA           Fld(1, 19) //[19:19]
+    #define SHU_CA_VREF_RG_RX_ARCA_VREF_EN_LB_RK0_CA           Fld(1, 20) //[20:20]
+    #define SHU_CA_VREF_RG_RX_ARCA_VREF_EN_CLK_CA              Fld(1, 21) //[21:21]
+    #define SHU_CA_VREF_RG_RX_ARCA_VREF_UNTERM_EN_CA           Fld(1, 22) //[22:22]
+
+#define DDRPHY_REG_SHU_CA_CMD13                                (DDRPHY_AO_BASE_ADDRESS + 0x0BB4)
+    #define SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA              Fld(1, 0) //[0:0]
+    #define SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA                Fld(1, 1) //[1:1]
+    #define SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA              Fld(1, 2) //[2:2]
+    #define SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_EN_CA           Fld(1, 3) //[3:3]
+    #define SHU_CA_CMD13_RG_TX_ARCLK_PRE_DATA_SEL_CA           Fld(1, 5) //[5:5]
+    #define SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_SWAP_CA          Fld(1, 6) //[6:6]
+    #define SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA         Fld(1, 7) //[7:7]
+    #define SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_CG_CA               Fld(1, 8) //[8:8]
+    #define SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_SEL_CA              Fld(2, 12) //[13:12]
+    #define SHU_CA_CMD13_RG_TX_ARCS_MCKIO_SEL_CA               Fld(1, 14) //[14:14]
+    #define SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_EN_CA          Fld(1, 15) //[15:15]
+    #define SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA          Fld(1, 16) //[16:16]
+    #define SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA Fld(1, 17) //[17:17]
+    #define SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_DATA_TIE_EN_CA  Fld(1, 18) //[18:18]
+    #define SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_EN_CA            Fld(1, 19) //[19:19]
+    #define SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_DATA_TIE_EN_CA   Fld(1, 20) //[20:20]
+    #define SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA            Fld(1, 24) //[24:24]
+    #define SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA             Fld(1, 25) //[25:25]
+    #define SHU_CA_CMD13_RG_TX_ARCLK_SER_READ_BASE_EN_C0       Fld(1, 26) //[26:26]
+
+#define DDRPHY_REG_SHU_CA_CMD14                                (DDRPHY_AO_BASE_ADDRESS + 0x0BB8)
+    #define SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA                Fld(2, 4) //[5:4]
+    #define SHU_CA_CMD14_RG_TX_ARCA_AUX_SER_MODE_CA            Fld(1, 6) //[6:6]
+    #define SHU_CA_CMD14_RG_TX_ARCA_PRE_DATA_SEL_CA            Fld(1, 9) //[9:9]
+    #define SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_SWAP_CA           Fld(1, 10) //[10:10]
+    #define SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA          Fld(1, 11) //[11:11]
+    #define SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA               Fld(8, 16) //[23:16]
+
+#define DDRPHY_REG_CA_SHU_MIDPI_CTRL                           (DDRPHY_AO_BASE_ADDRESS + 0x0BBC)
+    #define CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA                  Fld(1, 0) //[0:0]
+    #define CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA             Fld(1, 1) //[1:1]
+
+#define DDRPHY_REG_SHU_CA_LPBK_CTRL                            (DDRPHY_AO_BASE_ADDRESS + 0x0BC0)
+    #define SHU_CA_LPBK_CTRL_RG_RX_ART2RLPBK_CLK_SEL_C0        Fld(2, 0) //[1:0]
+    #define SHU_CA_LPBK_CTRL_RG_TX_ARCA_LPBK_SEL_C0            Fld(2, 2) //[3:2]
+    #define SHU_CA_LPBK_CTRL_RG_TX_ARCLK_LPBK_EN_C0            Fld(1, 4) //[4:4]
+
+#define DDRPHY_REG_SHU_CA_DQSIEN_CFG                           (DDRPHY_AO_BASE_ADDRESS + 0x0BC4)
+    #define SHU_CA_DQSIEN_CFG_RG_RX_ARCLK_DQSIEN_GLITCH_FREE_EN_C0 Fld(1, 0) //[0:0]
+    #define SHU_CA_DQSIEN_CFG_RG_RX_ARCLK_DQSIEN_FORCE_ON_EN_C0 Fld(1, 1) //[1:1]
+
+#define DDRPHY_REG_SHU_CA_CS_CTRL                              (DDRPHY_AO_BASE_ADDRESS + 0x0BC8)
+    #define SHU_CA_CS_CTRL_RG_TX_ARCS_OE_ODTEN_CG_EN_C0        Fld(1, 0) //[0:0]
+    #define SHU_CA_CS_CTRL_RG_TX_ARCS_MCKIO_SEL_C0             Fld(1, 1) //[1:1]
+    #define SHU_CA_CS_CTRL_RG_TX_ARCS_DRVN_C0                  Fld(5, 4) //[8:4]
+    #define SHU_CA_CS_CTRL_RG_TX_ARCS_DRVP_C0                  Fld(5, 12) //[16:12]
+    #define SHU_CA_CS_CTRL_RG_TX_ARCS_ODTN_C0                  Fld(5, 20) //[24:20]
+    #define SHU_CA_CS_CTRL_RG_TX_ARCS_DUTY_DLY_C0              Fld(6, 25) //[30:25]
+
+#define DDRPHY_REG_SHU_CA_DQ_DLY                               (DDRPHY_AO_BASE_ADDRESS + 0x0BCC)
+    #define SHU_CA_DQ_DLY_RG_TX_ARDQ6_DLY_C0                   Fld(8, 0) //[7:0]
+    #define SHU_CA_DQ_DLY_RG_TX_ARDQ7_DLY_C0                   Fld(8, 8) //[15:8]
+
+#define DDRPHY_REG_MISC_SHU_RK_DQSCTL                          (DDRPHY_AO_BASE_ADDRESS + 0x0BE0)
+    #define MISC_SHU_RK_DQSCTL_DQSINCTL                        Fld(4, 0) //[3:0]
+
+#define DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL                (DDRPHY_AO_BASE_ADDRESS + 0x0BE4)
+    #define MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT Fld(3, 0) //[2:0]
+    #define MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT Fld(3, 4) //[6:4]
+
+#define DDRPHY_REG_MISC_SHU_RK_DQSCAL                          (DDRPHY_AO_BASE_ADDRESS + 0x0BE8)
+    #define MISC_SHU_RK_DQSCAL_DQSIENLLMT                      Fld(7, 0) //[6:0]
+    #define MISC_SHU_RK_DQSCAL_DQSIENLLMTEN                    Fld(1, 7) //[7:7]
+    #define MISC_SHU_RK_DQSCAL_DQSIENHLMT                      Fld(7, 8) //[14:8]
+    #define MISC_SHU_RK_DQSCAL_DQSIENHLMTEN                    Fld(1, 15) //[15:15]
+
+#define DDRPHY_REG_MISC_SHU_DRVING7                            (DDRPHY_AO_BASE_ADDRESS + 0x0CE0)
+    #define MISC_SHU_DRVING7_WCK0_DRVN                         Fld(5, 0) //[4:0]
+    #define MISC_SHU_DRVING7_WCK0_DRVP                         Fld(5, 8) //[12:8]
+    #define MISC_SHU_DRVING7_WCK1_DRVN                         Fld(5, 16) //[20:16]
+    #define MISC_SHU_DRVING7_WCK1_DRVP                         Fld(5, 24) //[28:24]
+
+#define DDRPHY_REG_MISC_SHU_DRVING8                            (DDRPHY_AO_BASE_ADDRESS + 0x0CE4)
+    #define MISC_SHU_DRVING8_CS_DRVN                           Fld(5, 0) //[4:0]
+    #define MISC_SHU_DRVING8_CS_DRVP                           Fld(5, 8) //[12:8]
+
+#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET1                  (DDRPHY_AO_BASE_ADDRESS + 0x0CE8)
+    #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_DRVP_OFF           Fld(5, 0) //[4:0]
+    #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_DRVP_OFF_SUB       Fld(1, 7) //[7:7]
+    #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_DRVN_OFF           Fld(5, 8) //[12:8]
+    #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_DRVN_OFF_SUB       Fld(1, 15) //[15:15]
+    #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_ODTN_OFF           Fld(5, 16) //[20:16]
+    #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_ODTN_OFF_SUB       Fld(1, 23) //[23:23]
+
+#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET2                  (DDRPHY_AO_BASE_ADDRESS + 0x0CEC)
+    #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_DRVP_OFF           Fld(5, 0) //[4:0]
+    #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_DRVP_OFF_SUB       Fld(1, 7) //[7:7]
+    #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_DRVN_OFF           Fld(5, 8) //[12:8]
+    #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_DRVN_OFF_SUB       Fld(1, 15) //[15:15]
+    #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_ODTN_OFF           Fld(5, 16) //[20:16]
+    #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_ODTN_OFF_SUB       Fld(1, 23) //[23:23]
+
+#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET3                  (DDRPHY_AO_BASE_ADDRESS + 0x0CF0)
+    #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_DRVP_OFF            Fld(5, 0) //[4:0]
+    #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_DRVP_OFF_SUB        Fld(1, 7) //[7:7]
+    #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_DRVN_OFF            Fld(5, 8) //[12:8]
+    #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_DRVN_OFF_SUB        Fld(1, 15) //[15:15]
+    #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_ODTN_OFF            Fld(5, 16) //[20:16]
+    #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_ODTN_OFF_SUB        Fld(1, 23) //[23:23]
+
+#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET4                  (DDRPHY_AO_BASE_ADDRESS + 0x0CF4)
+    #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_DRVP_OFF            Fld(5, 0) //[4:0]
+    #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_DRVP_OFF_SUB        Fld(1, 7) //[7:7]
+    #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_DRVN_OFF            Fld(5, 8) //[12:8]
+    #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_DRVN_OFF_SUB        Fld(1, 15) //[15:15]
+    #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_ODTN_OFF            Fld(5, 16) //[20:16]
+    #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_ODTN_OFF_SUB        Fld(1, 23) //[23:23]
+
+#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET5                  (DDRPHY_AO_BASE_ADDRESS + 0x0CF8)
+    #define MISC_SHU_IMPEDAMCE_OFFSET5_WCK0_DRVP_OFF           Fld(5, 0) //[4:0]
+    #define MISC_SHU_IMPEDAMCE_OFFSET5_WCK0_DRVP_OFF_SUB       Fld(1, 7) //[7:7]
+    #define MISC_SHU_IMPEDAMCE_OFFSET5_WCK0_DRVN_OFF           Fld(5, 8) //[12:8]
+    #define MISC_SHU_IMPEDAMCE_OFFSET5_WCK0_DRVN_OFF_SUB       Fld(1, 15) //[15:15]
+
+#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET6                  (DDRPHY_AO_BASE_ADDRESS + 0x0CFC)
+    #define MISC_SHU_IMPEDAMCE_OFFSET6_WCK1_DRVP_OFF           Fld(5, 0) //[4:0]
+    #define MISC_SHU_IMPEDAMCE_OFFSET6_WCK1_DRVP_OFF_SUB       Fld(1, 7) //[7:7]
+    #define MISC_SHU_IMPEDAMCE_OFFSET6_WCK1_DRVN_OFF           Fld(5, 8) //[12:8]
+    #define MISC_SHU_IMPEDAMCE_OFFSET6_WCK1_DRVN_OFF_SUB       Fld(1, 15) //[15:15]
+
+#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET7                  (DDRPHY_AO_BASE_ADDRESS + 0x0D00)
+    #define MISC_SHU_IMPEDAMCE_OFFSET7_CS_DRVP_OFF             Fld(5, 0) //[4:0]
+    #define MISC_SHU_IMPEDAMCE_OFFSET7_CS_DRVP_OFF_SUB         Fld(1, 7) //[7:7]
+    #define MISC_SHU_IMPEDAMCE_OFFSET7_CS_DRVN_OFF             Fld(5, 8) //[12:8]
+    #define MISC_SHU_IMPEDAMCE_OFFSET7_CS_DRVN_OFF_SUB         Fld(1, 15) //[15:15]
+
+#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET8                  (DDRPHY_AO_BASE_ADDRESS + 0x0D04)
+    #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_DRVP_OFF           Fld(5, 0) //[4:0]
+    #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_DRVP_OFF_SUB       Fld(1, 7) //[7:7]
+    #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_DRVN_OFF           Fld(5, 8) //[12:8]
+    #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_DRVN_OFF_SUB       Fld(1, 15) //[15:15]
+    #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_ODTN_OFF           Fld(5, 16) //[20:16]
+    #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_ODTN_OFF_SUB       Fld(1, 23) //[23:23]
+
+#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET9                  (DDRPHY_AO_BASE_ADDRESS + 0x0D08)
+    #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_DRVP_OFF           Fld(5, 0) //[4:0]
+    #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_DRVP_OFF_SUB       Fld(1, 7) //[7:7]
+    #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_DRVN_OFF           Fld(5, 8) //[12:8]
+    #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_DRVN_OFF_SUB       Fld(1, 15) //[15:15]
+    #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_ODTN_OFF           Fld(5, 16) //[20:16]
+    #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_ODTN_OFF_SUB       Fld(1, 23) //[23:23]
+
+#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1                 (DDRPHY_AO_BASE_ADDRESS + 0x0D0C)
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVP_UPD_DIS       Fld(1, 0) //[0:0]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVN_UPD_DIS       Fld(1, 1) //[1:1]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_ODTN_UPD_DIS       Fld(1, 2) //[2:2]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVP_UPD_DIS        Fld(1, 4) //[4:4]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVN_UPD_DIS        Fld(1, 5) //[5:5]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_ODTN_UPD_DIS        Fld(1, 6) //[6:6]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS       Fld(1, 8) //[8:8]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS       Fld(1, 9) //[9:9]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS       Fld(1, 10) //[10:10]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVP_UPD_DIS        Fld(1, 12) //[12:12]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVN_UPD_DIS        Fld(1, 13) //[13:13]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_ODTN_UPD_DIS        Fld(1, 14) //[14:14]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVP_UPD_DIS      Fld(1, 16) //[16:16]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVN_UPD_DIS      Fld(1, 17) //[17:17]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_ODTN_UPD_DIS      Fld(1, 18) //[18:18]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVP_UPD_DIS      Fld(1, 20) //[20:20]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVN_UPD_DIS      Fld(1, 21) //[21:21]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_ODTN_UPD_DIS      Fld(1, 22) //[22:22]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVP_UPD_DIS           Fld(1, 28) //[28:28]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVN_UPD_DIS           Fld(1, 29) //[29:29]
+    #define MISC_SHU_IMPEDAMCE_UPD_DIS1_ODTN_UPD_DIS           Fld(1, 30) //[30:30]
+
+#define DDRPHY_REG_SHU_MISC_SW_IMPCAL                          (DDRPHY_AO_BASE_ADDRESS + 0x0D10)
+    #define SHU_MISC_SW_IMPCAL_IMPODTN                         Fld(5, 16) //[20:16]
+
+#define DDRPHY_REG_MISC_SHU_STBCAL                             (DDRPHY_AO_BASE_ADDRESS + 0x0D14)
+    #define MISC_SHU_STBCAL_DMSTBLAT                           Fld(4, 0) //[3:0]
+    #define MISC_SHU_STBCAL_PICGLAT                            Fld(3, 4) //[6:4]
+    #define MISC_SHU_STBCAL_DQSG_MODE                          Fld(1, 8) //[8:8]
+    #define MISC_SHU_STBCAL_DQSIEN_PICG_MODE                   Fld(1, 9) //[9:9]
+    #define MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE                 Fld(2, 12) //[13:12]
+    #define MISC_SHU_STBCAL_DQSIEN_BURST_MODE                  Fld(1, 14) //[14:14]
+    #define MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN                  Fld(1, 15) //[15:15]
+    #define MISC_SHU_STBCAL_STBCALEN                           Fld(1, 16) //[16:16]
+    #define MISC_SHU_STBCAL_STB_SELPHCALEN                     Fld(1, 17) //[17:17]
+    #define MISC_SHU_STBCAL_DQSIEN_4TO1_EN                     Fld(1, 20) //[20:20]
+    #define MISC_SHU_STBCAL_DQSIEN_8TO1_EN                     Fld(1, 21) //[21:21]
+    #define MISC_SHU_STBCAL_DQSIEN_16TO1_EN                    Fld(1, 22) //[22:22]
+
+#define DDRPHY_REG_MISC_SHU_STBCAL1                            (DDRPHY_AO_BASE_ADDRESS + 0x0D18)
+    #define MISC_SHU_STBCAL1_DLLFRZRFCOPT                      Fld(2, 0) //[1:0]
+    #define MISC_SHU_STBCAL1_DLLFRZWROPT                       Fld(2, 4) //[5:4]
+    #define MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT               Fld(3, 8) //[10:8]
+    #define MISC_SHU_STBCAL1_STB_UPDMASK_EN                    Fld(1, 11) //[11:11]
+    #define MISC_SHU_STBCAL1_STB_UPDMASKCYC                    Fld(4, 12) //[15:12]
+    #define MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL                  Fld(1, 16) //[16:16]
+    #define MISC_SHU_STBCAL1_STB_PI_TRACKING_RATIO             Fld(6, 20) //[25:20]
+
+#define DDRPHY_REG_MISC_SHU_DVFSDLL                            (DDRPHY_AO_BASE_ADDRESS + 0x0D1C)
+    #define MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL                  Fld(1, 0) //[0:0]
+    #define MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL                  Fld(1, 1) //[1:1]
+    #define MISC_SHU_DVFSDLL_R_DLL_IDLE                        Fld(7, 4) //[10:4]
+    #define MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE                    Fld(7, 16) //[22:16]
+
+#define DDRPHY_REG_MISC_SHU_RANKCTL                            (DDRPHY_AO_BASE_ADDRESS + 0x0D20)
+    #define MISC_SHU_RANKCTL_RANKINCTL_RXDLY                   Fld(4, 0) //[3:0]
+    #define MISC_SHU_RANKCTL_RANK_RXDLY_OPT                    Fld(1, 4) //[4:4]
+    #define MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN                Fld(1, 15) //[15:15]
+    #define MISC_SHU_RANKCTL_RANKINCTL_STB                     Fld(4, 16) //[19:16]
+    #define MISC_SHU_RANKCTL_RANKINCTL                         Fld(4, 20) //[23:20]
+    #define MISC_SHU_RANKCTL_RANKINCTL_ROOT1                   Fld(4, 24) //[27:24]
+    #define MISC_SHU_RANKCTL_RANKINCTL_PHY                     Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_MISC_SHU_PHY_RX_CTRL                        (DDRPHY_AO_BASE_ADDRESS + 0x0D24)
+    #define MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN          Fld(1, 8) //[8:8]
+    #define MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET         Fld(3, 9) //[11:9]
+    #define MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET      Fld(2, 14) //[15:14]
+    #define MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD            Fld(3, 16) //[18:16]
+    #define MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL            Fld(3, 20) //[22:20]
+    #define MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD            Fld(3, 24) //[26:24]
+    #define MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL            Fld(3, 28) //[30:28]
+
+#define DDRPHY_REG_MISC_SHU_ODTCTRL                            (DDRPHY_AO_BASE_ADDRESS + 0x0D28)
+    #define MISC_SHU_ODTCTRL_RODTEN                            Fld(1, 0) //[0:0]
+    #define MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG             Fld(1, 1) //[1:1]
+    #define MISC_SHU_ODTCTRL_RODT_LAT                          Fld(4, 4) //[7:4]
+    #define MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN                 Fld(1, 15) //[15:15]
+    #define MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT                   Fld(2, 24) //[25:24]
+    #define MISC_SHU_ODTCTRL_FIXRODT                           Fld(1, 27) //[27:27]
+    #define MISC_SHU_ODTCTRL_RODTEN_OPT                        Fld(1, 29) //[29:29]
+    #define MISC_SHU_ODTCTRL_RODTE2                            Fld(1, 30) //[30:30]
+    #define MISC_SHU_ODTCTRL_RODTE                             Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_SHU_RODTENSTB                          (DDRPHY_AO_BASE_ADDRESS + 0x0D2C)
+    #define MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN              Fld(1, 0) //[0:0]
+    #define MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE                Fld(1, 1) //[1:1]
+    #define MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN              Fld(1, 2) //[2:2]
+    #define MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL       Fld(1, 3) //[3:3]
+    #define MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE            Fld(1, 4) //[4:4]
+    #define MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME      Fld(1, 5) //[5:5]
+    #define MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET            Fld(4, 8) //[11:8]
+    #define MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET            Fld(4, 12) //[15:12]
+    #define MISC_SHU_RODTENSTB_RODTENSTB_EXT                   Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_MISC_SHU_RODTENSTB1                         (DDRPHY_AO_BASE_ADDRESS + 0x0D30)
+    #define MISC_SHU_RODTENSTB1_RODTENCGEN_HEAD                Fld(2, 4) //[5:4]
+    #define MISC_SHU_RODTENSTB1_RODTENCGEN_TAIL                Fld(2, 6) //[7:6]
+
+#define DDRPHY_REG_MISC_SHU_DQSG_RETRY1                        (DDRPHY_AO_BASE_ADDRESS + 0x0D34)
+    #define MISC_SHU_DQSG_RETRY1_RETRY_SW_RESET                Fld(1, 0) //[0:0]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_SW_EN                   Fld(1, 1) //[1:1]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS            Fld(1, 2) //[2:2]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_ONCE                    Fld(1, 3) //[3:3]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_3TIMES                  Fld(1, 4) //[4:4]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_1RANK                   Fld(1, 5) //[5:5]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_BY_RANK                 Fld(1, 6) //[6:6]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_DM4BYTE                 Fld(1, 7) //[7:7]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_DQSIENLAT               Fld(4, 8) //[11:8]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_STBENCMP_ALLBYTE        Fld(1, 12) //[12:12]
+    #define MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN             Fld(1, 13) //[13:13]
+    #define MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE            Fld(1, 14) //[14:14]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_CMP_DATA                Fld(1, 15) //[15:15]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_ALE_BLOCK_MASK          Fld(1, 20) //[20:20]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE             Fld(1, 21) //[21:21]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_USE_NON_EXTEND          Fld(1, 22) //[22:22]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_USE_CG_GATING           Fld(1, 23) //[23:23]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM               Fld(2, 24) //[25:24]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_RANKSEL_FROM_PHY        Fld(1, 28) //[28:28]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_PA_DISABLE              Fld(1, 29) //[29:29]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_STBEN_RESET_MSK         Fld(1, 30) //[30:30]
+    #define MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE          Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_SHU_RDAT                               (DDRPHY_AO_BASE_ADDRESS + 0x0D38)
+    #define MISC_SHU_RDAT_DATLAT                               Fld(5, 0) //[4:0]
+    #define MISC_SHU_RDAT_DATLAT_DSEL                          Fld(5, 8) //[12:8]
+    #define MISC_SHU_RDAT_DATLAT_DSEL_PHY                      Fld(5, 16) //[20:16]
+
+#define DDRPHY_REG_MISC_SHU_RDAT1                              (DDRPHY_AO_BASE_ADDRESS + 0x0D3C)
+    #define MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT                  Fld(1, 0) //[0:0]
+    #define MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT                Fld(1, 1) //[1:1]
+    #define MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT                Fld(1, 2) //[2:2]
+    #define MISC_SHU_RDAT1_RDATDIV2                            Fld(1, 4) //[4:4]
+    #define MISC_SHU_RDAT1_RDATDIV4                            Fld(1, 5) //[5:5]
+
+#define DDRPHY_REG_SHU_MISC_CLK_CTRL0                          (DDRPHY_AO_BASE_ADDRESS + 0x0D40)
+    #define SHU_MISC_CLK_CTRL0_FMEM_CK_CG_DRAMC_DLL_DIS        Fld(1, 0) //[0:0]
+    #define SHU_MISC_CLK_CTRL0_RESERVED_MISC_CLK_CTRL0_BIT3_1  Fld(3, 1) //[3:1]
+    #define SHU_MISC_CLK_CTRL0_M_CK_OPENLOOP_MODE_SEL          Fld(1, 4) //[4:4]
+    #define SHU_MISC_CLK_CTRL0_RESERVED_MISC_CLK_CTRL0_BIT31_5 Fld(27, 5) //[31:5]
+
+#define DDRPHY_REG_SHU_MISC_IMPCAL1                            (DDRPHY_AO_BASE_ADDRESS + 0x0D44)
+    #define SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE                   Fld(3, 0) //[2:0]
+    #define SHU_MISC_IMPCAL1_IMPDRVP                           Fld(5, 4) //[8:4]
+    #define SHU_MISC_IMPCAL1_IMPDRVN                           Fld(5, 12) //[16:12]
+    #define SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE                Fld(3, 17) //[19:17]
+    #define SHU_MISC_IMPCAL1_IMPCALCNT                         Fld(8, 20) //[27:20]
+    #define SHU_MISC_IMPCAL1_IMPCAL_CALICNT                    Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_SHU_MISC_DRVING1                            (DDRPHY_AO_BASE_ADDRESS + 0x0D48)
+    #define SHU_MISC_DRVING1_DQDRVN2                           Fld(5, 0) //[4:0]
+    #define SHU_MISC_DRVING1_DQDRVP2                           Fld(5, 5) //[9:5]
+    #define SHU_MISC_DRVING1_DQSDRVN1                          Fld(5, 10) //[14:10]
+    #define SHU_MISC_DRVING1_DQSDRVP1                          Fld(5, 15) //[19:15]
+    #define SHU_MISC_DRVING1_DQSDRVN2                          Fld(5, 20) //[24:20]
+    #define SHU_MISC_DRVING1_DQSDRVP2                          Fld(5, 25) //[29:25]
+    #define SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK                Fld(1, 30) //[30:30]
+    #define SHU_MISC_DRVING1_DIS_IMPCAL_HW                     Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_MISC_DRVING2                            (DDRPHY_AO_BASE_ADDRESS + 0x0D4C)
+    #define SHU_MISC_DRVING2_CMDDRVN1                          Fld(5, 0) //[4:0]
+    #define SHU_MISC_DRVING2_CMDDRVP1                          Fld(5, 5) //[9:5]
+    #define SHU_MISC_DRVING2_CMDDRVN2                          Fld(5, 10) //[14:10]
+    #define SHU_MISC_DRVING2_CMDDRVP2                          Fld(5, 15) //[19:15]
+    #define SHU_MISC_DRVING2_DQDRVN1                           Fld(5, 20) //[24:20]
+    #define SHU_MISC_DRVING2_DQDRVP1                           Fld(5, 25) //[29:25]
+    #define SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN                 Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_SHU_MISC_DRVING3                            (DDRPHY_AO_BASE_ADDRESS + 0x0D50)
+    #define SHU_MISC_DRVING3_DQODTN2                           Fld(5, 0) //[4:0]
+    #define SHU_MISC_DRVING3_DQODTP2                           Fld(5, 5) //[9:5]
+    #define SHU_MISC_DRVING3_DQSODTN                           Fld(5, 10) //[14:10]
+    #define SHU_MISC_DRVING3_DQSODTP                           Fld(5, 15) //[19:15]
+    #define SHU_MISC_DRVING3_DQSODTN2                          Fld(5, 20) //[24:20]
+    #define SHU_MISC_DRVING3_DQSODTP2                          Fld(5, 25) //[29:25]
+
+#define DDRPHY_REG_SHU_MISC_DRVING4                            (DDRPHY_AO_BASE_ADDRESS + 0x0D54)
+    #define SHU_MISC_DRVING4_CMDODTN1                          Fld(5, 0) //[4:0]
+    #define SHU_MISC_DRVING4_CMDODTP1                          Fld(5, 5) //[9:5]
+    #define SHU_MISC_DRVING4_CMDODTN2                          Fld(5, 10) //[14:10]
+    #define SHU_MISC_DRVING4_CMDODTP2                          Fld(5, 15) //[19:15]
+    #define SHU_MISC_DRVING4_DQODTN1                           Fld(5, 20) //[24:20]
+    #define SHU_MISC_DRVING4_DQODTP1                           Fld(5, 25) //[29:25]
+
+#define DDRPHY_REG_SHU_MISC_DRVING5                            (DDRPHY_AO_BASE_ADDRESS + 0x0D58)
+    #define SHU_MISC_DRVING5_DQCODTN2                          Fld(5, 0) //[4:0]
+    #define SHU_MISC_DRVING5_DQCODTP2                          Fld(5, 5) //[9:5]
+    #define SHU_MISC_DRVING5_DQCDRVN1                          Fld(5, 10) //[14:10]
+    #define SHU_MISC_DRVING5_DQCDRVP1                          Fld(5, 15) //[19:15]
+    #define SHU_MISC_DRVING5_DQCDRVN2                          Fld(5, 20) //[24:20]
+    #define SHU_MISC_DRVING5_DQCDRVP2                          Fld(5, 25) //[29:25]
+
+#define DDRPHY_REG_SHU_MISC_DRVING6                            (DDRPHY_AO_BASE_ADDRESS + 0x0D5C)
+    #define SHU_MISC_DRVING6_IMP_TXDLY_CMD                     Fld(6, 0) //[5:0]
+    #define SHU_MISC_DRVING6_DQCODTN1                          Fld(5, 20) //[24:20]
+    #define SHU_MISC_DRVING6_DQCODTP1                          Fld(5, 25) //[29:25]
+
+#define DDRPHY_REG_SHU_MISC_DUTY_SCAN                          (DDRPHY_AO_BASE_ADDRESS + 0x0D60)
+    #define SHU_MISC_DUTY_SCAN_R_DMFREQDIV2                    Fld(1, 0) //[0:0]
+    #define SHU_MISC_DUTY_SCAN_R_DM64BITEN                     Fld(1, 1) //[1:1]
+
+#define DDRPHY_REG_SHU_MISC_DMA                                (DDRPHY_AO_BASE_ADDRESS + 0x0D64)
+    #define SHU_MISC_DMA_SRAM_RL_2T                            Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_SHU_MISC_RVREF                              (DDRPHY_AO_BASE_ADDRESS + 0x0D68)
+    #define SHU_MISC_RVREF_RG_RVREF_SEL_DQ                     Fld(6, 16) //[21:16]
+    #define SHU_MISC_RVREF_RG_RVREF_DDR4_SEL                   Fld(1, 22) //[22:22]
+    #define SHU_MISC_RVREF_RG_RVREF_DDR3_SEL                   Fld(1, 23) //[23:23]
+    #define SHU_MISC_RVREF_RG_RVREF_SEL_CMD                    Fld(6, 24) //[29:24]
+
+#define DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL                       (DDRPHY_AO_BASE_ADDRESS + 0x0D6C)
+    #define SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN            Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_SHU_MISC_TX_PIPE_CTRL                       (DDRPHY_AO_BASE_ADDRESS + 0x0D70)
+    #define SHU_MISC_TX_PIPE_CTRL_CMD_TXPIPE_BYPASS_EN         Fld(1, 0) //[0:0]
+    #define SHU_MISC_TX_PIPE_CTRL_CK_TXPIPE_BYPASS_EN          Fld(1, 1) //[1:1]
+    #define SHU_MISC_TX_PIPE_CTRL_TX_PIPE_BYPASS_EN            Fld(1, 2) //[2:2]
+    #define SHU_MISC_TX_PIPE_CTRL_CS_TXPIPE_BYPASS_EN          Fld(1, 3) //[3:3]
+    #define SHU_MISC_TX_PIPE_CTRL_SKIP_TXPIPE_BYPASS           Fld(1, 8) //[8:8]
+
+#define DDRPHY_REG_SHU_MISC_EMI_CTRL                           (DDRPHY_AO_BASE_ADDRESS + 0x0D74)
+    #define SHU_MISC_EMI_CTRL_DR_EMI_RESERVE                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_SHU_MISC_RANK_SEL_STB                       (DDRPHY_AO_BASE_ADDRESS + 0x0D78)
+    #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN              Fld(1, 0) //[0:0]
+    #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23          Fld(1, 1) //[1:1]
+    #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE         Fld(2, 2) //[3:2]
+    #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK           Fld(1, 4) //[4:4]
+    #define SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK         Fld(1, 5) //[5:5]
+    #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN        Fld(1, 7) //[7:7]
+    #define SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL            Fld(4, 8) //[11:8]
+    #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS         Fld(4, 16) //[19:16]
+    #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS        Fld(4, 20) //[23:20]
+    #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS        Fld(4, 24) //[27:24]
+    #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS       Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_SHU_MISC_RDSEL_TRACK                        (DDRPHY_AO_BASE_ADDRESS + 0x0D7C)
+    #define SHU_MISC_RDSEL_TRACK_DMDATLAT_I                    Fld(5, 0) //[4:0]
+    #define SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK              Fld(1, 6) //[6:6]
+    #define SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN                Fld(1, 7) //[7:7]
+    #define SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG               Fld(12, 8) //[19:8]
+    #define SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS               Fld(12, 20) //[31:20]
+
+#define DDRPHY_REG_SHU_MISC_PRE_TDQSCK                         (DDRPHY_AO_BASE_ADDRESS + 0x0D80)
+    #define SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE                 Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_SHU_MISC_ASYNC_FIFO_CTRL                    (DDRPHY_AO_BASE_ADDRESS + 0x0D84)
+    #define SHU_MISC_ASYNC_FIFO_CTRL_ASYNC_EN                  Fld(1, 0) //[0:0]
+    #define SHU_MISC_ASYNC_FIFO_CTRL_AFIFO_SYNCDEPTH           Fld(2, 4) //[5:4]
+
+#define DDRPHY_REG_MISC_SHU_RX_SELPH_MODE                      (DDRPHY_AO_BASE_ADDRESS + 0x0D88)
+    #define MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE        Fld(2, 0) //[1:0]
+    #define MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE          Fld(2, 4) //[5:4]
+    #define MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE          Fld(2, 6) //[7:6]
+
+#define DDRPHY_REG_MISC_SHU_RANK_SEL_LAT                       (DDRPHY_AO_BASE_ADDRESS + 0x0D8C)
+    #define MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0              Fld(4, 0) //[3:0]
+    #define MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1              Fld(4, 4) //[7:4]
+    #define MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA              Fld(4, 8) //[11:8]
+
+#define DDRPHY_REG_MISC_SHU_DLINE_MON_CTRL                     (DDRPHY_AO_BASE_ADDRESS + 0x0D90)
+    #define MISC_SHU_DLINE_MON_CTRL_DLINE_MON_TSHIFT           Fld(2, 0) //[1:0]
+    #define MISC_SHU_DLINE_MON_CTRL_DLINE_MON_DIV              Fld(2, 2) //[3:2]
+    #define MISC_SHU_DLINE_MON_CTRL_DLINE_MON_DLY              Fld(7, 8) //[14:8]
+    #define MISC_SHU_DLINE_MON_CTRL_DLINE_MON_EN               Fld(1, 16) //[16:16]
+
+#define DDRPHY_REG_MISC_SHU_DLINE_MON_CNT                      (DDRPHY_AO_BASE_ADDRESS + 0x0D94)
+    #define MISC_SHU_DLINE_MON_CNT_TRIG_DLINE_MON_CNT          Fld(16, 0) //[15:0]
+
+#define DDRPHY_REG_MISC_SHU_MIDPI_CTRL                         (DDRPHY_AO_BASE_ADDRESS + 0x0D98)
+    #define MISC_SHU_MIDPI_CTRL_MIDPI_ENABLE                   Fld(1, 0) //[0:0]
+    #define MISC_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE              Fld(1, 1) //[1:1]
+
+#define DDRPHY_REG_MISC_SHU_RX_CG_CTRL                         (DDRPHY_AO_BASE_ADDRESS + 0x0DA0)
+    #define MISC_SHU_RX_CG_CTRL_RX_DCM_OPT                     Fld(1, 0) //[0:0]
+    #define MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT           Fld(1, 1) //[1:1]
+    #define MISC_SHU_RX_CG_CTRL_RX_RODT_DCM_OPT                Fld(1, 2) //[2:2]
+    #define MISC_SHU_RX_CG_CTRL_RX_DQSIEN_STBCAL_CG_EN         Fld(1, 4) //[4:4]
+    #define MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN          Fld(1, 5) //[5:5]
+    #define MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN        Fld(1, 8) //[8:8]
+    #define MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN          Fld(1, 9) //[9:9]
+    #define MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN                Fld(1, 10) //[10:10]
+    #define MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY                 Fld(4, 16) //[19:16]
+    #define MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY        Fld(4, 20) //[23:20]
+
+#define DDRPHY_REG_MISC_SHU_CG_CTRL0                           (DDRPHY_AO_BASE_ADDRESS + 0x0DA4)
+    #define MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_STBERR_ALL                             (DDRPHY_AO_BASE_ADDRESS + 0x1500)
+    #define MISC_STBERR_ALL_GATING_ERROR_ALL_RK0               Fld(1, 0) //[0:0]
+    #define MISC_STBERR_ALL_GATING_ERROR_B0_RK0                Fld(1, 1) //[1:1]
+    #define MISC_STBERR_ALL_GATING_ERROR_B1_RK0                Fld(1, 2) //[2:2]
+    #define MISC_STBERR_ALL_GATING_ERROR_CA_RK0                Fld(1, 3) //[3:3]
+    #define MISC_STBERR_ALL_GATING_ERROR_ALL_RK1               Fld(1, 4) //[4:4]
+    #define MISC_STBERR_ALL_GATING_ERROR_B0_RK1                Fld(1, 5) //[5:5]
+    #define MISC_STBERR_ALL_GATING_ERROR_B1_RK1                Fld(1, 6) //[6:6]
+    #define MISC_STBERR_ALL_GATING_ERROR_CA_RK1                Fld(1, 7) //[7:7]
+    #define MISC_STBERR_ALL_STBENERR_ALL                       Fld(1, 16) //[16:16]
+    #define MISC_STBERR_ALL_RX_ARDQ0_FIFO_STBEN_ERR_B0         Fld(1, 24) //[24:24]
+    #define MISC_STBERR_ALL_RX_ARDQ4_FIFO_STBEN_ERR_B0         Fld(1, 25) //[25:25]
+    #define MISC_STBERR_ALL_RX_ARDQ0_FIFO_STBEN_ERR_B1         Fld(1, 26) //[26:26]
+    #define MISC_STBERR_ALL_RX_ARDQ4_FIFO_STBEN_ERR_B1         Fld(1, 27) //[27:27]
+    #define MISC_STBERR_ALL_RX_ARCA0_FIFO_STBEN_ERR            Fld(1, 28) //[28:28]
+    #define MISC_STBERR_ALL_RX_ARCA4_FIFO_STBEN_ERR            Fld(1, 29) //[29:29]
+
+#define DDRPHY_REG_MISC_STBERR_RK0_R                           (DDRPHY_AO_BASE_ADDRESS + 0x1504)
+    #define MISC_STBERR_RK0_R_STBENERR_B0_RK0_R                Fld(8, 0) //[7:0]
+    #define MISC_STBERR_RK0_R_STBENERR_B1_RK0_R                Fld(8, 8) //[15:8]
+    #define MISC_STBERR_RK0_R_STBENERR_CA_RK0_R                Fld(8, 16) //[23:16]
+
+#define DDRPHY_REG_MISC_STBERR_RK0_F                           (DDRPHY_AO_BASE_ADDRESS + 0x1508)
+    #define MISC_STBERR_RK0_F_STBENERR_B0_RK0_F                Fld(8, 0) //[7:0]
+    #define MISC_STBERR_RK0_F_STBENERR_B1_RK0_F                Fld(8, 8) //[15:8]
+    #define MISC_STBERR_RK0_F_STBENERR_CA_RK0_F                Fld(8, 16) //[23:16]
+
+#define DDRPHY_REG_MISC_STBERR_RK1_R                           (DDRPHY_AO_BASE_ADDRESS + 0x150C)
+    #define MISC_STBERR_RK1_R_STBENERR_B0_RK1_R                Fld(8, 0) //[7:0]
+    #define MISC_STBERR_RK1_R_STBENERR_B1_RK1_R                Fld(8, 8) //[15:8]
+    #define MISC_STBERR_RK1_R_STBENERR_CA_RK1_R                Fld(8, 16) //[23:16]
+
+#define DDRPHY_REG_MISC_STBERR_RK1_F                           (DDRPHY_AO_BASE_ADDRESS + 0x1510)
+    #define MISC_STBERR_RK1_F_STBENERR_B0_RK1_F                Fld(8, 0) //[7:0]
+    #define MISC_STBERR_RK1_F_STBENERR_B1_RK1_F                Fld(8, 8) //[15:8]
+    #define MISC_STBERR_RK1_F_STBENERR_CA_RK1_F                Fld(8, 16) //[23:16]
+
+#define DDRPHY_REG_MISC_DDR_RESERVE_STATE                      (DDRPHY_AO_BASE_ADDRESS + 0x1520)
+    #define MISC_DDR_RESERVE_STATE_WDT_SM                      Fld(4, 0) //[3:0]
+
+#define DDRPHY_REG_MISC_IRQ_STATUS0                            (DDRPHY_AO_BASE_ADDRESS + 0x1530)
+    #define MISC_IRQ_STATUS0_REFRATE_EN                        Fld(1, 0) //[0:0]
+    #define MISC_IRQ_STATUS0_REFPENDING_EN                     Fld(1, 1) //[1:1]
+    #define MISC_IRQ_STATUS0_PRE_REFRATE_EN                    Fld(1, 2) //[2:2]
+    #define MISC_IRQ_STATUS0_RTMRW_ABNORMAL_STOP_EN            Fld(1, 3) //[3:3]
+    #define MISC_IRQ_STATUS0_SREF_REQ_NO_ACK_EN                Fld(1, 6) //[6:6]
+    #define MISC_IRQ_STATUS0_SREF_REQ_SHORT_EN                 Fld(1, 7) //[7:7]
+    #define MISC_IRQ_STATUS0_SREF_REQ_DTRIG_EN                 Fld(1, 8) //[8:8]
+    #define MISC_IRQ_STATUS0_RTSWCMD_NONVALIDCMD_EN            Fld(1, 12) //[12:12]
+    #define MISC_IRQ_STATUS0_TX_TRACKING1_EN                   Fld(1, 16) //[16:16]
+    #define MISC_IRQ_STATUS0_TX_TRACKING2_EN                   Fld(1, 17) //[17:17]
+    #define MISC_IRQ_STATUS0_DRAMC_IRQ_OUT_0                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_IRQ_STATUS1                            (DDRPHY_AO_BASE_ADDRESS + 0x1534)
+    #define MISC_IRQ_STATUS1_DRAMC_IRQ_OUT_1                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_IRQ_STATUS2                            (DDRPHY_AO_BASE_ADDRESS + 0x1538)
+    #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK1_B0_EN            Fld(1, 0)  //[0:0]
+    #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK0_B0_EN            Fld(1, 1)  //[1:1]
+    #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK1_B1_EN            Fld(1, 2)  //[2:2]
+    #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK0_B1_EN            Fld(1, 3)  //[3:3]
+    #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK1_CA_EN            Fld(1, 4)  //[4:4]
+    #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK0_CA_EN            Fld(1, 5)  //[5:5]
+    #define MISC_IRQ_STATUS2_STB_GATTING_ERR_EN                   Fld(1, 7)  //[7:7]
+    #define MISC_IRQ_STATUS2_RX_ARDQ0_FIFO_STBEN_ERR_B0_EN        Fld(1, 8)  //[8:8]
+    #define MISC_IRQ_STATUS2_RX_ARDQ4_FIFO_STBEN_ERR_B0_EN        Fld(1, 9)  //[9:9]
+    #define MISC_IRQ_STATUS2_RX_ARDQ0_FIFO_STBEN_ERR_B1_EN        Fld(1, 10)  //[10:10]
+    #define MISC_IRQ_STATUS2_RX_ARDQ4_FIFO_STBEN_ERR_B1_EN        Fld(1, 11)  //[11:11]
+    #define MISC_IRQ_STATUS2_TRACKING_STATUS_ERR_RISING_R1_B1_EN  Fld(1, 12)  //[12:12]
+    #define MISC_IRQ_STATUS2_TRACKING_STATUS_ERR_RISING_R1_B0_EN  Fld(1, 13)  //[13:13]
+    #define MISC_IRQ_STATUS2_TRACKING_STATUS_ERR_RISING_R0_B1_EN  Fld(1, 14)  //[14:14]
+    #define MISC_IRQ_STATUS2_TRACKING_STATUS_ERR_RISING_R0_B0_EN  Fld(1, 15)  //[15:15]
+    #define MISC_IRQ_STATUS2_IMP_CLK_ERR_EN                       Fld(1, 24)  //[24:24]
+    #define MISC_IRQ_STATUS2_IMP_CMD_ERR_EN                       Fld(1, 25)  //[25:25]
+    #define MISC_IRQ_STATUS2_IMP_DQ1_ERR_EN                       Fld(1, 26)  //[26:26]
+    #define MISC_IRQ_STATUS2_IMP_DQ0_ERR_EN                       Fld(1, 27)  //[27:27]
+    #define MISC_IRQ_STATUS2_IMP_DQS_ERR_EN                       Fld(1, 28)  //[28:28]
+    #define MISC_IRQ_STATUS2_IMP_ODTN_ERR_EN                      Fld(1, 29)  //[29:29]
+    #define MISC_IRQ_STATUS2_IMP_DRVN_ERR_EN                      Fld(1, 30)  //[30:30]
+    #define MISC_IRQ_STATUS2_IMP_DRVP_ERR_EN                      Fld(1, 31)  //[31:31]
+    #define MISC_IRQ_STATUS2_DRAMP_IRQ_OUT_0                      Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DBG_DB_MESSAGE0                        (DDRPHY_AO_BASE_ADDRESS + 0x1600)
+    #define MISC_DBG_DB_MESSAGE0_DBG_DB_REFRESH_RATE           Fld(5, 0) //[4:0]
+    #define MISC_DBG_DB_MESSAGE0_DBG_DB_REFRESH_QUEUE_CNT      Fld(4, 8) //[11:8]
+    #define MISC_DBG_DB_MESSAGE0_DBG_DB_REFRESH_RATE_CHG_QUEUE_CNT Fld(4, 12) //[15:12]
+
+#define DDRPHY_REG_MISC_DBG_DB_MESSAGE1                        (DDRPHY_AO_BASE_ADDRESS + 0x1604)
+    #define MISC_DBG_DB_MESSAGE1_DBG_DB_PRE_REFRESH_RATE_RK0   Fld(5, 0) //[4:0]
+    #define MISC_DBG_DB_MESSAGE1_DBG_DB_PRE_REFRESH_RATE_RK1   Fld(5, 8) //[12:8]
+    #define MISC_DBG_DB_MESSAGE1_DBG_DB_PRE_REFRESH_RATE_RK0_B1 Fld(5, 16) //[20:16]
+    #define MISC_DBG_DB_MESSAGE1_DBG_DB_PRE_REFRESH_RATE_RK1_B1 Fld(5, 24) //[28:24]
+
+#define DDRPHY_REG_MISC_DBG_DB_MESSAGE2                        (DDRPHY_AO_BASE_ADDRESS + 0x1608)
+    #define MISC_DBG_DB_MESSAGE2_DBG_DB_PI_DEC_ACC_CNT_RK0_B0  Fld(6, 0) //[5:0]
+    #define MISC_DBG_DB_MESSAGE2_DBG_DB_PI_INC_ACC_CNT_RK0_B0  Fld(6, 8) //[13:8]
+    #define MISC_DBG_DB_MESSAGE2_DBG_DB_PI_DEC_ACC_CNT_RK1_B0  Fld(6, 16) //[21:16]
+    #define MISC_DBG_DB_MESSAGE2_DBG_DB_PI_INC_ACC_CNT_RK1_B0  Fld(6, 24) //[29:24]
+
+#define DDRPHY_REG_MISC_DBG_DB_MESSAGE3                        (DDRPHY_AO_BASE_ADDRESS + 0x160C)
+    #define MISC_DBG_DB_MESSAGE3_DBG_DB_DQSIEN_SHU_INI_PI_RK0_B0 Fld(7, 0) //[6:0]
+    #define MISC_DBG_DB_MESSAGE3_DBG_DB_DQSIEN_SHU_INI_UI_RK0_B0 Fld(8, 8) //[15:8]
+    #define MISC_DBG_DB_MESSAGE3_DBG_DB_DQSIEN_SHU_CUR_PI_RK0_B0 Fld(7, 16) //[22:16]
+    #define MISC_DBG_DB_MESSAGE3_DBG_DB_DQSIEN_SHU_CUR_UI_RK0_B0 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_DBG_DB_MESSAGE4                        (DDRPHY_AO_BASE_ADDRESS + 0x1610)
+    #define MISC_DBG_DB_MESSAGE4_DBG_DB_DQSIEN_SHU_INI_PI_RK1_B0 Fld(7, 0) //[6:0]
+    #define MISC_DBG_DB_MESSAGE4_DBG_DB_DQSIEN_SHU_INI_UI_RK1_B0 Fld(8, 8) //[15:8]
+    #define MISC_DBG_DB_MESSAGE4_DBG_DB_DQSIEN_SHU_CUR_PI_RK1_B0 Fld(7, 16) //[22:16]
+    #define MISC_DBG_DB_MESSAGE4_DBG_DB_DQSIEN_SHU_CUR_UI_RK1_B0 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_DBG_DB_MESSAGE5                        (DDRPHY_AO_BASE_ADDRESS + 0x1614)
+    #define MISC_DBG_DB_MESSAGE5_DBG_DB_PI_DEC_ACC_CNT_RK0_B1  Fld(6, 0) //[5:0]
+    #define MISC_DBG_DB_MESSAGE5_DBG_DB_PI_INC_ACC_CNT_RK0_B1  Fld(6, 8) //[13:8]
+    #define MISC_DBG_DB_MESSAGE5_DBG_DB_PI_DEC_ACC_CNT_RK1_B1  Fld(6, 16) //[21:16]
+    #define MISC_DBG_DB_MESSAGE5_DBG_DB_PI_INC_ACC_CNT_RK1_B1  Fld(6, 24) //[29:24]
+
+#define DDRPHY_REG_MISC_DBG_DB_MESSAGE6                        (DDRPHY_AO_BASE_ADDRESS + 0x1618)
+    #define MISC_DBG_DB_MESSAGE6_DBG_DB_DQSIEN_SHU_INI_PI_RK0_B1 Fld(7, 0) //[6:0]
+    #define MISC_DBG_DB_MESSAGE6_DBG_DB_DQSIEN_SHU_INI_UI_RK0_B1 Fld(8, 8) //[15:8]
+    #define MISC_DBG_DB_MESSAGE6_DBG_DB_DQSIEN_SHU_CUR_PI_RK0_B1 Fld(7, 16) //[22:16]
+    #define MISC_DBG_DB_MESSAGE6_DBG_DB_DQSIEN_SHU_CUR_UI_RK0_B1 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_DBG_DB_MESSAGE7                        (DDRPHY_AO_BASE_ADDRESS + 0x161C)
+    #define MISC_DBG_DB_MESSAGE7_DBG_DB_DQSIEN_SHU_INI_PI_RK1_B1 Fld(7, 0) //[6:0]
+    #define MISC_DBG_DB_MESSAGE7_DBG_DB_DQSIEN_SHU_INI_UI_RK1_B1 Fld(8, 8) //[15:8]
+    #define MISC_DBG_DB_MESSAGE7_DBG_DB_DQSIEN_SHU_CUR_PI_RK1_B1 Fld(7, 16) //[22:16]
+    #define MISC_DBG_DB_MESSAGE7_DBG_DB_DQSIEN_SHU_CUR_UI_RK1_B1 Fld(8, 24) //[31:24]
+
+#endif // __DDRPHY_AO_REGS_H__
diff --git a/src/vendorcode/mediatek/mt8195/include/8195_Register_DDRPHY_MD32.h b/src/vendorcode/mediatek/mt8195/include/8195_Register_DDRPHY_MD32.h
new file mode 100644
index 000000000000..bd9fdb1a89f0
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/8195_Register_DDRPHY_MD32.h
@@ -0,0 +1,2903 @@
+#ifndef __DDRPHY_MD32_REGS_H__
+#define __DDRPHY_MD32_REGS_H__
+
+#define Channel_A_DDRPHY_DPM_BASE_ADDRESS    0x10940000
+
+#define DDRPHY_MD32_BASE_ADDRESS     Channel_A_DDRPHY_DPM_BASE_VIRTUAL
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_SW_RSTN                    (DDRPHY_MD32_BASE_ADDRESS + 0x0000)
+    #define SSPM_CFGREG_SW_RSTN_SW_RSTN                        Fld(1, 0) //[0:0]
+    #define SSPM_CFGREG_SW_RSTN_MEM_RATIO                      Fld(2, 28) //[29:28]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_RESOURCE_CTL               (DDRPHY_MD32_BASE_ADDRESS + 0x0004)
+    #define SSPM_CFGREG_RESOURCE_CTL_APSRC_REQ                 Fld(1, 0) //[0:0]
+    #define SSPM_CFGREG_RESOURCE_CTL_APSRC_ACK                 Fld(1, 4) //[4:4]
+    #define SSPM_CFGREG_RESOURCE_CTL_INFRA_REQ                 Fld(1, 8) //[8:8]
+    #define SSPM_CFGREG_RESOURCE_CTL_INFRA_ACK                 Fld(1, 12) //[12:12]
+    #define SSPM_CFGREG_RESOURCE_CTL_SRCLKENA_REQ              Fld(1, 16) //[16:16]
+    #define SSPM_CFGREG_RESOURCE_CTL_SRCLKENA_ACK              Fld(1, 20) //[20:20]
+    #define SSPM_CFGREG_RESOURCE_CTL_DCS_ULTRA_REQ             Fld(1, 24) //[24:24]
+    #define SSPM_CFGREG_RESOURCE_CTL_DCS_ULTRA_REQ_ACK         Fld(1, 28) //[28:28]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_SYS_RMAP                   (DDRPHY_MD32_BASE_ADDRESS + 0x0008)
+    #define SSPM_CFGREG_SYS_RMAP_SYS_RMAP                      Fld(4, 0) //[3:0]
+    #define SSPM_CFGREG_SYS_RMAP_DRAM_RMAP0                    Fld(6, 4) //[9:4]
+    #define SSPM_CFGREG_SYS_RMAP_DRAM_RMAP1                    Fld(6, 10) //[15:10]
+    #define SSPM_CFGREG_SYS_RMAP_DRAM_RMAP2                    Fld(6, 16) //[21:16]
+    #define SSPM_CFGREG_SYS_RMAP_DRAM_RMAP3                    Fld(6, 22) //[27:22]
+    #define SSPM_CFGREG_SYS_RMAP_BUS_ARB_POLICY                Fld(1, 28) //[28:28]
+    #define SSPM_CFGREG_SYS_RMAP_H2H_POSTWRITE_DIS             Fld(1, 29) //[29:29]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_OCD_BYPASS                 (DDRPHY_MD32_BASE_ADDRESS + 0x000C)
+    #define SSPM_CFGREG_OCD_BYPASS_OCD_BYPASS                  Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MD2HOST_IPC                (DDRPHY_MD32_BASE_ADDRESS + 0x0010)
+    #define SSPM_CFGREG_MD2HOST_IPC_MD2HOST_IPC                Fld(1, 0) //[0:0]
+    #define SSPM_CFGREG_MD2HOST_IPC_MD2HOST_IPC1               Fld(1, 1) //[1:1]
+    #define SSPM_CFGREG_MD2HOST_IPC_MD2HOST_IPC_INT            Fld(1, 8) //[8:8]
+    #define SSPM_CFGREG_MD2HOST_IPC_MD2HOST_IPC_INT1           Fld(1, 9) //[9:9]
+    #define SSPM_CFGREG_MD2HOST_IPC_WDT_INT                    Fld(1, 10) //[10:10]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MD2SPM_IPC                 (DDRPHY_MD32_BASE_ADDRESS + 0x0014)
+    #define SSPM_CFGREG_MD2SPM_IPC_MD2SPM_IPC                  Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_HOST2MD_IPC                (DDRPHY_MD32_BASE_ADDRESS + 0x0018)
+    #define SSPM_CFGREG_HOST2MD_IPC_HOST2MD_IPC                Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_SPM2MD_IPC                 (DDRPHY_MD32_BASE_ADDRESS + 0x001C)
+    #define SSPM_CFGREG_SPM2MD_IPC_SPM2MD_IPC                  Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR0                       (DDRPHY_MD32_BASE_ADDRESS + 0x0020)
+    #define SSPM_CFGREG_GPR0_GPR0                              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR1                       (DDRPHY_MD32_BASE_ADDRESS + 0x0024)
+    #define SSPM_CFGREG_GPR1_GPR1                              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR2                       (DDRPHY_MD32_BASE_ADDRESS + 0x0028)
+    #define SSPM_CFGREG_GPR2_GPR2                              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR3                       (DDRPHY_MD32_BASE_ADDRESS + 0x002C)
+    #define SSPM_CFGREG_GPR3_GPR3                              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR4                       (DDRPHY_MD32_BASE_ADDRESS + 0x0030)
+    #define SSPM_CFGREG_GPR4_GPR4                              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR5                       (DDRPHY_MD32_BASE_ADDRESS + 0x0034)
+    #define SSPM_CFGREG_GPR5_GPR5                              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_DVFS_INFO                  (DDRPHY_MD32_BASE_ADDRESS + 0x0038)
+    #define SSPM_CFGREG_DVFS_INFO_DVFS_INFO_0                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_TEMPERATURE                (DDRPHY_MD32_BASE_ADDRESS + 0x003C)
+    #define SSPM_CFGREG_TEMPERATURE_TEMPERATURE                Fld(15, 0) //[14:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_WDT_CFG                    (DDRPHY_MD32_BASE_ADDRESS + 0x0040)
+    #define SSPM_CFGREG_WDT_CFG_WDT_VAL                        Fld(20, 0) //[19:0]
+    #define SSPM_CFGREG_WDT_CFG_WDT_EN                         Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_WDT_KICK                   (DDRPHY_MD32_BASE_ADDRESS + 0x0044)
+    #define SSPM_CFGREG_WDT_KICK_WDT_KICK                      Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_SEMAPHORE                  (DDRPHY_MD32_BASE_ADDRESS + 0x0048)
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_0_M                     Fld(1, 0) //[0:0]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_0_H                     Fld(1, 1) //[1:1]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_1_M                     Fld(1, 2) //[2:2]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_1_H                     Fld(1, 3) //[3:3]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_2_M                     Fld(1, 4) //[4:4]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_2_H                     Fld(1, 5) //[5:5]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_3_M                     Fld(1, 6) //[6:6]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_3_H                     Fld(1, 7) //[7:7]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_4_M                     Fld(1, 8) //[8:8]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_4_H                     Fld(1, 9) //[9:9]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_5_M                     Fld(1, 10) //[10:10]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_5_H                     Fld(1, 11) //[11:11]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_6_M                     Fld(1, 12) //[12:12]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_6_H                     Fld(1, 13) //[13:13]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_7_M                     Fld(1, 14) //[14:14]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_7_H                     Fld(1, 15) //[15:15]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_8_M                     Fld(1, 16) //[16:16]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_8_H                     Fld(1, 17) //[17:17]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_9_M                     Fld(1, 18) //[18:18]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_9_H                     Fld(1, 19) //[19:19]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_10_M                    Fld(1, 20) //[20:20]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_10_H                    Fld(1, 21) //[21:21]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_11_M                    Fld(1, 22) //[22:22]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_11_H                    Fld(1, 23) //[23:23]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_12_M                    Fld(1, 24) //[24:24]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_12_H                    Fld(1, 25) //[25:25]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_13_M                    Fld(1, 26) //[26:26]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_13_H                    Fld(1, 27) //[27:27]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_14_M                    Fld(1, 28) //[28:28]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_14_H                    Fld(1, 29) //[29:29]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_15_M                    Fld(1, 30) //[30:30]
+    #define SSPM_CFGREG_SEMAPHORE_SEMA_15_H                    Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_TBUF_WPTR             (DDRPHY_MD32_BASE_ADDRESS + 0x004C)
+    #define SSPM_CFGREG_MD32_TBUF_WPTR_MON_TBUF_WPTR           Fld(4, 0) //[3:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_CCNT                  (DDRPHY_MD32_BASE_ADDRESS + 0x0050)
+    #define SSPM_CFGREG_MD32_CCNT_MON_CCNT                     Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_PCNT0                 (DDRPHY_MD32_BASE_ADDRESS + 0x0054)
+    #define SSPM_CFGREG_MD32_PCNT0_MON_PCNT0                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_PCNT1                 (DDRPHY_MD32_BASE_ADDRESS + 0x0058)
+    #define SSPM_CFGREG_MD32_PCNT1_MON_PCNT1                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_PCNT2                 (DDRPHY_MD32_BASE_ADDRESS + 0x005C)
+    #define SSPM_CFGREG_MD32_PCNT2_MON_PCNT2                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_CONTID                (DDRPHY_MD32_BASE_ADDRESS + 0x0060)
+    #define SSPM_CFGREG_MD32_CONTID_MON_CONTID                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_PC                    (DDRPHY_MD32_BASE_ADDRESS + 0x0064)
+    #define SSPM_CFGREG_MD32_PC_MON_PC                         Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_PC_MON                (DDRPHY_MD32_BASE_ADDRESS + 0x0068)
+    #define SSPM_CFGREG_MD32_PC_MON_MON_PC                     Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_BUS_STATUS            (DDRPHY_MD32_BASE_ADDRESS + 0x006C)
+    #define SSPM_CFGREG_MD32_BUS_STATUS_BUS_STATUS             Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_AHB_M0_ADDR           (DDRPHY_MD32_BASE_ADDRESS + 0x0070)
+    #define SSPM_CFGREG_MD32_AHB_M0_ADDR_AHB_M0_ADDR           Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_AHB_M1_ADDR           (DDRPHY_MD32_BASE_ADDRESS + 0x0074)
+    #define SSPM_CFGREG_MD32_AHB_M1_ADDR_AHB_M1_ADDR           Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_ONE_TIME_LOCK              (DDRPHY_MD32_BASE_ADDRESS + 0x0078)
+    #define SSPM_CFGREG_ONE_TIME_LOCK_ONE_TIME_LOCK            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_SECURE_CTRL                (DDRPHY_MD32_BASE_ADDRESS + 0x007C)
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_0              Fld(1, 0) //[0:0]
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_1              Fld(1, 1) //[1:1]
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_2              Fld(1, 2) //[2:2]
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_3              Fld(1, 3) //[3:3]
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_4              Fld(1, 4) //[4:4]
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_5              Fld(1, 5) //[5:5]
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_6              Fld(1, 6) //[6:6]
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_7              Fld(1, 7) //[7:7]
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_8              Fld(1, 8) //[8:8]
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_9              Fld(1, 9) //[9:9]
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_10             Fld(1, 10) //[10:10]
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_11             Fld(1, 11) //[11:11]
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_12             Fld(1, 12) //[12:12]
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_13             Fld(1, 13) //[13:13]
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_14             Fld(1, 14) //[14:14]
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_24             Fld(1, 24) //[24:24]
+    #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_28             Fld(1, 28) //[28:28]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_TCM_LOCK_CNT               (DDRPHY_MD32_BASE_ADDRESS + 0x0080)
+    #define SSPM_CFGREG_TCM_LOCK_CNT_TCM_LOCK_CNT              Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_SLPP_S_EN                  (DDRPHY_MD32_BASE_ADDRESS + 0x0088)
+    #define SSPM_CFGREG_SLPP_S_EN_SLPP_EN                      Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_P2P_TOEN                   (DDRPHY_MD32_BASE_ADDRESS + 0x008C)
+    #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_0                    Fld(1, 0) //[0:0]
+    #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_1                    Fld(1, 1) //[1:1]
+    #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_2                    Fld(1, 2) //[2:2]
+    #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_3                    Fld(1, 3) //[3:3]
+    #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_4                    Fld(1, 4) //[4:4]
+    #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_5                    Fld(1, 5) //[5:5]
+    #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_6                    Fld(1, 6) //[6:6]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX0_IN_IRQ               (DDRPHY_MD32_BASE_ADDRESS + 0x00A0)
+    #define SSPM_CFGREG_MBOX0_IN_IRQ_MBOX0_IN_IRQ              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX1_IN_IRQ               (DDRPHY_MD32_BASE_ADDRESS + 0x00A4)
+    #define SSPM_CFGREG_MBOX1_IN_IRQ_MBOX1_IN_IRQ              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX2_IN_IRQ               (DDRPHY_MD32_BASE_ADDRESS + 0x00A8)
+    #define SSPM_CFGREG_MBOX2_IN_IRQ_MBOX2_IN_IRQ              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX3_IN_IRQ               (DDRPHY_MD32_BASE_ADDRESS + 0x00AC)
+    #define SSPM_CFGREG_MBOX3_IN_IRQ_MBOX3_IN_IRQ              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX4_IN_IRQ               (DDRPHY_MD32_BASE_ADDRESS + 0x00B0)
+    #define SSPM_CFGREG_MBOX4_IN_IRQ_MBOX4_IN_IRQ              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX0_OUT_IRQ              (DDRPHY_MD32_BASE_ADDRESS + 0x00C0)
+    #define SSPM_CFGREG_MBOX0_OUT_IRQ_MBOX0_OUT_IRQ            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX1_OUT_IRQ              (DDRPHY_MD32_BASE_ADDRESS + 0x00C4)
+    #define SSPM_CFGREG_MBOX1_OUT_IRQ_MBOX1_OUT_IRQ            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX2_OUT_IRQ              (DDRPHY_MD32_BASE_ADDRESS + 0x00C8)
+    #define SSPM_CFGREG_MBOX2_OUT_IRQ_MBOX2_OUT_IRQ            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX3_OUT_IRQ              (DDRPHY_MD32_BASE_ADDRESS + 0x00CC)
+    #define SSPM_CFGREG_MBOX3_OUT_IRQ_MBOX3_OUT_IRQ            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX4_OUT_IRQ              (DDRPHY_MD32_BASE_ADDRESS + 0x00D0)
+    #define SSPM_CFGREG_MBOX4_OUT_IRQ_MBOX4_OUT_IRQ            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_ACAO_INT_SET               (DDRPHY_MD32_BASE_ADDRESS + 0x00D8)
+    #define SSPM_CFGREG_ACAO_INT_SET_ACAO_INT_SET              Fld(17, 0) //[16:0]
+    #define SSPM_CFGREG_ACAO_INT_SET_RSV0                      Fld(1, 17) //[17:17]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_ACAO_INT_CLR               (DDRPHY_MD32_BASE_ADDRESS + 0x00DC)
+    #define SSPM_CFGREG_ACAO_INT_CLR_ACAO_INT_CLR              Fld(17, 0) //[16:0]
+    #define SSPM_CFGREG_ACAO_INT_CLR_RSV0                      Fld(1, 17) //[17:17]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX0_BASE                 (DDRPHY_MD32_BASE_ADDRESS + 0x00E0)
+    #define SSPM_CFGREG_MBOX0_BASE_MBOX0_BASE                  Fld(13, 0) //[12:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX1_BASE                 (DDRPHY_MD32_BASE_ADDRESS + 0x00E4)
+    #define SSPM_CFGREG_MBOX1_BASE_MBOX1_BASE                  Fld(13, 0) //[12:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX2_BASE                 (DDRPHY_MD32_BASE_ADDRESS + 0x00E8)
+    #define SSPM_CFGREG_MBOX2_BASE_MBOX2_BASE                  Fld(13, 0) //[12:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX3_BASE                 (DDRPHY_MD32_BASE_ADDRESS + 0x00EC)
+    #define SSPM_CFGREG_MBOX3_BASE_MBOX3_BASE                  Fld(13, 0) //[12:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX4_BASE                 (DDRPHY_MD32_BASE_ADDRESS + 0x00F0)
+    #define SSPM_CFGREG_MBOX4_BASE_MBOX4_BASE                  Fld(13, 0) //[12:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX8_7B_BASE              (DDRPHY_MD32_BASE_ADDRESS + 0x00F4)
+    #define SSPM_CFGREG_MBOX8_7B_BASE_MBOX5_7B_4               Fld(5, 0) //[4:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_DVFS_INFO_1                (DDRPHY_MD32_BASE_ADDRESS + 0x00F8)
+    #define SSPM_CFGREG_DVFS_INFO_1_DVFS_INFO_1                Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_DVFS_INFO_2                (DDRPHY_MD32_BASE_ADDRESS + 0x00FC)
+    #define SSPM_CFGREG_DVFS_INFO_2_DVFS_INFO_2                Fld(5, 0) //[4:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_RSV_RW_REG0                (DDRPHY_MD32_BASE_ADDRESS + 0x0100)
+    #define SSPM_CFGREG_RSV_RW_REG0_GICNIRQOUT_IRQ             Fld(8, 0) //[7:0]
+    #define SSPM_CFGREG_RSV_RW_REG0_STANDBYWFI_INQ             Fld(8, 8) //[15:8]
+    #define SSPM_CFGREG_RSV_RW_REG0_SPM_WAKEUP_IRQ             Fld(1, 16) //[16:16]
+    #define SSPM_CFGREG_RSV_RW_REG0_RSV0                       Fld(1, 17) //[17:17]
+    #define SSPM_CFGREG_RSV_RW_REG0_RSV_RW_REG0                Fld(14, 18) //[31:18]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_RSV_RW_REG1                (DDRPHY_MD32_BASE_ADDRESS + 0x0104)
+    #define SSPM_CFGREG_RSV_RW_REG1_RSV_RW_REG1                Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_RSV_RO_REG0                (DDRPHY_MD32_BASE_ADDRESS + 0x0108)
+    #define SSPM_CFGREG_RSV_RO_REG0_RSV_RO_REG0                Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_RSV_RO_REG1                (DDRPHY_MD32_BASE_ADDRESS + 0x010C)
+    #define SSPM_CFGREG_RSV_RO_REG1_RSV_RO_REG1                Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR6                       (DDRPHY_MD32_BASE_ADDRESS + 0x0110)
+    #define SSPM_CFGREG_GPR6_GPR6                              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR7                       (DDRPHY_MD32_BASE_ADDRESS + 0x0114)
+    #define SSPM_CFGREG_GPR7_GPR7                              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR8                       (DDRPHY_MD32_BASE_ADDRESS + 0x0118)
+    #define SSPM_CFGREG_GPR8_GPR8                              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR9                       (DDRPHY_MD32_BASE_ADDRESS + 0x011C)
+    #define SSPM_CFGREG_GPR9_GPR9                              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR10                      (DDRPHY_MD32_BASE_ADDRESS + 0x0120)
+    #define SSPM_CFGREG_GPR10_GPR10                            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR11                      (DDRPHY_MD32_BASE_ADDRESS + 0x0124)
+    #define SSPM_CFGREG_GPR11_GPR11                            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR12                      (DDRPHY_MD32_BASE_ADDRESS + 0x0128)
+    #define SSPM_CFGREG_GPR12_GPR12                            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR13                      (DDRPHY_MD32_BASE_ADDRESS + 0x012C)
+    #define SSPM_CFGREG_GPR13_GPR13                            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR14                      (DDRPHY_MD32_BASE_ADDRESS + 0x0130)
+    #define SSPM_CFGREG_GPR14_GPR14                            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR15                      (DDRPHY_MD32_BASE_ADDRESS + 0x0134)
+    #define SSPM_CFGREG_GPR15_GPR15                            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_PC_DRAM_CHA                (DDRPHY_MD32_BASE_ADDRESS + 0x013C)
+    #define SSPM_CFGREG_PC_DRAM_CHA_PC_DRAM_CHA                Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_PC_DRAM_CHB                (DDRPHY_MD32_BASE_ADDRESS + 0x0140)
+    #define SSPM_CFGREG_PC_DRAM_CHB_PC_DRAM_CHB                Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_PC_DRAM_CHC                (DDRPHY_MD32_BASE_ADDRESS + 0x0144)
+    #define SSPM_CFGREG_PC_DRAM_CHC_PC_DRAM_CHC                Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_PC_DRAM_CHD                (DDRPHY_MD32_BASE_ADDRESS + 0x0148)
+    #define SSPM_CFGREG_PC_DRAM_CHD_PC_DRAM_CHD                Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_SP                    (DDRPHY_MD32_BASE_ADDRESS + 0x014C)
+    #define SSPM_CFGREG_MD32_SP_MON_SP                         Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_LR                    (DDRPHY_MD32_BASE_ADDRESS + 0x0150)
+    #define SSPM_CFGREG_MD32_LR_MON_LR                         Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_BUS_CTRL0                  (DDRPHY_MD32_BASE_ADDRESS + 0x0168)
+    #define SSPM_CFGREG_BUS_CTRL0_BUS_CTRL0                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_BUS_CTRL1                  (DDRPHY_MD32_BASE_ADDRESS + 0x016C)
+    #define SSPM_CFGREG_BUS_CTRL1_BUS_CTRL1                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_BUS_CTRL2                  (DDRPHY_MD32_BASE_ADDRESS + 0x0170)
+    #define SSPM_CFGREG_BUS_CTRL2_BUS_CTRL2                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_DR_APBP2P_CTRL             (DDRPHY_MD32_BASE_ADDRESS + 0x0174)
+    #define SSPM_CFGREG_DR_APBP2P_CTRL_R_APB_BROADCAST_EN      Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_TBUF_MON_SEL               (DDRPHY_MD32_BASE_ADDRESS + 0x0178)
+    #define SSPM_CFGREG_TBUF_MON_SEL_TBU_MON_SEL               Fld(4, 0) //[3:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_TBUFL                      (DDRPHY_MD32_BASE_ADDRESS + 0x017C)
+    #define SSPM_CFGREG_TBUFL_TBUFL                            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_TBUFH                      (DDRPHY_MD32_BASE_ADDRESS + 0x0180)
+    #define SSPM_CFGREG_TBUFH_TBUFH                            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBIST_CFG                  (DDRPHY_MD32_BASE_ADDRESS + 0x0190)
+    #define SSPM_CFGREG_MBIST_CFG_DM_MD32_MBIST_CFG            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_SRAM_DELSEL                (DDRPHY_MD32_BASE_ADDRESS + 0x0194)
+    #define SSPM_CFGREG_SRAM_DELSEL_DM_MD32_SRAM_DELSEL_0      Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CFGREG_MBIST_PREFUSE_0            (DDRPHY_MD32_BASE_ADDRESS + 0x01A0)
+    #define SSPM_CFGREG_MBIST_PREFUSE_0_MBIST_PREFUSE_0        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_TIMER0_CON                        (DDRPHY_MD32_BASE_ADDRESS + 0x1000)
+    #define SSPM_TIMER0_CON_TIMER0_EN                          Fld(1, 0) //[0:0]
+    #define SSPM_TIMER0_CON_TIMER0_RTC                         Fld(2, 4) //[5:4]
+
+#define DDRPHY_MD32_REG_SSPM_TIMER0_RESET_VAL                  (DDRPHY_MD32_BASE_ADDRESS + 0x1004)
+    #define SSPM_TIMER0_RESET_VAL_TIMER0_RST_VAL               Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_TIMER0_CUR_VAL                    (DDRPHY_MD32_BASE_ADDRESS + 0x1008)
+    #define SSPM_TIMER0_CUR_VAL_TIMER0_CUR_VAL                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_TIMER0_IRQ_ACK                    (DDRPHY_MD32_BASE_ADDRESS + 0x100C)
+    #define SSPM_TIMER0_IRQ_ACK_TIMER0_IRQ_EN                  Fld(1, 0) //[0:0]
+    #define SSPM_TIMER0_IRQ_ACK_TIMER0_IRQ_STATUS              Fld(1, 4) //[4:4]
+    #define SSPM_TIMER0_IRQ_ACK_TIMER0_IRQ_CLR                 Fld(1, 5) //[5:5]
+
+#define DDRPHY_MD32_REG_SSPM_TIMER1_CON                        (DDRPHY_MD32_BASE_ADDRESS + 0x1010)
+    #define SSPM_TIMER1_CON_TIMER1_EN                          Fld(1, 0) //[0:0]
+    #define SSPM_TIMER1_CON_TIMER1_RTC                         Fld(2, 4) //[5:4]
+
+#define DDRPHY_MD32_REG_SSPM_TIMER1_RESET_VAL                  (DDRPHY_MD32_BASE_ADDRESS + 0x1014)
+    #define SSPM_TIMER1_RESET_VAL_TIMER1_RST_VAL               Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_TIMER1_CUR_VAL                    (DDRPHY_MD32_BASE_ADDRESS + 0x1018)
+    #define SSPM_TIMER1_CUR_VAL_TIMER1_CUR_VAL                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_TIMER1_IRQ_ACK                    (DDRPHY_MD32_BASE_ADDRESS + 0x101C)
+    #define SSPM_TIMER1_IRQ_ACK_TIMER1_IRQ_EN                  Fld(1, 0) //[0:0]
+    #define SSPM_TIMER1_IRQ_ACK_TIMER1_IRQ_STATUS              Fld(1, 4) //[4:4]
+    #define SSPM_TIMER1_IRQ_ACK_TIMER2_IRQ_CLR                 Fld(1, 5) //[5:5]
+
+#define DDRPHY_MD32_REG_SSPM_TIMER2_CON                        (DDRPHY_MD32_BASE_ADDRESS + 0x1020)
+    #define SSPM_TIMER2_CON_TIMER2_EN                          Fld(1, 0) //[0:0]
+    #define SSPM_TIMER2_CON_TIMER2_RTC                         Fld(2, 4) //[5:4]
+
+#define DDRPHY_MD32_REG_SSPM_TIMER2_RESET_VAL                  (DDRPHY_MD32_BASE_ADDRESS + 0x1024)
+    #define SSPM_TIMER2_RESET_VAL_TIMER2_RST_VAL               Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_TIMER2_CUR_VAL                    (DDRPHY_MD32_BASE_ADDRESS + 0x1028)
+    #define SSPM_TIMER2_CUR_VAL_TIMER2_CUR_VAL                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_TIMER2_IRQ_ACK                    (DDRPHY_MD32_BASE_ADDRESS + 0x102C)
+    #define SSPM_TIMER2_IRQ_ACK_TIMER2_IRQ_EN                  Fld(1, 0) //[0:0]
+    #define SSPM_TIMER2_IRQ_ACK_TIMER2_IRQ_STATUS              Fld(1, 4) //[4:4]
+    #define SSPM_TIMER2_IRQ_ACK_TIMER2_IRQ_CLR                 Fld(1, 5) //[5:5]
+
+#define DDRPHY_MD32_REG_SSPM_TIMER3_CON                        (DDRPHY_MD32_BASE_ADDRESS + 0x1030)
+    #define SSPM_TIMER3_CON_TIMER3_EN                          Fld(1, 0) //[0:0]
+    #define SSPM_TIMER3_CON_TIMER3_RTC                         Fld(2, 4) //[5:4]
+
+#define DDRPHY_MD32_REG_SSPM_TIMER3_RESET_VAL                  (DDRPHY_MD32_BASE_ADDRESS + 0x1034)
+    #define SSPM_TIMER3_RESET_VAL_TIMER3_RST_VAL               Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_TIMER3_CUR_VAL                    (DDRPHY_MD32_BASE_ADDRESS + 0x1038)
+    #define SSPM_TIMER3_CUR_VAL_TIMER3_CUR_VAL                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_TIMER3_IRQ_ACK                    (DDRPHY_MD32_BASE_ADDRESS + 0x103C)
+    #define SSPM_TIMER3_IRQ_ACK_TIMER3_IRQ_EN                  Fld(1, 0) //[0:0]
+    #define SSPM_TIMER3_IRQ_ACK_TIMER3_IRQ_STATUS              Fld(1, 4) //[4:4]
+    #define SSPM_TIMER3_IRQ_ACK_TIMER3_IRQ_CLR                 Fld(1, 5) //[5:5]
+
+#define DDRPHY_MD32_REG_SSPM_OS_TIMER_CON                      (DDRPHY_MD32_BASE_ADDRESS + 0x1080)
+    #define SSPM_OS_TIMER_CON_OS_TIMER_EN                      Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_OS_TIMER_CNT_L                    (DDRPHY_MD32_BASE_ADDRESS + 0x108C)
+    #define SSPM_OS_TIMER_CNT_L_OS_TIMER_CNT_L                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_OS_TIMER_CNT_H                    (DDRPHY_MD32_BASE_ADDRESS + 0x1090)
+    #define SSPM_OS_TIMER_CNT_H_OS_TIMER_CNT_H                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_OS_TIMER_TVAL                     (DDRPHY_MD32_BASE_ADDRESS + 0x1094)
+    #define SSPM_OS_TIMER_TVAL_OS_TIMER_TVAL                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_OS_TIMER_IRQ_ACK                  (DDRPHY_MD32_BASE_ADDRESS + 0x1098)
+    #define SSPM_OS_TIMER_IRQ_ACK_OS_TIMER_IRQ_EN              Fld(1, 0) //[0:0]
+    #define SSPM_OS_TIMER_IRQ_ACK_OS_TIMER_IRQ_STATUS          Fld(1, 4) //[4:4]
+    #define SSPM_OS_TIMER_IRQ_ACK_OS_TIMER_IRQ_CLR             Fld(1, 5) //[5:5]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_RAW_STA0                 (DDRPHY_MD32_BASE_ADDRESS + 0x2000)
+    #define SSPM_INTC_IRQ_RAW_STA0_IRQ_RAW_STA0                Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_RAW_STA1                 (DDRPHY_MD32_BASE_ADDRESS + 0x2004)
+    #define SSPM_INTC_IRQ_RAW_STA1_IRQ_RAW_STA1                Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_STA0                     (DDRPHY_MD32_BASE_ADDRESS + 0x2010)
+    #define SSPM_INTC_IRQ_STA0_IRQ_STA0                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_STA1                     (DDRPHY_MD32_BASE_ADDRESS + 0x2014)
+    #define SSPM_INTC_IRQ_STA1_IRQ_STA1                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_EN0                      (DDRPHY_MD32_BASE_ADDRESS + 0x2020)
+    #define SSPM_INTC_IRQ_EN0_IRQ_EN0                          Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_EN1                      (DDRPHY_MD32_BASE_ADDRESS + 0x2024)
+    #define SSPM_INTC_IRQ_EN1_IRQ_EN1                          Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_WAKE_EN0                 (DDRPHY_MD32_BASE_ADDRESS + 0x2030)
+    #define SSPM_INTC_IRQ_WAKE_EN0_IRQ_WAKE_EN0                Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_WAKE_EN1                 (DDRPHY_MD32_BASE_ADDRESS + 0x2034)
+    #define SSPM_INTC_IRQ_WAKE_EN1_IRQ_WAKE_EN1                Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_POL0                     (DDRPHY_MD32_BASE_ADDRESS + 0x2040)
+    #define SSPM_INTC_IRQ_POL0_IRQ_POL0                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_POL1                     (DDRPHY_MD32_BASE_ADDRESS + 0x2044)
+    #define SSPM_INTC_IRQ_POL1_IRQ_POL1                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP0_0                   (DDRPHY_MD32_BASE_ADDRESS + 0x2050)
+    #define SSPM_INTC_IRQ_GRP0_0_IRQ_GRP0_0                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP0_1                   (DDRPHY_MD32_BASE_ADDRESS + 0x2054)
+    #define SSPM_INTC_IRQ_GRP0_1_IRQ_GRP0_1                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP1_0                   (DDRPHY_MD32_BASE_ADDRESS + 0x2060)
+    #define SSPM_INTC_IRQ_GRP1_0_IRQ_GRP1_0                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP1_1                   (DDRPHY_MD32_BASE_ADDRESS + 0x2064)
+    #define SSPM_INTC_IRQ_GRP1_1_IRQ_GRP1_1                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP2_0                   (DDRPHY_MD32_BASE_ADDRESS + 0x2070)
+    #define SSPM_INTC_IRQ_GRP2_0_IRQ_GRP2_0                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP2_1                   (DDRPHY_MD32_BASE_ADDRESS + 0x2074)
+    #define SSPM_INTC_IRQ_GRP2_1_IRQ_GRP2_1                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP3_0                   (DDRPHY_MD32_BASE_ADDRESS + 0x2080)
+    #define SSPM_INTC_IRQ_GRP3_0_IRQ_GRP3_0                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP3_1                   (DDRPHY_MD32_BASE_ADDRESS + 0x2084)
+    #define SSPM_INTC_IRQ_GRP3_1_IRQ_GRP3_1                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP4_0                   (DDRPHY_MD32_BASE_ADDRESS + 0x2090)
+    #define SSPM_INTC_IRQ_GRP4_0_IRQ_GRP4_0                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP4_1                   (DDRPHY_MD32_BASE_ADDRESS + 0x2094)
+    #define SSPM_INTC_IRQ_GRP4_1_IRQ_GRP4_1                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP5_0                   (DDRPHY_MD32_BASE_ADDRESS + 0x20A0)
+    #define SSPM_INTC_IRQ_GRP5_0_IRQ_GRP5_0                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP5_1                   (DDRPHY_MD32_BASE_ADDRESS + 0x20A4)
+    #define SSPM_INTC_IRQ_GRP5_1_IRQ_GRP5_1                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP6_0                   (DDRPHY_MD32_BASE_ADDRESS + 0x20B0)
+    #define SSPM_INTC_IRQ_GRP6_0_IRQ_GRP6_0                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP6_1                   (DDRPHY_MD32_BASE_ADDRESS + 0x20B4)
+    #define SSPM_INTC_IRQ_GRP6_1_IRQ_GRP6_1                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP7_0                   (DDRPHY_MD32_BASE_ADDRESS + 0x20C0)
+    #define SSPM_INTC_IRQ_GRP7_0_IRQ_GRP7_0                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP7_1                   (DDRPHY_MD32_BASE_ADDRESS + 0x20C4)
+    #define SSPM_INTC_IRQ_GRP7_1_IRQ_GRP7_1                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP8_0                   (DDRPHY_MD32_BASE_ADDRESS + 0x20D0)
+    #define SSPM_INTC_IRQ_GRP8_0_IRQ_GRP8_0                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP8_1                   (DDRPHY_MD32_BASE_ADDRESS + 0x20D4)
+    #define SSPM_INTC_IRQ_GRP8_1_IRQ_GRP8_1                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP9_0                   (DDRPHY_MD32_BASE_ADDRESS + 0x20E0)
+    #define SSPM_INTC_IRQ_GRP9_0_IRQ_GRP9_0                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP9_1                   (DDRPHY_MD32_BASE_ADDRESS + 0x20E4)
+    #define SSPM_INTC_IRQ_GRP9_1_IRQ_GRP9_1                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP10_0                  (DDRPHY_MD32_BASE_ADDRESS + 0x20F0)
+    #define SSPM_INTC_IRQ_GRP10_0_IRQ_GRP10_0                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP10_1                  (DDRPHY_MD32_BASE_ADDRESS + 0x20F4)
+    #define SSPM_INTC_IRQ_GRP10_1_IRQ_GRP10_1                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP11_0                  (DDRPHY_MD32_BASE_ADDRESS + 0x2100)
+    #define SSPM_INTC_IRQ_GRP11_0_IRQ_GRP11_0                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP11_1                  (DDRPHY_MD32_BASE_ADDRESS + 0x2104)
+    #define SSPM_INTC_IRQ_GRP11_1_IRQ_GRP11_1                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP12_0                  (DDRPHY_MD32_BASE_ADDRESS + 0x2110)
+    #define SSPM_INTC_IRQ_GRP12_0_IRQ_GRP12_0                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP12_1                  (DDRPHY_MD32_BASE_ADDRESS + 0x2114)
+    #define SSPM_INTC_IRQ_GRP12_1_IRQ_GRP12_1                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP13_0                  (DDRPHY_MD32_BASE_ADDRESS + 0x2120)
+    #define SSPM_INTC_IRQ_GRP13_0_IRQ_GRP13_0                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP13_1                  (DDRPHY_MD32_BASE_ADDRESS + 0x2124)
+    #define SSPM_INTC_IRQ_GRP13_1_IRQ_GRP13_1                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP14_0                  (DDRPHY_MD32_BASE_ADDRESS + 0x2130)
+    #define SSPM_INTC_IRQ_GRP14_0_IRQ_GRP14_0                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP14_1                  (DDRPHY_MD32_BASE_ADDRESS + 0x2134)
+    #define SSPM_INTC_IRQ_GRP14_1_IRQ_GRP14_1                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP0_STA0                (DDRPHY_MD32_BASE_ADDRESS + 0x2150)
+    #define SSPM_INTC_IRQ_GRP0_STA0_IRQ_GRP0_STA0              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP0_STA1                (DDRPHY_MD32_BASE_ADDRESS + 0x2154)
+    #define SSPM_INTC_IRQ_GRP0_STA1_IRQ_GRP0_STA1              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP1_STA0                (DDRPHY_MD32_BASE_ADDRESS + 0x2160)
+    #define SSPM_INTC_IRQ_GRP1_STA0_IRQ_GRP1_STA0              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP1_STA1                (DDRPHY_MD32_BASE_ADDRESS + 0x2164)
+    #define SSPM_INTC_IRQ_GRP1_STA1_IRQ_GRP1_STA1              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP2_STA0                (DDRPHY_MD32_BASE_ADDRESS + 0x2170)
+    #define SSPM_INTC_IRQ_GRP2_STA0_IRQ_GRP2_STA0              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP2_STA1                (DDRPHY_MD32_BASE_ADDRESS + 0x2174)
+    #define SSPM_INTC_IRQ_GRP2_STA1_IRQ_GRP2_STA1              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP3_STA0                (DDRPHY_MD32_BASE_ADDRESS + 0x2180)
+    #define SSPM_INTC_IRQ_GRP3_STA0_IRQ_GRP3_STA0              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP3_STA1                (DDRPHY_MD32_BASE_ADDRESS + 0x2184)
+    #define SSPM_INTC_IRQ_GRP3_STA1_IRQ_GRP3_STA1              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP4_STA0                (DDRPHY_MD32_BASE_ADDRESS + 0x2190)
+    #define SSPM_INTC_IRQ_GRP4_STA0_IRQ_GRP4_STA0              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP4_STA1                (DDRPHY_MD32_BASE_ADDRESS + 0x2194)
+    #define SSPM_INTC_IRQ_GRP4_STA1_IRQ_GRP4_STA1              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP5_STA0                (DDRPHY_MD32_BASE_ADDRESS + 0x21A0)
+    #define SSPM_INTC_IRQ_GRP5_STA0_IRQ_GRP5_STA0              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP5_STA1                (DDRPHY_MD32_BASE_ADDRESS + 0x21A4)
+    #define SSPM_INTC_IRQ_GRP5_STA1_IRQ_GRP5_STA1              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP6_STA0                (DDRPHY_MD32_BASE_ADDRESS + 0x21B0)
+    #define SSPM_INTC_IRQ_GRP6_STA0_IRQ_GRP6_STA0              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP6_STA1                (DDRPHY_MD32_BASE_ADDRESS + 0x21B4)
+    #define SSPM_INTC_IRQ_GRP6_STA1_IRQ_GRP6_STA1              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP7_STA0                (DDRPHY_MD32_BASE_ADDRESS + 0x21C0)
+    #define SSPM_INTC_IRQ_GRP7_STA0_IRQ_GRP7_STA0              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP7_STA1                (DDRPHY_MD32_BASE_ADDRESS + 0x21C4)
+    #define SSPM_INTC_IRQ_GRP7_STA1_IRQ_GRP7_STA1              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP8_STA0                (DDRPHY_MD32_BASE_ADDRESS + 0x21D0)
+    #define SSPM_INTC_IRQ_GRP8_STA0_IRQ_GRP8_STA0              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP8_STA1                (DDRPHY_MD32_BASE_ADDRESS + 0x21D4)
+    #define SSPM_INTC_IRQ_GRP8_STA1_IRQ_GRP8_STA1              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP9_STA0                (DDRPHY_MD32_BASE_ADDRESS + 0x21E0)
+    #define SSPM_INTC_IRQ_GRP9_STA0_IRQ_GRP9_STA0              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP9_STA1                (DDRPHY_MD32_BASE_ADDRESS + 0x21E4)
+    #define SSPM_INTC_IRQ_GRP9_STA1_IRQ_GRP9_STA1              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP10_STA0               (DDRPHY_MD32_BASE_ADDRESS + 0x21F0)
+    #define SSPM_INTC_IRQ_GRP10_STA0_IRQ_GRP10_STA0            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP10_STA1               (DDRPHY_MD32_BASE_ADDRESS + 0x21F4)
+    #define SSPM_INTC_IRQ_GRP10_STA1_IRQ_GRP10_STA1            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP11_STA0               (DDRPHY_MD32_BASE_ADDRESS + 0x2200)
+    #define SSPM_INTC_IRQ_GRP11_STA0_IRQ_GRP11_STA0            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP11_STA1               (DDRPHY_MD32_BASE_ADDRESS + 0x2204)
+    #define SSPM_INTC_IRQ_GRP11_STA1_IRQ_GRP11_STA1            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP12_STA0               (DDRPHY_MD32_BASE_ADDRESS + 0x2210)
+    #define SSPM_INTC_IRQ_GRP12_STA0_IRQ_GRP12_STA0            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP12_STA1               (DDRPHY_MD32_BASE_ADDRESS + 0x2214)
+    #define SSPM_INTC_IRQ_GRP12_STA1_IRQ_GRP12_STA1            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP13_STA0               (DDRPHY_MD32_BASE_ADDRESS + 0x2220)
+    #define SSPM_INTC_IRQ_GRP13_STA0_IRQ_GRP13_STA0            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP13_STA1               (DDRPHY_MD32_BASE_ADDRESS + 0x2224)
+    #define SSPM_INTC_IRQ_GRP13_STA1_IRQ_GRP13_STA1            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP14_STA0               (DDRPHY_MD32_BASE_ADDRESS + 0x2230)
+    #define SSPM_INTC_IRQ_GRP14_STA0_IRQ_GRP14_STA0            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP14_STA1               (DDRPHY_MD32_BASE_ADDRESS + 0x2234)
+    #define SSPM_INTC_IRQ_GRP14_STA1_IRQ_GRP14_STA1            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP15_STA0               (DDRPHY_MD32_BASE_ADDRESS + 0x2240)
+    #define SSPM_INTC_IRQ_GRP15_STA0_IRQ_GRP15_STA0            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP15_STA1               (DDRPHY_MD32_BASE_ADDRESS + 0x2244)
+    #define SSPM_INTC_IRQ_GRP15_STA1_IRQ_GRP15_STA1            Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_OUT                      (DDRPHY_MD32_BASE_ADDRESS + 0x2250)
+    #define SSPM_INTC_IRQ_OUT_IRQ_OUT                          Fld(15, 0) //[14:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_CLR_TRG                  (DDRPHY_MD32_BASE_ADDRESS + 0x2254)
+    #define SSPM_INTC_IRQ_CLR_TRG_IRQ_CLR_TRG                  Fld(15, 0) //[14:0]
+
+#define DDRPHY_MD32_REG_SSPM_INTC_UART_RX_IRQ                  (DDRPHY_MD32_BASE_ADDRESS + 0x2258)
+    #define SSPM_INTC_UART_RX_IRQ_UART_RX_IRQ                  Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_CK_EN                             (DDRPHY_MD32_BASE_ADDRESS + 0x3000)
+    #define SSPM_CK_EN_R_CLK_EN                                Fld(12, 0) //[11:0]
+    #define SSPM_CK_EN_R_LPIF_CLK_FR                           Fld(1, 12) //[12:12]
+    #define SSPM_CK_EN_R_DCM_MCLK_DIV                          Fld(2, 13) //[14:13]
+    #define SSPM_CK_EN_R_LPIF_CLK_26M                          Fld(1, 15) //[15:15]
+
+#define DDRPHY_MD32_REG_SSPM_MCLK_DIV                          (DDRPHY_MD32_BASE_ADDRESS + 0x3004)
+    #define SSPM_MCLK_DIV_MCLK_DIV                             Fld(2, 0) //[1:0]
+    #define SSPM_MCLK_DIV_RSV0                                 Fld(2, 2) //[3:2]
+    #define SSPM_MCLK_DIV_MCLK_SRC                             Fld(2, 4) //[5:4]
+    #define SSPM_MCLK_DIV_RSV1                                 Fld(2, 6) //[7:6]
+    #define SSPM_MCLK_DIV_MCLK_DCM_EN                          Fld(1, 8) //[8:8]
+    #define SSPM_MCLK_DIV_RSV2                                 Fld(7, 9) //[15:9]
+    #define SSPM_MCLK_DIV_DIVSW_SEL_O                          Fld(4, 16) //[19:16]
+    #define SSPM_MCLK_DIV_CKSRC_SEL_O                          Fld(4, 20) //[23:20]
+    #define SSPM_MCLK_DIV_RSV3                                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_SSPM_DCM_CTRL                          (DDRPHY_MD32_BASE_ADDRESS + 0x3008)
+    #define SSPM_DCM_CTRL_R_DCM_EN                             Fld(12, 0) //[11:0]
+    #define SSPM_DCM_CTRL_WAKEUP_TYPE                          Fld(1, 28) //[28:28]
+    #define SSPM_DCM_CTRL_MD32_GATED                           Fld(1, 30) //[30:30]
+    #define SSPM_DCM_CTRL_CLK_OFF                              Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_SSPM_WAKE_INT                          (DDRPHY_MD32_BASE_ADDRESS + 0x300C)
+    #define SSPM_WAKE_INT_WAKEUP_INT                           Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_CTRL                         (DDRPHY_MD32_BASE_ADDRESS + 0x3010)
+    #define SSPM_UART_CTRL_UART_BCLK_CG                        Fld(1, 0) //[0:0]
+    #define SSPM_UART_CTRL_UART_CLK_SEL                        Fld(2, 1) //[2:1]
+    #define SSPM_UART_CTRL_UART_RST_N                          Fld(1, 3) //[3:3]
+
+#define DDRPHY_MD32_REG_SSPM_DMA_GLBSTA                        (DDRPHY_MD32_BASE_ADDRESS + 0x4000)
+    #define SSPM_DMA_GLBSTA_RUN_1                              Fld(1, 0) //[0:0]
+    #define SSPM_DMA_GLBSTA_INTSTA_1                           Fld(1, 1) //[1:1]
+    #define SSPM_DMA_GLBSTA_RUN_2                              Fld(1, 2) //[2:2]
+    #define SSPM_DMA_GLBSTA_INTSTA_2                           Fld(1, 3) //[3:3]
+    #define SSPM_DMA_GLBSTA_RUN_3                              Fld(1, 4) //[4:4]
+    #define SSPM_DMA_GLBSTA_INTSTA_3                           Fld(1, 5) //[5:5]
+    #define SSPM_DMA_GLBSTA_RUN_4                              Fld(1, 6) //[6:6]
+    #define SSPM_DMA_GLBSTA_INTSTA_4                           Fld(1, 7) //[7:7]
+
+#define DDRPHY_MD32_REG_SSPM_DMA_GLBSTA2                       (DDRPHY_MD32_BASE_ADDRESS + 0x4004)
+    #define SSPM_DMA_GLBSTA2_RUN_1                             Fld(1, 0) //[0:0]
+    #define SSPM_DMA_GLBSTA2_INTSTA_1                          Fld(1, 1) //[1:1]
+    #define SSPM_DMA_GLBSTA2_RUN_2                             Fld(1, 2) //[2:2]
+    #define SSPM_DMA_GLBSTA2_INTSTA_2                          Fld(1, 3) //[3:3]
+    #define SSPM_DMA_GLBSTA2_RUN_3                             Fld(1, 4) //[4:4]
+    #define SSPM_DMA_GLBSTA2_INTSTA_3                          Fld(1, 5) //[5:5]
+    #define SSPM_DMA_GLBSTA2_RUN_4                             Fld(1, 6) //[6:6]
+    #define SSPM_DMA_GLBSTA2_INTSTA_4                          Fld(1, 7) //[7:7]
+
+#define DDRPHY_MD32_REG_SSPM_DMA_GLBLIMITER                    (DDRPHY_MD32_BASE_ADDRESS + 0x4028)
+    #define SSPM_DMA_GLBLIMITER_GLBLIMITER                     Fld(4, 0) //[3:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA1_SRC                          (DDRPHY_MD32_BASE_ADDRESS + 0x4100)
+    #define SSPM_DMA1_SRC_SRC                                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA1_DST                          (DDRPHY_MD32_BASE_ADDRESS + 0x4104)
+    #define SSPM_DMA1_DST_DST                                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA1_WPPT                         (DDRPHY_MD32_BASE_ADDRESS + 0x4108)
+    #define SSPM_DMA1_WPPT_WPPT                                Fld(16, 0) //[15:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA1_WPTO                         (DDRPHY_MD32_BASE_ADDRESS + 0x410C)
+    #define SSPM_DMA1_WPTO_WPTO                                Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA1_COUNT                        (DDRPHY_MD32_BASE_ADDRESS + 0x4110)
+    #define SSPM_DMA1_COUNT_COUNT                              Fld(16, 0) //[15:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA1_CON                          (DDRPHY_MD32_BASE_ADDRESS + 0x4114)
+    #define SSPM_DMA1_CON_SIZE                                 Fld(2, 0) //[1:0]
+    #define SSPM_DMA1_CON_SRC_BEN                              Fld(1, 2) //[2:2]
+    #define SSPM_DMA1_CON_DST_BEN                              Fld(1, 3) //[3:3]
+    #define SSPM_DMA1_CON_DRQ                                  Fld(1, 4) //[4:4]
+    #define SSPM_DMA1_CON_BRUST_TYPE                           Fld(2, 8) //[9:8]
+    #define SSPM_DMA1_CON_INTEN                                Fld(1, 15) //[15:15]
+    #define SSPM_DMA1_CON_WPSD                                 Fld(1, 16) //[16:16]
+    #define SSPM_DMA1_CON_WPEN                                 Fld(1, 17) //[17:17]
+
+#define DDRPHY_MD32_REG_SSPM_DMA1_START                        (DDRPHY_MD32_BASE_ADDRESS + 0x4118)
+    #define SSPM_DMA1_START_START                              Fld(1, 15) //[15:15]
+
+#define DDRPHY_MD32_REG_SSPM_DMA1_INTSTA                       (DDRPHY_MD32_BASE_ADDRESS + 0x411C)
+    #define SSPM_DMA1_INTSTA_INTSTA                            Fld(1, 15) //[15:15]
+
+#define DDRPHY_MD32_REG_SSPM_DMA1_ACKINT                       (DDRPHY_MD32_BASE_ADDRESS + 0x4120)
+    #define SSPM_DMA1_ACKINT_ACKINT                            Fld(1, 15) //[15:15]
+
+#define DDRPHY_MD32_REG_SSPM_DMA1_RLCT                         (DDRPHY_MD32_BASE_ADDRESS + 0x4124)
+    #define SSPM_DMA1_RLCT_RLCT                                Fld(16, 0) //[15:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA1_LIMITER                      (DDRPHY_MD32_BASE_ADDRESS + 0x4128)
+    #define SSPM_DMA1_LIMITER_LIMITER                          Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA2_SRC                          (DDRPHY_MD32_BASE_ADDRESS + 0x4200)
+    #define SSPM_DMA2_SRC_SRC                                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA2_DST                          (DDRPHY_MD32_BASE_ADDRESS + 0x4204)
+    #define SSPM_DMA2_DST_DST                                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA2_WPPT                         (DDRPHY_MD32_BASE_ADDRESS + 0x4208)
+    #define SSPM_DMA2_WPPT_WPPT                                Fld(16, 0) //[15:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA2_WPTO                         (DDRPHY_MD32_BASE_ADDRESS + 0x420C)
+    #define SSPM_DMA2_WPTO_WPTO                                Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA2_COUNT                        (DDRPHY_MD32_BASE_ADDRESS + 0x4210)
+    #define SSPM_DMA2_COUNT_COUNT                              Fld(16, 0) //[15:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA2_CON                          (DDRPHY_MD32_BASE_ADDRESS + 0x4214)
+    #define SSPM_DMA2_CON_SIZE                                 Fld(2, 0) //[1:0]
+    #define SSPM_DMA2_CON_SRC_BEN                              Fld(1, 2) //[2:2]
+    #define SSPM_DMA2_CON_DST_BEN                              Fld(1, 3) //[3:3]
+    #define SSPM_DMA2_CON_DRQ                                  Fld(1, 4) //[4:4]
+    #define SSPM_DMA2_CON_BRUST_TYPE                           Fld(2, 8) //[9:8]
+    #define SSPM_DMA2_CON_INTEN                                Fld(1, 15) //[15:15]
+    #define SSPM_DMA2_CON_WPSD                                 Fld(1, 16) //[16:16]
+    #define SSPM_DMA2_CON_WPEN                                 Fld(1, 17) //[17:17]
+
+#define DDRPHY_MD32_REG_SSPM_DMA2_START                        (DDRPHY_MD32_BASE_ADDRESS + 0x4218)
+    #define SSPM_DMA2_START_START                              Fld(1, 15) //[15:15]
+
+#define DDRPHY_MD32_REG_SSPM_DMA2_INTSTA                       (DDRPHY_MD32_BASE_ADDRESS + 0x421C)
+    #define SSPM_DMA2_INTSTA_INTSTA                            Fld(1, 15) //[15:15]
+
+#define DDRPHY_MD32_REG_SSPM_DMA2_ACKINT                       (DDRPHY_MD32_BASE_ADDRESS + 0x4220)
+    #define SSPM_DMA2_ACKINT_ACKINT                            Fld(1, 15) //[15:15]
+
+#define DDRPHY_MD32_REG_SSPM_DMA2_RLCT                         (DDRPHY_MD32_BASE_ADDRESS + 0x4224)
+    #define SSPM_DMA2_RLCT_RLCT                                Fld(16, 0) //[15:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA2_LIMITER                      (DDRPHY_MD32_BASE_ADDRESS + 0x4228)
+    #define SSPM_DMA2_LIMITER_LIMITER                          Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA3_SRC                          (DDRPHY_MD32_BASE_ADDRESS + 0x4300)
+    #define SSPM_DMA3_SRC_SRC                                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA3_DST                          (DDRPHY_MD32_BASE_ADDRESS + 0x4304)
+    #define SSPM_DMA3_DST_DST                                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA3_WPPT                         (DDRPHY_MD32_BASE_ADDRESS + 0x4308)
+    #define SSPM_DMA3_WPPT_WPPT                                Fld(16, 0) //[15:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA3_WPTO                         (DDRPHY_MD32_BASE_ADDRESS + 0x430C)
+    #define SSPM_DMA3_WPTO_WPTO                                Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA3_COUNT                        (DDRPHY_MD32_BASE_ADDRESS + 0x4310)
+    #define SSPM_DMA3_COUNT_COUNT                              Fld(16, 0) //[15:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA3_CON                          (DDRPHY_MD32_BASE_ADDRESS + 0x4314)
+    #define SSPM_DMA3_CON_SIZE                                 Fld(2, 0) //[1:0]
+    #define SSPM_DMA3_CON_SRC_BEN                              Fld(1, 2) //[2:2]
+    #define SSPM_DMA3_CON_DST_BEN                              Fld(1, 3) //[3:3]
+    #define SSPM_DMA3_CON_DRQ                                  Fld(1, 4) //[4:4]
+    #define SSPM_DMA3_CON_BRUST_TYPE                           Fld(2, 8) //[9:8]
+    #define SSPM_DMA3_CON_INTEN                                Fld(1, 15) //[15:15]
+    #define SSPM_DMA3_CON_WPSD                                 Fld(1, 16) //[16:16]
+    #define SSPM_DMA3_CON_WPEN                                 Fld(1, 17) //[17:17]
+
+#define DDRPHY_MD32_REG_SSPM_DMA3_START                        (DDRPHY_MD32_BASE_ADDRESS + 0x4318)
+    #define SSPM_DMA3_START_START                              Fld(1, 15) //[15:15]
+
+#define DDRPHY_MD32_REG_SSPM_DMA3_INTSTA                       (DDRPHY_MD32_BASE_ADDRESS + 0x431C)
+    #define SSPM_DMA3_INTSTA_INTSTA                            Fld(1, 15) //[15:15]
+
+#define DDRPHY_MD32_REG_SSPM_DMA3_ACKINT                       (DDRPHY_MD32_BASE_ADDRESS + 0x4320)
+    #define SSPM_DMA3_ACKINT_ACKINT                            Fld(1, 15) //[15:15]
+
+#define DDRPHY_MD32_REG_SSPM_DMA3_RLCT                         (DDRPHY_MD32_BASE_ADDRESS + 0x4324)
+    #define SSPM_DMA3_RLCT_RLCT                                Fld(16, 0) //[15:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA3_LIMITER                      (DDRPHY_MD32_BASE_ADDRESS + 0x4328)
+    #define SSPM_DMA3_LIMITER_LIMITER                          Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA4_SRC                          (DDRPHY_MD32_BASE_ADDRESS + 0x4400)
+    #define SSPM_DMA4_SRC_SRC                                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA4_DST                          (DDRPHY_MD32_BASE_ADDRESS + 0x4404)
+    #define SSPM_DMA4_DST_DST                                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA4_WPPT                         (DDRPHY_MD32_BASE_ADDRESS + 0x4408)
+    #define SSPM_DMA4_WPPT_WPPT                                Fld(16, 0) //[15:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA4_WPTO                         (DDRPHY_MD32_BASE_ADDRESS + 0x440C)
+    #define SSPM_DMA4_WPTO_WPTO                                Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA4_COUNT                        (DDRPHY_MD32_BASE_ADDRESS + 0x4410)
+    #define SSPM_DMA4_COUNT_COUNT                              Fld(16, 0) //[15:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA4_CON                          (DDRPHY_MD32_BASE_ADDRESS + 0x4414)
+    #define SSPM_DMA4_CON_SIZE                                 Fld(2, 0) //[1:0]
+    #define SSPM_DMA4_CON_SRC_BEN                              Fld(1, 2) //[2:2]
+    #define SSPM_DMA4_CON_DST_BEN                              Fld(1, 3) //[3:3]
+    #define SSPM_DMA4_CON_DRQ                                  Fld(1, 4) //[4:4]
+    #define SSPM_DMA4_CON_BRUST_TYPE                           Fld(2, 8) //[9:8]
+    #define SSPM_DMA4_CON_INTEN                                Fld(1, 15) //[15:15]
+    #define SSPM_DMA4_CON_WPSD                                 Fld(1, 16) //[16:16]
+    #define SSPM_DMA4_CON_WPEN                                 Fld(1, 17) //[17:17]
+
+#define DDRPHY_MD32_REG_SSPM_DMA4_START                        (DDRPHY_MD32_BASE_ADDRESS + 0x4418)
+    #define SSPM_DMA4_START_START                              Fld(1, 15) //[15:15]
+
+#define DDRPHY_MD32_REG_SSPM_DMA4_INTSTA                       (DDRPHY_MD32_BASE_ADDRESS + 0x441C)
+    #define SSPM_DMA4_INTSTA_INTSTA                            Fld(1, 15) //[15:15]
+
+#define DDRPHY_MD32_REG_SSPM_DMA4_ACKINT                       (DDRPHY_MD32_BASE_ADDRESS + 0x4420)
+    #define SSPM_DMA4_ACKINT_ACKINT                            Fld(1, 15) //[15:15]
+
+#define DDRPHY_MD32_REG_SSPM_DMA4_RLCT                         (DDRPHY_MD32_BASE_ADDRESS + 0x4424)
+    #define SSPM_DMA4_RLCT_RLCT                                Fld(16, 0) //[15:0]
+
+#define DDRPHY_MD32_REG_SSPM_DMA4_LIMITER                      (DDRPHY_MD32_BASE_ADDRESS + 0x4428)
+    #define SSPM_DMA4_LIMITER_LIMITER                          Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_RBR_THR_DLL_ADDR             (DDRPHY_MD32_BASE_ADDRESS + 0x5000)
+    #define SSPM_UART_RBR_THR_DLL_ADDR_RBR                     Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_IER_DLM_ADDR                 (DDRPHY_MD32_BASE_ADDRESS + 0x5004)
+    #define SSPM_UART_IER_DLM_ADDR_RHRI                        Fld(1, 0) //[0:0]
+    #define SSPM_UART_IER_DLM_ADDR_THRI                        Fld(1, 1) //[1:1]
+    #define SSPM_UART_IER_DLM_ADDR_LINT_STSI                   Fld(1, 2) //[2:2]
+    #define SSPM_UART_IER_DLM_ADDR_MODEM_STSI                  Fld(1, 3) //[3:3]
+    #define SSPM_UART_IER_DLM_ADDR_RESERVED                    Fld(1, 4) //[4:4]
+    #define SSPM_UART_IER_DLM_ADDR_XOFFI                       Fld(1, 5) //[5:5]
+    #define SSPM_UART_IER_DLM_ADDR_RTSI                        Fld(1, 6) //[6:6]
+    #define SSPM_UART_IER_DLM_ADDR_CTSI                        Fld(1, 7) //[7:7]
+
+#define DDRPHY_MD32_REG_SSPM_UART_IIR_FCR_EFR_ADDR             (DDRPHY_MD32_BASE_ADDRESS + 0x5008)
+    #define SSPM_UART_IIR_FCR_EFR_ADDR_ID                      Fld(6, 0) //[5:0]
+    #define SSPM_UART_IIR_FCR_EFR_ADDR_FIFOE                   Fld(2, 6) //[7:6]
+
+#define DDRPHY_MD32_REG_SSPM_UART_LCR_ADDR                     (DDRPHY_MD32_BASE_ADDRESS + 0x500C)
+    #define SSPM_UART_LCR_ADDR_CHAR_LENGTH                     Fld(2, 0) //[1:0]
+    #define SSPM_UART_LCR_ADDR_STB                             Fld(1, 2) //[2:2]
+    #define SSPM_UART_LCR_ADDR_PEN                             Fld(1, 3) //[3:3]
+    #define SSPM_UART_LCR_ADDR_EPS                             Fld(1, 4) //[4:4]
+    #define SSPM_UART_LCR_ADDR_SP                              Fld(1, 5) //[5:5]
+    #define SSPM_UART_LCR_ADDR_SB                              Fld(1, 6) //[6:6]
+    #define SSPM_UART_LCR_ADDR_DLAB                            Fld(1, 7) //[7:7]
+
+#define DDRPHY_MD32_REG_SSPM_UART_MCR_XON1_ADDR                (DDRPHY_MD32_BASE_ADDRESS + 0x5010)
+    #define SSPM_UART_MCR_XON1_ADDR_RTS                        Fld(1, 1) //[1:1]
+    #define SSPM_UART_MCR_XON1_ADDR_LOOPBACK_EN                Fld(1, 4) //[4:4]
+    #define SSPM_UART_MCR_XON1_ADDR_XOFF_STATUS                Fld(1, 7) //[7:7]
+
+#define DDRPHY_MD32_REG_SSPM_UART_LSR_XON2_ADDR                (DDRPHY_MD32_BASE_ADDRESS + 0x5014)
+    #define SSPM_UART_LSR_XON2_ADDR_DR                         Fld(1, 0) //[0:0]
+    #define SSPM_UART_LSR_XON2_ADDR_OE                         Fld(1, 1) //[1:1]
+    #define SSPM_UART_LSR_XON2_ADDR_PE                         Fld(1, 2) //[2:2]
+    #define SSPM_UART_LSR_XON2_ADDR_FE                         Fld(1, 3) //[3:3]
+    #define SSPM_UART_LSR_XON2_ADDR_BI                         Fld(1, 4) //[4:4]
+    #define SSPM_UART_LSR_XON2_ADDR_THRE                       Fld(1, 5) //[5:5]
+    #define SSPM_UART_LSR_XON2_ADDR_TEMT                       Fld(1, 6) //[6:6]
+    #define SSPM_UART_LSR_XON2_ADDR_FIFOERR                    Fld(1, 7) //[7:7]
+
+#define DDRPHY_MD32_REG_SSPM_UART_MSR_XOFF1_ADDR               (DDRPHY_MD32_BASE_ADDRESS + 0x5018)
+    #define SSPM_UART_MSR_XOFF1_ADDR_DCTS                      Fld(1, 0) //[0:0]
+    #define SSPM_UART_MSR_XOFF1_ADDR_CTS                       Fld(1, 4) //[4:4]
+
+#define DDRPHY_MD32_REG_SSPM_UART_SCR_XOFF2_ADDR               (DDRPHY_MD32_BASE_ADDRESS + 0x501C)
+    #define SSPM_UART_SCR_XOFF2_ADDR_SCR                       Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_AUTOBAUD_EN_ADDR             (DDRPHY_MD32_BASE_ADDRESS + 0x5020)
+    #define SSPM_UART_AUTOBAUD_EN_ADDR_AUTOBAUD_EN             Fld(1, 0) //[0:0]
+    #define SSPM_UART_AUTOBAUD_EN_ADDR_AUTOBAUD_SEL            Fld(1, 1) //[1:1]
+    #define SSPM_UART_AUTOBAUD_EN_ADDR_SLEEP_ACK_SEL           Fld(1, 2) //[2:2]
+
+#define DDRPHY_MD32_REG_SSPM_UART_RATE_STEP_ADDR               (DDRPHY_MD32_BASE_ADDRESS + 0x5024)
+    #define SSPM_UART_RATE_STEP_ADDR_SPEED                     Fld(2, 0) //[1:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_STEP_COUNT_ADDR              (DDRPHY_MD32_BASE_ADDRESS + 0x5028)
+    #define SSPM_UART_STEP_COUNT_ADDR_SAMPLECOUNT              Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_SAMPLE_COUNT_ADDR            (DDRPHY_MD32_BASE_ADDRESS + 0x502C)
+    #define SSPM_UART_SAMPLE_COUNT_ADDR_SAMPLEPOINT            Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_AUTOBAUD_DATA_ADDR           (DDRPHY_MD32_BASE_ADDRESS + 0x5030)
+    #define SSPM_UART_AUTOBAUD_DATA_ADDR_BAUD_RATE             Fld(4, 0) //[3:0]
+    #define SSPM_UART_AUTOBAUD_DATA_ADDR_BAUD_STAT             Fld(4, 4) //[7:4]
+
+#define DDRPHY_MD32_REG_SSPM_UART_RATE_FIX_ADDR                (DDRPHY_MD32_BASE_ADDRESS + 0x5034)
+    #define SSPM_UART_RATE_FIX_ADDR_RATE_FIX                   Fld(1, 0) //[0:0]
+    #define SSPM_UART_RATE_FIX_ADDR_AUTOBAUD_RATE_FIX          Fld(1, 1) //[1:1]
+    #define SSPM_UART_RATE_FIX_ADDR_FREQ_SEL                   Fld(1, 2) //[2:2]
+
+#define DDRPHY_MD32_REG_SSPM_UART_AUTOBAUD_RATE_ADDR           (DDRPHY_MD32_BASE_ADDRESS + 0x5038)
+    #define SSPM_UART_AUTOBAUD_RATE_ADDR_AUTOBAUDSAMPLE        Fld(6, 0) //[5:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_GUARD_ADDR                   (DDRPHY_MD32_BASE_ADDRESS + 0x503C)
+    #define SSPM_UART_GUARD_ADDR_GUARD_CNT                     Fld(4, 0) //[3:0]
+    #define SSPM_UART_GUARD_ADDR_GUARD_EN                      Fld(1, 4) //[4:4]
+
+#define DDRPHY_MD32_REG_SSPM_UART_ESC_CHAR_ADDR                (DDRPHY_MD32_BASE_ADDRESS + 0x5040)
+    #define SSPM_UART_ESC_CHAR_ADDR_ESC_CHAR                   Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_ESC_EN_ADDR                  (DDRPHY_MD32_BASE_ADDRESS + 0x5044)
+    #define SSPM_UART_ESC_EN_ADDR_ESC_EN                       Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_SLEEP_EN_ADDR                (DDRPHY_MD32_BASE_ADDRESS + 0x5048)
+    #define SSPM_UART_SLEEP_EN_ADDR_SLEEP_EN                   Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_RXDMA_EN_ADDR                (DDRPHY_MD32_BASE_ADDRESS + 0x504C)
+    #define SSPM_UART_RXDMA_EN_ADDR_RX_DMA_EN                  Fld(1, 0) //[0:0]
+    #define SSPM_UART_RXDMA_EN_ADDR_TX_DMA_EN                  Fld(1, 1) //[1:1]
+    #define SSPM_UART_RXDMA_EN_ADDR_TO_CNT_AUTORST             Fld(1, 2) //[2:2]
+    #define SSPM_UART_RXDMA_EN_ADDR_FIFO_LSR_SEL               Fld(1, 3) //[3:3]
+
+#define DDRPHY_MD32_REG_SSPM_UART_RXTRIG_ADDR                  (DDRPHY_MD32_BASE_ADDRESS + 0x5050)
+    #define SSPM_UART_RXTRIG_ADDR_RXTRIG                       Fld(4, 0) //[3:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_FRACDIV_L_ADDR               (DDRPHY_MD32_BASE_ADDRESS + 0x5054)
+    #define SSPM_UART_FRACDIV_L_ADDR_FRACDIV_L                 Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_FRACDIV_M_ADDR               (DDRPHY_MD32_BASE_ADDRESS + 0x5058)
+    #define SSPM_UART_FRACDIV_M_ADDR_FRACDIV_M                 Fld(2, 0) //[1:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_FCR_ADDR                     (DDRPHY_MD32_BASE_ADDRESS + 0x505C)
+    #define SSPM_UART_FCR_ADDR_FIFO_EN                         Fld(1, 0) //[0:0]
+    #define SSPM_UART_FCR_ADDR_RXFIFO_CLR                      Fld(1, 1) //[1:1]
+    #define SSPM_UART_FCR_ADDR_TXFIFO_CLR                      Fld(1, 2) //[2:2]
+    #define SSPM_UART_FCR_ADDR_RESERVED                        Fld(1, 3) //[3:3]
+    #define SSPM_UART_FCR_ADDR_TFTL1_TFTL0                     Fld(2, 4) //[5:4]
+    #define SSPM_UART_FCR_ADDR_RFTL1_RFTL0                     Fld(2, 6) //[7:6]
+
+#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_ADDR                   (DDRPHY_MD32_BASE_ADDRESS + 0x5060)
+    #define SSPM_UART_DEBUG_ADDR_ACC_SEL                       Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_1_ADDR                 (DDRPHY_MD32_BASE_ADDRESS + 0x5064)
+    #define SSPM_UART_DEBUG_1_ADDR_TXSTATE                     Fld(5, 0) //[4:0]
+    #define SSPM_UART_DEBUG_1_ADDR_XCSTATE                     Fld(3, 5) //[7:5]
+
+#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_2_ADDR                 (DDRPHY_MD32_BASE_ADDRESS + 0x5068)
+    #define SSPM_UART_DEBUG_2_ADDR_RXSTATE                     Fld(4, 0) //[3:0]
+    #define SSPM_UART_DEBUG_2_ADDR_IP_TX_DMA0                  Fld(4, 4) //[7:4]
+
+#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_3_ADDR                 (DDRPHY_MD32_BASE_ADDRESS + 0x506C)
+    #define SSPM_UART_DEBUG_3_ADDR_IP_TX_DMA1                  Fld(2, 0) //[1:0]
+    #define SSPM_UART_DEBUG_3_ADDR_TOFFSET_TX_DMA              Fld(6, 2) //[7:2]
+
+#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_4_ADDR                 (DDRPHY_MD32_BASE_ADDRESS + 0x5070)
+    #define SSPM_UART_DEBUG_4_ADDR_TX_WOFFSET                  Fld(6, 0) //[5:0]
+    #define SSPM_UART_DEBUG_4_ADDR_TX_ROFFSET0                 Fld(2, 6) //[7:6]
+
+#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_5_ADDR                 (DDRPHY_MD32_BASE_ADDRESS + 0x5074)
+    #define SSPM_UART_DEBUG_5_ADDR_TX_ROFFSET1                 Fld(4, 0) //[3:0]
+    #define SSPM_UART_DEBUG_5_ADDR_OP_RX_REQ0                  Fld(4, 4) //[7:4]
+
+#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_6_ADDR                 (DDRPHY_MD32_BASE_ADDRESS + 0x5078)
+    #define SSPM_UART_DEBUG_6_ADDR_OP_RX_REQ1                  Fld(2, 0) //[1:0]
+    #define SSPM_UART_DEBUG_6_ADDR_ROFFSET_RXDMA               Fld(6, 2) //[7:2]
+
+#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_7_ADDR                 (DDRPHY_MD32_BASE_ADDRESS + 0x507C)
+    #define SSPM_UART_DEBUG_7_ADDR_RX_WOFFSET                  Fld(6, 0) //[5:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_8_ADDR                 (DDRPHY_MD32_BASE_ADDRESS + 0x5080)
+    #define SSPM_UART_DEBUG_8_ADDR_XON_DET                     Fld(1, 0) //[0:0]
+    #define SSPM_UART_DEBUG_8_ADDR_XOFF_DET                    Fld(1, 1) //[1:1]
+    #define SSPM_UART_DEBUG_8_ADDR_SUPPLOAD                    Fld(1, 2) //[2:2]
+    #define SSPM_UART_DEBUG_8_ADDR_SW_TX_DIS                   Fld(1, 3) //[3:3]
+    #define SSPM_UART_DEBUG_8_ADDR_HW_TX_DIS                   Fld(1, 4) //[4:4]
+    #define SSPM_UART_DEBUG_8_ADDR_SLEEPING                    Fld(1, 5) //[5:5]
+    #define SSPM_UART_DEBUG_8_ADDR_VFIFO_LIMIT                 Fld(1, 6) //[6:6]
+    #define SSPM_UART_DEBUG_8_ADDR_HWFIFO_LIMIT                Fld(1, 7) //[7:7]
+
+#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_SEL                    (DDRPHY_MD32_BASE_ADDRESS + 0x5084)
+    #define SSPM_UART_DEBUG_SEL_UART_DBG_SEL                   Fld(3, 0) //[2:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_DLL_ADDR                     (DDRPHY_MD32_BASE_ADDRESS + 0x5090)
+    #define SSPM_UART_DLL_ADDR_DLL                             Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_DLM_ADDR                     (DDRPHY_MD32_BASE_ADDRESS + 0x5094)
+    #define SSPM_UART_DLM_ADDR_DLM                             Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_EFR_ADDR                     (DDRPHY_MD32_BASE_ADDRESS + 0x5098)
+    #define SSPM_UART_EFR_ADDR_SW_FLOW_CONTROL                 Fld(4, 0) //[3:0]
+    #define SSPM_UART_EFR_ADDR_ENHANCED_EN                     Fld(1, 4) //[4:4]
+    #define SSPM_UART_EFR_ADDR_AUTO_RTS_EN                     Fld(1, 6) //[6:6]
+    #define SSPM_UART_EFR_ADDR_AUTO_CTS_EN                     Fld(1, 7) //[7:7]
+
+#define DDRPHY_MD32_REG_SSPM_UART_FEATURE_SEL                  (DDRPHY_MD32_BASE_ADDRESS + 0x509C)
+    #define SSPM_UART_FEATURE_SEL_FEATURE_SEL                  Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_XON1_ADDR                    (DDRPHY_MD32_BASE_ADDRESS + 0x50A0)
+    #define SSPM_UART_XON1_ADDR_XON1                           Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_XON2_ADDR                    (DDRPHY_MD32_BASE_ADDRESS + 0x50A4)
+    #define SSPM_UART_XON2_ADDR_XON2                           Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_XOFF1_ADDR                   (DDRPHY_MD32_BASE_ADDRESS + 0x50A8)
+    #define SSPM_UART_XOFF1_ADDR_XOFF1                         Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_XOFF2_ADDR                   (DDRPHY_MD32_BASE_ADDRESS + 0x50AC)
+    #define SSPM_UART_XOFF2_ADDR_XOFF2                         Fld(8, 0) //[7:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_UART_RX_SEL_ADDR             (DDRPHY_MD32_BASE_ADDRESS + 0x50B0)
+    #define SSPM_UART_UART_RX_SEL_ADDR_USB_RX_SEL              Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_SLEEP_REQ_ADDR               (DDRPHY_MD32_BASE_ADDRESS + 0x50B4)
+    #define SSPM_UART_SLEEP_REQ_ADDR_SLEEP_REQ                 Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_SLEEP_ACK_ADDR               (DDRPHY_MD32_BASE_ADDRESS + 0x50B8)
+    #define SSPM_UART_SLEEP_ACK_ADDR_SLEEP_ACK                 Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_UART_SPM_SEL                      (DDRPHY_MD32_BASE_ADDRESS + 0x50BC)
+    #define SSPM_UART_SPM_SEL_SPM_SEL                          Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_TWAM_CTRL                         (DDRPHY_MD32_BASE_ADDRESS + 0x6000)
+    #define SSPM_TWAM_CTRL_TWAM_SW_RST                         Fld(1, 0) //[0:0]
+    #define SSPM_TWAM_CTRL_TWAM_EN                             Fld(1, 1) //[1:1]
+    #define SSPM_TWAM_CTRL_SPEED_MODE_EN                       Fld(1, 2) //[2:2]
+
+#define DDRPHY_MD32_REG_SSPM_TWAM_WINDOW_LEN                   (DDRPHY_MD32_BASE_ADDRESS + 0x6004)
+    #define SSPM_TWAM_WINDOW_LEN_TWAM_WINDOW_LEN               Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_TWAM_MON_TYPE                     (DDRPHY_MD32_BASE_ADDRESS + 0x6008)
+    #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE0                  Fld(2, 0) //[1:0]
+    #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE1                  Fld(2, 2) //[3:2]
+    #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE2                  Fld(2, 4) //[5:4]
+    #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE3                  Fld(2, 6) //[7:6]
+    #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE4                  Fld(2, 8) //[9:8]
+    #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE5                  Fld(2, 10) //[11:10]
+    #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE6                  Fld(2, 12) //[13:12]
+    #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE7                  Fld(2, 14) //[15:14]
+    #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE8                  Fld(2, 16) //[17:16]
+    #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE9                  Fld(2, 18) //[19:18]
+    #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE10                 Fld(2, 20) //[21:20]
+    #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE11                 Fld(2, 22) //[23:22]
+    #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE12                 Fld(2, 24) //[25:24]
+    #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE13                 Fld(2, 26) //[27:26]
+    #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE14                 Fld(2, 28) //[29:28]
+    #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE15                 Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_SSPM_TWAM_SIG_SEL0                     (DDRPHY_MD32_BASE_ADDRESS + 0x600C)
+    #define SSPM_TWAM_SIG_SEL0_TWAM_CH0_SIG_SEL                Fld(5, 0) //[4:0]
+    #define SSPM_TWAM_SIG_SEL0_TWAM_CH1_SIG_SEL                Fld(5, 5) //[9:5]
+    #define SSPM_TWAM_SIG_SEL0_TWAM_CH2_SIG_SEL                Fld(5, 10) //[14:10]
+    #define SSPM_TWAM_SIG_SEL0_TWAM_CH3_SIG_SEL                Fld(5, 15) //[19:15]
+    #define SSPM_TWAM_SIG_SEL0_TWAM_CH4_SIG_SEL                Fld(5, 20) //[24:20]
+    #define SSPM_TWAM_SIG_SEL0_TWAM_CH5_SIG_SEL                Fld(5, 25) //[29:25]
+
+#define DDRPHY_MD32_REG_SSPM_TWAM_SIG_SEL1                     (DDRPHY_MD32_BASE_ADDRESS + 0x6010)
+    #define SSPM_TWAM_SIG_SEL1_TWAM_CH6_SIG_SEL                Fld(5, 0) //[4:0]
+    #define SSPM_TWAM_SIG_SEL1_TWAM_CH7_SIG_SEL                Fld(5, 5) //[9:5]
+    #define SSPM_TWAM_SIG_SEL1_TWAM_CH8_SIG_SEL                Fld(5, 10) //[14:10]
+    #define SSPM_TWAM_SIG_SEL1_TWAM_CH9_SIG_SEL                Fld(5, 15) //[19:15]
+    #define SSPM_TWAM_SIG_SEL1_TWAM_CH10_SIG_SEL               Fld(5, 20) //[24:20]
+    #define SSPM_TWAM_SIG_SEL1_TWAM_CH11_SIG_SEL               Fld(5, 25) //[29:25]
+
+#define DDRPHY_MD32_REG_SSPM_TWAM_SIG_SEL2                     (DDRPHY_MD32_BASE_ADDRESS + 0x6014)
+    #define SSPM_TWAM_SIG_SEL2_TWAM_CH12_SIG_SEL               Fld(5, 0) //[4:0]
+    #define SSPM_TWAM_SIG_SEL2_TWAM_CH13_SIG_SEL               Fld(5, 5) //[9:5]
+    #define SSPM_TWAM_SIG_SEL2_TWAM_CH14_SIG_SEL               Fld(5, 10) //[14:10]
+    #define SSPM_TWAM_SIG_SEL2_TWAM_CH15_SIG_SEL               Fld(5, 15) //[19:15]
+
+#define DDRPHY_MD32_REG_SSPM_TWAM_IRQ                          (DDRPHY_MD32_BASE_ADDRESS + 0x6018)
+    #define SSPM_TWAM_IRQ_TIRQ                                 Fld(1, 0) //[0:0]
+    #define SSPM_TWAM_IRQ_IRQ_CLR                              Fld(1, 7) //[7:7]
+    #define SSPM_TWAM_IRQ_IRQ_CLR_FLAG                         Fld(1, 8) //[8:8]
+
+#define DDRPHY_MD32_REG_SSPM_TWAM_TIMER                        (DDRPHY_MD32_BASE_ADDRESS + 0x601C)
+    #define SSPM_TWAM_TIMER_TWAM_TIMER                         Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_WFI_WFE                           (DDRPHY_MD32_BASE_ADDRESS + 0x6020)
+    #define SSPM_WFI_WFE_WFI_WFE                               Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT0                     (DDRPHY_MD32_BASE_ADDRESS + 0x6030)
+    #define SSPM_CUR_IDLE_CNT0_CUR_IDLE_CNT0                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT1                     (DDRPHY_MD32_BASE_ADDRESS + 0x6034)
+    #define SSPM_CUR_IDLE_CNT1_CUR_IDLE_CNT1                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT2                     (DDRPHY_MD32_BASE_ADDRESS + 0x6038)
+    #define SSPM_CUR_IDLE_CNT2_CUR_IDLE_CNT2                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT3                     (DDRPHY_MD32_BASE_ADDRESS + 0x603C)
+    #define SSPM_CUR_IDLE_CNT3_CUR_IDLE_CNT3                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT4                     (DDRPHY_MD32_BASE_ADDRESS + 0x6040)
+    #define SSPM_CUR_IDLE_CNT4_CUR_IDLE_CNT4                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT5                     (DDRPHY_MD32_BASE_ADDRESS + 0x6044)
+    #define SSPM_CUR_IDLE_CNT5_CUR_IDLE_CNT5                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT6                     (DDRPHY_MD32_BASE_ADDRESS + 0x6048)
+    #define SSPM_CUR_IDLE_CNT6_CUR_IDLE_CNT6                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT7                     (DDRPHY_MD32_BASE_ADDRESS + 0x604C)
+    #define SSPM_CUR_IDLE_CNT7_CUR_IDLE_CNT7                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT8                     (DDRPHY_MD32_BASE_ADDRESS + 0x6050)
+    #define SSPM_CUR_IDLE_CNT8_CUR_IDLE_CNT8                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT9                     (DDRPHY_MD32_BASE_ADDRESS + 0x6054)
+    #define SSPM_CUR_IDLE_CNT9_CUR_IDLE_CNT9                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT10                    (DDRPHY_MD32_BASE_ADDRESS + 0x6058)
+    #define SSPM_CUR_IDLE_CNT10_CUR_IDLE_CNT10                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT11                    (DDRPHY_MD32_BASE_ADDRESS + 0x605C)
+    #define SSPM_CUR_IDLE_CNT11_CUR_IDLE_CNT11                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT12                    (DDRPHY_MD32_BASE_ADDRESS + 0x6060)
+    #define SSPM_CUR_IDLE_CNT12_CUR_IDLE_CNT12                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT13                    (DDRPHY_MD32_BASE_ADDRESS + 0x6064)
+    #define SSPM_CUR_IDLE_CNT13_CUR_IDLE_CNT13                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT14                    (DDRPHY_MD32_BASE_ADDRESS + 0x6068)
+    #define SSPM_CUR_IDLE_CNT14_CUR_IDLE_CNT14                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT15                    (DDRPHY_MD32_BASE_ADDRESS + 0x606C)
+    #define SSPM_CUR_IDLE_CNT15_CUR_IDLE_CNT15                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT0                    (DDRPHY_MD32_BASE_ADDRESS + 0x6080)
+    #define SSPM_LAST_IDLE_CNT0_LAST_IDEL_CNT0                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT1                    (DDRPHY_MD32_BASE_ADDRESS + 0x6084)
+    #define SSPM_LAST_IDLE_CNT1_LAST_IDEL_CNT1                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT2                    (DDRPHY_MD32_BASE_ADDRESS + 0x6088)
+    #define SSPM_LAST_IDLE_CNT2_LAST_IDEL_CNT2                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT3                    (DDRPHY_MD32_BASE_ADDRESS + 0x608C)
+    #define SSPM_LAST_IDLE_CNT3_LAST_IDEL_CNT3                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT4                    (DDRPHY_MD32_BASE_ADDRESS + 0x6090)
+    #define SSPM_LAST_IDLE_CNT4_LAST_IDEL_CNT4                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT5                    (DDRPHY_MD32_BASE_ADDRESS + 0x6094)
+    #define SSPM_LAST_IDLE_CNT5_LAST_IDEL_CNT5                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT6                    (DDRPHY_MD32_BASE_ADDRESS + 0x6098)
+    #define SSPM_LAST_IDLE_CNT6_LAST_IDEL_CNT6                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT7                    (DDRPHY_MD32_BASE_ADDRESS + 0x609C)
+    #define SSPM_LAST_IDLE_CNT7_LAST_IDEL_CNT7                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT8                    (DDRPHY_MD32_BASE_ADDRESS + 0x60A0)
+    #define SSPM_LAST_IDLE_CNT8_LAST_IDEL_CNT8                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT9                    (DDRPHY_MD32_BASE_ADDRESS + 0x60A4)
+    #define SSPM_LAST_IDLE_CNT9_LAST_IDEL_CNT9                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT10                   (DDRPHY_MD32_BASE_ADDRESS + 0x60A8)
+    #define SSPM_LAST_IDLE_CNT10_LAST_IDEL_CNT10               Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT11                   (DDRPHY_MD32_BASE_ADDRESS + 0x60AC)
+    #define SSPM_LAST_IDLE_CNT11_LAST_IDEL_CNT11               Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT12                   (DDRPHY_MD32_BASE_ADDRESS + 0x60B0)
+    #define SSPM_LAST_IDLE_CNT12_LAST_IDEL_CNT12               Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT13                   (DDRPHY_MD32_BASE_ADDRESS + 0x60B4)
+    #define SSPM_LAST_IDLE_CNT13_LAST_IDEL_CNT13               Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT14                   (DDRPHY_MD32_BASE_ADDRESS + 0x60B8)
+    #define SSPM_LAST_IDLE_CNT14_LAST_IDEL_CNT14               Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT15                   (DDRPHY_MD32_BASE_ADDRESS + 0x60BC)
+    #define SSPM_LAST_IDLE_CNT15_LAST_IDEL_CNT15               Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_FSM_CFG                           (DDRPHY_MD32_BASE_ADDRESS + 0x7000)
+    #define LPIF_FSM_CFG_LPIF_FMS_SW_RSTB                      Fld(1, 0) //[0:0]
+    #define LPIF_FSM_CFG_LPIF_INTERNAL_TEST                    Fld(1, 1) //[1:1]
+    #define LPIF_FSM_CFG_LPIF_DFS_RUNTIME_MRW_EN               Fld(1, 2) //[2:2]
+    #define LPIF_FSM_CFG_LPIF_FSM_VAL_LOAD_FROM_CFG            Fld(1, 3) //[3:3]
+    #define LPIF_FSM_CFG_LPIF_FSM_CTRL_SINGLE_CH               Fld(1, 4) //[4:4]
+    #define LPIF_FSM_CFG_LPIF_SPM_IN_SYNC_BYPASS               Fld(1, 5) //[5:5]
+    #define LPIF_FSM_CFG_LPIF_FSM_CONTROL_SINGLE_CH_HYBRID_S1  Fld(1, 6) //[6:6]
+    #define LPIF_FSM_CFG_LPIF_PLL_CONTROL_SINGLE_CHANNEL       Fld(1, 7) //[7:7]
+    #define LPIF_FSM_CFG_LPIF_LP_NEW_8X                        Fld(1, 8) //[8:8]
+    #define LPIF_FSM_CFG_LPIF_SHU_SRAM_BASED                   Fld(1, 9) //[9:9]
+    #define LPIF_FSM_CFG_LPIF_SHU_INDEX                        Fld(1, 10) //[10:10]
+    #define LPIF_FSM_CFG_DBG_LATENCY_CNT_EN                    Fld(1, 11) //[11:11]
+    #define LPIF_FSM_CFG_LPIF_FSM                              Fld(10, 12) //[21:12]
+    #define LPIF_FSM_CFG_SR_DEBON_EN                           Fld(1, 22) //[22:22]
+    #define LPIF_FSM_CFG_SR_MIN_PLS_DEBON_EN                   Fld(1, 23) //[23:23]
+    #define LPIF_FSM_CFG_DELAY_PST_ACK_OUTPUT_SEL              Fld(4, 24) //[27:24]
+    #define LPIF_FSM_CFG_DELAY_PST_ABOUT_OUTPUT_SEL            Fld(4, 28) //[31:28]
+
+#define DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0                   (DDRPHY_MD32_BASE_ADDRESS + 0x7004)
+    #define LPIF_LOW_POWER_CFG_0_DMSUS_OFF                     Fld(2, 0) //[1:0]
+    #define LPIF_LOW_POWER_CFG_0_PHYPLL_EN                     Fld(2, 2) //[3:2]
+    #define LPIF_LOW_POWER_CFG_0_DPY_DLL_EN                    Fld(2, 4) //[5:4]
+    #define LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN                Fld(2, 6) //[7:6]
+    #define LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN                 Fld(2, 8) //[9:8]
+    #define LPIF_LOW_POWER_CFG_0_DPY_VREF_EN                   Fld(2, 10) //[11:10]
+    #define LPIF_LOW_POWER_CFG_0_EMI_CLK_OFF_REQ               Fld(2, 12) //[13:12]
+    #define LPIF_LOW_POWER_CFG_0_MEM_CK_OFF                    Fld(2, 14) //[15:14]
+    #define LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN               Fld(2, 16) //[17:16]
+    #define LPIF_LOW_POWER_CFG_0_DR_GATE_RETRY_EN              Fld(2, 18) //[19:18]
+    #define LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN                 Fld(2, 20) //[21:20]
+    #define LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW                Fld(2, 22) //[23:22]
+    #define LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN                Fld(2, 24) //[25:24]
+    #define LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW               Fld(2, 26) //[27:26]
+    #define LPIF_LOW_POWER_CFG_0_DR_SHU_EN                     Fld(2, 28) //[29:28]
+    #define LPIF_LOW_POWER_CFG_0_DR_SHORT_QUEUE                Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1                   (DDRPHY_MD32_BASE_ADDRESS + 0x7008)
+    #define LPIF_LOW_POWER_CFG_1_DR_SHU_LEVEL                  Fld(4, 0) //[3:0]
+    #define LPIF_LOW_POWER_CFG_1_DPY_BCLK_ENABLE               Fld(2, 4) //[5:4]
+    #define LPIF_LOW_POWER_CFG_1_SHU_RESTORE                   Fld(2, 6) //[7:6]
+    #define LPIF_LOW_POWER_CFG_1_DPHY_PRECAL_UP                Fld(2, 8) //[9:8]
+    #define LPIF_LOW_POWER_CFG_1_DPHY_RXDLY_TRACK_EN           Fld(2, 10) //[11:10]
+    #define LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL                Fld(2, 12) //[13:12]
+    #define LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL                Fld(2, 14) //[15:14]
+    #define LPIF_LOW_POWER_CFG_1_DMYRD_EN                      Fld(2, 16) //[17:16]
+    #define LPIF_LOW_POWER_CFG_1_TX_TRACKING_DIS               Fld(2, 18) //[19:18]
+    #define LPIF_LOW_POWER_CFG_1_TX_TRACKING_RETRY_EN          Fld(2, 20) //[21:20]
+    #define LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL             Fld(8, 22) //[29:22]
+    #define LPIF_LOW_POWER_CFG_1_DR_SRAM_LOAD                  Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2                   (DDRPHY_MD32_BASE_ADDRESS + 0x700C)
+    #define LPIF_LOW_POWER_CFG_2_DR_SRAM_RESTORE               Fld(2, 0) //[1:0]
+    #define LPIF_LOW_POWER_CFG_2_DR_SHU_LEVEL_SRAM_LATCH       Fld(2, 2) //[3:2]
+    #define LPIF_LOW_POWER_CFG_2_DPY_MODE_SW                   Fld(2, 4) //[5:4]
+    #define LPIF_LOW_POWER_CFG_2_EMI_SLEEP_PROT_EN             Fld(1, 6) //[6:6]
+    #define LPIF_LOW_POWER_CFG_2_MPLLOUT_OFF                   Fld(1, 7) //[7:7]
+    #define LPIF_LOW_POWER_CFG_2_DPY_RESERVED                  Fld(8, 8) //[15:8]
+    #define LPIF_LOW_POWER_CFG_2_DRAMC_DFS_STA                 Fld(13, 16) //[28:16]
+    #define LPIF_LOW_POWER_CFG_2_MPLL_S_OFF                    Fld(1, 29) //[29:29]
+    #define LPIF_LOW_POWER_CFG_2_FHC_PAUSE_MPLL                Fld(1, 30) //[30:30]
+    #define LPIF_LOW_POWER_CFG_2_FHC_PAUSE_MEM                 Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_0                    (DDRPHY_MD32_BASE_ADDRESS + 0x7010)
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DMSUS_OFF              Fld(1, 0) //[0:0]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_EN              Fld(1, 1) //[1:1]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_EN             Fld(1, 2) //[2:2]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_2ND_DLL_EN         Fld(1, 3) //[3:3]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_CK_EN          Fld(1, 4) //[4:4]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_VREF_EN            Fld(1, 5) //[5:5]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_EMI_CLK_OFF_REQ        Fld(1, 6) //[6:6]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_MEM_CK_OFF             Fld(1, 7) //[7:7]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DDRPHY_FB_CK_EN        Fld(1, 8) //[8:8]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_GATE_RETRY_EN       Fld(1, 9) //[9:9]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN          Fld(1, 10) //[10:10]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_MODE_SW         Fld(1, 11) //[11:11]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL2_SHU_EN         Fld(1, 12) //[12:12]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL2_MODE_SW        Fld(1, 13) //[13:13]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SHU_EN              Fld(1, 14) //[14:14]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SHORT_QUEUE         Fld(1, 15) //[15:15]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SHU_LEVEL           Fld(1, 16) //[16:16]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_BCLK_ENABLE        Fld(1, 17) //[17:17]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_SHU_RESTORE            Fld(1, 18) //[18:18]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPHY_PRECAL_UP         Fld(1, 19) //[19:19]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPHY_RXDLY_TRACK_EN    Fld(1, 20) //[20:20]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DMY_EN_MOD_SEL         Fld(1, 21) //[21:21]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DMYRD_INTV_SEL         Fld(1, 22) //[22:22]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DMYRD_EN               Fld(1, 23) //[23:23]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_TX_TRACKING_DIS        Fld(1, 24) //[24:24]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_TX_TRACKING_RETRY_EN   Fld(1, 25) //[25:25]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SHU_SRAM_LEVEL      Fld(1, 26) //[26:26]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SRAM_LOAD           Fld(1, 27) //[27:27]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SRAM_RESTORE        Fld(1, 28) //[28:28]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SHU_LEVEL_SRAM_LATCH Fld(1, 29) //[29:29]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_RESERVED           Fld(1, 30) //[30:30]
+    #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DRAMC_DFS_STA          Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_1                    (DDRPHY_MD32_BASE_ADDRESS + 0x7014)
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_MODE_SW            Fld(1, 0) //[0:0]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_MPLL_S_OFF             Fld(1, 1) //[1:1]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_FHC_PAUSE_MPLL         Fld(1, 2) //[2:2]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_FHC_PAUSE_MEM          Fld(1, 3) //[3:3]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_MCK8X_EN           Fld(1, 4) //[4:4]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_MIDPI_EN           Fld(1, 5) //[5:5]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_PI_RESETB_EN       Fld(1, 6) //[6:6]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DVFS_MEM_CK_MUX_UPDATE Fld(1, 7) //[7:7]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DVFS_MEM_CK_MUX_SEL    Fld(1, 8) //[8:8]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_DSM_EN             Fld(1, 9) //[9:9]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_PICG_FREE          Fld(1, 10) //[10:10]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_FASTK_RDDQS_EN     Fld(1, 11) //[11:11]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_CS_PULL_UP_EN      Fld(1, 12) //[12:12]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_CS_PULL_DN_EN      Fld(1, 13) //[13:13]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_CA_PULL_UP_EN      Fld(1, 14) //[14:14]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_CA_PULL_DN_EN      Fld(1, 15) //[15:15]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_MPLLOUT_OFF            Fld(1, 16) //[16:16]
+    #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_EMI_S1_MODE_ASYNC      Fld(1, 17) //[17:17]
+    #define LPIF_FSM_OUT_CTRL_1_RESERVED_X14_31_16             Fld(14, 18) //[31:18]
+
+#define DDRPHY_MD32_REG_LPIF_IPC_MASK_0                        (DDRPHY_MD32_BASE_ADDRESS + 0x7018)
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0               Fld(1, 0) //[0:0]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_01              Fld(1, 1) //[1:1]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_02              Fld(1, 2) //[2:2]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_03              Fld(1, 3) //[3:3]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_04              Fld(1, 4) //[4:4]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_05              Fld(1, 5) //[5:5]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_06              Fld(1, 6) //[6:6]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_07              Fld(1, 7) //[7:7]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_08              Fld(1, 8) //[8:8]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_09              Fld(1, 9) //[9:9]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0A              Fld(1, 10) //[10:10]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0B              Fld(1, 11) //[11:11]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0C              Fld(1, 12) //[12:12]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0D              Fld(1, 13) //[13:13]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0E              Fld(1, 14) //[14:14]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0F              Fld(1, 15) //[15:15]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_10              Fld(1, 16) //[16:16]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_11              Fld(1, 17) //[17:17]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_12              Fld(1, 18) //[18:18]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_13              Fld(1, 19) //[19:19]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_14              Fld(1, 20) //[20:20]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_15              Fld(1, 21) //[21:21]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_16              Fld(1, 22) //[22:22]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_17              Fld(1, 23) //[23:23]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_18              Fld(1, 24) //[24:24]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_19              Fld(1, 25) //[25:25]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1A              Fld(1, 26) //[26:26]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1B              Fld(1, 27) //[27:27]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1C              Fld(1, 28) //[28:28]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1D              Fld(1, 29) //[29:29]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1E              Fld(1, 30) //[30:30]
+    #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1F              Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_IPC_MASK_1                        (DDRPHY_MD32_BASE_ADDRESS + 0x701C)
+    #define LPIF_IPC_MASK_1_PWR_STATE_IPC_MASK_RESERVED        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_0                        (DDRPHY_MD32_BASE_ADDRESS + 0x7020)
+    #define LPIF_FSM_CTRL_0_LPIF_SW_DDR_PST_ABORT_ACK          Fld(1, 0) //[0:0]
+    #define LPIF_FSM_CTRL_0_LPIF_SW_DDR_PST_ACK                Fld(1, 1) //[1:1]
+    #define LPIF_FSM_CTRL_0_RELEASE_LPIF_IRQ                   Fld(1, 2) //[2:2]
+    #define LPIF_FSM_CTRL_0_RELEASE_DDR_PST_ACK                Fld(1, 3) //[3:3]
+    #define LPIF_FSM_CTRL_0_DFS_STATUS_RECORD                  Fld(4, 4) //[7:4]
+    #define LPIF_FSM_CTRL_0_DVS_STATUS_RECORD                  Fld(1, 8) //[8:8]
+    #define LPIF_FSM_CTRL_0_RUN_TIME_STATUS_RECORD             Fld(1, 9) //[9:9]
+    #define LPIF_FSM_CTRL_0_RESERVED_X20_11_10                 Fld(2, 10) //[11:10]
+    #define LPIF_FSM_CTRL_0_DFS_STATUS_RECORD_UPDATE           Fld(1, 12) //[12:12]
+    #define LPIF_FSM_CTRL_0_DVS_STATUS_RECORD_UPDATE           Fld(1, 13) //[13:13]
+    #define LPIF_FSM_CTRL_0_RUN_TIME_STATUS_RECORD_UPDATE      Fld(1, 14) //[14:14]
+    #define LPIF_FSM_CTRL_0_RESERVED_X20_15_15                 Fld(1, 15) //[15:15]
+    #define LPIF_FSM_CTRL_0_JUMP_TO_SIDLE                      Fld(1, 16) //[16:16]
+    #define LPIF_FSM_CTRL_0_JUMP_TO_SR                         Fld(1, 17) //[17:17]
+    #define LPIF_FSM_CTRL_0_JUMP_TO_S1                         Fld(1, 18) //[18:18]
+    #define LPIF_FSM_CTRL_0_JUMP_TO_S0                         Fld(1, 19) //[19:19]
+    #define LPIF_FSM_CTRL_0_JUMP_TO_HYBRID_S1                  Fld(1, 20) //[20:20]
+    #define LPIF_FSM_CTRL_0_JUMP_TO_DFS                        Fld(1, 21) //[21:21]
+    #define LPIF_FSM_CTRL_0_JUMP_TO_DVS_ENTR                   Fld(1, 22) //[22:22]
+    #define LPIF_FSM_CTRL_0_JUMP_TO_DVS_EXIT                   Fld(1, 23) //[23:23]
+    #define LPIF_FSM_CTRL_0_JUMP_TO_EN_RUNTIME                 Fld(1, 24) //[24:24]
+    #define LPIF_FSM_CTRL_0_JUMP_TO_DIS_RUNTIME                Fld(1, 25) //[25:25]
+    #define LPIF_FSM_CTRL_0_DRAMC_S0_STATUS                    Fld(2, 26) //[27:26]
+    #define LPIF_FSM_CTRL_0_RESERVED_X20_31_28                 Fld(4, 28) //[31:28]
+
+#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_1                        (DDRPHY_MD32_BASE_ADDRESS + 0x7024)
+    #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_0                   Fld(1, 0) //[0:0]
+    #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_1                   Fld(1, 1) //[1:1]
+    #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_2                   Fld(1, 2) //[2:2]
+    #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_3                   Fld(1, 3) //[3:3]
+    #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_4                   Fld(1, 4) //[4:4]
+    #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_5                   Fld(1, 5) //[5:5]
+    #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_6                   Fld(1, 6) //[6:6]
+    #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_7                   Fld(1, 7) //[7:7]
+    #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_8                   Fld(1, 8) //[8:8]
+    #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_9                   Fld(1, 9) //[9:9]
+    #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_10                  Fld(1, 10) //[10:10]
+    #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_11                  Fld(1, 11) //[11:11]
+    #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_12                  Fld(1, 12) //[12:12]
+    #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_13                  Fld(1, 13) //[13:13]
+    #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_14                  Fld(1, 14) //[14:14]
+    #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_15                  Fld(1, 15) //[15:15]
+    #define LPIF_FSM_CTRL_1_DMYRD_EN_0                         Fld(1, 16) //[16:16]
+    #define LPIF_FSM_CTRL_1_DMYRD_EN_1                         Fld(1, 17) //[17:17]
+    #define LPIF_FSM_CTRL_1_DMYRD_EN_2                         Fld(1, 18) //[18:18]
+    #define LPIF_FSM_CTRL_1_DMYRD_EN_3                         Fld(1, 19) //[19:19]
+    #define LPIF_FSM_CTRL_1_DMYRD_EN_4                         Fld(1, 20) //[20:20]
+    #define LPIF_FSM_CTRL_1_DMYRD_EN_5                         Fld(1, 21) //[21:21]
+    #define LPIF_FSM_CTRL_1_DMYRD_EN_6                         Fld(1, 22) //[22:22]
+    #define LPIF_FSM_CTRL_1_DMYRD_EN_7                         Fld(1, 23) //[23:23]
+    #define LPIF_FSM_CTRL_1_DMYRD_EN_8                         Fld(1, 24) //[24:24]
+    #define LPIF_FSM_CTRL_1_DMYRD_EN_9                         Fld(1, 25) //[25:25]
+    #define LPIF_FSM_CTRL_1_DMYRD_EN_10                        Fld(1, 26) //[26:26]
+    #define LPIF_FSM_CTRL_1_DMYRD_EN_11                        Fld(1, 27) //[27:27]
+    #define LPIF_FSM_CTRL_1_DMYRD_EN_12                        Fld(1, 28) //[28:28]
+    #define LPIF_FSM_CTRL_1_DMYRD_EN_13                        Fld(1, 29) //[29:29]
+    #define LPIF_FSM_CTRL_1_DMYRD_EN_14                        Fld(1, 30) //[30:30]
+    #define LPIF_FSM_CTRL_1_DMYRD_EN_15                        Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_2                        (DDRPHY_MD32_BASE_ADDRESS + 0x7028)
+    #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_0                  Fld(1, 0) //[0:0]
+    #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_1                  Fld(1, 1) //[1:1]
+    #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_2                  Fld(1, 2) //[2:2]
+    #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_3                  Fld(1, 3) //[3:3]
+    #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_4                  Fld(1, 4) //[4:4]
+    #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_5                  Fld(1, 5) //[5:5]
+    #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_6                  Fld(1, 6) //[6:6]
+    #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_7                  Fld(1, 7) //[7:7]
+    #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_8                  Fld(1, 8) //[8:8]
+    #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_9                  Fld(1, 9) //[9:9]
+    #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_10                 Fld(1, 10) //[10:10]
+    #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_11                 Fld(1, 11) //[11:11]
+    #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_12                 Fld(1, 12) //[12:12]
+    #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_13                 Fld(1, 13) //[13:13]
+    #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_14                 Fld(1, 14) //[14:14]
+    #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_15                 Fld(1, 15) //[15:15]
+    #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_0                  Fld(1, 16) //[16:16]
+    #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_1                  Fld(1, 17) //[17:17]
+    #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_2                  Fld(1, 18) //[18:18]
+    #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_3                  Fld(1, 19) //[19:19]
+    #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_4                  Fld(1, 20) //[20:20]
+    #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_5                  Fld(1, 21) //[21:21]
+    #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_6                  Fld(1, 22) //[22:22]
+    #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_7                  Fld(1, 23) //[23:23]
+    #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_8                  Fld(1, 24) //[24:24]
+    #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_9                  Fld(1, 25) //[25:25]
+    #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_10                 Fld(1, 26) //[26:26]
+    #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_11                 Fld(1, 27) //[27:27]
+    #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_12                 Fld(1, 28) //[28:28]
+    #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_13                 Fld(1, 29) //[29:29]
+    #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_14                 Fld(1, 30) //[30:30]
+    #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_15                 Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_3                        (DDRPHY_MD32_BASE_ADDRESS + 0x702C)
+    #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_0                Fld(1, 0) //[0:0]
+    #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_1                Fld(1, 1) //[1:1]
+    #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_2                Fld(1, 2) //[2:2]
+    #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_3                Fld(1, 3) //[3:3]
+    #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_4                Fld(1, 4) //[4:4]
+    #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_5                Fld(1, 5) //[5:5]
+    #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_6                Fld(1, 6) //[6:6]
+    #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_7                Fld(1, 7) //[7:7]
+    #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_8                Fld(1, 8) //[8:8]
+    #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_9                Fld(1, 9) //[9:9]
+    #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_10               Fld(1, 10) //[10:10]
+    #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_11               Fld(1, 11) //[11:11]
+    #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_12               Fld(1, 12) //[12:12]
+    #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_13               Fld(1, 13) //[13:13]
+    #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_14               Fld(1, 14) //[14:14]
+    #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_15               Fld(1, 15) //[15:15]
+    #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_0               Fld(1, 16) //[16:16]
+    #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_1               Fld(1, 17) //[17:17]
+    #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_2               Fld(1, 18) //[18:18]
+    #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_3               Fld(1, 19) //[19:19]
+    #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_4               Fld(1, 20) //[20:20]
+    #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_5               Fld(1, 21) //[21:21]
+    #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_6               Fld(1, 22) //[22:22]
+    #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_7               Fld(1, 23) //[23:23]
+    #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_8               Fld(1, 24) //[24:24]
+    #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_9               Fld(1, 25) //[25:25]
+    #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_10              Fld(1, 26) //[26:26]
+    #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_11              Fld(1, 27) //[27:27]
+    #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_12              Fld(1, 28) //[28:28]
+    #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_13              Fld(1, 29) //[29:29]
+    #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_14              Fld(1, 30) //[30:30]
+    #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_15              Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_4                        (DDRPHY_MD32_BASE_ADDRESS + 0x7030)
+    #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_0                 Fld(1, 0) //[0:0]
+    #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_1                 Fld(1, 1) //[1:1]
+    #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_2                 Fld(1, 2) //[2:2]
+    #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_3                 Fld(1, 3) //[3:3]
+    #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_4                 Fld(1, 4) //[4:4]
+    #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_5                 Fld(1, 5) //[5:5]
+    #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_6                 Fld(1, 6) //[6:6]
+    #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_7                 Fld(1, 7) //[7:7]
+    #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_8                 Fld(1, 8) //[8:8]
+    #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_9                 Fld(1, 9) //[9:9]
+    #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_10                Fld(1, 10) //[10:10]
+    #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_11                Fld(1, 11) //[11:11]
+    #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_12                Fld(1, 12) //[12:12]
+    #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_13                Fld(1, 13) //[13:13]
+    #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_14                Fld(1, 14) //[14:14]
+    #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_15                Fld(1, 15) //[15:15]
+    #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_0            Fld(1, 16) //[16:16]
+    #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_1            Fld(1, 17) //[17:17]
+    #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_2            Fld(1, 18) //[18:18]
+    #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_3            Fld(1, 19) //[19:19]
+    #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_4            Fld(1, 20) //[20:20]
+    #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_5            Fld(1, 21) //[21:21]
+    #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_6            Fld(1, 22) //[22:22]
+    #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_7            Fld(1, 23) //[23:23]
+    #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_8            Fld(1, 24) //[24:24]
+    #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_9            Fld(1, 25) //[25:25]
+    #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_10           Fld(1, 26) //[26:26]
+    #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_11           Fld(1, 27) //[27:27]
+    #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_12           Fld(1, 28) //[28:28]
+    #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_13           Fld(1, 29) //[29:29]
+    #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_14           Fld(1, 30) //[30:30]
+    #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_15           Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_FSM_CFG_1                         (DDRPHY_MD32_BASE_ADDRESS + 0x7034)
+    #define LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL                 Fld(1, 0) //[0:0]
+    #define LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND             Fld(1, 1) //[1:1]
+    #define LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR         Fld(1, 2) //[2:2]
+    #define LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND     Fld(1, 3) //[3:3]
+    #define LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW            Fld(1, 4) //[4:4]
+    #define LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND        Fld(1, 5) //[5:5]
+    #define LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL              Fld(1, 6) //[6:6]
+    #define LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL_2ND          Fld(1, 7) //[7:7]
+
+#define DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3                   (DDRPHY_MD32_BASE_ADDRESS + 0x7038)
+    #define LPIF_LOW_POWER_CFG_3_DPY_MCK8X_EN                  Fld(2, 0) //[1:0]
+    #define LPIF_LOW_POWER_CFG_3_DPY_MIDPI_EN                  Fld(2, 2) //[3:2]
+    #define LPIF_LOW_POWER_CFG_3_DPY_PI_RESETB_EN              Fld(2, 4) //[5:4]
+    #define LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE        Fld(2, 6) //[7:6]
+    #define LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL           Fld(4, 8) //[11:8]
+    #define LPIF_LOW_POWER_CFG_3_DPY_DSM_EN                    Fld(2, 12) //[13:12]
+    #define LPIF_LOW_POWER_CFG_3_DPY_FASTK_RDDQS_EN            Fld(2, 14) //[15:14]
+    #define LPIF_LOW_POWER_CFG_3_DPY_CS_PULL_UP_EN             Fld(2, 16) //[17:16]
+    #define LPIF_LOW_POWER_CFG_3_DPY_CS_PULL_DN_EN             Fld(2, 18) //[19:18]
+    #define LPIF_LOW_POWER_CFG_3_DPY_CA_PULL_UP_EN             Fld(2, 20) //[21:20]
+    #define LPIF_LOW_POWER_CFG_3_DPY_CA_PULL_DN_EN             Fld(2, 22) //[23:22]
+    #define LPIF_LOW_POWER_CFG_3_EMI_S1_MODE_ASYNC             Fld(1, 24) //[24:24]
+    #define LPIF_LOW_POWER_CFG_3_RESERVED_X38_25_25            Fld(1, 25) //[25:25]
+    #define LPIF_LOW_POWER_CFG_3_DPY_PICG_FREE                 Fld(2, 26) //[27:26]
+    #define LPIF_LOW_POWER_CFG_3_RESERVED_X38_31_28            Fld(4, 28) //[31:28]
+
+#define DDRPHY_MD32_REG_LPIF_DFD_DBUG_0                        (DDRPHY_MD32_BASE_ADDRESS + 0x703C)
+    #define LPIF_DFD_DBUG_0_LPIF_DFD_DEBUG_ISO_EN              Fld(1, 0) //[0:0]
+    #define LPIF_DFD_DBUG_0_MD32_DRAMC_CKGEN_MCK_CG_EN         Fld(1, 1) //[1:1]
+    #define LPIF_DFD_DBUG_0_RESERVED_X3C_31_2                  Fld(30, 2) //[31:2]
+
+#define DDRPHY_MD32_REG_LPIF_RESERVED_3                        (DDRPHY_MD32_BASE_ADDRESS + 0x7040)
+    #define LPIF_RESERVED_3_RESERVED_X40_31_0                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_0             (DDRPHY_MD32_BASE_ADDRESS + 0x7044)
+    #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_TIME_OUT_CLR    Fld(1, 0) //[0:0]
+    #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_20US_CLR        Fld(1, 1) //[1:1]
+    #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_12US_CLR        Fld(1, 2) //[2:2]
+    #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_DLL_1ST_LOCKING_CLR Fld(1, 3) //[3:3]
+    #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_DLL_2ND_LOCKING_CLR Fld(1, 4) //[4:4]
+    #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_CK_OFF_TO_DMSUS_CLR Fld(1, 5) //[5:5]
+    #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_50NS_CLR        Fld(1, 6) //[6:6]
+    #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_4US_CLR         Fld(1, 7) //[7:7]
+    #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_SR_DEBON_CLR    Fld(1, 8) //[8:8]
+    #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_SR_MIN_PLS_DEBON_CLR Fld(1, 9) //[9:9]
+    #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_HW_S1_STEP_CLR  Fld(1, 10) //[10:10]
+    #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_256MCK_CLR      Fld(1, 11) //[11:11]
+    #define LPIF_TIMING_COUNTER_CTRL_0_RESERVED_X44_31_12      Fld(20, 12) //[31:12]
+
+#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_1             (DDRPHY_MD32_BASE_ADDRESS + 0x7048)
+    #define LPIF_TIMING_COUNTER_CTRL_1_FSM_COUNTER_CLK2        Fld(4, 0) //[3:0]
+    #define LPIF_TIMING_COUNTER_CTRL_1_FSM_COUNTER_CLK1        Fld(4, 4) //[7:4]
+    #define LPIF_TIMING_COUNTER_CTRL_1_FSM_COUNTER_CLK0        Fld(4, 8) //[11:8]
+    #define LPIF_TIMING_COUNTER_CTRL_1_COUNTER_SR_MIN_PLS_DEBON Fld(8, 12) //[19:12]
+    #define LPIF_TIMING_COUNTER_CTRL_1_COUNTER_SR_DEBON        Fld(11, 20) //[30:20]
+    #define LPIF_TIMING_COUNTER_CTRL_1_RESERVED_X44_31_31      Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_2             (DDRPHY_MD32_BASE_ADDRESS + 0x704C)
+    #define LPIF_TIMING_COUNTER_CTRL_2_COUNTER_DLL_1ST_LOCKING_CLK2 Fld(8, 0) //[7:0]
+    #define LPIF_TIMING_COUNTER_CTRL_2_COUNTER_DLL_2ND_LOCKING_CLK2 Fld(8, 8) //[15:8]
+    #define LPIF_TIMING_COUNTER_CTRL_2_COUNTER_CK_OFF_TO_DMSUS_CLK2 Fld(8, 16) //[23:16]
+    #define LPIF_TIMING_COUNTER_CTRL_2_COUNTER_50NS_CLK2       Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_3             (DDRPHY_MD32_BASE_ADDRESS + 0x7050)
+    #define LPIF_TIMING_COUNTER_CTRL_3_COUNTER_DLL_1ST_LOCKING_CLK1 Fld(8, 0) //[7:0]
+    #define LPIF_TIMING_COUNTER_CTRL_3_COUNTER_DLL_2ND_LOCKING_CLK1 Fld(8, 8) //[15:8]
+    #define LPIF_TIMING_COUNTER_CTRL_3_COUNTER_CK_OFF_TO_DMSUS_CLK1 Fld(8, 16) //[23:16]
+    #define LPIF_TIMING_COUNTER_CTRL_3_COUNTER_50NS_CLK1       Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_4             (DDRPHY_MD32_BASE_ADDRESS + 0x7054)
+    #define LPIF_TIMING_COUNTER_CTRL_4_COUNTER_DLL_1ST_LOCKING_CLK0 Fld(8, 0) //[7:0]
+    #define LPIF_TIMING_COUNTER_CTRL_4_COUNTER_DLL_2ND_LOCKING_CLK0 Fld(8, 8) //[15:8]
+    #define LPIF_TIMING_COUNTER_CTRL_4_COUNTER_CK_OFF_TO_DMSUS_CLK0 Fld(8, 16) //[23:16]
+    #define LPIF_TIMING_COUNTER_CTRL_4_COUNTER_50NS_CLK0       Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_5             (DDRPHY_MD32_BASE_ADDRESS + 0x7058)
+    #define LPIF_TIMING_COUNTER_CTRL_5_COUNTER_20US_26M        Fld(10, 0) //[9:0]
+    #define LPIF_TIMING_COUNTER_CTRL_5_RESERVED_X58_15_10      Fld(6, 10) //[15:10]
+    #define LPIF_TIMING_COUNTER_CTRL_5_COUNTER_TIME_OUT_26M    Fld(16, 16) //[31:16]
+
+#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_6             (DDRPHY_MD32_BASE_ADDRESS + 0x705C)
+    #define LPIF_TIMING_COUNTER_CTRL_6_COUNTER_12US_26M        Fld(10, 0) //[9:0]
+    #define LPIF_TIMING_COUNTER_CTRL_6_RESERVED_X5C_15_11      Fld(2, 10) //[11:10]
+    #define LPIF_TIMING_COUNTER_CTRL_6_COUNTER_4US_26M         Fld(10, 12) //[21:12]
+    #define LPIF_TIMING_COUNTER_CTRL_6_RESERVED_X5C_31_22      Fld(10, 22) //[31:22]
+
+#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_5                        (DDRPHY_MD32_BASE_ADDRESS + 0x7060)
+    #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_0              Fld(2, 0) //[1:0]
+    #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_1              Fld(2, 2) //[3:2]
+    #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_2              Fld(2, 4) //[5:4]
+    #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_3              Fld(2, 6) //[7:6]
+    #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_4              Fld(2, 8) //[9:8]
+    #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_5              Fld(2, 10) //[11:10]
+    #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_6              Fld(2, 12) //[13:12]
+    #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_7              Fld(2, 14) //[15:14]
+    #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_8              Fld(2, 16) //[17:16]
+    #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_9              Fld(2, 18) //[19:18]
+    #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_10             Fld(2, 20) //[21:20]
+    #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_11             Fld(2, 22) //[23:22]
+    #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_12             Fld(2, 24) //[25:24]
+    #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_13             Fld(2, 26) //[27:26]
+    #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_14             Fld(2, 28) //[29:28]
+    #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_15             Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_RESERVED_5                        (DDRPHY_MD32_BASE_ADDRESS + 0x7064)
+    #define LPIF_RESERVED_5_COUNTER_HW_S1_STEP                 Fld(4, 0) //[3:0]
+    #define LPIF_RESERVED_5_COUNTER_256MCK                     Fld(9, 4) //[12:4]
+    #define LPIF_RESERVED_5_RESERVED_X64_31_13                 Fld(19, 13) //[31:13]
+
+#define DDRPHY_MD32_REG_LPIF_RESERVED_6                        (DDRPHY_MD32_BASE_ADDRESS + 0x7068)
+    #define LPIF_RESERVED_6_MAX_CNT_SREF_REQ_HIGH_TO_SREF_ACK  Fld(8, 0) //[7:0]
+    #define LPIF_RESERVED_6_MAX_CNT_SREF_REQ_LOW_TO_SREF_ACK   Fld(8, 8) //[15:8]
+    #define LPIF_RESERVED_6_MAX_CNT_SHU_EN_HIGH_TO_ACK         Fld(8, 16) //[23:16]
+    #define LPIF_RESERVED_6_MAX_CNT_HW_S1_REQ_LOW_TO_SREF_ACK_LOW Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_RESERVED_7                        (DDRPHY_MD32_BASE_ADDRESS + 0x706C)
+    #define LPIF_RESERVED_7_RESERVED_X6C_31_0                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_RESERVED_8                        (DDRPHY_MD32_BASE_ADDRESS + 0x7070)
+    #define LPIF_RESERVED_8_RESERVED_X70_31_0                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_RESERVED_9                        (DDRPHY_MD32_BASE_ADDRESS + 0x7074)
+    #define LPIF_RESERVED_9_RESERVED_X74_31_0                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_RESERVED_10                       (DDRPHY_MD32_BASE_ADDRESS + 0x7078)
+    #define LPIF_RESERVED_10_RESERVED_X78_31_0                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_RESERVED_11                       (DDRPHY_MD32_BASE_ADDRESS + 0x707C)
+    #define LPIF_RESERVED_11_RESERVED_X7C_31_0                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_SEMA_0                            (DDRPHY_MD32_BASE_ADDRESS + 0x7080)
+    #define LPIF_SEMA_0_SEMA_0_M0                              Fld(1, 0) //[0:0]
+    #define LPIF_SEMA_0_SEMA_1_M0                              Fld(1, 1) //[1:1]
+    #define LPIF_SEMA_0_SEMA_2_M0                              Fld(1, 2) //[2:2]
+    #define LPIF_SEMA_0_SEMA_3_M0                              Fld(1, 3) //[3:3]
+    #define LPIF_SEMA_0_SEMA_4_M0                              Fld(1, 4) //[4:4]
+    #define LPIF_SEMA_0_SEMA_5_M0                              Fld(1, 5) //[5:5]
+    #define LPIF_SEMA_0_SEMA_6_M0                              Fld(1, 6) //[6:6]
+    #define LPIF_SEMA_0_SEMA_7_M0                              Fld(1, 7) //[7:7]
+    #define LPIF_SEMA_0_RESERVED_X80_31_8                      Fld(24, 8) //[31:8]
+
+#define DDRPHY_MD32_REG_LPIF_SEMA_1                            (DDRPHY_MD32_BASE_ADDRESS + 0x7084)
+    #define LPIF_SEMA_1_SEMA_0_M1                              Fld(1, 0) //[0:0]
+    #define LPIF_SEMA_1_SEMA_1_M1                              Fld(1, 1) //[1:1]
+    #define LPIF_SEMA_1_SEMA_2_M1                              Fld(1, 2) //[2:2]
+    #define LPIF_SEMA_1_SEMA_3_M1                              Fld(1, 3) //[3:3]
+    #define LPIF_SEMA_1_SEMA_4_M1                              Fld(1, 4) //[4:4]
+    #define LPIF_SEMA_1_SEMA_5_M1                              Fld(1, 5) //[5:5]
+    #define LPIF_SEMA_1_SEMA_6_M1                              Fld(1, 6) //[6:6]
+    #define LPIF_SEMA_1_SEMA_7_M1                              Fld(1, 7) //[7:7]
+    #define LPIF_SEMA_1_RESERVED_X84_31_8                      Fld(24, 8) //[31:8]
+
+#define DDRPHY_MD32_REG_LPIF_SEMA_2                            (DDRPHY_MD32_BASE_ADDRESS + 0x7088)
+    #define LPIF_SEMA_2_SEMA_0_M2                              Fld(1, 0) //[0:0]
+    #define LPIF_SEMA_2_SEMA_1_M2                              Fld(1, 1) //[1:1]
+    #define LPIF_SEMA_2_SEMA_2_M2                              Fld(1, 2) //[2:2]
+    #define LPIF_SEMA_2_SEMA_3_M2                              Fld(1, 3) //[3:3]
+    #define LPIF_SEMA_2_SEMA_4_M2                              Fld(1, 4) //[4:4]
+    #define LPIF_SEMA_2_SEMA_5_M2                              Fld(1, 5) //[5:5]
+    #define LPIF_SEMA_2_SEMA_6_M2                              Fld(1, 6) //[6:6]
+    #define LPIF_SEMA_2_SEMA_7_M2                              Fld(1, 7) //[7:7]
+    #define LPIF_SEMA_2_RESERVED_X88_31_8                      Fld(24, 8) //[31:8]
+
+#define DDRPHY_MD32_REG_LPIF_SEMA_3                            (DDRPHY_MD32_BASE_ADDRESS + 0x708C)
+    #define LPIF_SEMA_3_SEMA_0_M3                              Fld(1, 0) //[0:0]
+    #define LPIF_SEMA_3_SEMA_1_M3                              Fld(1, 1) //[1:1]
+    #define LPIF_SEMA_3_SEMA_2_M3                              Fld(1, 2) //[2:2]
+    #define LPIF_SEMA_3_SEMA_3_M3                              Fld(1, 3) //[3:3]
+    #define LPIF_SEMA_3_SEMA_4_M3                              Fld(1, 4) //[4:4]
+    #define LPIF_SEMA_3_SEMA_5_M3                              Fld(1, 5) //[5:5]
+    #define LPIF_SEMA_3_SEMA_6_M3                              Fld(1, 6) //[6:6]
+    #define LPIF_SEMA_3_SEMA_7_M3                              Fld(1, 7) //[7:7]
+    #define LPIF_SEMA_3_RESERVED_X8C_31_8                      Fld(24, 8) //[31:8]
+
+#define DDRPHY_MD32_REG_LPIF_RESERVED_16                       (DDRPHY_MD32_BASE_ADDRESS + 0x7090)
+    #define LPIF_RESERVED_16_DRAMC_DPM_BACKUP_FLAG             Fld(1, 0) //[0:0]
+    #define LPIF_RESERVED_16_RESERVED_X90_31_0                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_RESERVED_17                       (DDRPHY_MD32_BASE_ADDRESS + 0x7094)
+    #define LPIF_RESERVED_17_RESERVED_X94_31_0                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_RESERVED_18                       (DDRPHY_MD32_BASE_ADDRESS + 0x7098)
+    #define LPIF_RESERVED_18_RESERVED_X98_31_0                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DUMMY_REG                         (DDRPHY_MD32_BASE_ADDRESS + 0x709C)
+    #define LPIF_DUMMY_REG_DUMMY_REG                           Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_0                          (DDRPHY_MD32_BASE_ADDRESS + 0x70A0)
+    #define LPIF_STATUS_0_LPIF_DDR_PST                         Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_1                          (DDRPHY_MD32_BASE_ADDRESS + 0x70A4)
+    #define LPIF_STATUS_1_DDR_PST_REQ                          Fld(1, 0) //[0:0]
+    #define LPIF_STATUS_1_DDR_PST_ABORT_REQ                    Fld(1, 1) //[1:1]
+    #define LPIF_STATUS_1_DDR_PST_ABORT_REQ_LATCH              Fld(1, 2) //[2:2]
+    #define LPIF_STATUS_1_LPC_INTERNAL_COUNTER_ABORT_FLAG      Fld(1, 3) //[3:3]
+    #define LPIF_STATUS_1_RESERVED_XA4_31_4                    Fld(28, 4) //[31:4]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_2                          (DDRPHY_MD32_BASE_ADDRESS + 0x70A8)
+    #define LPIF_STATUS_2_DESTINATION_DDR_PST                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_3                          (DDRPHY_MD32_BASE_ADDRESS + 0x70AC)
+    #define LPIF_STATUS_3_CUR_DDR_PST_STA                      Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_4                          (DDRPHY_MD32_BASE_ADDRESS + 0x70B0)
+    #define LPIF_STATUS_4_EMI_CLK_OFF_REQ_ACK                  Fld(2, 0) //[1:0]
+    #define LPIF_STATUS_4_RESERVED_XB0_3_2                     Fld(2, 2) //[3:2]
+    #define LPIF_STATUS_4_DRAMC_DFS_STA                        Fld(4, 4) //[7:4]
+    #define LPIF_STATUS_4_DQSSOC_REQ                           Fld(2, 8) //[9:8]
+    #define LPIF_STATUS_4_RESERVED_XB0_11_10                   Fld(2, 10) //[11:10]
+    #define LPIF_STATUS_4_DR_SHORT_QUEUE_ACK                   Fld(2, 12) //[13:12]
+    #define LPIF_STATUS_4_DR_SHU_EN_ACK                        Fld(2, 14) //[15:14]
+    #define LPIF_STATUS_4_DR_SRAM_PLL_LOAD_ACK                 Fld(2, 16) //[17:16]
+    #define LPIF_STATUS_4_DR_SRAM_LOAD_ACK                     Fld(2, 18) //[19:18]
+    #define LPIF_STATUS_4_DR_SRAM_RESTORE_ACK                  Fld(2, 20) //[21:20]
+    #define LPIF_STATUS_4_TX_TRACKING_DIS_ACK                  Fld(2, 22) //[23:22]
+    #define LPIF_STATUS_4_RESERVED_XB0_27_24                   Fld(4, 24) //[27:24]
+    #define LPIF_STATUS_4_DDR_PST_ACK                          Fld(1, 28) //[28:28]
+    #define LPIF_STATUS_4_DDR_PST_ABORT_ACK                    Fld(1, 29) //[29:29]
+    #define LPIF_STATUS_4_RESERVED_XB0_31_30                   Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_5                          (DDRPHY_MD32_BASE_ADDRESS + 0x70B4)
+    #define LPIF_STATUS_5_DDR_PST_STA_D0                       Fld(6, 0) //[5:0]
+    #define LPIF_STATUS_5_DDR_PST_ACK_D0                       Fld(1, 6) //[6:6]
+    #define LPIF_STATUS_5_DDR_PST_ABORT_ACK_D0                 Fld(1, 7) //[7:7]
+    #define LPIF_STATUS_5_DDR_PST_STA_D1                       Fld(6, 8) //[13:8]
+    #define LPIF_STATUS_5_DDR_PST_ACK_D1                       Fld(1, 14) //[14:14]
+    #define LPIF_STATUS_5_DDR_PST_ABORT_ACK_D1                 Fld(1, 15) //[15:15]
+    #define LPIF_STATUS_5_DDR_PST_STA_D2                       Fld(6, 16) //[21:16]
+    #define LPIF_STATUS_5_DDR_PST_ACK_D2                       Fld(1, 22) //[22:22]
+    #define LPIF_STATUS_5_DDR_PST_ABORT_ACK_D2                 Fld(1, 23) //[23:23]
+    #define LPIF_STATUS_5_DDR_PST_STA_D3                       Fld(6, 24) //[29:24]
+    #define LPIF_STATUS_5_DDR_PST_ACK_D3                       Fld(1, 30) //[30:30]
+    #define LPIF_STATUS_5_DDR_PST_ABORT_ACK_D3                 Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_6                          (DDRPHY_MD32_BASE_ADDRESS + 0x70B8)
+    #define LPIF_STATUS_6_DDR_PST_STA_D4                       Fld(6, 0) //[5:0]
+    #define LPIF_STATUS_6_DDR_PST_ACK_D4                       Fld(1, 6) //[6:6]
+    #define LPIF_STATUS_6_DDR_PST_ABORT_ACK_D4                 Fld(1, 7) //[7:7]
+    #define LPIF_STATUS_6_DDR_PST_STA_D5                       Fld(6, 8) //[13:8]
+    #define LPIF_STATUS_6_DDR_PST_ACK_D5                       Fld(1, 14) //[14:14]
+    #define LPIF_STATUS_6_DDR_PST_ABORT_ACK_D5                 Fld(1, 15) //[15:15]
+    #define LPIF_STATUS_6_DDR_PST_STA_D6                       Fld(6, 16) //[21:16]
+    #define LPIF_STATUS_6_DDR_PST_ACK_D6                       Fld(1, 22) //[22:22]
+    #define LPIF_STATUS_6_DDR_PST_ABORT_ACK_D6                 Fld(1, 23) //[23:23]
+    #define LPIF_STATUS_6_DDR_PST_STA_D7                       Fld(6, 24) //[29:24]
+    #define LPIF_STATUS_6_DDR_PST_ACK_D7                       Fld(1, 30) //[30:30]
+    #define LPIF_STATUS_6_DDR_PST_ABORT_ACK_D7                 Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_7                          (DDRPHY_MD32_BASE_ADDRESS + 0x70BC)
+    #define LPIF_STATUS_7_DDR_PST_STA_D8                       Fld(6, 0) //[5:0]
+    #define LPIF_STATUS_7_DDR_PST_ACK_D8                       Fld(1, 6) //[6:6]
+    #define LPIF_STATUS_7_DDR_PST_ABORT_ACK_D8                 Fld(1, 7) //[7:7]
+    #define LPIF_STATUS_7_DDR_PST_STA_D9                       Fld(6, 8) //[13:8]
+    #define LPIF_STATUS_7_DDR_PST_ACK_D9                       Fld(1, 14) //[14:14]
+    #define LPIF_STATUS_7_DDR_PST_ABORT_ACK_D9                 Fld(1, 15) //[15:15]
+    #define LPIF_STATUS_7_DDR_PST_STA_DA                       Fld(6, 16) //[21:16]
+    #define LPIF_STATUS_7_DDR_PST_ACK_DA                       Fld(1, 22) //[22:22]
+    #define LPIF_STATUS_7_DDR_PST_ABORT_ACK_DA                 Fld(1, 23) //[23:23]
+    #define LPIF_STATUS_7_DDR_PST_STA_DB                       Fld(6, 24) //[29:24]
+    #define LPIF_STATUS_7_DDR_PST_ACK_DB                       Fld(1, 30) //[30:30]
+    #define LPIF_STATUS_7_DDR_PST_ABORT_ACK_DB                 Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_8                          (DDRPHY_MD32_BASE_ADDRESS + 0x70C0)
+    #define LPIF_STATUS_8_DDR_PST_STA_DC                       Fld(6, 0) //[5:0]
+    #define LPIF_STATUS_8_DDR_PST_ACK_DC                       Fld(1, 6) //[6:6]
+    #define LPIF_STATUS_8_DDR_PST_ABORT_ACK_DC                 Fld(1, 7) //[7:7]
+    #define LPIF_STATUS_8_DDR_PST_STA_DD                       Fld(6, 8) //[13:8]
+    #define LPIF_STATUS_8_DDR_PST_ACK_DD                       Fld(1, 14) //[14:14]
+    #define LPIF_STATUS_8_DDR_PST_ABORT_ACK_DD                 Fld(1, 15) //[15:15]
+    #define LPIF_STATUS_8_DDR_PST_STA_DE                       Fld(6, 16) //[21:16]
+    #define LPIF_STATUS_8_DDR_PST_ACK_DE                       Fld(1, 22) //[22:22]
+    #define LPIF_STATUS_8_DDR_PST_ABORT_ACK_DE                 Fld(1, 23) //[23:23]
+    #define LPIF_STATUS_8_DDR_PST_STA_DF                       Fld(6, 24) //[29:24]
+    #define LPIF_STATUS_8_DDR_PST_ACK_DF                       Fld(1, 30) //[30:30]
+    #define LPIF_STATUS_8_DDR_PST_ABORT_ACK_DF                 Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_9                          (DDRPHY_MD32_BASE_ADDRESS + 0x70C4)
+    #define LPIF_STATUS_9_DRAMC_DMSUS_OFF                      Fld(2, 0) //[1:0]
+    #define LPIF_STATUS_9_DRAMC_PHYPLL_EN                      Fld(2, 2) //[3:2]
+    #define LPIF_STATUS_9_DRAMC_DPY_DLL_EN                     Fld(2, 4) //[5:4]
+    #define LPIF_STATUS_9_DRAMC_DPY_2ND_DLL_EN                 Fld(2, 6) //[7:6]
+    #define LPIF_STATUS_9_DRAMC_DPY_DLL_CK_EN                  Fld(2, 8) //[9:8]
+    #define LPIF_STATUS_9_DRAMC_DPY_VREF_EN                    Fld(2, 10) //[11:10]
+    #define LPIF_STATUS_9_DRAMC_EMI_CLK_OFF_REQ                Fld(2, 12) //[13:12]
+    #define LPIF_STATUS_9_DRAMC_MEM_CK_OFF                     Fld(2, 14) //[15:14]
+    #define LPIF_STATUS_9_DRAMC_DDRPHY_FB_CK_EN                Fld(2, 16) //[17:16]
+    #define LPIF_STATUS_9_DRAMC_DR_GATE_RETRY_EN               Fld(2, 18) //[19:18]
+    #define LPIF_STATUS_9_DRAMC_PHYPLL_SHU_EN                  Fld(2, 20) //[21:20]
+    #define LPIF_STATUS_9_DRAMC_PHYPLL_MODE_SW                 Fld(2, 22) //[23:22]
+    #define LPIF_STATUS_9_DRAMC_PHYPLL2_SHU_EN                 Fld(2, 24) //[25:24]
+    #define LPIF_STATUS_9_DRAMC_PHYPLL2_MODE_SW                Fld(2, 26) //[27:26]
+    #define LPIF_STATUS_9_DRAMC_DR_SHU_EN                      Fld(2, 28) //[29:28]
+    #define LPIF_STATUS_9_DRAMC_DR_SHORT_QUEUE                 Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_10                         (DDRPHY_MD32_BASE_ADDRESS + 0x70C8)
+    #define LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL                  Fld(4, 0) //[3:0]
+    #define LPIF_STATUS_10_DRAMC_DPY_BCLK_ENABLE               Fld(2, 4) //[5:4]
+    #define LPIF_STATUS_10_DRAMC_SHU_RESTORE                   Fld(2, 6) //[7:6]
+    #define LPIF_STATUS_10_DRAMC_DPHY_PRECAL_UP                Fld(2, 8) //[9:8]
+    #define LPIF_STATUS_10_DRAMC_DPHY_RXDLY_TRACK_EN           Fld(2, 10) //[11:10]
+    #define LPIF_STATUS_10_DRAMC_DMY_EN_MOD_SEL                Fld(2, 12) //[13:12]
+    #define LPIF_STATUS_10_DRAMC_DMYRD_INTV_SEL                Fld(2, 14) //[15:14]
+    #define LPIF_STATUS_10_DRAMC_DMYRD_EN                      Fld(2, 16) //[17:16]
+    #define LPIF_STATUS_10_DRAMC_TX_TRACKING_DIS               Fld(2, 18) //[19:18]
+    #define LPIF_STATUS_10_DRAMC_TX_TRACKING_RETRY_EN          Fld(2, 20) //[21:20]
+    #define LPIF_STATUS_10_DRAMC_DR_SHU_SRAM_LEVEL             Fld(8, 22) //[29:22]
+    #define LPIF_STATUS_10_DRAMC_DR_SRAM_LOAD                  Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_11                         (DDRPHY_MD32_BASE_ADDRESS + 0x70CC)
+    #define LPIF_STATUS_11_DRAMC_DR_SRAM_RESTORE               Fld(2, 0) //[1:0]
+    #define LPIF_STATUS_11_DRAMC_DR_SHU_LEVEL_SRAM_LATCH       Fld(2, 2) //[3:2]
+    #define LPIF_STATUS_11_DRAMC_DPY_MODE_SW                   Fld(2, 4) //[5:4]
+    #define LPIF_STATUS_11_RESERVED_XCC_7_6                    Fld(2, 6) //[7:6]
+    #define LPIF_STATUS_11_DRAMC_DPY_RESERVED                  Fld(8, 8) //[15:8]
+    #define LPIF_STATUS_11_DRAMC_DRAMC_DFS_CON                 Fld(13, 16) //[28:16]
+    #define LPIF_STATUS_11_RESERVED_XCC_31_27                  Fld(3, 29) //[31:29]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_12                         (DDRPHY_MD32_BASE_ADDRESS + 0x70D0)
+    #define LPIF_STATUS_12_FSM_TIME_OUT_FLAG                   Fld(1, 0) //[0:0]
+    #define LPIF_STATUS_12_EXP_FSM_JUMP                        Fld(1, 1) //[1:1]
+    #define LPIF_STATUS_12_IRQ_LPIF_LOW_POWER                  Fld(1, 2) //[2:2]
+    #define LPIF_STATUS_12_IRQ_LPIF_OTHERS_STATE               Fld(1, 3) //[3:3]
+    #define LPIF_STATUS_12_DFS_STATUS_RECORD                   Fld(4, 4) //[7:4]
+    #define LPIF_STATUS_12_DVS_STATUS_RECORD                   Fld(1, 8) //[8:8]
+    #define LPIF_STATUS_12_RUNTIME_STATUS_RECORD               Fld(1, 9) //[9:9]
+    #define LPIF_STATUS_12_RESERVED_XD0_11_10                  Fld(2, 10) //[11:10]
+    #define LPIF_STATUS_12_MUX_LPIF_DPHY_RXDLY_TRACK_EN        Fld(1, 12) //[12:12]
+    #define LPIF_STATUS_12_MUX_LPIF_DMYRD_EN                   Fld(1, 13) //[13:13]
+    #define LPIF_STATUS_12_MUX_LPIF_TX_TRACKING_DIS            Fld(1, 14) //[14:14]
+    #define LPIF_STATUS_12_MUX_LPIF_DR_SRAM_RESTORE            Fld(1, 15) //[15:15]
+    #define LPIF_STATUS_12_MUX_LPIF_TX_TRACK_RETRY_EN          Fld(1, 16) //[16:16]
+    #define LPIF_STATUS_12_MUX_LPIF_RX_GATING_RETRY_EN         Fld(1, 17) //[17:17]
+    #define LPIF_STATUS_12_MUX_LPIF_DLL_ALL_SLAVE_EN           Fld(1, 18) //[18:18]
+    #define LPIF_STATUS_12_MUX_LPIF_IMPEDANCE_TRACKING_EN      Fld(1, 19) //[19:19]
+    #define LPIF_STATUS_12_MUX_LPIF_DPHY_RXDLY_TRACK_EN_PREV   Fld(1, 20) //[20:20]
+    #define LPIF_STATUS_12_MUX_LPIF_DMYRD_EN_PREV              Fld(1, 21) //[21:21]
+    #define LPIF_STATUS_12_MUX_LPIF_TX_TRACKING_DIS_PREV       Fld(1, 22) //[22:22]
+    #define LPIF_STATUS_12_MUX_LPIF_DR_SRAM_RESTORE_PREV       Fld(1, 23) //[23:23]
+    #define LPIF_STATUS_12_MUX_LPIF_TX_TRACK_RETRY_EN_PREV     Fld(1, 24) //[24:24]
+    #define LPIF_STATUS_12_MUX_LPIF_RX_GATING_RETRY_EN_PREV    Fld(1, 25) //[25:25]
+    #define LPIF_STATUS_12_MUX_LPIF_DLL_ALL_SLAVE_EN_PREV      Fld(1, 26) //[26:26]
+    #define LPIF_STATUS_12_MUX_LPIF_IMPEDANCE_TRACKING_EN_PREV Fld(1, 27) //[27:27]
+    #define LPIF_STATUS_12_SHU_INDEX                           Fld(1, 28) //[28:28]
+    #define LPIF_STATUS_12_RESERVED_XD0_31_29                  Fld(3, 29) //[31:29]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_13                         (DDRPHY_MD32_BASE_ADDRESS + 0x70D4)
+    #define LPIF_STATUS_13_COUNTER_TIME_OUT_FLAG               Fld(1, 0) //[0:0]
+    #define LPIF_STATUS_13_COUNTER_20US_DONE                   Fld(1, 1) //[1:1]
+    #define LPIF_STATUS_13_COUNTER_12US_DONE                   Fld(1, 2) //[2:2]
+    #define LPIF_STATUS_13_COUNTER_DLL_1ST_LOCKING_DONE        Fld(1, 3) //[3:3]
+    #define LPIF_STATUS_13_COUNTER_DLL_2ND_LOCKING_DONE        Fld(1, 4) //[4:4]
+    #define LPIF_STATUS_13_COUNTER_CK_OFF_TO_DMSUS_DONE        Fld(1, 5) //[5:5]
+    #define LPIF_STATUS_13_COUNTER_50NS_DONE                   Fld(1, 6) //[6:6]
+    #define LPIF_STATUS_13_COUNTER_4US_DONE                    Fld(1, 7) //[7:7]
+    #define LPIF_STATUS_13_LPIF_FSM                            Fld(10, 8) //[17:8]
+    #define LPIF_STATUS_13_COUNTER_SR_DEBON_DONE               Fld(2, 18) //[19:18]
+    #define LPIF_STATUS_13_COUNTER_SR_MIN_PLS_DEBON_DONE       Fld(2, 20) //[21:20]
+    #define LPIF_STATUS_13_HW_S1_STEP_COUNTER_DONE             Fld(1, 22) //[22:22]
+    #define LPIF_STATUS_13_COUNTER_256MCK_DONE                 Fld(1, 23) //[23:23]
+    #define LPIF_STATUS_13_MUX_LPIF_DRAM_PAR_CLOCK_MODE        Fld(2, 24) //[25:24]
+    #define LPIF_STATUS_13_MUX_LPIF_DRAM_PAR_CLOCK_MODE_PREV   Fld(2, 26) //[27:26]
+    #define LPIF_STATUS_13_RESERVED_XD4_31_28                  Fld(4, 28) //[31:28]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_14                         (DDRPHY_MD32_BASE_ADDRESS + 0x70D8)
+    #define LPIF_STATUS_14_DRAMC_DPY_MCK8X_EN                  Fld(2, 0) //[1:0]
+    #define LPIF_STATUS_14_DRAMC_DPY_MIDPI_EN                  Fld(2, 2) //[3:2]
+    #define LPIF_STATUS_14_DRAMC_DPY_PI_RESETB_EN              Fld(2, 4) //[5:4]
+    #define LPIF_STATUS_14_DRAMC_DVFS_MEM_CK_MUX_UPDATE        Fld(2, 6) //[7:6]
+    #define LPIF_STATUS_14_DRAMC_DVFS_MEM_CK_MUX_SEL           Fld(4, 8) //[11:8]
+    #define LPIF_STATUS_14_DRAMC_DPY_DSM_EN                    Fld(2, 12) //[13:12]
+    #define LPIF_STATUS_14_DRAMC_DPY_FASTK_RDDQS_EN            Fld(2, 14) //[15:14]
+    #define LPIF_STATUS_14_DRAMC_DPY_CS_PULL_UP_EN             Fld(2, 16) //[17:16]
+    #define LPIF_STATUS_14_DRAMC_DPY_CS_PULL_DN_EN             Fld(2, 18) //[19:18]
+    #define LPIF_STATUS_14_DRAMC_DPY_CA_PULL_UP_EN             Fld(2, 20) //[21:20]
+    #define LPIF_STATUS_14_DRAMC_DPY_CA_PULL_DN_EN             Fld(2, 22) //[23:22]
+    #define LPIF_STATUS_14_DRAMC_FHC_PAUSE_MEM                 Fld(1, 24) //[24:24]
+    #define LPIF_STATUS_14_DRAMC_FHC_PAUSE_MPLL                Fld(1, 25) //[25:25]
+    #define LPIF_STATUS_14_DRAMC_MPLL_S_OFF                    Fld(1, 26) //[26:26]
+    #define LPIF_STATUS_14_DRAMC_MPLLOUT_OFF                   Fld(1, 27) //[27:27]
+    #define LPIF_STATUS_14_DRAMC_EMI_S1_MODE_ASYNC             Fld(1, 28) //[28:28]
+    #define LPIF_STATUS_14_RESERVED_XD8_29_29                  Fld(1, 29) //[29:29]
+    #define LPIF_STATUS_14_DRAMC_DPY_PICG_FREE                 Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_RESERVED_20                       (DDRPHY_MD32_BASE_ADDRESS + 0x70DC)
+    #define LPIF_RESERVED_20_RESERVED_XDC_31_0                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_15                         (DDRPHY_MD32_BASE_ADDRESS + 0x70E0)
+    #define LPIF_STATUS_15_DRAMC_PWR_RST_B                     Fld(2, 0) //[1:0]
+    #define LPIF_STATUS_15_DRAMC_PWR_ISO                       Fld(2, 2) //[3:2]
+    #define LPIF_STATUS_15_DRAMC_PWR_ON                        Fld(2, 4) //[5:4]
+    #define LPIF_STATUS_15_DRAMC_PWR_ON_2ND                    Fld(2, 6) //[7:6]
+    #define LPIF_STATUS_15_DRAMC_PWR_CLK_DIS                   Fld(2, 8) //[9:8]
+    #define LPIF_STATUS_15_DRAMC_MPLL_OFF                      Fld(1, 12) //[12:12]
+    #define LPIF_STATUS_15_DRAMC_PWR_SRAM_PDN                  Fld(4, 16) //[19:16]
+    #define LPIF_STATUS_15_DRAMC_PWR_SC_SRAM_PDN_ACK           Fld(1, 20) //[20:20]
+    #define LPIF_STATUS_15_DRAMC_SHU_SRAM_SLEEP_B              Fld(2, 24) //[25:24]
+    #define LPIF_STATUS_15_DRAMC_SHU_SRAM_CKISO                Fld(2, 26) //[27:26]
+    #define LPIF_STATUS_15_DRAMC_SHU_SRAM_ISOINT_B             Fld(2, 28) //[29:28]
+    #define LPIF_STATUS_15_DRAMC_SHU_SRAM_PDN                  Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_16                         (DDRPHY_MD32_BASE_ADDRESS + 0x70E4)
+    #define LPIF_STATUS_16_SC_PWR_RST_B                        Fld(2, 0) //[1:0]
+    #define LPIF_STATUS_16_SC_PWR_ISO                          Fld(2, 2) //[3:2]
+    #define LPIF_STATUS_16_SC_PWR_ON                           Fld(2, 4) //[5:4]
+    #define LPIF_STATUS_16_SC_PWR_ON_2ND                       Fld(2, 6) //[7:6]
+    #define LPIF_STATUS_16_SC_PWR_CLK_DIS                      Fld(2, 8) //[9:8]
+    #define LPIF_STATUS_16_RESERVED_XE4_11_10                  Fld(2, 10) //[11:10]
+    #define LPIF_STATUS_16_SC_MPLL_OFF                         Fld(1, 12) //[12:12]
+    #define LPIF_STATUS_16_RESERVED_XE4_15_13                  Fld(3, 13) //[15:13]
+    #define LPIF_STATUS_16_SC_PWR_SRAM_PDN                     Fld(4, 16) //[19:16]
+    #define LPIF_STATUS_16_RESERVED_XE4_23_20                  Fld(4, 20) //[23:20]
+    #define LPIF_STATUS_16_SC_SHU_SRAM_SLEEP_B                 Fld(2, 24) //[25:24]
+    #define LPIF_STATUS_16_RESERVED_XE4_26_26                  Fld(1, 26) //[26:26]
+    #define LPIF_STATUS_16_SC_SHU_SRAM_CKISO                   Fld(1, 27) //[27:27]
+    #define LPIF_STATUS_16_RESERVED_XE4_28_28                  Fld(1, 28) //[28:28]
+    #define LPIF_STATUS_16_SC_SHU_SRAM_ISOINT_B                Fld(1, 29) //[29:29]
+    #define LPIF_STATUS_16_SC_SHU_SRAM_PDN                     Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_17                         (DDRPHY_MD32_BASE_ADDRESS + 0x70E8)
+    #define LPIF_STATUS_17_LPIF_PWR_RST_B                      Fld(2, 0) //[1:0]
+    #define LPIF_STATUS_17_LPIF_PWR_ISO                        Fld(2, 2) //[3:2]
+    #define LPIF_STATUS_17_LPIF_PWR_ON                         Fld(2, 4) //[5:4]
+    #define LPIF_STATUS_17_LPIF_PWR_ON_2ND                     Fld(2, 6) //[7:6]
+    #define LPIF_STATUS_17_LPIF_PWR_CLK_DIS                    Fld(2, 8) //[9:8]
+    #define LPIF_STATUS_17_LPIF_MPLL_OFF                       Fld(1, 12) //[12:12]
+    #define LPIF_STATUS_17_LPIF_PWR_SRAM_PDN                   Fld(8, 16) //[23:16]
+    #define LPIF_STATUS_17_LPIF_SHU_SRAM_SLEEP_B               Fld(2, 24) //[25:24]
+    #define LPIF_STATUS_17_LPIF_SHU_SRAM_CKISO                 Fld(2, 26) //[27:26]
+    #define LPIF_STATUS_17_LPIF_SHU_SRAM_ISOINT_B              Fld(2, 28) //[29:28]
+    #define LPIF_STATUS_17_LPIF_SHU_SRAM_PDN                   Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_18                         (DDRPHY_MD32_BASE_ADDRESS + 0x70EC)
+    #define LPIF_STATUS_18_DRAMC_LPIF_COM                      Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_STATUS_19                         (DDRPHY_MD32_BASE_ADDRESS + 0x70F0)
+    #define LPIF_STATUS_19_DRAMC_LPIF_STA                      Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_MISC_CTL_0                        (DDRPHY_MD32_BASE_ADDRESS + 0x70F4)
+    #define LPIF_MISC_CTL_0_EMI_SLEEP_IDLE                     Fld(1, 0) //[0:0]
+
+#define DDRPHY_MD32_REG_LPIF_MISC_CTL_1                        (DDRPHY_MD32_BASE_ADDRESS + 0x70F8)
+    #define LPIF_MISC_CTL_1_PWR_RST_B                          Fld(2, 0) //[1:0]
+    #define LPIF_MISC_CTL_1_PWR_ISO                            Fld(2, 2) //[3:2]
+    #define LPIF_MISC_CTL_1_PWR_ON                             Fld(2, 4) //[5:4]
+    #define LPIF_MISC_CTL_1_PWR_ON_2ND                         Fld(2, 6) //[7:6]
+    #define LPIF_MISC_CTL_1_PWR_CLK_DIS                        Fld(2, 8) //[9:8]
+    #define LPIF_MISC_CTL_1_MPLL_OFF                           Fld(1, 12) //[12:12]
+    #define LPIF_MISC_CTL_1_PWR_SRAM_PDN                       Fld(8, 16) //[23:16]
+    #define LPIF_MISC_CTL_1_SHU_SRAM_SLEEP_B                   Fld(2, 24) //[25:24]
+    #define LPIF_MISC_CTL_1_SHU_SRAM_CKISO                     Fld(2, 26) //[27:26]
+    #define LPIF_MISC_CTL_1_SHU_SRAM_ISOINT_B                  Fld(2, 28) //[29:28]
+    #define LPIF_MISC_CTL_1_SHU_SRAM_PDN                       Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_MISC_STATUS_0                     (DDRPHY_MD32_BASE_ADDRESS + 0x70FC)
+    #define LPIF_MISC_STATUS_0_PWR_ON_ACK                      Fld(2, 0) //[1:0]
+    #define LPIF_MISC_STATUS_0_PWR_ON_2ND_ACK                  Fld(2, 2) //[3:2]
+    #define LPIF_MISC_STATUS_0_SRAM_PDN_ACK                    Fld(4, 8) //[11:8]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_0                        (DDRPHY_MD32_BASE_ADDRESS + 0x7100)
+    #define LPIF_DVFS_CMD_0_DVFS_CMD0                          Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_1                        (DDRPHY_MD32_BASE_ADDRESS + 0x7104)
+    #define LPIF_DVFS_CMD_1_DVFS_CMD1                          Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_2                        (DDRPHY_MD32_BASE_ADDRESS + 0x7108)
+    #define LPIF_DVFS_CMD_2_DVFS_CMD2                          Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_3                        (DDRPHY_MD32_BASE_ADDRESS + 0x710C)
+    #define LPIF_DVFS_CMD_3_DVFS_CMD3                          Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_4                        (DDRPHY_MD32_BASE_ADDRESS + 0x7110)
+    #define LPIF_DVFS_CMD_4_DVFS_CMD4                          Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_5                        (DDRPHY_MD32_BASE_ADDRESS + 0x7114)
+    #define LPIF_DVFS_CMD_5_DVFS_CMD5                          Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_6                        (DDRPHY_MD32_BASE_ADDRESS + 0x7118)
+    #define LPIF_DVFS_CMD_6_DVFS_CMD6                          Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_7                        (DDRPHY_MD32_BASE_ADDRESS + 0x711C)
+    #define LPIF_DVFS_CMD_7_DVFS_CMD7                          Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_8                        (DDRPHY_MD32_BASE_ADDRESS + 0x7120)
+    #define LPIF_DVFS_CMD_8_DVFS_CMD8                          Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_9                        (DDRPHY_MD32_BASE_ADDRESS + 0x7124)
+    #define LPIF_DVFS_CMD_9_DVFS_CMD9                          Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_10                       (DDRPHY_MD32_BASE_ADDRESS + 0x7128)
+    #define LPIF_DVFS_CMD_10_DVFS_CMD10                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_11                       (DDRPHY_MD32_BASE_ADDRESS + 0x712C)
+    #define LPIF_DVFS_CMD_11_DVFS_CMD11                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_12                       (DDRPHY_MD32_BASE_ADDRESS + 0x7130)
+    #define LPIF_DVFS_CMD_12_DVFS_CMD12                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_13                       (DDRPHY_MD32_BASE_ADDRESS + 0x7134)
+    #define LPIF_DVFS_CMD_13_DVFS_CMD13                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_14                       (DDRPHY_MD32_BASE_ADDRESS + 0x7138)
+    #define LPIF_DVFS_CMD_14_DVFS_CMD14                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_15                       (DDRPHY_MD32_BASE_ADDRESS + 0x713C)
+    #define LPIF_DVFS_CMD_15_DVFS_CMD15                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_16                       (DDRPHY_MD32_BASE_ADDRESS + 0x7140)
+    #define LPIF_DVFS_CMD_16_DVFS_CMD16                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_17                       (DDRPHY_MD32_BASE_ADDRESS + 0x7144)
+    #define LPIF_DVFS_CMD_17_DVFS_CMD17                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_18                       (DDRPHY_MD32_BASE_ADDRESS + 0x7148)
+    #define LPIF_DVFS_CMD_18_DVFS_CMD18                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_19                       (DDRPHY_MD32_BASE_ADDRESS + 0x714C)
+    #define LPIF_DVFS_CMD_19_DVFS_CMD19                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_20                       (DDRPHY_MD32_BASE_ADDRESS + 0x7150)
+    #define LPIF_DVFS_CMD_20_DVFS_CMD20                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_21                       (DDRPHY_MD32_BASE_ADDRESS + 0x7154)
+    #define LPIF_DVFS_CMD_21_DVFS_CMD21                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_22                       (DDRPHY_MD32_BASE_ADDRESS + 0x7158)
+    #define LPIF_DVFS_CMD_22_DVFS_CMD22                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_23                       (DDRPHY_MD32_BASE_ADDRESS + 0x715C)
+    #define LPIF_DVFS_CMD_23_DVFS_CMD23                        Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_CONFIG                       (DDRPHY_MD32_BASE_ADDRESS + 0x7160)
+    #define LPIF_DVFS_CONFIG_DVFS_CON                          Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_STATUS_0                     (DDRPHY_MD32_BASE_ADDRESS + 0x7164)
+    #define LPIF_DVFS_STATUS_0_DVFS_CMD_ACK                    Fld(1, 0) //[0:0]
+    #define LPIF_DVFS_STATUS_0_DVFS_CMD_REQ                    Fld(1, 1) //[1:1]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_STATUS_1                     (DDRPHY_MD32_BASE_ADDRESS + 0x7168)
+    #define LPIF_DVFS_STATUS_1_DVFS_CMD_DAT                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DVFS_STATUS_2                     (DDRPHY_MD32_BASE_ADDRESS + 0x716C)
+    #define LPIF_DVFS_STATUS_2_DVFS_CON_STA                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_RESERVED_170                      (DDRPHY_MD32_BASE_ADDRESS + 0x7170)
+    #define LPIF_RESERVED_170_RESERVED_X170_31_0               Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_RESERVED_174                      (DDRPHY_MD32_BASE_ADDRESS + 0x7174)
+    #define LPIF_RESERVED_174_RESERVED_X174_31_0               Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_RESERVED_178                      (DDRPHY_MD32_BASE_ADDRESS + 0x7178)
+    #define LPIF_RESERVED_178_RESERVED_X178_31_0               Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_RESERVED_17C                      (DDRPHY_MD32_BASE_ADDRESS + 0x717C)
+    #define LPIF_RESERVED_17C_RESERVED_X17C_31_0               Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0               (DDRPHY_MD32_BASE_ADDRESS + 0x7180)
+    #define LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_0         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_1         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_2         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_3         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1               (DDRPHY_MD32_BASE_ADDRESS + 0x7184)
+    #define LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_4         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_5         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_6         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_7         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2               (DDRPHY_MD32_BASE_ADDRESS + 0x7188)
+    #define LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_8         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_9         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_10        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_11        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_3               (DDRPHY_MD32_BASE_ADDRESS + 0x718C)
+    #define LPIF_MR_OP_STORE_SHU_0_3_MR_OP_SET_SHU_0_12        Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_0_3_MR_OP_SET_SHU_0_13        Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_0_3_MR_OP_SET_SHU_0_14        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_0_3_MR_OP_SET_SHU_0_15        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_1_0               (DDRPHY_MD32_BASE_ADDRESS + 0x7190)
+    #define LPIF_MR_OP_STORE_SHU_1_0_MR_OP_SET_SHU_1_0         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_1_0_MR_OP_SET_SHU_1_1         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_1_0_MR_OP_SET_SHU_1_2         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_1_0_MR_OP_SET_SHU_1_3         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_1_1               (DDRPHY_MD32_BASE_ADDRESS + 0x7194)
+    #define LPIF_MR_OP_STORE_SHU_1_1_MR_OP_SET_SHU_1_4         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_1_1_MR_OP_SET_SHU_1_5         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_1_1_MR_OP_SET_SHU_1_6         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_1_1_MR_OP_SET_SHU_1_7         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_1_2               (DDRPHY_MD32_BASE_ADDRESS + 0x7198)
+    #define LPIF_MR_OP_STORE_SHU_1_2_MR_OP_SET_SHU_1_8         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_1_2_MR_OP_SET_SHU_1_9         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_1_2_MR_OP_SET_SHU_1_10        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_1_2_MR_OP_SET_SHU_1_11        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_1_3               (DDRPHY_MD32_BASE_ADDRESS + 0x719C)
+    #define LPIF_MR_OP_STORE_SHU_1_3_MR_OP_SET_SHU_1_12        Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_1_3_MR_OP_SET_SHU_1_13        Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_1_3_MR_OP_SET_SHU_1_14        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_1_3_MR_OP_SET_SHU_1_15        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_2_0               (DDRPHY_MD32_BASE_ADDRESS + 0x71A0)
+    #define LPIF_MR_OP_STORE_SHU_2_0_MR_OP_SET_SHU_2_0         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_2_0_MR_OP_SET_SHU_2_1         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_2_0_MR_OP_SET_SHU_2_2         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_2_0_MR_OP_SET_SHU_2_3         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_2_1               (DDRPHY_MD32_BASE_ADDRESS + 0x71A4)
+    #define LPIF_MR_OP_STORE_SHU_2_1_MR_OP_SET_SHU_2_4         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_2_1_MR_OP_SET_SHU_2_5         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_2_1_MR_OP_SET_SHU_2_6         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_2_1_MR_OP_SET_SHU_2_7         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_2_2               (DDRPHY_MD32_BASE_ADDRESS + 0x71A8)
+    #define LPIF_MR_OP_STORE_SHU_2_2_MR_OP_SET_SHU_2_8         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_2_2_MR_OP_SET_SHU_2_9         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_2_2_MR_OP_SET_SHU_2_10        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_2_2_MR_OP_SET_SHU_2_11        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_2_3               (DDRPHY_MD32_BASE_ADDRESS + 0x71AC)
+    #define LPIF_MR_OP_STORE_SHU_2_3_MR_OP_SET_SHU_2_12        Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_2_3_MR_OP_SET_SHU_2_13        Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_2_3_MR_OP_SET_SHU_2_14        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_2_3_MR_OP_SET_SHU_2_15        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_3_0               (DDRPHY_MD32_BASE_ADDRESS + 0x71B0)
+    #define LPIF_MR_OP_STORE_SHU_3_0_MR_OP_SET_SHU_3_0         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_3_0_MR_OP_SET_SHU_3_1         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_3_0_MR_OP_SET_SHU_3_2         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_3_0_MR_OP_SET_SHU_3_3         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_3_1               (DDRPHY_MD32_BASE_ADDRESS + 0x71B4)
+    #define LPIF_MR_OP_STORE_SHU_3_1_MR_OP_SET_SHU_3_4         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_3_1_MR_OP_SET_SHU_3_5         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_3_1_MR_OP_SET_SHU_3_6         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_3_1_MR_OP_SET_SHU_3_7         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_3_2               (DDRPHY_MD32_BASE_ADDRESS + 0x71B8)
+    #define LPIF_MR_OP_STORE_SHU_3_2_MR_OP_SET_SHU_3_8         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_3_2_MR_OP_SET_SHU_3_9         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_3_2_MR_OP_SET_SHU_3_10        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_3_2_MR_OP_SET_SHU_3_11        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_3_3               (DDRPHY_MD32_BASE_ADDRESS + 0x71BC)
+    #define LPIF_MR_OP_STORE_SHU_3_3_MR_OP_SET_SHU_3_12        Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_3_3_MR_OP_SET_SHU_3_13        Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_3_3_MR_OP_SET_SHU_3_14        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_3_3_MR_OP_SET_SHU_3_15        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_4_0               (DDRPHY_MD32_BASE_ADDRESS + 0x71C0)
+    #define LPIF_MR_OP_STORE_SHU_4_0_MR_OP_SET_SHU_4_0         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_4_0_MR_OP_SET_SHU_4_1         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_4_0_MR_OP_SET_SHU_4_2         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_4_0_MR_OP_SET_SHU_4_3         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_4_1               (DDRPHY_MD32_BASE_ADDRESS + 0x71C4)
+    #define LPIF_MR_OP_STORE_SHU_4_1_MR_OP_SET_SHU_4_4         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_4_1_MR_OP_SET_SHU_4_5         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_4_1_MR_OP_SET_SHU_4_6         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_4_1_MR_OP_SET_SHU_4_7         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_4_2               (DDRPHY_MD32_BASE_ADDRESS + 0x71C8)
+    #define LPIF_MR_OP_STORE_SHU_4_2_MR_OP_SET_SHU_4_8         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_4_2_MR_OP_SET_SHU_4_9         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_4_2_MR_OP_SET_SHU_4_10        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_4_2_MR_OP_SET_SHU_4_11        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_4_3               (DDRPHY_MD32_BASE_ADDRESS + 0x71CC)
+    #define LPIF_MR_OP_STORE_SHU_4_3_MR_OP_SET_SHU_4_12        Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_4_3_MR_OP_SET_SHU_4_13        Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_4_3_MR_OP_SET_SHU_4_14        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_4_3_MR_OP_SET_SHU_4_15        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_5_0               (DDRPHY_MD32_BASE_ADDRESS + 0x71D0)
+    #define LPIF_MR_OP_STORE_SHU_5_0_MR_OP_SET_SHU_5_0         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_5_0_MR_OP_SET_SHU_5_1         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_5_0_MR_OP_SET_SHU_5_2         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_5_0_MR_OP_SET_SHU_5_3         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_5_1               (DDRPHY_MD32_BASE_ADDRESS + 0x71D4)
+    #define LPIF_MR_OP_STORE_SHU_5_1_MR_OP_SET_SHU_5_4         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_5_1_MR_OP_SET_SHU_5_5         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_5_1_MR_OP_SET_SHU_5_6         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_5_1_MR_OP_SET_SHU_5_7         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_5_2               (DDRPHY_MD32_BASE_ADDRESS + 0x71D8)
+    #define LPIF_MR_OP_STORE_SHU_5_2_MR_OP_SET_SHU_5_8         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_5_2_MR_OP_SET_SHU_5_9         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_5_2_MR_OP_SET_SHU_5_10        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_5_2_MR_OP_SET_SHU_5_11        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_5_3               (DDRPHY_MD32_BASE_ADDRESS + 0x71DC)
+    #define LPIF_MR_OP_STORE_SHU_5_3_MR_OP_SET_SHU_5_12        Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_5_3_MR_OP_SET_SHU_5_13        Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_5_3_MR_OP_SET_SHU_5_14        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_5_3_MR_OP_SET_SHU_5_15        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_6_0               (DDRPHY_MD32_BASE_ADDRESS + 0x71E0)
+    #define LPIF_MR_OP_STORE_SHU_6_0_MR_OP_SET_SHU_6_0         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_6_0_MR_OP_SET_SHU_6_1         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_6_0_MR_OP_SET_SHU_6_2         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_6_0_MR_OP_SET_SHU_6_3         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_6_1               (DDRPHY_MD32_BASE_ADDRESS + 0x71E4)
+    #define LPIF_MR_OP_STORE_SHU_6_1_MR_OP_SET_SHU_6_4         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_6_1_MR_OP_SET_SHU_6_5         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_6_1_MR_OP_SET_SHU_6_6         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_6_1_MR_OP_SET_SHU_6_7         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_6_2               (DDRPHY_MD32_BASE_ADDRESS + 0x71E8)
+    #define LPIF_MR_OP_STORE_SHU_6_2_MR_OP_SET_SHU_6_8         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_6_2_MR_OP_SET_SHU_6_9         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_6_2_MR_OP_SET_SHU_6_10        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_6_2_MR_OP_SET_SHU_6_11        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_6_3               (DDRPHY_MD32_BASE_ADDRESS + 0x71EC)
+    #define LPIF_MR_OP_STORE_SHU_6_3_MR_OP_SET_SHU_6_12        Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_6_3_MR_OP_SET_SHU_6_13        Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_6_3_MR_OP_SET_SHU_6_14        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_6_3_MR_OP_SET_SHU_6_15        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_0               (DDRPHY_MD32_BASE_ADDRESS + 0x71F0)
+    #define LPIF_MR_OP_STORE_SHU_7_0_MR_OP_SET_SHU_7_0         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_7_0_MR_OP_SET_SHU_7_1         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_7_0_MR_OP_SET_SHU_7_2         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_7_0_MR_OP_SET_SHU_7_3         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_1               (DDRPHY_MD32_BASE_ADDRESS + 0x71F4)
+    #define LPIF_MR_OP_STORE_SHU_7_1_MR_OP_SET_SHU_7_4         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_7_1_MR_OP_SET_SHU_7_5         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_7_1_MR_OP_SET_SHU_7_6         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_7_1_MR_OP_SET_SHU_7_7         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_2               (DDRPHY_MD32_BASE_ADDRESS + 0x71F8)
+    #define LPIF_MR_OP_STORE_SHU_7_2_MR_OP_SET_SHU_7_8         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_7_2_MR_OP_SET_SHU_7_9         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_7_2_MR_OP_SET_SHU_7_10        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_7_2_MR_OP_SET_SHU_7_11        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_3               (DDRPHY_MD32_BASE_ADDRESS + 0x71FC)
+    #define LPIF_MR_OP_STORE_SHU_7_3_MR_OP_SET_SHU_7_12        Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_7_3_MR_OP_SET_SHU_7_13        Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_7_3_MR_OP_SET_SHU_7_14        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_7_3_MR_OP_SET_SHU_7_15        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_8_0               (DDRPHY_MD32_BASE_ADDRESS + 0x7200)
+    #define LPIF_MR_OP_STORE_SHU_8_0_MR_OP_SET_SHU_8_0         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_8_0_MR_OP_SET_SHU_8_1         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_8_0_MR_OP_SET_SHU_8_2         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_8_0_MR_OP_SET_SHU_8_3         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_8_1               (DDRPHY_MD32_BASE_ADDRESS + 0x7204)
+    #define LPIF_MR_OP_STORE_SHU_8_1_MR_OP_SET_SHU_8_4         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_8_1_MR_OP_SET_SHU_8_5         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_8_1_MR_OP_SET_SHU_8_6         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_8_1_MR_OP_SET_SHU_8_7         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_8_2               (DDRPHY_MD32_BASE_ADDRESS + 0x7208)
+    #define LPIF_MR_OP_STORE_SHU_8_2_MR_OP_SET_SHU_8_8         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_8_2_MR_OP_SET_SHU_8_9         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_8_2_MR_OP_SET_SHU_8_10        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_8_2_MR_OP_SET_SHU_8_11        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_8_3               (DDRPHY_MD32_BASE_ADDRESS + 0x720C)
+    #define LPIF_MR_OP_STORE_SHU_8_3_MR_OP_SET_SHU_8_12        Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_8_3_MR_OP_SET_SHU_8_13        Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_8_3_MR_OP_SET_SHU_8_14        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_8_3_MR_OP_SET_SHU_8_15        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_9_0               (DDRPHY_MD32_BASE_ADDRESS + 0x7210)
+    #define LPIF_MR_OP_STORE_SHU_9_0_MR_OP_SET_SHU_9_0         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_9_0_MR_OP_SET_SHU_9_1         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_9_0_MR_OP_SET_SHU_9_2         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_9_0_MR_OP_SET_SHU_9_3         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_9_1               (DDRPHY_MD32_BASE_ADDRESS + 0x7214)
+    #define LPIF_MR_OP_STORE_SHU_9_1_MR_OP_SET_SHU_9_4         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_9_1_MR_OP_SET_SHU_9_5         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_9_1_MR_OP_SET_SHU_9_6         Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_9_1_MR_OP_SET_SHU_9_7         Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_9_2               (DDRPHY_MD32_BASE_ADDRESS + 0x7218)
+    #define LPIF_MR_OP_STORE_SHU_9_2_MR_OP_SET_SHU_9_8         Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_9_2_MR_OP_SET_SHU_9_9         Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_9_2_MR_OP_SET_SHU_9_10        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_9_2_MR_OP_SET_SHU_9_11        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_9_3               (DDRPHY_MD32_BASE_ADDRESS + 0x721C)
+    #define LPIF_MR_OP_STORE_SHU_9_3_MR_OP_SET_SHU_9_12        Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_9_3_MR_OP_SET_SHU_9_13        Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_9_3_MR_OP_SET_SHU_9_14        Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_9_3_MR_OP_SET_SHU_9_15        Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_10_0              (DDRPHY_MD32_BASE_ADDRESS + 0x7220)
+    #define LPIF_MR_OP_STORE_SHU_10_0_MR_OP_SET_SHU_10_0       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_10_0_MR_OP_SET_SHU_10_1       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_10_0_MR_OP_SET_SHU_10_2       Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_10_0_MR_OP_SET_SHU_10_3       Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_10_1              (DDRPHY_MD32_BASE_ADDRESS + 0x7224)
+    #define LPIF_MR_OP_STORE_SHU_10_1_MR_OP_SET_SHU_10_4       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_10_1_MR_OP_SET_SHU_10_5       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_10_1_MR_OP_SET_SHU_10_6       Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_10_1_MR_OP_SET_SHU_10_7       Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_10_2              (DDRPHY_MD32_BASE_ADDRESS + 0x7228)
+    #define LPIF_MR_OP_STORE_SHU_10_2_MR_OP_SET_SHU_10_8       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_10_2_MR_OP_SET_SHU_10_9       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_10_2_MR_OP_SET_SHU_10_10      Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_10_2_MR_OP_SET_SHU_10_11      Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_10_3              (DDRPHY_MD32_BASE_ADDRESS + 0x722C)
+    #define LPIF_MR_OP_STORE_SHU_10_3_MR_OP_SET_SHU_10_12      Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_10_3_MR_OP_SET_SHU_10_13      Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_10_3_MR_OP_SET_SHU_10_14      Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_10_3_MR_OP_SET_SHU_10_15      Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_11_0              (DDRPHY_MD32_BASE_ADDRESS + 0x7230)
+    #define LPIF_MR_OP_STORE_SHU_11_0_MR_OP_SET_SHU_11_0       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_11_0_MR_OP_SET_SHU_11_1       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_11_0_MR_OP_SET_SHU_11_2       Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_11_0_MR_OP_SET_SHU_11_3       Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_11_1              (DDRPHY_MD32_BASE_ADDRESS + 0x7234)
+    #define LPIF_MR_OP_STORE_SHU_11_1_MR_OP_SET_SHU_11_4       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_11_1_MR_OP_SET_SHU_11_5       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_11_1_MR_OP_SET_SHU_11_6       Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_11_1_MR_OP_SET_SHU_11_7       Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_11_2              (DDRPHY_MD32_BASE_ADDRESS + 0x7238)
+    #define LPIF_MR_OP_STORE_SHU_11_2_MR_OP_SET_SHU_11_8       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_11_2_MR_OP_SET_SHU_11_9       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_11_2_MR_OP_SET_SHU_11_10      Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_11_2_MR_OP_SET_SHU_11_11      Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_11_3              (DDRPHY_MD32_BASE_ADDRESS + 0x723C)
+    #define LPIF_MR_OP_STORE_SHU_11_3_MR_OP_SET_SHU_11_12      Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_11_3_MR_OP_SET_SHU_11_13      Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_11_3_MR_OP_SET_SHU_11_14      Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_11_3_MR_OP_SET_SHU_11_15      Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_12_0              (DDRPHY_MD32_BASE_ADDRESS + 0x7240)
+    #define LPIF_MR_OP_STORE_SHU_12_0_MR_OP_SET_SHU_12_0       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_12_0_MR_OP_SET_SHU_12_1       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_12_0_MR_OP_SET_SHU_12_2       Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_12_0_MR_OP_SET_SHU_12_3       Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_12_1              (DDRPHY_MD32_BASE_ADDRESS + 0x7244)
+    #define LPIF_MR_OP_STORE_SHU_12_1_MR_OP_SET_SHU_12_4       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_12_1_MR_OP_SET_SHU_12_5       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_12_1_MR_OP_SET_SHU_12_6       Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_12_1_MR_OP_SET_SHU_12_7       Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_12_2              (DDRPHY_MD32_BASE_ADDRESS + 0x7248)
+    #define LPIF_MR_OP_STORE_SHU_12_2_MR_OP_SET_SHU_12_8       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_12_2_MR_OP_SET_SHU_12_9       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_12_2_MR_OP_SET_SHU_12_10      Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_12_2_MR_OP_SET_SHU_12_11      Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_12_3              (DDRPHY_MD32_BASE_ADDRESS + 0x724C)
+    #define LPIF_MR_OP_STORE_SHU_12_3_MR_OP_SET_SHU_12_12      Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_12_3_MR_OP_SET_SHU_12_13      Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_12_3_MR_OP_SET_SHU_12_14      Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_12_3_MR_OP_SET_SHU_12_15      Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_13_0              (DDRPHY_MD32_BASE_ADDRESS + 0x7250)
+    #define LPIF_MR_OP_STORE_SHU_13_0_MR_OP_SET_SHU_13_0       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_13_0_MR_OP_SET_SHU_13_1       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_13_0_MR_OP_SET_SHU_13_2       Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_13_0_MR_OP_SET_SHU_13_3       Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_13_1              (DDRPHY_MD32_BASE_ADDRESS + 0x7254)
+    #define LPIF_MR_OP_STORE_SHU_13_1_MR_OP_SET_SHU_13_4       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_13_1_MR_OP_SET_SHU_13_5       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_13_1_MR_OP_SET_SHU_13_6       Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_13_1_MR_OP_SET_SHU_13_7       Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_13_2              (DDRPHY_MD32_BASE_ADDRESS + 0x7258)
+    #define LPIF_MR_OP_STORE_SHU_13_2_MR_OP_SET_SHU_13_8       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_13_2_MR_OP_SET_SHU_13_9       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_13_2_MR_OP_SET_SHU_13_10      Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_13_2_MR_OP_SET_SHU_13_11      Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_13_3              (DDRPHY_MD32_BASE_ADDRESS + 0x725C)
+    #define LPIF_MR_OP_STORE_SHU_13_3_MR_OP_SET_SHU_13_12      Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_13_3_MR_OP_SET_SHU_13_13      Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_13_3_MR_OP_SET_SHU_13_14      Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_13_3_MR_OP_SET_SHU_13_15      Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_14_0              (DDRPHY_MD32_BASE_ADDRESS + 0x7260)
+    #define LPIF_MR_OP_STORE_SHU_14_0_MR_OP_SET_SHU_14_0       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_14_0_MR_OP_SET_SHU_14_1       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_14_0_MR_OP_SET_SHU_14_2       Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_14_0_MR_OP_SET_SHU_14_3       Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_14_1              (DDRPHY_MD32_BASE_ADDRESS + 0x7264)
+    #define LPIF_MR_OP_STORE_SHU_14_1_MR_OP_SET_SHU_14_4       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_14_1_MR_OP_SET_SHU_14_5       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_14_1_MR_OP_SET_SHU_14_6       Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_14_1_MR_OP_SET_SHU_14_7       Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_14_2              (DDRPHY_MD32_BASE_ADDRESS + 0x7268)
+    #define LPIF_MR_OP_STORE_SHU_14_2_MR_OP_SET_SHU_14_8       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_14_2_MR_OP_SET_SHU_14_9       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_14_2_MR_OP_SET_SHU_14_10      Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_14_2_MR_OP_SET_SHU_14_11      Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_14_3              (DDRPHY_MD32_BASE_ADDRESS + 0x726C)
+    #define LPIF_MR_OP_STORE_SHU_14_3_MR_OP_SET_SHU_14_12      Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_14_3_MR_OP_SET_SHU_14_13      Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_14_3_MR_OP_SET_SHU_14_14      Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_14_3_MR_OP_SET_SHU_14_15      Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_0              (DDRPHY_MD32_BASE_ADDRESS + 0x7270)
+    #define LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_0       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_1       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_2       Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_3       Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_1              (DDRPHY_MD32_BASE_ADDRESS + 0x7274)
+    #define LPIF_MR_OP_STORE_SHU_15_1_MR_OP_SET_SHU_15_4       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_15_1_MR_OP_SET_SHU_15_5       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_15_1_MR_OP_SET_SHU_15_6       Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_15_1_MR_OP_SET_SHU_15_7       Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_2              (DDRPHY_MD32_BASE_ADDRESS + 0x7278)
+    #define LPIF_MR_OP_STORE_SHU_15_2_MR_OP_SET_SHU_15_8       Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_15_2_MR_OP_SET_SHU_15_9       Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_15_2_MR_OP_SET_SHU_15_10      Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_15_2_MR_OP_SET_SHU_15_11      Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_3              (DDRPHY_MD32_BASE_ADDRESS + 0x727C)
+    #define LPIF_MR_OP_STORE_SHU_15_3_MR_OP_SET_SHU_15_12      Fld(8, 0) //[7:0]
+    #define LPIF_MR_OP_STORE_SHU_15_3_MR_OP_SET_SHU_15_13      Fld(8, 8) //[15:8]
+    #define LPIF_MR_OP_STORE_SHU_15_3_MR_OP_SET_SHU_15_14      Fld(8, 16) //[23:16]
+    #define LPIF_MR_OP_STORE_SHU_15_3_MR_OP_SET_SHU_15_15      Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_INT_PSTA_0                        (DDRPHY_MD32_BASE_ADDRESS + 0x7280)
+    #define LPIF_INT_PSTA_0_PSTA_CLK_26M_EN                    Fld(1, 0) //[0:0]
+    #define LPIF_INT_PSTA_0_PSTA_IN_SYNC_BYPASS                Fld(1, 1) //[1:1]
+    #define LPIF_INT_PSTA_0_PSTA_TEST_TRIGGER_EN               Fld(1, 2) //[2:2]
+    #define LPIF_INT_PSTA_0_PTA_ABORT_CASE_EN                  Fld(1, 3) //[3:3]
+    #define LPIF_INT_PSTA_0_PSTA_ABORT_TIME_RAND_EN            Fld(1, 4) //[4:4]
+    #define LPIF_INT_PSTA_0_PSTA_PST_TO_REQ_TIME_RAND_EN       Fld(1, 5) //[5:5]
+    #define LPIF_INT_PSTA_0_PSTA_REQ_TO_NXT_PST_TIME_RAND_EN   Fld(1, 6) //[6:6]
+    #define LPIF_INT_PSTA_0_PSTA_ACK_TO_PST_REQ_LOW_TIME_RAND_EN Fld(1, 7) //[7:7]
+    #define LPIF_INT_PSTA_0_PSTA_LOOP_MODE_ENABLE              Fld(1, 8) //[8:8]
+    #define LPIF_INT_PSTA_0_PSTA_TEST_CLR                      Fld(1, 9) //[9:9]
+    #define LPIF_INT_PSTA_0_RESERVED_XA0_11_10                 Fld(2, 10) //[11:10]
+    #define LPIF_INT_PSTA_0_PSTA_HW_S1_TEST_EN                 Fld(1, 12) //[12:12]
+    #define LPIF_INT_PSTA_0_PSTA_HW_S1_HIGH_PERIOD_TIME_RAND_EN Fld(1, 13) //[13:13]
+    #define LPIF_INT_PSTA_0_PSTA_HW_S1_REQ_INTV_TIME_RAND_EN   Fld(1, 14) //[14:14]
+    #define LPIF_INT_PSTA_0_PSTA_HW_S1_BYPASS_LOW_ACK_CHK      Fld(1, 15) //[15:15]
+    #define LPIF_INT_PSTA_0_PSTA_TEST_CND_0_EN                 Fld(1, 16) //[16:16]
+    #define LPIF_INT_PSTA_0_PSTA_TEST_CND_1_EN                 Fld(1, 17) //[17:17]
+    #define LPIF_INT_PSTA_0_PSTA_TEST_CND_2_EN                 Fld(1, 18) //[18:18]
+    #define LPIF_INT_PSTA_0_PSTA_TEST_CND_3_EN                 Fld(1, 19) //[19:19]
+    #define LPIF_INT_PSTA_0_PSTA_TEST_CND_4_EN                 Fld(1, 20) //[20:20]
+    #define LPIF_INT_PSTA_0_PSTA_TEST_CND_5_EN                 Fld(1, 21) //[21:21]
+    #define LPIF_INT_PSTA_0_PSTA_TEST_CND_6_EN                 Fld(1, 22) //[22:22]
+    #define LPIF_INT_PSTA_0_PSTA_TEST_CND_7_EN                 Fld(1, 23) //[23:23]
+    #define LPIF_INT_PSTA_0_RESERVED_XA0_31_24                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_INT_PSTA_1                        (DDRPHY_MD32_BASE_ADDRESS + 0x7284)
+    #define LPIF_INT_PSTA_1_PSTA_LOOP_MODE_TIME                Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_INT_PSTA_2                        (DDRPHY_MD32_BASE_ADDRESS + 0x7288)
+    #define LPIF_INT_PSTA_2_PSTA_ABORT_TIME                    Fld(10, 0) //[9:0]
+    #define LPIF_INT_PSTA_2_PSTA_ABORT_TIME_MIN                Fld(10, 10) //[19:10]
+    #define LPIF_INT_PSTA_2_PSTA_ABORT_TIME_MAX                Fld(10, 20) //[29:20]
+    #define LPIF_INT_PSTA_2_RESERVED_XA2_31_30                 Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_INT_PSTA_3                        (DDRPHY_MD32_BASE_ADDRESS + 0x728C)
+    #define LPIF_INT_PSTA_3_PSTA_PST_TO_REQ_TIME               Fld(4, 0) //[3:0]
+    #define LPIF_INT_PSTA_3_PSTA_PST_TO_REQ_TIME_MIN           Fld(4, 4) //[7:4]
+    #define LPIF_INT_PSTA_3_PSTA_PST_TO_REQ_TIME_MAX           Fld(4, 8) //[11:8]
+    #define LPIF_INT_PSTA_3_RESERVED_XA3_15_12                 Fld(4, 12) //[15:12]
+    #define LPIF_INT_PSTA_3_PSTA_ACK_TO_PST_REQ_LOW_TIME       Fld(4, 16) //[19:16]
+    #define LPIF_INT_PSTA_3_PSTA_ACK_TO_PST_REQ_LOW_TIME_MIN   Fld(4, 20) //[23:20]
+    #define LPIF_INT_PSTA_3_PSTA_ACK_TO_PST_REQ_LOW_TIME_MAX   Fld(4, 24) //[27:24]
+    #define LPIF_INT_PSTA_3_RESERVED_XA3_31_28                 Fld(4, 28) //[31:28]
+
+#define DDRPHY_MD32_REG_LPIF_INT_PSTA_4                        (DDRPHY_MD32_BASE_ADDRESS + 0x7290)
+    #define LPIF_INT_PSTA_4_PSTA_REQ_TO_NXT_PST_TIME           Fld(8, 0) //[7:0]
+    #define LPIF_INT_PSTA_4_PSTA_REQ_TO_NXT_PST_TIME_MIN       Fld(8, 8) //[15:8]
+    #define LPIF_INT_PSTA_4_PSTA_REQ_TO_NXT_PST_TIME_MAX       Fld(8, 16) //[23:16]
+    #define LPIF_INT_PSTA_4_RESERVED_XA4_31_24                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_INT_PSTA_5                        (DDRPHY_MD32_BASE_ADDRESS + 0x7294)
+    #define LPIF_INT_PSTA_5_PSTA_CMD_PST_0                     Fld(5, 0) //[4:0]
+    #define LPIF_INT_PSTA_5_RESERVED_XA5_7_5                   Fld(3, 5) //[7:5]
+    #define LPIF_INT_PSTA_5_PSTA_CMD_PST_1                     Fld(5, 8) //[12:8]
+    #define LPIF_INT_PSTA_5_RESERVED_XA5_15_13                 Fld(3, 13) //[15:13]
+    #define LPIF_INT_PSTA_5_PSTA_CMD_PST_2                     Fld(5, 16) //[20:16]
+    #define LPIF_INT_PSTA_5_RESERVED_XA5_23_21                 Fld(3, 21) //[23:21]
+    #define LPIF_INT_PSTA_5_PSTA_CMD_PST_3                     Fld(5, 24) //[28:24]
+    #define LPIF_INT_PSTA_5_RESERVED_XA5_31_29                 Fld(3, 29) //[31:29]
+
+#define DDRPHY_MD32_REG_LPIF_INT_PSTA_6                        (DDRPHY_MD32_BASE_ADDRESS + 0x7298)
+    #define LPIF_INT_PSTA_6_PSTA_CMD_PST_4                     Fld(5, 0) //[4:0]
+    #define LPIF_INT_PSTA_6_RESERVED_XA6_7_5                   Fld(3, 5) //[7:5]
+    #define LPIF_INT_PSTA_6_PSTA_CMD_PST_5                     Fld(5, 8) //[12:8]
+    #define LPIF_INT_PSTA_6_RESERVED_XA6_15_13                 Fld(3, 13) //[15:13]
+    #define LPIF_INT_PSTA_6_PSTA_CMD_PST_6                     Fld(5, 16) //[20:16]
+    #define LPIF_INT_PSTA_6_RESERVED_XA6_23_21                 Fld(3, 21) //[23:21]
+    #define LPIF_INT_PSTA_6_PSTA_CMD_PST_7                     Fld(5, 24) //[28:24]
+    #define LPIF_INT_PSTA_6_RESERVED_XA6_31_29                 Fld(3, 29) //[31:29]
+
+#define DDRPHY_MD32_REG_LPIF_INT_PSTA_7                        (DDRPHY_MD32_BASE_ADDRESS + 0x729C)
+    #define LPIF_INT_PSTA_7_PSTA_ABORT_TIME_LSFR_POL           Fld(20, 0) //[19:0]
+    #define LPIF_INT_PSTA_7_RESERVED_XA7_23_20                 Fld(4, 20) //[23:20]
+    #define LPIF_INT_PSTA_7_PSTA_ACK_TO_PST_REQ_LOW_TIME_LSFR_POL Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_INT_PSTA_8                        (DDRPHY_MD32_BASE_ADDRESS + 0x72A0)
+    #define LPIF_INT_PSTA_8_PSTA_REQ_TO_NXT_PST_TIME_LSFR_POL  Fld(16, 0) //[15:0]
+    #define LPIF_INT_PSTA_8_PSTA_PST_TO_REQ_TIME_LSFR_POL      Fld(8, 16) //[23:16]
+    #define LPIF_INT_PSTA_8_RESERVED_XA8_31_24                 Fld(8, 24) //[31:24]
+
+#define DDRPHY_MD32_REG_LPIF_INT_PSTA_9                        (DDRPHY_MD32_BASE_ADDRESS + 0x72A4)
+    #define LPIF_INT_PSTA_9_PSTA_DDR_PST                       Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_INT_PSTA_10                       (DDRPHY_MD32_BASE_ADDRESS + 0x72A8)
+    #define LPIF_INT_PSTA_10_PSTA_DDR_PST_REQ                  Fld(1, 0) //[0:0]
+    #define LPIF_INT_PSTA_10_PSTA_DDR_PST_ABORT_REQ            Fld(1, 1) //[1:1]
+    #define LPIF_INT_PSTA_10_RESERVED_XAA_3_2                  Fld(2, 2) //[3:2]
+    #define LPIF_INT_PSTA_10_PSTA_DDR_FSM_DONE                 Fld(1, 4) //[4:4]
+    #define LPIF_INT_PSTA_10_PSTA_DDR_HW_S1_ACK                Fld(1, 5) //[5:5]
+    #define LPIF_INT_PSTA_10_PSTA_FSM                          Fld(5, 8) //[12:8]
+    #define LPIF_INT_PSTA_10_CNT_PSTA_FSM                      Fld(12, 16) //[27:16]
+    #define LPIF_INT_PSTA_10_RESERVED_XAA_31_28                Fld(4, 28) //[31:28]
+
+#define DDRPHY_MD32_REG_LPIF_INT_PSTA_11                       (DDRPHY_MD32_BASE_ADDRESS + 0x72AC)
+    #define LPIF_INT_PSTA_11_PSTA_HW_S1_REQ_INTV_TIME          Fld(10, 0) //[9:0]
+    #define LPIF_INT_PSTA_11_PSTA_HW_S1_REQ_INTV_TIME_MIN      Fld(10, 10) //[19:10]
+    #define LPIF_INT_PSTA_11_PSTA_HW_S1_REQ_INTV_TIME_MAX      Fld(10, 20) //[29:20]
+    #define LPIF_INT_PSTA_11_RESERVED_XAB_31_30                Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_INT_PSTA_12                       (DDRPHY_MD32_BASE_ADDRESS + 0x72B0)
+    #define LPIF_INT_PSTA_12_PSTA_HW_S1_HIGH_PERIOD_TIME       Fld(10, 0) //[9:0]
+    #define LPIF_INT_PSTA_12_PSTA_HW_S1_HIGH_PERIOD_TIME_MIN   Fld(10, 10) //[19:10]
+    #define LPIF_INT_PSTA_12_PSTA_HW_S1_HIGH_PERIOD_TIME_MAX   Fld(10, 20) //[29:20]
+    #define LPIF_INT_PSTA_12_RESERVED_XAC_31_30                Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_INT_PSTA_13                       (DDRPHY_MD32_BASE_ADDRESS + 0x72B4)
+    #define LPIF_INT_PSTA_13_PSTA_HW_S1_REQ_INTV_TIME_LSFR_POL Fld(20, 0) //[19:0]
+    #define LPIF_INT_PSTA_13_RESERVED_XAD_31_30                Fld(12, 20) //[31:20]
+
+#define DDRPHY_MD32_REG_LPIF_INT_PSTA_14                       (DDRPHY_MD32_BASE_ADDRESS + 0x72B8)
+    #define LPIF_INT_PSTA_14_PSTA_HW_S1_HIGH_PERIOD_TIME_LSFR_POL Fld(20, 0) //[19:0]
+    #define LPIF_INT_PSTA_14_RESERVED_XAE_31_30                Fld(12, 20) //[31:20]
+
+#define DDRPHY_MD32_REG_LPIF_HW_S1_0                           (DDRPHY_MD32_BASE_ADDRESS + 0x72C0)
+    #define LPIF_HW_S1_0_HW_S1_PS_CHK_RESULT_CLR               Fld(1, 0) //[0:0]
+    #define LPIF_HW_S1_0_HW_S1_LATCH_CLR                       Fld(1, 1) //[1:1]
+    #define LPIF_HW_S1_0_HW_S1_TRIG_BY_FSM_EN                  Fld(1, 2) //[2:2]
+    #define LPIF_HW_S1_0_HW_S1_TRIG_BY_IRQ_EN                  Fld(1, 3) //[3:3]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_DMSUS_OFF                Fld(1, 4) //[4:4]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_MODE_SW              Fld(1, 5) //[5:5]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_DLL_EN               Fld(1, 6) //[6:6]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_2ND_DLL_EN           Fld(1, 7) //[7:7]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_DLL_CK_EN            Fld(1, 8) //[8:8]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_VREF_EN              Fld(1, 9) //[9:9]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_EMI_CLK_OFF_REQ          Fld(1, 10) //[10:10]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_MEM_CK_OFF               Fld(1, 11) //[11:11]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_DDRPHY_FB_CK_EN          Fld(1, 12) //[12:12]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_TX_TRACKING_DIS          Fld(1, 13) //[13:13]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_FHC_PAUSE_MPLL           Fld(1, 14) //[14:14]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_FHC_PAUSE_MEM            Fld(1, 15) //[15:15]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_MCK8X_EN             Fld(1, 16) //[16:16]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_MIDPI_EN             Fld(1, 17) //[17:17]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_PI_RESETB_EN         Fld(1, 18) //[18:18]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_DR_GATE_RETRY_EN         Fld(1, 19) //[19:19]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_DPHY_PRECAL_UP           Fld(1, 20) //[20:20]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_TX_TRACKING_RETRY_EN     Fld(1, 21) //[21:21]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_CS_PULL_DN_EN        Fld(1, 22) //[22:22]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_EMI_S1_MODE_ASYNC    Fld(1, 23) //[23:23]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_CA_PULL_DN_EN        Fld(1, 24) //[24:24]
+    #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_PICG_FREE            Fld(1, 25) //[25:25]
+    #define LPIF_HW_S1_0_RESERVED_XB0_31_26                    Fld(6, 26) //[31:26]
+
+#define DDRPHY_MD32_REG_LPIF_HW_S1_1                           (DDRPHY_MD32_BASE_ADDRESS + 0x72C4)
+    #define LPIF_HW_S1_1_HW_S1_PST_CHK                         Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_HW_S1_2                           (DDRPHY_MD32_BASE_ADDRESS + 0x72C8)
+    #define LPIF_HW_S1_2_HW_S1_PST_CHK_RESULT                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_HW_S1_3                           (DDRPHY_MD32_BASE_ADDRESS + 0x72CC)
+    #define LPIF_HW_S1_3_HW_S1_REQ                             Fld(1, 0) //[0:0]
+    #define LPIF_HW_S1_3_HW_S1_ACK                             Fld(1, 1) //[1:1]
+    #define LPIF_HW_S1_3_HW_S1_PST_REQ_CHK_RESULT              Fld(1, 2) //[2:2]
+    #define LPIF_HW_S1_3_RESERVED_XB0_3_3                      Fld(1, 3) //[3:3]
+    #define LPIF_HW_S1_3_RISING_HW_S1_REQ_LATCH                Fld(1, 4) //[4:4]
+    #define LPIF_HW_S1_3_FALLING_HW_S1_REQ_LATCH               Fld(1, 5) //[5:5]
+    #define LPIF_HW_S1_3_HW_S1_FSM                             Fld(6, 6) //[11:6]
+    #define LPIF_HW_S1_3_RESERVED_XB3_31_12                    Fld(20, 12) //[31:12]
+
+#define DDRPHY_MD32_REG_LPIF_HW_S1_4                           (DDRPHY_MD32_BASE_ADDRESS + 0x72D0)
+    #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_PI_RESETB_EN          Fld(2, 0) //[1:0]
+    #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_MIDPI_EN              Fld(2, 2) //[3:2]
+    #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_MCK8X_EN              Fld(2, 4) //[5:4]
+    #define LPIF_HW_S1_4_HW_S1_DRAMC_TX_TRACKING_RETRY_EN      Fld(2, 6) //[7:6]
+    #define LPIF_HW_S1_4_HW_S1_DRAMC_TX_TRACKING_DIS           Fld(2, 8) //[9:8]
+    #define LPIF_HW_S1_4_HW_S1_DRAMC_DPHY_PRECAL_UP            Fld(2, 10) //[11:10]
+    #define LPIF_HW_S1_4_HW_S1_DRAMC_DR_GATE_RETRY_EN          Fld(2, 12) //[13:12]
+    #define LPIF_HW_S1_4_HW_S1_DRAMC_DDRPHY_FB_CK_EN           Fld(2, 14) //[15:14]
+    #define LPIF_HW_S1_4_HW_S1_DRAMC_MEM_CK_OFF                Fld(2, 16) //[17:16]
+    #define LPIF_HW_S1_4_HW_S1_DRAMC_EMI_CLK_OFF_REQ           Fld(2, 18) //[19:18]
+    #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_VREF_EN               Fld(2, 20) //[21:20]
+    #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_DLL_CK_EN             Fld(2, 22) //[23:22]
+    #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_2ND_DLL_EN            Fld(2, 24) //[25:24]
+    #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_DLL_EN                Fld(2, 26) //[27:26]
+    #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_MODE_SW               Fld(2, 28) //[29:28]
+    #define LPIF_HW_S1_4_HW_S1_DRAMC_DMSUS_OFF                 Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_HW_S1_5                           (DDRPHY_MD32_BASE_ADDRESS + 0x72D4)
+    #define LPIF_HW_S1_5_HW_S1_DRAMC_FHC_PAUSE_MPLL            Fld(1, 0) //[0:0]
+    #define LPIF_HW_S1_5_HW_S1_DRAMC_FHC_PAUSE_MEM             Fld(1, 1) //[1:1]
+    #define LPIF_HW_S1_5_HW_S1_DRAMC_DPY_CS_PULL_DN_EN         Fld(2, 2) //[3:2]
+    #define LPIF_HW_S1_5_HW_S1_DRAMC_EMI_S1_MODE_ASYNC         Fld(1, 4) //[4:4]
+    #define LPIF_HW_S1_5_HW_S1_DRAMC_DPY_CA_PULL_DN_EN         Fld(2, 5) //[6:5]
+    #define LPIF_HW_S1_5_HW_S1_DRAMC_DPY_PICG_FREE             Fld(2, 8) //[9:8]
+    #define LPIF_HW_S1_5_RESERVED_XB5_31_10                    Fld(22, 10) //[31:10]
+
+#define DDRPHY_MD32_REG_LPIF_HW_S1_6                           (DDRPHY_MD32_BASE_ADDRESS + 0x72D8)
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_DMSUS_OFF                Fld(1, 0) //[0:0]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_MODE_SW              Fld(1, 1) //[1:1]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_DLL_EN               Fld(1, 2) //[2:2]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_2ND_DLL_EN           Fld(1, 3) //[3:3]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_DLL_CK_EN            Fld(1, 4) //[4:4]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_VREF_EN              Fld(1, 5) //[5:5]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_EMI_CLK_OFF_REQ          Fld(1, 6) //[6:6]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_MEM_CK_OFF               Fld(1, 7) //[7:7]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_DDRPHY_FB_CK_EN          Fld(1, 8) //[8:8]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_TX_TRACKING_DIS          Fld(1, 9) //[9:9]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_FHC_PAUSE_MPLL           Fld(1, 10) //[10:10]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_FHC_PAUSE_MEM            Fld(1, 11) //[11:11]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_MCK8X_EN             Fld(1, 12) //[12:12]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_MIDPI_EN             Fld(1, 13) //[13:13]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_PI_RESETB_EN         Fld(1, 14) //[14:14]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_DR_GATE_RETRY_EN         Fld(1, 15) //[15:15]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPHY_PRECAL_UP           Fld(1, 16) //[16:16]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_TX_TRACKING_RETRY_EN     Fld(1, 17) //[17:17]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_CS_PULL_DN_EN        Fld(1, 18) //[18:18]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_CA_PULL_DN_EN        Fld(1, 19) //[19:19]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_EMI_S1_MODE_ASYNC        Fld(1, 20) //[20:20]
+    #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_PICG_FREE            Fld(1, 21) //[21:21]
+    #define LPIF_HW_S1_6_RESERVED_XB6_31_22                    Fld(10, 22) //[31:22]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH0                        (DDRPHY_MD32_BASE_ADDRESS + 0x7380)
+    #define LPIF_DBG_LATCH0_LPIF_DDR_PST                       Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH1                        (DDRPHY_MD32_BASE_ADDRESS + 0x7384)
+    #define LPIF_DBG_LATCH1_CUR_LPIF_DDR_PST_STA               Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH2                        (DDRPHY_MD32_BASE_ADDRESS + 0x7388)
+    #define LPIF_DBG_LATCH2_EMI_CLK_OFF_REQ_ACK                Fld(2, 0) //[1:0]
+    #define LPIF_DBG_LATCH2_RESERVED_XE2_3_2                   Fld(2, 2) //[3:2]
+    #define LPIF_DBG_LATCH2_DRAMC_DFS_STA                      Fld(4, 4) //[7:4]
+    #define LPIF_DBG_LATCH2_DQSSOC_REQ                         Fld(2, 8) //[9:8]
+    #define LPIF_DBG_LATCH2_RESERVED_XE2_11_10                 Fld(2, 10) //[11:10]
+    #define LPIF_DBG_LATCH2_DR_SHORT_QUEUE_ACK                 Fld(2, 12) //[13:12]
+    #define LPIF_DBG_LATCH2_DR_SHU_EN_ACK                      Fld(2, 14) //[15:14]
+    #define LPIF_DBG_LATCH2_DR_SRAM_PLL_LOAD_ACK               Fld(2, 16) //[17:16]
+    #define LPIF_DBG_LATCH2_DR_SRAM_LOAD_ACK                   Fld(2, 18) //[19:18]
+    #define LPIF_DBG_LATCH2_DR_SRAM_RESTORE_ACK                Fld(2, 20) //[21:20]
+    #define LPIF_DBG_LATCH2_TX_TRACKING_DIS_ACK                Fld(2, 22) //[23:22]
+    #define LPIF_DBG_LATCH2_DDR_PST_ACK                        Fld(1, 24) //[24:24]
+    #define LPIF_DBG_LATCH2_DDR_PST_ABORT_ACK                  Fld(1, 25) //[25:25]
+    #define LPIF_DBG_LATCH2_EMI_SLEEP_IDLE                     Fld(1, 26) //[26:26]
+    #define LPIF_DBG_LATCH2_EMI_SLEEP_PROT_EN                  Fld(1, 27) //[27:27]
+    #define LPIF_DBG_LATCH2_DDR_PST_REQ                        Fld(1, 28) //[28:28]
+    #define LPIF_DBG_LATCH2_DDR_PST_ABORT_REQ                  Fld(1, 29) //[29:29]
+    #define LPIF_DBG_LATCH2_DDR_PST_ABORT_REQ_LATCH            Fld(1, 30) //[30:30]
+    #define LPIF_DBG_LATCH2_LPC_INTERNAL_COUNTER_ABORT_FLAG    Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH3                        (DDRPHY_MD32_BASE_ADDRESS + 0x738C)
+    #define LPIF_DBG_LATCH3_DDR_PST_STA_D0                     Fld(6, 0) //[5:0]
+    #define LPIF_DBG_LATCH3_DDR_PST_ACK_D0                     Fld(1, 6) //[6:6]
+    #define LPIF_DBG_LATCH3_DDR_PST_ABORT_ACK_D0               Fld(1, 7) //[7:7]
+    #define LPIF_DBG_LATCH3_DDR_PST_STA_D1                     Fld(6, 8) //[13:8]
+    #define LPIF_DBG_LATCH3_DDR_PST_ACK_D1                     Fld(1, 14) //[14:14]
+    #define LPIF_DBG_LATCH3_DDR_PST_ABORT_ACK_D1               Fld(1, 15) //[15:15]
+    #define LPIF_DBG_LATCH3_DDR_PST_STA_D2                     Fld(6, 16) //[21:16]
+    #define LPIF_DBG_LATCH3_DDR_PST_ACK_D2                     Fld(1, 22) //[22:22]
+    #define LPIF_DBG_LATCH3_DDR_PST_ABORT_ACK_D2               Fld(1, 23) //[23:23]
+    #define LPIF_DBG_LATCH3_DDR_PST_STA_D3                     Fld(6, 24) //[29:24]
+    #define LPIF_DBG_LATCH3_DDR_PST_ACK_D3                     Fld(1, 30) //[30:30]
+    #define LPIF_DBG_LATCH3_DDR_PST_ABORT_ACK_D3               Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH4                        (DDRPHY_MD32_BASE_ADDRESS + 0x7390)
+    #define LPIF_DBG_LATCH4_DDR_PST_STA_D4                     Fld(6, 0) //[5:0]
+    #define LPIF_DBG_LATCH4_DDR_PST_ACK_D4                     Fld(1, 6) //[6:6]
+    #define LPIF_DBG_LATCH4_DDR_PST_ABORT_ACK_D4               Fld(1, 7) //[7:7]
+    #define LPIF_DBG_LATCH4_DDR_PST_STA_D5                     Fld(6, 8) //[13:8]
+    #define LPIF_DBG_LATCH4_DDR_PST_ACK_D5                     Fld(1, 14) //[14:14]
+    #define LPIF_DBG_LATCH4_DDR_PST_ABORT_ACK_D5               Fld(1, 15) //[15:15]
+    #define LPIF_DBG_LATCH4_DDR_PST_STA_D6                     Fld(6, 16) //[21:16]
+    #define LPIF_DBG_LATCH4_DDR_PST_ACK_D6                     Fld(1, 22) //[22:22]
+    #define LPIF_DBG_LATCH4_DDR_PST_ABORT_ACK_D6               Fld(1, 23) //[23:23]
+    #define LPIF_DBG_LATCH4_DDR_PST_STA_D7                     Fld(6, 24) //[29:24]
+    #define LPIF_DBG_LATCH4_DDR_PST_ACK_D7                     Fld(1, 30) //[30:30]
+    #define LPIF_DBG_LATCH4_DDR_PST_ABORT_ACK_D7               Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH5                        (DDRPHY_MD32_BASE_ADDRESS + 0x7394)
+    #define LPIF_DBG_LATCH5_DDR_PST_STA_D8                     Fld(6, 0) //[5:0]
+    #define LPIF_DBG_LATCH5_DDR_PST_ACK_D8                     Fld(1, 6) //[6:6]
+    #define LPIF_DBG_LATCH5_DDR_PST_ABORT_ACK_D8               Fld(1, 7) //[7:7]
+    #define LPIF_DBG_LATCH5_DDR_PST_STA_D9                     Fld(6, 8) //[13:8]
+    #define LPIF_DBG_LATCH5_DDR_PST_ACK_D9                     Fld(1, 14) //[14:14]
+    #define LPIF_DBG_LATCH5_DDR_PST_ABORT_ACK_D9               Fld(1, 15) //[15:15]
+    #define LPIF_DBG_LATCH5_DDR_PST_STA_DA                     Fld(6, 16) //[21:16]
+    #define LPIF_DBG_LATCH5_DDR_PST_ACK_DA                     Fld(1, 22) //[22:22]
+    #define LPIF_DBG_LATCH5_DDR_PST_ABORT_ACK_DA               Fld(1, 23) //[23:23]
+    #define LPIF_DBG_LATCH5_DDR_PST_STA_DB                     Fld(6, 24) //[29:24]
+    #define LPIF_DBG_LATCH5_DDR_PST_ACK_DB                     Fld(1, 30) //[30:30]
+    #define LPIF_DBG_LATCH5_DDR_PST_ABORT_ACK_DB               Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH6                        (DDRPHY_MD32_BASE_ADDRESS + 0x7398)
+    #define LPIF_DBG_LATCH6_DDR_PST_STA_DC                     Fld(6, 0) //[5:0]
+    #define LPIF_DBG_LATCH6_DDR_PST_ACK_DC                     Fld(1, 6) //[6:6]
+    #define LPIF_DBG_LATCH6_DDR_PST_ABORT_ACK_DC               Fld(1, 7) //[7:7]
+    #define LPIF_DBG_LATCH6_DDR_PST_STA_DD                     Fld(6, 8) //[13:8]
+    #define LPIF_DBG_LATCH6_DDR_PST_ACK_DD                     Fld(1, 14) //[14:14]
+    #define LPIF_DBG_LATCH6_DDR_PST_ABORT_ACK_DD               Fld(1, 15) //[15:15]
+    #define LPIF_DBG_LATCH6_DDR_PST_STA_DE                     Fld(6, 16) //[21:16]
+    #define LPIF_DBG_LATCH6_DDR_PST_ACK_DE                     Fld(1, 22) //[22:22]
+    #define LPIF_DBG_LATCH6_DDR_PST_ABORT_ACK_DE               Fld(1, 23) //[23:23]
+    #define LPIF_DBG_LATCH6_DDR_PST_STA_DF                     Fld(6, 24) //[29:24]
+    #define LPIF_DBG_LATCH6_DDR_PST_ACK_DF                     Fld(1, 30) //[30:30]
+    #define LPIF_DBG_LATCH6_DDR_PST_ABORT_ACK_DF               Fld(1, 31) //[31:31]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH7                        (DDRPHY_MD32_BASE_ADDRESS + 0x739C)
+    #define LPIF_DBG_LATCH7_DRAMC_DMSUS_OFF                    Fld(2, 0) //[1:0]
+    #define LPIF_DBG_LATCH7_DRAMC_PHYPLL_EN                    Fld(2, 2) //[3:2]
+    #define LPIF_DBG_LATCH7_DRAMC_DPY_DLL_EN                   Fld(2, 4) //[5:4]
+    #define LPIF_DBG_LATCH7_DRAMC_DPY_2ND_DLL_EN               Fld(2, 6) //[7:6]
+    #define LPIF_DBG_LATCH7_DRAMC_DPY_DLL_CK_EN                Fld(2, 8) //[9:8]
+    #define LPIF_DBG_LATCH7_DRAMC_DPY_VREF_EN                  Fld(2, 10) //[11:10]
+    #define LPIF_DBG_LATCH7_DRAMC_EMI_CLK_OFF_REQ              Fld(2, 12) //[13:12]
+    #define LPIF_DBG_LATCH7_DRAMC_MEM_CK_OFF                   Fld(2, 14) //[15:14]
+    #define LPIF_DBG_LATCH7_DRAMC_DDRPHY_FB_CK_EN              Fld(2, 16) //[17:16]
+    #define LPIF_DBG_LATCH7_DRAMC_DR_GATE_RETRY_EN             Fld(2, 18) //[19:18]
+    #define LPIF_DBG_LATCH7_DRAMC_PHYPLL_SHU_EN                Fld(2, 20) //[21:20]
+    #define LPIF_DBG_LATCH7_DRAMC_PHYPLL_MODE_SW               Fld(2, 22) //[23:22]
+    #define LPIF_DBG_LATCH7_DRAMC_PHYPLL2_SHU_EN               Fld(2, 24) //[25:24]
+    #define LPIF_DBG_LATCH7_DRAMC_PHYPLL2_MODE_SW              Fld(2, 26) //[27:26]
+    #define LPIF_DBG_LATCH7_DRAMC_DR_SHU_EN                    Fld(2, 28) //[29:28]
+    #define LPIF_DBG_LATCH7_DRAMC_DR_SHORT_QUEUE               Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH8                        (DDRPHY_MD32_BASE_ADDRESS + 0x73A0)
+    #define LPIF_DBG_LATCH8_DRAMC_DR_SHU_LEVEL                 Fld(4, 0) //[3:0]
+    #define LPIF_DBG_LATCH8_DRAMC_DPY_BCLK_ENABLE              Fld(2, 4) //[5:4]
+    #define LPIF_DBG_LATCH8_DRAMC_SHU_RESTORE                  Fld(2, 6) //[7:6]
+    #define LPIF_DBG_LATCH8_DRAMC_DPHY_PRECAL_UP               Fld(2, 8) //[9:8]
+    #define LPIF_DBG_LATCH8_DRAMC_DPHY_RXDLY_TRACK_EN          Fld(2, 10) //[11:10]
+    #define LPIF_DBG_LATCH8_DRAMC_DMY_EN_MOD_SEL               Fld(2, 12) //[13:12]
+    #define LPIF_DBG_LATCH8_DRAMC_DMYRD_INTV_SEL               Fld(2, 14) //[15:14]
+    #define LPIF_DBG_LATCH8_DRAMC_DMYRD_EN                     Fld(2, 16) //[17:16]
+    #define LPIF_DBG_LATCH8_DRAMC_TX_TRACKING_DIS              Fld(2, 18) //[19:18]
+    #define LPIF_DBG_LATCH8_DRAMC_TX_TRACKING_RETRY_EN         Fld(2, 20) //[21:20]
+    #define LPIF_DBG_LATCH8_DRAMC_DR_SHU_SRAM_LEVEL            Fld(8, 22) //[29:22]
+    #define LPIF_DBG_LATCH8_DRAMC_DR_SRAM_LOAD                 Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH9                        (DDRPHY_MD32_BASE_ADDRESS + 0x73A4)
+    #define LPIF_DBG_LATCH9_DRAMC_DPY_MCK8X_EN                 Fld(2, 0) //[1:0]
+    #define LPIF_DBG_LATCH9_DRAMC_DPY_MIDPI_EN                 Fld(2, 2) //[3:2]
+    #define LPIF_DBG_LATCH9_DRAMC_DPY_PI_RESETB_EN             Fld(2, 4) //[5:4]
+    #define LPIF_DBG_LATCH9_DRAMC_DVFS_MEM_CK_MUX_UPDATE       Fld(2, 6) //[7:6]
+    #define LPIF_DBG_LATCH9_DRAMC_DVFS_MEM_CK_MUX_SEL          Fld(4, 8) //[11:8]
+    #define LPIF_DBG_LATCH9_DRAMC_DPY_DSM_EN                   Fld(2, 12) //[13:12]
+    #define LPIF_DBG_LATCH9_DRAMC_DPY_FASTK_RDDQS_EN           Fld(2, 14) //[15:14]
+    #define LPIF_DBG_LATCH9_DRAMC_DPY_CS_PULL_UP_EN            Fld(2, 16) //[17:16]
+    #define LPIF_DBG_LATCH9_DRAMC_DPY_CS_PULL_DN_EN            Fld(2, 18) //[19:18]
+    #define LPIF_DBG_LATCH9_DRAMC_DPY_CA_PULL_UP_EN            Fld(2, 20) //[21:20]
+    #define LPIF_DBG_LATCH9_DRAMC_DPY_CA_PULL_DN_EN            Fld(2, 22) //[23:22]
+    #define LPIF_DBG_LATCH9_DRAMC_FHC_PAUSE_MEM                Fld(1, 24) //[24:24]
+    #define LPIF_DBG_LATCH9_DRAMC_FHC_PAUSE_MPLL               Fld(1, 25) //[25:25]
+    #define LPIF_DBG_LATCH9_DRAMC_MPLL_S_OFF                   Fld(1, 26) //[26:26]
+    #define LPIF_DBG_LATCH9_DRAMC_MPLLOUT_OFF                  Fld(1, 27) //[27:27]
+    #define LPIF_DBG_LATCH9_DRAMC_EMI_S1_MODE_ASYNC            Fld(1, 28) //[28:28]
+    #define LPIF_DBG_LATCH9_RESERVED_XE9_29_29                 Fld(1, 29) //[29:29]
+    #define LPIF_DBG_LATCH9_DRAMC_DPY_PICG_FREE                Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH10                       (DDRPHY_MD32_BASE_ADDRESS + 0x73A8)
+    #define LPIF_DBG_LATCH10_DRAMC_DR_SRAM_RESTORE             Fld(2, 0) //[1:0]
+    #define LPIF_DBG_LATCH10_DRAMC_DR_SHU_LEVEL_SRAM_LATCH     Fld(2, 2) //[3:2]
+    #define LPIF_DBG_LATCH10_DRAMC_DPY_MODE_SW                 Fld(2, 4) //[5:4]
+    #define LPIF_DBG_LATCH10_RESERVED_XEA_7_6                  Fld(2, 6) //[7:6]
+    #define LPIF_DBG_LATCH10_DRAMC_DPY_RESERVED                Fld(8, 8) //[15:8]
+    #define LPIF_DBG_LATCH10_DRAMC_DRAMC_DFS_CON               Fld(13, 16) //[28:16]
+    #define LPIF_DBG_LATCH10_RESERVED_XEA_31_29                Fld(3, 29) //[31:29]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH11                       (DDRPHY_MD32_BASE_ADDRESS + 0x73AC)
+    #define LPIF_DBG_LATCH11_FSM_TIME_OUT_FLAG                 Fld(1, 0) //[0:0]
+    #define LPIF_DBG_LATCH11_EXP_FSM_JUMP                      Fld(1, 1) //[1:1]
+    #define LPIF_DBG_LATCH11_IRQ_LPIF_LOW_POWER                Fld(1, 2) //[2:2]
+    #define LPIF_DBG_LATCH11_IRQ_LPIF_OTHERS_STATE             Fld(1, 3) //[3:3]
+    #define LPIF_DBG_LATCH11_DFS_STATUS_RECORD                 Fld(4, 4) //[7:4]
+    #define LPIF_DBG_LATCH11_DVS_STATUS_RECORD                 Fld(1, 8) //[8:8]
+    #define LPIF_DBG_LATCH11_RUNTIME_STATUS_RECORD             Fld(1, 9) //[9:9]
+    #define LPIF_DBG_LATCH11_RESERVED_XEB_11_10                Fld(2, 10) //[11:10]
+    #define LPIF_DBG_LATCH11_MUX_LPIF_DPHY_RXDLY_TRACK_EN      Fld(1, 12) //[12:12]
+    #define LPIF_DBG_LATCH11_MUX_LPIF_DMYRD_EN                 Fld(1, 13) //[13:13]
+    #define LPIF_DBG_LATCH11_MUX_LPIF_TX_TRACKING_DIS          Fld(1, 14) //[14:14]
+    #define LPIF_DBG_LATCH11_MUX_LPIF_DR_SRAM_RESTORE          Fld(1, 15) //[15:15]
+    #define LPIF_DBG_LATCH11_MUX_LPIF_TX_TRACK_RETRY_EN        Fld(1, 16) //[16:16]
+    #define LPIF_DBG_LATCH11_MUX_LPIF_RX_GATING_RETRY_EN       Fld(1, 17) //[17:17]
+    #define LPIF_DBG_LATCH11_MUX_LPIF_DLL_ALL_SLAVE_EN         Fld(1, 18) //[18:18]
+    #define LPIF_DBG_LATCH11_MUX_LPIF_IMPEDANCE_TRACKING_EN    Fld(1, 19) //[19:19]
+    #define LPIF_DBG_LATCH11_MUX_LPIF_DPHY_RXDLY_TRACK_EN_PREV Fld(1, 20) //[20:20]
+    #define LPIF_DBG_LATCH11_MUX_LPIF_DMYRD_EN_PREV            Fld(1, 21) //[21:21]
+    #define LPIF_DBG_LATCH11_MUX_LPIF_TX_TRACKING_DIS_PREV     Fld(1, 22) //[22:22]
+    #define LPIF_DBG_LATCH11_MUX_LPIF_DR_SRAM_RESTORE_PREV     Fld(1, 23) //[23:23]
+    #define LPIF_DBG_LATCH11_MUX_LPIF_TX_TRACK_RETRY_EN_PREV   Fld(1, 24) //[24:24]
+    #define LPIF_DBG_LATCH11_MUX_LPIF_RX_GATING_RETRY_EN_PREV  Fld(1, 25) //[25:25]
+    #define LPIF_DBG_LATCH11_MUX_LPIF_DLL_ALL_SLAVE_EN_PREV    Fld(1, 26) //[26:26]
+    #define LPIF_DBG_LATCH11_MUX_LPIF_IMPEDANCE_TRACKING_EN_PREV Fld(1, 27) //[27:27]
+    #define LPIF_DBG_LATCH11_SHU_INDEX                         Fld(1, 28) //[28:28]
+    #define LPIF_DBG_LATCH11_RESERVED_XEB_31_29                Fld(3, 29) //[31:29]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH12                       (DDRPHY_MD32_BASE_ADDRESS + 0x73B0)
+    #define LPIF_DBG_LATCH12_DRAMC_PWR_RST_B                   Fld(2, 0) //[1:0]
+    #define LPIF_DBG_LATCH12_DRAMC_PWR_ISO                     Fld(2, 2) //[3:2]
+    #define LPIF_DBG_LATCH12_DRAMC_PWR_ON                      Fld(2, 4) //[5:4]
+    #define LPIF_DBG_LATCH12_DRAMC_PWR_ON_2ND                  Fld(2, 6) //[7:6]
+    #define LPIF_DBG_LATCH12_DRAMC_PWR_CLK_DIS                 Fld(2, 8) //[9:8]
+    #define LPIF_DBG_LATCH12_DRAMC_MPLL_OFF                    Fld(1, 12) //[12:12]
+    #define LPIF_DBG_LATCH12_DRAMC_PWR_SRAM_PDN                Fld(4, 16) //[19:16]
+    #define LPIF_DBG_LATCH12_DRAMC_PWR_SC_SRAM_PDN_ACK         Fld(1, 20) //[20:20]
+    #define LPIF_DBG_LATCH12_DRAMC_SHU_SRAM_SLEEP_B            Fld(2, 24) //[25:24]
+    #define LPIF_DBG_LATCH12_DRAMC_SHU_SRAM_CKISO              Fld(2, 26) //[27:26]
+    #define LPIF_DBG_LATCH12_DRAMC_SHU_SRAM_ISOINT_B           Fld(2, 28) //[29:28]
+    #define LPIF_DBG_LATCH12_DRAMC_SHU_SRAM_PDN                Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH13                       (DDRPHY_MD32_BASE_ADDRESS + 0x73B4)
+    #define LPIF_DBG_LATCH13_DRAMC_LPIF_COM                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH14                       (DDRPHY_MD32_BASE_ADDRESS + 0x73B8)
+    #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_PI_RESETB_EN      Fld(2, 0) //[1:0]
+    #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_MIDPI_EN          Fld(2, 2) //[3:2]
+    #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_MCK8X_EN          Fld(2, 4) //[5:4]
+    #define LPIF_DBG_LATCH14_HW_S1_DRAMC_TX_TRACKING_RETRY_EN  Fld(2, 6) //[7:6]
+    #define LPIF_DBG_LATCH14_HW_S1_DRAMC_TX_TRACKING_DIS       Fld(2, 8) //[9:8]
+    #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPHY_PRECAL_UP        Fld(2, 10) //[11:10]
+    #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DR_GATE_RETRY_EN      Fld(2, 12) //[13:12]
+    #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DDRPHY_FB_CK_EN       Fld(2, 14) //[15:14]
+    #define LPIF_DBG_LATCH14_HW_S1_DRAMC_MEM_CK_OFF            Fld(2, 16) //[17:16]
+    #define LPIF_DBG_LATCH14_HW_S1_DRAMC_EMI_CLK_OFF_REQ       Fld(2, 18) //[19:18]
+    #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_VREF_EN           Fld(2, 20) //[21:20]
+    #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_DLL_CK_EN         Fld(2, 22) //[23:22]
+    #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_2ND_DLL_EN        Fld(2, 24) //[25:24]
+    #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_DLL_EN            Fld(2, 26) //[27:26]
+    #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_MODE_SW           Fld(2, 28) //[29:28]
+    #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DMSUS_OFF             Fld(2, 30) //[31:30]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH15                       (DDRPHY_MD32_BASE_ADDRESS + 0x73BC)
+    #define LPIF_DBG_LATCH15_HW_S1_DRAMC_FHC_PAUSE_MPLL        Fld(1, 0) //[0:0]
+    #define LPIF_DBG_LATCH15_HW_S1_DRAMC_FHC_PAUSE_MEM         Fld(1, 1) //[1:1]
+    #define LPIF_DBG_LATCH15_HW_S1_DRAMC_DPY_CS_PULL_DN_EN     Fld(2, 2) //[3:2]
+    #define LPIF_DBG_LATCH15_HW_S1_DRAMC_EMI_S1_MODE_ASYNC     Fld(1, 4) //[4:4]
+    #define LPIF_DBG_LATCH15_HW_S1_DRAMC_DPY_CA_PULL_DN_EN     Fld(2, 5) //[6:5]
+    #define LPIF_DBG_LATCH15_HW_S1_DRAMC_DPY_PICG_FREE         Fld(2, 8) //[9:8]
+    #define LPIF_DBG_LATCH15_PWR_ON_ACK                        Fld(2, 12) //[13:12]
+    #define LPIF_DBG_LATCH15_PWR_ON_2ND_ACK                    Fld(2, 14) //[15:14]
+    #define LPIF_DBG_LATCH15_SRAM_PDN_ACK                      Fld(4, 16) //[19:16]
+    #define LPIF_DBG_LATCH15_HW_S1_REQ                         Fld(1, 20) //[20:20]
+    #define LPIF_DBG_LATCH15_HW_S1_ACK                         Fld(1, 21) //[21:21]
+    #define LPIF_DBG_LATCH15_HW_S1_PST_REQ_CHK_RESULT          Fld(1, 22) //[22:22]
+    #define LPIF_DBG_LATCH15_RESERVED_XEF_31_23                Fld(9, 23) //[31:23]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH16                       (DDRPHY_MD32_BASE_ADDRESS + 0x73C0)
+    #define LPIF_DBG_LATCH16_HW_S1_PST_CHK_RESULT              Fld(32, 0) //[31:0]
+
+#define DDRPHY_MD32_REG_LPIF_DBG_LATCH17                       (DDRPHY_MD32_BASE_ADDRESS + 0x73C4)
+    #define LPIF_DBG_LATCH17_MAX_CNT_SREF_REQ_HIGH_TO_SREF_ACK Fld(8, 0) //[7:0]
+    #define LPIF_DBG_LATCH17_MAX_CNT_SREF_REQ_LOW_TO_SREF_ACK  Fld(8, 8) //[15:8]
+    #define LPIF_DBG_LATCH17_MAX_CNT_SHU_EN_HIGH_TO_ACK        Fld(8, 16) //[23:16]
+    #define LPIF_DBG_LATCH17_MAX_CNT_HW_S1_REQ_LOW_TO_SREF_ACK_LOW Fld(8, 24) //[31:24]
+
+#endif // __DDRPHY_MD32_REGS_H__
diff --git a/src/vendorcode/mediatek/mt8195/include/8195_Register_DDRPHY_NAO.h b/src/vendorcode/mediatek/mt8195/include/8195_Register_DDRPHY_NAO.h
new file mode 100644
index 000000000000..234f56e72d24
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/8195_Register_DDRPHY_NAO.h
@@ -0,0 +1,1206 @@
+#ifndef __DDRPHY_NAO_REGS_H__
+#define __DDRPHY_NAO_REGS_H__
+
+#define Channel_A_DDRPHY_NAO_BASE_ADDRESS    0x10236000
+#define Channel_B_DDRPHY_NAO_BASE_ADDRESS    0x10246000
+
+#define DDRPHY_NAO_BASE_ADDRESS     Channel_A_DDRPHY_NAO_BASE_VIRTUAL
+
+#define DDRPHY_REG_MISC_STA_EXTLB0                             (DDRPHY_NAO_BASE_ADDRESS + 0x0000)
+    #define MISC_STA_EXTLB0_STA_EXTLB_DONE                     Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_STA_EXTLB1                             (DDRPHY_NAO_BASE_ADDRESS + 0x0004)
+    #define MISC_STA_EXTLB1_STA_EXTLB_FAIL                     Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_STA_EXTLB2                             (DDRPHY_NAO_BASE_ADDRESS + 0x0008)
+    #define MISC_STA_EXTLB2_STA_EXTLB_DBG_INFO                 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DMA_DEBUG0                             (DDRPHY_NAO_BASE_ADDRESS + 0x0010)
+    #define MISC_DMA_DEBUG0_WPTR                               Fld(2, 0) //[1:0]
+    #define MISC_DMA_DEBUG0_RPTR                               Fld(2, 2) //[3:2]
+    #define MISC_DMA_DEBUG0_CMD_CNT                            Fld(3, 4) //[6:4]
+    #define MISC_DMA_DEBUG0_DATA_CNT                           Fld(3, 8) //[10:8]
+    #define MISC_DMA_DEBUG0_FIFO_EMPTY                         Fld(1, 12) //[12:12]
+    #define MISC_DMA_DEBUG0_FIFO_FULL                          Fld(1, 13) //[13:13]
+    #define MISC_DMA_DEBUG0_DMA_FIRE                           Fld(1, 14) //[14:14]
+    #define MISC_DMA_DEBUG0_SHU_REG_PTR                        Fld(1, 15) //[15:15]
+    #define MISC_DMA_DEBUG0_SRAM_DONE                          Fld(1, 16) //[16:16]
+    #define MISC_DMA_DEBUG0_APB_DONE                           Fld(1, 17) //[17:17]
+    #define MISC_DMA_DEBUG0_SRAM_DONE_EARLY                    Fld(1, 18) //[18:18]
+    #define MISC_DMA_DEBUG0_APB_DONE_EARLY                     Fld(1, 19) //[19:19]
+    #define MISC_DMA_DEBUG0_SRAM_STEP                          Fld(4, 20) //[23:20]
+    #define MISC_DMA_DEBUG0_APB_STEP                           Fld(4, 24) //[27:24]
+    #define MISC_DMA_DEBUG0_SC_DR_SRAM_PLL_LOAD_ACK            Fld(1, 28) //[28:28]
+    #define MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK                Fld(1, 29) //[29:29]
+    #define MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK             Fld(1, 30) //[30:30]
+
+#define DDRPHY_REG_MISC_DMA_DEBUG1                             (DDRPHY_NAO_BASE_ADDRESS + 0x0014)
+    #define MISC_DMA_DEBUG1_DMA_TIMER_EARLY                    Fld(6, 0) //[5:0]
+    #define MISC_DMA_DEBUG1_DMA_TIMER_ALL                      Fld(12, 8) //[19:8]
+    #define MISC_DMA_DEBUG1_PSEL_DDRPHY                        Fld(1, 20) //[20:20]
+    #define MISC_DMA_DEBUG1_PSEL_DRAMC                         Fld(1, 21) //[21:21]
+    #define MISC_DMA_DEBUG1_PSEL_DDRPHY2                       Fld(1, 22) //[22:22]
+    #define MISC_DMA_DEBUG1_PSEL_DRAMC2                        Fld(1, 23) //[23:23]
+    #define MISC_DMA_DEBUG1_DMA_PENABLE                        Fld(1, 24) //[24:24]
+    #define MISC_DMA_DEBUG1_PREADY                             Fld(1, 25) //[25:25]
+    #define MISC_DMA_DEBUG1_KEEP_APB_ARB                       Fld(1, 26) //[26:26]
+    #define MISC_DMA_DEBUG1_WR_APB                             Fld(1, 27) //[27:27]
+    #define MISC_DMA_DEBUG1_SRAM_CS                            Fld(1, 28) //[28:28]
+    #define MISC_DMA_DEBUG1_SRAM_GRANT                         Fld(1, 29) //[29:29]
+    #define MISC_DMA_DEBUG1_KEEP_SRAM_ARB                      Fld(1, 30) //[30:30]
+    #define MISC_DMA_DEBUG1_WR_SRAM                            Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_RETRY_DBG0                             (DDRPHY_NAO_BASE_ADDRESS + 0x0018)
+    #define MISC_RETRY_DBG0_PRECAL_CONF_CAL_DONE_ALL           Fld(1, 0) //[0:0]
+    #define MISC_RETRY_DBG0_RETRY_DONE_ALL                     Fld(1, 1) //[1:1]
+    #define MISC_RETRY_DBG0_RK0_RETRY_DONE0                    Fld(1, 4) //[4:4]
+    #define MISC_RETRY_DBG0_RK0_RETRY_DONE1                    Fld(1, 5) //[5:5]
+    #define MISC_RETRY_DBG0_RK0_RETRY_DONE2                    Fld(1, 6) //[6:6]
+    #define MISC_RETRY_DBG0_RK0_RETRY_FAIL0                    Fld(1, 8) //[8:8]
+    #define MISC_RETRY_DBG0_RK0_RETRY_FAIL1                    Fld(1, 9) //[9:9]
+    #define MISC_RETRY_DBG0_RK0_RETRY_FAIL2                    Fld(1, 10) //[10:10]
+    #define MISC_RETRY_DBG0_RK1_RETRY_DONE0                    Fld(1, 12) //[12:12]
+    #define MISC_RETRY_DBG0_RK1_RETRY_DONE1                    Fld(1, 13) //[13:13]
+    #define MISC_RETRY_DBG0_RK1_RETRY_DONE2                    Fld(1, 14) //[14:14]
+    #define MISC_RETRY_DBG0_RK1_RETRY_FAIL0                    Fld(1, 16) //[16:16]
+    #define MISC_RETRY_DBG0_RK1_RETRY_FAIL1                    Fld(1, 17) //[17:17]
+    #define MISC_RETRY_DBG0_RK1_RETRY_FAIL2                    Fld(1, 18) //[18:18]
+
+#define DDRPHY_REG_MISC_RETRY_DBG1                             (DDRPHY_NAO_BASE_ADDRESS + 0x001C)
+    #define MISC_RETRY_DBG1_DQSG_RETRY_1ST_ST                  Fld(8, 0) //[7:0]
+    #define MISC_RETRY_DBG1_DQSG_RETRY_2ND_ST                  Fld(8, 8) //[15:8]
+    #define MISC_RETRY_DBG1_DQSG_RETRY_3RD_ST                  Fld(8, 16) //[23:16]
+    #define MISC_RETRY_DBG1_DQSG_RETRY_4TH_ST                  Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_RETRY_DBG2                             (DDRPHY_NAO_BASE_ADDRESS + 0x0020)
+    #define MISC_RETRY_DBG2_DQSG_RETRY_5TH_ST                  Fld(8, 0) //[7:0]
+
+#define DDRPHY_REG_MISC_RDSEL_TRACK_DBG                        (DDRPHY_NAO_BASE_ADDRESS + 0x0024)
+    #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_SLOW_ST             Fld(1, 2) //[2:2]
+    #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_FAST_ST             Fld(1, 3) //[3:3]
+    #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_INI2SLOW            Fld(1, 4) //[4:4]
+    #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_INI2FAST            Fld(1, 5) //[5:5]
+    #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_SLOW2INI            Fld(1, 6) //[6:6]
+    #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_FAST2INI            Fld(1, 7) //[7:7]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO0                         (DDRPHY_NAO_BASE_ADDRESS + 0x0080)
+    #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LAG_CNT_OUT_B0   Fld(8, 0) //[7:0]
+    #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LEAD_CNT_OUT_B0  Fld(8, 8) //[15:8]
+    #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LAG_CNT_OUT_B1   Fld(8, 16) //[23:16]
+    #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LEAD_CNT_OUT_B1  Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO1                         (DDRPHY_NAO_BASE_ADDRESS + 0x0084)
+    #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LAG_CNT_OUT_B2   Fld(8, 0) //[7:0]
+    #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LEAD_CNT_OUT_B2  Fld(8, 8) //[15:8]
+    #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LAG_CNT_OUT_B3   Fld(8, 16) //[23:16]
+    #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LEAD_CNT_OUT_B3  Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO2                         (DDRPHY_NAO_BASE_ADDRESS + 0x0088)
+    #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LAG_CNT_OUT_B4   Fld(8, 0) //[7:0]
+    #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LEAD_CNT_OUT_B4  Fld(8, 8) //[15:8]
+    #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LAG_CNT_OUT_B5   Fld(8, 16) //[23:16]
+    #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LEAD_CNT_OUT_B5  Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO3                         (DDRPHY_NAO_BASE_ADDRESS + 0x008C)
+    #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LAG_CNT_OUT_B6   Fld(8, 0) //[7:0]
+    #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LEAD_CNT_OUT_B6  Fld(8, 8) //[15:8]
+    #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LAG_CNT_OUT_B7   Fld(8, 16) //[23:16]
+    #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LEAD_CNT_OUT_B7  Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO4                         (DDRPHY_NAO_BASE_ADDRESS + 0x0090)
+    #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B0 Fld(8, 0) //[7:0]
+    #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B1 Fld(8, 8) //[15:8]
+    #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B2 Fld(8, 16) //[23:16]
+    #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B3 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO5                         (DDRPHY_NAO_BASE_ADDRESS + 0x0094)
+    #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B4 Fld(8, 0) //[7:0]
+    #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B5 Fld(8, 8) //[15:8]
+    #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B6 Fld(8, 16) //[23:16]
+    #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B7 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO6                         (DDRPHY_NAO_BASE_ADDRESS + 0x0098)
+    #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_SW_LAG_CNT_OUT_DQM0 Fld(8, 0) //[7:0]
+    #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_SW_LEAD_CNT_OUT_DQM0 Fld(8, 8) //[15:8]
+    #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_LEAD_LAG_CNT_OUT_DQM0 Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO7                         (DDRPHY_NAO_BASE_ADDRESS + 0x009C)
+    #define MISC_DQ_RXDLY_TRRO7_DVS_RK0_B0_SW_UP_DONE          Fld(1, 0) //[0:0]
+    #define MISC_DQ_RXDLY_TRRO7_DVS_RK0_B1_SW_UP_DONE          Fld(1, 4) //[4:4]
+    #define MISC_DQ_RXDLY_TRRO7_DVS_RK1_B0_SW_UP_DONE          Fld(1, 8) //[8:8]
+    #define MISC_DQ_RXDLY_TRRO7_DVS_RK1_B1_SW_UP_DONE          Fld(1, 12) //[12:12]
+    #define MISC_DQ_RXDLY_TRRO7_DVS_RK2_B0_SW_UP_DONE          Fld(1, 16) //[16:16]
+    #define MISC_DQ_RXDLY_TRRO7_DVS_RK2_B1_SW_UP_DONE          Fld(1, 20) //[20:20]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO8                         (DDRPHY_NAO_BASE_ADDRESS + 0x00A0)
+    #define MISC_DQ_RXDLY_TRRO8_DVS_RKX_BX_TH_CNT_OUT_B0       Fld(9, 0) //[8:0]
+    #define MISC_DQ_RXDLY_TRRO8_DVS_RKX_BX_TH_CNT_OUT_B1       Fld(9, 16) //[24:16]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO9                         (DDRPHY_NAO_BASE_ADDRESS + 0x00A4)
+    #define MISC_DQ_RXDLY_TRRO9_DVS_RKX_BX_TH_CNT_OUT_B2       Fld(9, 0) //[8:0]
+    #define MISC_DQ_RXDLY_TRRO9_DVS_RKX_BX_TH_CNT_OUT_B3       Fld(9, 16) //[24:16]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO10                        (DDRPHY_NAO_BASE_ADDRESS + 0x00A8)
+    #define MISC_DQ_RXDLY_TRRO10_DVS_RKX_BX_TH_CNT_OUT_B4      Fld(9, 0) //[8:0]
+    #define MISC_DQ_RXDLY_TRRO10_DVS_RKX_BX_TH_CNT_OUT_B5      Fld(9, 16) //[24:16]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO11                        (DDRPHY_NAO_BASE_ADDRESS + 0x00AC)
+    #define MISC_DQ_RXDLY_TRRO11_DVS_RKX_BX_TH_CNT_OUT_B6      Fld(9, 0) //[8:0]
+    #define MISC_DQ_RXDLY_TRRO11_DVS_RKX_BX_TH_CNT_OUT_B7      Fld(9, 16) //[24:16]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO12                        (DDRPHY_NAO_BASE_ADDRESS + 0x00B0)
+    #define MISC_DQ_RXDLY_TRRO12_DVS_RKX_BX_TH_CNT_OUT_DQM0    Fld(9, 0) //[8:0]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO13                        (DDRPHY_NAO_BASE_ADDRESS + 0x00B4)
+    #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQX_B0_R_DLY           Fld(6, 0) //[5:0]
+    #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQS0_R_DLY             Fld(7, 8) //[14:8]
+    #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQX_B1_R_DLY           Fld(6, 16) //[21:16]
+    #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQS1_R_DLY             Fld(7, 24) //[30:24]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO14                        (DDRPHY_NAO_BASE_ADDRESS + 0x00B8)
+    #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQX_B0_R_DLY           Fld(6, 0) //[5:0]
+    #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQS0_R_DLY             Fld(7, 8) //[14:8]
+    #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQX_B1_R_DLY           Fld(6, 16) //[21:16]
+    #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQS1_R_DLY             Fld(7, 24) //[30:24]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO15                        (DDRPHY_NAO_BASE_ADDRESS + 0x00BC)
+    #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQX_B0_R_DLY           Fld(6, 0) //[5:0]
+    #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQS0_R_DLY             Fld(7, 8) //[14:8]
+    #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQX_B1_R_DLY           Fld(6, 16) //[21:16]
+    #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQS1_R_DLY             Fld(7, 24) //[30:24]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO16                        (DDRPHY_NAO_BASE_ADDRESS + 0x00C0)
+    #define MISC_DQ_RXDLY_TRRO16_DVS_RXDLY_STS_ERR_CNT_ALL     Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO17                        (DDRPHY_NAO_BASE_ADDRESS + 0x00C4)
+    #define MISC_DQ_RXDLY_TRRO17_DVS_RXDLY_STS_ERR_CNT_ALL_47_32 Fld(16, 0) //[15:0]
+    #define MISC_DQ_RXDLY_TRRO17_PBYTE_LEADLAG_STUCK_B0        Fld(1, 16) //[16:16]
+    #define MISC_DQ_RXDLY_TRRO17_PBYTE_LEADLAG_STUCK_B1        Fld(1, 24) //[24:24]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO18                        (DDRPHY_NAO_BASE_ADDRESS + 0x00C8)
+    #define MISC_DQ_RXDLY_TRRO18_RXDLY_DBG_MON_VALID           Fld(1, 0) //[0:0]
+    #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK0_FAIL_LAT            Fld(1, 1) //[1:1]
+    #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK1_FAIL_LAT            Fld(1, 2) //[2:2]
+    #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK2_FAIL_LAT            Fld(1, 3) //[3:3]
+    #define MISC_DQ_RXDLY_TRRO18_DFS_SHU_GP_FAIL_LAT           Fld(2, 4) //[5:4]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO19                        (DDRPHY_NAO_BASE_ADDRESS + 0x00CC)
+    #define MISC_DQ_RXDLY_TRRO19_RESERVED_0X00C                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO20                        (DDRPHY_NAO_BASE_ADDRESS + 0x00D0)
+    #define MISC_DQ_RXDLY_TRRO20_RESERVED_0X0D0                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO21                        (DDRPHY_NAO_BASE_ADDRESS + 0x00D4)
+    #define MISC_DQ_RXDLY_TRRO21_RESERVED_0X0D4                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO22                        (DDRPHY_NAO_BASE_ADDRESS + 0x00D8)
+    #define MISC_DQ_RXDLY_TRRO22_RESERVED_0X0D8                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO23                        (DDRPHY_NAO_BASE_ADDRESS + 0x00DC)
+    #define MISC_DQ_RXDLY_TRRO23_RESERVED_0X0DC                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO24                        (DDRPHY_NAO_BASE_ADDRESS + 0x00E0)
+    #define MISC_DQ_RXDLY_TRRO24_RESERVED_0X0E0                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO25                        (DDRPHY_NAO_BASE_ADDRESS + 0x00E4)
+    #define MISC_DQ_RXDLY_TRRO25_RESERVED_0X0E4                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO26                        (DDRPHY_NAO_BASE_ADDRESS + 0x00E8)
+    #define MISC_DQ_RXDLY_TRRO26_RESERVED_0X0E8                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO27                        (DDRPHY_NAO_BASE_ADDRESS + 0x00EC)
+    #define MISC_DQ_RXDLY_TRRO27_RESERVED_0X0EC                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO28                        (DDRPHY_NAO_BASE_ADDRESS + 0x00F0)
+    #define MISC_DQ_RXDLY_TRRO28_RESERVED_0X0F0                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO29                        (DDRPHY_NAO_BASE_ADDRESS + 0x00F4)
+    #define MISC_DQ_RXDLY_TRRO29_RESERVED_0X0F4                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO30                        (DDRPHY_NAO_BASE_ADDRESS + 0x00F8)
+    #define MISC_DQ_RXDLY_TRRO30_RESERVED_0X0F8                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO31                        (DDRPHY_NAO_BASE_ADDRESS + 0x00FC)
+    #define MISC_DQ_RXDLY_TRRO31_RESERVED_0X0FC                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_CA_RXDLY_TRRO20                        (DDRPHY_NAO_BASE_ADDRESS + 0x0150)
+    #define MISC_CA_RXDLY_TRRO20_RESERVED_0X150                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_CA_RXDLY_TRRO21                        (DDRPHY_NAO_BASE_ADDRESS + 0x0154)
+    #define MISC_CA_RXDLY_TRRO21_RESERVED_0X154                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_CA_RXDLY_TRRO22                        (DDRPHY_NAO_BASE_ADDRESS + 0x0158)
+    #define MISC_CA_RXDLY_TRRO22_RESERVED_0X158                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_CA_RXDLY_TRRO23                        (DDRPHY_NAO_BASE_ADDRESS + 0x015C)
+    #define MISC_CA_RXDLY_TRRO23_RESERVED_0X15C                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_CA_RXDLY_TRRO24                        (DDRPHY_NAO_BASE_ADDRESS + 0x0160)
+    #define MISC_CA_RXDLY_TRRO24_RESERVED_0X160                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_CA_RXDLY_TRRO25                        (DDRPHY_NAO_BASE_ADDRESS + 0x0164)
+    #define MISC_CA_RXDLY_TRRO25_RESERVED_0X164                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_CA_RXDLY_TRRO26                        (DDRPHY_NAO_BASE_ADDRESS + 0x0168)
+    #define MISC_CA_RXDLY_TRRO26_RESERVED_0X168                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_CA_RXDLY_TRRO27                        (DDRPHY_NAO_BASE_ADDRESS + 0x016C)
+    #define MISC_CA_RXDLY_TRRO27_RESERVED_0X16C                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_CA_RXDLY_TRRO28                        (DDRPHY_NAO_BASE_ADDRESS + 0x0170)
+    #define MISC_CA_RXDLY_TRRO28_RESERVED_0X170                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_CA_RXDLY_TRRO29                        (DDRPHY_NAO_BASE_ADDRESS + 0x0174)
+    #define MISC_CA_RXDLY_TRRO29_RESERVED_0X174                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_CA_RXDLY_TRRO30                        (DDRPHY_NAO_BASE_ADDRESS + 0x0178)
+    #define MISC_CA_RXDLY_TRRO30_RESERVED_0X178                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_CA_RXDLY_TRRO31                        (DDRPHY_NAO_BASE_ADDRESS + 0x017C)
+    #define MISC_CA_RXDLY_TRRO31_RESERVED_0X17C                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DQO1                                   (DDRPHY_NAO_BASE_ADDRESS + 0x0180)
+    #define MISC_DQO1_DQO1_RO                                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_CAO1                                   (DDRPHY_NAO_BASE_ADDRESS + 0x0184)
+    #define MISC_CAO1_DQM0O1_RO                                Fld(1, 0) //[0:0]
+    #define MISC_CAO1_DQM1O1_RO                                Fld(1, 1) //[1:1]
+    #define MISC_CAO1_DQM2O1_RO                                Fld(1, 2) //[2:2]
+    #define MISC_CAO1_DQM3O1_RO                                Fld(1, 3) //[3:3]
+
+#define DDRPHY_REG_MISC_AD_RX_DQ_O1                            (DDRPHY_NAO_BASE_ADDRESS + 0x0188)
+    #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B0                  Fld(8, 0) //[7:0]
+    #define MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B0                Fld(1, 8) //[8:8]
+    #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B1                  Fld(8, 16) //[23:16]
+    #define MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B1                Fld(1, 24) //[24:24]
+    #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ6_O1_C0                 Fld(1, 25) //[25:25]
+    #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ7_O1_C0                 Fld(1, 26) //[26:26]
+
+#define DDRPHY_REG_MISC_AD_RX_CMD_O1                           (DDRPHY_NAO_BASE_ADDRESS + 0x018C)
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCA0_O1                   Fld(1, 0) //[0:0]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCA1_O1                   Fld(1, 1) //[1:1]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCA2_O1                   Fld(1, 2) //[2:2]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCA3_O1                   Fld(1, 3) //[3:3]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCA4_O1                   Fld(1, 4) //[4:4]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCA5_O1                   Fld(1, 5) //[5:5]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCA6_O1                   Fld(1, 6) //[6:6]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCA7_O1                   Fld(1, 7) //[7:7]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCA8_O1                   Fld(1, 8) //[8:8]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCA9_O1                   Fld(1, 9) //[9:9]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE0_O1                  Fld(1, 10) //[10:10]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE1_O1                  Fld(1, 11) //[11:11]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE2_O1                  Fld(1, 12) //[12:12]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCS0_O1                   Fld(1, 13) //[13:13]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCS1_O1                   Fld(1, 14) //[14:14]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCS2_O1                   Fld(1, 15) //[15:15]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCS1_O1_B1                Fld(1, 16) //[16:16]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE0_O1_B1               Fld(1, 17) //[17:17]
+    #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE1_O1_B1               Fld(1, 18) //[18:18]
+
+#define DDRPHY_REG_MISC_PHY_RGS_DQ                             (DDRPHY_NAO_BASE_ADDRESS + 0x0190)
+    #define MISC_PHY_RGS_DQ_RGS_ARDQ_OFFSET_FLAG_B0            Fld(8, 0) //[7:0]
+    #define MISC_PHY_RGS_DQ_RGS_ARDQM0_OFFSET_FLAG_B0          Fld(1, 8) //[8:8]
+    #define MISC_PHY_RGS_DQ_RGS_RX_ARDQS0_RDY_EYE_B0           Fld(1, 9) //[9:9]
+    #define MISC_PHY_RGS_DQ_APB_ARB_M_DEBUG                    Fld(2, 12) //[13:12]
+    #define MISC_PHY_RGS_DQ_SRAM_ARB_M_DEBUG                   Fld(2, 14) //[15:14]
+    #define MISC_PHY_RGS_DQ_RGS_ARDQ_OFFSET_FLAG_B1            Fld(8, 16) //[23:16]
+    #define MISC_PHY_RGS_DQ_RGS_ARDQM0_OFFSET_FLAG_B1          Fld(1, 24) //[24:24]
+    #define MISC_PHY_RGS_DQ_RGS_RX_ARDQS0_RDY_EYE_B1           Fld(1, 25) //[25:25]
+    #define MISC_PHY_RGS_DQ_DA_RPHYPLLGP_CK_SEL                Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_PHY_RGS_CMD                            (DDRPHY_NAO_BASE_ADDRESS + 0x0194)
+    #define MISC_PHY_RGS_CMD_RGS_ARCA0_OFFSET_FLAG             Fld(1, 0) //[0:0]
+    #define MISC_PHY_RGS_CMD_RGS_ARCA1_OFFSET_FLAG             Fld(1, 1) //[1:1]
+    #define MISC_PHY_RGS_CMD_RGS_ARCA2_OFFSET_FLAG             Fld(1, 2) //[2:2]
+    #define MISC_PHY_RGS_CMD_RGS_ARCA3_OFFSET_FLAG             Fld(1, 3) //[3:3]
+    #define MISC_PHY_RGS_CMD_RGS_ARCA4_OFFSET_FLAG             Fld(1, 4) //[4:4]
+    #define MISC_PHY_RGS_CMD_RGS_ARCA5_OFFSET_FLAG             Fld(1, 5) //[5:5]
+    #define MISC_PHY_RGS_CMD_RGS_ARCA6_OFFSET_FLAG             Fld(1, 6) //[6:6]
+    #define MISC_PHY_RGS_CMD_RGS_ARCA7_OFFSET_FLAG             Fld(1, 7) //[7:7]
+    #define MISC_PHY_RGS_CMD_RGS_ARCA8_OFFSET_FLAG             Fld(1, 8) //[8:8]
+    #define MISC_PHY_RGS_CMD_RGS_ARCA9_OFFSET_FLAG             Fld(1, 9) //[9:9]
+    #define MISC_PHY_RGS_CMD_RGS_ARCKE0_OFFSET_FLAG            Fld(1, 10) //[10:10]
+    #define MISC_PHY_RGS_CMD_RGS_ARCKE1_OFFSET_FLAG            Fld(1, 11) //[11:11]
+    #define MISC_PHY_RGS_CMD_RGS_ARCKE2_OFFSET_FLAG            Fld(1, 12) //[12:12]
+    #define MISC_PHY_RGS_CMD_RGS_ARCS0_OFFSET_FLAG             Fld(1, 13) //[13:13]
+    #define MISC_PHY_RGS_CMD_RGS_ARCS1_OFFSET_FLAG             Fld(1, 14) //[14:14]
+    #define MISC_PHY_RGS_CMD_RGS_ARCS2_OFFSET_FLAG             Fld(1, 15) //[15:15]
+    #define MISC_PHY_RGS_CMD_RGS_RX_ARCLK_RDY_EYE              Fld(1, 16) //[16:16]
+    #define MISC_PHY_RGS_CMD_RGS_RIMPCALOUT                    Fld(1, 24) //[24:24]
+
+#define DDRPHY_REG_MISC_PHY_RGS_STBEN_B0                       (DDRPHY_NAO_BASE_ADDRESS + 0x0198)
+    #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQ0_STBEN_B0         Fld(9, 0) //[8:0]
+    #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LEAD_B0   Fld(1, 16) //[16:16]
+    #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LAG_B0    Fld(1, 17) //[17:17]
+    #define MISC_PHY_RGS_STBEN_B0_AD_ARDLL_PD_EN_B0            Fld(1, 18) //[18:18]
+    #define MISC_PHY_RGS_STBEN_B0_AD_ARDLL_MON_B0              Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_PHY_RGS_STBEN_B1                       (DDRPHY_NAO_BASE_ADDRESS + 0x019C)
+    #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQ0_STBEN_B1         Fld(9, 0) //[8:0]
+    #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LEAD_B1   Fld(1, 16) //[16:16]
+    #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LAG_B1    Fld(1, 17) //[17:17]
+    #define MISC_PHY_RGS_STBEN_B1_AD_ARDLL_PD_EN_B1            Fld(1, 18) //[18:18]
+    #define MISC_PHY_RGS_STBEN_B1_AD_ARDLL_MON_B1              Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_PHY_RGS_STBEN_CMD                      (DDRPHY_NAO_BASE_ADDRESS + 0x01A0)
+    #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCA0_STBEN           Fld(9, 0) //[8:0]
+    #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LEAD      Fld(1, 16) //[16:16]
+    #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LAG       Fld(1, 17) //[17:17]
+    #define MISC_PHY_RGS_STBEN_CMD_AD_ARDLL_PD_EN_CA           Fld(1, 18) //[18:18]
+    #define MISC_PHY_RGS_STBEN_CMD_AD_ARDLL_MON_CA             Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_PHY_PICG_MON_S0                        (DDRPHY_NAO_BASE_ADDRESS + 0x01A4)
+    #define MISC_PHY_PICG_MON_S0_PICG_MON_S0                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_PHY_PICG_MON_S1                        (DDRPHY_NAO_BASE_ADDRESS + 0x01A8)
+    #define MISC_PHY_PICG_MON_S1_PICG_MON_S1                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_PHY_PICG_MON_S2                        (DDRPHY_NAO_BASE_ADDRESS + 0x01AC)
+    #define MISC_PHY_PICG_MON_S2_PICG_MON_S2                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_PHY_PICG_MON_S3                        (DDRPHY_NAO_BASE_ADDRESS + 0x01B0)
+    #define MISC_PHY_PICG_MON_S3_PICG_MON_S3                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_PHY_PICG_MON_S4                        (DDRPHY_NAO_BASE_ADDRESS + 0x01B4)
+    #define MISC_PHY_PICG_MON_S4_PICG_MON_S4                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_PHY_PICG_MON_S5                        (DDRPHY_NAO_BASE_ADDRESS + 0x01B8)
+    #define MISC_PHY_PICG_MON_S5_PICG_MON_S5                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_PHY_PICG_MON_S6                        (DDRPHY_NAO_BASE_ADDRESS + 0x01BC)
+    #define MISC_PHY_PICG_MON_S6_PICG_MON_S6                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_PHY_PICG_MON_S7                        (DDRPHY_NAO_BASE_ADDRESS + 0x01C0)
+    #define MISC_PHY_PICG_MON_S7_PICG_MON_S7                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_PHY_PICG_MON_S8                        (DDRPHY_NAO_BASE_ADDRESS + 0x01C4)
+    #define MISC_PHY_PICG_MON_S8_PICG_MON_S8                   Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_MBIST_STATUS                           (DDRPHY_NAO_BASE_ADDRESS + 0x01C8)
+    #define MISC_MBIST_STATUS_MISC_MBIST_PRE_RP_FAIL           Fld(1, 0) //[0:0]
+    #define MISC_MBIST_STATUS_MISC_MBIST_PRE_RP_OK             Fld(1, 1) //[1:1]
+    #define MISC_MBIST_STATUS_MISC_MBIST_PRE_FUSE              Fld(7, 2) //[8:2]
+
+#define DDRPHY_REG_MISC_MBIST_STATUS2                          (DDRPHY_NAO_BASE_ADDRESS + 0x01CC)
+    #define MISC_MBIST_STATUS2_MISC_MBIST_FAIL                 Fld(1, 0) //[0:0]
+    #define MISC_MBIST_STATUS2_MISC_MBIST_DONE                 Fld(1, 1) //[1:1]
+
+#define DDRPHY_REG_MISC_IMPCAL_STATUS1                         (DDRPHY_NAO_BASE_ADDRESS + 0x01D0)
+    #define MISC_IMPCAL_STATUS1_DRVNDQS_SAVE_1                 Fld(5, 0) //[4:0]
+    #define MISC_IMPCAL_STATUS1_DRVPDQS_SAVE_1                 Fld(5, 8) //[12:8]
+    #define MISC_IMPCAL_STATUS1_ODTNDQS_SAVE_1                 Fld(5, 16) //[20:16]
+
+#define DDRPHY_REG_MISC_IMPCAL_STATUS2                         (DDRPHY_NAO_BASE_ADDRESS + 0x01D4)
+    #define MISC_IMPCAL_STATUS2_DRVNDQS_SAVE_2                 Fld(5, 0) //[4:0]
+    #define MISC_IMPCAL_STATUS2_DRVPDQS_SAVE_2                 Fld(5, 8) //[12:8]
+    #define MISC_IMPCAL_STATUS2_ODTNDQS_SAVE_2                 Fld(5, 16) //[20:16]
+
+#define DDRPHY_REG_MISC_IMPCAL_STATUS3                         (DDRPHY_NAO_BASE_ADDRESS + 0x01D8)
+    #define MISC_IMPCAL_STATUS3_DRVNDQ_SAVE_1                  Fld(5, 0) //[4:0]
+    #define MISC_IMPCAL_STATUS3_DRVPDQ_SAVE_1                  Fld(5, 8) //[12:8]
+    #define MISC_IMPCAL_STATUS3_ODTNDQ_SAVE_1                  Fld(5, 16) //[20:16]
+
+#define DDRPHY_REG_MISC_IMPCAL_STATUS4                         (DDRPHY_NAO_BASE_ADDRESS + 0x01DC)
+    #define MISC_IMPCAL_STATUS4_DRVNDQ_SAVE_2                  Fld(5, 0) //[4:0]
+    #define MISC_IMPCAL_STATUS4_DRVPDQ_SAVE_2                  Fld(5, 8) //[12:8]
+    #define MISC_IMPCAL_STATUS4_ODTNDQ_SAVE_2                  Fld(5, 16) //[20:16]
+
+#define DDRPHY_REG_MISC_IMPCAL_STATUS5                         (DDRPHY_NAO_BASE_ADDRESS + 0x01E0)
+    #define MISC_IMPCAL_STATUS5_DRVNWCK_SAVE_1                 Fld(5, 0) //[4:0]
+    #define MISC_IMPCAL_STATUS5_DRVPWCK_SAVE_1                 Fld(5, 8) //[12:8]
+    #define MISC_IMPCAL_STATUS5_DRVNWCK_SAVE_2                 Fld(5, 16) //[20:16]
+    #define MISC_IMPCAL_STATUS5_DRVPWCK_SAVE_2                 Fld(5, 24) //[28:24]
+
+#define DDRPHY_REG_MISC_IMPCAL_STATUS6                         (DDRPHY_NAO_BASE_ADDRESS + 0x01E4)
+    #define MISC_IMPCAL_STATUS6_DRVNCS_SAVE_1                  Fld(5, 0) //[4:0]
+    #define MISC_IMPCAL_STATUS6_DRVPCS_SAVE_1                  Fld(5, 8) //[12:8]
+
+#define DDRPHY_REG_MISC_IMPCAL_STATUS7                         (DDRPHY_NAO_BASE_ADDRESS + 0x01E8)
+    #define MISC_IMPCAL_STATUS7_DRVNCMD_SAVE_1                 Fld(5, 0) //[4:0]
+    #define MISC_IMPCAL_STATUS7_DRVPCMD_SAVE_1                 Fld(5, 8) //[12:8]
+    #define MISC_IMPCAL_STATUS7_ODTNCMD_SAVE_1                 Fld(5, 16) //[20:16]
+
+#define DDRPHY_REG_MISC_IMPCAL_STATUS8                         (DDRPHY_NAO_BASE_ADDRESS + 0x01EC)
+    #define MISC_IMPCAL_STATUS8_DRVNCMD_SAVE_2                 Fld(5, 0) //[4:0]
+    #define MISC_IMPCAL_STATUS8_DRVPCMD_SAVE_2                 Fld(5, 8) //[12:8]
+    #define MISC_IMPCAL_STATUS8_ODTNCMD_SAVE_2                 Fld(5, 16) //[20:16]
+
+#define DDRPHY_REG_MISC_IMPCAL_STATUS9                         (DDRPHY_NAO_BASE_ADDRESS + 0x01F4)
+    #define MISC_IMPCAL_STATUS9_IMPCAL_N_ERROR                 Fld(1, 0) //[0:0]
+    #define MISC_IMPCAL_STATUS9_IMPCAL_P_ERROR                 Fld(1, 1) //[1:1]
+    #define MISC_IMPCAL_STATUS9_DRVNDQC_SAVE_1                 Fld(5, 10) //[14:10]
+    #define MISC_IMPCAL_STATUS9_DRVPDQC_SAVE_1                 Fld(5, 15) //[19:15]
+    #define MISC_IMPCAL_STATUS9_DRVNDQC_SAVE_2                 Fld(5, 20) //[24:20]
+    #define MISC_IMPCAL_STATUS9_DRVPDQC_SAVE_2                 Fld(5, 25) //[29:25]
+
+#define DDRPHY_REG_MISC_STA_TOGLB0                             (DDRPHY_NAO_BASE_ADDRESS + 0x01F8)
+    #define MISC_STA_TOGLB0_STA_TOGLB_DONE                     Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_STA_TOGLB1                             (DDRPHY_NAO_BASE_ADDRESS + 0x01FC)
+    #define MISC_STA_TOGLB1_STA_TOGLB_FAIL                     Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_STA_EXTLB_DBG0                         (DDRPHY_NAO_BASE_ADDRESS + 0x0214)
+    #define MISC_STA_EXTLB_DBG0_STA_EXTLB_DVS_LEAD_0TO1        Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_STA_EXTLB_DBG1                         (DDRPHY_NAO_BASE_ADDRESS + 0x0218)
+    #define MISC_STA_EXTLB_DBG1_STA_EXTLB_DVS_LEAD_1TO0        Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_STA_EXTLB_DBG2                         (DDRPHY_NAO_BASE_ADDRESS + 0x021C)
+    #define MISC_STA_EXTLB_DBG2_STA_EXTLB_DVS_LAG_0TO1         Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_STA_EXTLB_DBG3                         (DDRPHY_NAO_BASE_ADDRESS + 0x0220)
+    #define MISC_STA_EXTLB_DBG3_STA_EXTLB_DVS_LAG_1TO0         Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DUTY_TOGGLE_CNT                        (DDRPHY_NAO_BASE_ADDRESS + 0x0224)
+    #define MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT                    Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DUTY_DQS0_ERR_CNT                      (DDRPHY_NAO_BASE_ADDRESS + 0x0228)
+    #define MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DUTY_DQ_ERR_CNT0                       (DDRPHY_NAO_BASE_ADDRESS + 0x022C)
+    #define MISC_DUTY_DQ_ERR_CNT0_DQ_ERR_CNT0                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DUTY_DQS1_ERR_CNT                      (DDRPHY_NAO_BASE_ADDRESS + 0x0230)
+    #define MISC_DUTY_DQS1_ERR_CNT_DQS1_ERR_CNT                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DUTY_DQ_ERR_CNT1                       (DDRPHY_NAO_BASE_ADDRESS + 0x0234)
+    #define MISC_DUTY_DQ_ERR_CNT1_DQ_ERR_CNT1                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DUTY_DQS2_ERR_CNT                      (DDRPHY_NAO_BASE_ADDRESS + 0x0238)
+    #define MISC_DUTY_DQS2_ERR_CNT_DQS2_ERR_CNT                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DUTY_DQ_ERR_CNT2                       (DDRPHY_NAO_BASE_ADDRESS + 0x023C)
+    #define MISC_DUTY_DQ_ERR_CNT2_DQ_ERR_CNT2                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DUTY_DQS3_ERR_CNT                      (DDRPHY_NAO_BASE_ADDRESS + 0x0240)
+    #define MISC_DUTY_DQS3_ERR_CNT_DQS3_ERR_CNT                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DUTY_DQ_ERR_CNT3                       (DDRPHY_NAO_BASE_ADDRESS + 0x0244)
+    #define MISC_DUTY_DQ_ERR_CNT3_DQ_ERR_CNT3                  Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_JMETER_ST0                             (DDRPHY_NAO_BASE_ADDRESS + 0x0248)
+    #define MISC_JMETER_ST0_JMTR_DONE                          Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_JMETER_ST1                             (DDRPHY_NAO_BASE_ADDRESS + 0x024C)
+    #define MISC_JMETER_ST1_ZEROS_CNT                          Fld(16, 0) //[15:0]
+    #define MISC_JMETER_ST1_ONES_CNT                           Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_MISC_EMI_LPBK0                              (DDRPHY_NAO_BASE_ADDRESS + 0x0250)
+    #define MISC_EMI_LPBK0_RDATA_DQ0_B0                        Fld(16, 0) //[15:0]
+    #define MISC_EMI_LPBK0_RDATA_DQ1_B0                        Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_MISC_EMI_LPBK1                              (DDRPHY_NAO_BASE_ADDRESS + 0x0254)
+    #define MISC_EMI_LPBK1_RDATA_DQ2_B0                        Fld(16, 0) //[15:0]
+    #define MISC_EMI_LPBK1_RDATA_DQ3_B0                        Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_MISC_EMI_LPBK2                              (DDRPHY_NAO_BASE_ADDRESS + 0x0258)
+    #define MISC_EMI_LPBK2_RDATA_DQ4_B0                        Fld(16, 0) //[15:0]
+    #define MISC_EMI_LPBK2_RDATA_DQ5_B0                        Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_MISC_EMI_LPBK3                              (DDRPHY_NAO_BASE_ADDRESS + 0x025C)
+    #define MISC_EMI_LPBK3_RDATA_DQ6_B0                        Fld(16, 0) //[15:0]
+    #define MISC_EMI_LPBK3_RDATA_DQ7_B0                        Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_MISC_EMI_LPBK4                              (DDRPHY_NAO_BASE_ADDRESS + 0x0260)
+    #define MISC_EMI_LPBK4_RDATA_DQ0_B1                        Fld(16, 0) //[15:0]
+    #define MISC_EMI_LPBK4_RDATA_DQ1_B1                        Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_MISC_EMI_LPBK5                              (DDRPHY_NAO_BASE_ADDRESS + 0x0264)
+    #define MISC_EMI_LPBK5_RDATA_DQ2_B1                        Fld(16, 0) //[15:0]
+    #define MISC_EMI_LPBK5_RDATA_DQ3_B1                        Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_MISC_EMI_LPBK6                              (DDRPHY_NAO_BASE_ADDRESS + 0x0268)
+    #define MISC_EMI_LPBK6_RDATA_DQ4_B1                        Fld(16, 0) //[15:0]
+    #define MISC_EMI_LPBK6_RDATA_DQ5_B1                        Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_MISC_EMI_LPBK7                              (DDRPHY_NAO_BASE_ADDRESS + 0x026C)
+    #define MISC_EMI_LPBK7_RDATA_DQ6_B1                        Fld(16, 0) //[15:0]
+    #define MISC_EMI_LPBK7_RDATA_DQ7_B1                        Fld(16, 16) //[31:16]
+
+#define DDRPHY_REG_MISC_FT_STATUS0                             (DDRPHY_NAO_BASE_ADDRESS + 0x0270)
+    #define MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B1            Fld(8, 0) //[7:0]
+    #define MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LEAD_B1           Fld(8, 8) //[15:8]
+    #define MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B0            Fld(8, 16) //[23:16]
+    #define MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LEAD_B0           Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_FT_STATUS1                             (DDRPHY_NAO_BASE_ADDRESS + 0x0274)
+    #define MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LAG_B1            Fld(8, 0) //[7:0]
+    #define MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LEAD_B1           Fld(8, 8) //[15:8]
+    #define MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LAG_B0            Fld(8, 16) //[23:16]
+    #define MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LEAD_B0           Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_FT_STATUS2                             (DDRPHY_NAO_BASE_ADDRESS + 0x0278)
+    #define MISC_FT_STATUS2_AD_RRESETB_O                       Fld(1, 0) //[0:0]
+
+#define DDRPHY_REG_MISC_FT_STATUS3                             (DDRPHY_NAO_BASE_ADDRESS + 0x027C)
+    #define MISC_FT_STATUS3_AD_RX_ARCA0_DVS_R_LAG              Fld(1, 0) //[0:0]
+    #define MISC_FT_STATUS3_AD_RX_ARCA1_DVS_R_LAG              Fld(1, 1) //[1:1]
+    #define MISC_FT_STATUS3_AD_RX_ARCA2_DVS_R_LAG              Fld(1, 2) //[2:2]
+    #define MISC_FT_STATUS3_AD_RX_ARCA3_DVS_R_LAG              Fld(1, 3) //[3:3]
+    #define MISC_FT_STATUS3_AD_RX_ARCA4_DVS_R_LAG              Fld(1, 4) //[4:4]
+    #define MISC_FT_STATUS3_AD_RX_ARCA5_DVS_R_LAG              Fld(1, 5) //[5:5]
+    #define MISC_FT_STATUS3_AD_RX_ARCKE0_DVS_R_LAG             Fld(1, 6) //[6:6]
+    #define MISC_FT_STATUS3_AD_RX_ARCKE1_DVS_R_LAG             Fld(1, 7) //[7:7]
+    #define MISC_FT_STATUS3_AD_RX_ARCS0_DVS_R_LAG              Fld(1, 8) //[8:8]
+    #define MISC_FT_STATUS3_AD_RX_ARCS1_DVS_R_LAG              Fld(1, 9) //[9:9]
+    #define MISC_FT_STATUS3_AD_RX_ARCA0_DVS_R_LEAD             Fld(1, 16) //[16:16]
+    #define MISC_FT_STATUS3_AD_RX_ARCA1_DVS_R_LEAD             Fld(1, 17) //[17:17]
+    #define MISC_FT_STATUS3_AD_RX_ARCA2_DVS_R_LEAD             Fld(1, 18) //[18:18]
+    #define MISC_FT_STATUS3_AD_RX_ARCA3_DVS_R_LEAD             Fld(1, 19) //[19:19]
+    #define MISC_FT_STATUS3_AD_RX_ARCA4_DVS_R_LEAD             Fld(1, 20) //[20:20]
+    #define MISC_FT_STATUS3_AD_RX_ARCA5_DVS_R_LEAD             Fld(1, 21) //[21:21]
+    #define MISC_FT_STATUS3_AD_RX_ARCKE0_DVS_R_LEAD            Fld(1, 22) //[22:22]
+    #define MISC_FT_STATUS3_AD_RX_ARCKE1_DVS_R_LEAD            Fld(1, 23) //[23:23]
+    #define MISC_FT_STATUS3_AD_RX_ARCS0_DVS_R_LEAD             Fld(1, 24) //[24:24]
+    #define MISC_FT_STATUS3_AD_RX_ARCS1_DVS_R_LEAD             Fld(1, 25) //[25:25]
+
+#define DDRPHY_REG_MISC_FT_STATUS4                             (DDRPHY_NAO_BASE_ADDRESS + 0x0280)
+    #define MISC_FT_STATUS4_AD_RX_ARCA0_DVS_F_LAG              Fld(1, 0) //[0:0]
+    #define MISC_FT_STATUS4_AD_RX_ARCA1_DVS_F_LAG              Fld(1, 1) //[1:1]
+    #define MISC_FT_STATUS4_AD_RX_ARCA2_DVS_F_LAG              Fld(1, 2) //[2:2]
+    #define MISC_FT_STATUS4_AD_RX_ARCA3_DVS_F_LAG              Fld(1, 3) //[3:3]
+    #define MISC_FT_STATUS4_AD_RX_ARCA4_DVS_F_LAG              Fld(1, 4) //[4:4]
+    #define MISC_FT_STATUS4_AD_RX_ARCA5_DVS_F_LAG              Fld(1, 5) //[5:5]
+    #define MISC_FT_STATUS4_AD_RX_ARCKE0_DVS_F_LAG             Fld(1, 6) //[6:6]
+    #define MISC_FT_STATUS4_AD_RX_ARCKE1_DVS_F_LAG             Fld(1, 7) //[7:7]
+    #define MISC_FT_STATUS4_AD_RX_ARCS0_DVS_F_LAG              Fld(1, 8) //[8:8]
+    #define MISC_FT_STATUS4_AD_RX_ARCS1_DVS_F_LAG              Fld(1, 9) //[9:9]
+    #define MISC_FT_STATUS4_AD_RX_ARCA0_DVS_F_LEAD             Fld(1, 16) //[16:16]
+    #define MISC_FT_STATUS4_AD_RX_ARCA1_DVS_F_LEAD             Fld(1, 17) //[17:17]
+    #define MISC_FT_STATUS4_AD_RX_ARCA2_DVS_F_LEAD             Fld(1, 18) //[18:18]
+    #define MISC_FT_STATUS4_AD_RX_ARCA3_DVS_F_LEAD             Fld(1, 19) //[19:19]
+    #define MISC_FT_STATUS4_AD_RX_ARCA4_DVS_F_LEAD             Fld(1, 20) //[20:20]
+    #define MISC_FT_STATUS4_AD_RX_ARCA5_DVS_F_LEAD             Fld(1, 21) //[21:21]
+    #define MISC_FT_STATUS4_AD_RX_ARCKE0_DVS_F_LEAD            Fld(1, 22) //[22:22]
+    #define MISC_FT_STATUS4_AD_RX_ARCKE1_DVS_F_LEAD            Fld(1, 23) //[23:23]
+    #define MISC_FT_STATUS4_AD_RX_ARCS0_DVS_F_LEAD             Fld(1, 24) //[24:24]
+    #define MISC_FT_STATUS4_AD_RX_ARCS1_DVS_F_LEAD             Fld(1, 25) //[25:25]
+
+#define DDRPHY_REG_MISC_STA_TOGLB2                             (DDRPHY_NAO_BASE_ADDRESS + 0x0284)
+    #define MISC_STA_TOGLB2_STA_TOGLB_PUHI_TIMEOUT             Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_STA_TOGLB3                             (DDRPHY_NAO_BASE_ADDRESS + 0x0288)
+    #define MISC_STA_TOGLB3_STA_TOGLB_PULO_TIMEOUT             Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_STA_EXTLB3                             (DDRPHY_NAO_BASE_ADDRESS + 0x028C)
+    #define MISC_STA_EXTLB3_STA_EXTLB_RISING_FAIL              Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_STA_EXTLB4                             (DDRPHY_NAO_BASE_ADDRESS + 0x0290)
+    #define MISC_STA_EXTLB4_STA_EXTLB_FALLING_FAIL             Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_STA_EXTLB5                             (DDRPHY_NAO_BASE_ADDRESS + 0x0294)
+    #define MISC_STA_EXTLB5_STA_EXTLB_DBG_INFO2                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DEBUG_APHY_RX_CTL                           (DDRPHY_NAO_BASE_ADDRESS + 0x0400)
+    #define DEBUG_APHY_RX_CTL_DEBUG_STATUS_APHY_RX_CTL         Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_GATING_ERR_INFOR                            (DDRPHY_NAO_BASE_ADDRESS + 0x0410)
+    #define GATING_ERR_INFOR_STB_GATING_ERR                    Fld(1, 0) //[0:0]
+    #define GATING_ERR_INFOR_STBUPD_STOP                       Fld(1, 1) //[1:1]
+    #define GATING_ERR_INFOR_R_OTHER_SHU_GP_GATING_ERR         Fld(2, 4) //[5:4]
+    #define GATING_ERR_INFOR_R_MPDIV_SHU_GP_GATING_ERR         Fld(3, 8) //[10:8]
+    #define GATING_ERR_INFOR_GATING_ERR_INF_STATUS             Fld(4, 16) //[19:16]
+    #define GATING_ERR_INFOR_GATING_ERR_PRE_SHU_ST             Fld(4, 20) //[23:20]
+    #define GATING_ERR_INFOR_GATING_ERR_CUR_SHU_ST             Fld(4, 24) //[27:24]
+
+#define DDRPHY_REG_DEBUG_DQSIEN_B0                             (DDRPHY_NAO_BASE_ADDRESS + 0x0414)
+    #define DEBUG_DQSIEN_B0_DQSIEN_PICG_HEAD_ERR_FLAG_B0_RK0   Fld(1, 0) //[0:0]
+    #define DEBUG_DQSIEN_B0_STB_CNT_SHU_ST_ERR_FLAG_B0_RK0     Fld(1, 1) //[1:1]
+    #define DEBUG_DQSIEN_B0_DQSIEN_PICG_HEAD_ERR_FLAG_B0_RK1   Fld(1, 16) //[16:16]
+    #define DEBUG_DQSIEN_B0_STB_CNT_SHU_ST_ERR_FLAG_B0_RK1     Fld(1, 17) //[17:17]
+
+#define DDRPHY_REG_DEBUG_DQSIEN_B1                             (DDRPHY_NAO_BASE_ADDRESS + 0x0418)
+    #define DEBUG_DQSIEN_B1_DQSIEN_PICG_HEAD_ERR_FLAG_B1_RK0   Fld(1, 0) //[0:0]
+    #define DEBUG_DQSIEN_B1_STB_CNT_SHU_ST_ERR_FLAG_B1_RK0     Fld(1, 1) //[1:1]
+    #define DEBUG_DQSIEN_B1_DQSIEN_PICG_HEAD_ERR_FLAG_B1_RK1   Fld(1, 16) //[16:16]
+    #define DEBUG_DQSIEN_B1_STB_CNT_SHU_ST_ERR_FLAG_B1_RK1     Fld(1, 17) //[17:17]
+
+#define DDRPHY_REG_DEBUG_DQSIEN_CA                             (DDRPHY_NAO_BASE_ADDRESS + 0x041C)
+    #define DEBUG_DQSIEN_CA_DQSIEN_PICG_HEAD_ERR_FLAG_CA_RK0   Fld(1, 0) //[0:0]
+    #define DEBUG_DQSIEN_CA_STB_CNT_SHU_ST_ERR_FLAG_CA_RK0     Fld(1, 1) //[1:1]
+    #define DEBUG_DQSIEN_CA_DQSIEN_PICG_HEAD_ERR_FLAG_CA_RK1   Fld(1, 16) //[16:16]
+    #define DEBUG_DQSIEN_CA_STB_CNT_SHU_ST_ERR_FLAG_CA_RK1     Fld(1, 17) //[17:17]
+
+#define DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0                 (DDRPHY_NAO_BASE_ADDRESS + 0x0420)
+    #define GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_PI_DLY_RK0     Fld(7, 0) //[6:0]
+    #define GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_UI_P0_DLY_RK0  Fld(8, 16) //[23:16]
+    #define GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_UI_P1_DLY_RK0  Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0                 (DDRPHY_NAO_BASE_ADDRESS + 0x0424)
+    #define GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_PI_DLY_RK0     Fld(7, 0) //[6:0]
+    #define GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P0_DLY_RK0  Fld(8, 16) //[23:16]
+    #define GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P1_DLY_RK0  Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_GATING_ERR_LATCH_DLY_CA_RK0                 (DDRPHY_NAO_BASE_ADDRESS + 0x0428)
+    #define GATING_ERR_LATCH_DLY_CA_RK0_DQSIEN2_PI_DLY_RK0     Fld(7, 0) //[6:0]
+    #define GATING_ERR_LATCH_DLY_CA_RK0_DQSIEN2_UI_P0_DLY_RK0  Fld(8, 16) //[23:16]
+    #define GATING_ERR_LATCH_DLY_CA_RK0_DQSIEN2_UI_P1_DLY_RK0  Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK1                 (DDRPHY_NAO_BASE_ADDRESS + 0x0430)
+    #define GATING_ERR_LATCH_DLY_B0_RK1_DQSIEN0_PI_DLY_RK1     Fld(7, 0) //[6:0]
+    #define GATING_ERR_LATCH_DLY_B0_RK1_DQSIEN0_UI_P0_DLY_RK1  Fld(8, 16) //[23:16]
+    #define GATING_ERR_LATCH_DLY_B0_RK1_DQSIEN0_UI_P1_DLY_RK1  Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK1                 (DDRPHY_NAO_BASE_ADDRESS + 0x0434)
+    #define GATING_ERR_LATCH_DLY_B1_RK1_DQSIEN1_PI_DLY_RK1     Fld(7, 0) //[6:0]
+    #define GATING_ERR_LATCH_DLY_B1_RK1_DQSIEN1_UI_P0_DLY_RK1  Fld(8, 16) //[23:16]
+    #define GATING_ERR_LATCH_DLY_B1_RK1_DQSIEN1_UI_P1_DLY_RK1  Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_GATING_ERR_LATCH_DLY_CA_RK1                 (DDRPHY_NAO_BASE_ADDRESS + 0x0438)
+    #define GATING_ERR_LATCH_DLY_CA_RK1_DQSIEN2_PI_DLY_RK1     Fld(7, 0) //[6:0]
+    #define GATING_ERR_LATCH_DLY_CA_RK1_DQSIEN2_UI_P0_DLY_RK1  Fld(8, 16) //[23:16]
+    #define GATING_ERR_LATCH_DLY_CA_RK1_DQSIEN2_UI_P1_DLY_RK1  Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_DEBUG_RODT_CTL                              (DDRPHY_NAO_BASE_ADDRESS + 0x0440)
+    #define DEBUG_RODT_CTL_DEBUG_STATUS_RODTCTL                Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_CAL_DQSG_CNT_B0                             (DDRPHY_NAO_BASE_ADDRESS + 0x0500)
+    #define CAL_DQSG_CNT_B0_DQS_B0_F_GATING_COUNTER            Fld(8, 0) //[7:0]
+    #define CAL_DQSG_CNT_B0_DQS_B0_R_GATING_COUNTER            Fld(8, 8) //[15:8]
+
+#define DDRPHY_REG_CAL_DQSG_CNT_B1                             (DDRPHY_NAO_BASE_ADDRESS + 0x0504)
+    #define CAL_DQSG_CNT_B1_DQS_B1_F_GATING_COUNTER            Fld(8, 0) //[7:0]
+    #define CAL_DQSG_CNT_B1_DQS_B1_R_GATING_COUNTER            Fld(8, 8) //[15:8]
+
+#define DDRPHY_REG_CAL_DQSG_CNT_CA                             (DDRPHY_NAO_BASE_ADDRESS + 0x0508)
+    #define CAL_DQSG_CNT_CA_DQS_CA_F_GATING_COUNTER            Fld(8, 0) //[7:0]
+    #define CAL_DQSG_CNT_CA_DQS_CA_R_GATING_COUNTER            Fld(8, 8) //[15:8]
+
+#define DDRPHY_REG_DVFS_STATUS                                 (DDRPHY_NAO_BASE_ADDRESS + 0x050C)
+    #define DVFS_STATUS_CUT_PHY_ST_SHU                         Fld(8, 0) //[7:0]
+    #define DVFS_STATUS_PLL_SEL                                Fld(1, 8) //[8:8]
+    #define DVFS_STATUS_MPDIV_SHU_GP                           Fld(3, 12) //[14:12]
+    #define DVFS_STATUS_OTHER_SHU_GP                           Fld(2, 16) //[17:16]
+    #define DVFS_STATUS_PICG_SHUFFLE                           Fld(1, 20) //[20:20]
+    #define DVFS_STATUS_SHUFFLE_PHY_STATE_START                Fld(1, 21) //[21:21]
+    #define DVFS_STATUS_SHUFFLE_PHY_STATE_DONE                 Fld(1, 22) //[22:22]
+    #define DVFS_STATUS_SHUFFLE_PERIOD                         Fld(1, 23) //[23:23]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS0                            (DDRPHY_NAO_BASE_ADDRESS + 0x0510)
+    #define RX_AUTOK_STATUS0_RO_RX_CAL_FAIL                    Fld(1, 0) //[0:0]
+    #define RX_AUTOK_STATUS0_RO_RX_CAL_PASS                    Fld(1, 1) //[1:1]
+    #define RX_AUTOK_STATUS0_RO_RX_CAL_DONE                    Fld(1, 2) //[2:2]
+    #define RX_AUTOK_STATUS0_RO_RX_CAL_OUT_WIN1_LEN_ARDQX      Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS0_RO_RX_CAL_OUT_WIN1_BEGIN_ARDQX    Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS1                            (DDRPHY_NAO_BASE_ADDRESS + 0x0514)
+    #define RX_AUTOK_STATUS1_RO_RX_CAL_OUT_WIN2_LEN_ARDQX      Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS1_RO_RX_CAL_OUT_WIN2_BEGIN_ARDQX    Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS2                            (DDRPHY_NAO_BASE_ADDRESS + 0x0518)
+    #define RX_AUTOK_STATUS2_RO_RX_CAL_OUT_WIN3_LEN_ARDQX      Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS2_RO_RX_CAL_OUT_WIN3_BEGIN_ARDQX    Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS3                            (DDRPHY_NAO_BASE_ADDRESS + 0x051C)
+    #define RX_AUTOK_STATUS3_RO_RX_CAL_OUT_WIN4_LEN_ARDQX      Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS3_RO_RX_CAL_OUT_WIN4_BEGIN_ARDQX    Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS4                            (DDRPHY_NAO_BASE_ADDRESS + 0x0520)
+    #define RX_AUTOK_STATUS4_RO_RX_CAL_OUT_WIN5_LEN_ARDQX      Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS4_RO_RX_CAL_OUT_WIN5_BEGIN_ARDQX    Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS5                            (DDRPHY_NAO_BASE_ADDRESS + 0x0524)
+    #define RX_AUTOK_STATUS5_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ0   Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS5_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ0 Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS6                            (DDRPHY_NAO_BASE_ADDRESS + 0x0528)
+    #define RX_AUTOK_STATUS6_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ1   Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS6_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ1 Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS7                            (DDRPHY_NAO_BASE_ADDRESS + 0x052C)
+    #define RX_AUTOK_STATUS7_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ2   Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS7_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ2 Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS8                            (DDRPHY_NAO_BASE_ADDRESS + 0x0530)
+    #define RX_AUTOK_STATUS8_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ3   Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS8_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ3 Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS9                            (DDRPHY_NAO_BASE_ADDRESS + 0x0534)
+    #define RX_AUTOK_STATUS9_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ4   Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS9_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ4 Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS10                           (DDRPHY_NAO_BASE_ADDRESS + 0x0538)
+    #define RX_AUTOK_STATUS10_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ5  Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS10_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ5 Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS11                           (DDRPHY_NAO_BASE_ADDRESS + 0x053C)
+    #define RX_AUTOK_STATUS11_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ6  Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS11_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ6 Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS12                           (DDRPHY_NAO_BASE_ADDRESS + 0x0540)
+    #define RX_AUTOK_STATUS12_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ7  Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS12_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ7 Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS13                           (DDRPHY_NAO_BASE_ADDRESS + 0x0544)
+    #define RX_AUTOK_STATUS13_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ8  Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS13_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ8 Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS14                           (DDRPHY_NAO_BASE_ADDRESS + 0x0548)
+    #define RX_AUTOK_STATUS14_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ9  Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS14_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ9 Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS15                           (DDRPHY_NAO_BASE_ADDRESS + 0x054C)
+    #define RX_AUTOK_STATUS15_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ10 Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS15_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ10 Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS16                           (DDRPHY_NAO_BASE_ADDRESS + 0x0550)
+    #define RX_AUTOK_STATUS16_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ11 Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS16_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ11 Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS17                           (DDRPHY_NAO_BASE_ADDRESS + 0x0554)
+    #define RX_AUTOK_STATUS17_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ12 Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS17_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ12 Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS18                           (DDRPHY_NAO_BASE_ADDRESS + 0x0558)
+    #define RX_AUTOK_STATUS18_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ13 Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS18_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ13 Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS19                           (DDRPHY_NAO_BASE_ADDRESS + 0x055C)
+    #define RX_AUTOK_STATUS19_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ14 Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS19_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ14 Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_RX_AUTOK_STATUS20                           (DDRPHY_NAO_BASE_ADDRESS + 0x0560)
+    #define RX_AUTOK_STATUS20_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ15 Fld(10, 4) //[13:4]
+    #define RX_AUTOK_STATUS20_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ15 Fld(11, 16) //[26:16]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0                 (DDRPHY_NAO_BASE_ADDRESS + 0x0600)
+    #define DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C__PI_B0_RK0 Fld(7, 0) //[6:0]
+    #define DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C__UI_B0_RK0 Fld(4, 8) //[11:8]
+    #define DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C_MCK_B0_RK0 Fld(4, 12) //[15:12]
+    #define DQSIEN_AUTOK_B0_RK0_STATUS0_AUTOK_DONE_B0_RK0      Fld(1, 16) //[16:16]
+    #define DQSIEN_AUTOK_B0_RK0_STATUS0_AUTOK_ERR_B0_RK0       Fld(1, 17) //[17:17]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1                 (DDRPHY_NAO_BASE_ADDRESS + 0x0604)
+    #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R__PI_B0_RK0 Fld(7, 0) //[6:0]
+    #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R__UI_B0_RK0 Fld(4, 8) //[11:8]
+    #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R_MCK_B0_RK0 Fld(4, 12) //[15:12]
+    #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L__PI_B0_RK0 Fld(7, 16) //[22:16]
+    #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L__UI_B0_RK0 Fld(4, 24) //[27:24]
+    #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L_MCK_B0_RK0 Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS0             (DDRPHY_NAO_BASE_ADDRESS + 0x0608)
+    #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS0_DBG_GATING_STATUS_0_B0_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS1             (DDRPHY_NAO_BASE_ADDRESS + 0x060C)
+    #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS1_DBG_GATING_STATUS_1_B0_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS2             (DDRPHY_NAO_BASE_ADDRESS + 0x0610)
+    #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS2_DBG_GATING_STATUS_2_B0_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS3             (DDRPHY_NAO_BASE_ADDRESS + 0x0614)
+    #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS3_DBG_GATING_STATUS_3_B0_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS4             (DDRPHY_NAO_BASE_ADDRESS + 0x0618)
+    #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS4_DBG_GATING_STATUS_4_B0_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS5             (DDRPHY_NAO_BASE_ADDRESS + 0x061C)
+    #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS5_DBG_GATING_STATUS_5_B0_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_STATUS0                 (DDRPHY_NAO_BASE_ADDRESS + 0x0620)
+    #define DQSIEN_AUTOK_B0_RK1_STATUS0_DQSIEN_AUTOK_C__PI_B0_RK1 Fld(7, 0) //[6:0]
+    #define DQSIEN_AUTOK_B0_RK1_STATUS0_DQSIEN_AUTOK_C__UI_B0_RK1 Fld(4, 8) //[11:8]
+    #define DQSIEN_AUTOK_B0_RK1_STATUS0_DQSIEN_AUTOK_C_MCK_B0_RK1 Fld(4, 12) //[15:12]
+    #define DQSIEN_AUTOK_B0_RK1_STATUS0_AUTOK_DONE_B0_RK1      Fld(1, 16) //[16:16]
+    #define DQSIEN_AUTOK_B0_RK1_STATUS0_AUTOK_ERR_B0_RK1       Fld(1, 17) //[17:17]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_STATUS1                 (DDRPHY_NAO_BASE_ADDRESS + 0x0624)
+    #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_R__PI_B0_RK1 Fld(7, 0) //[6:0]
+    #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_R__UI_B0_RK1 Fld(4, 8) //[11:8]
+    #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_R_MCK_B0_RK1 Fld(4, 12) //[15:12]
+    #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_L__PI_B0_RK1 Fld(7, 16) //[22:16]
+    #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_L__UI_B0_RK1 Fld(4, 24) //[27:24]
+    #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_L_MCK_B0_RK1 Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS0             (DDRPHY_NAO_BASE_ADDRESS + 0x0628)
+    #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS0_DBG_GATING_STATUS_0_B0_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS1             (DDRPHY_NAO_BASE_ADDRESS + 0x062C)
+    #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS1_DBG_GATING_STATUS_1_B0_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS2             (DDRPHY_NAO_BASE_ADDRESS + 0x0630)
+    #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS2_DBG_GATING_STATUS_2_B0_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS3             (DDRPHY_NAO_BASE_ADDRESS + 0x0634)
+    #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS3_DBG_GATING_STATUS_3_B0_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS4             (DDRPHY_NAO_BASE_ADDRESS + 0x0638)
+    #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS4_DBG_GATING_STATUS_4_B0_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS5             (DDRPHY_NAO_BASE_ADDRESS + 0x063C)
+    #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS5_DBG_GATING_STATUS_5_B0_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_STATUS0                 (DDRPHY_NAO_BASE_ADDRESS + 0x0640)
+    #define DQSIEN_AUTOK_B1_RK0_STATUS0_DQSIEN_AUTOK_C__PI_B1_RK0 Fld(7, 0) //[6:0]
+    #define DQSIEN_AUTOK_B1_RK0_STATUS0_DQSIEN_AUTOK_C__UI_B1_RK0 Fld(4, 8) //[11:8]
+    #define DQSIEN_AUTOK_B1_RK0_STATUS0_DQSIEN_AUTOK_C_MCK_B1_RK0 Fld(4, 12) //[15:12]
+    #define DQSIEN_AUTOK_B1_RK0_STATUS0_AUTOK_DONE_B1_RK0      Fld(1, 16) //[16:16]
+    #define DQSIEN_AUTOK_B1_RK0_STATUS0_AUTOK_ERR_B1_RK0       Fld(1, 17) //[17:17]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_STATUS1                 (DDRPHY_NAO_BASE_ADDRESS + 0x0644)
+    #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_R__PI_B1_RK0 Fld(7, 0) //[6:0]
+    #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_R__UI_B1_RK0 Fld(4, 8) //[11:8]
+    #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_R_MCK_B1_RK0 Fld(4, 12) //[15:12]
+    #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_L__PI_B1_RK0 Fld(7, 16) //[22:16]
+    #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_L__UI_B1_RK0 Fld(4, 24) //[27:24]
+    #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_L_MCK_B1_RK0 Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS0             (DDRPHY_NAO_BASE_ADDRESS + 0x0648)
+    #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS0_DBG_GATING_STATUS_0_B1_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS1             (DDRPHY_NAO_BASE_ADDRESS + 0x064C)
+    #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS1_DBG_GATING_STATUS_1_B1_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS2             (DDRPHY_NAO_BASE_ADDRESS + 0x0650)
+    #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS2_DBG_GATING_STATUS_2_B1_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS3             (DDRPHY_NAO_BASE_ADDRESS + 0x0654)
+    #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS3_DBG_GATING_STATUS_3_B1_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS4             (DDRPHY_NAO_BASE_ADDRESS + 0x0658)
+    #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS4_DBG_GATING_STATUS_4_B1_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS5             (DDRPHY_NAO_BASE_ADDRESS + 0x065C)
+    #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS5_DBG_GATING_STATUS_5_B1_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_STATUS0                 (DDRPHY_NAO_BASE_ADDRESS + 0x0660)
+    #define DQSIEN_AUTOK_B1_RK1_STATUS0_DQSIEN_AUTOK_C__PI_B1_RK1 Fld(7, 0) //[6:0]
+    #define DQSIEN_AUTOK_B1_RK1_STATUS0_DQSIEN_AUTOK_C__UI_B1_RK1 Fld(4, 8) //[11:8]
+    #define DQSIEN_AUTOK_B1_RK1_STATUS0_DQSIEN_AUTOK_C_MCK_B1_RK1 Fld(4, 12) //[15:12]
+    #define DQSIEN_AUTOK_B1_RK1_STATUS0_AUTOK_DONE_B1_RK1      Fld(1, 16) //[16:16]
+    #define DQSIEN_AUTOK_B1_RK1_STATUS0_AUTOK_ERR_B1_RK1       Fld(1, 17) //[17:17]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_STATUS1                 (DDRPHY_NAO_BASE_ADDRESS + 0x0664)
+    #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_R__PI_B1_RK1 Fld(7, 0) //[6:0]
+    #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_R__UI_B1_RK1 Fld(4, 8) //[11:8]
+    #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_R_MCK_B1_RK1 Fld(4, 12) //[15:12]
+    #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_L__PI_B1_RK1 Fld(7, 16) //[22:16]
+    #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_L__UI_B1_RK1 Fld(4, 24) //[27:24]
+    #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_L_MCK_B1_RK1 Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS0             (DDRPHY_NAO_BASE_ADDRESS + 0x0668)
+    #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS0_DBG_GATING_STATUS_0_B1_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS1             (DDRPHY_NAO_BASE_ADDRESS + 0x066C)
+    #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS1_DBG_GATING_STATUS_1_B1_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS2             (DDRPHY_NAO_BASE_ADDRESS + 0x0670)
+    #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS2_DBG_GATING_STATUS_2_B1_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS3             (DDRPHY_NAO_BASE_ADDRESS + 0x0674)
+    #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS3_DBG_GATING_STATUS_3_B1_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS4             (DDRPHY_NAO_BASE_ADDRESS + 0x0678)
+    #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS4_DBG_GATING_STATUS_4_B1_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS5             (DDRPHY_NAO_BASE_ADDRESS + 0x067C)
+    #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS5_DBG_GATING_STATUS_5_B1_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_STATUS0                 (DDRPHY_NAO_BASE_ADDRESS + 0x0680)
+    #define DQSIEN_AUTOK_CA_RK0_STATUS0_DQSIEN_AUTOK_C__PI_CA_RK0 Fld(7, 0) //[6:0]
+    #define DQSIEN_AUTOK_CA_RK0_STATUS0_DQSIEN_AUTOK_C__UI_CA_RK0 Fld(4, 8) //[11:8]
+    #define DQSIEN_AUTOK_CA_RK0_STATUS0_DQSIEN_AUTOK_C_MCK_CA_RK0 Fld(4, 12) //[15:12]
+    #define DQSIEN_AUTOK_CA_RK0_STATUS0_AUTOK_DONE_CA_RK0      Fld(1, 16) //[16:16]
+    #define DQSIEN_AUTOK_CA_RK0_STATUS0_AUTOK_ERR_CA_RK0       Fld(1, 17) //[17:17]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_STATUS1                 (DDRPHY_NAO_BASE_ADDRESS + 0x0684)
+    #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_R__PI_CA_RK0 Fld(7, 0) //[6:0]
+    #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_R__UI_CA_RK0 Fld(4, 8) //[11:8]
+    #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_R_MCK_CA_RK0 Fld(4, 12) //[15:12]
+    #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_L__PI_CA_RK0 Fld(7, 16) //[22:16]
+    #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_L__UI_CA_RK0 Fld(4, 24) //[27:24]
+    #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_L_MCK_CA_RK0 Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS0             (DDRPHY_NAO_BASE_ADDRESS + 0x0688)
+    #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS0_DBG_GATING_STATUS_0_CA_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS1             (DDRPHY_NAO_BASE_ADDRESS + 0x068C)
+    #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS1_DBG_GATING_STATUS_1_CA_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS2             (DDRPHY_NAO_BASE_ADDRESS + 0x0690)
+    #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS2_DBG_GATING_STATUS_2_CA_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS3             (DDRPHY_NAO_BASE_ADDRESS + 0x0694)
+    #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS3_DBG_GATING_STATUS_3_CA_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS4             (DDRPHY_NAO_BASE_ADDRESS + 0x0698)
+    #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS4_DBG_GATING_STATUS_4_CA_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS5             (DDRPHY_NAO_BASE_ADDRESS + 0x069C)
+    #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS5_DBG_GATING_STATUS_5_CA_RK0 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_STATUS0                 (DDRPHY_NAO_BASE_ADDRESS + 0x0700)
+    #define DQSIEN_AUTOK_CA_RK1_STATUS0_DQSIEN_AUTOK_C__PI_CA_RK1 Fld(7, 0) //[6:0]
+    #define DQSIEN_AUTOK_CA_RK1_STATUS0_DQSIEN_AUTOK_C__UI_CA_RK1 Fld(4, 8) //[11:8]
+    #define DQSIEN_AUTOK_CA_RK1_STATUS0_DQSIEN_AUTOK_C_MCK_CA_RK1 Fld(4, 12) //[15:12]
+    #define DQSIEN_AUTOK_CA_RK1_STATUS0_AUTOK_DONE_CA_RK1      Fld(1, 16) //[16:16]
+    #define DQSIEN_AUTOK_CA_RK1_STATUS0_AUTOK_ERR_CA_RK1       Fld(1, 17) //[17:17]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_STATUS1                 (DDRPHY_NAO_BASE_ADDRESS + 0x0704)
+    #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_R__PI_CA_RK1 Fld(7, 0) //[6:0]
+    #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_R__UI_CA_RK1 Fld(4, 8) //[11:8]
+    #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_R_MCK_CA_RK1 Fld(4, 12) //[15:12]
+    #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_L__PI_CA_RK1 Fld(7, 16) //[22:16]
+    #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_L__UI_CA_RK1 Fld(4, 24) //[27:24]
+    #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_L_MCK_CA_RK1 Fld(4, 28) //[31:28]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS0             (DDRPHY_NAO_BASE_ADDRESS + 0x0708)
+    #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS0_DBG_GATING_STATUS_0_CA_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS1             (DDRPHY_NAO_BASE_ADDRESS + 0x070C)
+    #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS1_DBG_GATING_STATUS_1_CA_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS2             (DDRPHY_NAO_BASE_ADDRESS + 0x0710)
+    #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS2_DBG_GATING_STATUS_2_CA_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS3             (DDRPHY_NAO_BASE_ADDRESS + 0x0714)
+    #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS3_DBG_GATING_STATUS_3_CA_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS4             (DDRPHY_NAO_BASE_ADDRESS + 0x0718)
+    #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS4_DBG_GATING_STATUS_4_CA_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS5             (DDRPHY_NAO_BASE_ADDRESS + 0x071C)
+    #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS5_DBG_GATING_STATUS_5_CA_RK1 Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_DQSIEN_AUTOK_CTRL_STATUS                    (DDRPHY_NAO_BASE_ADDRESS + 0x0720)
+    #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_DONE_RK0     Fld(1, 0) //[0:0]
+    #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_DONE_RK1     Fld(1, 1) //[1:1]
+    #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_DLE_TIMEOUT_ERROR Fld(1, 2) //[2:2]
+    #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_FSM_ST       Fld(3, 4) //[6:4]
+    #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_FSM_CUR_EDGE Fld(1, 8) //[8:8]
+
+#define DDRPHY_REG_AD_DLINE_MON                                (DDRPHY_NAO_BASE_ADDRESS + 0x0724)
+    #define AD_DLINE_MON_AD_RPLLGP_DLINE_MON                   Fld(24, 0) //[23:0]
+
+#define DDRPHY_REG_DLINE_MON_TRACK_DBG                         (DDRPHY_NAO_BASE_ADDRESS + 0x0728)
+    #define DLINE_MON_TRACK_DBG_DLINE_MON_TRACK_DBG            Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_DUTYCAL_STATUS                         (DDRPHY_NAO_BASE_ADDRESS + 0x072C)
+    #define MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B0 Fld(1, 0) //[0:0]
+    #define MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B1 Fld(1, 1) //[1:1]
+    #define MISC_DUTYCAL_STATUS_RGS_RX_ARCA_DUTY_VCAL_CMP_OUT_C0 Fld(1, 2) //[2:2]
+
+#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE0                    (DDRPHY_NAO_BASE_ADDRESS + 0x0730)
+    #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_DRVP_MAX      Fld(5, 0) //[4:0]
+    #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_DRVP_MAX_ERR  Fld(1, 7) //[7:7]
+    #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_DRVN_MAX      Fld(5, 8) //[12:8]
+    #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_DRVN_MAX_ERR  Fld(1, 15) //[15:15]
+    #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_ODTN_MAX      Fld(5, 16) //[20:16]
+    #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_ODTN_MAX_ERR  Fld(1, 23) //[23:23]
+    #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_WCK0_DRVP_MAX      Fld(5, 24) //[28:24]
+    #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_WCK0_DRVP_MAX_ERR  Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE1                    (DDRPHY_NAO_BASE_ADDRESS + 0x0734)
+    #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_DRVP_MAX      Fld(5, 0) //[4:0]
+    #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_DRVP_MAX_ERR  Fld(1, 7) //[7:7]
+    #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_DRVN_MAX      Fld(5, 8) //[12:8]
+    #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_DRVN_MAX_ERR  Fld(1, 15) //[15:15]
+    #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_ODTN_MAX      Fld(5, 16) //[20:16]
+    #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_ODTN_MAX_ERR  Fld(1, 23) //[23:23]
+    #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_WCK0_DRVN_MAX      Fld(5, 24) //[28:24]
+    #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_WCK0_DRVN_MAX_ERR  Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE2                    (DDRPHY_NAO_BASE_ADDRESS + 0x0738)
+    #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_DRVP_MAX       Fld(5, 0) //[4:0]
+    #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_DRVP_MAX_ERR   Fld(1, 7) //[7:7]
+    #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_DRVN_MAX       Fld(5, 8) //[12:8]
+    #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_DRVN_MAX_ERR   Fld(1, 15) //[15:15]
+    #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_ODTN_MAX       Fld(5, 16) //[20:16]
+    #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_ODTN_MAX_ERR   Fld(1, 23) //[23:23]
+    #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_WCK1_DRVP_MAX      Fld(5, 24) //[28:24]
+    #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_WCK1_DRVP_MAX_ERR  Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE3                    (DDRPHY_NAO_BASE_ADDRESS + 0x073C)
+    #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_DRVP_MAX       Fld(5, 0) //[4:0]
+    #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_DRVP_MAX_ERR   Fld(1, 7) //[7:7]
+    #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_DRVN_MAX       Fld(5, 8) //[12:8]
+    #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_DRVN_MAX_ERR   Fld(1, 15) //[15:15]
+    #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_ODTN_MAX       Fld(5, 16) //[20:16]
+    #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_ODTN_MAX_ERR   Fld(1, 23) //[23:23]
+    #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_WCK1_DRVN_MAX      Fld(5, 24) //[28:24]
+    #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_WCK1_DRVN_MAX_ERR  Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE4                    (DDRPHY_NAO_BASE_ADDRESS + 0x0740)
+    #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_DRVP_MAX       Fld(5, 0) //[4:0]
+    #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_DRVP_MAX_ERR   Fld(1, 7) //[7:7]
+    #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_DRVN_MAX       Fld(5, 8) //[12:8]
+    #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_DRVN_MAX_ERR   Fld(1, 15) //[15:15]
+    #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_ODTN_MAX       Fld(5, 16) //[20:16]
+    #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_ODTN_MAX_ERR   Fld(1, 23) //[23:23]
+    #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CS_DRVP_MAX        Fld(5, 24) //[28:24]
+    #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CS_DRVP_MAX_ERR    Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE5                    (DDRPHY_NAO_BASE_ADDRESS + 0x0744)
+    #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_DRVP_MAX       Fld(5, 0) //[4:0]
+    #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_DRVP_MAX_ERR   Fld(1, 7) //[7:7]
+    #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_DRVN_MAX       Fld(5, 8) //[12:8]
+    #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_DRVN_MAX_ERR   Fld(1, 15) //[15:15]
+    #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_ODTN_MAX       Fld(5, 16) //[20:16]
+    #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_ODTN_MAX_ERR   Fld(1, 23) //[23:23]
+    #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CS_DRVN_MAX        Fld(5, 24) //[28:24]
+    #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CS_DRVN_MAX_ERR    Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE6                    (DDRPHY_NAO_BASE_ADDRESS + 0x0748)
+    #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_DRVP_MIN      Fld(5, 0) //[4:0]
+    #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_DRVP_MIN_ERR  Fld(1, 7) //[7:7]
+    #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_DRVN_MIN      Fld(5, 8) //[12:8]
+    #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_DRVN_MIN_ERR  Fld(1, 15) //[15:15]
+    #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_ODTN_MIN      Fld(5, 16) //[20:16]
+    #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_ODTN_MIN_ERR  Fld(1, 23) //[23:23]
+    #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_WCK0_DRVP_MIN      Fld(5, 24) //[28:24]
+    #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_WCK0_DRVP_MIN_ERR  Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE7                    (DDRPHY_NAO_BASE_ADDRESS + 0x074C)
+    #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_DRVP_MIN      Fld(5, 0) //[4:0]
+    #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_DRVP_MIN_ERR  Fld(1, 7) //[7:7]
+    #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_DRVN_MIN      Fld(5, 8) //[12:8]
+    #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_DRVN_MIN_ERR  Fld(1, 15) //[15:15]
+    #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_ODTN_MIN      Fld(5, 16) //[20:16]
+    #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_ODTN_MIN_ERR  Fld(1, 23) //[23:23]
+    #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_WCK0_DRVN_MIN      Fld(5, 24) //[28:24]
+    #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_WCK0_DRVN_MIN_ERR  Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE8                    (DDRPHY_NAO_BASE_ADDRESS + 0x0750)
+    #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_DRVP_MIN       Fld(5, 0) //[4:0]
+    #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_DRVP_MIN_ERR   Fld(1, 7) //[7:7]
+    #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_DRVN_MIN       Fld(5, 8) //[12:8]
+    #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_DRVN_MIN_ERR   Fld(1, 15) //[15:15]
+    #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_ODTN_MIN       Fld(5, 16) //[20:16]
+    #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_ODTN_MIN_ERR   Fld(1, 23) //[23:23]
+    #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_WCK1_DRVP_MIN      Fld(5, 24) //[28:24]
+    #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_WCK1_DRVP_MIN_ERR  Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE9                    (DDRPHY_NAO_BASE_ADDRESS + 0x0754)
+    #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_DRVP_MIN       Fld(5, 0) //[4:0]
+    #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_DRVP_MIN_ERR   Fld(1, 7) //[7:7]
+    #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_DRVN_MIN       Fld(5, 8) //[12:8]
+    #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_DRVN_MIN_ERR   Fld(1, 15) //[15:15]
+    #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_ODTN_MIN       Fld(5, 16) //[20:16]
+    #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_ODTN_MIN_ERR   Fld(1, 23) //[23:23]
+    #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_WCK1_DRVN_MIN      Fld(5, 24) //[28:24]
+    #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_WCK1_DRVN_MIN_ERR  Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE10                   (DDRPHY_NAO_BASE_ADDRESS + 0x0758)
+    #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_DRVP_MIN      Fld(5, 0) //[4:0]
+    #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_DRVP_MIN_ERR  Fld(1, 7) //[7:7]
+    #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_DRVN_MIN      Fld(5, 8) //[12:8]
+    #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_DRVN_MIN_ERR  Fld(1, 15) //[15:15]
+    #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_ODTN_MIN      Fld(5, 16) //[20:16]
+    #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_ODTN_MIN_ERR  Fld(1, 23) //[23:23]
+    #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CS_DRVP_MIN       Fld(5, 24) //[28:24]
+    #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CS_DRVP_MIN_ERR   Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE11                   (DDRPHY_NAO_BASE_ADDRESS + 0x075C)
+    #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_DRVP_MIN      Fld(5, 0) //[4:0]
+    #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_DRVP_MIN_ERR  Fld(1, 7) //[7:7]
+    #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_DRVN_MIN      Fld(5, 8) //[12:8]
+    #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_DRVN_MIN_ERR  Fld(1, 15) //[15:15]
+    #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_ODTN_MIN      Fld(5, 16) //[20:16]
+    #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_ODTN_MIN_ERR  Fld(1, 23) //[23:23]
+    #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CS_DRVN_MIN       Fld(5, 24) //[28:24]
+    #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CS_DRVN_MIN_ERR   Fld(1, 31) //[31:31]
+
+#define DDRPHY_REG_MISC_DMA_SRAM_MBIST                         (DDRPHY_NAO_BASE_ADDRESS + 0x0800)
+    #define MISC_DMA_SRAM_MBIST_DRAMC_MBIST_MBIST_PRE_FUSE     Fld(8, 0) //[7:0]
+
+#define DDRPHY_REG_MISC_APHY_OBS0                              (DDRPHY_NAO_BASE_ADDRESS + 0x0820)
+    #define MISC_APHY_OBS0_AD_RX_ARDQ1_RCNT_B0                 Fld(9, 0) //[8:0]
+    #define MISC_APHY_OBS0_AD_RX_ARDQ2_RCNT_B0                 Fld(9, 9) //[17:9]
+    #define MISC_APHY_OBS0_AD_RX_ARDQ3_RCNT_B0                 Fld(9, 18) //[26:18]
+
+#define DDRPHY_REG_MISC_APHY_OBS1                              (DDRPHY_NAO_BASE_ADDRESS + 0x0824)
+    #define MISC_APHY_OBS1_AD_RX_ARDQ5_RCNT_B0                 Fld(9, 0) //[8:0]
+    #define MISC_APHY_OBS1_AD_RX_ARDQ6_RCNT_B0                 Fld(9, 9) //[17:9]
+    #define MISC_APHY_OBS1_AD_RX_ARDQ7_RCNT_B0                 Fld(9, 18) //[26:18]
+
+#define DDRPHY_REG_MISC_APHY_OBS2                              (DDRPHY_NAO_BASE_ADDRESS + 0x0828)
+    #define MISC_APHY_OBS2_AD_RX_ARDQ1_RCNT_B1                 Fld(9, 0) //[8:0]
+    #define MISC_APHY_OBS2_AD_RX_ARDQ2_RCNT_B1                 Fld(9, 9) //[17:9]
+    #define MISC_APHY_OBS2_AD_RX_ARDQ3_RCNT_B1                 Fld(9, 18) //[26:18]
+
+#define DDRPHY_REG_MISC_APHY_OBS3                              (DDRPHY_NAO_BASE_ADDRESS + 0x082C)
+    #define MISC_APHY_OBS3_AD_RX_ARDQ5_RCNT_B1                 Fld(9, 0) //[8:0]
+    #define MISC_APHY_OBS3_AD_RX_ARDQ6_RCNT_B1                 Fld(9, 9) //[17:9]
+    #define MISC_APHY_OBS3_AD_RX_ARDQ7_RCNT_B1                 Fld(9, 18) //[26:18]
+
+#define DDRPHY_REG_MISC_APHY_OBS4                              (DDRPHY_NAO_BASE_ADDRESS + 0x0830)
+    #define MISC_APHY_OBS4_AD_RX_ARDQM_RCNT_B0                 Fld(9, 0) //[8:0]
+    #define MISC_APHY_OBS4_AD_RX_ARDQM_RCNT_B1                 Fld(9, 9) //[17:9]
+
+#define DDRPHY_REG_MISC_APHY_OBS5                              (DDRPHY_NAO_BASE_ADDRESS + 0x0834)
+    #define MISC_APHY_OBS5_AD_RX_ARCA1_RCNT_C0                 Fld(9, 0) //[8:0]
+    #define MISC_APHY_OBS5_AD_RX_ARCA2_RCNT_C0                 Fld(9, 9) //[17:9]
+    #define MISC_APHY_OBS5_AD_RX_ARCA3_RCNT_C0                 Fld(9, 18) //[26:18]
+
+#define DDRPHY_REG_MISC_APHY_OBS6                              (DDRPHY_NAO_BASE_ADDRESS + 0x0838)
+    #define MISC_APHY_OBS6_AD_RX_ARCA5_RCNT_C0                 Fld(9, 0) //[8:0]
+    #define MISC_APHY_OBS6_AD_RX_ARCS0_RCNT_C0                 Fld(9, 9) //[17:9]
+    #define MISC_APHY_OBS6_AD_RX_ARCS1_RCNT_C0                 Fld(9, 18) //[26:18]
+
+#define DDRPHY_REG_MISC_APHY_OBS7                              (DDRPHY_NAO_BASE_ADDRESS + 0x083C)
+    #define MISC_APHY_OBS7_AD_RX_ARCKE0_RCNT_C0                Fld(9, 0) //[8:0]
+    #define MISC_APHY_OBS7_AD_RX_ARCKE1_RCNT_C0                Fld(9, 9) //[17:9]
+
+#define DDRPHY_REG_MISC_APHY_OBS8                              (DDRPHY_NAO_BASE_ADDRESS + 0x0840)
+    #define MISC_APHY_OBS8_RGS_ARDLL_ULCK_B0                   Fld(2, 0) //[1:0]
+    #define MISC_APHY_OBS8_RGS_ARDLL_ULCK_B1                   Fld(2, 2) //[3:2]
+    #define MISC_APHY_OBS8_RGS_ARDLL_ULCK_C0                   Fld(2, 4) //[5:4]
+    #define MISC_APHY_OBS8_RGS_RPHYPLL_DET_RSTB                Fld(1, 6) //[6:6]
+    #define MISC_APHY_OBS8_RGS_RCLRPLL_DET_RSTB                Fld(1, 7) //[7:7]
+
+#define DDRPHY_REG_MISC_EMI_LPBK8                              (DDRPHY_NAO_BASE_ADDRESS + 0x0844)
+    #define MISC_EMI_LPBK8_RDATA_CA0                           Fld(8, 0) //[7:0]
+    #define MISC_EMI_LPBK8_RDATA_CA1                           Fld(8, 8) //[15:8]
+    #define MISC_EMI_LPBK8_RDATA_CA2                           Fld(8, 16) //[23:16]
+    #define MISC_EMI_LPBK8_RDATA_CA3                           Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_EMI_LPBK9                              (DDRPHY_NAO_BASE_ADDRESS + 0x0848)
+    #define MISC_EMI_LPBK9_RDATA_CA4                           Fld(8, 0) //[7:0]
+    #define MISC_EMI_LPBK9_RDATA_CA5                           Fld(8, 8) //[15:8]
+    #define MISC_EMI_LPBK9_RDATA_CA6                           Fld(8, 16) //[23:16]
+    #define MISC_EMI_LPBK9_RDATA_CA7                           Fld(8, 24) //[31:24]
+
+#define DDRPHY_REG_MISC_EMI_LPBK10                             (DDRPHY_NAO_BASE_ADDRESS + 0x084C)
+    #define MISC_EMI_LPBK10_RDATA_CKE0                         Fld(8, 0) //[7:0]
+    #define MISC_EMI_LPBK10_RDATA_CKE1                         Fld(8, 8) //[15:8]
+    #define MISC_EMI_LPBK10_RDATA_CKE2                         Fld(8, 16) //[23:16]
+
+#define DDRPHY_REG_MISC_EMI_LPBK11                             (DDRPHY_NAO_BASE_ADDRESS + 0x0850)
+    #define MISC_EMI_LPBK11_RDATA_CS0                          Fld(8, 0) //[7:0]
+    #define MISC_EMI_LPBK11_RDATA_CS1                          Fld(8, 8) //[15:8]
+    #define MISC_EMI_LPBK11_RDATA_CS2                          Fld(8, 16) //[23:16]
+
+#define DDRPHY_REG_MISC_FT_STATUS5                             (DDRPHY_NAO_BASE_ADDRESS + 0x0854)
+    #define MISC_FT_STATUS5_AD_RX_ARDQ6_DVS_R_LEAD_C0          Fld(1, 0) //[0:0]
+    #define MISC_FT_STATUS5_AD_RX_ARDQ6_DVS_R_LAG_C0           Fld(1, 1) //[1:1]
+    #define MISC_FT_STATUS5_AD_RX_ARDQ6_DVS_F_LEAD_C0          Fld(1, 2) //[2:2]
+    #define MISC_FT_STATUS5_AD_RX_ARDQ6_DVS_F_LAG_C0           Fld(1, 3) //[3:3]
+    #define MISC_FT_STATUS5_AD_RX_ARDQ7_DVS_R_LEAD_C0          Fld(1, 4) //[4:4]
+    #define MISC_FT_STATUS5_AD_RX_ARDQ7_DVS_R_LAG_C0           Fld(1, 5) //[5:5]
+    #define MISC_FT_STATUS5_AD_RX_ARDQ7_DVS_F_LEAD_C0          Fld(1, 6) //[6:6]
+    #define MISC_FT_STATUS5_AD_RX_ARDQ7_DVS_F_LAG_C0           Fld(1, 7) //[7:7]
+    #define MISC_FT_STATUS5_AD_RX_ARCS1_DVS_R_LEAD_B1          Fld(1, 8) //[8:8]
+    #define MISC_FT_STATUS5_AD_RX_ARCS1_DVS_R_LAG_B1           Fld(1, 9) //[9:9]
+    #define MISC_FT_STATUS5_AD_RX_ARCS1_DVS_F_LEAD_B1          Fld(1, 10) //[10:10]
+    #define MISC_FT_STATUS5_AD_RX_ARCS1_DVS_F_LAG_B1           Fld(1, 11) //[11:11]
+    #define MISC_FT_STATUS5_AD_RX_ARCKE0_DVS_R_LEAD_B1         Fld(1, 12) //[12:12]
+    #define MISC_FT_STATUS5_AD_RX_ARCKE0_DVS_R_LAG_B1          Fld(1, 13) //[13:13]
+    #define MISC_FT_STATUS5_AD_RX_ARCKE0_DVS_F_LEAD_B1         Fld(1, 14) //[14:14]
+    #define MISC_FT_STATUS5_AD_RX_ARCKE0_DVS_F_LAG_B1          Fld(1, 15) //[15:15]
+    #define MISC_FT_STATUS5_AD_RX_ARCKE1_DVS_R_LEAD_B1         Fld(1, 16) //[16:16]
+    #define MISC_FT_STATUS5_AD_RX_ARCKE1_DVS_R_LAG_B1          Fld(1, 17) //[17:17]
+    #define MISC_FT_STATUS5_AD_RX_ARCKE1_DVS_F_LEAD_B1         Fld(1, 18) //[18:18]
+    #define MISC_FT_STATUS5_AD_RX_ARCKE1_DVS_F_LAG_B1          Fld(1, 19) //[19:19]
+
+#define DDRPHY_REG_MISC_STA_EXTLB6                             (DDRPHY_NAO_BASE_ADDRESS + 0x0858)
+    #define MISC_STA_EXTLB6_STA_EXTLB_DONE_EXTEND              Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_STA_EXTLB7                             (DDRPHY_NAO_BASE_ADDRESS + 0x085C)
+    #define MISC_STA_EXTLB7_STA_EXTLB_FAIL_EXTEND              Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_STA_EXTLB8                             (DDRPHY_NAO_BASE_ADDRESS + 0x0860)
+    #define MISC_STA_EXTLB8_STA_EXTLB_RISING_FAIL_EXTEND       Fld(32, 0) //[31:0]
+
+#define DDRPHY_REG_MISC_STA_EXTLB9                             (DDRPHY_NAO_BASE_ADDRESS + 0x0864)
+    #define MISC_STA_EXTLB9_STA_EXTLB_FALLING_FAIL_EXTEND      Fld(32, 0) //[31:0]
+
+#endif // __DDRPHY_NAO_REGS_H__
diff --git a/src/vendorcode/mediatek/mt8195/include/8195_Register_DRAMC_AO.h b/src/vendorcode/mediatek/mt8195/include/8195_Register_DRAMC_AO.h
new file mode 100644
index 000000000000..40fa01acff8a
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/8195_Register_DRAMC_AO.h
@@ -0,0 +1,1690 @@
+#ifndef __DRAMC_AO_REGS_H__
+#define __DRAMC_AO_REGS_H__
+
+#define Channel_A_DRAMC_AO_BASE_ADDRESS    0x10230000
+#define Channel_B_DRAMC_AO_BASE_ADDRESS    0x10240000
+
+#define DRAMC_AO_BASE_ADDRESS     Channel_A_DRAMC_AO_BASE_VIRTUAL
+
+#define DRAMC_REG_DDRCOMMON0                                   (DRAMC_AO_BASE_ADDRESS + 0x0000)
+    #define DDRCOMMON0_DISSTOP26M                              Fld(1, 0) //[0:0]
+    #define DDRCOMMON0_RANK_ASYM                               Fld(1, 1) //[1:1]
+    #define DDRCOMMON0_DM16BITFULL                             Fld(1, 2) //[2:2]
+    #define DDRCOMMON0_TRCDEARLY                               Fld(1, 3) //[3:3]
+    #define DDRCOMMON0_BK8EN                                   Fld(1, 8) //[8:8]
+    #define DDRCOMMON0_BG4EN                                   Fld(1, 11) //[11:11]
+    #define DDRCOMMON0_GDDR3EN                                 Fld(1, 16) //[16:16]
+    #define DDRCOMMON0_LPDDR2EN                                Fld(1, 17) //[17:17]
+    #define DDRCOMMON0_LPDDR3EN                                Fld(1, 18) //[18:18]
+    #define DDRCOMMON0_LPDDR4EN                                Fld(1, 19) //[19:19]
+    #define DDRCOMMON0_LPDDR5EN                                Fld(1, 20) //[20:20]
+    #define DDRCOMMON0_DDR2EN                                  Fld(1, 22) //[22:22]
+    #define DDRCOMMON0_DDR3EN                                  Fld(1, 23) //[23:23]
+    #define DDRCOMMON0_DDR4EN                                  Fld(1, 24) //[24:24]
+    #define DDRCOMMON0_DRAMC_SW_RST                            Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_SA_RESERVE                                   (DRAMC_AO_BASE_ADDRESS + 0x000C)
+    #define SA_RESERVE_SINGLE_RANK                             Fld(1, 0) //[0:0]
+    #define SA_RESERVE_DFS_FSP_RTMRW                           Fld(2, 1) //[2:1]
+    #define SA_RESERVE_SUPPORT_4266                            Fld(1, 3) //[3: 3]
+    #define SA_RESERVE_DRM_SHU_SRAM_LEVEL                      Fld(4, 4) //[7: 4]
+    #define SA_RESERVE_DRM_SHU_LEVEL                           Fld(1, 8) //[8:8]
+    #define SA_RESERVE_DRM_DSC_DRAM                            Fld(1, 9) //[9:9]
+    #define SA_RESERVE_SA_RESERVE                              Fld(14, 10) //[23:10]
+    #define SA_RESERVE_MODE_RK1                                Fld(4, 24) //[27:24]
+    #define SA_RESERVE_MODE_RK0                                Fld(4, 28) //[31:28]
+
+#define DRAMC_REG_NONSHU_RSV                                   (DRAMC_AO_BASE_ADDRESS + 0x00FC)
+    #define NONSHU_RSV_NONSHU_RSV                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_TEST2_A0                                     (DRAMC_AO_BASE_ADDRESS + 0x0100)
+    #define TEST2_A0_TEST2_PAT1                                Fld(8, 0) //[7:0]
+    #define TEST2_A0_TEST2_PAT0                                Fld(8, 8) //[15:8]
+    #define TEST2_A0_LOOP_NV_END                               Fld(1, 16) //[16:16]
+    #define TEST2_A0_ERR_BREAK_EN                              Fld(1, 17) //[17:17]
+    #define TEST2_A0_TA2_LOOP_EN                               Fld(1, 18) //[18:18]
+    #define TEST2_A0_TA2_CG_FR                                 Fld(1, 19) //[19:19]
+    #define TEST2_A0_LOOP_CNT_INDEX                            Fld(4, 20) //[23:20]
+    #define TEST2_A0_WDT_BY_DRAMC_DIS                          Fld(1, 24) //[24:24]
+
+#define DRAMC_REG_TEST2_A2                                     (DRAMC_AO_BASE_ADDRESS + 0x0104)
+    #define TEST2_A2_TEST2_OFF                                 Fld(28, 4) //[31:4]
+
+#define DRAMC_REG_TEST2_A3                                     (DRAMC_AO_BASE_ADDRESS + 0x0108)
+    #define TEST2_A3_TESTCNT                                   Fld(4, 0) //[3:0]
+    #define TEST2_A3_TESTWRHIGH                                Fld(1, 4) //[4:4]
+    #define TEST2_A3_ADRDECEN_TARKMODE                         Fld(1, 5) //[5:5]
+    #define TEST2_A3_PSTWR2                                    Fld(1, 6) //[6:6]
+    #define TEST2_A3_TESTAUDPAT                                Fld(1, 7) //[7:7]
+    #define TEST2_A3_TESTCLKRUN                                Fld(1, 8) //[8:8]
+    #define TEST2_A3_ERRFLAG_BYTE_SEL                          Fld(2, 9) //[10:9]
+    #define TEST2_A3_PAT_SHIFT_SW_EN                           Fld(1, 11) //[11:11]
+    #define TEST2_A3_PAT_SHIFT_OFFSET                          Fld(3, 12) //[14:12]
+    #define TEST2_A3_TEST2_PAT_SHIFT                           Fld(1, 15) //[15:15]
+    #define TEST2_A3_TEST_AID_EN                               Fld(1, 16) //[16:16]
+    #define TEST2_A3_HFIDPAT                                   Fld(1, 17) //[17:17]
+    #define TEST2_A3_AUTO_GEN_PAT                              Fld(1, 18) //[18:18]
+    #define TEST2_A3_LBSELFCMP                                 Fld(1, 19) //[19:19]
+    #define TEST2_A3_DMPAT32                                   Fld(1, 24) //[24:24]
+    #define TEST2_A3_TESTADR_SHIFT                             Fld(1, 25) //[25:25]
+    #define TEST2_A3_TAHPRI_B                                  Fld(1, 26) //[26:26]
+    #define TEST2_A3_TESTLP                                    Fld(1, 27) //[27:27]
+    #define TEST2_A3_TEST2WREN2_HW_EN                          Fld(1, 28) //[28:28]
+    #define TEST2_A3_TEST1                                     Fld(1, 29) //[29:29]
+    #define TEST2_A3_TEST2R                                    Fld(1, 30) //[30:30]
+    #define TEST2_A3_TEST2W                                    Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_TEST2_A4                                     (DRAMC_AO_BASE_ADDRESS + 0x010C)
+    #define TEST2_A4_TESTAUDINC                                Fld(5, 0) //[4:0]
+    #define TEST2_A4_TEST2DISSCRAM                             Fld(1, 5) //[5:5]
+    #define TEST2_A4_TESTSSOPAT                                Fld(1, 6) //[6:6]
+    #define TEST2_A4_TESTSSOXTALKPAT                           Fld(1, 7) //[7:7]
+    #define TEST2_A4_TESTAUDINIT                               Fld(5, 8) //[12:8]
+    #define TEST2_A4_TEST2_EN1ARB_DIS                          Fld(1, 13) //[13:13]
+    #define TEST2_A4_TESTAUDBITINV                             Fld(1, 14) //[14:14]
+    #define TEST2_A4_TESTAUDMODE                               Fld(1, 15) //[15:15]
+    #define TEST2_A4_TESTXTALKPAT                              Fld(1, 16) //[16:16]
+    #define TEST2_A4_TEST_REQ_LEN1                             Fld(1, 17) //[17:17]
+    #define TEST2_A4_TEST2EN1_OPT2                             Fld(1, 18) //[18:18]
+    #define TEST2_A4_TEST2EN1_OPT1_DIS                         Fld(1, 19) //[19:19]
+    #define TEST2_A4_TEST2_DQMTGL                              Fld(1, 21) //[21:21]
+    #define TEST2_A4_TESTAGENTRK                               Fld(2, 24) //[25:24]
+    #define TEST2_A4_TESTDMITGLPAT                             Fld(1, 26) //[26:26]
+    #define TEST2_A4_TEST1TO4LEN1_DIS                          Fld(1, 27) //[27:27]
+    #define TEST2_A4_TESTAGENTRKSEL                            Fld(3, 28) //[30:28]
+    #define TEST2_A4_TESTAGENT_DMYRD_OPT                       Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_DUMMY_RD                                     (DRAMC_AO_BASE_ADDRESS + 0x0110)
+    #define DUMMY_RD_SREF_DMYRD_MASK                           Fld(1, 0) //[0:0]
+    #define DUMMY_RD_DMYRDOFOEN                                Fld(1, 1) //[1:1]
+    #define DUMMY_RD_DUMMY_RD_SW                               Fld(1, 4) //[4:4]
+    #define DUMMY_RD_DMYWR_LPRI_EN                             Fld(1, 5) //[5:5]
+    #define DUMMY_RD_DMY_WR_DBG                                Fld(1, 6) //[6:6]
+    #define DUMMY_RD_DMY_RD_DBG                                Fld(1, 7) //[7:7]
+    #define DUMMY_RD_DRS_CNTX                                  Fld(7, 8) //[14:8]
+    #define DUMMY_RD_DRS_SELFWAKE_DMYRD_DIS                    Fld(1, 15) //[15:15]
+    #define DUMMY_RD_RANK_NUM                                  Fld(2, 16) //[17:16]
+    #define DUMMY_RD_DUMMY_RD_EN                               Fld(1, 20) //[20:20]
+    #define DUMMY_RD_SREF_DMYRD_EN                             Fld(1, 21) //[21:21]
+    #define DUMMY_RD_DQSG_DMYRD_EN                             Fld(1, 22) //[22:22]
+    #define DUMMY_RD_DQSG_DMYWR_EN                             Fld(1, 23) //[23:23]
+    #define DUMMY_RD_DUMMY_RD_PA_OPT                           Fld(1, 24) //[24:24]
+    #define DUMMY_RD_DMY_RD_RX_TRACK                           Fld(1, 25) //[25:25]
+    #define DUMMY_RD_DMYRD_HPRI_DIS                            Fld(1, 26) //[26:26]
+    #define DUMMY_RD_DMYRD_REORDER_DIS                         Fld(1, 27) //[27:27]
+    #define DUMMY_RD_RETRY_SP_RK_DIS                           Fld(1, 28) //[28:28]
+
+#define DRAMC_REG_DUMMY_RD_INTV                                (DRAMC_AO_BASE_ADDRESS + 0x0114)
+    #define DUMMY_RD_INTV_DUMMY_RD_CNT0                        Fld(1, 0) //[0:0]
+    #define DUMMY_RD_INTV_DUMMY_RD_CNT1                        Fld(1, 1) //[1:1]
+    #define DUMMY_RD_INTV_DUMMY_RD_CNT2                        Fld(1, 2) //[2:2]
+    #define DUMMY_RD_INTV_DUMMY_RD_CNT3                        Fld(1, 3) //[3:3]
+    #define DUMMY_RD_INTV_DUMMY_RD_CNT4                        Fld(1, 4) //[4:4]
+    #define DUMMY_RD_INTV_DUMMY_RD_CNT5                        Fld(1, 5) //[5:5]
+    #define DUMMY_RD_INTV_DUMMY_RD_CNT6                        Fld(1, 6) //[6:6]
+    #define DUMMY_RD_INTV_DUMMY_RD_CNT7                        Fld(1, 7) //[7:7]
+    #define DUMMY_RD_INTV_DUMMY_RD_1_CNT0                      Fld(1, 16) //[16:16]
+    #define DUMMY_RD_INTV_DUMMY_RD_1_CNT1                      Fld(1, 17) //[17:17]
+    #define DUMMY_RD_INTV_DUMMY_RD_1_CNT2                      Fld(1, 18) //[18:18]
+    #define DUMMY_RD_INTV_DUMMY_RD_1_CNT3                      Fld(1, 19) //[19:19]
+    #define DUMMY_RD_INTV_DUMMY_RD_1_CNT4                      Fld(1, 20) //[20:20]
+    #define DUMMY_RD_INTV_DUMMY_RD_1_CNT5                      Fld(1, 21) //[21:21]
+    #define DUMMY_RD_INTV_DUMMY_RD_1_CNT6                      Fld(1, 22) //[22:22]
+    #define DUMMY_RD_INTV_DUMMY_RD_1_CNT7                      Fld(1, 23) //[23:23]
+
+#define DRAMC_REG_BUS_MON1                                     (DRAMC_AO_BASE_ADDRESS + 0x0118)
+    #define BUS_MON1_WRBYTE_CNT_OPT                            Fld(1, 0) //[0:0]
+
+#define DRAMC_REG_DRAMC_DBG_SEL1                               (DRAMC_AO_BASE_ADDRESS + 0x011C)
+    #define DRAMC_DBG_SEL1_DEBUG_SEL_0                         Fld(16, 0) //[15:0]
+    #define DRAMC_DBG_SEL1_DEBUG_SEL_1                         Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_DRAMC_DBG_SEL2                               (DRAMC_AO_BASE_ADDRESS + 0x0120)
+    #define DRAMC_DBG_SEL2_DEBUG_SEL_2                         Fld(16, 0) //[15:0]
+    #define DRAMC_DBG_SEL2_DEBUG_SEL_3                         Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_SWCMD_EN                                     (DRAMC_AO_BASE_ADDRESS + 0x0124)
+    #define SWCMD_EN_MPRWEN                                    Fld(1, 0) //[0:0]
+    #define SWCMD_EN_STESTEN                                   Fld(1, 1) //[1:1]
+    #define SWCMD_EN_MPCMANEN                                  Fld(1, 2) //[2:2]
+    #define SWCMD_EN_PREAEN                                    Fld(1, 3) //[3:3]
+    #define SWCMD_EN_ACTEN                                     Fld(1, 4) //[4:4]
+    #define SWCMD_EN_RDDQCEN                                   Fld(1, 5) //[5:5]
+    #define SWCMD_EN_WRFIFOEN                                  Fld(1, 6) //[6:6]
+    #define SWCMD_EN_RDFIFOEN                                  Fld(1, 7) //[7:7]
+    #define SWCMD_EN_DQSOSCDISEN                               Fld(1, 8) //[8:8]
+    #define SWCMD_EN_DQSOSCENEN                                Fld(1, 9) //[9:9]
+    #define SWCMD_EN_ZQLATEN                                   Fld(1, 10) //[10:10]
+    #define SWCMD_EN_MRWEN                                     Fld(1, 11) //[11:11]
+    #define SWCMD_EN_MRREN                                     Fld(1, 12) //[12:12]
+    #define SWCMD_EN_AREFEN                                    Fld(1, 13) //[13:13]
+    #define SWCMD_EN_ZQCEN                                     Fld(1, 14) //[14:14]
+    #define SWCMD_EN_SPREA_EN                                  Fld(1, 15) //[15:15]
+    #define SWCMD_EN_ZQCEN_SWTRIG                              Fld(1, 16) //[16:16]
+    #define SWCMD_EN_ZQLATEN_SWTRIG                            Fld(1, 17) //[17:17]
+    #define SWCMD_EN_WCK2DQI_START_SWTRIG                      Fld(1, 18) //[18:18]
+    #define SWCMD_EN_WCK2DQO_START_SWTRIG                      Fld(1, 19) //[19:19]
+    #define SWCMD_EN_ZQ_SW                                     Fld(1, 20) //[20:20]
+    #define SWCMD_EN_WCK2DQ_SW                                 Fld(1, 21) //[21:21]
+    #define SWCMD_EN_SWCMDEN_RESERVED87                        Fld(2, 22) //[23:22]
+    #define SWCMD_EN_RTMRWEN                                   Fld(1, 24) //[24:24]
+    #define SWCMD_EN_RTSWCMDEN                                 Fld(1, 25) //[25:25]
+    #define SWCMD_EN_RTSWCMD_SEL                               Fld(6, 26) //[31:26]
+
+#define DRAMC_REG_SWCMD_CTRL0                                  (DRAMC_AO_BASE_ADDRESS + 0x0128)
+    #define SWCMD_CTRL0_MRSOP                                  Fld(8, 0) //[7:0]
+    #define SWCMD_CTRL0_MRSMA                                  Fld(13, 8) //[20:8]
+    #define SWCMD_CTRL0_MRSBA                                  Fld(3, 21) //[23:21]
+    #define SWCMD_CTRL0_MRSRK                                  Fld(2, 24) //[25:24]
+    #define SWCMD_CTRL0_MRRRK                                  Fld(2, 26) //[27:26]
+    #define SWCMD_CTRL0_MRSBG                                  Fld(2, 28) //[29:28]
+    #define SWCMD_CTRL0_SWTRIG_ZQ_RK                           Fld(1, 30) //[30:30]
+
+#define DRAMC_REG_SWCMD_CTRL1                                  (DRAMC_AO_BASE_ADDRESS + 0x012C)
+    #define SWCMD_CTRL1_RDDQC_LP_INTV                          Fld(2, 0) //[1:0]
+    #define SWCMD_CTRL1_RDDQC_LP_ENB                           Fld(1, 2) //[2:2]
+    #define SWCMD_CTRL1_ACTEN_BK                               Fld(3, 3) //[5:3]
+    #define SWCMD_CTRL1_ACTEN_ROW_R17_R16                      Fld(2, 22) //[22:23] //Lewis add for ppr
+    #define SWCMD_CTRL1_ACTEN_ROW                              Fld(18, 6) //[23:6]
+    #define SWCMD_CTRL1_WRFIFO_MODE2                           Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_SWCMD_CTRL2                                  (DRAMC_AO_BASE_ADDRESS + 0x0130)
+    #define SWCMD_CTRL2_RTSWCMD_AGE                            Fld(10, 0) //[9:0]
+    #define SWCMD_CTRL2_RTSWCMD_RK                             Fld(2, 10) //[11:10]
+    #define SWCMD_CTRL2_RTSWCMD_MA                             Fld(8, 12) //[19:12]
+    #define SWCMD_CTRL2_RTSWCMD_OP                             Fld(8, 20) //[27:20]
+    #define SWCMD_CTRL2_RTSWCMD_ALLTYPE_OPT                    Fld(1, 28) //[28:28]
+
+#define DRAMC_REG_RDDQCGOLDEN1                                 (DRAMC_AO_BASE_ADDRESS + 0x0134)
+    #define RDDQCGOLDEN1_LP5_MR20_6_GOLDEN                     Fld(1, 0) //[0:0]
+    #define RDDQCGOLDEN1_LP5_MR20_7_GOLDEN                     Fld(1, 1) //[1:1]
+
+#define DRAMC_REG_RDDQCGOLDEN                                  (DRAMC_AO_BASE_ADDRESS + 0x0138)
+    #define RDDQCGOLDEN_MR20_GOLDEN                            Fld(8, 0) //[7:0]
+    #define RDDQCGOLDEN_MR15_GOLDEN                            Fld(8, 8) //[15:8]
+    #define RDDQCGOLDEN_MR40_GOLDEN                            Fld(8, 16) //[23:16]
+    #define RDDQCGOLDEN_MR32_GOLDEN                            Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_RTMRW_CTRL0                                  (DRAMC_AO_BASE_ADDRESS + 0x013C)
+    #define RTMRW_CTRL0_RTMRW0_RK                              Fld(2, 0) //[1:0]
+    #define RTMRW_CTRL0_RTMRW1_RK                              Fld(2, 2) //[3:2]
+    #define RTMRW_CTRL0_RTMRW2_RK                              Fld(2, 4) //[5:4]
+    #define RTMRW_CTRL0_RTMRW3_RK                              Fld(2, 6) //[7:6]
+    #define RTMRW_CTRL0_RTMRW4_RK                              Fld(2, 8) //[9:8]
+    #define RTMRW_CTRL0_RTMRW5_RK                              Fld(2, 10) //[11:10]
+    #define RTMRW_CTRL0_RTMRW_LEN                              Fld(3, 12) //[14:12]
+    #define RTMRW_CTRL0_RTMRW_AGE                              Fld(10, 15) //[24:15]
+    #define RTMRW_CTRL0_RTMRW_LAT                              Fld(7, 25) //[31:25]
+
+#define DRAMC_REG_RTMRW_CTRL1                                  (DRAMC_AO_BASE_ADDRESS + 0x0140)
+    #define RTMRW_CTRL1_RTMRW0_MA                              Fld(8, 0) //[7:0]
+    #define RTMRW_CTRL1_RTMRW1_MA                              Fld(8, 8) //[15:8]
+    #define RTMRW_CTRL1_RTMRW2_MA                              Fld(8, 16) //[23:16]
+    #define RTMRW_CTRL1_RTMRW3_MA                              Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_RTMRW_CTRL2                                  (DRAMC_AO_BASE_ADDRESS + 0x0144)
+    #define RTMRW_CTRL2_RTMRW0_OP                              Fld(8, 0) //[7:0]
+    #define RTMRW_CTRL2_RTMRW1_OP                              Fld(8, 8) //[15:8]
+    #define RTMRW_CTRL2_RTMRW2_OP                              Fld(8, 16) //[23:16]
+    #define RTMRW_CTRL2_RTMRW3_OP                              Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_RTMRW_CTRL3                                  (DRAMC_AO_BASE_ADDRESS + 0x0148)
+    #define RTMRW_CTRL3_RTMRW4_MA                              Fld(8, 0) //[7:0]
+    #define RTMRW_CTRL3_RTMRW5_MA                              Fld(8, 8) //[15:8]
+    #define RTMRW_CTRL3_RTMRW4_OP                              Fld(8, 16) //[23:16]
+    #define RTMRW_CTRL3_RTMRW5_OP                              Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_CBT_WLEV_CTRL0                               (DRAMC_AO_BASE_ADDRESS + 0x014C)
+    #define CBT_WLEV_CTRL0_CBT_CAPATEN                         Fld(1, 0) //[0:0]
+    #define CBT_WLEV_CTRL0_TCMDEN                              Fld(1, 1) //[1:1]
+    #define CBT_WLEV_CTRL0_BYTEMODECBTEN                       Fld(1, 2) //[2:2]
+    #define CBT_WLEV_CTRL0_WRITE_LEVEL_EN                      Fld(1, 3) //[3:3]
+    #define CBT_WLEV_CTRL0_DQSOEAOEN                           Fld(1, 4) //[4:4]
+    #define CBT_WLEV_CTRL0_CBTMASKDQSOE                        Fld(1, 5) //[5:5]
+    #define CBT_WLEV_CTRL0_WLEV_DQSPATEN                       Fld(1, 6) //[6:6]
+    #define CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG                   Fld(1, 7) //[7:7]
+    #define CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL                    Fld(4, 8) //[11:8]
+    #define CBT_WLEV_CTRL0_WLEV_DQSPAT_LAT                     Fld(8, 12) //[19:12]
+    #define CBT_WLEV_CTRL0_WLEV_MCK_NUM                        Fld(2, 20) //[21:20]
+    #define CBT_WLEV_CTRL0_WLEV_WCK_HR                         Fld(1, 22) //[22:22]
+    #define CBT_WLEV_CTRL0_CBT_WLEV_WCKAO                      Fld(1, 23) //[23:23]
+    #define CBT_WLEV_CTRL0_CBT_SW_DQM_B0_LP5                   Fld(1, 24) //[24:24]
+    #define CBT_WLEV_CTRL0_CBT_SW_DQM_B1_LP5                   Fld(1, 25) //[25:25]
+    #define CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN                  Fld(4, 26) //[29:26]
+    #define CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE                    Fld(1, 30) //[30:30]
+
+#define DRAMC_REG_CBT_WLEV_CTRL1                               (DRAMC_AO_BASE_ADDRESS + 0x0150)
+    #define CBT_WLEV_CTRL1_CATRAINCSEXT                        Fld(1, 0) //[0:0]
+    #define CBT_WLEV_CTRL1_CATRAINMRS                          Fld(1, 1) //[1:1]
+    #define CBT_WLEV_CTRL1_CATRAINEN                           Fld(1, 2) //[2:2]
+    #define CBT_WLEV_CTRL1_CATRAINLAT                          Fld(4, 11) //[14:11]
+    #define CBT_WLEV_CTRL1_CATRAIN_INTV                        Fld(8, 15) //[22:15]
+    #define CBT_WLEV_CTRL1_TCMDO1LAT                           Fld(8, 23) //[30:23]
+
+#define DRAMC_REG_CBT_WLEV_CTRL2                               (DRAMC_AO_BASE_ADDRESS + 0x0154)
+    #define CBT_WLEV_CTRL2_CATRAINCA                           Fld(16, 0) //[15:0]
+    #define CBT_WLEV_CTRL2_CATRAINCA_Y                         Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_CBT_WLEV_CTRL3                               (DRAMC_AO_BASE_ADDRESS + 0x0158)
+    #define CBT_WLEV_CTRL3_CATRAIN_PAT_STOP0                   Fld(4, 0) //[3:0]
+    #define CBT_WLEV_CTRL3_CATRAIN_PAT_STOP1                   Fld(3, 4) //[6:4]
+    #define CBT_WLEV_CTRL3_CATRAIN_1PAT_SEL0                   Fld(4, 7) //[10:7]
+    #define CBT_WLEV_CTRL3_CATRAIN_1PAT_SEL1                   Fld(3, 11) //[13:11]
+    #define CBT_WLEV_CTRL3_DQSBX_G                             Fld(4, 14) //[17:14]
+    #define CBT_WLEV_CTRL3_DQSBY_G                             Fld(4, 18) //[21:18]
+    #define CBT_WLEV_CTRL3_DQSBX1_G                            Fld(4, 22) //[25:22]
+    #define CBT_WLEV_CTRL3_DQSBY1_G                            Fld(4, 26) //[29:26]
+
+#define DRAMC_REG_CBT_WLEV_CTRL4                               (DRAMC_AO_BASE_ADDRESS + 0x015C)
+    #define CBT_WLEV_CTRL4_CBT_TXDQ_B0                         Fld(8, 0) //[7:0]
+    #define CBT_WLEV_CTRL4_CBT_TXDQ_B1                         Fld(8, 8) //[15:8]
+
+#define DRAMC_REG_CBT_WLEV_ATK_CTRL0                           (DRAMC_AO_BASE_ADDRESS + 0x0160)
+    #define CBT_WLEV_ATK_CTRL0_ARPICS_SW                       Fld(1, 0) //[0:0]
+    #define CBT_WLEV_ATK_CTRL0_ARPICA_SW                       Fld(1, 1) //[1:1]
+    #define CBT_WLEV_ATK_CTRL0_ARPIDQS_SW                      Fld(1, 2) //[2:2]
+    #define CBT_WLEV_ATK_CTRL0_CSTRAIN_ATKEN                   Fld(1, 3) //[3:3]
+    #define CBT_WLEV_ATK_CTRL0_CATRAIN_ATKEN                   Fld(1, 4) //[4:4]
+    #define CBT_WLEV_ATK_CTRL0_WLEV_ATKEN                      Fld(1, 5) //[5:5]
+    #define CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_INTV               Fld(5, 6) //[10:6]
+    #define CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_LENPI              Fld(6, 11) //[16:11]
+    #define CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_RESPI              Fld(2, 17) //[18:17]
+    #define CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_INITPI             Fld(6, 19) //[24:19]
+    #define CBT_WLEV_ATK_CTRL0_CBT_ATK_CABITDBG                Fld(3, 25) //[27:25]
+
+#define DRAMC_REG_CBT_WLEV_ATK_CTRL1                           (DRAMC_AO_BASE_ADDRESS + 0x0164)
+    #define CBT_WLEV_ATK_CTRL1_UICS_SW                         Fld(2, 0) //[1:0]
+    #define CBT_WLEV_ATK_CTRL1_UICA_SW                         Fld(7, 2) //[8:2]
+    #define CBT_WLEV_ATK_CTRL1_UIDQS_SW                        Fld(4, 9) //[12:9]
+    #define CBT_WLEV_ATK_CTRL1_UIWCK_FS_B1_RK0_SW              Fld(1, 13) //[13:13]
+    #define CBT_WLEV_ATK_CTRL1_UIWCK_FS_B0_RK0_SW              Fld(1, 14) //[14:14]
+    #define CBT_WLEV_ATK_CTRL1_UIWCK_FS_B1_RK1_SW              Fld(1, 15) //[15:15]
+    #define CBT_WLEV_ATK_CTRL1_UIWCK_FS_B0_RK1_SW              Fld(1, 16) //[16:16]
+    #define CBT_WLEV_ATK_CTRL1_CBT_ATK_CA1UI64PI               Fld(1, 17) //[17:17]
+
+#define DRAMC_REG_SREF_DPD_CTRL                                (DRAMC_AO_BASE_ADDRESS + 0x0168)
+    #define SREF_DPD_CTRL_LPSM_BYPASS_B                        Fld(1, 7) //[7:7]
+    #define SREF_DPD_CTRL_DPDWOSC                              Fld(1, 8) //[8:8]
+    #define SREF_DPD_CTRL_CLR_EN                               Fld(1, 9) //[9:9]
+    #define SREF_DPD_CTRL_SELFREF_AUTOSAVE_EN                  Fld(1, 10) //[10:10]
+    #define SREF_DPD_CTRL_SREF_PRD_OPT                         Fld(1, 11) //[11:11]
+    #define SREF_DPD_CTRL_SREF_CG_OPT                          Fld(1, 12) //[12:12]
+    #define SREF_DPD_CTRL_SRFPD_DIS                            Fld(1, 13) //[13:13]
+    #define SREF_DPD_CTRL_SREF3_OPTION                         Fld(1, 14) //[14:14]
+    #define SREF_DPD_CTRL_SREF2_OPTION                         Fld(1, 15) //[15:15]
+    #define SREF_DPD_CTRL_SREFDLY                              Fld(4, 16) //[19:16]
+    #define SREF_DPD_CTRL_DSM_HW_EN                            Fld(1, 20) //[20:20]
+    #define SREF_DPD_CTRL_DSM_TRIGGER                          Fld(1, 21) //[21:21]
+    #define SREF_DPD_CTRL_SREF_HW_EN                           Fld(1, 22) //[22:22]
+    #define SREF_DPD_CTRL_SELFREF                              Fld(1, 23) //[23:23]
+    #define SREF_DPD_CTRL_DPDWAKEDCMCKE                        Fld(1, 25) //[25:25]
+    #define SREF_DPD_CTRL_CMDCKAR                              Fld(1, 26) //[26:26]
+    #define SREF_DPD_CTRL_GTDMW_SYNC_MASK                      Fld(1, 28) //[28:28]
+    #define SREF_DPD_CTRL_GT_SYNC_MASK                         Fld(1, 29) //[29:29]
+    #define SREF_DPD_CTRL_DAT_SYNC_MASK                        Fld(1, 30) //[30:30]
+    #define SREF_DPD_CTRL_PHY_SYNC_MASK                        Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_CFC_CTRL                                     (DRAMC_AO_BASE_ADDRESS + 0x016C)
+    #define CFC_CTRL_CFC_CTRL_RESERVED                         Fld(1, 0) //[0:0]
+
+#define DRAMC_REG_DLLFRZ_CTRL                                  (DRAMC_AO_BASE_ADDRESS + 0x0170)
+    #define DLLFRZ_CTRL_INPUTRXTRACK_BLOCK                     Fld(1, 0) //[0:0]
+    #define DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT                   Fld(1, 1) //[1:1]
+    #define DLLFRZ_CTRL_DLLFRZ_BLOCKLONG                       Fld(1, 2) //[2:2]
+    #define DLLFRZ_CTRL_DLLFRZIDLE4XUPD                        Fld(1, 3) //[3:3]
+    #define DLLFRZ_CTRL_FASTDQSG2X                             Fld(1, 4) //[4:4]
+    #define DLLFRZ_CTRL_FASTDQSGUPD                            Fld(1, 5) //[5:5]
+    #define DLLFRZ_CTRL_MANUDLLFRZ                             Fld(1, 6) //[6:6]
+    #define DLLFRZ_CTRL_DLLFRZ                                 Fld(1, 7) //[7:7]
+    #define DLLFRZ_CTRL_UPDBYWR                                Fld(1, 8) //[8:8]
+
+#define DRAMC_REG_MPC_CTRL                                     (DRAMC_AO_BASE_ADDRESS + 0x0174)
+    #define MPC_CTRL_MPC_BLOCKALE_OPT                          Fld(1, 0) //[0:0]
+    #define MPC_CTRL_MPC_BLOCKALE_OPT1                         Fld(1, 1) //[1:1]
+    #define MPC_CTRL_MPC_BLOCKALE_OPT2                         Fld(1, 2) //[2:2]
+    #define MPC_CTRL_ZQ_BLOCKALE_OPT                           Fld(1, 3) //[3:3]
+    #define MPC_CTRL_RW2ZQLAT_OPT                              Fld(1, 4) //[4:4]
+    #define MPC_CTRL_REFR_BLOCKEN                              Fld(1, 5) //[5:5]
+    #define MPC_CTRL_RTMRW_HPRI_EN                             Fld(1, 6) //[6:6]
+    #define MPC_CTRL_RTSWCMD_HPRI_EN                           Fld(1, 7) //[7:7]
+
+#define DRAMC_REG_HW_MRR_FUN                                   (DRAMC_AO_BASE_ADDRESS + 0x0178)
+    #define HW_MRR_FUN_TMRR_ENA                                Fld(1, 0) //[0:0]
+    #define HW_MRR_FUN_TRCDMRR_EN                              Fld(1, 1) //[1:1]
+    #define HW_MRR_FUN_TRPMRR_EN                               Fld(1, 2) //[2:2]
+    #define HW_MRR_FUN_MANTMRR_EN                              Fld(1, 3) //[3:3]
+    #define HW_MRR_FUN_TR2MRR_ENA                              Fld(1, 4) //[4:4]
+    #define HW_MRR_FUN_R2MRRHPRICTL                            Fld(1, 5) //[5:5]
+    #define HW_MRR_FUN_BUFEN_RFC_OPT                           Fld(1, 8) //[8:8]
+    #define HW_MRR_FUN_MRR_REQNOPUSH_DIS                       Fld(1, 9) //[9:9]
+    #define HW_MRR_FUN_MRR_BLOCK_NOR_DIS                       Fld(1, 10) //[10:10]
+    #define HW_MRR_FUN_MRR_HW_HIPRI                            Fld(1, 11) //[11:11]
+    #define HW_MRR_FUN_MRR_SPCMD_WAKE_DIS                      Fld(1, 12) //[12:12]
+    #define HW_MRR_FUN_TMRR_OE_OPT_DIS                         Fld(1, 13) //[13:13]
+    #define HW_MRR_FUN_MRR_SBR_OPT_DIS                         Fld(1, 14) //[14:14]
+    #define HW_MRR_FUN_MRR_INT_TIE0_DIS                        Fld(1, 15) //[15:15]
+    #define HW_MRR_FUN_MRR_PUSH2POP_ENA                        Fld(1, 16) //[16:16]
+    #define HW_MRR_FUN_MRR_PUSH2POP_CLR                        Fld(1, 17) //[17:17]
+    #define HW_MRR_FUN_MRR_PUSH2POP_ST_CLR                     Fld(1, 18) //[18:18]
+    #define HW_MRR_FUN_MRR_MADIS                               Fld(1, 19) //[19:19]
+    #define HW_MRR_FUN_MRR_PUSH2POP_SEL                        Fld(3, 20) //[22:20]
+    #define HW_MRR_FUN_MRR_SBR3_BKVA_DIS                       Fld(1, 23) //[23:23]
+    #define HW_MRR_FUN_MRR_DDRCLKCOMB_DIS                      Fld(1, 24) //[24:24]
+    #define HW_MRR_FUN_TRPRCD_DIS_OPT1                         Fld(1, 25) //[25:25]
+    #define HW_MRR_FUN_TRPRCD_OPT2                             Fld(1, 26) //[26:26]
+    #define HW_MRR_FUN_MRR_SBR2_QHIT_DIS                       Fld(1, 27) //[27:27]
+    #define HW_MRR_FUN_MRR_INPUT_BANK                          Fld(3, 28) //[30:28]
+    #define HW_MRR_FUN_MRR_TZQCS_DIS                           Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_SCHEDULER_COM                                (DRAMC_AO_BASE_ADDRESS + 0x017C)
+    #define SCHEDULER_COM_RWOFOEN                              Fld(1, 0) //[0:0]
+    #define SCHEDULER_COM_RWHPRICTL                            Fld(1, 4) //[4:4]
+    #define SCHEDULER_COM_RWSPLIT                              Fld(1, 5) //[5:5]
+    #define SCHEDULER_COM_MWHPRIEN                             Fld(1, 6) //[6:6]
+    #define SCHEDULER_COM_SPEC_MODE                            Fld(1, 7) //[7:7]
+    #define SCHEDULER_COM_DISRDPHASE1                          Fld(1, 8) //[8:8]
+    #define SCHEDULER_COM_PBR2PBR_OPT                          Fld(1, 9) //[9:9]
+
+#define DRAMC_REG_ACTIMING_CTRL                                (DRAMC_AO_BASE_ADDRESS + 0x0190)
+    #define ACTIMING_CTRL_SEQCLKRUN3                           Fld(1, 0) //[0:0]
+    #define ACTIMING_CTRL_SEQCLKRUN2                           Fld(1, 1) //[1:1]
+    #define ACTIMING_CTRL_SEQCLKRUN                            Fld(1, 2) //[2:2]
+    #define ACTIMING_CTRL_TMRR2WDIS                            Fld(1, 4) //[4:4]
+    #define ACTIMING_CTRL_MRRSWUPD                             Fld(1, 5) //[5:5]
+    #define ACTIMING_CTRL_REFNA_OPT                            Fld(1, 6) //[6:6]
+    #define ACTIMING_CTRL_REFBW_FREN                           Fld(1, 8) //[8:8]
+    #define ACTIMING_CTRL_CLKWITRFC                            Fld(1, 9) //[9:9]
+    #define ACTIMING_CTRL_CHKFORPRE                            Fld(1, 10) //[10:10]
+    #define ACTIMING_CTRL_BC4OTF_OPT                           Fld(1, 11) //[11:11]
+    #define ACTIMING_CTRL_TMRRICHKDIS                          Fld(1, 21) //[21:21]
+    #define ACTIMING_CTRL_TMRRIBYRK_DIS                        Fld(1, 22) //[22:22]
+    #define ACTIMING_CTRL_MRRIOPT                              Fld(1, 23) //[23:23]
+    #define ACTIMING_CTRL_FASTW2R                              Fld(1, 24) //[24:24]
+    #define ACTIMING_CTRL_APBL2                                Fld(1, 25) //[25:25]
+    #define ACTIMING_CTRL_LPDDR2_NO_INT                        Fld(1, 27) //[27:27]
+
+#define DRAMC_REG_ZQ_SET0                                      (DRAMC_AO_BASE_ADDRESS + 0x01A0)
+    #define ZQ_SET0_ZQCSOP                                     Fld(8, 0) //[7:0]
+    #define ZQ_SET0_ZQCSAD                                     Fld(8, 8) //[15:8]
+    #define ZQ_SET0_ZQCS_MASK_SEL                              Fld(3, 16) //[18:16]
+    #define ZQ_SET0_ZQCS_MASK_SEL_CGAR                         Fld(1, 19) //[19:19]
+    #define ZQ_SET0_ZQMASK_CGAR                                Fld(1, 20) //[20:20]
+    #define ZQ_SET0_ZQCSMASK_OPT                               Fld(1, 21) //[21:21]
+    #define ZQ_SET0_ZQ_SRF_OPT                                 Fld(1, 22) //[22:22]
+    #define ZQ_SET0_DM3RANK                                    Fld(1, 23) //[23:23]
+    #define ZQ_SET0_ZQCSMASK                                   Fld(1, 29) //[29:29]
+    #define ZQ_SET0_ZQCSDUAL                                   Fld(1, 30) //[30:30]
+    #define ZQ_SET0_ZQCALL                                     Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_ZQ_SET1                                      (DRAMC_AO_BASE_ADDRESS + 0x01A4)
+    #define ZQ_SET1_ZQCS_NONMASK_CLR                           Fld(1, 20) //[20:20]
+    #define ZQ_SET1_ZQCS_MASK_FIX                              Fld(1, 21) //[21:21]
+    #define ZQ_SET1_ZQCS_MASK_VALUE                            Fld(1, 22) //[22:22]
+    #define ZQ_SET1_ZQCALDISB                                  Fld(1, 30) //[30:30]
+    #define ZQ_SET1_ZQCSDISB                                   Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_TX_TRACKING_SET0                             (DRAMC_AO_BASE_ADDRESS + 0x01B0)
+    #define TX_TRACKING_SET0_TX_TRACKING_OPT                   Fld(1, 15) //[15:15]
+    #define TX_TRACKING_SET0_SW_UP_TX_NOW_CASE                 Fld(1, 16) //[16:16]
+    #define TX_TRACKING_SET0_TXUIPI_CAL_CGAR                   Fld(1, 17) //[17:17]
+    #define TX_TRACKING_SET0_SHU_PRELOAD_TX_START              Fld(1, 18) //[18:18]
+    #define TX_TRACKING_SET0_SHU_PRELOAD_TX_HW                 Fld(1, 19) //[19:19]
+    #define TX_TRACKING_SET0_APHY_CG_OPT1                      Fld(1, 20) //[20:20]
+    #define TX_TRACKING_SET0_HMRRSEL_CGAR                      Fld(1, 21) //[21:21]
+    #define TX_TRACKING_SET0_RDDQSOSC_CGAR                     Fld(1, 22) //[22:22]
+    #define TX_TRACKING_SET0_DQSOSC_THRD_OPT                   Fld(1, 23) //[23:23]
+    #define TX_TRACKING_SET0_TX_PRECAL_RELOAD_OPT              Fld(1, 24) //[24:24]
+    #define TX_TRACKING_SET0_DQSOSC_C2R_OPT                    Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_TX_RETRY_SET0                                (DRAMC_AO_BASE_ADDRESS + 0x01C0)
+    #define TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK          Fld(1, 0) //[0:0]
+    #define TX_RETRY_SET0_XSR_TX_RETRY_OPT                     Fld(1, 1) //[1:1]
+    #define TX_RETRY_SET0_XSR_TX_RETRY_EN                      Fld(1, 2) //[2:2]
+    #define TX_RETRY_SET0_XSR_TX_RETRY_SPM_MODE                Fld(1, 3) //[3:3]
+    #define TX_RETRY_SET0_XSR_TX_RETRY_SW_EN                   Fld(1, 4) //[4:4]
+    #define TX_RETRY_SET0_TX_RETRY_UPDPI_CG_OPT                Fld(1, 5) //[5:5]
+    #define TX_RETRY_SET0_TX_RETRY_SHU_RESP_OPT                Fld(1, 6) //[6:6]
+
+#define DRAMC_REG_MPC_OPTION                                   (DRAMC_AO_BASE_ADDRESS + 0x01C8)
+    #define MPC_OPTION_MPCOP                                   Fld(7, 8) //[14:8]
+    #define MPC_OPTION_MPCMAN_CAS2EN                           Fld(1, 16) //[16:16]
+    #define MPC_OPTION_MPCRKEN                                 Fld(1, 17) //[17:17]
+
+#define DRAMC_REG_MRR_BIT_MUX1                                 (DRAMC_AO_BASE_ADDRESS + 0x01D0)
+    #define MRR_BIT_MUX1_MRR_BIT0_SEL                          Fld(5, 0) //[4:0]
+    #define MRR_BIT_MUX1_MRR_BIT1_SEL                          Fld(5, 8) //[12:8]
+    #define MRR_BIT_MUX1_MRR_BIT2_SEL                          Fld(5, 16) //[20:16]
+    #define MRR_BIT_MUX1_MRR_BIT3_SEL                          Fld(5, 24) //[28:24]
+
+#define DRAMC_REG_MRR_BIT_MUX2                                 (DRAMC_AO_BASE_ADDRESS + 0x01D4)
+    #define MRR_BIT_MUX2_MRR_BIT4_SEL                          Fld(5, 0) //[4:0]
+    #define MRR_BIT_MUX2_MRR_BIT5_SEL                          Fld(5, 8) //[12:8]
+    #define MRR_BIT_MUX2_MRR_BIT6_SEL                          Fld(5, 16) //[20:16]
+    #define MRR_BIT_MUX2_MRR_BIT7_SEL                          Fld(5, 24) //[28:24]
+
+#define DRAMC_REG_MRR_BIT_MUX3                                 (DRAMC_AO_BASE_ADDRESS + 0x01D8)
+    #define MRR_BIT_MUX3_MRR_BIT8_SEL                          Fld(5, 0) //[4:0]
+    #define MRR_BIT_MUX3_MRR_BIT9_SEL                          Fld(5, 8) //[12:8]
+    #define MRR_BIT_MUX3_MRR_BIT10_SEL                         Fld(5, 16) //[20:16]
+    #define MRR_BIT_MUX3_MRR_BIT11_SEL                         Fld(5, 24) //[28:24]
+
+#define DRAMC_REG_MRR_BIT_MUX4                                 (DRAMC_AO_BASE_ADDRESS + 0x01DC)
+    #define MRR_BIT_MUX4_MRR_BIT12_SEL                         Fld(5, 0) //[4:0]
+    #define MRR_BIT_MUX4_MRR_BIT13_SEL                         Fld(5, 8) //[12:8]
+    #define MRR_BIT_MUX4_MRR_BIT14_SEL                         Fld(5, 16) //[20:16]
+    #define MRR_BIT_MUX4_MRR_BIT15_SEL                         Fld(5, 24) //[28:24]
+
+#define DRAMC_REG_SHUCTRL                                      (DRAMC_AO_BASE_ADDRESS + 0x01F8)
+    #define SHUCTRL_R_DVFS_FSM_CLR                             Fld(1, 0) //[0:0]
+    #define SHUCTRL_DMSHU_DRAMC                                Fld(1, 4) //[4:4]
+
+#define DRAMC_REG_DRAMC_PD_CTRL                                (DRAMC_AO_BASE_ADDRESS + 0x01FC)
+    #define DRAMC_PD_CTRL_DCMEN                                Fld(1, 0) //[0:0]
+    #define DRAMC_PD_CTRL_DCMEN2                               Fld(1, 1) //[1:1]
+    #define DRAMC_PD_CTRL_DCMENNOTRFC                          Fld(1, 2) //[2:2]
+    #define DRAMC_PD_CTRL_PHYGLUECLKRUN                        Fld(1, 3) //[3:3]
+    #define DRAMC_PD_CTRL_PHYCLK_REFWKEN                       Fld(1, 4) //[4:4]
+    #define DRAMC_PD_CTRL_COMBPHY_CLKENSAME                    Fld(1, 5) //[5:5]
+    #define DRAMC_PD_CTRL_MIOCKCTRLOFF                         Fld(1, 6) //[6:6]
+    #define DRAMC_PD_CTRL_DRAMC_IDLE_DCM_FIXON                 Fld(1, 7) //[7:7]
+    #define DRAMC_PD_CTRL_PG_DCM_OPT                           Fld(1, 9) //[9:9]
+    #define DRAMC_PD_CTRL_COMB_DCM                             Fld(1, 10) //[10:10]
+    #define DRAMC_PD_CTRL_APHYCKCG_FIXOFF                      Fld(1, 12) //[12:12]
+    #define DRAMC_PD_CTRL_TCKFIXON                             Fld(1, 13) //[13:13]
+    #define DRAMC_PD_CTRL_PHYCLKDYNGEN                         Fld(1, 30) //[30:30]
+    #define DRAMC_PD_CTRL_COMBCLKCTRL                          Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_DCM_CTRL0                                    (DRAMC_AO_BASE_ADDRESS + 0x0200)
+    #define DCM_CTRL0_BCLKAR                                   Fld(1, 2) //[2:2]
+    #define DCM_CTRL0_DBG_CKE1FIXON                            Fld(1, 4) //[4:4]
+    #define DCM_CTRL0_DBG_CKE1FIXOFF                           Fld(1, 5) //[5:5]
+    #define DCM_CTRL0_DBG_CKEFIXON                             Fld(1, 6) //[6:6]
+    #define DCM_CTRL0_DBG_CKEFIXOFF                            Fld(1, 7) //[7:7]
+    #define DCM_CTRL0_DISDMOEDIS                               Fld(1, 8) //[8:8]
+    #define DCM_CTRL0_IDLE_CNT_OPT                             Fld(1, 16) //[16:16]
+    #define DCM_CTRL0_IDLEDCM_CNT_OPT                          Fld(1, 17) //[17:17]
+    #define DCM_CTRL0_IDLE_COND_OPT                            Fld(1, 18) //[18:18]
+
+#define DRAMC_REG_CKECTRL                                      (DRAMC_AO_BASE_ADDRESS + 0x0204)
+    #define CKECTRL_CKE2RANK_OPT3                              Fld(1, 1) //[1:1]
+    #define CKECTRL_CKE2FIXON                                  Fld(1, 2) //[2:2]
+    #define CKECTRL_CKE2FIXOFF                                 Fld(1, 3) //[3:3]
+    #define CKECTRL_CKE1FIXON                                  Fld(1, 4) //[4:4]
+    #define CKECTRL_CKE1FIXOFF                                 Fld(1, 5) //[5:5]
+    #define CKECTRL_CKEFIXON                                   Fld(1, 6) //[6:6]
+    #define CKECTRL_CKEFIXOFF                                  Fld(1, 7) //[7:7]
+    #define CKECTRL_CKE2RANK_OPT5                              Fld(1, 8) //[8:8]
+    #define CKECTRL_CKE2RANK_OPT6                              Fld(1, 9) //[9:9]
+    #define CKECTRL_CKE2RANK_OPT7                              Fld(1, 10) //[10:10]
+    #define CKECTRL_CKE2RANK_OPT8                              Fld(1, 11) //[11:11]
+    #define CKECTRL_CKEEXTEND                                  Fld(1, 12) //[12:12]
+    #define CKECTRL_CKETIMER_SEL                               Fld(1, 13) //[13:13]
+    #define CKECTRL_FASTWAKE_SEL                               Fld(1, 14) //[14:14]
+    #define CKECTRL_CKEWAKE_SEL                                Fld(1, 15) //[15:15]
+    #define CKECTRL_CKEWAKE_SEL2                               Fld(1, 16) //[16:16]
+    #define CKECTRL_CKE2RANK_OPT9                              Fld(1, 17) //[17:17]
+    #define CKECTRL_CKE2RANK_OPT10                             Fld(1, 18) //[18:18]
+    #define CKECTRL_CKE2RANK_OPT11                             Fld(1, 19) //[19:19]
+    #define CKECTRL_CKE2RANK_OPT12                             Fld(1, 20) //[20:20]
+    #define CKECTRL_CKE2RANK_OPT13                             Fld(1, 21) //[21:21]
+    #define CKECTRL_CKEPBDIS                                   Fld(1, 22) //[22:22]
+    #define CKECTRL_CKELCKFIX                                  Fld(1, 23) //[23:23]
+    #define CKECTRL_CKE2RANK_OPT2                              Fld(1, 24) //[24:24]
+    #define CKECTRL_CKE2RANK_OPT                               Fld(1, 25) //[25:25]
+    #define CKECTRL_RUNTIMEMRRCKEFIX                           Fld(1, 27) //[27:27]
+    #define CKECTRL_RUNTIMEMRRMIODIS                           Fld(1, 28) //[28:28]
+    #define CKECTRL_CKEON                                      Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_DVFS_CTRL0                                   (DRAMC_AO_BASE_ADDRESS + 0x0208)
+    #define DVFS_CTRL0_R_DRAMC_CHA                             Fld(1, 0) //[0:0]
+    #define DVFS_CTRL0_SHU_PHYRST_SEL                          Fld(1, 1) //[1:1]
+    #define DVFS_CTRL0_R_DVFS_SREF_OPT                         Fld(1, 5) //[5:5]
+    #define DVFS_CTRL0_HWSET_WLRL                              Fld(1, 8) //[8:8]
+    #define DVFS_CTRL0_MR13_SHU_EN                             Fld(1, 9) //[9:9]
+    #define DVFS_CTRL0_VRCG_EN                                 Fld(1, 10) //[10:10]
+    #define DVFS_CTRL0_SHU_CLK_MASK                            Fld(1, 12) //[12:12]
+    #define DVFS_CTRL0_DVFS_RXFIFOST_SKIP                      Fld(1, 13) //[13:13]
+    #define DVFS_CTRL0_DVFS_MR2_SKIP                           Fld(1, 14) //[14:14]
+    #define DVFS_CTRL0_DVFS_NOQUEFLUSH_EN                      Fld(1, 15) //[15:15]
+    #define DVFS_CTRL0_DVFS_CKE_OPT                            Fld(1, 16) //[16:16]
+    #define DVFS_CTRL0_R_SHUFFLE_BLOCK_OPT                     Fld(2, 17) //[18:17]
+    #define DVFS_CTRL0_DVFS_CG_OPT                             Fld(1, 19) //[19:19]
+    #define DVFS_CTRL0_SCARB_PRI_OPT                           Fld(1, 20) //[20:20]
+    #define DVFS_CTRL0_R_DMDVFSMRW_EN                          Fld(1, 21) //[21:21]
+    #define DVFS_CTRL0_MRWWOPRA                                Fld(1, 22) //[22:22]
+    #define DVFS_CTRL0_SHU2RKOPT                               Fld(1, 23) //[23:23]
+    #define DVFS_CTRL0_R_DMSHU_RDATRST_MASK                    Fld(1, 25) //[25:25]
+    #define DVFS_CTRL0_DVFS_SYNC_MASK                          Fld(1, 27) //[27:27]
+
+#define DRAMC_REG_SHUCTRL1                                     (DRAMC_AO_BASE_ADDRESS + 0x020C)
+    #define SHUCTRL1_FC_PRDCNT                                 Fld(8, 0) //[7:0]
+    #define SHUCTRL1_CKFSPE_PRDCNT                             Fld(8, 8) //[15:8]
+    #define SHUCTRL1_CKFSPX_PRDCNT                             Fld(8, 16) //[23:16]
+    #define SHUCTRL1_VRCGEN_PRDCNT                             Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_DVFS_TIMING_CTRL1                            (DRAMC_AO_BASE_ADDRESS + 0x0210)
+    #define DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT           Fld(8, 0) //[7:0]
+    #define DVFS_TIMING_CTRL1_DMSHU_CNT                        Fld(6, 16) //[21:16]
+
+#define DRAMC_REG_SHUCTRL3                                     (DRAMC_AO_BASE_ADDRESS + 0x0214)
+    #define SHUCTRL3_VRCGDIS_MRSMA                             Fld(13, 0) //[12:0]
+    #define SHUCTRL3_VRCGDISOP                                 Fld(8, 16) //[23:16]
+
+#define DRAMC_REG_DVFS_TIMING_CTRL3                            (DRAMC_AO_BASE_ADDRESS + 0x0218)
+    #define DVFS_TIMING_CTRL3_PREA_INTV                        Fld(5, 0) //[4:0]
+    #define DVFS_TIMING_CTRL3_MRW_INTV                         Fld(5, 8) //[12:8]
+    #define DVFS_TIMING_CTRL3_RTMRW_MRW1_SKIP                  Fld(1, 16) //[16:16]
+    #define DVFS_TIMING_CTRL3_RTMRW_MRW2_SKIP                  Fld(1, 17) //[17:17]
+    #define DVFS_TIMING_CTRL3_RTMRW_MRW3_SKIP                  Fld(1, 18) //[18:18]
+    #define DVFS_TIMING_CTRL3_RTMRW_MRW1_PAUSE                 Fld(1, 19) //[19:19]
+    #define DVFS_TIMING_CTRL3_RTMRW_MRW2_PAUSE                 Fld(1, 20) //[20:20]
+    #define DVFS_TIMING_CTRL3_RTMRW_MRW3_PAUSE                 Fld(1, 21) //[21:21]
+    #define DVFS_TIMING_CTRL3_RTMRW_MRW3_PRDCNT                Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_CMD_DEC_CTRL0                                (DRAMC_AO_BASE_ADDRESS + 0x021C)
+    #define CMD_DEC_CTRL0_GDDR3RST                             Fld(1, 0) //[0:0]
+    #define CMD_DEC_CTRL0_SELPH_CMD_CG_DIS                     Fld(1, 4) //[4:4]
+    #define CMD_DEC_CTRL0_RA15TOCS1                            Fld(1, 27) //[27:27]
+    #define CMD_DEC_CTRL0_RKMODE                               Fld(3, 8) //[10:8]
+    #define CMD_DEC_CTRL0_RKSWAP                               Fld(1, 11) //[11:11]
+    #define CMD_DEC_CTRL0_CS1FIXOFF                            Fld(1, 12) //[12:12]
+    #define CMD_DEC_CTRL0_PHYPIPE1EN                           Fld(1, 15) //[15:15]
+    #define CMD_DEC_CTRL0_PHYPIPE2EN                           Fld(1, 16) //[16:16]
+    #define CMD_DEC_CTRL0_PHYPIPE3EN                           Fld(1, 17) //[17:17]
+    #define CMD_DEC_CTRL0_DQCMD                                Fld(1, 19) //[19:19]
+
+#define DRAMC_REG_HMR4                                         (DRAMC_AO_BASE_ADDRESS + 0x0220)
+    #define HMR4_DRS_MR4_OPT_B                                 Fld(1, 0) //[0:0]
+    #define HMR4_HMR4_TOG_OPT                                  Fld(1, 1) //[1:1]
+    #define HMR4_SPDR_MR4_OPT                                  Fld(1, 2) //[2:2]
+    #define HMR4_SRFMR4_CNTKEEP_B                              Fld(1, 3) //[3:3]
+    #define HMR4_MRRREFUPD_B                                   Fld(1, 4) //[4:4]
+    #define HMR4_HMR4_BYTEMODE_EN                              Fld(1, 5) //[5:5]
+    #define HMR4_MR4INT_LIMITEN                                Fld(1, 6) //[6:6]
+    #define HMR4_REFR_PERIOD_OPT                               Fld(1, 7) //[7:7]
+    #define HMR4_REFRDIS                                       Fld(1, 8) //[8:8]
+    #define HMR4_REFRCNT_OPT                                   Fld(1, 9) //[9:9]
+
+#define DRAMC_REG_BYPASS_FSPOP                                 (DRAMC_AO_BASE_ADDRESS + 0x0224)
+    #define BYPASS_FSPOP_BPFSP_SET_SHU0                        Fld(1, 0) //[0:0]
+    #define BYPASS_FSPOP_BPFSP_SET_SHU1                        Fld(1, 1) //[1:1]
+    #define BYPASS_FSPOP_BPFSP_SET_SHU2                        Fld(1, 2) //[2:2]
+    #define BYPASS_FSPOP_BPFSP_SET_SHU3                        Fld(1, 3) //[3:3]
+    #define BYPASS_FSPOP_BPFSP_SET_SHU4                        Fld(1, 4) //[4:4]
+    #define BYPASS_FSPOP_BPFSP_SET_SHU5                        Fld(1, 5) //[5:5]
+    #define BYPASS_FSPOP_BPFSP_SET_SHU6                        Fld(1, 6) //[6:6]
+    #define BYPASS_FSPOP_BPFSP_SET_SHU7                        Fld(1, 7) //[7:7]
+    #define BYPASS_FSPOP_BPFSP_SET_SHU8                        Fld(1, 8) //[8:8]
+    #define BYPASS_FSPOP_BPFSP_SET_SHU9                        Fld(1, 9) //[9:9]
+    #define BYPASS_FSPOP_BPFSP_OPT                             Fld(1, 16) //[16:16]
+
+#define DRAMC_REG_RKCFG                                        (DRAMC_AO_BASE_ADDRESS + 0x0228)
+    #define RKCFG_MRS2RK                                       Fld(1, 10) //[10:10]
+    #define RKCFG_CKE2RANK                                     Fld(1, 12) //[12:12]
+
+#define DRAMC_REG_SLP4_TESTMODE                                (DRAMC_AO_BASE_ADDRESS + 0x022C)
+    #define SLP4_TESTMODE_CA0_TEST                             Fld(4, 0) //[3:0]
+    #define SLP4_TESTMODE_CA1_TEST                             Fld(4, 4) //[7:4]
+    #define SLP4_TESTMODE_CA2_TEST                             Fld(4, 8) //[11:8]
+    #define SLP4_TESTMODE_CA3_TEST                             Fld(4, 12) //[15:12]
+    #define SLP4_TESTMODE_CA4_TEST                             Fld(4, 16) //[19:16]
+    #define SLP4_TESTMODE_CA5_TEST                             Fld(4, 20) //[23:20]
+
+#define DRAMC_REG_DQ_MUX_SET0                                  (DRAMC_AO_BASE_ADDRESS + 0x0230)
+    #define DQ_MUX_SET0_SRF_ENTER_MASK_OPT                     Fld(1, 30) //[30:30]
+    #define DQ_MUX_SET0_DQ4BMUX                                Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_DBIWR_PROTECT                                (DRAMC_AO_BASE_ADDRESS + 0x0234)
+    #define DBIWR_PROTECT_DBIWR_IMP_EN                         Fld(1, 0) //[0:0]
+    #define DBIWR_PROTECT_DBIWR_PINMUX_EN                      Fld(1, 1) //[1:1]
+    #define DBIWR_PROTECT_DBIWR_OPT_B0                         Fld(8, 16) //[23:16]
+    #define DBIWR_PROTECT_DBIWR_OPT_B1                         Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_TX_SET0                                      (DRAMC_AO_BASE_ADDRESS + 0x0238)
+    #define TX_SET0_TXRANK                                     Fld(2, 0) //[1:0]
+    #define TX_SET0_TXRANKFIX                                  Fld(1, 2) //[2:2]
+    #define TX_SET0_DDRPHY_COMB_CG_SEL                         Fld(1, 3) //[3:3]
+    #define TX_SET0_TX_DQM_DEFAULT                             Fld(1, 4) //[4:4]
+    #define TX_SET0_DQBUS_X32                                  Fld(1, 5) //[5:5]
+    #define TX_SET0_OE_DOWNGRADE                               Fld(1, 6) //[6:6]
+    #define TX_SET0_DQ16COM1                                   Fld(1, 21) //[21:21]
+    #define TX_SET0_WPRE2T                                     Fld(1, 22) //[22:22]
+    #define TX_SET0_DRSCLR_EN                                  Fld(1, 24) //[24:24]
+    #define TX_SET0_DRSCLR_RK0_EN                              Fld(1, 25) //[25:25]
+    #define TX_SET0_ARPI_CAL_E2OPT                             Fld(1, 26) //[26:26]
+    #define TX_SET0_TX_DLY_CAL_E2OPT                           Fld(1, 27) //[27:27]
+    #define TX_SET0_DQS_OE_OP1_DIS                             Fld(1, 28) //[28:28]
+    #define TX_SET0_DQS_OE_OP2_EN                              Fld(1, 29) //[29:29]
+    #define TX_SET0_RK_SCINPUT_OPT                             Fld(1, 30) //[30:30]
+    #define TX_SET0_DRAMOEN                                    Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_TX_CG_SET0                                   (DRAMC_AO_BASE_ADDRESS + 0x023C)
+    #define TX_CG_SET0_SELPH_4LCG_DIS                          Fld(1, 0) //[0:0]
+    #define TX_CG_SET0_SELPH_CG_DIS                            Fld(1, 1) //[1:1]
+    #define TX_CG_SET0_DWCLKRUN                                Fld(1, 2) //[2:2]
+    #define TX_CG_SET0_WDATA_CG_DIS                            Fld(1, 3) //[3:3]
+    #define TX_CG_SET0_TX_ATK_CLKRUN                           Fld(1, 4) //[4:4]
+    #define TX_CG_SET0_PSEL_OPT3                               Fld(1, 22) //[22:22]
+    #define TX_CG_SET0_PSEL_OPT2                               Fld(1, 23) //[23:23]
+    #define TX_CG_SET0_PSEL_OPT1                               Fld(1, 24) //[24:24]
+    #define TX_CG_SET0_PSEL_CNT                                Fld(6, 25) //[30:25]
+    #define TX_CG_SET0_PSELAR                                  Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_RX_SET0                                      (DRAMC_AO_BASE_ADDRESS + 0x0240)
+    #define RX_SET0_RDATRST                                    Fld(1, 0) //[0:0]
+    #define RX_SET0_PRE_DLE_VLD_OPT                            Fld(1, 1) //[1:1]
+    #define RX_SET0_DATLAT_PDLE_TH                             Fld(3, 2) //[4:2]
+    #define RX_SET0_RANKRDY_OPT                                Fld(1, 5) //[5:5]
+    #define RX_SET0_SMRR_UPD_OLD                               Fld(1, 6) //[6:6]
+    #define RX_SET0_EBG_DLE_SKIP_SPEC_RID                      Fld(1, 29) //[29:29]
+    #define RX_SET0_DM32BIT_RDSEL_OPT                          Fld(1, 30) //[30:30]
+    #define RX_SET0_DM4TO1MODE                                 Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_RX_CG_SET0                                   (DRAMC_AO_BASE_ADDRESS + 0x0244)
+    #define RX_CG_SET0_RDPERIODON                              Fld(1, 29) //[29:29]
+    #define RX_CG_SET0_RDATCKAR                                Fld(1, 30) //[30:30]
+    #define RX_CG_SET0_RDYCKAR                                 Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_DQSOSCR                                      (DRAMC_AO_BASE_ADDRESS + 0x0248)
+    #define DQSOSCR_DQSOSC_INTEN                               Fld(1, 0) //[0:0]
+    #define DQSOSCR_DQSOSC2RK                                  Fld(1, 1) //[1:1]
+    #define DQSOSCR_TXUPD_BLOCK_SEL                            Fld(2, 2) //[3:2]
+    #define DQSOSCR_TXUPD_BLOCK_OPT                            Fld(1, 4) //[4:4]
+    #define DQSOSCR_TXUPDMODE                                  Fld(1, 5) //[5:5]
+    #define DQSOSCR_MANUTXUPD                                  Fld(1, 6) //[6:6]
+    #define DQSOSCR_ARUIDQ_SW                                  Fld(1, 7) //[7:7]
+    #define DQSOSCR_DQS2DQ_UPD_BLOCK_CNT                       Fld(5, 8) //[12:8]
+    #define DQSOSCR_TDQS2DQ_UPD_BLOCKING                       Fld(1, 13) //[13:13]
+    #define DQSOSCR_DQS2DQ_UPD_MON_OPT                         Fld(1, 14) //[14:14]
+    #define DQSOSCR_DQS2DQ_UPD_MON_CNT_SEL                     Fld(2, 15) //[16:15]
+    #define DQSOSCR_TXUPD_IDLE_SEL                             Fld(2, 17) //[18:17]
+    #define DQSOSCR_TXUPD_ABREF_SEL                            Fld(2, 19) //[20:19]
+    #define DQSOSCR_TXUPD_IDLE_OPT                             Fld(1, 21) //[21:21]
+    #define DQSOSCR_DQS2DQ_SHU_HW_CAL_DIS                      Fld(1, 22) //[22:22]
+    #define DQSOSCR_SREF_TXUI_RELOAD_OPT                       Fld(1, 23) //[23:23]
+    #define DQSOSCR_DQSOSCRDIS                                 Fld(1, 24) //[24:24]
+    #define DQSOSCR_DQS2DQ_WARN_OPT                            Fld(1, 25) //[25:25]
+    #define DQSOSCR_R_DMDQS2DQ_FILT_OPT                        Fld(1, 26) //[26:26]
+    #define DQSOSCR_SREF_TXPI_RELOAD_OPT                       Fld(1, 27) //[27:27]
+    #define DQSOSCR_EMPTY_WRITE_OPT                            Fld(1, 28) //[28:28]
+    #define DQSOSCR_TXUPD_ABREF_OPT                            Fld(1, 29) //[29:29]
+    #define DQSOSCR_DQSOSCLOPAD                                Fld(1, 30) //[30:30]
+    #define DQSOSCR_DQSOSC_CALEN                               Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_DRAMCTRL                                     (DRAMC_AO_BASE_ADDRESS + 0x024C)
+    #define DRAMCTRL_CTOREQ_HPRI_OPT                           Fld(1, 0) //[0:0]
+    #define DRAMCTRL_MATAB_LP5_MODE                            Fld(1, 1) //[1:1]
+    #define DRAMCTRL_ADRDECEN                                  Fld(1, 2) //[2:2]
+    #define DRAMCTRL_ADRBIT3DEC                                Fld(1, 3) //[3:3]
+    #define DRAMCTRL_ADRDEN_1TO4_OPT                           Fld(1, 5) //[5:5]
+    #define DRAMCTRL_ALL_BLOCK_CTO_ALE_DBG_EN                  Fld(1, 8) //[8:8]
+    #define DRAMCTRL_SELFREF_BLOCK_CTO_ALE_DBG_EN              Fld(1, 9) //[9:9]
+    #define DRAMCTRL_DVFS_BLOCK_CTO_ALE_DBG_EN                 Fld(1, 10) //[10:10]
+    #define DRAMCTRL_AG0MWR                                    Fld(1, 12) //[12:12]
+    #define DRAMCTRL_DYNMWREN                                  Fld(1, 13) //[13:13]
+    #define DRAMCTRL_ALEBLOCK                                  Fld(1, 14) //[14:14]
+    #define DRAMCTRL_PREALL_OPTION                             Fld(1, 19) //[19:19]
+    #define DRAMCTRL_REQQUE_DEPTH_UPD                          Fld(1, 25) //[25:25]
+    #define DRAMCTRL_REQQUE_THD_EN                             Fld(1, 26) //[26:26]
+    #define DRAMCTRL_REQQUE_MAXCNT_CHG                         Fld(1, 27) //[27:27]
+    #define DRAMCTRL_PREA_RK                                   Fld(2, 28) //[29:28]
+    #define DRAMCTRL_SHORTQ_OPT                                Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_MISCTL0                                      (DRAMC_AO_BASE_ADDRESS + 0x0250)
+    #define MISCTL0_REFP_ARBMASK_PBR2PBR_ENA                   Fld(1, 0) //[0:0]
+    #define MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS                Fld(1, 1) //[1:1]
+    #define MISCTL0_WDLE_DVFS_NO_FLUSH_OPT_DIS                 Fld(1, 4) //[4:4]
+    #define MISCTL0_GROUP_A_REV                                Fld(4, 8) //[11:8]
+    #define MISCTL0_PG_WAKEUP_OPT                              Fld(2, 14) //[15:14]
+    #define MISCTL0_PAGDIS                                     Fld(1, 17) //[17:17]
+    #define MISCTL0_REFA_ARB_EN2                               Fld(1, 19) //[19:19]
+    #define MISCTL0_REFA_ARB_EN_OPTION                         Fld(1, 21) //[21:21]
+    #define MISCTL0_REORDER_MASK_E1T                           Fld(1, 22) //[22:22]
+    #define MISCTL0_PBC_ARB_E1T                                Fld(1, 23) //[23:23]
+    #define MISCTL0_PBC_ARB_EN                                 Fld(1, 24) //[24:24]
+    #define MISCTL0_REFA_ARB_EN                                Fld(1, 25) //[25:25]
+    #define MISCTL0_REFP_ARB_EN                                Fld(1, 26) //[26:26]
+    #define MISCTL0_EMIPREEN                                   Fld(1, 27) //[27:27]
+    #define MISCTL0_REFP_ARB_EN2                               Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_PERFCTL0                                     (DRAMC_AO_BASE_ADDRESS + 0x0254)
+    #define PERFCTL0_EBG_EN                                    Fld(1, 0) //[0:0]
+    #define PERFCTL0_AIDCHKEN                                  Fld(1, 3) //[3:3]
+    #define PERFCTL0_RWHPRIEN                                  Fld(1, 8) //[8:8]
+    #define PERFCTL0_RWLLATEN                                  Fld(1, 9) //[9:9]
+    #define PERFCTL0_RWAGEEN                                   Fld(1, 10) //[10:10]
+    #define PERFCTL0_EMILLATEN                                 Fld(1, 11) //[11:11]
+    #define PERFCTL0_WFLUSHEN                                  Fld(1, 14) //[14:14]
+    #define PERFCTL0_REORDER_MODE                              Fld(1, 18) //[18:18]
+    #define PERFCTL0_REORDEREN                                 Fld(1, 19) //[19:19]
+    #define PERFCTL0_SBR_MASK_OPT                              Fld(1, 20) //[20:20]
+    #define PERFCTL0_SBR_MASK_OPT2                             Fld(1, 21) //[21:21]
+    #define PERFCTL0_MAFIXHIGH                                 Fld(1, 22) //[22:22]
+    #define PERFCTL0_RECORDER_MASK_OPT                         Fld(1, 24) //[24:24]
+    #define PERFCTL0_MDMCU_MASK_EN                             Fld(1, 25) //[25:25]
+
+#define DRAMC_REG_ARBCTL                                       (DRAMC_AO_BASE_ADDRESS + 0x0258)
+    #define ARBCTL_MAXPENDCNT                                  Fld(8, 0) //[7:0]
+    #define ARBCTL_RDATACNTDIS                                 Fld(1, 8) //[8:8]
+    #define ARBCTL_WDATACNTDIS                                 Fld(1, 9) //[9:9]
+
+#define DRAMC_REG_DATASCR                                      (DRAMC_AO_BASE_ADDRESS + 0x025C)
+    #define DATASCR_WDATKEY0                                   Fld(1, 0) //[0:0]
+    #define DATASCR_WDATKEY1                                   Fld(1, 1) //[1:1]
+    #define DATASCR_WDATKEY2                                   Fld(1, 2) //[2:2]
+    #define DATASCR_WDATKEY3                                   Fld(1, 3) //[3:3]
+    #define DATASCR_WDATKEY4                                   Fld(1, 4) //[4:4]
+    #define DATASCR_WDATKEY5                                   Fld(1, 5) //[5:5]
+    #define DATASCR_WDATKEY6                                   Fld(1, 6) //[6:6]
+    #define DATASCR_WDATKEY7                                   Fld(1, 7) //[7:7]
+    #define DATASCR_WDATITLV                                   Fld(1, 8) //[8:8]
+
+#define DRAMC_REG_CLKAR                                        (DRAMC_AO_BASE_ADDRESS + 0x0260)
+    #define CLKAR_REQQUE_PACG_DIS                              Fld(15, 0) //[14:0]
+    #define CLKAR_SRF_CLKRUN                                   Fld(1, 17) //[17:17]
+    #define CLKAR_IDLE_OPT                                     Fld(1, 18) //[18:18]
+    #define CLKAR_RKSIZE                                       Fld(3, 20) //[22:20]
+    #define CLKAR_DCMREF_OPT                                   Fld(1, 24) //[24:24]
+    #define CLKAR_REQQUECLKRUN                                 Fld(1, 27) //[27:27]
+
+#define DRAMC_REG_REFCTRL0                                     (DRAMC_AO_BASE_ADDRESS + 0x0264)
+    #define REFCTRL0_PBREF_BK_REFA_NUM                         Fld(3, 0) //[2:0]
+    #define REFCTRL0_PBREF_BK_REFA_ENA                         Fld(1, 3) //[3:3]
+    #define REFCTRL0_RFRINTCTL                                 Fld(1, 5) //[5:5]
+    #define REFCTRL0_RFRINTEN                                  Fld(1, 6) //[6:6]
+    #define REFCTRL0_REFOVERCNT_RST                            Fld(1, 7) //[7:7]
+    #define REFCTRL0_DMPGVLD_IG                                Fld(1, 8) //[8:8]
+    #define REFCTRL0_KEEP_PBREF_OPT                            Fld(1, 9) //[9:9]
+    #define REFCTRL0_KEEP_PBREF                                Fld(1, 10) //[10:10]
+    #define REFCTRL0_REFRATE_FOR_BK_ARBMASK                    Fld(1, 11) //[11:11]
+    #define REFCTRL0_DISBYREFNUM                               Fld(3, 12) //[14:12]
+    #define REFCTRL0_PBREF_DISBYREFNUM                         Fld(1, 16) //[16:16]
+    #define REFCTRL0_PBREF_DISBYRATE                           Fld(1, 17) //[17:17]
+    #define REFCTRL0_SREF3_OPTION1                             Fld(1, 19) //[19:19]
+    #define REFCTRL0_ADVREF_CNT                                Fld(4, 20) //[23:20]
+    #define REFCTRL0_REF_PREGATE_CNT                           Fld(4, 24) //[27:24]
+    #define REFCTRL0_REFDIS                                    Fld(1, 29) //[29:29]
+
+#define DRAMC_REG_REFCTRL1                                     (DRAMC_AO_BASE_ADDRESS + 0x0268)
+    #define REFCTRL1_PB2AB_OPT                                 Fld(1, 0) //[0:0]
+    #define REFCTRL1_PB2AB_OPT1                                Fld(1, 1) //[1:1]
+    #define REFCTRL1_PBREF_DISBYMODREF                         Fld(1, 2) //[2:2]
+    #define REFCTRL1_REFPENDINGINT_OPT1                        Fld(1, 3) //[3:3]
+    #define REFCTRL1_PRE8REF                                   Fld(1, 4) //[4:4]
+    #define REFCTRL1_REF_QUE_AUTOSAVE_EN                       Fld(1, 5) //[5:5]
+    #define REFCTRL1_REFPEND_OPT1                              Fld(1, 6) //[6:6]
+    #define REFCTRL1_REFPEND_OPT2                              Fld(1, 7) //[7:7]
+    #define REFCTRL1_REFPB2AB_IGZQCS                           Fld(1, 8) //[8:8]
+    #define REFCTRL1_REFRATE_MON_CLR                           Fld(1, 11) //[11:11]
+    #define REFCTRL1_REF_OVERHEAD_PBR2PB_ENA                   Fld(1, 13) //[13:13]
+    #define REFCTRL1_REF_OVERHEAD_RATE_REFAL_ENA               Fld(1, 14) //[14:14]
+    #define REFCTRL1_REF_OVERHEAD_RATE_REFPB_ENA               Fld(1, 15) //[15:15]
+    #define REFCTRL1_REFRATE_MANUAL                            Fld(5, 16) //[20:16]
+    #define REFCTRL1_REF_OVERHEAD_SLOW_REFAL_ENA               Fld(1, 24) //[24:24]
+    #define REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA               Fld(1, 25) //[25:25]
+    #define REFCTRL1_REF_OVERHEAD_ALL_REFAL_ENA                Fld(1, 26) //[26:26]
+    #define REFCTRL1_REF_OVERHEAD_ALL_REFPB_ENA                Fld(1, 27) //[27:27]
+    #define REFCTRL1_REFRATE_MANUAL_RATE_TRIG                  Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_REF_BOUNCE1                                  (DRAMC_AO_BASE_ADDRESS + 0x026C)
+    #define REF_BOUNCE1_REFRATE_DEBOUNCE_COUNT                 Fld(8, 0) //[7:0]
+    #define REF_BOUNCE1_REFRATE_DEBOUNCE_TH                    Fld(5, 8) //[12:8]
+    #define REF_BOUNCE1_REFRATE_DEBOUNCE_OPT                   Fld(1, 13) //[13:13]
+    #define REF_BOUNCE1_REFRATE_DEBOUNCE_DIS                   Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_REF_BOUNCE2                                  (DRAMC_AO_BASE_ADDRESS + 0x0270)
+    #define REF_BOUNCE2_PRE_MR4INT_TH                          Fld(5, 0) //[4:0]
+
+#define DRAMC_REG_REFPEND1                                     (DRAMC_AO_BASE_ADDRESS + 0x0278)
+    #define REFPEND1_MPENDREFCNT_TH0                           Fld(4, 0) //[3:0]
+    #define REFPEND1_MPENDREFCNT_TH1                           Fld(4, 4) //[7:4]
+    #define REFPEND1_MPENDREFCNT_TH2                           Fld(4, 8) //[11:8]
+    #define REFPEND1_MPENDREFCNT_TH3                           Fld(4, 12) //[15:12]
+    #define REFPEND1_MPENDREFCNT_TH4                           Fld(4, 16) //[19:16]
+    #define REFPEND1_MPENDREFCNT_TH5                           Fld(4, 20) //[23:20]
+    #define REFPEND1_MPENDREFCNT_TH6                           Fld(4, 24) //[27:24]
+    #define REFPEND1_MPENDREFCNT_TH7                           Fld(4, 28) //[31:28]
+
+#define DRAMC_REG_REFPEND2                                     (DRAMC_AO_BASE_ADDRESS + 0x027C)
+    #define REFPEND2_MPENDREFCNT_TH8                           Fld(4, 0) //[3:0]
+    #define REFPEND2_MPENDREFCNT_TH9                           Fld(4, 4) //[7:4]
+    #define REFPEND2_MPENDREFCNT_TH10                          Fld(4, 8) //[11:8]
+    #define REFPEND2_MPENDREFCNT_TH11                          Fld(4, 12) //[15:12]
+    #define REFPEND2_MPENDREFCNT_TH12                          Fld(4, 16) //[19:16]
+    #define REFPEND2_MPENDREFCNT_TH13                          Fld(4, 20) //[23:20]
+    #define REFPEND2_MPENDREFCNT_TH14                          Fld(4, 24) //[27:24]
+    #define REFPEND2_MPENDREFCNT_TH15                          Fld(4, 28) //[31:28]
+
+#define DRAMC_REG_REFQUE_CNT                                   (DRAMC_AO_BASE_ADDRESS + 0x0280)
+    #define REFQUE_CNT_REFRESH_QUEUE_CNT_FROM_AO               Fld(4, 0) //[3:0]
+
+#define DRAMC_REG_SCSMCTRL                                     (DRAMC_AO_BASE_ADDRESS + 0x0284)
+    #define SCSMCTRL_SC_PG_UPD_OPT                             Fld(1, 0) //[0:0]
+    #define SCSMCTRL_SC_PG_MAN_DIS                             Fld(1, 1) //[1:1]
+    #define SCSMCTRL_SC_PG_OPT2_DIS                            Fld(1, 8) //[8:8]
+    #define SCSMCTRL_SC_PG_STCMD_AREF_DIS                      Fld(1, 9) //[9:9]
+    #define SCSMCTRL_SC_PG_MPRW_DIS                            Fld(1, 10) //[10:10]
+    #define SCSMCTRL_SCPRE                                     Fld(1, 19) //[19:19]
+
+#define DRAMC_REG_SCSMCTRL_CG                                  (DRAMC_AO_BASE_ADDRESS + 0x0288)
+    #define SCSMCTRL_CG_SCARB_SM_CGAR                          Fld(1, 30) //[30:30]
+    #define SCSMCTRL_CG_SCSM_CGAR                              Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_REFCTRL2                                     (DRAMC_AO_BASE_ADDRESS + 0x028C)
+    #define REFCTRL2_MR4INT_TH                                 Fld(5, 0) //[4:0]
+    #define REFCTRL2_PB2AB_THD                                 Fld(3, 8) //[10:8]
+    #define REFCTRL2_REF_OVERHEAD_RATE                         Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0                      (DRAMC_AO_BASE_ADDRESS + 0x0290)
+    #define TX_FREQ_RATIO_OLD_MODE0_FREQ_RATIO_TX_8            Fld(5, 0) //[4:0]
+    #define TX_FREQ_RATIO_OLD_MODE0_FREQ_RATIO_TX_9            Fld(5, 8) //[12:8]
+    #define TX_FREQ_RATIO_OLD_MODE0_FREQ_RATIO_TX_10           Fld(5, 16) //[20:16]
+    #define TX_FREQ_RATIO_OLD_MODE0_FREQ_RATIO_TX_11           Fld(5, 24) //[28:24]
+    #define TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT  Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_TX_FREQ_RATIO_OLD_MODE1                      (DRAMC_AO_BASE_ADDRESS + 0x0294)
+    #define TX_FREQ_RATIO_OLD_MODE1_FREQ_RATIO_TX_4            Fld(5, 0) //[4:0]
+    #define TX_FREQ_RATIO_OLD_MODE1_FREQ_RATIO_TX_5            Fld(5, 8) //[12:8]
+    #define TX_FREQ_RATIO_OLD_MODE1_FREQ_RATIO_TX_6            Fld(5, 16) //[20:16]
+    #define TX_FREQ_RATIO_OLD_MODE1_FREQ_RATIO_TX_7            Fld(5, 24) //[28:24]
+
+#define DRAMC_REG_TX_FREQ_RATIO_OLD_MODE2                      (DRAMC_AO_BASE_ADDRESS + 0x0298)
+    #define TX_FREQ_RATIO_OLD_MODE2_FREQ_RATIO_TX_0            Fld(5, 0) //[4:0]
+    #define TX_FREQ_RATIO_OLD_MODE2_FREQ_RATIO_TX_1            Fld(5, 8) //[12:8]
+    #define TX_FREQ_RATIO_OLD_MODE2_FREQ_RATIO_TX_2            Fld(5, 16) //[20:16]
+    #define TX_FREQ_RATIO_OLD_MODE2_FREQ_RATIO_TX_3            Fld(5, 24) //[28:24]
+
+#define DRAMC_REG_WDT_RST                                      (DRAMC_AO_BASE_ADDRESS + 0x029C)
+    #define WDT_RST_WDT_DBG_RST                                Fld(1, 0) //[0:0]
+
+#define DRAMC_REG_SEDA_LOOP_BAK_ERR_PAT_B01                    (DRAMC_AO_BASE_ADDRESS + 0x02A0)
+    #define SEDA_LOOP_BAK_ERR_PAT_B01_SEDA_LOOP_BAK_ERR_PAT0   Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_SEDA_LOOP_BAK_ERR_PAT_B23                    (DRAMC_AO_BASE_ADDRESS + 0x02A4)
+    #define SEDA_LOOP_BAK_ERR_PAT_B23_SEDA_LOOP_BAK_ERR_PAT1   Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_SEDA_LOOP_BAK_ERR_PAT_B45                    (DRAMC_AO_BASE_ADDRESS + 0x02A8)
+    #define SEDA_LOOP_BAK_ERR_PAT_B45_SEDA_LOOP_BAK_ERR_PAT2   Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_SEDA_LOOP_BAK_ERR_PAT_B67                    (DRAMC_AO_BASE_ADDRESS + 0x02AC)
+    #define SEDA_LOOP_BAK_ERR_PAT_B67_SEDA_LOOP_BAK_ERR_PAT3   Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_SEDA_LOOP_BAK_SET                            (DRAMC_AO_BASE_ADDRESS + 0x02B0)
+    #define SEDA_LOOP_BAK_SET_WPRE0T                           Fld(1, 0) //[0:0]
+    #define SEDA_LOOP_BAK_SET_DRAMC_LOOP_BAK_EN                Fld(1, 1) //[1:1]
+    #define SEDA_LOOP_BAK_SET_DRAMC_LOOP_BAK_CMP_EN            Fld(1, 2) //[2:2]
+    #define SEDA_LOOP_BAK_SET_LOOP_BAK_WDAT_SEL                Fld(3, 4) //[6:4]
+
+#define DRAMC_REG_DBG_CMDDEC_CMDSEL0                           (DRAMC_AO_BASE_ADDRESS + 0x02C0)
+    #define DBG_CMDDEC_CMDSEL0_RANK0_10GBEN                    Fld(1, 0) //[0:0]
+    #define DBG_CMDDEC_CMDSEL0_RANK1_10GBEN                    Fld(1, 1) //[1:1]
+    #define DBG_CMDDEC_CMDSEL0_DBG_CMDDEC_CMDSEL               Fld(1, 4) //[4:4]
+    #define DBG_CMDDEC_CMDSEL0_DBG_CMDDEC_CMDTYPE              Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_DBG_CMDDEC_CMDSEL1                           (DRAMC_AO_BASE_ADDRESS + 0x02C4)
+    #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_OP            Fld(8, 0) //[7:0]
+    #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_MA            Fld(8, 8) //[15:8]
+    #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_C             Fld(12, 16) //[27:16]
+    #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_RK            Fld(2, 28) //[29:28]
+    #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_SINGLE        Fld(1, 30) //[30:30]
+
+#define DRAMC_REG_DBG_CMDDEC_CMDSEL2                           (DRAMC_AO_BASE_ADDRESS + 0x02C8)
+    #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_R             Fld(17, 0) //[16:0]
+    #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_BA            Fld(3, 17) //[19:17]
+    #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_BL            Fld(1, 20) //[20:20]
+    #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_AP            Fld(1, 21) //[21:21]
+    #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_AB            Fld(1, 22) //[22:22]
+
+#define DRAMC_REG_DBG_CMDDEC_CMDSEL3                           (DRAMC_AO_BASE_ADDRESS + 0x02CC)
+    #define DBG_CMDDEC_CMDSEL3_DBG_CMDDEC_CMDSEL_CA0           Fld(8, 0) //[7:0]
+    #define DBG_CMDDEC_CMDSEL3_DBG_CMDDEC_CMDSEL_CA1           Fld(8, 8) //[15:8]
+    #define DBG_CMDDEC_CMDSEL3_DBG_CMDDEC_CMDSEL_CA2           Fld(8, 16) //[23:16]
+    #define DBG_CMDDEC_CMDSEL3_DBG_CMDDEC_CMDSEL_CA3           Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_DBG_CMDDEC_CMDSEL4                           (DRAMC_AO_BASE_ADDRESS + 0x02D0)
+    #define DBG_CMDDEC_CMDSEL4_DBG_CMDDEC_CMDSEL_CA4           Fld(8, 0) //[7:0]
+    #define DBG_CMDDEC_CMDSEL4_DBG_CMDDEC_CMDSEL_CA5           Fld(8, 8) //[15:8]
+
+#define DRAMC_REG_RTSWCMD_CNT                                  (DRAMC_AO_BASE_ADDRESS + 0x02D4)
+    #define RTSWCMD_CNT_RTSWCMD_CNT                            Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_REFCTRL3                                     (DRAMC_AO_BASE_ADDRESS + 0x02D8)
+    #define REFCTRL3_REF_DERATING_EN                           Fld(16, 0) //[15:0]
+
+#define DRAMC_REG_DRAMC_IRQ_EN                                 (DRAMC_AO_BASE_ADDRESS + 0x02E0)
+    #define DRAMC_IRQ_EN_MR4INT_EN                             Fld(1, 0) //[0:0]
+    #define DRAMC_IRQ_EN_REFPENDINGINT_EN                      Fld(1, 1) //[1:1]
+    #define DRAMC_IRQ_EN_PRE_MR4INT_EN                         Fld(1, 2) //[2:2]
+    #define DRAMC_IRQ_EN_RTMRWINT_EN                           Fld(1, 3) //[3:3]
+    #define DRAMC_IRQ_EN_INT_SREF_REQ_NO_ACK_EN                Fld(1, 6) //[6:6]
+    #define DRAMC_IRQ_EN_INT_SREF_REQ_SHORT_EN                 Fld(1, 7) //[7:7]
+    #define DRAMC_IRQ_EN_INT_SREF_REQ_DTRIG_EN                 Fld(1, 8) //[8:8]
+    #define DRAMC_IRQ_EN_RTSWCMDINT_EN                         Fld(1, 12) //[12:12]
+    #define DRAMC_IRQ_EN_TX_TRACKING_INT1_EN                   Fld(1, 16) //[16:16]
+    #define DRAMC_IRQ_EN_TX_TRACKING_INT2_EN                   Fld(1, 17) //[17:17]
+    #define DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV                      Fld(14, 18) //[31:18]
+
+#define DRAMC_REG_DRAMC_IRQ_CLEAR                              (DRAMC_AO_BASE_ADDRESS + 0x02E4)
+    #define DRAMC_IRQ_CLEAR_MR4INT_CLR                         Fld(1, 0) //[0:0]
+    #define DRAMC_IRQ_CLEAR_REFPENDINGINT_CLR                  Fld(1, 1) //[1:1]
+    #define DRAMC_IRQ_CLEAR_PRE_MR4INT_CLR                     Fld(1, 2) //[2:2]
+    #define DRAMC_IRQ_CLEAR_RTMRWINT_CLR                       Fld(1, 3) //[3:3]
+    #define DRAMC_IRQ_CLEAR_INT_SREF_REQ_NO_ACK_CLR            Fld(1, 6) //[6:6]
+    #define DRAMC_IRQ_CLEAR_INT_SREF_REQ_SHORT_CLR             Fld(1, 7) //[7:7]
+    #define DRAMC_IRQ_CLEAR_INT_SREF_REQ_DTRIG_CLR             Fld(1, 8) //[8:8]
+    #define DRAMC_IRQ_CLEAR_RTSWCMDINT_CLR                     Fld(1, 12) //[12:12]
+    #define DRAMC_IRQ_CLEAR_DRAMC_IRQ_CLEAR_RSV                Fld(19, 13) //[31:13]
+
+#define DRAMC_REG_IRQ_RSV1                                     (DRAMC_AO_BASE_ADDRESS + 0x02E8)
+    #define IRQ_RSV1_IRQ_RSV1                                  Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_IRQ_RSV2                                     (DRAMC_AO_BASE_ADDRESS + 0x02EC)
+    #define IRQ_RSV2_IRQ_RSV2                                  Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_REFCNT_FR_CLK1                               (DRAMC_AO_BASE_ADDRESS + 0x02F0)
+    #define REFCNT_FR_CLK1_REFCNT_FR_CLK_1X                    Fld(11, 0) //[10:0]
+    #define REFCNT_FR_CLK1_REFCNT_FR_CLK_2X                    Fld(11, 16) //[26:16]
+
+#define DRAMC_REG_REFCNT_FR_CLK2                               (DRAMC_AO_BASE_ADDRESS + 0x02F4)
+    #define REFCNT_FR_CLK2_REFCNT_FR_CLK_4X                    Fld(11, 0) //[10:0]
+    #define REFCNT_FR_CLK2_REFCNT_FR_CLK_8X                    Fld(11, 16) //[26:16]
+
+#define DRAMC_REG_REFCNT_FR_CLK3                               (DRAMC_AO_BASE_ADDRESS + 0x02F8)
+    #define REFCNT_FR_CLK3_REFCNT_FR_CLK_0P25X                 Fld(11, 0) //[10:0]
+    #define REFCNT_FR_CLK3_REFCNT_FR_CLK_0P5X                  Fld(11, 16) //[26:16]
+
+#define DRAMC_REG_REFCNT_FR_CLK4                               (DRAMC_AO_BASE_ADDRESS + 0x02FC)
+    #define REFCNT_FR_CLK4_REFCNT_FR_CLK_1P3X                  Fld(11, 0) //[10:0]
+    #define REFCNT_FR_CLK4_REFCNT_FR_CLK_1P7X                  Fld(11, 16) //[26:16]
+
+#define DRAMC_REG_REFCNT_FR_CLK5                               (DRAMC_AO_BASE_ADDRESS + 0x0300)
+    #define REFCNT_FR_CLK5_REFCNT_FR_CLK_2P5X                  Fld(11, 0) //[10:0]
+    #define REFCNT_FR_CLK5_REFCNT_FR_CLK_3P3X                  Fld(11, 16) //[26:16]
+
+#define DRAMC_REG_REFCNT_FR_CLK6                               (DRAMC_AO_BASE_ADDRESS + 0x0304)
+    #define REFCNT_FR_CLK6_REFCNT_FR_CLK_6X                    Fld(11, 0) //[10:0]
+    #define REFCNT_FR_CLK6_REFCNT_FR_CLK_0P7X                  Fld(11, 16) //[26:16]
+
+#define DRAMC_REG_REFCNT_FR_CLK7                               (DRAMC_AO_BASE_ADDRESS + 0x0308)
+    #define REFCNT_FR_CLK7_REFCNT_FR_CLK_0P125X                Fld(11, 0) //[10:0]
+
+#define DRAMC_REG_DCM_SUB_CTRL                                 (DRAMC_AO_BASE_ADDRESS + 0x0310)
+    #define DCM_SUB_CTRL_SUBCLK_CTRL_ZQ_CAL                    Fld(1, 0) //[0:0]
+    #define DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING               Fld(1, 1) //[1:1]
+    #define DCM_SUB_CTRL_SUBCLK_CTRL_TEST2                     Fld(1, 2) //[2:2]
+    #define DCM_SUB_CTRL_SUBCLK_CTRL_SWCMD                     Fld(1, 3) //[3:3]
+    #define DCM_SUB_CTRL_SUBCLK_CTRL_SREF                      Fld(1, 4) //[4:4]
+    #define DCM_SUB_CTRL_SUBCLK_CTRL_SHUFFLE_SM                Fld(1, 5) //[5:5]
+    #define DCM_SUB_CTRL_SUBCLK_CTRL_REF                       Fld(1, 6) //[6:6]
+    #define DCM_SUB_CTRL_SUBCLK_CTRL_PD_NEW                    Fld(1, 7) //[7:7]
+    #define DCM_SUB_CTRL_SUBCLK_CTRL_HMR4                      Fld(1, 8) //[8:8]
+    #define DCM_SUB_CTRL_SUBCLK_CTRL_DUMMY_READ                Fld(1, 9) //[9:9]
+    #define DCM_SUB_CTRL_SUBCLK_CTRL_DPD                       Fld(1, 10) //[10:10]
+    #define DCM_SUB_CTRL_SUBCLK_CTRL_CBT_WLEV                  Fld(1, 11) //[11:11]
+    #define DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK                  Fld(1, 12) //[12:12]
+
+#define DRAMC_REG_CBT_WLEV_CTRL5                               (DRAMC_AO_BASE_ADDRESS + 0x0320)
+    #define CBT_WLEV_CTRL5_NEW_CBT_CAPATEN                     Fld(1, 0) //[0:0]
+    #define CBT_WLEV_CTRL5_NEW_CBT_CAGOLDEN_SEL                Fld(3, 1) //[3:1]
+    #define CBT_WLEV_CTRL5_NEW_CBT_PAT_INTV                    Fld(8, 4) //[11:4]
+    #define CBT_WLEV_CTRL5_NEW_CBT_INVERT_NUM                  Fld(1, 12) //[12:12]
+    #define CBT_WLEV_CTRL5_NEW_CBT_PAT_NUM                     Fld(3, 13) //[15:13]
+    #define CBT_WLEV_CTRL5_NEW_CBT_CA_NUM                      Fld(4, 16) //[19:16]
+    #define CBT_WLEV_CTRL5_NEW_CBT_PAT_RKSEL                   Fld(2, 20) //[21:20]
+    #define CBT_WLEV_CTRL5_CBT_NEW_MODE                        Fld(1, 22) //[22:22]
+
+#define DRAMC_REG_DRAM_CLK_CTRL                                (DRAMC_AO_BASE_ADDRESS + 0x0330)
+    #define DRAM_CLK_CTRL_CLK_EN                               Fld(1, 0) //[0:0]
+
+#define DRAMC_REG_SCRAMBLE_CFG0                                (DRAMC_AO_BASE_ADDRESS + 0x0334)
+    #define SCRAMBLE_CFG0_SC_CFG0                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_SCRAMBLE_CFG1                                (DRAMC_AO_BASE_ADDRESS + 0x0338)
+    #define SCRAMBLE_CFG1_SC_CFG1                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_SCRAMBLE_CFG2                                (DRAMC_AO_BASE_ADDRESS + 0x033C)
+    #define SCRAMBLE_CFG2_SC_CFG2                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_SCRAMBLE_CFG3                                (DRAMC_AO_BASE_ADDRESS + 0x0340)
+    #define SCRAMBLE_CFG3_SC_CFG3                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_SCRAMBLE_CFG4                                (DRAMC_AO_BASE_ADDRESS + 0x0344)
+    #define SCRAMBLE_CFG4_SC_CFG4                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_SCRAMBLE_CFG5                                (DRAMC_AO_BASE_ADDRESS + 0x0348)
+    #define SCRAMBLE_CFG5_SC_CFG5                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_SCRAMBLE_CFG6                                (DRAMC_AO_BASE_ADDRESS + 0x034C)
+    #define SCRAMBLE_CFG6_SC_CFG6                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_SCRAMBLE_CFG7                                (DRAMC_AO_BASE_ADDRESS + 0x0350)
+    #define SCRAMBLE_CFG7_SC_CFG7                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_SCRAMBLE_CFG8                                (DRAMC_AO_BASE_ADDRESS + 0x0354)
+    #define SCRAMBLE_CFG8_SC_CMP_EN0                           Fld(1, 0) //[0:0]
+    #define SCRAMBLE_CFG8_SC_CMP_TYPE0                         Fld(1, 2) //[2:2]
+    #define SCRAMBLE_CFG8_SC_CMP_EN1                           Fld(1, 4) //[4:4]
+    #define SCRAMBLE_CFG8_SC_CMP_TYPE1                         Fld(1, 6) //[6:6]
+    #define SCRAMBLE_CFG8_SC_CMP_EN2                           Fld(1, 8) //[8:8]
+    #define SCRAMBLE_CFG8_SC_CMP_TYPE2                         Fld(1, 10) //[10:10]
+    #define SCRAMBLE_CFG8_SC_CMP_EN3                           Fld(1, 12) //[12:12]
+    #define SCRAMBLE_CFG8_SC_CMP_TYPE3                         Fld(1, 14) //[14:14]
+    #define SCRAMBLE_CFG8_SC_DDR_TYPE                          Fld(1, 16) //[16:16]
+    #define SCRAMBLE_CFG8_SC_EX32_EN                           Fld(1, 17) //[17:17]
+    #define SCRAMBLE_CFG8_SC_RETRUN_HUSKY                      Fld(1, 19) //[19:19]
+    #define SCRAMBLE_CFG8_SC_EN                                Fld(1, 24) //[24:24]
+    #define SCRAMBLE_CFG8_SC_CMP_SEL                           Fld(2, 28) //[29:28]
+
+#define DRAMC_REG_SCRAMBLE_CFG9                                (DRAMC_AO_BASE_ADDRESS + 0x0358)
+    #define SCRAMBLE_CFG9_SC_DWADDR_3                          Fld(16, 0) //[15:0]
+    #define SCRAMBLE_CFG9_SC_UPADDR_3                          Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_SCRAMBLE_CFGA                                (DRAMC_AO_BASE_ADDRESS + 0x035C)
+    #define SCRAMBLE_CFGA_SC_DWADDR_2                          Fld(16, 0) //[15:0]
+    #define SCRAMBLE_CFGA_SC_UPADDR_2                          Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_SCRAMBLE_CFGB                                (DRAMC_AO_BASE_ADDRESS + 0x0360)
+    #define SCRAMBLE_CFGB_SC_DWADDR_1                          Fld(16, 0) //[15:0]
+    #define SCRAMBLE_CFGB_SC_UPADDR_1                          Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_SCRAMBLE_CFGC                                (DRAMC_AO_BASE_ADDRESS + 0x0364)
+    #define SCRAMBLE_CFGC_SC_DWADDR_0                          Fld(16, 0) //[15:0]
+    #define SCRAMBLE_CFGC_SC_UPADDR_0                          Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_SCRAMBLE_CFGD                                (DRAMC_AO_BASE_ADDRESS + 0x0368)
+    #define SCRAMBLE_CFGD_SC_CFGD                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_SCRAMBLE_CFGE                                (DRAMC_AO_BASE_ADDRESS + 0x036C)
+    #define SCRAMBLE_CFGE_SC_CFGE                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_SCRAMBLE_CFGF                                (DRAMC_AO_BASE_ADDRESS + 0x0370)
+    #define SCRAMBLE_CFGF_SC_CFGF                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK_TEST2_A1                                  (DRAMC_AO_BASE_ADDRESS + 0x0500)
+    #define RK_TEST2_A1_TEST2_BASE                             Fld(29, 3) //[31:3]
+
+#define DRAMC_REG_RK_DUMMY_RD_WDATA0                           (DRAMC_AO_BASE_ADDRESS + 0x0504)
+    #define RK_DUMMY_RD_WDATA0_DMY_RD_WDATA0                   Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK_DUMMY_RD_WDATA1                           (DRAMC_AO_BASE_ADDRESS + 0x0508)
+    #define RK_DUMMY_RD_WDATA1_DMY_RD_WDATA1                   Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK_DUMMY_RD_WDATA2                           (DRAMC_AO_BASE_ADDRESS + 0x050C)
+    #define RK_DUMMY_RD_WDATA2_DMY_RD_WDATA2                   Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK_DUMMY_RD_WDATA3                           (DRAMC_AO_BASE_ADDRESS + 0x0510)
+    #define RK_DUMMY_RD_WDATA3_DMY_RD_WDATA3                   Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK_DUMMY_RD_ADR                              (DRAMC_AO_BASE_ADDRESS + 0x0514)
+    #define RK_DUMMY_RD_ADR_DMY_RD_COL_ADR                     Fld(11, 17) //[27:17]
+    #define RK_DUMMY_RD_ADR_DMY_RD_LEN                         Fld(4, 28) //[31:28]
+
+#define DRAMC_REG_RK_DUMMY_RD_ADR2                             (DRAMC_AO_BASE_ADDRESS + 0x0554)
+    #define RK_DUMMY_RD_ADR2_DMY_RD_BK                         Fld(4, 0) //[3:0]
+    #define RK_DUMMY_RD_ADR2_DMY_RD_ROW_ADR                    Fld(18, 4) //[21:4]
+
+#define DRAMC_REG_RK_SREF_DPD_TCK_RK_CTRL                      (DRAMC_AO_BASE_ADDRESS + 0x0568)
+    #define RK_SREF_DPD_TCK_RK_CTRL_DPD_EN                     Fld(1, 29) //[29:29]
+    #define RK_SREF_DPD_TCK_RK_CTRL_DPDX_EN                    Fld(1, 30) //[30:30]
+    #define RK_SREF_DPD_TCK_RK_CTRL_SRF_EN                     Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_RK_DQSOSC                                    (DRAMC_AO_BASE_ADDRESS + 0x0590)
+    #define RK_DQSOSC_RK0_BYTE_MODE                            Fld(1, 29) //[29:29]
+    #define RK_DQSOSC_DQSOSCR_RK0EN                            Fld(1, 30) //[30:30]
+    #define RK_DQSOSC_DQSOSC_RK0INTCLR                         Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_WDT_DBG_SIGNAL                               (DRAMC_AO_BASE_ADDRESS + 0x0D00)
+    #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_CPT2_RK0_FROM_AO Fld(1, 0) //[0:0]
+    #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_CPT2_RK1_FROM_AO Fld(1, 1) //[1:1]
+    #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_ERR2_RK0_FROM_AO Fld(1, 2) //[2:2]
+    #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_ERR2_RK1_FROM_AO Fld(1, 3) //[3:3]
+    #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DLE_CNT_OK2_RK0_FROM_AO Fld(1, 4) //[4:4]
+    #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DLE_CNT_OK2_RK1_FROM_AO Fld(1, 5) //[5:5]
+    #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_CPT2_RK0_FROM_AO Fld(1, 8) //[8:8]
+    #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_CPT2_RK1_FROM_AO Fld(1, 9) //[9:9]
+    #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_ERR2_RK0_FROM_AO Fld(1, 10) //[10:10]
+    #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_ERR2_RK1_FROM_AO Fld(1, 11) //[11:11]
+    #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DLE_CNT_OK2_RK0_FROM_AO Fld(1, 12) //[12:12]
+    #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DLE_CNT_OK2_RK1_FROM_AO Fld(1, 13) //[13:13]
+    #define WDT_DBG_SIGNAL_LATCH_DRAMC_GATING_ERROR_FROM_AO    Fld(1, 14) //[14:14]
+
+#define DRAMC_REG_SELFREF_HWSAVE_FLAG                          (DRAMC_AO_BASE_ADDRESS + 0x0D08)
+    #define SELFREF_HWSAVE_FLAG_SELFREF_HWSAVE_FLAG_FROM_AO    Fld(1, 0) //[0:0]
+
+#define DRAMC_REG_DRAMC_IRQ_STATUS1                            (DRAMC_AO_BASE_ADDRESS + 0x0F00)
+    #define DRAMC_IRQ_STATUS1_DRAMC_IRQ_STATUS1_X0             Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DRAMC_IRQ_STATUS2                            (DRAMC_AO_BASE_ADDRESS + 0x0F04)
+    #define DRAMC_IRQ_STATUS2_DRAMC_IRQ_STATUS2_X0             Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DRAMC_IRQ_INFO1                              (DRAMC_AO_BASE_ADDRESS + 0x0F10)
+    #define DRAMC_IRQ_INFO1_REFRESH_RATE_FOR_INT_X0            Fld(5, 0) //[4:0]
+    #define DRAMC_IRQ_INFO1_REFRESH_QUEUE_CNT_FOR_INT_X0       Fld(4, 8) //[11:8]
+    #define DRAMC_IRQ_INFO1_REFRESH_RATE_CHG_QUEUE_CNT_FOR_INT_X0 Fld(4, 12) //[15:12]
+
+#define DRAMC_REG_DRAMC_IRQ_INFO1A                             (DRAMC_AO_BASE_ADDRESS + 0x0F14)
+    #define DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK0_FOR_INT_X0   Fld(5, 0) //[4:0]
+    #define DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK1_FOR_INT_X0   Fld(5, 8) //[12:8]
+    #define DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK0_B1_FOR_INT_X0 Fld(5, 16) //[20:16]
+    #define DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK1_B1_FOR_INT_X0 Fld(5, 24) //[28:24]
+
+#define DRAMC_REG_DRAMC_IRQ_INFO2                              (DRAMC_AO_BASE_ADDRESS + 0x0F20)
+    #define DRAMC_IRQ_INFO2_RK0_MR18_INT1_X0                   Fld(16, 0) //[15:0]
+    #define DRAMC_IRQ_INFO2_RK0_MR19_INT1_X0                   Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_DRAMC_IRQ_INFO3                              (DRAMC_AO_BASE_ADDRESS + 0x0F24)
+    #define DRAMC_IRQ_INFO3_RK1_MR18_INT1_X0                   Fld(16, 0) //[15:0]
+    #define DRAMC_IRQ_INFO3_RK1_MR19_INT1_X0                   Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_DRAMC_IRQ_INFO4                              (DRAMC_AO_BASE_ADDRESS + 0x0F28)
+    #define DRAMC_IRQ_INFO4_RK0_MR18_INT2_X0                   Fld(16, 0) //[15:0]
+    #define DRAMC_IRQ_INFO4_RK0_MR19_INT2_X0                   Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_DRAMC_IRQ_INFO5                              (DRAMC_AO_BASE_ADDRESS + 0x0F2C)
+    #define DRAMC_IRQ_INFO5_RK1_MR18_INT2_X0                   Fld(16, 0) //[15:0]
+    #define DRAMC_IRQ_INFO5_RK1_MR19_INT2_X0                   Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_SHURK_SELPH_DQ0                              (DRAMC_AO_BASE_ADDRESS + 0x1200)
+    #define SHURK_SELPH_DQ0_TXDLY_DQ0                          Fld(3, 0) //[2:0]
+    #define SHURK_SELPH_DQ0_TXDLY_DQ1                          Fld(3, 4) //[6:4]
+    #define SHURK_SELPH_DQ0_TXDLY_DQ2                          Fld(3, 8) //[10:8]
+    #define SHURK_SELPH_DQ0_TXDLY_DQ3                          Fld(3, 12) //[14:12]
+    #define SHURK_SELPH_DQ0_TXDLY_OEN_DQ0                      Fld(3, 16) //[18:16]
+    #define SHURK_SELPH_DQ0_TXDLY_OEN_DQ1                      Fld(3, 20) //[22:20]
+    #define SHURK_SELPH_DQ0_TXDLY_OEN_DQ2                      Fld(3, 24) //[26:24]
+    #define SHURK_SELPH_DQ0_TXDLY_OEN_DQ3                      Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_SHURK_SELPH_DQ1                              (DRAMC_AO_BASE_ADDRESS + 0x1204)
+    #define SHURK_SELPH_DQ1_TXDLY_DQM0                         Fld(3, 0) //[2:0]
+    #define SHURK_SELPH_DQ1_TXDLY_DQM1                         Fld(3, 4) //[6:4]
+    #define SHURK_SELPH_DQ1_TXDLY_DQM2                         Fld(3, 8) //[10:8]
+    #define SHURK_SELPH_DQ1_TXDLY_DQM3                         Fld(3, 12) //[14:12]
+    #define SHURK_SELPH_DQ1_TXDLY_OEN_DQM0                     Fld(3, 16) //[18:16]
+    #define SHURK_SELPH_DQ1_TXDLY_OEN_DQM1                     Fld(3, 20) //[22:20]
+    #define SHURK_SELPH_DQ1_TXDLY_OEN_DQM2                     Fld(3, 24) //[26:24]
+    #define SHURK_SELPH_DQ1_TXDLY_OEN_DQM3                     Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_SHURK_SELPH_DQ2                              (DRAMC_AO_BASE_ADDRESS + 0x1208)
+    #define SHURK_SELPH_DQ2_DLY_DQ0                            Fld(4, 0) //[3:0]
+    #define SHURK_SELPH_DQ2_DLY_DQ1                            Fld(4, 4) //[7:4]
+    #define SHURK_SELPH_DQ2_DLY_DQ2                            Fld(4, 8) //[11:8]
+    #define SHURK_SELPH_DQ2_DLY_DQ3                            Fld(4, 12) //[15:12]
+    #define SHURK_SELPH_DQ2_DLY_OEN_DQ0                        Fld(4, 16) //[19:16]
+    #define SHURK_SELPH_DQ2_DLY_OEN_DQ1                        Fld(4, 20) //[23:20]
+    #define SHURK_SELPH_DQ2_DLY_OEN_DQ2                        Fld(4, 24) //[27:24]
+    #define SHURK_SELPH_DQ2_DLY_OEN_DQ3                        Fld(4, 28) //[31:28]
+
+#define DRAMC_REG_SHURK_SELPH_DQ3                              (DRAMC_AO_BASE_ADDRESS + 0x120C)
+    #define SHURK_SELPH_DQ3_DLY_DQM0                           Fld(4, 0) //[3:0]
+    #define SHURK_SELPH_DQ3_DLY_DQM1                           Fld(4, 4) //[7:4]
+    #define SHURK_SELPH_DQ3_DLY_DQM2                           Fld(4, 8) //[11:8]
+    #define SHURK_SELPH_DQ3_DLY_DQM3                           Fld(4, 12) //[15:12]
+    #define SHURK_SELPH_DQ3_DLY_OEN_DQM0                       Fld(4, 16) //[19:16]
+    #define SHURK_SELPH_DQ3_DLY_OEN_DQM1                       Fld(4, 20) //[23:20]
+    #define SHURK_SELPH_DQ3_DLY_OEN_DQM2                       Fld(4, 24) //[27:24]
+    #define SHURK_SELPH_DQ3_DLY_OEN_DQM3                       Fld(4, 28) //[31:28]
+
+#define DRAMC_REG_SHURK_DQS2DQ_CAL1                            (DRAMC_AO_BASE_ADDRESS + 0x1210)
+    #define SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0             Fld(11, 0) //[10:0]
+    #define SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1             Fld(11, 16) //[26:16]
+
+#define DRAMC_REG_SHURK_DQS2DQ_CAL2                            (DRAMC_AO_BASE_ADDRESS + 0x1214)
+    #define SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0             Fld(11, 0) //[10:0]
+    #define SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1             Fld(11, 16) //[26:16]
+
+#define DRAMC_REG_SHURK_DQS2DQ_CAL3                            (DRAMC_AO_BASE_ADDRESS + 0x1218)
+    #define SHURK_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0         Fld(6, 0) //[5:0]
+    #define SHURK_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1         Fld(6, 6) //[11:6]
+    #define SHURK_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0   Fld(5, 12) //[16:12]
+    #define SHURK_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0   Fld(5, 17) //[21:17]
+
+#define DRAMC_REG_SHURK_DQS2DQ_CAL4                            (DRAMC_AO_BASE_ADDRESS + 0x121C)
+    #define SHURK_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0        Fld(6, 0) //[5:0]
+    #define SHURK_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1        Fld(6, 6) //[11:6]
+    #define SHURK_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0  Fld(5, 12) //[16:12]
+    #define SHURK_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0  Fld(5, 17) //[21:17]
+
+#define DRAMC_REG_SHURK_DQS2DQ_CAL5                            (DRAMC_AO_BASE_ADDRESS + 0x1220)
+    #define SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0            Fld(11, 0) //[10:0]
+    #define SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1            Fld(11, 16) //[26:16]
+
+#define DRAMC_REG_SHURK_PI                                     (DRAMC_AO_BASE_ADDRESS + 0x1224)
+    #define SHURK_PI_RK0_ARPI_DQ_B1                            Fld(6, 0) //[5:0]
+    #define SHURK_PI_RK0_ARPI_DQ_B0                            Fld(6, 8) //[13:8]
+    #define SHURK_PI_RK0_ARPI_DQM_B1                           Fld(6, 16) //[21:16]
+    #define SHURK_PI_RK0_ARPI_DQM_B0                           Fld(6, 24) //[29:24]
+
+#define DRAMC_REG_SHURK_DQSOSC                                 (DRAMC_AO_BASE_ADDRESS + 0x1228)
+    #define SHURK_DQSOSC_DQSOSC_BASE_RK0                       Fld(16, 0) //[15:0]
+    #define SHURK_DQSOSC_DQSOSC_BASE_RK0_B1                    Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_SHURK_DQSOSC_THRD                            (DRAMC_AO_BASE_ADDRESS + 0x122C)
+    #define SHURK_DQSOSC_THRD_DQSOSCTHRD_INC                   Fld(12, 0) //[11:0]
+    #define SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC                   Fld(12, 16) //[27:16]
+
+#define DRAMC_REG_SHURK_APHY_TX_PICG_CTRL                      (DRAMC_AO_BASE_ADDRESS + 0x1230)
+    #define SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 Fld(3, 0) //[2:0]
+    #define SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 Fld(3, 4) //[6:4]
+
+#define DRAMC_REG_SHURK_WCK_WR_MCK                             (DRAMC_AO_BASE_ADDRESS + 0x1240)
+    #define SHURK_WCK_WR_MCK_WCK_WR_B0_MCK                     Fld(4, 0) //[3:0]
+    #define SHURK_WCK_WR_MCK_WCK_WR_B1_MCK                     Fld(4, 4) //[7:4]
+
+#define DRAMC_REG_SHURK_WCK_RD_MCK                             (DRAMC_AO_BASE_ADDRESS + 0x1244)
+    #define SHURK_WCK_RD_MCK_WCK_RD_B0_MCK                     Fld(4, 0) //[3:0]
+    #define SHURK_WCK_RD_MCK_WCK_RD_B1_MCK                     Fld(4, 4) //[7:4]
+
+#define DRAMC_REG_SHURK_WCK_FS_MCK                             (DRAMC_AO_BASE_ADDRESS + 0x1248)
+    #define SHURK_WCK_FS_MCK_WCK_FS_B0_MCK                     Fld(4, 0) //[3:0]
+    #define SHURK_WCK_FS_MCK_WCK_FS_B1_MCK                     Fld(4, 4) //[7:4]
+
+#define DRAMC_REG_SHURK_WCK_WR_UI                              (DRAMC_AO_BASE_ADDRESS + 0x124C)
+    #define SHURK_WCK_WR_UI_WCK_WR_B0_UI                       Fld(4, 0) //[3:0]
+    #define SHURK_WCK_WR_UI_WCK_WR_B1_UI                       Fld(4, 4) //[7:4]
+
+#define DRAMC_REG_SHURK_WCK_RD_UI                              (DRAMC_AO_BASE_ADDRESS + 0x1250)
+    #define SHURK_WCK_RD_UI_WCK_RD_B0_UI                       Fld(4, 0) //[3:0]
+    #define SHURK_WCK_RD_UI_WCK_RD_B1_UI                       Fld(4, 4) //[7:4]
+
+#define DRAMC_REG_SHURK_WCK_FS_UI                              (DRAMC_AO_BASE_ADDRESS + 0x1254)
+    #define SHURK_WCK_FS_UI_WCK_FS_B0_UI                       Fld(4, 0) //[3:0]
+    #define SHURK_WCK_FS_UI_WCK_FS_B1_UI                       Fld(4, 4) //[7:4]
+
+#define DRAMC_REG_SHURK_CKE_CTRL                               (DRAMC_AO_BASE_ADDRESS + 0x1260)
+    #define SHURK_CKE_CTRL_CKE_DBE_CNT                         Fld(4, 0) //[3:0]
+
+#define DRAMC_REG_SHU_MATYPE                                   (DRAMC_AO_BASE_ADDRESS + 0x1600)
+    #define SHU_MATYPE_MATYPE                                  Fld(2, 0) //[1:0]
+    #define SHU_MATYPE_NORMPOP_LEN                             Fld(3, 4) //[6:4]
+
+#define DRAMC_REG_SHU_COMMON0                                  (DRAMC_AO_BASE_ADDRESS + 0x1604)
+    #define SHU_COMMON0_FREQDIV4                               Fld(1, 0) //[0:0]
+    #define SHU_COMMON0_FDIV2                                  Fld(1, 1) //[1:1]
+    #define SHU_COMMON0_FREQDIV8                               Fld(1, 2) //[2:2]
+    #define SHU_COMMON0_DM64BITEN                              Fld(1, 4) //[4:4]
+    #define SHU_COMMON0_DLE256EN                               Fld(1, 5) //[5:5]
+    #define SHU_COMMON0_LP5BGEN                                Fld(1, 6) //[6:6]
+    #define SHU_COMMON0_LP5WCKON                               Fld(1, 7) //[7:7]
+    #define SHU_COMMON0_CL2                                    Fld(1, 8) //[8:8]
+    #define SHU_COMMON0_BL2                                    Fld(1, 9) //[9:9]
+    #define SHU_COMMON0_BL4                                    Fld(1, 10) //[10:10]
+    #define SHU_COMMON0_LP5BGOTF                               Fld(1, 11) //[11:11]
+    #define SHU_COMMON0_BC4OTF                                 Fld(1, 12) //[12:12]
+    #define SHU_COMMON0_LP5HEFF_MODE                           Fld(1, 13) //[13:13]
+    #define SHU_COMMON0_LP5WRAPEN                              Fld(1, 14) //[14:14]
+    #define SHU_COMMON0_SHU_COMMON0_RSV                        Fld(17, 15) //[31:15]
+
+#define DRAMC_REG_SHU_SREF_CTRL                                (DRAMC_AO_BASE_ADDRESS + 0x1608)
+    #define SHU_SREF_CTRL_CKEHCMD                              Fld(2, 4) //[5:4]
+    #define SHU_SREF_CTRL_SREF_CK_DLY                          Fld(2, 28) //[29:28]
+
+#define DRAMC_REG_SHU_SCHEDULER                                (DRAMC_AO_BASE_ADDRESS + 0x160C)
+    #define SHU_SCHEDULER_DUALSCHEN                            Fld(1, 2) //[2:2]
+
+#define DRAMC_REG_SHU_DCM_CTRL0                                (DRAMC_AO_BASE_ADDRESS + 0x1610)
+    #define SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT                    Fld(1, 7) //[7:7]
+    #define SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT                Fld(3, 8) //[10:8]
+    #define SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL            Fld(4, 12) //[15:12]
+    #define SHU_DCM_CTRL0_APHYPI_CKCGL_CNT                     Fld(4, 16) //[19:16]
+    #define SHU_DCM_CTRL0_APHYPI_CKCGH_CNT                     Fld(4, 20) //[23:20]
+    #define SHU_DCM_CTRL0_FASTWAKE2                            Fld(1, 29) //[29:29]
+    #define SHU_DCM_CTRL0_FASTWAKE                             Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_SHU_HMR4_DVFS_CTRL0                          (DRAMC_AO_BASE_ADDRESS + 0x1614)
+    #define SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT                  Fld(8, 8) //[15:8]
+    #define SHU_HMR4_DVFS_CTRL0_REFRCNT                        Fld(12, 16) //[27:16]
+
+#define DRAMC_REG_SHU_SELPH_CA1                                (DRAMC_AO_BASE_ADDRESS + 0x1618)
+    #define SHU_SELPH_CA1_TXDLY_CS                             Fld(3, 0) //[2:0]
+    #define SHU_SELPH_CA1_TXDLY_CKE                            Fld(3, 4) //[6:4]
+    #define SHU_SELPH_CA1_TXDLY_ODT                            Fld(3, 8) //[10:8]
+    #define SHU_SELPH_CA1_TXDLY_RESET                          Fld(3, 12) //[14:12]
+    #define SHU_SELPH_CA1_TXDLY_WE                             Fld(3, 16) //[18:16]
+    #define SHU_SELPH_CA1_TXDLY_CAS                            Fld(3, 20) //[22:20]
+    #define SHU_SELPH_CA1_TXDLY_RAS                            Fld(3, 24) //[26:24]
+    #define SHU_SELPH_CA1_TXDLY_CS1                            Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_SHU_SELPH_CA2                                (DRAMC_AO_BASE_ADDRESS + 0x161C)
+    #define SHU_SELPH_CA2_TXDLY_BA0                            Fld(3, 0) //[2:0]
+    #define SHU_SELPH_CA2_TXDLY_BA1                            Fld(3, 4) //[6:4]
+    #define SHU_SELPH_CA2_TXDLY_BA2                            Fld(3, 8) //[10:8]
+    #define SHU_SELPH_CA2_TXDLY_CMD                            Fld(5, 16) //[20:16]
+    #define SHU_SELPH_CA2_TXDLY_CKE1                           Fld(3, 24) //[26:24]
+
+#define DRAMC_REG_SHU_SELPH_CA3                                (DRAMC_AO_BASE_ADDRESS + 0x1620)
+    #define SHU_SELPH_CA3_TXDLY_RA0                            Fld(3, 0) //[2:0]
+    #define SHU_SELPH_CA3_TXDLY_RA1                            Fld(3, 4) //[6:4]
+    #define SHU_SELPH_CA3_TXDLY_RA2                            Fld(3, 8) //[10:8]
+    #define SHU_SELPH_CA3_TXDLY_RA3                            Fld(3, 12) //[14:12]
+    #define SHU_SELPH_CA3_TXDLY_RA4                            Fld(3, 16) //[18:16]
+    #define SHU_SELPH_CA3_TXDLY_RA5                            Fld(3, 20) //[22:20]
+    #define SHU_SELPH_CA3_TXDLY_RA6                            Fld(3, 24) //[26:24]
+    #define SHU_SELPH_CA3_TXDLY_RA7                            Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_SHU_SELPH_CA4                                (DRAMC_AO_BASE_ADDRESS + 0x1624)
+    #define SHU_SELPH_CA4_TXDLY_RA8                            Fld(3, 0) //[2:0]
+    #define SHU_SELPH_CA4_TXDLY_RA9                            Fld(3, 4) //[6:4]
+    #define SHU_SELPH_CA4_TXDLY_RA10                           Fld(3, 8) //[10:8]
+    #define SHU_SELPH_CA4_TXDLY_RA11                           Fld(3, 12) //[14:12]
+    #define SHU_SELPH_CA4_TXDLY_RA12                           Fld(3, 16) //[18:16]
+    #define SHU_SELPH_CA4_TXDLY_RA13                           Fld(3, 20) //[22:20]
+    #define SHU_SELPH_CA4_TXDLY_RA14                           Fld(3, 24) //[26:24]
+    #define SHU_SELPH_CA4_TXDLY_RA15                           Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_SHU_SELPH_CA5                                (DRAMC_AO_BASE_ADDRESS + 0x1628)
+    #define SHU_SELPH_CA5_DLY_CS                               Fld(3, 0) //[2:0]
+    #define SHU_SELPH_CA5_DLY_CKE                              Fld(3, 4) //[6:4]
+    #define SHU_SELPH_CA5_DLY_ODT                              Fld(3, 8) //[10:8]
+    #define SHU_SELPH_CA5_DLY_RESET                            Fld(3, 12) //[14:12]
+    #define SHU_SELPH_CA5_DLY_WE                               Fld(3, 16) //[18:16]
+    #define SHU_SELPH_CA5_DLY_CAS                              Fld(3, 20) //[22:20]
+    #define SHU_SELPH_CA5_DLY_RAS                              Fld(3, 24) //[26:24]
+    #define SHU_SELPH_CA5_DLY_CS1                              Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_SHU_SELPH_CA6                                (DRAMC_AO_BASE_ADDRESS + 0x162C)
+    #define SHU_SELPH_CA6_DLY_BA0                              Fld(3, 0) //[2:0]
+    #define SHU_SELPH_CA6_DLY_BA1                              Fld(3, 4) //[6:4]
+    #define SHU_SELPH_CA6_DLY_BA2                              Fld(3, 8) //[10:8]
+    #define SHU_SELPH_CA6_DLY_CKE1                             Fld(3, 24) //[26:24]
+
+#define DRAMC_REG_SHU_SELPH_CA7                                (DRAMC_AO_BASE_ADDRESS + 0x1630)
+    #define SHU_SELPH_CA7_DLY_RA0                              Fld(3, 0) //[2:0]
+    #define SHU_SELPH_CA7_DLY_RA1                              Fld(3, 4) //[6:4]
+    #define SHU_SELPH_CA7_DLY_RA2                              Fld(3, 8) //[10:8]
+    #define SHU_SELPH_CA7_DLY_RA3                              Fld(3, 12) //[14:12]
+    #define SHU_SELPH_CA7_DLY_RA4                              Fld(3, 16) //[18:16]
+    #define SHU_SELPH_CA7_DLY_RA5                              Fld(3, 20) //[22:20]
+    #define SHU_SELPH_CA7_DLY_RA6                              Fld(3, 24) //[26:24]
+    #define SHU_SELPH_CA7_DLY_RA7                              Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_SHU_SELPH_CA8                                (DRAMC_AO_BASE_ADDRESS + 0x1634)
+    #define SHU_SELPH_CA8_DLY_RA8                              Fld(3, 0) //[2:0]
+    #define SHU_SELPH_CA8_DLY_RA9                              Fld(3, 4) //[6:4]
+    #define SHU_SELPH_CA8_DLY_RA10                             Fld(3, 8) //[10:8]
+    #define SHU_SELPH_CA8_DLY_RA11                             Fld(3, 12) //[14:12]
+    #define SHU_SELPH_CA8_DLY_RA12                             Fld(3, 16) //[18:16]
+    #define SHU_SELPH_CA8_DLY_RA13                             Fld(3, 20) //[22:20]
+    #define SHU_SELPH_CA8_DLY_RA14                             Fld(3, 24) //[26:24]
+    #define SHU_SELPH_CA8_DLY_RA15                             Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_SHU_HWSET_MR2                                (DRAMC_AO_BASE_ADDRESS + 0x1638)
+    #define SHU_HWSET_MR2_HWSET_MR2_MRSMA                      Fld(13, 0) //[12:0]
+    #define SHU_HWSET_MR2_HWSET_MR2_OP                         Fld(8, 16) //[23:16]
+
+#define DRAMC_REG_SHU_HWSET_MR13                               (DRAMC_AO_BASE_ADDRESS + 0x163C)
+    #define SHU_HWSET_MR13_HWSET_MR13_MRSMA                    Fld(13, 0) //[12:0]
+    #define SHU_HWSET_MR13_HWSET_MR13_OP                       Fld(8, 16) //[23:16]
+
+#define DRAMC_REG_SHU_HWSET_VRCG                               (DRAMC_AO_BASE_ADDRESS + 0x1640)
+    #define SHU_HWSET_VRCG_HWSET_VRCG_MRSMA                    Fld(13, 0) //[12:0]
+    #define SHU_HWSET_VRCG_HWSET_VRCG_OP                       Fld(8, 16) //[23:16]
+    #define SHU_HWSET_VRCG_VRCGDIS_PRDCNT                      Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_SHU_ACTIM0                                   (DRAMC_AO_BASE_ADDRESS + 0x1644)
+    #define SHU_ACTIM0_TWTR                                    Fld(6, 0) //[5:0]
+    #define SHU_ACTIM0_TWR                                     Fld(8, 8) //[15:8]
+    #define SHU_ACTIM0_TRRD                                    Fld(3, 16) //[18:16]
+    #define SHU_ACTIM0_TRCD                                    Fld(4, 24) //[27:24]
+    #define SHU_ACTIM0_CKELCKCNT                               Fld(4, 28) //[31:28]
+
+#define DRAMC_REG_SHU_ACTIM1                                   (DRAMC_AO_BASE_ADDRESS + 0x1648)
+    #define SHU_ACTIM1_TRPAB                                   Fld(4, 0) //[3:0]
+    #define SHU_ACTIM1_TMRWCKEL                                Fld(4, 4) //[7:4]
+    #define SHU_ACTIM1_TRP                                     Fld(4, 8) //[11:8]
+    #define SHU_ACTIM1_TRAS                                    Fld(6, 16) //[21:16]
+    #define SHU_ACTIM1_TRC                                     Fld(5, 24) //[28:24]
+
+#define DRAMC_REG_SHU_ACTIM2                                   (DRAMC_AO_BASE_ADDRESS + 0x164C)
+    #define SHU_ACTIM2_TXP                                     Fld(4, 0) //[3:0]
+    #define SHU_ACTIM2_TMRRI                                   Fld(5, 4) //[8:4]
+    #define SHU_ACTIM2_TRTP                                    Fld(3, 12) //[14:12]
+    #define SHU_ACTIM2_TR2W                                    Fld(6, 16) //[21:16]
+    #define SHU_ACTIM2_TFAW                                    Fld(5, 24) //[28:24]
+
+#define DRAMC_REG_SHU_ACTIM3                                   (DRAMC_AO_BASE_ADDRESS + 0x1650)
+    #define SHU_ACTIM3_TRFCPB                                  Fld(8, 0) //[7:0]
+    #define SHU_ACTIM3_MANTMRR                                 Fld(4, 8) //[11:8]
+    #define SHU_ACTIM3_TR2MRR                                  Fld(4, 12) //[15:12]
+    #define SHU_ACTIM3_TRFC                                    Fld(8, 16) //[23:16]
+    #define SHU_ACTIM3_TWTR_L                                  Fld(6, 24) //[29:24]
+
+#define DRAMC_REG_SHU_ACTIM4                                   (DRAMC_AO_BASE_ADDRESS + 0x1654)
+    #define SHU_ACTIM4_TXREFCNT                                Fld(10, 0) //[9:0]
+    #define SHU_ACTIM4_TMRR2MRW                                Fld(6, 10) //[15:10]
+    #define SHU_ACTIM4_TMRR2W                                  Fld(6, 16) //[21:16]
+    #define SHU_ACTIM4_TZQCS                                   Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_SHU_ACTIM5                                   (DRAMC_AO_BASE_ADDRESS + 0x1658)
+    #define SHU_ACTIM5_TR2PD                                   Fld(7, 0) //[6:0]
+    #define SHU_ACTIM5_TWTPD                                   Fld(7, 8) //[14:8]
+    #define SHU_ACTIM5_TPBR2PBR                                Fld(8, 16) //[23:16]
+    #define SHU_ACTIM5_TPBR2ACT                                Fld(2, 28) //[29:28]
+
+#define DRAMC_REG_SHU_ACTIM6                                   (DRAMC_AO_BASE_ADDRESS + 0x165C)
+    #define SHU_ACTIM6_TZQLAT2                                 Fld(5, 0) //[4:0]
+    #define SHU_ACTIM6_TMRD                                    Fld(4, 8) //[11:8]
+    #define SHU_ACTIM6_TMRW                                    Fld(4, 12) //[15:12]
+    #define SHU_ACTIM6_TW2MRW                                  Fld(6, 20) //[25:20]
+    #define SHU_ACTIM6_TR2MRW                                  Fld(6, 26) //[31:26]
+
+#define DRAMC_REG_SHU_ACTIM_XRT                                (DRAMC_AO_BASE_ADDRESS + 0x1660)
+    #define SHU_ACTIM_XRT_XRTR2R                               Fld(5, 0) //[4:0]
+    #define SHU_ACTIM_XRT_XRTR2W                               Fld(6, 8) //[13:8]
+    #define SHU_ACTIM_XRT_XRTW2R                               Fld(4, 16) //[19:16]
+    #define SHU_ACTIM_XRT_XRTW2W                               Fld(5, 24) //[28:24]
+
+#define DRAMC_REG_SHU_AC_TIME_05T                              (DRAMC_AO_BASE_ADDRESS + 0x1664)
+    #define SHU_AC_TIME_05T_TRC_05T                            Fld(1, 0) //[0:0]
+    #define SHU_AC_TIME_05T_TRFCPB_05T                         Fld(1, 1) //[1:1]
+    #define SHU_AC_TIME_05T_TRFC_05T                           Fld(1, 2) //[2:2]
+    #define SHU_AC_TIME_05T_TPBR2PBR_05T                       Fld(1, 3) //[3:3]
+    #define SHU_AC_TIME_05T_TXP_05T                            Fld(1, 4) //[4:4]
+    #define SHU_AC_TIME_05T_TRTP_05T                           Fld(1, 5) //[5:5]
+    #define SHU_AC_TIME_05T_TRCD_05T                           Fld(1, 6) //[6:6]
+    #define SHU_AC_TIME_05T_TRP_05T                            Fld(1, 7) //[7:7]
+    #define SHU_AC_TIME_05T_TRPAB_05T                          Fld(1, 8) //[8:8]
+    #define SHU_AC_TIME_05T_TRAS_05T                           Fld(1, 9) //[9:9]
+    #define SHU_AC_TIME_05T_TWR_M05T                           Fld(1, 10) //[10:10]
+    #define SHU_AC_TIME_05T_TRRD_05T                           Fld(1, 12) //[12:12]
+    #define SHU_AC_TIME_05T_TFAW_05T                           Fld(1, 13) //[13:13]
+    #define SHU_AC_TIME_05T_TCKEPRD_05T                        Fld(1, 14) //[14:14]
+    #define SHU_AC_TIME_05T_TR2PD_05T                          Fld(1, 15) //[15:15]
+    #define SHU_AC_TIME_05T_TWTPD_M05T                         Fld(1, 16) //[16:16]
+    #define SHU_AC_TIME_05T_TMRRI_05T                          Fld(1, 17) //[17:17]
+    #define SHU_AC_TIME_05T_TMRWCKEL_05T                       Fld(1, 18) //[18:18]
+    #define SHU_AC_TIME_05T_BGTRRD_05T                         Fld(1, 19) //[19:19]
+    #define SHU_AC_TIME_05T_BGTCCD_05T                         Fld(1, 20) //[20:20]
+    #define SHU_AC_TIME_05T_BGTWTR_M05T                        Fld(1, 21) //[21:21]
+    #define SHU_AC_TIME_05T_TR2W_05T                           Fld(1, 22) //[22:22]
+    #define SHU_AC_TIME_05T_TWTR_M05T                          Fld(1, 23) //[23:23]
+    #define SHU_AC_TIME_05T_XRTR2W_05T                         Fld(1, 24) //[24:24]
+    #define SHU_AC_TIME_05T_TMRD_05T                           Fld(1, 25) //[25:25]
+    #define SHU_AC_TIME_05T_TMRW_05T                           Fld(1, 26) //[26:26]
+    #define SHU_AC_TIME_05T_TMRR2MRW_05T                       Fld(1, 27) //[27:27]
+    #define SHU_AC_TIME_05T_TW2MRW_05T                         Fld(1, 28) //[28:28]
+    #define SHU_AC_TIME_05T_TR2MRW_05T                         Fld(1, 29) //[29:29]
+    #define SHU_AC_TIME_05T_TPBR2ACT_05T                       Fld(1, 30) //[30:30]
+    #define SHU_AC_TIME_05T_XRTW2R_M05T                        Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_SHU_AC_DERATING0                             (DRAMC_AO_BASE_ADDRESS + 0x1668)
+    #define SHU_AC_DERATING0_ACDERATEEN                        Fld(1, 0) //[0:0]
+    #define SHU_AC_DERATING0_TRRD_DERATE                       Fld(3, 16) //[18:16]
+    #define SHU_AC_DERATING0_TRCD_DERATE                       Fld(4, 24) //[27:24]
+
+#define DRAMC_REG_SHU_AC_DERATING1                             (DRAMC_AO_BASE_ADDRESS + 0x166C)
+    #define SHU_AC_DERATING1_TRPAB_DERATE                      Fld(4, 0) //[3:0]
+    #define SHU_AC_DERATING1_TRP_DERATE                        Fld(4, 8) //[11:8]
+    #define SHU_AC_DERATING1_TRAS_DERATE                       Fld(6, 16) //[21:16]
+    #define SHU_AC_DERATING1_TRC_DERATE                        Fld(5, 24) //[28:24]
+
+#define DRAMC_REG_SHU_AC_DERATING_05T                          (DRAMC_AO_BASE_ADDRESS + 0x1670)
+    #define SHU_AC_DERATING_05T_TRC_05T_DERATE                 Fld(1, 0) //[0:0]
+    #define SHU_AC_DERATING_05T_TRCD_05T_DERATE                Fld(1, 6) //[6:6]
+    #define SHU_AC_DERATING_05T_TRP_05T_DERATE                 Fld(1, 7) //[7:7]
+    #define SHU_AC_DERATING_05T_TRPAB_05T_DERATE               Fld(1, 8) //[8:8]
+    #define SHU_AC_DERATING_05T_TRAS_05T_DERATE                Fld(1, 9) //[9:9]
+    #define SHU_AC_DERATING_05T_TRRD_05T_DERATE                Fld(1, 12) //[12:12]
+
+#define DRAMC_REG_SHU_ACTIMING_CONF                            (DRAMC_AO_BASE_ADDRESS + 0x1674)
+    #define SHU_ACTIMING_CONF_SCINTV                           Fld(6, 0) //[5:0]
+    #define SHU_ACTIMING_CONF_TRFCPBIG                         Fld(1, 8) //[8:8]
+    #define SHU_ACTIMING_CONF_REFBW_FR                         Fld(10, 16) //[25:16]
+    #define SHU_ACTIMING_CONF_TREFBWIG                         Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_SHU_CKECTRL                                  (DRAMC_AO_BASE_ADDRESS + 0x1678)
+    #define SHU_CKECTRL_TPDE_05T                               Fld(1, 0) //[0:0]
+    #define SHU_CKECTRL_TPDX_05T                               Fld(1, 1) //[1:1]
+    #define SHU_CKECTRL_TPDE                                   Fld(3, 12) //[14:12]
+    #define SHU_CKECTRL_TPDX                                   Fld(3, 16) //[18:16]
+    #define SHU_CKECTRL_TCKEPRD                                Fld(3, 20) //[22:20]
+    #define SHU_CKECTRL_TCKESRX                                Fld(2, 24) //[25:24]
+
+#define DRAMC_REG_SHU_SELPH_DQS0                               (DRAMC_AO_BASE_ADDRESS + 0x167C)
+    #define SHU_SELPH_DQS0_TXDLY_DQS0                          Fld(3, 0) //[2:0]
+    #define SHU_SELPH_DQS0_TXDLY_DQS1                          Fld(3, 4) //[6:4]
+    #define SHU_SELPH_DQS0_TXDLY_DQS2                          Fld(3, 8) //[10:8]
+    #define SHU_SELPH_DQS0_TXDLY_DQS3                          Fld(3, 12) //[14:12]
+    #define SHU_SELPH_DQS0_TXDLY_OEN_DQS0                      Fld(3, 16) //[18:16]
+    #define SHU_SELPH_DQS0_TXDLY_OEN_DQS1                      Fld(3, 20) //[22:20]
+    #define SHU_SELPH_DQS0_TXDLY_OEN_DQS2                      Fld(3, 24) //[26:24]
+    #define SHU_SELPH_DQS0_TXDLY_OEN_DQS3                      Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_SHU_SELPH_DQS1                               (DRAMC_AO_BASE_ADDRESS + 0x1680)
+    #define SHU_SELPH_DQS1_DLY_DQS0                            Fld(4, 0) //[3:0]
+    #define SHU_SELPH_DQS1_DLY_DQS1                            Fld(4, 4) //[7:4]
+    #define SHU_SELPH_DQS1_DLY_DQS2                            Fld(4, 8) //[11:8]
+    #define SHU_SELPH_DQS1_DLY_DQS3                            Fld(4, 12) //[15:12]
+    #define SHU_SELPH_DQS1_DLY_OEN_DQS0                        Fld(4, 16) //[19:16]
+    #define SHU_SELPH_DQS1_DLY_OEN_DQS1                        Fld(4, 20) //[23:20]
+    #define SHU_SELPH_DQS1_DLY_OEN_DQS2                        Fld(4, 24) //[27:24]
+    #define SHU_SELPH_DQS1_DLY_OEN_DQS3                        Fld(4, 28) //[31:28]
+
+#define DRAMC_REG_SHU_WODT                                     (DRAMC_AO_BASE_ADDRESS + 0x1684)
+    #define SHU_WODT_DISWODT                                   Fld(3, 0) //[2:0]
+    #define SHU_WODT_WODTFIX                                   Fld(1, 3) //[3:3]
+    #define SHU_WODT_WODTFIXOFF                                Fld(1, 4) //[4:4]
+    #define SHU_WODT_DISWODTE                                  Fld(1, 5) //[5:5]
+    #define SHU_WODT_DISWODTE2                                 Fld(1, 6) //[6:6]
+    #define SHU_WODT_WODTPDEN                                  Fld(1, 7) //[7:7]
+    #define SHU_WODT_WOEN                                      Fld(1, 8) //[8:8]
+    #define SHU_WODT_DQS2DQ_WARN_PITHRD                        Fld(6, 9) //[14:9]
+    #define SHU_WODT_TWODT                                     Fld(7, 16) //[22:16]
+
+#define DRAMC_REG_SHU_TX_SET0                                  (DRAMC_AO_BASE_ADDRESS + 0x1688)
+    #define SHU_TX_SET0_DQOE_CNT                               Fld(4, 0) //[3:0]
+    #define SHU_TX_SET0_DQOE_OPT                               Fld(1, 4) //[4:4]
+    #define SHU_TX_SET0_WR_NEW_OPT                             Fld(1, 5) //[5:5]
+    #define SHU_TX_SET0_TXUPD_SEL                              Fld(2, 6) //[7:6]
+    #define SHU_TX_SET0_TXUPD_W2R_SEL                          Fld(3, 8) //[10:8]
+    #define SHU_TX_SET0_WECC_EN                                Fld(1, 11) //[11:11]
+    #define SHU_TX_SET0_DBIWR                                  Fld(1, 12) //[12:12]
+    #define SHU_TX_SET0_WDATRGO                                Fld(1, 13) //[13:13]
+    #define SHU_TX_SET0_TXUPD_W2R_OPT                          Fld(1, 14) //[14:14]
+    #define SHU_TX_SET0_WPST1P5T                               Fld(1, 15) //[15:15]
+    #define SHU_TX_SET0_TXOEN_AUTOSET_OFFSET                   Fld(4, 16) //[19:16]
+    #define SHU_TX_SET0_TWCKPST                                Fld(2, 20) //[21:20]
+    #define SHU_TX_SET0_OE_EXT2UI                              Fld(3, 22) //[24:22]
+    #define SHU_TX_SET0_DQS2DQ_FILT_PITHRD                     Fld(6, 25) //[30:25]
+    #define SHU_TX_SET0_TXOEN_AUTOSET_EN                       Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_SHU_RX_CG_SET0                               (DRAMC_AO_BASE_ADDRESS + 0x168C)
+    #define SHU_RX_CG_SET0_DLE_LAST_EXTEND3                    Fld(1, 0) //[0:0]
+    #define SHU_RX_CG_SET0_READ_START_EXTEND3                  Fld(1, 1) //[1:1]
+    #define SHU_RX_CG_SET0_DLE_LAST_EXTEND2                    Fld(1, 2) //[2:2]
+    #define SHU_RX_CG_SET0_READ_START_EXTEND2                  Fld(1, 3) //[3:3]
+    #define SHU_RX_CG_SET0_DLE_LAST_EXTEND1                    Fld(1, 4) //[4:4]
+    #define SHU_RX_CG_SET0_READ_START_EXTEND1                  Fld(1, 5) //[5:5]
+
+#define DRAMC_REG_SHU_DQSOSC_SET0                              (DRAMC_AO_BASE_ADDRESS + 0x1690)
+    #define SHU_DQSOSC_SET0_DQSOSCENDIS                        Fld(1, 0) //[0:0]
+    #define SHU_DQSOSC_SET0_DQSOSC_PRDCNT                      Fld(10, 4) //[13:4]
+    #define SHU_DQSOSC_SET0_DQSOSCENCNT                        Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_SHU_DQSOSCR                                  (DRAMC_AO_BASE_ADDRESS + 0x1694)
+    #define SHU_DQSOSCR_DQSOSCRCNT                             Fld(8, 0) //[7:0]
+    #define SHU_DQSOSCR_DQSOSC_ADV_SEL                         Fld(2, 8) //[9:8]
+    #define SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL                     Fld(2, 10) //[11:10]
+    #define SHU_DQSOSCR_TX_SW_FORCE_UPD_SEL                    Fld(3, 12) //[14:12]
+    #define SHU_DQSOSCR_DQSOSC_DELTA                           Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_SHU_TX_RANKCTL                               (DRAMC_AO_BASE_ADDRESS + 0x1698)
+    #define SHU_TX_RANKCTL_TXRANKINCTL_TXDLY                   Fld(4, 0) //[3:0]
+    #define SHU_TX_RANKCTL_TXRANKINCTL                         Fld(4, 4) //[7:4]
+    #define SHU_TX_RANKCTL_TXRANKINCTL_ROOT                    Fld(4, 8) //[11:8]
+
+#define DRAMC_REG_SHU_ZQ_SET0                                  (DRAMC_AO_BASE_ADDRESS + 0x169C)
+    #define SHU_ZQ_SET0_ZQCSCNT                                Fld(16, 0) //[15:0]
+    #define SHU_ZQ_SET0_TZQLAT                                 Fld(5, 27) //[31:27]
+
+#define DRAMC_REG_SHU_CONF0                                    (DRAMC_AO_BASE_ADDRESS + 0x16A0)
+    #define SHU_CONF0_DMPGTIM                                  Fld(7, 0) //[6:0]
+    #define SHU_CONF0_ADVPREEN                                 Fld(1, 7) //[7:7]
+    #define SHU_CONF0_PBREFEN                                  Fld(1, 8) //[8:8]
+    #define SHU_CONF0_REFTHD                                   Fld(4, 12) //[15:12]
+    #define SHU_CONF0_REQQUE_DEPTH                             Fld(4, 16) //[19:16]
+    #define SHU_CONF0_ADVREFEN                                 Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_SHU_MISC                                     (DRAMC_AO_BASE_ADDRESS + 0x16A4)
+    #define SHU_MISC_REQQUE_MAXCNT                             Fld(4, 0) //[3:0]
+    #define SHU_MISC_DCMDLYREF                                 Fld(3, 16) //[18:16]
+    #define SHU_MISC_DAREFEN                                   Fld(1, 30) //[30:30]
+
+#define DRAMC_REG_SHU_NEW_XRW2W_CTRL                           (DRAMC_AO_BASE_ADDRESS + 0x16A8)
+    #define SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0                 Fld(3, 16) //[18:16]
+    #define SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1                 Fld(3, 24) //[26:24]
+    #define SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE                   Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_SHU_APHY_TX_PICG_CTRL                        (DRAMC_AO_BASE_ADDRESS + 0x16AC)
+    #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT Fld(4, 0) //[3:0]
+    #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 Fld(3, 4) //[6:4]
+    #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 Fld(3, 8) //[10:8]
+    #define SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT           Fld(4, 12) //[15:12]
+    #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT    Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_SHU_FREQ_RATIO_SET0                          (DRAMC_AO_BASE_ADDRESS + 0x16B0)
+    #define SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3             Fld(8, 0) //[7:0]
+    #define SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2             Fld(8, 8) //[15:8]
+    #define SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1             Fld(8, 16) //[23:16]
+    #define SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0             Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_SHU_FREQ_RATIO_SET1                          (DRAMC_AO_BASE_ADDRESS + 0x16B4)
+    #define SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7             Fld(8, 0) //[7:0]
+    #define SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6             Fld(8, 8) //[15:8]
+    #define SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5             Fld(8, 16) //[23:16]
+    #define SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4             Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_SHU_FREQ_RATIO_SET2                          (DRAMC_AO_BASE_ADDRESS + 0x16B8)
+    #define SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9             Fld(8, 16) //[23:16]
+    #define SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8             Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_SHUREG_RSV                                   (DRAMC_AO_BASE_ADDRESS + 0x16BC)
+    #define SHUREG_RSV_SHUREG_RSV                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_SHU_WCKCTRL                                  (DRAMC_AO_BASE_ADDRESS + 0x16C0)
+    #define SHU_WCKCTRL_WCKRDOFF                               Fld(6, 0) //[5:0]
+    #define SHU_WCKCTRL_WCKRDOFF_05T                           Fld(1, 7) //[7:7]
+    #define SHU_WCKCTRL_WCKWROFF                               Fld(6, 8) //[13:8]
+    #define SHU_WCKCTRL_WCKWROFF_05T                           Fld(1, 15) //[15:15]
+    #define SHU_WCKCTRL_WCKDUAL                                Fld(1, 16) //[16:16]
+
+#define DRAMC_REG_SHU_WCKCTRL_1                                (DRAMC_AO_BASE_ADDRESS + 0x16C4)
+    #define SHU_WCKCTRL_1_WCKSYNC_PRE_MODE                     Fld(1, 0) //[0:0]
+
+#define DRAMC_REG_SHU_RX_SET0                                  (DRAMC_AO_BASE_ADDRESS + 0x16D0)
+    #define SHU_RX_SET0_RECC_EN                                Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_SHU_REF0                                     (DRAMC_AO_BASE_ADDRESS + 0x16D4)
+    #define SHU_REF0_MPENDREF_CNT                              Fld(3, 0) //[2:0]
+
+#define DRAMC_REG_SHU_LP5_CMD                                  (DRAMC_AO_BASE_ADDRESS + 0x16E0)
+    #define SHU_LP5_CMD_LP5_CMD1TO2EN                          Fld(1, 0) //[0:0]
+    #define SHU_LP5_CMD_TCSH                                   Fld(4, 4) //[7:4]
+
+#define DRAMC_REG_SHU_LP5_SACT                                 (DRAMC_AO_BASE_ADDRESS + 0x16E4)
+    #define SHU_LP5_SACT_LP5_SEPARATE_ACT                      Fld(1, 0) //[0:0]
+
+#define DRAMC_REG_SHU_ACTIM7                                   (DRAMC_AO_BASE_ADDRESS + 0x16E8)
+    #define SHU_ACTIM7_TCSH_CSCAL                              Fld(4, 0) //[3:0]
+    #define SHU_ACTIM7_TCACSH                                  Fld(4, 4) //[7:4]
+
+#endif // __DRAMC_AO_REGS_H__
diff --git a/src/vendorcode/mediatek/mt8195/include/8195_Register_DRAMC_NAO.h b/src/vendorcode/mediatek/mt8195/include/8195_Register_DRAMC_NAO.h
new file mode 100644
index 000000000000..96964de8d648
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/8195_Register_DRAMC_NAO.h
@@ -0,0 +1,1079 @@
+#ifndef __DRAMC_NAO_REGS_H__
+#define __DRAMC_NAO_REGS_H__
+
+#define Channel_A_DRAMC_NAO_BASE_ADDRESS    0x10234000
+#define Channel_B_DRAMC_NAO_BASE_ADDRESS    0x10244000
+
+#define DRAMC_NAO_BASE_ADDRESS     Channel_A_DRAMC_NAO_BASE_VIRTUAL
+
+#define DRAMC_REG_TESTMODE                                     (DRAMC_NAO_BASE_ADDRESS + 0x0000)
+    #define TESTMODE_TESTM_PAT0                                Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_RDQC_CMP                                     (DRAMC_NAO_BASE_ADDRESS + 0x0014)
+    #define RDQC_CMP_RDDQC_CMP0_ERR                            Fld(16, 0) //[15:0]
+    #define RDQC_CMP_RDDQC_CMP1_ERR                            Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_RDQC_DQM_CMP                                 (DRAMC_NAO_BASE_ADDRESS + 0x0018)
+    #define RDQC_DQM_CMP_RDDQC_DQM_CMP0_ERR                    Fld(2, 0) //[1:0]
+    #define RDQC_DQM_CMP_RDDQC_DQM_CMP1_ERR                    Fld(2, 2) //[3:2]
+
+#define DRAMC_REG_DMMONITOR                                    (DRAMC_NAO_BASE_ADDRESS + 0x0024)
+    #define DMMONITOR_MONPAUSE_SW                              Fld(1, 2) //[2:2]
+    #define DMMONITOR_BUSMONEN_SW                              Fld(1, 3) //[3:3]
+    #define DMMONITOR_WDQ_MON_OPT                              Fld(1, 4) //[4:4]
+    #define DMMONITOR_REQQUE_MON_SREF_DIS                      Fld(1, 8) //[8:8]
+    #define DMMONITOR_REQQUE_MON_SREF_REOR                     Fld(1, 9) //[9:9]
+    #define DMMONITOR_REQQUE_MON_SREF_LLAT                     Fld(1, 10) //[10:10]
+    #define DMMONITOR_REQQUE_MON_SREF_HPRI                     Fld(1, 11) //[11:11]
+    #define DMMONITOR_REQQUE_MON_SREF_RW                       Fld(1, 12) //[12:12]
+    #define DMMONITOR_EBG_PGHIT_COUNTER_CLR                    Fld(1, 16) //[16:16]
+
+#define DRAMC_REG_INITK_PAT0                                   (DRAMC_NAO_BASE_ADDRESS + 0x0030)
+    #define INITK_PAT0_INITK_PAT0                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_INITK_PAT1                                   (DRAMC_NAO_BASE_ADDRESS + 0x0034)
+    #define INITK_PAT1_INITK_PAT1                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_INITK_PAT2                                   (DRAMC_NAO_BASE_ADDRESS + 0x0038)
+    #define INITK_PAT2_INITK_PAT2                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_INITK_PAT3                                   (DRAMC_NAO_BASE_ADDRESS + 0x003C)
+    #define INITK_PAT3_INITK_PAT3                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_INITK_PAT4                                   (DRAMC_NAO_BASE_ADDRESS + 0x0040)
+    #define INITK_PAT4_INITK_PAT4                              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_SPCMDRESP3                                   (DRAMC_NAO_BASE_ADDRESS + 0x0050)
+    #define SPCMDRESP3_RTSWCMD_RESPONSE                        Fld(1, 0) //[0:0]
+    #define SPCMDRESP3_ZQC_SWTRIG_RESPONSE                     Fld(1, 1) //[1:1]
+    #define SPCMDRESP3_ZQLAT_SWTRIG_RESPONSE                   Fld(1, 2) //[2:2]
+    #define SPCMDRESP3_WCK2DQI_START_SWTRIG_RESPONSE           Fld(1, 3) //[3:3]
+    #define SPCMDRESP3_WCK2DQO_START_SWTRIG_RESPONSE           Fld(1, 4) //[4:4]
+    #define SPCMDRESP3_DVFS_RTMRW_RESPONSE                     Fld(1, 5) //[5:5]
+
+#define DRAMC_REG_CBT_WLEV_STATUS2                             (DRAMC_NAO_BASE_ADDRESS + 0x0054)
+    #define CBT_WLEV_STATUS2_CBT_PAT_CMP_CPT                   Fld(1, 0) //[0:0]
+    #define CBT_WLEV_STATUS2_CBT_PAT_CMP_ERR_B0                Fld(7, 1) //[7:1]
+    #define CBT_WLEV_STATUS2_CBT_PAT_RDAT_B0                   Fld(7, 8) //[14:8]
+    #define CBT_WLEV_STATUS2_CBT_PAT_CMP_ERR_B1                Fld(7, 15) //[21:15]
+    #define CBT_WLEV_STATUS2_CBT_PAT_RDAT_B1                   Fld(7, 22) //[28:22]
+
+#define DRAMC_REG_MISC_STATUSA                                 (DRAMC_NAO_BASE_ADDRESS + 0x0080)
+    #define MISC_STATUSA_WAIT_DLE                              Fld(1, 0) //[0:0]
+    #define MISC_STATUSA_WRITE_DATA_BUFFER_EMPTY               Fld(1, 1) //[1:1]
+    #define MISC_STATUSA_REQQ_EMPTY                            Fld(1, 2) //[2:2]
+    #define MISC_STATUSA_PG_VLD                                Fld(1, 3) //[3:3]
+    #define MISC_STATUSA_REQQUE_DEPTH                          Fld(4, 4) //[7:4]
+    #define MISC_STATUSA_REFRESH_RATE                          Fld(5, 8) //[12:8]
+    #define MISC_STATUSA_CKEO_PRE                              Fld(1, 13) //[13:13]
+    #define MISC_STATUSA_CKE1O_PRE                             Fld(1, 14) //[14:14]
+    #define MISC_STATUSA_SREF_STATE                            Fld(1, 16) //[16:16]
+    #define MISC_STATUSA_SELFREF_SM                            Fld(3, 17) //[19:17]
+    #define MISC_STATUSA_REFRESH_OVER_CNT                      Fld(4, 20) //[23:20]
+    #define MISC_STATUSA_REFRESH_QUEUE_CNT                     Fld(4, 24) //[27:24]
+    #define MISC_STATUSA_REQDEPTH_UPD_DONE                     Fld(1, 28) //[28:28]
+    #define MISC_STATUSA_DRAMC_IDLE_STATUS                     Fld(1, 30) //[30:30]
+    #define MISC_STATUSA_DRAMC_IDLE_DCM                        Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_SPECIAL_STATUS                               (DRAMC_NAO_BASE_ADDRESS + 0x0084)
+    #define SPECIAL_STATUS_SPECIAL_COMMAND_ENABLE              Fld(1, 0) //[0:0]
+    #define SPECIAL_STATUS_H_ZQLAT_REQ                         Fld(1, 1) //[1:1]
+    #define SPECIAL_STATUS_H_ZQLCAL_REQ                        Fld(1, 2) //[2:2]
+    #define SPECIAL_STATUS_TX_RETRY_PERIOD                     Fld(1, 3) //[3:3]
+    #define SPECIAL_STATUS_H_DQSOSCEN_REQ                      Fld(1, 4) //[4:4]
+    #define SPECIAL_STATUS_DQSOSCEN_PERIOD                     Fld(1, 5) //[5:5]
+    #define SPECIAL_STATUS_H_ZQCS_REQ                          Fld(1, 6) //[6:6]
+    #define SPECIAL_STATUS_H_REFR_REQ                          Fld(1, 7) //[7:7]
+    #define SPECIAL_STATUS_HW_ZQLAT_REQ                        Fld(1, 9) //[9:9]
+    #define SPECIAL_STATUS_HW_ZQCAL_REQ                        Fld(1, 10) //[10:10]
+    #define SPECIAL_STATUS_SPECIAL_STATUS                      Fld(1, 11) //[11:11]
+    #define SPECIAL_STATUS_SCSM                                Fld(5, 12) //[16:12]
+    #define SPECIAL_STATUS_XSR_TX_RETRY_SM                     Fld(3, 17) //[19:17]
+    #define SPECIAL_STATUS_SCARB_SM                            Fld(5, 20) //[24:20]
+    #define SPECIAL_STATUS_TX_RETRY_PERIOD_WO_RX_RETRY         Fld(1, 25) //[25:25]
+    #define SPECIAL_STATUS_DSM_REQ_2Q                          Fld(1, 26) //[26:26]
+    #define SPECIAL_STATUS_DSM_REQ                             Fld(1, 27) //[27:27]
+    #define SPECIAL_STATUS_SC_DRAMC_QUEUE_ACK                  Fld(1, 28) //[28:28]
+    #define SPECIAL_STATUS_SREF_REQ_2Q                         Fld(1, 30) //[30:30]
+    #define SPECIAL_STATUS_SREF_REQ                            Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_SPCMDRESP                                    (DRAMC_NAO_BASE_ADDRESS + 0x0088)
+    #define SPCMDRESP_MRW_RESPONSE                             Fld(1, 0) //[0:0]
+    #define SPCMDRESP_MRR_RESPONSE                             Fld(1, 1) //[1:1]
+    #define SPCMDRESP_PREA_RESPONSE                            Fld(1, 2) //[2:2]
+    #define SPCMDRESP_AREF_RESPONSE                            Fld(1, 3) //[3:3]
+    #define SPCMDRESP_ZQC_RESPONSE                             Fld(1, 4) //[4:4]
+    #define SPCMDRESP_TCMD_RESPONSE                            Fld(1, 5) //[5:5]
+    #define SPCMDRESP_ZQLAT_RESPONSE                           Fld(1, 6) //[6:6]
+    #define SPCMDRESP_RDDQC_RESPONSE                           Fld(1, 7) //[7:7]
+    #define SPCMDRESP_STEST_RESPONSE                           Fld(1, 8) //[8:8]
+    #define SPCMDRESP_MPCMAN_RESPONSE                          Fld(1, 9) //[9:9]
+    #define SPCMDRESP_DQSOSCEN_RESPONSE                        Fld(1, 10) //[10:10]
+    #define SPCMDRESP_DQSOSCDIS_RESPONSE                       Fld(1, 11) //[11:11]
+    #define SPCMDRESP_ACT_RESPONSE                             Fld(1, 12) //[12:12]
+    #define SPCMDRESP_MPRW_RESPONSE                            Fld(1, 13) //[13:13]
+    #define SPCMDRESP_TX_RETRY_DONE_RESPONSE                   Fld(1, 15) //[15:15]
+    #define SPCMDRESP_DVFS_RESPONSE                            Fld(1, 16) //[16:16]
+    #define SPCMDRESP_HW_ZQLAT_POP                             Fld(1, 17) //[17:17]
+    #define SPCMDRESP_HW_ZQCAL_POP                             Fld(1, 18) //[18:18]
+    #define SPCMDRESP_RTMRW_RESPONSE                           Fld(1, 19) //[19:19]
+    #define SPCMDRESP_RTMRW_REQ_CNT                            Fld(3, 20) //[22:20]
+    #define SPCMDRESP_RTMRW_ACK_CNT                            Fld(3, 23) //[25:23]
+    #define SPCMDRESP_RTMRW_POP_CNT                            Fld(3, 26) //[28:26]
+    #define SPCMDRESP_RDFIFO_RESPONSE                          Fld(1, 30) //[30:30]
+    #define SPCMDRESP_WRFIFO_RESPONSE                          Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_MRR_STATUS                                   (DRAMC_NAO_BASE_ADDRESS + 0x008C)
+    #define MRR_STATUS_MRR_REG                                 Fld(16, 0) //[15:0]
+    #define MRR_STATUS_MRR_SW_REG                              Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_MRR_STATUS2                                  (DRAMC_NAO_BASE_ADDRESS + 0x0090)
+    #define MRR_STATUS2_MR4_REG                                Fld(16, 0) //[15:0]
+    #define MRR_STATUS2_SHUFFLE_MRW_VRCG_NORMAL_OK             Fld(1, 16) //[16:16]
+    #define MRR_STATUS2_TFC_OK                                 Fld(1, 17) //[17:17]
+    #define MRR_STATUS2_TCKFSPX_OK                             Fld(1, 18) //[18:18]
+    #define MRR_STATUS2_TVRCG_EN_OK                            Fld(1, 19) //[19:19]
+    #define MRR_STATUS2_TCKFSPE_OK                             Fld(1, 20) //[20:20]
+    #define MRR_STATUS2_TVRCG_DIS_OK                           Fld(1, 21) //[21:21]
+    #define MRR_STATUS2_PHY_SHUFFLE_PERIOD_GO_ZERO_OK          Fld(1, 22) //[22:22]
+    #define MRR_STATUS2_DVFS_STATE                             Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MRRDATA0                                     (DRAMC_NAO_BASE_ADDRESS + 0x0094)
+    #define MRRDATA0_MRR_DATA0                                 Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_MRRDATA1                                     (DRAMC_NAO_BASE_ADDRESS + 0x0098)
+    #define MRRDATA1_MRR_DATA1                                 Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_MRRDATA2                                     (DRAMC_NAO_BASE_ADDRESS + 0x009C)
+    #define MRRDATA2_MRR_DATA2                                 Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_MRRDATA3                                     (DRAMC_NAO_BASE_ADDRESS + 0x00A0)
+    #define MRRDATA3_MRR_DATA3                                 Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_REF_STATUS                                   (DRAMC_NAO_BASE_ADDRESS + 0x00A4)
+    #define REF_STATUS_REFRATE_INT_TRIGGER1                    Fld(1, 0) //[0:0]
+    #define REF_STATUS_REFRATE_INT_TRIGGER2                    Fld(1, 1) //[1:1]
+    #define REF_STATUS_PRE_REFRATE_INT_TRIGGER1                Fld(1, 2) //[2:2]
+    #define REF_STATUS_REFPENDING_INT_TRIGGER_1                Fld(1, 3) //[3:3]
+    #define REF_STATUS_REFPENDING_INT_TRIGGER_2                Fld(1, 4) //[4:4]
+
+#define DRAMC_REG_WCK_STATUS                                   (DRAMC_NAO_BASE_ADDRESS + 0x00B0)
+    #define WCK_STATUS_WCKEN_RK0_SM                            Fld(2, 0) //[1:0]
+    #define WCK_STATUS_WCKEN_RK1_SM                            Fld(2, 2) //[3:2]
+
+#define DRAMC_REG_TCMDO1LAT                                    (DRAMC_NAO_BASE_ADDRESS + 0x00C0)
+    #define TCMDO1LAT_MANUTXUPD_B0_DONE                        Fld(1, 6) //[6:6]
+    #define TCMDO1LAT_MANUTXUPD_B1_DONE                        Fld(1, 7) //[7:7]
+
+#define DRAMC_REG_CBT_WLEV_STATUS1                             (DRAMC_NAO_BASE_ADDRESS + 0x00C4)
+    #define CBT_WLEV_STATUS1_CATRAIN_CMP_CPT                   Fld(1, 0) //[0:0]
+    #define CBT_WLEV_STATUS1_CATRAIN_CMP_ERR_B0                Fld(7, 1) //[7:1]
+    #define CBT_WLEV_STATUS1_CATRAIN_RDAT_B0                   Fld(7, 8) //[14:8]
+    #define CBT_WLEV_STATUS1_CATRAIN_CMP_ERR_B1                Fld(7, 15) //[21:15]
+    #define CBT_WLEV_STATUS1_CATRAIN_RDAT_B1                   Fld(7, 22) //[28:22]
+
+#define DRAMC_REG_CBT_WLEV_STATUS                              (DRAMC_NAO_BASE_ADDRESS + 0x00C8)
+    #define CBT_WLEV_STATUS_WLEV_CMP_CPT                       Fld(1, 0) //[0:0]
+    #define CBT_WLEV_STATUS_WLEV_CMP_ERR                       Fld(2, 1) //[2:1]
+    #define CBT_WLEV_STATUS_TCMD_CMP_ERR_B0                    Fld(1, 3) //[3:3]
+    #define CBT_WLEV_STATUS_TCMD_CMP_ERR_B1                    Fld(1, 4) //[4:4]
+    #define CBT_WLEV_STATUS_TCMD_O1_LATCH_DATA_B0              Fld(7, 5) //[11:5]
+    #define CBT_WLEV_STATUS_TCMD_O1_LATCH_DATA_B1              Fld(7, 12) //[18:12]
+    #define CBT_WLEV_STATUS_CBT_WLEV_ATK_CNT                   Fld(6, 19) //[24:19]
+    #define CBT_WLEV_STATUS_CBT_WLEV_ATK_RESPONSE              Fld(1, 25) //[25:25]
+
+#define DRAMC_REG_SPCMDRESP2                                   (DRAMC_NAO_BASE_ADDRESS + 0x00CC)
+    #define SPCMDRESP2_RTMRW_ABNORMAL_STOP                     Fld(1, 0) //[0:0]
+
+#define DRAMC_REG_CBT_WLEV_ATK_RESULT0                         (DRAMC_NAO_BASE_ADDRESS + 0x00D0)
+    #define CBT_WLEV_ATK_RESULT0_CBT_WLEV_ATK_CMP_ERR0         Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CBT_WLEV_ATK_RESULT1                         (DRAMC_NAO_BASE_ADDRESS + 0x00D4)
+    #define CBT_WLEV_ATK_RESULT1_CBT_WLEV_ATK_CMP_ERR1         Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CBT_WLEV_ATK_RESULT2                         (DRAMC_NAO_BASE_ADDRESS + 0x00D8)
+    #define CBT_WLEV_ATK_RESULT2_CBT_WLEV_ATK_CMP_ERR2         Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CBT_WLEV_ATK_RESULT3                         (DRAMC_NAO_BASE_ADDRESS + 0x00DC)
+    #define CBT_WLEV_ATK_RESULT3_CBT_WLEV_ATK_CMP_ERR3         Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CBT_WLEV_ATK_RESULT4                         (DRAMC_NAO_BASE_ADDRESS + 0x00E0)
+    #define CBT_WLEV_ATK_RESULT4_CBT_WLEV_ATK_CMP_ERR4         Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CBT_WLEV_ATK_RESULT5                         (DRAMC_NAO_BASE_ADDRESS + 0x00E4)
+    #define CBT_WLEV_ATK_RESULT5_CBT_WLEV_ATK_CMP_ERR5         Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CBT_WLEV_ATK_RESULT6                         (DRAMC_NAO_BASE_ADDRESS + 0x00E8)
+    #define CBT_WLEV_ATK_RESULT6_CBT_WLEV_ATK_CMP_ERR6         Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CBT_WLEV_ATK_RESULT7                         (DRAMC_NAO_BASE_ADDRESS + 0x00EC)
+    #define CBT_WLEV_ATK_RESULT7_CBT_WLEV_ATK_CMP_ERR7         Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CBT_WLEV_ATK_RESULT8                         (DRAMC_NAO_BASE_ADDRESS + 0x00F0)
+    #define CBT_WLEV_ATK_RESULT8_CBT_WLEV_ATK_CMP_ERR8         Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CBT_WLEV_ATK_RESULT9                         (DRAMC_NAO_BASE_ADDRESS + 0x00F4)
+    #define CBT_WLEV_ATK_RESULT9_CBT_WLEV_ATK_CMP_ERR9         Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CBT_WLEV_ATK_RESULT10                        (DRAMC_NAO_BASE_ADDRESS + 0x00F8)
+    #define CBT_WLEV_ATK_RESULT10_CBT_WLEV_ATK_CMP_ERR10       Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CBT_WLEV_ATK_RESULT11                        (DRAMC_NAO_BASE_ADDRESS + 0x00FC)
+    #define CBT_WLEV_ATK_RESULT11_CBT_WLEV_ATK_CMP_ERR11       Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CBT_WLEV_ATK_RESULT12                        (DRAMC_NAO_BASE_ADDRESS + 0x0100)
+    #define CBT_WLEV_ATK_RESULT12_CBT_WLEV_ATK_CMP_ERR12       Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CBT_WLEV_ATK_RESULT13                        (DRAMC_NAO_BASE_ADDRESS + 0x0104)
+    #define CBT_WLEV_ATK_RESULT13_CBT_WLEV_ATK_CMP_ERR13       Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_HWMRR_PUSH2POP_CNT                           (DRAMC_NAO_BASE_ADDRESS + 0x010C)
+    #define HWMRR_PUSH2POP_CNT_HWMRR_PUSH2POP_CNT              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_HWMRR_STATUS                                 (DRAMC_NAO_BASE_ADDRESS + 0x0110)
+    #define HWMRR_STATUS_OV_P2P_CNT                            Fld(8, 0) //[7:0]
+    #define HWMRR_STATUS_MRR_CNT_UNDER_FULL                    Fld(1, 30) //[30:30]
+    #define HWMRR_STATUS_MRR_CNT_OVER_FULL                     Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_HW_REFRATE_MON                               (DRAMC_NAO_BASE_ADDRESS + 0x0114)
+    #define HW_REFRATE_MON_REFRESH_RATE_MIN_MON                Fld(5, 0) //[4:0]
+    #define HW_REFRATE_MON_REFRESH_RATE_MAX_MON                Fld(5, 8) //[12:8]
+
+#define DRAMC_REG_HW_REFRATE_MON2                              (DRAMC_NAO_BASE_ADDRESS + 0x0118)
+    #define HW_REFRATE_MON2_REFRESH_RATE_MIN_MON_RK1_B1        Fld(5, 0) //[4:0]
+    #define HW_REFRATE_MON2_REFRESH_RATE_MAX_MON_RK1_B1        Fld(5, 8) //[12:8]
+    #define HW_REFRATE_MON2_REFRESH_RATE_MIN_MON_RK0_B1        Fld(5, 16) //[20:16]
+    #define HW_REFRATE_MON2_REFRESH_RATE_MAX_MON_RK0_B1        Fld(5, 24) //[28:24]
+
+#define DRAMC_REG_HW_REFRATE_MON3                              (DRAMC_NAO_BASE_ADDRESS + 0x011C)
+    #define HW_REFRATE_MON3_REFRESH_RATE_MIN_MON_RK1_B0        Fld(5, 0) //[4:0]
+    #define HW_REFRATE_MON3_REFRESH_RATE_MAX_MON_RK1_B0        Fld(5, 8) //[12:8]
+    #define HW_REFRATE_MON3_REFRESH_RATE_MIN_MON_RK0_B0        Fld(5, 16) //[20:16]
+    #define HW_REFRATE_MON3_REFRESH_RATE_MAX_MON_RK0_B0        Fld(5, 24) //[28:24]
+
+#define DRAMC_REG_TESTRPT                                      (DRAMC_NAO_BASE_ADDRESS + 0x0120)
+    #define TESTRPT_DM_CMP_CPT_RK0                             Fld(1, 0) //[0:0]
+    #define TESTRPT_DM_CMP_CPT_RK1                             Fld(1, 1) //[1:1]
+    #define TESTRPT_DM_CMP_ERR_RK0                             Fld(1, 4) //[4:4]
+    #define TESTRPT_DM_CMP_ERR_RK1                             Fld(1, 5) //[5:5]
+    #define TESTRPT_DLE_CNT_OK_RK0                             Fld(1, 8) //[8:8]
+    #define TESTRPT_DLE_CNT_OK_RK1                             Fld(1, 9) //[9:9]
+    #define TESTRPT_LPBK_CMP_ERR                               Fld(1, 12) //[12:12]
+    #define TESTRPT_TESTSTAT                                   Fld(3, 20) //[22:20]
+
+#define DRAMC_REG_CMP_ERR                                      (DRAMC_NAO_BASE_ADDRESS + 0x0124)
+    #define CMP_ERR_CMP_ERR                                    Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_TEST_ABIT_STATUS1                            (DRAMC_NAO_BASE_ADDRESS + 0x0128)
+    #define TEST_ABIT_STATUS1_TEST_ABIT_ERR1                   Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_TEST_ABIT_STATUS2                            (DRAMC_NAO_BASE_ADDRESS + 0x012C)
+    #define TEST_ABIT_STATUS2_TEST_ABIT_ERR2                   Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_TEST_ABIT_STATUS3                            (DRAMC_NAO_BASE_ADDRESS + 0x0130)
+    #define TEST_ABIT_STATUS3_TEST_ABIT_ERR3                   Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_TEST_ABIT_STATUS4                            (DRAMC_NAO_BASE_ADDRESS + 0x0134)
+    #define TEST_ABIT_STATUS4_TEST_ABIT_ERR4                   Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_TEST_ABIT_STATUS5                            (DRAMC_NAO_BASE_ADDRESS + 0x0138)
+    #define TEST_ABIT_STATUS5_TEST_ABIT_ERR5                   Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_TEST_ABIT_STATUS6                            (DRAMC_NAO_BASE_ADDRESS + 0x013C)
+    #define TEST_ABIT_STATUS6_TEST_ABIT_ERR6                   Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_TEST_ABIT_STATUS7                            (DRAMC_NAO_BASE_ADDRESS + 0x0140)
+    #define TEST_ABIT_STATUS7_TEST_ABIT_ERR7                   Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_TEST_ABIT_STATUS8                            (DRAMC_NAO_BASE_ADDRESS + 0x0144)
+    #define TEST_ABIT_STATUS8_TEST_ABIT_ERR8                   Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_TEST_RF_ERROR_FLAG0                          (DRAMC_NAO_BASE_ADDRESS + 0x0148)
+    #define TEST_RF_ERROR_FLAG0_TEST_RF_ERROR_FLAG0            Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_TEST_RF_ERROR_FLAG1                          (DRAMC_NAO_BASE_ADDRESS + 0x014C)
+    #define TEST_RF_ERROR_FLAG1_TEST_RF_ERROR_FLAG1            Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_TEST_RF_ERROR_CNT1                           (DRAMC_NAO_BASE_ADDRESS + 0x0150)
+    #define TEST_RF_ERROR_CNT1_DQ0F_ERR_CNT                    Fld(11, 16) //[26:16]
+    #define TEST_RF_ERROR_CNT1_DQ0R_ERR_CNT                    Fld(11, 0) //[10:0]
+
+#define DRAMC_REG_TEST_RF_ERROR_CNT2                           (DRAMC_NAO_BASE_ADDRESS + 0x0154)
+    #define TEST_RF_ERROR_CNT2_DQ1F_ERR_CNT                    Fld(11, 16) //[26:16]
+    #define TEST_RF_ERROR_CNT2_DQ1R_ERR_CNT                    Fld(11, 0) //[10:0]
+
+#define DRAMC_REG_TEST_RF_ERROR_CNT3                           (DRAMC_NAO_BASE_ADDRESS + 0x0158)
+    #define TEST_RF_ERROR_CNT3_DQ2F_ERR_CNT                    Fld(11, 16) //[26:16]
+    #define TEST_RF_ERROR_CNT3_DQ2R_ERR_CNT                    Fld(11, 0) //[10:0]
+
+#define DRAMC_REG_TEST_RF_ERROR_CNT4                           (DRAMC_NAO_BASE_ADDRESS + 0x015C)
+    #define TEST_RF_ERROR_CNT4_DQ3F_ERR_CNT                    Fld(11, 16) //[26:16]
+    #define TEST_RF_ERROR_CNT4_DQ3R_ERR_CNT                    Fld(11, 0) //[10:0]
+
+#define DRAMC_REG_TEST_RF_ERROR_CNT5                           (DRAMC_NAO_BASE_ADDRESS + 0x0160)
+    #define TEST_RF_ERROR_CNT5_DQ4F_ERR_CNT                    Fld(11, 16) //[26:16]
+    #define TEST_RF_ERROR_CNT5_DQ4R_ERR_CNT                    Fld(11, 0) //[10:0]
+
+#define DRAMC_REG_TEST_RF_ERROR_CNT6                           (DRAMC_NAO_BASE_ADDRESS + 0x0164)
+    #define TEST_RF_ERROR_CNT6_DQ5F_ERR_CNT                    Fld(11, 16) //[26:16]
+    #define TEST_RF_ERROR_CNT6_DQ5R_ERR_CNT                    Fld(11, 0) //[10:0]
+
+#define DRAMC_REG_TEST_RF_ERROR_CNT7                           (DRAMC_NAO_BASE_ADDRESS + 0x0168)
+    #define TEST_RF_ERROR_CNT7_DQ6F_ERR_CNT                    Fld(11, 16) //[26:16]
+    #define TEST_RF_ERROR_CNT7_DQ6R_ERR_CNT                    Fld(11, 0) //[10:0]
+
+#define DRAMC_REG_TEST_RF_ERROR_CNT8                           (DRAMC_NAO_BASE_ADDRESS + 0x016C)
+    #define TEST_RF_ERROR_CNT8_DQ7F_ERR_CNT                    Fld(11, 16) //[26:16]
+    #define TEST_RF_ERROR_CNT8_DQ7R_ERR_CNT                    Fld(11, 0) //[10:0]
+
+#define DRAMC_REG_TEST_LOOP_CNT                                (DRAMC_NAO_BASE_ADDRESS + 0x0170)
+    #define TEST_LOOP_CNT_LOOP_CNT                             Fld(16, 0) //[15:0]
+
+#define DRAMC_REG_SREF_DLY_CNT                                 (DRAMC_NAO_BASE_ADDRESS + 0x0180)
+    #define SREF_DLY_CNT_SREF_DLY_CNT                          Fld(16, 0) //[15:0]
+    #define SREF_DLY_CNT_SREF_DLY_CNT_ECO                      Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_TX_ATK_SET0                                  (DRAMC_NAO_BASE_ADDRESS + 0x0200)
+    #define TX_ATK_SET0_TX_ATK_DQ_B0_PI_INIT                   Fld(6, 0) //[5:0]
+    #define TX_ATK_SET0_TX_ATK_DQ_B1_PI_INIT                   Fld(6, 8) //[13:8]
+    #define TX_ATK_SET0_TX_ATK_DQM_B0_PI_INIT                  Fld(6, 16) //[21:16]
+    #define TX_ATK_SET0_TX_ATK_DQM_B1_PI_INIT                  Fld(6, 24) //[29:24]
+
+#define DRAMC_REG_TX_ATK_SET1                                  (DRAMC_NAO_BASE_ADDRESS + 0x0204)
+    #define TX_ATK_SET1_TX_ATK_DQ_PI_EN                        Fld(1, 0) //[0:0]
+    #define TX_ATK_SET1_TX_ATK_DQM_PI_EN                       Fld(1, 1) //[1:1]
+    #define TX_ATK_SET1_TX_ATK_PI_LEN                          Fld(2, 2) //[3:2]
+    #define TX_ATK_SET1_TX_ATK_EARLY_BREAK                     Fld(1, 4) //[4:4]
+    #define TX_ATK_SET1_TX_ATK_PASS_PI_THRD                    Fld(6, 8) //[13:8]
+    #define TX_ATK_SET1_TX_ATK_DBG_EN                          Fld(1, 15) //[15:15]
+    #define TX_ATK_SET1_TX_ATK_DBG_BIT_SEL                     Fld(4, 16) //[19:16]
+    #define TX_ATK_SET1_TX_ATK_CLR                             Fld(1, 30) //[30:30]
+    #define TX_ATK_SET1_TX_ATK_TRIG                            Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_TX_ATK_RESULT0                               (DRAMC_NAO_BASE_ADDRESS + 0x0210)
+    #define TX_ATK_RESULT0_TX_ATK_MAX_PW_PI_INIT_BIT0          Fld(8, 0) //[7:0]
+    #define TX_ATK_RESULT0_TX_ATK_MAX_PW_PI_INIT_BIT1          Fld(8, 8) //[15:8]
+    #define TX_ATK_RESULT0_TX_ATK_MAX_PW_PI_INIT_BIT2          Fld(8, 16) //[23:16]
+    #define TX_ATK_RESULT0_TX_ATK_MAX_PW_PI_INIT_BIT3          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_TX_ATK_RESULT1                               (DRAMC_NAO_BASE_ADDRESS + 0x0214)
+    #define TX_ATK_RESULT1_TX_ATK_MAX_PW_PI_INIT_BIT4          Fld(8, 0) //[7:0]
+    #define TX_ATK_RESULT1_TX_ATK_MAX_PW_PI_INIT_BIT5          Fld(8, 8) //[15:8]
+    #define TX_ATK_RESULT1_TX_ATK_MAX_PW_PI_INIT_BIT6          Fld(8, 16) //[23:16]
+    #define TX_ATK_RESULT1_TX_ATK_MAX_PW_PI_INIT_BIT7          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_TX_ATK_RESULT2                               (DRAMC_NAO_BASE_ADDRESS + 0x0218)
+    #define TX_ATK_RESULT2_TX_ATK_MAX_PW_PI_INIT_BIT8          Fld(8, 0) //[7:0]
+    #define TX_ATK_RESULT2_TX_ATK_MAX_PW_PI_INIT_BIT9          Fld(8, 8) //[15:8]
+    #define TX_ATK_RESULT2_TX_ATK_MAX_PW_PI_INIT_BIT10         Fld(8, 16) //[23:16]
+    #define TX_ATK_RESULT2_TX_ATK_MAX_PW_PI_INIT_BIT11         Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_TX_ATK_RESULT3                               (DRAMC_NAO_BASE_ADDRESS + 0x021C)
+    #define TX_ATK_RESULT3_TX_ATK_MAX_PW_PI_INIT_BIT12         Fld(8, 0) //[7:0]
+    #define TX_ATK_RESULT3_TX_ATK_MAX_PW_PI_INIT_BIT13         Fld(8, 8) //[15:8]
+    #define TX_ATK_RESULT3_TX_ATK_MAX_PW_PI_INIT_BIT14         Fld(8, 16) //[23:16]
+    #define TX_ATK_RESULT3_TX_ATK_MAX_PW_PI_INIT_BIT15         Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_TX_ATK_RESULT4                               (DRAMC_NAO_BASE_ADDRESS + 0x0220)
+    #define TX_ATK_RESULT4_TX_ATK_MAX_PW_PI_LEN_BIT0           Fld(8, 0) //[7:0]
+    #define TX_ATK_RESULT4_TX_ATK_MAX_PW_PI_LEN_BIT1           Fld(8, 8) //[15:8]
+    #define TX_ATK_RESULT4_TX_ATK_MAX_PW_PI_LEN_BIT2           Fld(8, 16) //[23:16]
+    #define TX_ATK_RESULT4_TX_ATK_MAX_PW_PI_LEN_BIT3           Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_TX_ATK_RESULT5                               (DRAMC_NAO_BASE_ADDRESS + 0x0224)
+    #define TX_ATK_RESULT5_TX_ATK_MAX_PW_PI_LEN_BIT4           Fld(8, 0) //[7:0]
+    #define TX_ATK_RESULT5_TX_ATK_MAX_PW_PI_LEN_BIT5           Fld(8, 8) //[15:8]
+    #define TX_ATK_RESULT5_TX_ATK_MAX_PW_PI_LEN_BIT6           Fld(8, 16) //[23:16]
+    #define TX_ATK_RESULT5_TX_ATK_MAX_PW_PI_LEN_BIT7           Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_TX_ATK_RESULT6                               (DRAMC_NAO_BASE_ADDRESS + 0x0228)
+    #define TX_ATK_RESULT6_TX_ATK_MAX_PW_PI_LEN_BIT8           Fld(8, 0) //[7:0]
+    #define TX_ATK_RESULT6_TX_ATK_MAX_PW_PI_LEN_BIT9           Fld(8, 8) //[15:8]
+    #define TX_ATK_RESULT6_TX_ATK_MAX_PW_PI_LEN_BIT10          Fld(8, 16) //[23:16]
+    #define TX_ATK_RESULT6_TX_ATK_MAX_PW_PI_LEN_BIT11          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_TX_ATK_RESULT7                               (DRAMC_NAO_BASE_ADDRESS + 0x022C)
+    #define TX_ATK_RESULT7_TX_ATK_MAX_PW_PI_LEN_BIT12          Fld(8, 0) //[7:0]
+    #define TX_ATK_RESULT7_TX_ATK_MAX_PW_PI_LEN_BIT13          Fld(8, 8) //[15:8]
+    #define TX_ATK_RESULT7_TX_ATK_MAX_PW_PI_LEN_BIT14          Fld(8, 16) //[23:16]
+    #define TX_ATK_RESULT7_TX_ATK_MAX_PW_PI_LEN_BIT15          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_TX_ATK_RESULT8                               (DRAMC_NAO_BASE_ADDRESS + 0x0230)
+    #define TX_ATK_RESULT8_TX_ATK_FIND_PW                      Fld(1, 24) //[24:24]
+    #define TX_ATK_RESULT8_TX_ATK_DONE                         Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_TX_ATK_DBG_BIT_STATUS1                       (DRAMC_NAO_BASE_ADDRESS + 0x0240)
+    #define TX_ATK_DBG_BIT_STATUS1_TX_ATK_DBG_BIT_STATUS1      Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_TX_ATK_DBG_BIT_STATUS2                       (DRAMC_NAO_BASE_ADDRESS + 0x0244)
+    #define TX_ATK_DBG_BIT_STATUS2_TX_ATK_DBG_BIT_STATUS2      Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_TX_ATK_DBG_BIT_STATUS3                       (DRAMC_NAO_BASE_ADDRESS + 0x0248)
+    #define TX_ATK_DBG_BIT_STATUS3_TX_ATK_DBG_BIT_STATUS3      Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_TX_ATK_DBG_BIT_STATUS4                       (DRAMC_NAO_BASE_ADDRESS + 0x024C)
+    #define TX_ATK_DBG_BIT_STATUS4_TX_ATK_DBG_BIT_STATUS4      Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_LP5_PDX_PDE_MON                              (DRAMC_NAO_BASE_ADDRESS + 0x02D8)
+    #define LP5_PDX_PDE_MON_PDX_CMD_REQ_RK0_COUNTER            Fld(8, 0) //[7:0]
+    #define LP5_PDX_PDE_MON_PDX_CMD_REQ_RK1_COUNTER            Fld(8, 8) //[15:8]
+    #define LP5_PDX_PDE_MON_PDE_CMD_REQ_RK0_COUNTER            Fld(8, 16) //[23:16]
+    #define LP5_PDX_PDE_MON_PDE_CMD_REQ_RK1_COUNTER            Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_LP5_PDX_PDE_MAX_MON                          (DRAMC_NAO_BASE_ADDRESS + 0x02DC)
+    #define LP5_PDX_PDE_MAX_MON_WAIT_PDX_CMD_RK0_MAX_COUNTER   Fld(8, 0) //[7:0]
+    #define LP5_PDX_PDE_MAX_MON_WAIT_PDX_CMD_RK1_MAX_COUNTER   Fld(8, 8) //[15:8]
+    #define LP5_PDX_PDE_MAX_MON_WAIT_PDE_CMD_RK0_MAX_COUNTER   Fld(8, 16) //[23:16]
+    #define LP5_PDX_PDE_MAX_MON_WAIT_PDE_CMD_RK1_MAX_COUNTER   Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_DRAM_CLK_EN_0_OLD_COUNTER                    (DRAMC_NAO_BASE_ADDRESS + 0x02E0)
+    #define DRAM_CLK_EN_0_OLD_COUNTER_DRAM_CLK_EN_0_OLD_COUNTER Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_APHYPI_CG_CK_OLD_COUNTER                     (DRAMC_NAO_BASE_ADDRESS + 0x02E4)
+    #define APHYPI_CG_CK_OLD_COUNTER_APHYPI_CG_CK_OLD_COUNTER  Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CKEO_PRE_OLD_COUNTER                         (DRAMC_NAO_BASE_ADDRESS + 0x02E8)
+    #define CKEO_PRE_OLD_COUNTER_CKEO_PRE_OLD_COUNTER          Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CKE1O_PRE_OLD_COUNTER                        (DRAMC_NAO_BASE_ADDRESS + 0x02EC)
+    #define CKE1O_PRE_OLD_COUNTER_CKE1O_PRE_OLD_COUNTER        Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DRAM_CLK_EN_0_NEW_COUNTER                    (DRAMC_NAO_BASE_ADDRESS + 0x02F0)
+    #define DRAM_CLK_EN_0_NEW_COUNTER_DRAM_CLK_EN_0_NEW_COUNTER Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_APHYPI_CG_CK_NEW_COUNTER                     (DRAMC_NAO_BASE_ADDRESS + 0x02F4)
+    #define APHYPI_CG_CK_NEW_COUNTER_APHYPI_CG_CK_NEW_COUNTER  Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CKEO_PRE_NEW_COUNTER                         (DRAMC_NAO_BASE_ADDRESS + 0x02F8)
+    #define CKEO_PRE_NEW_COUNTER_CKEO_PRE_NEW_COUNTER          Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_CKE1O_PRE_NEW_COUNTER                        (DRAMC_NAO_BASE_ADDRESS + 0x02FC)
+    #define CKE1O_PRE_NEW_COUNTER_CKE1O_PRE_NEW_COUNTER        Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_REFRESH_POP_COUNTER                          (DRAMC_NAO_BASE_ADDRESS + 0x0300)
+    #define REFRESH_POP_COUNTER_REFRESH_POP_COUNTER            Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_FREERUN_26M_COUNTER                          (DRAMC_NAO_BASE_ADDRESS + 0x0304)
+    #define FREERUN_26M_COUNTER_FREERUN_26M_COUNTER            Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DRAMC_IDLE_COUNTER                           (DRAMC_NAO_BASE_ADDRESS + 0x0308)
+    #define DRAMC_IDLE_COUNTER_DRAMC_IDLE_COUNTER              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_R2R_PAGE_HIT_COUNTER                         (DRAMC_NAO_BASE_ADDRESS + 0x030C)
+    #define R2R_PAGE_HIT_COUNTER_R2R_PAGE_HIT_COUNTER          Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_R2R_PAGE_MISS_COUNTER                        (DRAMC_NAO_BASE_ADDRESS + 0x0310)
+    #define R2R_PAGE_MISS_COUNTER_R2R_PAGE_MISS_COUNTER        Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_R2R_INTERBANK_COUNTER                        (DRAMC_NAO_BASE_ADDRESS + 0x0314)
+    #define R2R_INTERBANK_COUNTER_R2R_INTERBANK_COUNTER        Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_R2W_PAGE_HIT_COUNTER                         (DRAMC_NAO_BASE_ADDRESS + 0x0318)
+    #define R2W_PAGE_HIT_COUNTER_R2W_PAGE_HIT_COUNTER          Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_R2W_PAGE_MISS_COUNTER                        (DRAMC_NAO_BASE_ADDRESS + 0x031C)
+    #define R2W_PAGE_MISS_COUNTER_R2W_PAGE_MISS_COUNTER        Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_R2W_INTERBANK_COUNTER                        (DRAMC_NAO_BASE_ADDRESS + 0x0320)
+    #define R2W_INTERBANK_COUNTER_R2W_INTERBANK_COUNTER        Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_W2R_PAGE_HIT_COUNTER                         (DRAMC_NAO_BASE_ADDRESS + 0x0324)
+    #define W2R_PAGE_HIT_COUNTER_W2R_PAGE_HIT_COUNTER          Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_W2R_PAGE_MISS_COUNTER                        (DRAMC_NAO_BASE_ADDRESS + 0x0328)
+    #define W2R_PAGE_MISS_COUNTER_W2R_PAGE_MISS_COUNTER        Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_W2R_INTERBANK_COUNTER                        (DRAMC_NAO_BASE_ADDRESS + 0x032C)
+    #define W2R_INTERBANK_COUNTER_W2R_INTERBANK_COUNTER        Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_W2W_PAGE_HIT_COUNTER                         (DRAMC_NAO_BASE_ADDRESS + 0x0330)
+    #define W2W_PAGE_HIT_COUNTER_W2W_PAGE_HIT_COUNTER          Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_W2W_PAGE_MISS_COUNTER                        (DRAMC_NAO_BASE_ADDRESS + 0x0334)
+    #define W2W_PAGE_MISS_COUNTER_W2W_PAGE_MISS_COUNTER        Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_W2W_INTERBANK_COUNTER                        (DRAMC_NAO_BASE_ADDRESS + 0x0338)
+    #define W2W_INTERBANK_COUNTER_W2W_INTERBANK_COUNTER        Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK0_PRE_STANDBY_COUNTER                      (DRAMC_NAO_BASE_ADDRESS + 0x033C)
+    #define RK0_PRE_STANDBY_COUNTER_RK0_PRE_STANDBY_COUNTER    Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK0_PRE_POWERDOWN_COUNTER                    (DRAMC_NAO_BASE_ADDRESS + 0x0340)
+    #define RK0_PRE_POWERDOWN_COUNTER_RK0_PRE_POWERDOWN_COUNTER Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK0_ACT_STANDBY_COUNTER                      (DRAMC_NAO_BASE_ADDRESS + 0x0344)
+    #define RK0_ACT_STANDBY_COUNTER_RK0_ACT_STANDBY_COUNTER    Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK0_ACT_POWERDOWN_COUNTER                    (DRAMC_NAO_BASE_ADDRESS + 0x0348)
+    #define RK0_ACT_POWERDOWN_COUNTER_RK0_ACT_POWERDOWN_COUNTER Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK1_PRE_STANDBY_COUNTER                      (DRAMC_NAO_BASE_ADDRESS + 0x034C)
+    #define RK1_PRE_STANDBY_COUNTER_RK1_PRE_STANDBY_COUNTER    Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK1_PRE_POWERDOWN_COUNTER                    (DRAMC_NAO_BASE_ADDRESS + 0x0350)
+    #define RK1_PRE_POWERDOWN_COUNTER_RK1_PRE_POWERDOWN_COUNTER Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK1_ACT_STANDBY_COUNTER                      (DRAMC_NAO_BASE_ADDRESS + 0x0354)
+    #define RK1_ACT_STANDBY_COUNTER_RK1_ACT_STANDBY_COUNTER    Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK1_ACT_POWERDOWN_COUNTER                    (DRAMC_NAO_BASE_ADDRESS + 0x0358)
+    #define RK1_ACT_POWERDOWN_COUNTER_RK1_ACT_POWERDOWN_COUNTER Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK2_PRE_STANDBY_COUNTER                      (DRAMC_NAO_BASE_ADDRESS + 0x035C)
+    #define RK2_PRE_STANDBY_COUNTER_RK2_PRE_STANDBY_COUNTER    Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK2_PRE_POWERDOWN_COUNTER                    (DRAMC_NAO_BASE_ADDRESS + 0x0360)
+    #define RK2_PRE_POWERDOWN_COUNTER_RK2_PRE_POWERDOWN_COUNTER Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK2_ACT_STANDBY_COUNTER                      (DRAMC_NAO_BASE_ADDRESS + 0x0364)
+    #define RK2_ACT_STANDBY_COUNTER_RK2_ACT_STANDBY_COUNTER    Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK2_ACT_POWERDOWN_COUNTER                    (DRAMC_NAO_BASE_ADDRESS + 0x0368)
+    #define RK2_ACT_POWERDOWN_COUNTER_RK2_ACT_POWERDOWN_COUNTER Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DQ0_TOGGLE_COUNTER                           (DRAMC_NAO_BASE_ADDRESS + 0x036C)
+    #define DQ0_TOGGLE_COUNTER_DQ0_TOGGLE_COUNTER              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DQ1_TOGGLE_COUNTER                           (DRAMC_NAO_BASE_ADDRESS + 0x0370)
+    #define DQ1_TOGGLE_COUNTER_DQ1_TOGGLE_COUNTER              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DQ2_TOGGLE_COUNTER                           (DRAMC_NAO_BASE_ADDRESS + 0x0374)
+    #define DQ2_TOGGLE_COUNTER_DQ2_TOGGLE_COUNTER              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DQ3_TOGGLE_COUNTER                           (DRAMC_NAO_BASE_ADDRESS + 0x0378)
+    #define DQ3_TOGGLE_COUNTER_DQ3_TOGGLE_COUNTER              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DQ0_TOGGLE_COUNTER_R                         (DRAMC_NAO_BASE_ADDRESS + 0x037C)
+    #define DQ0_TOGGLE_COUNTER_R_DQ0_TOGGLE_COUNTER_R          Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DQ1_TOGGLE_COUNTER_R                         (DRAMC_NAO_BASE_ADDRESS + 0x0380)
+    #define DQ1_TOGGLE_COUNTER_R_DQ1_TOGGLE_COUNTER_R          Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DQ2_TOGGLE_COUNTER_R                         (DRAMC_NAO_BASE_ADDRESS + 0x0384)
+    #define DQ2_TOGGLE_COUNTER_R_DQ2_TOGGLE_COUNTER_R          Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DQ3_TOGGLE_COUNTER_R                         (DRAMC_NAO_BASE_ADDRESS + 0x0388)
+    #define DQ3_TOGGLE_COUNTER_R_DQ3_TOGGLE_COUNTER_R          Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_READ_BYTES_COUNTER                           (DRAMC_NAO_BASE_ADDRESS + 0x038C)
+    #define READ_BYTES_COUNTER_READ_BYTES_COUNTER              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_WRITE_BYTES_COUNTER                          (DRAMC_NAO_BASE_ADDRESS + 0x0390)
+    #define WRITE_BYTES_COUNTER_WRITE_BYTES_COUNTER            Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_MAX_SREF_REQ_TO_ACK_LATENCY_COUNTER          (DRAMC_NAO_BASE_ADDRESS + 0x0394)
+    #define MAX_SREF_REQ_TO_ACK_LATENCY_COUNTER_SREF_REQTOACK_MAX_COUNTER Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DRAMC_IDLE_DCM_COUNTER                       (DRAMC_NAO_BASE_ADDRESS + 0x03A0)
+    #define DRAMC_IDLE_DCM_COUNTER_DRAMC_IDLE_DCM_COUNTER      Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DDRPHY_CLK_EN_COUNTER                        (DRAMC_NAO_BASE_ADDRESS + 0x03A4)
+    #define DDRPHY_CLK_EN_COUNTER_DDRPHY_CLK_EN_COUNTER        Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DDRPHY_CLK_EN_COMB_COUNTER                   (DRAMC_NAO_BASE_ADDRESS + 0x03A8)
+    #define DDRPHY_CLK_EN_COMB_COUNTER_DDRPHY_CLK_EN_COMB_COUNTER Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_EBG_COUNTER_CNT0                             (DRAMC_NAO_BASE_ADDRESS + 0x03B0)
+    #define EBG_COUNTER_CNT0_EBG_PGHIT_COUNTER                 Fld(16, 0) //[15:0]
+
+#define DRAMC_REG_EBG_COUNTER_CNT1                             (DRAMC_NAO_BASE_ADDRESS + 0x03B4)
+    #define EBG_COUNTER_CNT1_EBG_PGMISS_COUNTER                Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_EBG_COUNTER_CNT2                             (DRAMC_NAO_BASE_ADDRESS + 0x03B8)
+    #define EBG_COUNTER_CNT2_EBG_PGOPEN_COUNTER                Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_LAT_COUNTER_CMD0                             (DRAMC_NAO_BASE_ADDRESS + 0x03C0)
+    #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX                  Fld(16, 0) //[15:0]
+    #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX_HPRI             Fld(1, 16) //[16:16]
+    #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX_LLAT             Fld(1, 17) //[17:17]
+    #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX_REORDER          Fld(1, 18) //[18:18]
+
+#define DRAMC_REG_LAT_COUNTER_CMD1                             (DRAMC_NAO_BASE_ADDRESS + 0x03C4)
+    #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX                  Fld(16, 0) //[15:0]
+    #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX_HPRI             Fld(1, 16) //[16:16]
+    #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX_LLAT             Fld(1, 17) //[17:17]
+    #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX_REORDER          Fld(1, 18) //[18:18]
+
+#define DRAMC_REG_LAT_COUNTER_CMD2                             (DRAMC_NAO_BASE_ADDRESS + 0x03C8)
+    #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX                  Fld(16, 0) //[15:0]
+    #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX_HPRI             Fld(1, 16) //[16:16]
+    #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX_LLAT             Fld(1, 17) //[17:17]
+    #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX_REORDER          Fld(1, 18) //[18:18]
+
+#define DRAMC_REG_LAT_COUNTER_CMD3                             (DRAMC_NAO_BASE_ADDRESS + 0x03CC)
+    #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX                  Fld(16, 0) //[15:0]
+    #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX_HPRI             Fld(1, 16) //[16:16]
+    #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX_LLAT             Fld(1, 17) //[17:17]
+    #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX_REORDER          Fld(1, 18) //[18:18]
+
+#define DRAMC_REG_LAT_COUNTER_CMD4                             (DRAMC_NAO_BASE_ADDRESS + 0x03D0)
+    #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX                  Fld(16, 0) //[15:0]
+    #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX_HPRI             Fld(1, 16) //[16:16]
+    #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX_LLAT             Fld(1, 17) //[17:17]
+    #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX_REORDER          Fld(1, 18) //[18:18]
+
+#define DRAMC_REG_LAT_COUNTER_CMD5                             (DRAMC_NAO_BASE_ADDRESS + 0x03D4)
+    #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX                  Fld(16, 0) //[15:0]
+    #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX_HPRI             Fld(1, 16) //[16:16]
+    #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX_LLAT             Fld(1, 17) //[17:17]
+    #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX_REORDER          Fld(1, 18) //[18:18]
+
+#define DRAMC_REG_LAT_COUNTER_CMD6                             (DRAMC_NAO_BASE_ADDRESS + 0x03D8)
+    #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX                  Fld(16, 0) //[15:0]
+    #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX_HPRI             Fld(1, 16) //[16:16]
+    #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX_LLAT             Fld(1, 17) //[17:17]
+    #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX_REORDER          Fld(1, 18) //[18:18]
+
+#define DRAMC_REG_LAT_COUNTER_CMD7                             (DRAMC_NAO_BASE_ADDRESS + 0x03DC)
+    #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX                  Fld(16, 0) //[15:0]
+    #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX_HPRI             Fld(1, 16) //[16:16]
+    #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX_LLAT             Fld(1, 17) //[17:17]
+    #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX_REORDER          Fld(1, 18) //[18:18]
+
+#define DRAMC_REG_LAT_COUNTER_AVER                             (DRAMC_NAO_BASE_ADDRESS + 0x03E0)
+    #define LAT_COUNTER_AVER_LAT_CMD_AVER_CNT                  Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_LAT_COUNTER_NUM                              (DRAMC_NAO_BASE_ADDRESS + 0x03E4)
+    #define LAT_COUNTER_NUM_LAT_CMD_NUM                        Fld(16, 0) //[15:0]
+
+#define DRAMC_REG_LAT_COUNTER_BLOCK_ALE                        (DRAMC_NAO_BASE_ADDRESS + 0x03E8)
+    #define LAT_COUNTER_BLOCK_ALE_CTO_BLOCK_CNT_MAX            Fld(16, 0) //[15:0]
+
+#define DRAMC_REG_DRAMC_LOOP_BAK_ADR                           (DRAMC_NAO_BASE_ADDRESS + 0x0504)
+    #define DRAMC_LOOP_BAK_ADR_TEST_WR_BK_ADR                  Fld(3, 0) //[2:0]
+    #define DRAMC_LOOP_BAK_ADR_TEST_WR_COL_ADR                 Fld(11, 3) //[13:3]
+    #define DRAMC_LOOP_BAK_ADR_TEST_WR_ROW_ADR                 Fld(18, 14) //[31:14]
+
+#define DRAMC_REG_DRAMC_LOOP_BAK_RK                            (DRAMC_NAO_BASE_ADDRESS + 0x0508)
+    #define DRAMC_LOOP_BAK_RK_TEST_WR_RK                       Fld(2, 0) //[1:0]
+    #define DRAMC_LOOP_BAK_RK_LOOP_BAK_ADR_CMP_FAIL            Fld(1, 4) //[4:4]
+
+#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT0                         (DRAMC_NAO_BASE_ADDRESS + 0x0510)
+    #define DRAMC_LOOP_BAK_WDAT0_LOOP_BACK_WDAT0               Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT1                         (DRAMC_NAO_BASE_ADDRESS + 0x0514)
+    #define DRAMC_LOOP_BAK_WDAT1_LOOP_BACK_WDAT1               Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT2                         (DRAMC_NAO_BASE_ADDRESS + 0x0518)
+    #define DRAMC_LOOP_BAK_WDAT2_LOOP_BACK_WDAT2               Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT3                         (DRAMC_NAO_BASE_ADDRESS + 0x051C)
+    #define DRAMC_LOOP_BAK_WDAT3_LOOP_BACK_WDAT3               Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT4                         (DRAMC_NAO_BASE_ADDRESS + 0x0520)
+    #define DRAMC_LOOP_BAK_WDAT4_LOOP_BACK_WDAT4               Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT5                         (DRAMC_NAO_BASE_ADDRESS + 0x0524)
+    #define DRAMC_LOOP_BAK_WDAT5_LOOP_BACK_WDAT5               Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT6                         (DRAMC_NAO_BASE_ADDRESS + 0x0528)
+    #define DRAMC_LOOP_BAK_WDAT6_LOOP_BACK_WDAT6               Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT7                         (DRAMC_NAO_BASE_ADDRESS + 0x052C)
+    #define DRAMC_LOOP_BAK_WDAT7_LOOP_BACK_WDAT7               Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK0_DQSOSC_STATUS                            (DRAMC_NAO_BASE_ADDRESS + 0x0600)
+    #define RK0_DQSOSC_STATUS_MR18_REG                         Fld(16, 0) //[15:0]
+    #define RK0_DQSOSC_STATUS_MR19_REG                         Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_RK0_DQSOSC_DELTA                             (DRAMC_NAO_BASE_ADDRESS + 0x0604)
+    #define RK0_DQSOSC_DELTA_ABS_RK0_DQSOSC_DELTA              Fld(16, 0) //[15:0]
+    #define RK0_DQSOSC_DELTA_SIGN_RK0_DQSOSC_DELTA             Fld(1, 16) //[16:16]
+    #define RK0_DQSOSC_DELTA_DQSOSCR_RESPONSE                  Fld(1, 17) //[17:17]
+    #define RK0_DQSOSC_DELTA_H_DQSOSCLSBR_REQ                  Fld(1, 18) //[18:18]
+    #define RK0_DQSOSC_DELTA_DQSOSC_INT_RK0                    Fld(1, 19) //[19:19]
+
+#define DRAMC_REG_RK0_DQSOSC_DELTA2                            (DRAMC_NAO_BASE_ADDRESS + 0x0608)
+    #define RK0_DQSOSC_DELTA2_ABS_RK0_DQSOSC_B1_DELTA          Fld(16, 0) //[15:0]
+    #define RK0_DQSOSC_DELTA2_SIGN_RK0_DQSOSC_B1_DELTA         Fld(1, 16) //[16:16]
+
+#define DRAMC_REG_RK0_CURRENT_TX_SETTING1                      (DRAMC_NAO_BASE_ADDRESS + 0x0610)
+    #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ0_MOD         Fld(3, 0) //[2:0]
+    #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ1_MOD         Fld(3, 4) //[6:4]
+    #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ2_MOD         Fld(3, 8) //[10:8]
+    #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ3_MOD         Fld(3, 12) //[14:12]
+    #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM0_MOD        Fld(3, 16) //[18:16]
+    #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM1_MOD        Fld(3, 20) //[22:20]
+    #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM2_MOD        Fld(3, 24) //[26:24]
+    #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM3_MOD        Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_RK0_CURRENT_TX_SETTING2                      (DRAMC_NAO_BASE_ADDRESS + 0x0614)
+    #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ0_MOD            Fld(3, 0) //[2:0]
+    #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ1_MOD            Fld(3, 4) //[6:4]
+    #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ2_MOD            Fld(3, 8) //[10:8]
+    #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ3_MOD            Fld(3, 12) //[14:12]
+    #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM0_MOD           Fld(3, 16) //[18:16]
+    #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM1_MOD           Fld(3, 20) //[22:20]
+    #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM2_MOD           Fld(3, 24) //[26:24]
+    #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM3_MOD           Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_RK0_CURRENT_TX_SETTING3                      (DRAMC_NAO_BASE_ADDRESS + 0x0618)
+    #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ0_MOD     Fld(3, 0) //[2:0]
+    #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ1_MOD     Fld(3, 4) //[6:4]
+    #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ2_MOD     Fld(3, 8) //[10:8]
+    #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ3_MOD     Fld(3, 12) //[14:12]
+    #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM0_MOD    Fld(3, 16) //[18:16]
+    #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM1_MOD    Fld(3, 20) //[22:20]
+    #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM2_MOD    Fld(3, 24) //[26:24]
+    #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM3_MOD    Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_RK0_CURRENT_TX_SETTING4                      (DRAMC_NAO_BASE_ADDRESS + 0x061C)
+    #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ0_MOD        Fld(3, 0) //[2:0]
+    #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ1_MOD        Fld(3, 4) //[6:4]
+    #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ2_MOD        Fld(3, 8) //[10:8]
+    #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ3_MOD        Fld(3, 12) //[14:12]
+    #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM0_MOD       Fld(3, 16) //[18:16]
+    #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM1_MOD       Fld(3, 20) //[22:20]
+    #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM2_MOD       Fld(3, 24) //[26:24]
+    #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM3_MOD       Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_RK0_DUMMY_RD_DATA0                           (DRAMC_NAO_BASE_ADDRESS + 0x0620)
+    #define RK0_DUMMY_RD_DATA0_DUMMY_RD_RK0_DATA0              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK0_DUMMY_RD_DATA1                           (DRAMC_NAO_BASE_ADDRESS + 0x0624)
+    #define RK0_DUMMY_RD_DATA1_DUMMY_RD_RK0_DATA1              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK0_DUMMY_RD_DATA2                           (DRAMC_NAO_BASE_ADDRESS + 0x0628)
+    #define RK0_DUMMY_RD_DATA2_DUMMY_RD_RK0_DATA2              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK0_DUMMY_RD_DATA3                           (DRAMC_NAO_BASE_ADDRESS + 0x062C)
+    #define RK0_DUMMY_RD_DATA3_DUMMY_RD_RK0_DATA3              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK0_DUMMY_RD_DATA4                           (DRAMC_NAO_BASE_ADDRESS + 0x0630)
+    #define RK0_DUMMY_RD_DATA4_DUMMY_RD_RK0_DATA4              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK0_DUMMY_RD_DATA5                           (DRAMC_NAO_BASE_ADDRESS + 0x0634)
+    #define RK0_DUMMY_RD_DATA5_DUMMY_RD_RK0_DATA5              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK0_DUMMY_RD_DATA6                           (DRAMC_NAO_BASE_ADDRESS + 0x0638)
+    #define RK0_DUMMY_RD_DATA6_DUMMY_RD_RK0_DATA6              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK0_DUMMY_RD_DATA7                           (DRAMC_NAO_BASE_ADDRESS + 0x063C)
+    #define RK0_DUMMY_RD_DATA7_DUMMY_RD_RK0_DATA7              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK0_PI_DQ_CAL                                (DRAMC_NAO_BASE_ADDRESS + 0x0660)
+    #define RK0_PI_DQ_CAL_RK0_ARPI_DQ_B0_CAL                   Fld(6, 0) //[5:0]
+    #define RK0_PI_DQ_CAL_RK0_ARPI_DQ_B1_CAL                   Fld(6, 8) //[13:8]
+    #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0                        Fld(6, 16) //[21:16]
+    #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_OVERFLOW               Fld(1, 22) //[22:22]
+    #define RK0_PI_DQ_CAL_RK0_B0_PI_CHANGE_DBG                 Fld(1, 23) //[23:23]
+    #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_B1                     Fld(6, 24) //[29:24]
+    #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_B1_OVERFLOW            Fld(1, 30) //[30:30]
+    #define RK0_PI_DQ_CAL_RK0_B1_PI_CHANGE_DBG                 Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_RK0_PI_DQM_CAL                               (DRAMC_NAO_BASE_ADDRESS + 0x0668)
+    #define RK0_PI_DQM_CAL_RK0_ARPI_DQM_B0_CAL                 Fld(6, 0) //[5:0]
+    #define RK0_PI_DQM_CAL_RK0_ARPI_DQM_B1_CAL                 Fld(6, 8) //[13:8]
+
+#define DRAMC_REG_RK1_DQSOSC_STATUS                            (DRAMC_NAO_BASE_ADDRESS + 0x0700)
+    #define RK1_DQSOSC_STATUS_MR18_RK1_REG                     Fld(16, 0) //[15:0]
+    #define RK1_DQSOSC_STATUS_MR19_RK1_REG                     Fld(16, 16) //[31:16]
+
+#define DRAMC_REG_RK1_DQSOSC_DELTA                             (DRAMC_NAO_BASE_ADDRESS + 0x0704)
+    #define RK1_DQSOSC_DELTA_ABS_RK1_DQSOSC_DELTA              Fld(16, 0) //[15:0]
+    #define RK1_DQSOSC_DELTA_SIGN_RK1_DQSOSC_DELTA             Fld(1, 16) //[16:16]
+    #define RK1_DQSOSC_DELTA_DQSOSCR_RK1_RESPONSE              Fld(1, 17) //[17:17]
+    #define RK1_DQSOSC_DELTA_H_DQSOSCLSBR_RK1_REQ              Fld(1, 18) //[18:18]
+    #define RK1_DQSOSC_DELTA_DQSOSC_INT_RK1                    Fld(1, 19) //[19:19]
+
+#define DRAMC_REG_RK1_DQSOSC_DELTA2                            (DRAMC_NAO_BASE_ADDRESS + 0x0708)
+    #define RK1_DQSOSC_DELTA2_ABS_RK1_DQSOSC_B1_DELTA          Fld(16, 0) //[15:0]
+    #define RK1_DQSOSC_DELTA2_SIGN_RK1_DQSOSC_B1_DELTA         Fld(1, 16) //[16:16]
+
+#define DRAMC_REG_RK1_CURRENT_TX_SETTING1                      (DRAMC_NAO_BASE_ADDRESS + 0x0710)
+    #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ0_MOD       Fld(3, 0) //[2:0]
+    #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ1_MOD       Fld(3, 4) //[6:4]
+    #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ2_MOD       Fld(3, 8) //[10:8]
+    #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ3_MOD       Fld(3, 12) //[14:12]
+    #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM0_MOD      Fld(3, 16) //[18:16]
+    #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM1_MOD      Fld(3, 20) //[22:20]
+    #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM2_MOD      Fld(3, 24) //[26:24]
+    #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM3_MOD      Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_RK1_CURRENT_TX_SETTING2                      (DRAMC_NAO_BASE_ADDRESS + 0x0714)
+    #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ0_MOD          Fld(3, 0) //[2:0]
+    #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ1_MOD          Fld(3, 4) //[6:4]
+    #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ2_MOD          Fld(3, 8) //[10:8]
+    #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ3_MOD          Fld(3, 12) //[14:12]
+    #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM0_MOD         Fld(3, 16) //[18:16]
+    #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM1_MOD         Fld(3, 20) //[22:20]
+    #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM2_MOD         Fld(3, 24) //[26:24]
+    #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM3_MOD         Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_RK1_CURRENT_TX_SETTING3                      (DRAMC_NAO_BASE_ADDRESS + 0x0718)
+    #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ0_MOD   Fld(3, 0) //[2:0]
+    #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ1_MOD   Fld(3, 4) //[6:4]
+    #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ2_MOD   Fld(3, 8) //[10:8]
+    #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ3_MOD   Fld(3, 12) //[14:12]
+    #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM0_MOD  Fld(3, 16) //[18:16]
+    #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM1_MOD  Fld(3, 20) //[22:20]
+    #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM2_MOD  Fld(3, 24) //[26:24]
+    #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM3_MOD  Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_RK1_CURRENT_TX_SETTING4                      (DRAMC_NAO_BASE_ADDRESS + 0x071C)
+    #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ0_MOD      Fld(3, 0) //[2:0]
+    #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ1_MOD      Fld(3, 4) //[6:4]
+    #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ2_MOD      Fld(3, 8) //[10:8]
+    #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ3_MOD      Fld(3, 12) //[14:12]
+    #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM0_MOD     Fld(3, 16) //[18:16]
+    #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM1_MOD     Fld(3, 20) //[22:20]
+    #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM2_MOD     Fld(3, 24) //[26:24]
+    #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM3_MOD     Fld(3, 28) //[30:28]
+
+#define DRAMC_REG_RK1_DUMMY_RD_DATA0                           (DRAMC_NAO_BASE_ADDRESS + 0x0720)
+    #define RK1_DUMMY_RD_DATA0_DUMMY_RD_RK1_DATA0              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK1_DUMMY_RD_DATA1                           (DRAMC_NAO_BASE_ADDRESS + 0x0724)
+    #define RK1_DUMMY_RD_DATA1_DUMMY_RD_RK1_DATA1              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK1_DUMMY_RD_DATA2                           (DRAMC_NAO_BASE_ADDRESS + 0x0728)
+    #define RK1_DUMMY_RD_DATA2_DUMMY_RD_RK1_DATA2              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK1_DUMMY_RD_DATA3                           (DRAMC_NAO_BASE_ADDRESS + 0x072C)
+    #define RK1_DUMMY_RD_DATA3_DUMMY_RD_RK1_DATA3              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK1_DUMMY_RD_DATA4                           (DRAMC_NAO_BASE_ADDRESS + 0x0730)
+    #define RK1_DUMMY_RD_DATA4_DUMMY_RD_RK1_DATA4              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK1_DUMMY_RD_DATA5                           (DRAMC_NAO_BASE_ADDRESS + 0x0734)
+    #define RK1_DUMMY_RD_DATA5_DUMMY_RD_RK1_DATA5              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK1_DUMMY_RD_DATA6                           (DRAMC_NAO_BASE_ADDRESS + 0x0738)
+    #define RK1_DUMMY_RD_DATA6_DUMMY_RD_RK1_DATA6              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK1_DUMMY_RD_DATA7                           (DRAMC_NAO_BASE_ADDRESS + 0x073C)
+    #define RK1_DUMMY_RD_DATA7_DUMMY_RD_RK1_DATA7              Fld(32, 0) //[31:0]
+
+#define DRAMC_REG_RK1_PI_DQ_CAL                                (DRAMC_NAO_BASE_ADDRESS + 0x0760)
+    #define RK1_PI_DQ_CAL_RK1_ARPI_DQ_B0_CAL                   Fld(6, 0) //[5:0]
+    #define RK1_PI_DQ_CAL_RK1_ARPI_DQ_B1_CAL                   Fld(6, 8) //[13:8]
+    #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1                        Fld(6, 16) //[21:16]
+    #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_OVERFLOW               Fld(1, 22) //[22:22]
+    #define RK1_PI_DQ_CAL_RK1_B0_PI_CHANGE_DBG                 Fld(1, 23) //[23:23]
+    #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_B1                     Fld(6, 24) //[29:24]
+    #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_B1_OVERFLOW            Fld(1, 30) //[30:30]
+    #define RK1_PI_DQ_CAL_RK1_B1_PI_CHANGE_DBG                 Fld(1, 31) //[31:31]
+
+#define DRAMC_REG_RK1_PI_DQM_CAL                               (DRAMC_NAO_BASE_ADDRESS + 0x0768)
+    #define RK1_PI_DQM_CAL_RK1_ARPI_DQM_B0_CAL                 Fld(6, 0) //[5:0]
+    #define RK1_PI_DQM_CAL_RK1_ARPI_DQM_B1_CAL                 Fld(6, 8) //[13:8]
+
+#define DRAMC_REG_MR_BACKUP_00_RK0_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0900)
+    #define MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR1           Fld(8, 0) //[7:0]
+    #define MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR2           Fld(8, 8) //[15:8]
+    #define MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR3           Fld(8, 16) //[23:16]
+    #define MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR4           Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_01_RK0_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0904)
+    #define MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR9           Fld(8, 0) //[7:0]
+    #define MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR10          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR11          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR12          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_02_RK0_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0908)
+    #define MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR13          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR14          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR15          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR16          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_03_RK0_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x090C)
+    #define MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR17          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR18          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR19          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR20          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_04_RK0_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0910)
+    #define MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR21          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR22          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR23          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR24          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_05_RK0_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0914)
+    #define MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR25          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR26          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR27          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR28          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_06_RK0_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0918)
+    #define MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR30          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR31          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR32          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR33          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_07_RK0_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x091C)
+    #define MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR34          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR37          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR39          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR40          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_08_RK0_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0920)
+    #define MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR41          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR42          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR46          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR48          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_09_RK0_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0924)
+    #define MR_BACKUP_09_RK0_FSP0_MRWBK_RK0_FSP0_MR63          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_09_RK0_FSP0_MRWBK_RK0_FSP0_MR51          Fld(8, 8) //[15:8]
+
+#define DRAMC_REG_MR_BACKUP_00_RK0_FSP1                        (DRAMC_NAO_BASE_ADDRESS + 0x0930)
+    #define MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR1           Fld(8, 0) //[7:0]
+    #define MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR2           Fld(8, 8) //[15:8]
+    #define MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR3           Fld(8, 16) //[23:16]
+    #define MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR10          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_01_RK0_FSP1                        (DRAMC_NAO_BASE_ADDRESS + 0x0934)
+    #define MR_BACKUP_01_RK0_FSP1_MRWBK_RK0_FSP1_MR11          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_01_RK0_FSP1_MRWBK_RK0_FSP1_MR12          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_01_RK0_FSP1_MRWBK_RK0_FSP1_MR14          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_01_RK0_FSP1_MRWBK_RK0_FSP1_MR15          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_02_RK0_FSP1                        (DRAMC_NAO_BASE_ADDRESS + 0x0938)
+    #define MR_BACKUP_02_RK0_FSP1_MRWBK_RK0_FSP1_MR17          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_02_RK0_FSP1_MRWBK_RK0_FSP1_MR18          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_02_RK0_FSP1_MRWBK_RK0_FSP1_MR19          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_02_RK0_FSP1_MRWBK_RK0_FSP1_MR20          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_03_RK0_FSP1                        (DRAMC_NAO_BASE_ADDRESS + 0x093C)
+    #define MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR22          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR24          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR30          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR41          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_04_RK0_FSP1                        (DRAMC_NAO_BASE_ADDRESS + 0x0940)
+    #define MR_BACKUP_04_RK0_FSP1_MRWBK_RK0_FSP1_MR21          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_04_RK0_FSP1_MRWBK_RK0_FSP1_MR51          Fld(8, 8) //[15:8]
+
+#define DRAMC_REG_MR_BACKUP_00_RK0_FSP2                        (DRAMC_NAO_BASE_ADDRESS + 0x0960)
+    #define MR_BACKUP_00_RK0_FSP2_MRWBK_RK0_FSP2_MR1           Fld(8, 0) //[7:0]
+    #define MR_BACKUP_00_RK0_FSP2_MRWBK_RK0_FSP2_MR2           Fld(8, 8) //[15:8]
+    #define MR_BACKUP_00_RK0_FSP2_MRWBK_RK0_FSP2_MR3           Fld(8, 16) //[23:16]
+    #define MR_BACKUP_00_RK0_FSP2_MRWBK_RK0_FSP2_MR10          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_01_RK0_FSP2                        (DRAMC_NAO_BASE_ADDRESS + 0x0964)
+    #define MR_BACKUP_01_RK0_FSP2_MRWBK_RK0_FSP2_MR11          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_01_RK0_FSP2_MRWBK_RK0_FSP2_MR12          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_01_RK0_FSP2_MRWBK_RK0_FSP2_MR14          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_01_RK0_FSP2_MRWBK_RK0_FSP2_MR15          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_02_RK0_FSP2                        (DRAMC_NAO_BASE_ADDRESS + 0x0968)
+    #define MR_BACKUP_02_RK0_FSP2_MRWBK_RK0_FSP2_MR17          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_02_RK0_FSP2_MRWBK_RK0_FSP2_MR18          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_02_RK0_FSP2_MRWBK_RK0_FSP2_MR19          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_02_RK0_FSP2_MRWBK_RK0_FSP2_MR20          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_03_RK0_FSP2                        (DRAMC_NAO_BASE_ADDRESS + 0x096C)
+    #define MR_BACKUP_03_RK0_FSP2_MRWBK_RK0_FSP2_MR24          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_03_RK0_FSP2_MRWBK_RK0_FSP2_MR30          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_03_RK0_FSP2_MRWBK_RK0_FSP2_MR41          Fld(8, 16) //[23:16]
+
+#define DRAMC_REG_MR_BACKUP_00_RK1_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0B00)
+    #define MR_BACKUP_00_RK1_FSP0_MRWBK_RK1_FSP0_MR1           Fld(8, 0) //[7:0]
+    #define MR_BACKUP_00_RK1_FSP0_MRWBK_RK1_FSP0_MR2           Fld(8, 8) //[15:8]
+    #define MR_BACKUP_00_RK1_FSP0_MRWBK_RK1_FSP0_MR3           Fld(8, 16) //[23:16]
+    #define MR_BACKUP_00_RK1_FSP0_MRWBK_RK1_FSP0_MR4           Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_01_RK1_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0B04)
+    #define MR_BACKUP_01_RK1_FSP0_MRWBK_RK1_FSP0_MR9           Fld(8, 0) //[7:0]
+    #define MR_BACKUP_01_RK1_FSP0_MRWBK_RK1_FSP0_MR10          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_01_RK1_FSP0_MRWBK_RK1_FSP0_MR11          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_01_RK1_FSP0_MRWBK_RK1_FSP0_MR12          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_02_RK1_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0B08)
+    #define MR_BACKUP_02_RK1_FSP0_MRWBK_RK1_FSP0_MR13          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_02_RK1_FSP0_MRWBK_RK1_FSP0_MR14          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_02_RK1_FSP0_MRWBK_RK1_FSP0_MR15          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_02_RK1_FSP0_MRWBK_RK1_FSP0_MR16          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_03_RK1_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0B0C)
+    #define MR_BACKUP_03_RK1_FSP0_MRWBK_RK1_FSP0_MR17          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_03_RK1_FSP0_MRWBK_RK1_FSP0_MR18          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_03_RK1_FSP0_MRWBK_RK1_FSP0_MR19          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_03_RK1_FSP0_MRWBK_RK1_FSP0_MR20          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_04_RK1_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0B10)
+    #define MR_BACKUP_04_RK1_FSP0_MRWBK_RK1_FSP0_MR21          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_04_RK1_FSP0_MRWBK_RK1_FSP0_MR22          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_04_RK1_FSP0_MRWBK_RK1_FSP0_MR23          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_04_RK1_FSP0_MRWBK_RK1_FSP0_MR24          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_05_RK1_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0B14)
+    #define MR_BACKUP_05_RK1_FSP0_MRWBK_RK1_FSP0_MR25          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_05_RK1_FSP0_MRWBK_RK1_FSP0_MR26          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_05_RK1_FSP0_MRWBK_RK1_FSP0_MR27          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_05_RK1_FSP0_MRWBK_RK1_FSP0_MR28          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_06_RK1_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0B18)
+    #define MR_BACKUP_06_RK1_FSP0_MRWBK_RK1_FSP0_MR30          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_06_RK1_FSP0_MRWBK_RK1_FSP0_MR31          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_06_RK1_FSP0_MRWBK_RK1_FSP0_MR32          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_06_RK1_FSP0_MRWBK_RK1_FSP0_MR33          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_07_RK1_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0B1C)
+    #define MR_BACKUP_07_RK1_FSP0_MRWBK_RK1_FSP0_MR34          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_07_RK1_FSP0_MRWBK_RK1_FSP0_MR37          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_07_RK1_FSP0_MRWBK_RK1_FSP0_MR39          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_07_RK1_FSP0_MRWBK_RK1_FSP0_MR40          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_08_RK1_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0B20)
+    #define MR_BACKUP_08_RK1_FSP0_MRWBK_RK1_FSP0_MR41          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_08_RK1_FSP0_MRWBK_RK1_FSP0_MR42          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_08_RK1_FSP0_MRWBK_RK1_FSP0_MR46          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_08_RK1_FSP0_MRWBK_RK1_FSP0_MR48          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_09_RK1_FSP0                        (DRAMC_NAO_BASE_ADDRESS + 0x0B24)
+    #define MR_BACKUP_09_RK1_FSP0_MRWBK_RK1_FSP0_MR63          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_09_RK1_FSP0_MRWBK_RK1_FSP0_MR51          Fld(8, 8) //[15:8]
+
+#define DRAMC_REG_MR_BACKUP_00_RK1_FSP1                        (DRAMC_NAO_BASE_ADDRESS + 0x0B30)
+    #define MR_BACKUP_00_RK1_FSP1_MRWBK_RK1_FSP1_MR1           Fld(8, 0) //[7:0]
+    #define MR_BACKUP_00_RK1_FSP1_MRWBK_RK1_FSP1_MR2           Fld(8, 8) //[15:8]
+    #define MR_BACKUP_00_RK1_FSP1_MRWBK_RK1_FSP1_MR3           Fld(8, 16) //[23:16]
+    #define MR_BACKUP_00_RK1_FSP1_MRWBK_RK1_FSP1_MR10          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_01_RK1_FSP1                        (DRAMC_NAO_BASE_ADDRESS + 0x0B34)
+    #define MR_BACKUP_01_RK1_FSP1_MRWBK_RK1_FSP1_MR11          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_01_RK1_FSP1_MRWBK_RK1_FSP1_MR12          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_01_RK1_FSP1_MRWBK_RK1_FSP1_MR14          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_01_RK1_FSP1_MRWBK_RK1_FSP1_MR15          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_02_RK1_FSP1                        (DRAMC_NAO_BASE_ADDRESS + 0x0B38)
+    #define MR_BACKUP_02_RK1_FSP1_MRWBK_RK1_FSP1_MR17          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_02_RK1_FSP1_MRWBK_RK1_FSP1_MR18          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_02_RK1_FSP1_MRWBK_RK1_FSP1_MR19          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_02_RK1_FSP1_MRWBK_RK1_FSP1_MR20          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_03_RK1_FSP1                        (DRAMC_NAO_BASE_ADDRESS + 0x0B3C)
+    #define MR_BACKUP_03_RK1_FSP1_MRWBK_RK1_FSP1_MR22          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_03_RK1_FSP1_MRWBK_RK1_FSP1_MR24          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_03_RK1_FSP1_MRWBK_RK1_FSP1_MR30          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_03_RK1_FSP1_MRWBK_RK1_FSP1_MR41          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_04_RK1_FSP1                        (DRAMC_NAO_BASE_ADDRESS + 0x0B40)
+    #define MR_BACKUP_04_RK1_FSP1_MRWBK_RK1_FSP1_MR21          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_04_RK1_FSP1_MRWBK_RK1_FSP1_MR51          Fld(8, 8) //[15:8]
+
+#define DRAMC_REG_MR_BACKUP_00_RK1_FSP2                        (DRAMC_NAO_BASE_ADDRESS + 0x0B60)
+    #define MR_BACKUP_00_RK1_FSP2_MRWBK_RK1_FSP2_MR1           Fld(8, 0) //[7:0]
+    #define MR_BACKUP_00_RK1_FSP2_MRWBK_RK1_FSP2_MR2           Fld(8, 8) //[15:8]
+    #define MR_BACKUP_00_RK1_FSP2_MRWBK_RK1_FSP2_MR3           Fld(8, 16) //[23:16]
+    #define MR_BACKUP_00_RK1_FSP2_MRWBK_RK1_FSP2_MR10          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_01_RK1_FSP2                        (DRAMC_NAO_BASE_ADDRESS + 0x0B64)
+    #define MR_BACKUP_01_RK1_FSP2_MRWBK_RK1_FSP2_MR11          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_01_RK1_FSP2_MRWBK_RK1_FSP2_MR12          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_01_RK1_FSP2_MRWBK_RK1_FSP2_MR14          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_01_RK1_FSP2_MRWBK_RK1_FSP2_MR15          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_02_RK1_FSP2                        (DRAMC_NAO_BASE_ADDRESS + 0x0B68)
+    #define MR_BACKUP_02_RK1_FSP2_MRWBK_RK1_FSP2_MR17          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_02_RK1_FSP2_MRWBK_RK1_FSP2_MR18          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_02_RK1_FSP2_MRWBK_RK1_FSP2_MR19          Fld(8, 16) //[23:16]
+    #define MR_BACKUP_02_RK1_FSP2_MRWBK_RK1_FSP2_MR20          Fld(8, 24) //[31:24]
+
+#define DRAMC_REG_MR_BACKUP_03_RK1_FSP2                        (DRAMC_NAO_BASE_ADDRESS + 0x0B6C)
+    #define MR_BACKUP_03_RK1_FSP2_MRWBK_RK1_FSP2_MR24          Fld(8, 0) //[7:0]
+    #define MR_BACKUP_03_RK1_FSP2_MRWBK_RK1_FSP2_MR30          Fld(8, 8) //[15:8]
+    #define MR_BACKUP_03_RK1_FSP2_MRWBK_RK1_FSP2_MR41          Fld(8, 16) //[23:16]
+
+#endif // __DRAMC_NAO_REGS_H__
diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_actiming.h b/src/vendorcode/mediatek/mt8195/include/dramc_actiming.h
new file mode 100644
index 000000000000..bb1d5a52af4c
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/dramc_actiming.h
@@ -0,0 +1,397 @@
+#ifndef _ACTIMING_H
+#define _ACTIMING_H
+
+/***********************************************************************/
+/*              Includes                                               */
+/***********************************************************************/
+#include "dramc_register.h"
+
+
+//Definitions to enable specific freq's LP4 ACTiming support (To save code size)
+#define SUPPORT_LP5_DDR6400_ACTIM 0
+#define SUPPORT_LP5_DDR5500_ACTIM 0
+#define SUPPORT_LP5_DDR4266_ACTIM 0
+#define SUPPORT_LP5_DDR3200_ACTIM 0
+#define SUPPORT_LP4_DDR4266_ACTIM 1
+#define SUPPORT_LP4_DDR3733_ACTIM 1
+#define SUPPORT_LP4_DDR3200_ACTIM 1
+#define SUPPORT_LP4_DDR2667_ACTIM 0
+#define SUPPORT_LP4_DDR2400_ACTIM 1
+#define SUPPORT_LP4_DDR1866_ACTIM 1
+#define SUPPORT_LP4_DDR1600_ACTIM 1
+#define SUPPORT_LP4_DDR1333_ACTIM 0
+#define SUPPORT_LP4_DDR1200_ACTIM 1
+#define SUPPORT_LP4_DDR800_ACTIM  1
+#if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
+#define SUPPORT_LP4_DDR400_ACTIM  1
+#else
+#define SUPPORT_LP4_DDR400_ACTIM  0
+#endif
+/* Used to keep track the total number of LP4 ACTimings */
+/* Since READ_DBI is enable/disabled using preprocessor C define
+ * -> Save code size by excluding unneeded ACTimingTable entries
+ * Note 1: READ_DBI on/off is for (LP4 data rate >= DDR2667 (FSP1))
+ * Must make sure DDR3733 is the 1st entry (DMCATRAIN_INTV is used)
+ */
+typedef enum
+{
+#if SUPPORT_LP4_DDR4266_ACTIM
+#if ENABLE_READ_DBI
+    AC_TIME_LP4_BYTE_DDR4266_RDBI_ON = 0,
+    AC_TIME_LP4_NORM_DDR4266_RDBI_ON,
+#else //(ENABLE_READ_DBI == 0)
+    AC_TIME_LP4_BYTE_DDR4266_RDBI_OFF,
+    AC_TIME_LP4_NORM_DDR4266_RDBI_OFF,
+#endif //ENABLE_READ_DBI
+#endif
+
+#if SUPPORT_LP4_DDR3733_ACTIM
+#if ENABLE_READ_DBI
+    AC_TIME_LP4_BYTE_DDR3733_RDBI_ON,
+    AC_TIME_LP4_NORM_DDR3733_RDBI_ON,
+#else //(ENABLE_READ_DBI == 0)
+    AC_TIME_LP4_BYTE_DDR3733_RDBI_OFF,
+    AC_TIME_LP4_NORM_DDR3733_RDBI_OFF,
+#endif //ENABLE_READ_DBI
+#endif
+
+#if SUPPORT_LP4_DDR3200_ACTIM
+#if ENABLE_READ_DBI
+    AC_TIME_LP4_BYTE_DDR3200_RDBI_ON,
+    AC_TIME_LP4_NORM_DDR3200_RDBI_ON,
+#else //(ENABLE_READ_DBI == 0)
+    AC_TIME_LP4_BYTE_DDR3200_RDBI_OFF,
+    AC_TIME_LP4_NORM_DDR3200_RDBI_OFF,
+#endif //ENABLE_READ_DBI
+#endif
+
+#if SUPPORT_LP4_DDR2667_ACTIM
+#if ENABLE_READ_DBI
+    AC_TIME_LP4_BYTE_DDR2667_RDBI_ON,
+    AC_TIME_LP4_NORM_DDR2667_RDBI_ON,
+#else //(ENABLE_READ_DBI == 0)
+    AC_TIME_LP4_BYTE_DDR2667_RDBI_OFF,
+    AC_TIME_LP4_NORM_DDR2667_RDBI_OFF,
+#endif //ENABLE_READ_DBI
+#endif
+
+#if SUPPORT_LP4_DDR2400_ACTIM
+    AC_TIME_LP4_BYTE_DDR2400_RDBI_OFF,
+    AC_TIME_LP4_NORM_DDR2400_RDBI_OFF,
+#endif
+
+#if SUPPORT_LP4_DDR1866_ACTIM
+    AC_TIME_LP4_BYTE_DDR1866_RDBI_OFF,
+    AC_TIME_LP4_NORM_DDR1866_RDBI_OFF,
+#endif
+
+#if SUPPORT_LP4_DDR1600_ACTIM
+    AC_TIME_LP4_BYTE_DDR1600_RDBI_OFF,
+    AC_TIME_LP4_NORM_DDR1600_RDBI_OFF,
+    AC_TIME_LP4_BYTE_DDR1600_DIV4_RDBI_OFF,
+    AC_TIME_LP4_NORM_DDR1600_DIV4_RDBI_OFF,
+#endif
+
+#if SUPPORT_LP4_DDR1333_ACTIM
+    AC_TIME_LP4_BYTE_DDR1333_RDBI_OFF,
+    AC_TIME_LP4_NORM_DDR1333_RDBI_OFF,
+#endif
+
+
+#if SUPPORT_LP4_DDR1200_ACTIM
+    AC_TIME_LP4_BYTE_DDR1200_RDBI_OFF,
+    AC_TIME_LP4_NORM_DDR1200_RDBI_OFF,
+    AC_TIME_LP4_BYTE_DDR1200_DIV4_RDBI_OFF,
+    AC_TIME_LP4_NORM_DDR1200_DIV4_RDBI_OFF,
+#endif
+
+#if SUPPORT_LP4_DDR800_ACTIM
+    AC_TIME_LP4_BYTE_DDR800_RDBI_OFF,
+    AC_TIME_LP4_NORM_DDR800_RDBI_OFF,
+    AC_TIME_LP4_BYTE_DDR800_DIV4_RDBI_OFF,
+    AC_TIME_LP4_NORM_DDR800_DIV4_RDBI_OFF,
+#endif
+
+#if SUPPORT_LP4_DDR400_ACTIM
+    AC_TIME_LP4_BYTE_DDR400_RDBI_OFF,
+    AC_TIME_LP4_NORM_DDR400_RDBI_OFF,
+#endif
+
+    AC_TIMING_NUMBER_LP4
+} AC_TIMING_LP4_COUNT_TYPE_T;
+
+#if (__LP5_COMBO__)
+/* Used to keep track the total number of LP5 ACTimings */
+typedef enum
+{
+#if SUPPORT_LP5_DDR6400_ACTIM
+#if ENABLE_READ_DBI
+        AC_TIME_LP5_BYTE_DDR6400_RDBI_ON = 0,
+        AC_TIME_LP5_NORM_DDR6400_RDBI_ON,
+#else //(ENABLE_READ_DBI == 0)
+        AC_TIME_LP5_BYTE_DDR6400_RDBI_OFF,
+        AC_TIME_LP5_NORM_DDR6400_RDBI_OFF,
+#endif //ENABLE_READ_DBI
+#endif
+
+#if SUPPORT_LP5_DDR5500_ACTIM
+#if ((ENABLE_READ_DBI) || (LP5_DDR4266_RDBI_WORKAROUND))
+    AC_TIME_LP5_BYTE_DDR5500_RDBI_ON,
+    AC_TIME_LP5_NORM_DDR5500_RDBI_ON,
+#else
+    AC_TIME_LP5_BYTE_DDR5500_RDBI_OFF,
+    AC_TIME_LP5_NORM_DDR5500_RDBI_OFF,
+#endif
+#endif
+
+#if SUPPORT_LP5_DDR4266_ACTIM
+#if ((ENABLE_READ_DBI) || (LP5_DDR4266_RDBI_WORKAROUND))
+        AC_TIME_LP5_BYTE_DDR4266_RDBI_ON,
+        AC_TIME_LP5_NORM_DDR4266_RDBI_ON,
+#else //(ENABLE_READ_DBI == 0)
+        AC_TIME_LP5_BYTE_DDR4266_RDBI_OFF,
+        AC_TIME_LP5_NORM_DDR4266_RDBI_OFF,
+#endif //ENABLE_READ_DBI
+#endif
+
+#if SUPPORT_LP5_DDR3200_ACTIM
+    AC_TIME_LP5_BYTE_DDR3200_RDBI_OFF,
+    AC_TIME_LP5_NORM_DDR3200_RDBI_OFF,
+#endif
+    AC_TIMING_NUMBER_LP5
+} AC_TIMING_LP5_COUNT_TYPE_T;
+#else
+#define AC_TIMING_NUMBER_LP5    0
+#endif
+
+/* ACTiming struct declaration (declared here due Fld_wid for each register type)
+ * Should include all fields from ACTiming excel file (And update the correct values in UpdateACTimingReg()
+ * Note: DQSINCTL, DATLAT aren't in ACTiming excel file (internal delay parameters)
+ */
+typedef struct _ACTime_T_LP4
+{
+    U8 dramType, cbtMode, readDBI;
+    U8 DivMode;
+    U16 freq;
+    U8 readLat, writeLat;
+    U8 dqsinctl, datlat; //DQSINCTL, DATLAT aren't in ACTiming excel file
+
+    U8 tras;
+    U8 trp;
+    U8 trpab;
+    U8 trc;
+    U8 trfc;
+    U8 trfcpb;
+    U8 txp;
+    U8 trtp;
+    U8 trcd;
+    U8 twr;
+    U8 twtr;
+    U8 tpbr2pbr;
+    U8 tpbr2act;
+    U8 tr2mrw;
+    U8 tw2mrw;
+    U8 tmrr2mrw;
+    U8 tmrw;
+    U8 tmrd;
+    U8 tmrwckel;
+    U8 tpde;
+    U8 tpdx;
+    U8 tmrri;
+    U8 trrd;
+    U8 trrd_4266;
+    U8 tfaw;
+    U8 tfaw_4266;
+    U8 trtw_odt_off;
+    U8 trtw_odt_on;
+    U16 txrefcnt;
+    U8 tzqcs;
+    U8 xrtw2w_new_mode;
+    U8 xrtw2w_old_mode;
+    U8 xrtw2r_odt_on;
+    U8 xrtw2r_odt_off;
+    U8 xrtr2w_odt_on;
+    U8 xrtr2w_odt_off;
+    U8 xrtr2r_new_mode;
+    U8 xrtr2r_old_mode;
+    U8 tr2mrr;
+    U8 vrcgdis_prdcnt;
+    U8 hwset_mr2_op;
+    U8 hwset_mr13_op;
+    U8 hwset_vrcg_op;
+    U8 trcd_derate;
+    U8 trc_derate;
+    U8 tras_derate;
+    U8 trpab_derate;
+    U8 trp_derate;
+    U8 trrd_derate;
+    U8 trtpd;
+    U8 twtpd;
+    U8 tmrr2w_odt_off;
+    U8 tmrr2w_odt_on;
+    U8 ckeprd;
+    U8 ckelckcnt;
+    U8 zqlat2;
+
+    //DRAMC_REG_SHU_AC_TIME_05T ===================================
+    U8 tras_05T;
+    U8 trp_05T;
+    U8 trpab_05T;
+    U8 trc_05T;
+    U8 trfc_05T;
+    U8 trfcpb_05T;
+    U8 txp_05T;
+    U8 trtp_05T;
+    U8 trcd_05T;
+    U8 twr_05T;
+    U8 twtr_05T;
+    U8 tpbr2pbr_05T;
+    U8 tpbr2act_05T;
+    U8 tr2mrw_05T;
+    U8 tw2mrw_05T;
+    U8 tmrr2mrw_05T;
+    U8 tmrw_05T;
+    U8 tmrd_05T;
+    U8 tmrwckel_05T;
+    U8 tpde_05T;
+    U8 tpdx_05T;
+    U8 tmrri_05T;
+    U8 trrd_05T;
+    U8 trrd_4266_05T;
+    U8 tfaw_05T;
+    U8 tfaw_4266_05T;
+    U8 trtw_odt_off_05T;
+    U8 trtw_odt_on_05T;
+    U8 trcd_derate_05T;
+    U8 trc_derate_05T;
+    U8 tras_derate_05T;
+    U8 trpab_derate_05T;
+    U8 trp_derate_05T;
+    U8 trrd_derate_05T;
+    U8 trtpd_05T;
+    U8 twtpd_05T;
+} ACTime_T_LP4;
+
+typedef struct _ACTime_T_LP5
+{
+    U8 dramType, cbtMode, readDBI;
+    U8 DivMode;
+    U16 freq;
+    U8 readLat, writeLat;
+    U8 dqsinctl, datlat; //DQSINCTL, DATLAT aren't in ACTiming excel file
+
+    U8 tras;
+    U8 trp;
+    U8 trpab;
+    U8 trc;
+    U8 trfc;
+    U8 trfcpb;
+    U8 txp;
+    U8 trtp;
+    U8 trcd;
+    U8 twr;
+    U8 twtr;
+    U8 twtr_l;
+    U8 tpbr2pbr;
+    U8 tpbr2act;
+    U8 tr2mrw;
+    U8 tw2mrw;
+    U8 tmrr2mrw;
+    U8 tmrw;
+    U8 tmrd;
+    U8 tmrwckel;
+    U8 tpde;
+    U8 tpdx;
+    U8 tmrri;
+    U8 trrd;
+    U8 tfaw;
+    U8 tr2w_odt_off;
+    U8 tr2w_odt_on;
+    U16 txrefcnt;
+    U8 wckrdoff;
+    U8 wckwroff;
+    U8 tzqcs;
+    U8 xrtw2w_odt_off;
+    U8 xrtw2w_odt_on;
+    U8 xrtw2r_odt_off_otf_off;
+    U8 xrtw2r_odt_on_otf_off;
+    U8 xrtw2r_odt_off_otf_on;
+    U8 xrtw2r_odt_on_otf_on;
+    U8 xrtr2w_odt_on;
+    U8 xrtr2w_odt_off;
+    U8 xrtr2r_odt_off;
+    U8 xrtr2r_odt_on;
+    U8 xrtw2w_odt_off_wck;
+    U8 xrtw2w_odt_on_wck;
+    U8 xrtw2r_odt_off_wck;
+    U8 xrtw2r_odt_on_wck;
+    U8 xrtr2w_odt_off_wck;
+    U8 xrtr2w_odt_on_wck;
+    U8 xrtr2r_wck;
+    U8 tr2mrr;
+    U8 hwset_mr2_op;
+    U8 hwset_mr13_op;
+    U8 hwset_vrcg_op;
+    U8 vrcgdis_prdcnt;
+    U8 lp5_cmd1to2en;
+    U8 trtpd;
+    U8 twtpd;
+    U8 tmrr2w;
+    U8 ckeprd;
+    U8 ckelckcnt;
+    U8 tcsh_cscal;
+    U8 tcacsh;
+    U8 tcsh;
+    U8 trcd_derate;
+    U8 trc_derate;
+    U8 tras_derate;
+    U8 trpab_derate;
+    U8 trp_derate;
+    U8 trrd_derate;
+    U8 zqlat2;
+
+    //DRAMC_REG_SHU_AC_TIME_05T ===================================
+    U8 tras_05T;
+    U8 trp_05T;
+    U8 trpab_05T;
+    U8 trc_05T;
+    U8 trfc_05T;
+    U8 trfcpb_05T;
+    U8 txp_05T;
+    U8 trtp_05T;
+    U8 trcd_05T;
+    U8 twr_05T;
+    U8 twtr_05T;
+    U8 twtr_l_05T;
+    U8 tr2mrw_05T;
+    U8 tw2mrw_05T;
+    U8 tmrr2mrw_05T;
+    U8 tmrw_05T;
+    U8 tmrd_05T;
+    U8 tmrwckel_05T;
+    U8 tpde_05T;
+    U8 tpdx_05T;
+    U8 tmrri_05T;
+    U8 trrd_05T;
+    U8 tfaw_05T;
+    U8 tr2w_odt_off_05T;
+    U8 tr2w_odt_on_05T;
+    U8 wckrdoff_05T;
+    U8 wckwroff_05T;
+    U8 trtpd_05T;
+    U8 twtpd_05T;
+    U8 tpbr2pbr_05T;
+    U8 tpbr2act_05T;
+    U8 trcd_derate_05T;
+    U8 trc_derate_05T;
+    U8 tras_derate_05T;
+    U8 trpab_derate_05T;
+    U8 trp_derate_05T;
+    U8 trrd_derate_05T;
+} ACTime_T_LP5;
+
+//ACTimingTbl[] forward declaration
+
+extern U8 vDramcACTimingGetDatLat(DRAMC_CTX_T *p);
+extern DRAM_STATUS_T DdrUpdateACTiming(DRAMC_CTX_T *p);
+#endif
diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_common.h b/src/vendorcode/mediatek/mt8195/include/dramc_common.h
new file mode 100644
index 000000000000..f0a5b9106680
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/dramc_common.h
@@ -0,0 +1,285 @@
+/*
+ *
+ * DRAMC_COMMON.H
+ *
+ */
+
+#ifndef _DRAMC_COMMON_H_
+#define _DRAMC_COMMON_H_
+
+
+#include <soc/dramc_soc.h>
+
+#include <delay.h>
+#include <device/mmio.h>
+#include <stdint.h>
+#include <types.h>
+#include <reg.h>
+#include <soc/dramc_common.h>
+#include <timer.h>
+#include <print.h>
+
+#include <string.h>
+#include "dramc_register.h"
+#include "dramc_pi_api.h"
+#include "dramc_int_slt.h"
+#include "print.h"
+#include "reg.h"
+
+#if FOR_DV_SIMULATION_USED == 1
+#include "dramc_dv_init.h"
+#else
+#ifdef __DPM__
+#include "dramc_dpm.h"
+#elif __ETT__
+#include "common.h"
+#endif
+#endif
+
+#if __ETT__
+#include "dramc_version.h"
+#else
+#define _VERSION_ "ETT Version 0.0.0.1"
+#define _COMMIT_VERSION_ "01234567"
+#define _COMMIT_DATE_ "2020-10-10/10:10:10"
+#endif
+/***********************************************************************/
+/*                  Public Types                                       */
+/***********************************************************************/
+
+/*------------------------------------------------------------*/
+/*                  macros, defines, typedefs, enums          */
+/*------------------------------------------------------------*/
+/************************** Common Macro *********************/
+
+
+#define dsb()		asm volatile("dsb sy" : : : "memory")
+#define DRV_Reg32(x)		read32((const void *)((u64)(x)))
+#define DRV_WriteReg32(x, y)	write32((void *)((u64)(x)), (y))
+
+#define mcDELAY_US(x)       udelay(x)
+#define mcDELAY_MS(x)       udelay(x*1000)
+#define mcDELAY_XUS(x)      udelay(x)
+#define mcDELAY_XNS(x)      udelay(1)
+// choose a proper mcDELAY
+#if defined(__DPM__)
+#define mcDELAY_US(x)		timer_busy_wait_us(TIMER3, x)
+#define mcDELAY_XUS(x)		timer_busy_wait_us(TIMER3, x)
+#define mcDELAY_XNS(x)		timer_busy_wait_us(TIMER3, 1)
+#define mcDELAY_MS(x)		timer_busy_wait_ms(TIMER3, x)
+#endif
+
+/**********************************************/
+/* Priority of debug log                      */
+/*--------------------------------------------*/
+/* mcSHOW_DBG_MSG: High                       */
+/* mcSHOW_DBG_MSG2: Medium High               */
+/* mcSHOW_DBG_MSG3: Medium Low                */
+/* mcSHOW_DBG_MSG4: Low                       */
+/**********************************************/
+#if __FLASH_TOOL_DA__
+  #define printf DBG_MSG
+  #define print DBG_MSG
+#elif defined(RELEASE)
+#if !__ETT__
+  #undef printf
+  #define printf
+  #undef print
+  #define print
+#endif
+#endif
+
+#if FOR_DV_SIMULATION_USED
+    #define mcSHOW_DBG_MSG(_x_)   {printf _x_;}
+    #define mcSHOW_DBG_MSG2(_x_)  {printf _x_;}
+    #define mcSHOW_DBG_MSG3(_x_)  {printf _x_;}
+    #define mcSHOW_DBG_MSG4(_x_)  {printf _x_;}
+    #define mcSHOW_DBG_MSG5(_x_)
+    #define mcSHOW_DBG_MSG6(_x_)  {printf _x_;}
+    #define mcSHOW_EYESCAN_MSG(_x_)
+    #define mcSHOW_TIME_MSG(_x_)
+    #define mcSHOW_ERR_MSG(_x_)   {printf _x_;}
+    #define mcSHOW_DUMP_INIT_RG_MSG(_x_)  {printf _x_;}
+#elif __ETT__
+    #if QT_GUI_Tool
+        #if MRW_CHECK_ONLY
+        #define mcSHOW_DBG_MSG_tmp(...) {printf (__VA_ARGS__);  if(fp_A60868){fprintf (fp_A60868,__VA_ARGS__);}}
+        #define mcSHOW_DBG_MSG_Dump(...)
+        #define mcSHOW_DBG_MSG(_x_)
+        #define mcSHOW_DBG_MSG2(_x_)
+        #define mcSHOW_DBG_MSG3(_x_)
+        #define mcSHOW_DBG_MSG4(_x_)
+        #define mcSHOW_DBG_MSG5(_x_)
+        #define mcSHOW_DBG_MSG6(_x_)
+        #define mcSHOW_EYESCAN_MSG(_x_)
+        #define mcSHOW_TIME_MSG(_x_)
+        #define mcSHOW_ERR_MSG(_x_)
+        #define mcSHOW_DUMP_INIT_RG_MSG(_x_)
+        #define mcSHOW_MRW_MSG(_x_)    {mcSHOW_DBG_MSG_tmp _x_;}
+        #else
+        #define mcSHOW_DBG_MSG_tmp(...)   {printf (__VA_ARGS__);  if(fp_A60868){fprintf (fp_A60868,__VA_ARGS__);}}
+        #define mcSHOW_DBG_MSG_Dump(...)  {if(fp_A60868_RGDump){fprintf (fp_A60868_RGDump,__VA_ARGS__);}}
+        #define mcSHOW_DBG_MSG(_x_)   {mcSHOW_DBG_MSG_tmp _x_;}
+        #define mcSHOW_DBG_MSG2(_x_)  {mcSHOW_DBG_MSG_tmp _x_;}
+        #define mcSHOW_DBG_MSG3(_x_)  {mcSHOW_DBG_MSG_tmp _x_;}
+        #define mcSHOW_DBG_MSG4(_x_)  {mcSHOW_DBG_MSG_tmp _x_;}
+        #define mcSHOW_DBG_MSG5(_x_)
+        #define mcSHOW_DBG_MSG6(_x_)
+        #define mcSHOW_EYESCAN_MSG(_x_) {mcSHOW_DBG_MSG_tmp _x_;}
+        #define mcSHOW_TIME_MSG(_x_)
+        #define mcSHOW_ERR_MSG(_x_)   {mcSHOW_DBG_MSG_tmp _x_;}
+        #define mcSHOW_DUMP_INIT_RG_MSG(_x_)
+        #endif
+    #elif (defined(DDR_INIT_TIME_PROFILING))
+    #define mcSHOW_DBG_MSG(_x_)
+    #define mcSHOW_DBG_MSG2(_x_)
+    #define mcSHOW_DBG_MSG3(_x_)
+    #define mcSHOW_DBG_MSG4(_x_)
+    #define mcSHOW_DBG_MSG5(_x_)
+    #define mcSHOW_DBG_MSG6(_x_)
+    #define mcSHOW_JV_LOG_MSG(_x_)
+    #define mcSHOW_EYESCAN_MSG(_x_)
+    #define mcSHOW_TIME_MSG(_x_)   {opt_print _x_;}
+    #define mcSHOW_ERR_MSG(_x_)
+    #elif DUMP_ALLSUH_RG
+    #define mcSHOW_DBG_MSG(_x_)     {mcDELAY_US(50);opt_print _x_;}
+    #define mcSHOW_DBG_MSG2(_x_)    {mcDELAY_US(50); opt_print _x_;}
+    #define mcSHOW_DBG_MSG3(_x_)
+    #define mcSHOW_DBG_MSG4(_x_)
+    #define mcSHOW_DBG_MSG5(_x_)
+    #define mcSHOW_DBG_MSG6(_x_)
+    #define mcSHOW_JV_LOG_MSG(_x_)
+    #define mcSHOW_EYESCAN_MSG(_x_)
+    #define mcSHOW_TIME_MSG(_x_)
+    #define mcSHOW_ERR_MSG(_x_) {mcDELAY_US(50);opt_print _x_;}
+    #elif defined(RELEASE)
+    #define mcSHOW_DBG_MSG(_x_)  //{opt_print _x_;}
+    #define mcSHOW_DBG_MSG2(_x_)
+    #define mcSHOW_DBG_MSG3(_x_)
+    #define mcSHOW_DBG_MSG4(_x_)
+    #define mcSHOW_DBG_MSG5(_x_)
+    #define mcSHOW_DBG_MSG6(_x_)
+    #define mcSHOW_JV_LOG_MSG(_x_) {opt_print _x_;}
+    #define mcSHOW_EYESCAN_MSG(_x_) {opt_print _x_;}   //mcSHOW_JV_LOG_MSG(_x_) is for vendor JV
+    #define mcSHOW_TIME_MSG(_x_)
+    #define mcSHOW_ERR_MSG(_x_)  {opt_print _x_;}
+    #elif VENDER_JV_LOG
+    #define mcSHOW_DBG_MSG(_x_)
+    #define mcSHOW_DBG_MSG2(_x_)
+    #define mcSHOW_DBG_MSG3(_x_)
+    #define mcSHOW_DBG_MSG4(_x_)
+    #define mcSHOW_DBG_MSG5(_x_)
+    #define mcSHOW_DBG_MSG6(_x_)
+    #define mcSHOW_JV_LOG_MSG(_x_)    {opt_print _x_;}   //mcSHOW_JV_LOG_MSG(_x_) is for vendor JV
+    #define mcSHOW_EYESCAN_MSG(_x_) {opt_print _x_;}   //mcSHOW_JV_LOG_MSG(_x_) is for vendor JV
+    #define mcSHOW_TIME_MSG(_x_)
+    #define mcSHOW_ERR_MSG(_x_)
+    #elif SW_CHANGE_FOR_SIMULATION
+    #define mcSHOW_DBG_MSG(_x_)
+    #define mcSHOW_DBG_MSG2(_x_)
+    #define mcSHOW_DBG_MSG3(_x_)
+    #define mcSHOW_DBG_MSG4(_x_)
+    #define mcSHOW_DBG_MSG5(_x_)
+    #define mcSHOW_DBG_MSG6(_x_)
+    #define mcSHOW_JV_LOG_MSG(_x_)
+    #define mcSHOW_EYESCAN_MSG(_x_)
+    #define mcSHOW_TIME_MSG(_x_)
+    #define mcSHOW_ERR_MSG(_x_)
+    #elif defined(DUMP_INIT_RG_LOG_TO_DE)
+    #define mcSHOW_DBG_MSG(_x_)
+    #define mcSHOW_DBG_MSG2(_x_)
+    #define mcSHOW_DBG_MSG3(_x_)
+    #define mcSHOW_DBG_MSG4(_x_)
+    #define mcSHOW_DBG_MSG5(_x_)
+    #define mcSHOW_DBG_MSG6(_x_)
+    #define mcSHOW_JV_LOG_MSG(_x_)
+    #define mcSHOW_DUMP_INIT_RG_MSG(_x_) {gpt_busy_wait_us(50); print _x_;}
+    #define mcSHOW_EYESCAN_MSG(_x_)
+    #define mcSHOW_TIME_MSG(_x_)
+    #define mcSHOW_ERR_MSG(_x_)
+    #elif MRW_CHECK_ONLY
+    #define mcSHOW_DBG_MSG(_x_)
+    #define mcSHOW_DBG_MSG2(_x_)
+    #define mcSHOW_DBG_MSG3(_x_)
+    #define mcSHOW_DBG_MSG4(_x_)
+    #define mcSHOW_DBG_MSG5(_x_)
+    #define mcSHOW_DBG_MSG6(_x_)
+    #define mcSHOW_JV_LOG_MSG(_x_)
+    #define mcSHOW_MRW_MSG(_x_)    {printf _x_;}
+    #define mcSHOW_EYESCAN_MSG(_x_)
+    #define mcSHOW_TIME_MSG(_x_)
+    #define mcSHOW_ERR_MSG(_x_)
+    #else   // ETT real chip
+    #define mcSHOW_DBG_MSG(_x_)   {mcDELAY_US(10); print _x_;}
+    #define mcSHOW_DBG_MSG2(_x_)  {mcDELAY_US(10); print _x_;}
+    #define mcSHOW_DBG_MSG3(_x_)  {mcDELAY_US(10); print _x_;}
+    #define mcSHOW_DBG_MSG4(_x_)
+    #define mcSHOW_DBG_MSG5(_x_)
+    #define mcSHOW_DBG_MSG6(_x_)
+    #define mcSHOW_JV_LOG_MSG(_x_)
+    #define mcSHOW_EYESCAN_MSG(_x_) {if (gEye_Scan_color_flag) {mcDELAY_US(200);}; print _x_;}
+    #define mcSHOW_TIME_MSG(_x_)
+    #define mcSHOW_ERR_MSG(_x_)   {print _x_;}
+    #endif
+#else  // preloader
+    #if defined(DDR_INIT_TIME_PROFILING)
+    #define mcSHOW_DBG_MSG(_x_)
+    #define mcSHOW_DBG_MSG2(_x_)
+    #define mcSHOW_DBG_MSG3(_x_)
+    #define mcSHOW_DBG_MSG4(_x_)
+    #define mcSHOW_DBG_MSG5(_x_)
+    #define mcSHOW_DBG_MSG6(_x_)
+    #define mcSHOW_JV_LOG_MSG(_x_)
+    #define mcSHOW_EYESCAN_MSG(_x_)
+    #define mcSHOW_TIME_MSG(_x_)   {print _x_;}
+    #define mcSHOW_ERR_MSG(_x_)
+    #elif defined(TARGET_BUILD_VARIANT_ENG) //&& !defined(MTK_EFUSE_WRITER_SUPPORT) && !CFG_TEE_SUPPORT && !MTK_EMMC_SUPPORT
+    #define mcSHOW_DBG_MSG(_x_)   {print _x_;}
+    #define mcSHOW_DBG_MSG2(_x_)  {print _x_;}
+    #define mcSHOW_DBG_MSG3(_x_)  {print _x_;}
+    #define mcSHOW_DBG_MSG4(_x_)
+    #define mcSHOW_DBG_MSG5(_x_)
+    #define mcSHOW_DBG_MSG6(_x_)  {print _x_;}
+        #if (CFG_DRAM_LOG_TO_STORAGE)
+        #define mcSHOW_EYESCAN_MSG(_x_)  {print _x_;}
+        #define mcSHOW_JV_LOG_MSG(_x_)   {print _x_;}
+        #else
+        #define mcSHOW_EYESCAN_MSG(_x_)
+        #define mcSHOW_JV_LOG_MSG(_x_)
+        #endif
+    #define mcSHOW_TIME_MSG(_x_)
+    #define mcSHOW_ERR_MSG(_x_)   {print _x_;}
+    #else
+    #define mcSHOW_DBG_MSG(_x_)
+    #define mcSHOW_DBG_MSG2(_x_)
+    #define mcSHOW_DBG_MSG3(_x_)
+    #define mcSHOW_DBG_MSG4(_x_)
+    #define mcSHOW_DBG_MSG5(_x_)
+    #define mcSHOW_DBG_MSG6(_x_)
+    #define mcSHOW_JV_LOG_MSG(_x_)
+    #define mcSHOW_EYESCAN_MSG(_x_)
+    #define mcSHOW_TIME_MSG(_x_)
+    #define mcSHOW_ERR_MSG(_x_)     {print _x_;}
+    #endif
+#endif
+
+
+
+#if QT_GUI_Tool ==1
+#define mcFPRINTF(_x_)     fprintf _x_;
+#else
+#define mcFPRINTF(_x_)
+#endif
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(x)    (sizeof (x) / sizeof (x[0]))
+#endif
+
+#define enter_function() \
+	({mcSHOW_DBG_MSG(("enter %s\n", __FUNCTION__));})
+
+#define exit_function() \
+	({mcSHOW_DBG_MSG(("exit %s\n", __FUNCTION__));})
+
+extern int dump_log;
+#endif   // _DRAMC_COMMON_H_
diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_custom.h b/src/vendorcode/mediatek/mt8195/include/dramc_custom.h
new file mode 100644
index 000000000000..fa755ec9aefa
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/dramc_custom.h
@@ -0,0 +1,59 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2010. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("Media Tek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __DRAMC_CUSTOM_H__
+#define __DRAMC_CUSTOM_H__
+
+//[FOR_CHROMEOS] Define the EMI_SETTINGS here
+#include "dramc_top.h"
+
+
+EMI_SETTINGS g_default_emi_setting = {
+	.type = 0x0006,
+	.EMI_CONA_VAL = 0xf053f154,
+	.EMI_CONF_VAL = 0x08421000,
+	.EMI_CONH_VAL = 0x44440083,
+	.EMI_CONK_VAL = 0x0,
+	.CHN0_EMI_CONA_VAL = 0x0400f051,
+	.CHN1_EMI_CONA_VAL = 0x0400f051,
+	.DRAM_RANK_SIZE = {0x100000000, 0x100000000, 0x0, 0x0},
+	.dram_cbt_mode_extern = CBT_R0_R1_BYTE,
+	.iLPDDR3_MODE_REG_5 = 0x6,
+	.highest_freq = 4266,
+};
+#endif /* __DRAMC_CUSTOM_H__ */
+
diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_dv_init.h b/src/vendorcode/mediatek/mt8195/include/dramc_dv_init.h
new file mode 100644
index 000000000000..e870bddebba0
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/dramc_dv_init.h
@@ -0,0 +1,332 @@
+#ifndef _DRAMC_DV_INIT_H_
+#define _DRAMC_DV_INIT_H_
+
+#include "dramc_common.h"
+#include "dramc_int_global.h"
+#include "x_hal_io.h"
+#include "sv_c_data_traffic.h"
+
+
+//=========================================================
+//DRAM CONFIG ELEMENT COLLECTION
+//=========================================================
+typedef enum { DDR3, DDR4, LPDDR3, LPDDR4, LPDDR5, PSRAM } DRAM_TYPE_T;
+typedef enum {BG4BK4, BK8, BK16, BKORG_RFU} e_BKORG;
+typedef enum {DIS_both, EN_t, EN_both, EN_c} e_RDQSWCK;//MR20
+
+#define SA_CONFIG_EN 1
+#define DV_CONFIG_EN 1
+//=========================================================
+//Build Top configuration
+//=========================================================
+#define DFS_GROUP_NUM 10
+#define CH_NUM        2
+#define RK_NUM_PER_CH 2
+#define DONT_CARE_VALUE 0
+#define PULL_UP   1
+#define PULL_DOWN 1
+
+
+
+typedef struct Gating_config
+{
+    U8 GAT_TRACK_EN         ;
+    U8 RX_GATING_MODE       ; 
+    U8 RX_GATING_TRACK_MODE ;
+    U8 SELPH_MODE           ;
+    U8 PICG_EARLY_EN        ;
+    U8 VALID_LAT_VALUE      ; 
+}Gating_confg_T;
+
+
+//=========================================================
+//DV configuration connection
+//=========================================================
+#if DV_CONFIG_EN==1
+typedef struct DRAMC_DVFS_GROUP_transfer
+{
+    U8                CKR         ; //LPDDR5 CKR could be 4 and 2  other memory type should be 1
+    U8                DQSIEN_MODE ; //ANA DQSG mode config  LPDDR4 = 1, LPDDR5 with other modes
+    U8                DQ_P2S_RATIO; //16-1 8-1 4-1   LPDDR5 could support 16-1 mode
+    U8                RESERVED_8BIT;
+    U32               data_rate   ;
+}DRAMC_DVFS_GROUP_transfer_T;
+
+typedef struct DV_configuration
+{
+    U8  EX_ROW_EN_1      ;
+    U8  EX_ROW_EN_0      ;
+    U8  BYTE_MODE_1      ;
+    U8  BYTE_MODE_0      ;
+    U8  LP4Y_EN          ; 
+    U8  LP4_WR_PST       ;
+    U8  LP4_OTF          ;
+    U8  NEW_8X_MODE      ; 
+    U8  LP45_APHY_COMB_EN; 
+    U8  DLL_IDLE_MODE    ; 
+    U8  NEW_RANK_MODE    ; 
+    U8  DLL_ASYNC_EN     ; 
+    U8  MD32_EN          ;
+    U8  SRAM_EN          ;
+    U8  GP_NUM           ;
+} DV_new_config_T;
+#endif
+
+
+//=========================================================
+//LPDDR4 DRAM config
+//=========================================================
+typedef struct LP4_DRAM_CONFIG
+{
+    U8  BYTE_MODE[2]; //diff rank
+    U8  EX_ROW_EN[2]; //diff rank --density over 10G should 1
+    U8  MR_WL    ;     
+	U8  MR_RL    ;     
+	U8  BL       ;     
+	U8  RPST     ;     
+	U8  RD_PRE   ;     
+	U8  WR_PRE   ;     
+	U8  WR_PST   ;     
+	U8  DBI_WR   ;     
+	U8  DBI_RD   ;     
+//	U8  DMI      ;    //No use  default enable 
+	U8  OTF      ;     
+    U8  LP4Y_EN  ;
+    U8  WORK_FSP ;
+} LP4_DRAM_CONFIG_T;
+
+
+
+//=========================================================
+//LPDDR5 DRAM config
+//=========================================================
+typedef struct LP5_DRAM_CONFIG
+{
+    U8          BYTE_MODE[2] ; 
+    U8          EX_ROW_EN[2] ; 
+    U8          MR_WL        ;            
+	U8          MR_RL        ;            
+	U8          BL           ;            
+	U8          CK_Mode      ;   
+	U8          RPST         ;      
+	U8          RD_PRE       ;    
+	U8          WR_PRE       ;    
+	U8          WR_PST       ;    
+	U8          DBI_WR       ;    
+	U8          DBI_RD       ;    
+	U8          DMI          ;       
+	U8          OTF          ;           
+    U8          WCK_PST      ;
+    U8          RDQS_PRE     ;
+    U8          RDQS_PST     ;
+    U8          CA_ODT       ;
+    U8          DQ_ODT       ;
+    U8          CKR          ;
+    U8          WCK_ON       ;
+    U8          WCK_FM       ;
+    U8          WCK_ODT      ;
+    U8          DVFSQ        ;
+    U8          DVFSC        ;
+    e_RDQSWCK   RDQSmode[2]  ;
+    U8          WCKmode[2]   ;
+    U8          RECC         ;
+    U8          WECC         ;
+    e_BKORG     BankMode     ;
+    U8          WORK_FSP     ;
+} LP5_DRAM_CONFIG_T;
+
+//=========================================================
+//Analog PHY config
+//=========================================================
+typedef struct ANA_top_function_config
+{
+    U8   DLL_ASYNC_EN     ;
+    U8   ALL_SLAVE_EN     ;
+    U8   NEW_RANK_MODE    ;
+    U8   DLL_IDLE_MODE    ;
+    U8   LP45_APHY_COMB_EN;
+    U8   TX_ODT_DIS       ;
+    U8   NEW_8X_MODE      ;
+    U8   LP4_WDQS_MODE    ;
+}ANA_top_config_T;
+
+
+typedef struct ANA_DVFS_core_config
+{
+    U8   CKR;
+    U8   DQ_P2S_RATIO;
+    U8   LP5_1600_DQ_P2S_MODE;
+    U8   CA_P2S_RATIO;
+    U8   DQ_CA_OPEN;
+    U8   DQ_SEMI_OPEN;
+    U8   CA_SEMI_OPEN;
+    U8   CA_FULL_RATE;
+    U8   DQ_CKDIV4_EN;
+    U8   CA_CKDIV4_EN;
+    U8   CA_PREDIV_EN;
+    U8   PH8_DLY;
+    U8   SEMI_OPEN_CA_PICK_MCK_RATIO;
+    U8   DQ_AAMCK_DIV;
+    U8   CA_AAMCK_DIV;
+    U8   CA_ADMCK_DIV;
+    U8   DQ_TRACK_CA_EN;
+    U32  PLL_FREQ;
+    U8   DQ_UI_PI_RATIO;
+    U8   CA_UI_PI_RATIO;
+} ANA_DVFS_CORE_T;
+
+
+//=========================================================
+//DVFS group configuration
+//=========================================================
+typedef struct DRAMC_DVFS_GROUP_CONFIG
+{
+    U32               data_rate   ;
+    U8                DQSIEN_MODE ; //ANA DQSG mode config  LPDDR4 = 1, LPDDR5 with other modes
+    U8                DQ_P2S_RATIO; //16-1 8-1 4-1   LPDDR5 could support 16-1 mode
+    U8                CKR         ; //LPDDR5 CKR could be 4 and 2  other memory type should be 1
+}DRAMC_DVFS_GROUP_CONFIG_T;
+
+//=========================================================
+//DRAMC Subsystem config
+//=========================================================
+typedef struct DRAMC_SUBSYS_CONFIG
+{
+    U8                        GP_NUM               ;
+    U8                        SRAM_EN              ;
+    U8                        MD32_EN              ;
+    ANA_top_config_T          *a_cfg               ;
+    ANA_DVFS_CORE_T           *a_opt               ;
+    LP4_DRAM_CONFIG_T         *lp4_init            ;
+    LP5_DRAM_CONFIG_T         *lp5_init            ;
+    DRAMC_DVFS_GROUP_CONFIG_T *DFS_GP[DFS_GROUP_NUM];
+}DRAMC_SUBSYS_CONFIG_T;
+
+
+typedef struct DUT_shuf_config_T {         
+  U8         CKE_DBE_CNT                   ;
+  U8         FASTWAKE2                     ;
+  U8         DMPGTIM                       ;
+  U8         ADVPREEN                      ;
+  U8         DLE_256EN                     ;
+  U8         LECC                          ;
+  U8         WPST1P5T_OPT                  ;
+  U8         LP4YEN                        ;
+  U8         LP5_CAS_MODE                  ;
+  U8         LP5_SEP_ACT                   ;
+  U8         LP5_BGOTF                     ;
+  U8         LP5_BGEN                      ;
+  U8         LP5_RDQS_SE_EN                ;
+  U8         CKR                           ;
+  U8         DQSIEN_MODE                   ;
+  U8         DQ_P2S_RATIO                  ;
+  U32        data_rate                     ;
+}__attribute__((packed))  DUT_shuf_config_T;     
+
+
+typedef struct DUT_top_set_T {         
+  U8         PINMUX_setAB                  ;
+  U8         DVFSRTMRWEN                   ;
+  U8         NO_QUEUEFLUSH_EN              ;
+  U8         RG_SPM_MODE                   ;
+  U8         MD32_EN                       ;
+  U8         SRAM_EN                       ;
+  U8         RX_PIPE_BYPASS_EN             ;
+  U8         TX_PIPE_BYPASS_EN             ;
+  U32        WAIT_DLE_EXT_DLY              ;
+  U32        RX_DCM_EXT_DLY                ;
+  U8         old_dcm_mode                  ;
+  U8         DPHY_DCM_MODE                 ;
+  U8         TX_OE_EXT_OPT                 ;
+  U8         TXP_WORKAROUND_OPT            ;
+  U32        VALID_LAT_VALUE               ;
+  U8         RXTRACK_PBYTE_OPT             ;
+  U8         TRACK_UP_MODE                 ;
+  U8         TREFBWIG_IGNORE               ;
+  U8         SELPH_MODE                    ;
+  U8         EX_ROW_EN_RK1                 ;
+  U8         EX_ROW_EN_RK0                 ;
+  U8         RANK_SWAP                     ;
+  U8         BGPIPE_EN                     ;
+  U8         PICG_MODE                     ;
+  U8         RTMRR_MODE                    ;
+  U8         TMRRI_MODE                    ;
+  U8         DQS_OSC_AT_TIMER              ;
+  U8         WPST1P5T_OPT                  ;
+  U8         LP5_ZQ_OPT                    ;
+  U8         LP5WRAPEN                     ;
+  U8         LP4_SE_MODE                   ;
+  U8         LP4Y_EN                       ;
+  U8         LP4_WR_PST                    ;
+  U8         LP4_OTF                       ;
+  U8         PLL_MODE_OPTION               ;
+  U8         NEW_8X_MODE                   ;
+  U8         LP45_APHY_COMB_EN             ;
+  U8         DLL_IDLE_MODE                 ;
+  U8         NEW_RANK_MODE                 ;
+  U8         DLL_ASYNC_EN                  ;
+  U32        memory_type                   ;
+  U32        GP_NUM                        ;
+}__attribute__((packed))  DUT_top_set_T;     
+
+
+
+extern Gating_confg_T Gat_p;
+extern DRAM_TYPE_T MEM_TYPE;
+extern LP4_DRAM_CONFIG_T LP4_INIT;
+extern LP5_DRAM_CONFIG_T LP5_INIT;
+extern ANA_top_config_T ana_top_p;
+extern ANA_DVFS_CORE_T ANA_option;
+extern DRAMC_DVFS_GROUP_CONFIG_T DFS_TOP[DFS_GROUP_NUM];
+extern DRAMC_SUBSYS_CONFIG_T DV_p;
+extern DRAMC_CTX_T *DramcConfig;
+extern DUT_top_set_T  DUTTopSetGlobal;
+extern DUT_shuf_config_T  DUTShufConfigGlobal[10];
+
+#define A_T DV_p.a_cfg
+#define A_D DV_p.a_opt
+#define M_LP4 DV_p.lp4_init
+#define DFS(i) DV_p.DFS_GP[i]
+#define LPDDR5_EN_S ((MEM_TYPE==LPDDR5) ? 1 : 0)
+#define LPDDR4_EN_S ((MEM_TYPE==LPDDR4) ? 1 : 0)
+
+#define  DUT_p DUTTopSetGlobal
+#define  DUT_shu_p DUTShufConfigGlobal
+
+
+#if FOR_DV_SIMULATION_USED==1
+EXTERN void register_write(int address, int data);
+EXTERN void register_read(int address, int * data);
+EXTERN void delay_us(u32 delta);
+EXTERN void delay_ns(u32 delta);
+EXTERN void timestamp_show();
+EXTERN void build_api_initial();
+EXTERN void register_write_c(u32 address, u32 data);
+EXTERN u32 register_read_c(u32 address);
+EXTERN void conf_to_sram_sudo(int ch_id , int group_id, int conf_id);
+//================ added by Lingyun Wu 11.14 =====================
+EXTERN void broadcast_on(void);
+EXTERN void broadcast_off(void);
+//================ added by Lingyun Wu 11.14 =====================
+EXTERN void mygetscope();
+EXTERN void mysetscope();
+#endif
+
+
+#if DV_CONFIG_EN
+extern void get_dfs_configuration_from_DV_random(DRAMC_DVFS_GROUP_transfer_T * tr, int group_id);
+extern void get_top_configuration_from_DV_random(DV_new_config_T * tr);
+#endif
+//DRAM LP4 initial configuration 
+extern void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr);
+extern void DPI_SW_main_LP4(DRAMC_CTX_T *p, cal_sv_rand_args_t *psra);
+extern void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr);
+#if __LP5_COMBO__
+extern void LP5_DRAM_config(DRAMC_DVFS_GROUP_CONFIG_T *dfs_tr, LP5_DRAM_CONFIG_T *tr);
+#endif
+extern void ANA_TOP_FUNCTION_CFG(ANA_top_config_T *tr,U16 data_rate);
+extern void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs);
+extern void ANA_sequence_shuffle_colletion(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr);
+extern void ANA_Config_shuffle(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 group_id);
+
+#endif   // _DRAMC_DV_INIT_H_
diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_int_global.h b/src/vendorcode/mediatek/mt8195/include/dramc_int_global.h
new file mode 100644
index 000000000000..2fa925cff9c4
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/dramc_int_global.h
@@ -0,0 +1,660 @@
+#ifndef _INT_GLOBAL_H
+#define _INT_GLOBAL_H
+
+#include "dramc_pi_api.h"
+#include "dramc_int_slt.h"
+
+/*
+ ****************************************************************************************
+ ** macro
+ ****************************************************************************************
+ */
+#define DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM 0
+//#define DVT_TEST_DUMMY_READ_FOR_DQS_GATING_TRACKING
+//#define DVT_TEST_RX_DLY_HW_TRACKING
+
+
+/*
+ ****************************************************************************************
+ ** ANA_init_config.c
+ ****************************************************************************************
+ */
+EXTERN void ANA_init(DRAMC_CTX_T *p);
+EXTERN void RESETB_PULL_DN(DRAMC_CTX_T *p);
+
+
+
+/*
+ ****************************************************************************************
+ ** DIG_NONSHUF_config.c
+ ****************************************************************************************
+ */
+EXTERN void DIG_STATIC_SETTING(DRAMC_CTX_T *p);
+
+
+/*
+ ****************************************************************************************
+ *
+ ** DIG_SHUF_config.c
+ ****************************************************************************************
+ */
+EXTERN void DIG_CONFIG_SHUF(DRAMC_CTX_T *p,U32 ch_id, U32 group_id);
+
+
+/*
+ ****************************************************************************************
+ *
+ ** dramc_debug.c
+ ****************************************************************************************
+ */
+EXTERN U8 gFinalCBTVrefDQ[CHANNEL_NUM][RANK_MAX];
+EXTERN U8 gFinalRXVrefDQ[CHANNEL_NUM][RANK_MAX][2];
+EXTERN U8 gFinalTXVrefDQ[CHANNEL_NUM][RANK_MAX];
+
+#ifdef FOR_HQA_REPORT_USED
+EXTERN U8 gHQALog_flag;
+EXTERN U16 gHQALOG_RX_delay_cell_ps_075V;
+EXTERN U8 gHQALog_SLT_BIN[DRAM_DFS_SRAM_MAX];
+#endif
+
+
+// --- Eye scan variables -----
+
+EXTERN U8 gCBT_EYE_Scan_flag;
+EXTERN U8 gRX_EYE_Scan_flag;
+EXTERN U8 gTX_EYE_Scan_flag;
+EXTERN U8 gEye_Scan_color_flag;
+EXTERN U8 gCBT_EYE_Scan_only_higheset_freq_flag;
+EXTERN U8 gRX_EYE_Scan_only_higheset_freq_flag;
+EXTERN U8 gTX_EYE_Scan_only_higheset_freq_flag;
+EXTERN U8 gEye_Scan_unterm_highest_flag;
+
+#if ENABLE_EYESCAN_GRAPH
+#define VREF_TOTAL_NUM_WITH_RANGE (((51 + 30) + 1) / (EYESCAN_GRAPH_CATX_VREF_STEP < EYESCAN_GRAPH_RX_VREF_STEP ? EYESCAN_GRAPH_CATX_VREF_STEP : EYESCAN_GRAPH_RX_VREF_STEP))	//range0 0~50 + range1 21~50
+#define EYESCAN_BROKEN_NUM 3
+#define EYESCAN_DATA_INVALID 0x7f
+EXTERN S16  gEyeScan_Min[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH][EYESCAN_BROKEN_NUM];
+EXTERN S16  gEyeScan_Max[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH][EYESCAN_BROKEN_NUM];
+EXTERN S16 gEyeScan_MinMax_store_delay[DQS_BYTE_NUMBER];
+EXTERN U16 gEyeScan_CaliDelay[DQS_BYTE_NUMBER];
+EXTERN U16  gEyeScan_WinSize[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH];
+EXTERN S16  gEyeScan_DelayCellPI[DQ_DATA_WIDTH];
+EXTERN U16 gEyeScan_ContinueVrefHeight[DQ_DATA_WIDTH];
+EXTERN U16 gEyeScan_TotalPassCount[DQ_DATA_WIDTH];
+EXTERN void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p);
+EXTERN void print_EYESCAN_LOG_message(DRAMC_CTX_T *p, U8 print_type);
+#endif
+#if MRW_CHECK_ONLY || MRW_BACKUP
+EXTERN U8 gFSPWR_Flag[RANK_MAX];
+#endif
+#ifdef FOR_HQA_TEST_USED
+EXTERN void HQA_measure_message_reset_all_data(DRAMC_CTX_T *p);
+#endif
+#if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION
+void DramcRunTimeShmooRG_BackupRestore(DRAMC_CTX_T *p);
+#endif
+#if DUMP_ALLSUH_RG
+EXTERN void DumpAllChAllShuRG(DRAMC_CTX_T *p);
+#endif
+#if PIN_CHECK_TOOL
+//EXTERN U8* print_Impedence_LOG_type(U8 print_type);
+EXTERN void vPrintPinInfoResult(DRAMC_CTX_T *p);
+EXTERN void vGetErrorTypeResult(DRAMC_CTX_T *p);
+EXTERN DEBUG_PIN_INF_FOR_FLASHTOOL_T PINInfo_flashtool;
+#endif
+#ifdef DEVIATION
+extern U8 gSetSpecificedVref_Enable[];
+extern U8 gSetSpecificedVref_Type;
+extern U8 gSetSpecificedVref_All_ChRk[];
+extern U8 gSetSpecificedVref_Channel[];
+extern U8 gSetSpecificedVref_Rank[];
+extern S8 gSetSpecificedVref_Vref_Offset[];
+#endif
+
+
+/*
+ ****************************************************************************************
+ ** dramc_dvfs.c
+ ****************************************************************************************
+ */
+EXTERN void vSetDFSTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable);
+EXTERN DRAM_DFS_FREQUENCY_TABLE_T* get_FreqTbl_by_SRAMIndex(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T SRAMIdx);
+EXTERN void vSetDFSFreqSelByTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable);
+EXTERN void DramcDFSDirectJump(DRAMC_CTX_T *p, U8 shu_level);
+EXTERN void DramcSaveToShuffleSRAM(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T srcRG, DRAM_DFS_SRAM_SHU_T dstRG);
+EXTERN void LoadShuffleSRAMtoDramc(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T srcRG, DRAM_DFS_REG_SHU_T dstRG);
+EXTERN void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_level);
+EXTERN void DVFSSettings(DRAMC_CTX_T *p);
+EXTERN void DPMEnableTracking(DRAMC_CTX_T *p, U32 u4Reg, U32 u4Field, U8 u1ShuIdx, U8 u1Enable);
+EXTERN void DPMInit(DRAMC_CTX_T *p);
+EXTERN void DramcCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr);
+EXTERN void DdrphyCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr);
+EXTERN void EnableDFSHwModeClk(DRAMC_CTX_T *p);
+
+
+/*
+ ****************************************************************************************
+ ** dramc_dv_freq_related.c
+ ****************************************************************************************
+ */
+EXTERN void sv_algorithm_assistance_LP4_1600(DRAMC_CTX_T *p);
+EXTERN void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p);
+EXTERN void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p);
+EXTERN void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p);
+EXTERN void CInit_golden_mini_freq_related_vseq_LP4_4266(DRAMC_CTX_T *p);
+EXTERN void CInit_golden_mini_freq_related_vseq_LP5_3200(DRAMC_CTX_T *p);
+EXTERN void CInit_golden_mini_freq_related_vseq_LP5_3200_SHU1(DRAMC_CTX_T *p);
+EXTERN void CInit_golden_mini_freq_related_vseq_LP5_4266(DRAMC_CTX_T *p);
+EXTERN void CInit_golden_mini_freq_related_vseq_LP5_5500(DRAMC_CTX_T *p);
+
+
+/*
+ ****************************************************************************************
+ ** dramc_dv_main.c
+ ****************************************************************************************
+ */
+#if (FOR_DV_SIMULATION_USED == 1)
+EXTERN void DPI_DRAMC_init_entry();
+EXTERN void DPI_DRAM_INIT();
+#endif
+
+
+/*
+ ****************************************************************************************
+ ** dramc_pi_basic.c
+ ****************************************************************************************
+ */
+EXTERN U8 u1PrintModeRegWrite;
+EXTERN void vApplyConfigBeforeCalibration(DRAMC_CTX_T *p);
+EXTERN DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p);
+EXTERN void SetCKE2RankIndependent(DRAMC_CTX_T *p);
+EXTERN void DramcDQSPrecalculation_TrackingOff(DRAMC_CTX_T *p, U8 shu_level);
+EXTERN void DramcDQSPrecalculation_TrackingOn(DRAMC_CTX_T *p, U8 shu_level);
+EXTERN void DramcHWDQSGatingTracking_ModeSetting(DRAMC_CTX_T *p);
+//EXTERN void Set_MRR_Pinmux_Mapping(DRAMC_CTX_T *p);
+//EXTERN void Set_DQO1_Pinmux_Mapping(DRAMC_CTX_T *p);
+#if CBT_MOVE_CA_INSTEAD_OF_CLK
+EXTERN void DramcCmdUIDelaySetting(DRAMC_CTX_T *p, U8 value);
+#endif
+EXTERN void cbt_switch_freq(DRAMC_CTX_T *p, U8 freq);
+EXTERN DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p);
+EXTERN DRAM_STATUS_T DramcModeRegInit_CATerm(DRAMC_CTX_T *p, U8 bWorkAround);
+EXTERN void DramcPowerOnSequence(DRAMC_CTX_T *p);
+EXTERN void Global_Option_Init(DRAMC_CTX_T *p);
+EXTERN U16 u2DFSGetHighestFreq(DRAMC_CTX_T * p);
+EXTERN void EnableDRAMModeRegWriteDBIAfterCalibration(DRAMC_CTX_T *p);
+EXTERN void EnableDRAMModeRegReadDBIAfterCalibration(DRAMC_CTX_T *p);
+EXTERN void ApplyWriteDBIPowerImprove(DRAMC_CTX_T *p, U8 onoff);
+EXTERN void DramcHMR4_Presetting(DRAMC_CTX_T *p);
+#if ENABLE_PER_BANK_REFRESH
+EXTERN void DramcSetPerBankRefreshMode(DRAMC_CTX_T *p);
+#endif
+//EXTERN void RXPICGSetting(DRAMC_CTX_T * p);
+EXTERN void TXPICGNewModeEnable(DRAMC_CTX_T * p);
+EXTERN unsigned int DDRPhyFreqMeter(DRAMC_CTX_T * p);
+#ifndef DPM_CONTROL_AFTERK
+EXTERN void dramc_exit_with_DFS_legacy_mode(DRAMC_CTX_T * p);
+#endif
+
+
+
+/*
+ ****************************************************************************************
+ ** dramc_pi_calibration_api.c
+ ****************************************************************************************
+ */
+EXTERN U16 gu2MR0_Value[RANK_MAX];	//read only mode register
+EXTERN U32 gDramcImpedanceResult[IMP_VREF_MAX][IMP_DRV_MAX];	//ODT_ON/OFF x DRVP/DRVN/ODTP/ODTN
+EXTERN U8 gCBT_VREF_RANGE_SEL;
+EXTERN JMETER_DELAYCELL_T JMeter_DelayCell_Table[DRAM_DFS_SRAM_MAX];
+EXTERN U8 uiLPDDR4_O1_Mapping_POP[CHANNEL_NUM][16];
+EXTERN const U8 uiLPDDR4_O1_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16];
+EXTERN U8 uiLPDDR4_CA_Mapping_POP[CHANNEL_NUM][6];
+EXTERN const U8 uiLPDDR4_CA_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][6];
+
+#if __ETT__
+EXTERN U8 gETT_WHILE_1_flag;
+#endif
+
+#ifdef FOR_HQA_TEST_USED
+EXTERN U16 gFinalCBTVrefCA[CHANNEL_NUM][RANK_MAX];
+EXTERN U16 gFinalCBTCA[CHANNEL_NUM][RANK_MAX][10];
+EXTERN U16 gFinalRXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH];
+EXTERN U16 gFinalTXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH];
+EXTERN U16 gFinalTXPerbitWin_min_max[CHANNEL_NUM][RANK_MAX];
+EXTERN U16 gFinalTXPerbitWin_min_margin[CHANNEL_NUM][RANK_MAX];
+EXTERN U16 gFinalTXPerbitWin_min_margin_bit[CHANNEL_NUM][RANK_MAX];
+EXTERN S8 gFinalClkDuty[CHANNEL_NUM];
+EXTERN U32 gFinalClkDutyMinMax[CHANNEL_NUM][2];
+EXTERN S8 gFinalDQSDuty[CHANNEL_NUM][DQS_BYTE_NUMBER];
+EXTERN U32 gFinalDQSDutyMinMax[CHANNEL_NUM][DQS_BYTE_NUMBER][2];
+#endif
+EXTERN U8 u1MR01Value[FSP_MAX];
+EXTERN U8 u1MR02Value[FSP_MAX];
+EXTERN U8 u1MR03Value[FSP_MAX];
+EXTERN U8 u1MR11Value[FSP_MAX];
+EXTERN U8 u1MR18Value[FSP_MAX];
+EXTERN U8 u1MR19Value[FSP_MAX];
+EXTERN U8 u1MR20Value[FSP_MAX];
+EXTERN U8 u1MR21Value[FSP_MAX];
+EXTERN U8 u1MR22Value[FSP_MAX];
+EXTERN U8 u1MR51Value[FSP_MAX];
+EXTERN U8 u1MR04Value[RANK_MAX];
+EXTERN U8 u1MR13Value[RANK_MAX];
+EXTERN U8 u1MR26Value[RANK_MAX];
+EXTERN U8 u1MR30Value[RANK_MAX];
+EXTERN U8 u1MR12Value[CHANNEL_NUM][RANK_MAX][FSP_MAX];
+EXTERN U8 u1MR14Value[CHANNEL_NUM][RANK_MAX][FSP_MAX];
+#if PINMUX_AUTO_TEST_PER_BIT_RX
+EXTERN U8 gRX_check_per_bit_flag;
+EXTERN S16 gFinalRXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH];
+#endif
+#if PINMUX_AUTO_TEST_PER_BIT_TX
+EXTERN U8 gTX_check_per_bit_flag;
+EXTERN S16 gFinalTXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH];
+#endif
+EXTERN U8 u1IsLP4Div4DDR800(DRAMC_CTX_T *p);
+EXTERN DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 u1VrefScanEnable, u8 isAutoK);
+EXTERN DRAM_STATUS_T DramcZQCalibration(DRAMC_CTX_T *p, U8 rank);
+EXTERN DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type);
+EXTERN DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T stDelayBase);
+EXTERN DRAM_STATUS_T dramc_rx_dqs_gating_cal(DRAMC_CTX_T *p, u8 autok, U8 use_enhanced_rdqs);
+EXTERN DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, RX_PATTERN_OPTION_T eRxPattern, U8 *u1AssignedVref, U8 isAutoK, U8 K_Type);
+EXTERN DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p);
+EXTERN DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p);
+EXTERN DRAM_STATUS_T DramcImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_region);
+EXTERN void DramcSwImpedanceSaveRegister(DRAMC_CTX_T *p, U8 ca_freq_option, U8 dq_freq_option, U8 save_to_where);
+EXTERN void vBeforeCalibration(DRAMC_CTX_T *p);
+EXTERN void vAfterCalibration(DRAMC_CTX_T *p);
+EXTERN void DramcRunTimeConfig(DRAMC_CTX_T *p);
+EXTERN DRAM_STATUS_T DramcDutyCycleMonitor(DRAMC_CTX_T *p);
+EXTERN void DramcTxOECalibration(DRAMC_CTX_T *p);
+EXTERN DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p);
+EXTERN void LP4_ShiftDQS_OENUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx);
+EXTERN void ShiftDQ_OENUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx);
+EXTERN U8 u1IsPhaseMode(DRAMC_CTX_T *p);
+//EXTERN void RODTSettings(DRAMC_CTX_T *p);
+//EXTERN void DQSSTBSettings(DRAMC_CTX_T *p);
+EXTERN void DramcWriteShiftMCKForWriteDBI(DRAMC_CTX_T *p, S8 iShiftMCK);
+EXTERN void DramPhyReset(DRAMC_CTX_T *p);
+//EXTERN U32 DramcRxWinRDDQCInit(DRAMC_CTX_T *p);
+//EXTERN U32 DramcRxWinRDDQCRun(DRAMC_CTX_T *p);
+//EXTERN U32 DramcRxWinRDDQCEnd(DRAMC_CTX_T *p);
+#if BYPASS_CALIBRATION
+EXTERN void dle_factor_handler(DRAMC_CTX_T *p, U8 curr_val);
+EXTERN void ShiftDQSWCK_UI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx);
+EXTERN void ShiftDQUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx);
+EXTERN void TXSetDelayReg_DQ(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdqm_ui_large[], U8 ucdqm_oen_ui_large[], U8 ucdqm_ui_small[], U8 ucdqm_oen_ui_small[], U8 ucdqm_pi[]);
+EXTERN void TXSetDelayReg_DQM(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdqm_ui_large[], U8 ucdqm_oen_ui_large[], U8 ucdqm_ui_small[], U8 ucdqm_oen_ui_small[], U8 ucdqm_pi[]);
+EXTERN void TXUpdateTXTracking(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 ucdq_pi[], U8 ucdqm_pi[]);
+EXTERN void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p);
+EXTERN void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p);
+#endif
+EXTERN void vInitGlobalVariablesByCondition(DRAMC_CTX_T *p);
+EXTERN void DramcDramcRxDVSCalPostProcess(DRAMC_CTX_T *p);
+EXTERN void CBTDelayCACLK(DRAMC_CTX_T *p, S32 iDelay);
+EXTERN U16 GetVcoreDelayCellTime(DRAMC_CTX_T *p);
+
+
+
+/*
+ ****************************************************************************************
+ ** dramc_pi_main.c
+ ****************************************************************************************
+ */
+EXTERN DRAMC_CTX_T gTimeProfilingDramCtx;
+EXTERN U8 gHQA_Test_Freq_Vcore_Level;
+#if (FOR_DV_SIMULATION_USED == 1)
+EXTERN U8 gu1BroadcastIsLP4;
+#endif
+EXTERN bool gAndroid_DVFS_en;
+EXTERN bool gUpdateHighestFreq;
+EXTERN DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX];
+EXTERN void dump_dramc_ctx(DRAMC_CTX_T *p);
+EXTERN void vCalibration_Flow_For_MDL(DRAMC_CTX_T *p);
+EXTERN void vDramCalibrationAllChannel(DRAMC_CTX_T *p);
+EXTERN U32 vGetVoltage(DRAMC_CTX_T *p, U32 get_voltage_type);
+#if __ETT__
+EXTERN void ett_set_emi_rank1_address(void);
+#endif
+
+
+/*
+ ****************************************************************************************
+ ** dramc_slt.c
+ ****************************************************************************************
+ */
+#if ENABLE_EMI_LPBK_TEST
+EXTERN U8 gEmiLpbkTest;
+#endif
+EXTERN void SLT_DramcDFS(DRAMC_CTX_T *p, int iDoDMA);
+EXTERN void SLT_DFSTestProgram(DRAMC_CTX_T *p, int iDoDMA);
+EXTERN void SLT_Test_DFS_and_Memory_Test(DRAMC_CTX_T*p);
+
+
+
+/*
+ ****************************************************************************************
+ ** dramc_temp_function.c
+ ****************************************************************************************
+ */
+EXTERN DRAMC_CTX_T DramCtx_LPDDR4;
+
+
+/*
+ ****************************************************************************************
+ ** dramc_tracking.c
+ ****************************************************************************************
+ */
+EXTERN U8 gu1MR23[CHANNEL_NUM][RANK_MAX];
+EXTERN void DramcHWGatingInit(DRAMC_CTX_T *p);
+EXTERN void DramcHWGatingOnOff(DRAMC_CTX_T *p, U8 u1OnOff);
+EXTERN void DramcHWGatingDebugOnOff(DRAMC_CTX_T *p, U8 u1OnOff);
+EXTERN void DramcPrintHWGatingStatus(DRAMC_CTX_T *p, U8 u1Channel);
+#if (ENABLE_TX_TRACKING || TDQSCK_PRECALCULATION_FOR_DVFS)
+EXTERN void FreqJumpRatioCalculation(DRAMC_CTX_T *p);
+#endif
+#if TDQSCK_PRECALCULATION_FOR_DVFS
+EXTERN void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p);
+EXTERN void DramcDQSPrecalculation_enable(DRAMC_CTX_T *p);
+#endif
+EXTERN void DramcDQSOSCInit(void);
+EXTERN DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p);
+#if ENABLE_TX_TRACKING
+EXTERN DRAM_STATUS_T DramcDQSOSCMR23(DRAMC_CTX_T *p);
+EXTERN DRAM_STATUS_T DramcDQSOSCSetMR18MR19(DRAMC_CTX_T *p);
+EXTERN DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p);
+EXTERN void DramcHwDQSOSC(DRAMC_CTX_T *p);
+EXTERN void Enable_TX_Tracking(DRAMC_CTX_T *p);
+#endif
+#if RDSEL_TRACKING_EN
+EXTERN void Enable_RDSEL_Tracking(DRAMC_CTX_T *p, U16 u2Freq);
+EXTERN void RDSELRunTimeTracking_preset(DRAMC_CTX_T *p);
+#endif
+#ifdef HW_GATING
+EXTERN void Enable_Gating_Tracking(DRAMC_CTX_T *p);
+#endif
+#if ENABLE_PER_BANK_REFRESH
+EXTERN void Enable_PerBank_Refresh(DRAMC_CTX_T *p);
+#endif
+EXTERN void DramcImpedanceHWSaving(DRAMC_CTX_T *p);
+#ifdef IMPEDANCE_TRACKING_ENABLE
+EXTERN void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p);
+#endif
+EXTERN void DramcRxInputDelayTrackingInit_Common(DRAMC_CTX_T *p);
+EXTERN void DramcRxInputDelayTrackingHW(DRAMC_CTX_T *p);
+EXTERN void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p);
+
+
+/*
+ ****************************************************************************************
+ ** dramc_utility.c
+ ****************************************************************************************
+ */
+EXTERN U16 gddrphyfmeter_value[DRAM_DFS_SRAM_MAX];
+#if FOR_DV_SIMULATION_USED
+EXTERN U8 u1BroadcastOnOff;
+#endif
+#if (fcFOR_CHIP_ID == fcA60868)
+EXTERN U8 u1EnterRuntime;
+#endif
+EXTERN U8 u1MaType;
+EXTERN void TA2_Test_Run_Time_HW_Set_Column_Num(DRAMC_CTX_T * p);
+EXTERN void TA2_Test_Run_Time_HW_Presetting(DRAMC_CTX_T * p, U32 len, TA2_RKSEL_TYPE_T rksel_mode);
+EXTERN void TA2_Test_Run_Time_Pat_Setting(DRAMC_CTX_T *p, U8 PatSwitch);
+EXTERN void TA2_Test_Run_Time_HW_Write(DRAMC_CTX_T * p, U8 u1Enable);
+EXTERN U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p);
+EXTERN void TA2_Test_Run_Time_HW(DRAMC_CTX_T * p);
+EXTERN void vAutoRefreshSwitch(DRAMC_CTX_T *p, U8 option);
+EXTERN void vSetRank(DRAMC_CTX_T *p, U8 ucRank);
+EXTERN void vSetPHY2ChannelMapping(DRAMC_CTX_T *p, U8 u1Channel);
+EXTERN VREF_CALIBRATION_ENABLE_T Get_Vref_Calibration_OnOff(DRAMC_CTX_T *p);
+EXTERN u8 lp5heff_save_disable(DRAMC_CTX_T *p);
+EXTERN void lp5heff_restore(DRAMC_CTX_T *p);
+EXTERN u8 is_lp5_family(DRAMC_CTX_T *p);
+EXTERN U32 GetDramcBroadcast(void);
+EXTERN void DramCLKAlwaysOnOff(DRAMC_CTX_T *p, U8 option, CHANNEL_RANK_SEL_T WriteChannelNUM);
+EXTERN void CKEFixOnOff(DRAMC_CTX_T *p, U8 u1RankIdx, CKE_FIX_OPTION option,
+		CHANNEL_RANK_SEL_T WriteChannelNUM);
+EXTERN void DramcBackupRegisters(DRAMC_CTX_T *p, U32 *backup_addr, U32 backup_num);
+EXTERN U8 u1GetRank(DRAMC_CTX_T *p);
+EXTERN void vPrintCalibrationBasicInfo(DRAMC_CTX_T *p);
+EXTERN void vPrintCalibrationBasicInfo_ForJV(DRAMC_CTX_T *p);
+EXTERN U32 DramcEngine2Run(DRAMC_CTX_T *p, DRAM_TE_OP_T wr, U8 testaudpat);
+EXTERN void DramcEngine2End(DRAMC_CTX_T *p);
+EXTERN DRAM_STATUS_T DramcEngine2Init(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1TestPat, U8 u1LoopCnt, U8 u1EnableUiShift);
+EXTERN void DramcRestoreRegisters(DRAMC_CTX_T *p, U32 *restore_addr, U32 restore_num);
+EXTERN DDR800_MODE_T vGet_DDR_Loop_Mode(DRAMC_CTX_T *p);
+EXTERN u8 is_heff_mode(DRAMC_CTX_T *p);
+EXTERN void DramcEngine2SetPat(DRAMC_CTX_T *p, U8 u1TestPat, U8 u1LoopCnt, U8 u1Len1Flag, U8 u1EnableUiShift);
+EXTERN void DramcSetRankEngine2(DRAMC_CTX_T *p, U8 u1RankSel);
+EXTERN U16 GetFreqBySel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel);
+EXTERN U8 GetEyeScanEnable(DRAMC_CTX_T * p, U8 get_type);
+EXTERN U8 vGetPHY2ChannelMapping(DRAMC_CTX_T *p);
+EXTERN DUTY_CALIBRATION_T Get_Duty_Calibration_Mode(DRAMC_CTX_T *p);
+EXTERN void DDRPhyFreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel);
+EXTERN DRAM_DFS_SRAM_SHU_T vGet_Current_SRAMIdx(DRAMC_CTX_T *p);
+EXTERN void vSetChannelNumber(DRAMC_CTX_T *p);
+EXTERN void vSetRankNumber(DRAMC_CTX_T *p);
+EXTERN void vSetFSPNumber(DRAMC_CTX_T *p);
+EXTERN void vCKERankCtrl(DRAMC_CTX_T *p, CKE_CTRL_MODE_T CKECtrlMode);
+EXTERN DRAM_PLL_FREQ_SEL_T vGet_PLL_FreqSel(DRAMC_CTX_T *p);
+EXTERN void vSet_PLL_FreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel);
+EXTERN void Temp_TA2_Test_After_K(DRAMC_CTX_T * p);
+EXTERN void DramcBroadcastOnOff(U32 bOnOff);
+EXTERN DIV_MODE_T vGet_Div_Mode(DRAMC_CTX_T *p);
+EXTERN void DramcMRWriteFldMsk(DRAMC_CTX_T *p, U8 mr_idx, U8 listValue, U8 msk, U8 UpdateMode);
+EXTERN void DramcMRWriteFldAlign(DRAMC_CTX_T *p, U8 mr_idx, U8 value, U32 mr_fld, U8 UpdateMode);
+EXTERN void DramcModeRegReadByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U16 *u2pValue);
+EXTERN void DramcModeRegRead(DRAMC_CTX_T *p, U8 u1MRIdx, U16 *u1pValue);
+EXTERN void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value);
+EXTERN void SetDramModeRegForWriteDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff);
+EXTERN void SetDramModeRegForReadDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff);
+#if MRW_CHECK_ONLY
+EXTERN void vPrintFinalModeRegisterSetting(DRAMC_CTX_T *p);
+#endif
+#if MRW_BACKUP
+EXTERN U8 DramcMRWriteBackup(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Rank);
+#endif
+#if QT_GUI_Tool
+EXTERN void TA2_Test_Run_Time_SW_Presetting(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 testaudpat, U8 log2loopcount);
+EXTERN U32 TestEngineCompare(DRAMC_CTX_T *p);
+#endif
+EXTERN void vSet_Div_Mode(DRAMC_CTX_T *p, DIV_MODE_T eMode);
+EXTERN void vSet_Current_SRAMIdx(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T u1ShuIndex);
+EXTERN void GetPhyPllFrequency(DRAMC_CTX_T *p);
+EXTERN void DramcWriteDBIOnOff(DRAMC_CTX_T *p, U8 onoff);
+EXTERN void DramcReadDBIOnOff(DRAMC_CTX_T *p, U8 onoff);
+EXTERN void CheckDramcWBR(U32 u4address);
+EXTERN void DramcModeRegWriteByRank_RTMRW(DRAMC_CTX_T *p, U8 *u1Rank, U8 *u1MRIdx, U8 *u1Value, U8 u1Len);
+#if PRINT_CALIBRATION_SUMMARY
+EXTERN void vPrintCalibrationResult(DRAMC_CTX_T *p);
+#endif
+EXTERN int dramc_complex_mem_test (unsigned int start, unsigned int len);
+EXTERN U16 DDRPhyGetRealFreq(DRAMC_CTX_T *p);
+#ifdef DDR_INIT_TIME_PROFILING
+void TimeProfileGetTick(PROFILING_TIME_T *ptime);
+U32 TimeProfileDiffUS(PROFILING_TIME_T *base);
+void TimeProfileBegin(void);
+UINT32 TimeProfileEnd(void);
+#endif
+
+
+
+/*
+ ****************************************************************************************
+ ** Hal_IO.cpp
+ ****************************************************************************************
+ */
+#ifdef DUMP_INIT_RG_LOG_TO_DE
+EXTERN U8  gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag;
+#endif
+
+
+
+/*
+ ****************************************************************************************
+ ** dramc_utility.cpp
+ ****************************************************************************************
+ */
+#if (QT_GUI_Tool == 1)
+EXTERN MCK_TO_UI_SHIFT_T u1Lp5MCK2WCKUI_DivShift(DRAMC_CTX_T *p);
+#endif
+
+
+/*
+ ****************************************************************************************
+ ** dramc_debug.cpp
+ ****************************************************************************************
+ */
+extern void HQA_Log_Message_for_Report(DRAMC_CTX_T *p, U8 u1ChannelIdx, U8 u1RankIdx, U32 who_am_I, U8 *main_str, U8 *main_str2, U8 byte_bit_idx, S32 value1, U8 *ans_str);
+extern void HQA_LOG_Print_Prefix_String(DRAMC_CTX_T *p);
+extern void print_HQA_message_before_CalibrationAllChannel(DRAMC_CTX_T *p);
+
+
+/*
+ ****************************************************************************************
+ ** dramc_utility_QT.cpp
+ ****************************************************************************************
+ */
+#if (QT_GUI_Tool == 1)
+EXTERN void QT_DRAMCTX_INIT(DRAMC_CTX_T *p);
+EXTERN DRAM_STATUS_T DramcDDRPHYInit_FPGA_A60868(DRAMC_CTX_T *p);
+EXTERN DRAM_STATUS_T DramcDDRPHYInit_LP5_FPGA_A60868(DRAMC_CTX_T *p);
+EXTERN void TA2_Stress_Test(DRAMC_CTX_T *p);
+EXTERN void TA2_Stress_Test_2(DRAMC_CTX_T *p);
+EXTERN U32 QT_TestEngineCompare(DRAMC_CTX_T *p);
+EXTERN void Write_Byte_Counter_Begin(DRAMC_CTX_T *p);
+EXTERN U32 Write_Byte_Counter_End(DRAMC_CTX_T *p);
+EXTERN void DDRPhyFMeter_Init(DRAMC_CTX_T *p);
+EXTERN U32 DDRPhyFreqMeter(DRAMC_CTX_T * p);
+#endif
+
+
+/*
+ ****************************************************************************************
+ ** fake_engine.c
+ ****************************************************************************************
+ */
+
+
+/*
+ ****************************************************************************************
+ ** low_power_test.c
+ ****************************************************************************************
+ */
+EXTERN int global_which_test;
+EXTERN void EnableDramcPhyDCMShuffle(DRAMC_CTX_T *p, bool bEn);
+EXTERN void Enter_Precharge_All(DRAMC_CTX_T *p);
+EXTERN void EnableDramcPhyDCM(DRAMC_CTX_T *p, bool bEn);
+EXTERN DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p);
+EXTERN void Low_Power_Scenarios_Test(DRAMC_CTX_T *p);
+#if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION
+void DDR800semiPowerSavingOn(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff);
+#endif
+
+#define LOW_POWER_SCENARIO_PRECHARGE_ALL 3 //idle(all bank refresh)
+#define LOW_POWER_SCENARIO_S1 5
+#define LOW_POWER_SCENARIO_S0 6
+#define LOW_POWER_SCENARIO_PASR 7
+#define LOW_POWER_SCENARIO_ALL 8
+#define LOW_POWER_SCENARIO_FAKE_ENGINE_READ 9
+#define LOW_POWER_SCENARIO_FAKE_ENGINE_WRITE 10
+#define LOW_POWER_SCENARIO_ONLY_SELF_REFRESH 12
+#define LOW_POWER_SCENARIO_HW_AUTO_SAVE_S0 13
+#define LOW_POWER_SCENARIO_HW_AUTO_SAVE_S0_METHOD_2 14
+#define LOW_POWER_SCENARIO_PASR_1BANK 15
+#define LOW_POWER_SCENARIO_PASR_2BANK 16
+#define LOW_POWER_SCENARIO_PASR_4BANK 17
+#define LOW_POWER_SCENARIO_PASR_8BANK 18
+#define LOW_POWER_SCENARIO_FAKE_ENGINE_BW 19
+#define LOW_POWER_SCENARIO_FAKE_ENGINE_READ_WRITE 21
+#define AUTO_REFRESH_RESERVE_TEST 22
+/*
+ ****************************************************************************************
+ ** low_power_test.c
+ ****************************************************************************************
+ */
+EXTERN U8 u1StopMiniStress;
+EXTERN void Ett_Mini_Strss_Test(DRAMC_CTX_T *p);
+
+
+/*
+ ****************************************************************************************
+ ** LP4_dram_init.c
+ ****************************************************************************************
+ */
+EXTERN void CKE_FIX_ON(DRAMC_CTX_T *p, U8 EN, U8 rank);
+EXTERN void LP4_UpdateInitialSettings(DRAMC_CTX_T *p);
+EXTERN void LP4_DRAM_INIT(DRAMC_CTX_T *p);
+
+
+/*
+ ****************************************************************************************
+ ** LP5_dram_init.c
+ ****************************************************************************************
+ */
+EXTERN void LP5_UpdateInitialSettings(DRAMC_CTX_T *p);
+EXTERN void LP5_DRAM_INIT(DRAMC_CTX_T *p);
+
+
+/*
+ ****************************************************************************************
+ ** system_init.c
+ ****************************************************************************************
+ */
+#if (fcFOR_CHIP_ID == fcA60868)
+EXTERN void syspll_init(DRAMC_CTX_T *p);
+#endif
+
+
+/*
+ ****************************************************************************************
+ ** dramc_utility_QT.cpp
+ ****************************************************************************************
+ */
+#if (QT_GUI_Tool == 1)
+EXTERN U8 ucDramRegRead_1(U32 reg_addr, U32 *reg_data);
+EXTERN U8 ucDramRegWrite_1(U32 reg_addr, U32 reg_data);
+#endif
+
+
+/*
+ ****************************************************************************************
+ ** svsim_dummy.c
+ ****************************************************************************************
+ */
+#if (FOR_DV_SIMULATION_USED == 0)
+#define delay_us(x)
+#define delay_ns(x)
+#define mysetscope()
+#define broadcast_on()
+#define broadcast_off()
+#define timestamp_show()
+#define build_api_initial()
+#define conf_to_sram_sudo(...)
+#endif
+
+/*
+ ****************************************************************************************
+ ** RS232.cpp
+ ****************************************************************************************
+ */
+#if (QT_GUI_Tool == 1)
+EXTERN U8 ucDramSetReg_1(U32 address, U32 *data, U16 count);
+EXTERN U8 ucDramGetReg_1(U32 address, U32 *data, U16 count);
+#endif
+
+
+/*
+ ****************************************************************************************
+ ** ett_test.c
+ ****************************************************************************************
+ */
+#ifdef DDR_INIT_TIME_PROFILING
+extern U16 u2TimeProfileCnt;
+#endif
+extern int hqa_vmddr_voltage, hqa_vmddr_class;
+
+
+#endif //_INT_GLOBAL_H
diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_int_slt.h b/src/vendorcode/mediatek/mt8195/include/dramc_int_slt.h
new file mode 100644
index 000000000000..343193201637
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/dramc_int_slt.h
@@ -0,0 +1,104 @@
+#ifndef _INT_SLT_H
+#define _INT_SLT_H
+
+
+//======================== EMI LPBK TEST Definition =====================================
+
+#if defined(SLT)
+#define ENABLE_EMI_LPBK_TEST 1
+#else
+#define ENABLE_EMI_LPBK_TEST 0
+#endif
+
+#define EMI_LPBK_DRAM_USED  !ENABLE_EMI_LPBK_TEST   // 0: EMI LPBK test, 1: normal K, dram used
+
+#define EMI_LPBK_USE_THROUGH_IO 0           //test through IO
+#define EMI_INT_LPBK_WL_DQS_RINGCNT   0     //DQS Ring cnt: through io @ 800,1600,2400,3200, emi intlpbk wo rx/tx K window
+#define EMI_LPBK_ADDRESS_DEFECT 0           //test address defect, MUST use CPU WRITE mode
+
+#if ENABLE_EMI_LPBK_TEST
+#define EMI_USE_TA2     0   // 0:CPU write, 1:TA2,  DVsim/Dsim use TA2, but 1:4 mode must use cpu write(because TA2 not support 1:4 mode)
+#else
+#define EMI_USE_TA2     0
+#endif
+
+/****************************
+Summary:
+1W1R: address offset : 0, 4, 8, c (1:8 mode only), no support 1:4 mode
+8W1R: address offset 0x0 ~ 0xC (8W1R), 0x10 ~ 0x1C, (10W1R) (1:8 & 1:4 mode)
+****************************/
+#define EMI_LPBK_1W1R   0   //CPU mode 0:8W1R, 1:1W1R
+
+#define EMI_LPBK_S1     0
+
+#define FREQ_METER      1
+#define DQSG_COUNTER    1
+
+
+#define ADJUST_TXDLY_SCAN_RX_WIN   0
+
+#define EMI_LPBK_K_TX     0
+#define ENABLE_PRE_POSTAMBLE !EMI_USE_TA2  //0: no pre/post-amble for TA2, 1: need pre/post-amble for cpu write
+
+
+#define EMI_LPBK_DFS_32 0   //DFS 32<->32<->32
+#define EMI_LPBK_DFS_24 0   //DFS 24<->24<->24
+#define EMI_LPBK_DFS_16 0   //DFS 16<->16<->16
+#define EMI_LPBK_USE_LP3_PINMUX 0
+#define EMI_LPBK_8W1R   1
+#if EMI_LPBK_1W1R
+#undef EMI_LPBK_8W1R
+#define EMI_LPBK_8W1R   0
+#endif
+
+#if EMI_LPBK_USE_THROUGH_IO
+#define EMI_LPBK_USE_DDR_800 1
+#else
+#define EMI_LPBK_USE_DDR_800 0
+#endif
+//#define K_TX_DQS_DLY 0
+
+#define LP4_4266_freq_meter  533    //   //shu0 533
+#define LP4_3733_freq_meter  464    //   //shu0 464
+#define LP4_3200_freq_meter  386    //   //shu8 386  //shu9 386
+#define LP4_2400_freq_meter  299          //shu6 299  shu5 299
+#define LP4_1600_freq_meter  191    //199   //shu4 383  shu3 191
+#define LP4_1200_freq_meter  299          //shu2 299  shu1 299
+#define LP4_800_freq_meter   199          //shu7 199
+
+
+#if ENABLE_EMI_LPBK_TEST    //EMI_LPBK_DRAM_USED==0
+/*
+#define SLT
+#undef ENABLE_TMRRI_NEW_MODE
+#define ENABLE_TMRRI_NEW_MODE 0
+#undef ENABLE_DUTY_SCAN_V2
+#define ENABLE_DUTY_SCAN_V2   0
+#undef ENABLE_RODT_TRACKING
+#define ENABLE_RODT_TRACKING 0
+#undef TX_K_DQM_WITH_WDBI
+#define TX_K_DQM_WITH_WDBI  0
+#undef ENABLE_WRITE_DBI
+#define ENABLE_WRITE_DBI 0
+*/
+
+#if EMI_INT_LPBK_WL_DQS_RINGCNT
+#undef EMI_LPBK_USE_THROUGH_IO
+#define EMI_LPBK_USE_THROUGH_IO 1
+#undef EMI_LPBK_USE_DDR_800
+#define EMI_LPBK_USE_DDR_800 0
+#endif
+
+#endif
+//#if (EMI_LPBK_DRAM_USED)
+//#undef ENABLE_MIOCK_JMETER
+//#define ENABLE_MIOCK_JMETER   // for TX_PER_BIT_DELAY_CELL
+//#endif
+
+
+//=============================================================================
+
+
+
+
+#endif //_INT_GLOBAL_H
diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h b/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h
new file mode 100644
index 000000000000..a7d0a2abf75c
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h
@@ -0,0 +1,1727 @@
+#ifndef _PI_API_H
+#define _PI_API_H
+
+/***********************************************************************/
+/*              Includes                                               */
+/***********************************************************************/
+
+/***********************************************************************/
+/*              Constant Define                                        */
+/***********************************************************************/
+
+#include "dramc_typedefs.h"
+//#include <soc/addressmap.h>
+#include <soc/dramc_soc.h>
+#include <soc/dramc_param.h>
+
+#define SW_CHANGE_FOR_SIMULATION 0  //calibration funciton for whole chip simulation. Code changed due to different compiler
+#ifndef FOR_DV_SIMULATION_USED
+#define FOR_DV_SIMULATION_USED  (FALSE) ////calibration funciton for DV simulation. Code changed due to different compiler#define FT_DSIM_USED 0
+#endif
+#define DV_SIMULATION_LP4 1
+#define BYPASS_CALIBRATION 0
+#define __ETT__ 0
+#define FT_DSIM_USED 0
+#define __FLASH_TOOL_DA__ 0
+#define CFG_ENABLE_DCACHE 0
+#define CFG_DRAM_CALIB_OPTIMIZATION 1
+#define GATING_AUTO_K_ENABLE 0
+#define CFG_DRAM_SAVE_FOR_RUNTIME_SHMOO 0
+#define CFG_DRAM_LOG_TO_STORAGE 0
+#define CBT_OLDMODE_ENABLE 0
+#define CBT_AUTO_K_ENABLE 0
+#define LJPLL_FREQ_DEBUG_LOG 0
+#define DRAM_AUXADC_CONFIG 0
+//Bring Up Selection : Do Not open it when normal operation
+//#define SLT
+//#define SLT_2400_EXIT_PRELOADER
+//#define FIRST_BRING_UP
+//#define DUMP_INIT_RG_LOG_TO_DE  //dump init RG settings to DE
+
+#define ENABLE      (1)
+#define DISABLE     (0)
+#define ON          (1)
+#define OFF         (0)
+#define AUTOK_ON    (1)
+#define AUTOK_OFF   (0)
+#define DCM_ON      (1)
+#define DCM_OFF     (0)
+#define NORMAL_K    (1)
+#define EYESCAN_K   (0)
+
+
+//Read Chip QT Tool
+#ifndef QT_GUI_Tool
+#define QT_GUI_Tool     0    //Setting 1 when using QT GUI Tool Compiler.
+#define HAPS_FPFG_A60868    0  //Setting 1 when testing HAPS FPGA
+#endif
+
+//DRAMC Chip
+#define fcA60868        1
+#define fcPetrus        2
+#define fcIPM           3
+#define fcMargaux       4
+#define fcMouton        5
+#define fcColgin        6
+#define fcPalmer        7
+#define fc8195          8
+#define fcFOR_CHIP_ID   fc8195
+
+#define __A60868_TO_BE_PORTING__ 0
+#define __Petrus_TO_BE_PORTING__ 0
+
+#define VENDOR_SAMSUNG 1
+#define VENDOR_HYNIX 6
+#define REVISION_ID_MAGIC 0x9501
+
+
+#define __LP5_COMBO__   (FALSE)
+#define FEATURE_RDDQC_K_DMI   (FALSE)   // This feature is not supported at A60868 test chip
+
+#if FOR_DV_SIMULATION_USED
+#undef __ETT__
+#else
+//#define __ETT__ 1 /* If you want to disable ETT , please mark all line */
+#endif
+
+#if __ETT__
+#define __FLASH_TOOL_DA__ 0
+#endif
+
+#if (FEATURE_RDDQC_K_DMI == TRUE)
+    #define RDDQC_ADD_DMI_NUM   2
+#else
+    #define RDDQC_ADD_DMI_NUM   0
+#endif
+
+#if FOR_DV_SIMULATION_USED
+#define CHANNEL_NUM    2   // 1 single channel, 2 dual channel, 4 channel
+#else
+#define CHANNEL_NUM    4 // 1 single channel, 2 dual channel, 4 channel
+#endif
+#define DPM_CH_NUM     2 // CH0/1 is Master, CH2/3 is Slave
+
+//ZQ calibration
+#define ENABLE_LP4_ZQ_CAL  1
+#if ENABLE_LP4_ZQ_CAL //choose one mode to do ZQ calibration
+#define ZQ_SWCMD_MODE         1 //suggested SW CMD mode
+#define ZQ_RTSWCMD_MODE       0 //run time SW mode
+#define ZQ_SCSM_MODE          0 //old mode
+#endif
+
+#define CODE_SIZE_REDUCE 0
+#define CALIBRATION_SPEED_UP_DEBUG 0
+#define VENDER_JV_LOG 0
+
+//SW option
+#define DUAL_FREQ_K 1   //0 : only K 1 freq(1600), 1: K multi freq
+#define SCRAMBLE_EN 1
+#if 1 //[FOR_CHROMEOS]
+#define ENABLE_EYESCAN_GRAPH 0 //__ETT__ //draw eye diagram after calibration, if enable, need to fix code size problem.
+#else
+#define ENABLE_EYESCAN_GRAPH 1
+#endif
+#define EYESCAN_GRAPH_CATX_VREF_STEP 1  // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868
+#define EYESCAN_GRAPH_RX_VREF_STEP 2
+#define EYESCAN_RX_VREF_RANGE_END 128   //field is 6 bit, but can only use 0~63,7bit ->127
+#define EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF    10
+#if (fcFOR_CHIP_ID == fcA60868)
+#define ENABLE_EYESCAN_CBT 0      //TO DO:Forece to draw CBT eye diagram after calibration
+#define ENABLE_EYESCAN_RX 0       //TO DO:Forece to draw RX eye diagram after calibration
+#define ENABLE_EYESCAN_TX 0       //TO DO:Forece to draw TX eye diagram after calibration
+#define ENABLE_VREFSCAN 0           //TO DO:Forece to Vref Scan for calibration
+#endif
+
+#define CHECK_HQA_CRITERIA  0
+#define REDUCE_LOG_FOR_PRELOADER 1
+#define APPLY_LP4_POWER_INIT_SEQUENCE 1
+#define ENABLE_READ_DBI 0
+#define ENABLE_WRITE_DBI 1
+#define ENABLE_WRITE_DBI_Protect 0
+#define ENABLE_TX_WDQS 1
+#define ENABLE_WDQS_MODE_2 0
+#define ENABLE_DRS 0
+#define ENABLE_TX_TRACKING 1
+#define ENABLE_K_WITH_WORST_SI_UI_SHIFT 1
+#define ETT_MINI_STRESS_USE_TA2_LOOP_MODE 1
+#define DUMP_TA2_WINDOW_SIZE_RX_TX 0
+#if ENABLE_TX_TRACKING
+    #define ENABLE_SW_TX_TRACKING 0 //if SW_TX_TRACKING is 0, using HW_TX_TRACKING
+    //can only choose 1 to set as 1 in the following 3 define
+    #define DQSOSC_SWCMD 1
+    #define DQSOSC_RTSWCMD 0
+    #define DQSOSC_SCSM 0
+#endif
+#define ENABLE_PA_IMPRO_FOR_TX_TRACKING 1
+#define ENABLE_WRITE_POST_AMBLE_1_POINT_5_TCK 1
+#define ENABLE_RX_TRACKING 0
+#if ENABLE_RX_TRACKING
+    #define RX_DVS_NOT_SHU_WA 1
+#endif
+#define ENABLE_OPEN_LOOP_MODE_OPTION 1
+#define ENABLE_TMRRI_NEW_MODE 1
+#define ENABLE_8PHASE_CALIBRATION 1
+#define ENABLE_DUTY_SCAN_V2 1
+#define DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ 0 //0: K all Freq 1: K highest Freq
+#define APPLY_DQDQM_DUTY_CALIBRATION 1
+#define IMPEDANCE_TRACKING_ENABLE //Impendence tracking
+#ifdef IMPEDANCE_TRACKING_ENABLE
+#define IMPEDANCE_HW_CALIBRATION 0
+#else
+#define IMPEDANCE_HW_CALIBRATION 0
+#endif
+#define IMPEDANCE_HW_SAVING   //mask because function fail, it lets clk swing change larger before DVFS occurs
+#define IMP_DEBUG_ENABLE
+#define ENABLE_MIOCK_JMETER
+#define MIOCK_JMETER_CNT_WA 1
+#define ENABLE_RUNTIME_MRW_FOR_LP5	1
+#define ENABLE_RODT_TRACKING 1
+#define GATING_ADJUST_TXDLY_FOR_TRACKING 1
+#define TDQSCK_PRECALCULATION_FOR_DVFS 1
+#define HW_GATING
+#define ENABLE_RX_FIFO_MISMATCH_DEBUG 1
+#define VERIFY_CKE_PWR_DOWN_FLOW 0 //Lewis add for DVT
+#define CBT_MOVE_CA_INSTEAD_OF_CLK 1	// need to check on LP5
+#define MRW_CHECK_ONLY 0
+#define MRW_BACKUP 0
+#define ENABLE_SAMSUNG_NT_ODT 0
+#if CODE_SIZE_REDUCE
+#define DRAMC_MODEREG_CHECK 0
+#else
+#define DRAMC_MODEREG_CHECK 1
+#endif
+#define DVT_READ_LATENCY_MONITOR 0
+#define DUMP_ALLSUH_RG 0
+#define PIN_CHECK_TOOL 0
+#define ENABLE_DATLAT_BY_FORMULA 1
+#define ENABLE_RX_AUTOK_MISS_FIRSTPASS_WA 1 //TOBE remove at IPMv2.2
+
+//Debug option
+#define GATING_ONLY_FOR_DEBUG 0
+#define ENABLE_RX_AUTOK_DEBUG_MODE 0
+#define RX_DLY_TRACK_ONLY_FOR_DEBUG 0 // LP4 only, LP3 not support
+#if CODE_SIZE_REDUCE || FOR_DV_SIMULATION_USED
+#define CPU_RW_TEST_AFTER_K 0  // need to enable GATING_ONLY_FOR_DEBUG at the same time for gating debug log
+#define TA2_RW_TEST_AFTER_K 0
+#else
+#define CPU_RW_TEST_AFTER_K 1  // need to enable GATING_ONLY_FOR_DEBUG at the same time for gating debug log
+#define TA2_RW_TEST_AFTER_K 1
+#endif
+//PINMUX auto test per bit related
+#define PINMUX_AUTO_TEST_PER_BIT_CA 0
+#define PINMUX_AUTO_TEST_PER_BIT_RX 0
+#define PINMUX_AUTO_TEST_PER_BIT_TX 0
+
+#define CA_PER_BIT_DELAY_CELL 1//LP4
+#if PINMUX_AUTO_TEST_PER_BIT_CA
+#undef CA_PER_BIT_DELAY_CELL
+#define CA_PER_BIT_DELAY_CELL 0
+#endif
+
+//Gating calibration
+#define GATING_LEADLAG_LOW_LEVEL_CHECK 0
+
+#if CODE_SIZE_REDUCE
+#define GATING_AUTO_K_SUPPORT    0
+#else
+#define GATING_AUTO_K_SUPPORT    1
+#endif
+#if GATING_AUTO_K_ENABLE
+#define ENABLE_GATING_AUTOK_WA  1
+#else
+#define ENABLE_GATING_AUTOK_WA  0
+#endif
+
+#define DVT_TEST_RX_FIFO_MISMATCH_IRQ_CLEAN 0
+
+#define DPM_CONTROL_AFTERK
+#if __ETT__
+#define ENABLE_DBG_2_0_IRQ
+#endif
+
+#define ETT_LOAD_DPM  1
+
+//////////////////////////////////// FIXME start /////////////////////////
+#define CMD_CKE_WORKAROUND_FIX 0
+#define DQS_DUTY_SLT_CONDITION_TEST 0
+#define DV_SIMULATION_BEFORE_K 0
+#define DV_SIMULATION_DATLAT 0
+#define DV_SIMULATION_DBI_ON 0
+#define DV_SIMULATION_DFS 0
+#define DV_SIMULATION_GATING 0
+#define ENABLE_APB_MASK_WRITE 0
+#define ENABLE_DVFS_BYPASS_MR13_FSP 0
+#define ENABLE_RODT_TRACKING_SAVE_MCK 0
+#define ETT_NO_DRAM 0
+#define EYESCAN_LOG 0
+#define FSP1_CLKCA_TERM 1
+#define CBT_FSP1_MATCH_FSP0_UNTERM_WA 1
+#define MR_CBT_SWITCH_FREQ !FOR_DV_SIMULATION_USED //@Darren, Wait DFS ready
+#define FT_DSIM_USED 0
+#define GATING_ONLY_FOR_DEBUG 0
+#define MEASURE_DRAM_POWER_INDEX 0
+#define REG_ACCESS_PORTING_DGB 0
+#define RX_PIPE_BYPASS_ENABLE 0
+#define SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER 0
+#define SUPPORT_PICG_MONITOR 0
+#define SUPPORT_REQ_QUEUE_BLOCK_ALE 0
+#define SUPPORT_REQ_QUEUE_READ_LATERNCY_MONITOR 0
+#define REFRESH_OVERHEAD_REDUCTION 1
+#define XRTRTR_NEW_CROSS_RK_MODE 1
+#define XRTWTW_NEW_CROSS_RK_MODE 1
+#define APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST 0
+#define SUPPORT_HYNIX_RX_DQS_WEAK_PULL 0
+#define RX_DLY_TRACK_ONLY_FOR_DEBUG 0
+//Run time config
+#define TEMP_SENSOR_ENABLE // Enable rumtime HMR4
+#define ENABLE_REFRESH_RATE_DEBOUNCE 1
+#define ENABLE_PER_BANK_REFRESH 1
+#define PER_BANK_REFRESH_USE_MODE 1 // 0: original mode, 1: hybrid mode, 2: always pb mode
+#define IMP_TRACKING_PB_TO_AB_REFRESH_WA 1
+#define DRAMC_MODIFIED_REFRESH_MODE 1
+#define DRAMC_CKE_DEBOUNCE 1
+#define XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
+
+#define SAMSUNG_LP4_NWR_WORKAROUND 1
+#define AC_TIMING_DERATE_ENABLE 1
+#define ENABLE_EARLY_BG_CMD 0   // 0: Disable 1: Enable, Reduce the CMD latency by CTO_EBG request
+
+//////////////////////////////////// DVFS //////////////////////////////
+#define ENABLE_DVS 1 //DVS need tracking enable
+#define DRAMC_DFS_MODE 1 // 0:Legacy, 1:DPM RG, 2: PHY RG
+#define ENABLE_RTMRW_DEBUG_LOG 0
+#define ENABLE_TX_REBASE_ODT_WA 0 // for Pexxxs/xxx868
+#define ENABLE_DDR800_SOPEN_DSC_WA 1 //Paxxer
+#if ENABLE_TX_WDQS
+#define ENABLE_TX_REBASE_WDQS_DQS_PI_WA 0
+#endif
+#define ENABLE_DFS_DEBUG_MODE 0
+#define DFS_NOQUEUE_FLUSH_ENABLE 1
+#define DFS_NOQUEUE_FLUSH_LATENCY_CNT 0
+#define ENABLE_DFS_NOQUEUE_FLUSH_DBG 0
+#define ENABLE_CONFIG_MCK_4TO1_MUX 0
+#define ENABLE_TPBR2PBR_REFRESH_TIMING 1
+#define ENABLE_DFS_TIMING_ENLARGE 0
+#define ENABLE_DFS_208M_CLOCK 0
+#define ENABLE_DFS_HW_SAVE_MASK 0
+#define REPLACE_DFS_RG_MODE 1 //Trial run Remove DFS PHY RG mode
+#define ENABLE_LP4Y_DFS 0
+#if ENABLE_LP4Y_DFS
+#define LP4Y_BACKUP_SOLUTION 0 // 0:  Set SE after calibration, 1: Set SE before calibration
+#define ENABLE_LP4Y_WA 1 //no que flush actiming extend and CBT can't train in SE
+#define ENABLE_DFS_RUNTIME_MRW 1
+#else
+#define LP4Y_BACKUP_SOLUTION 0
+#define ENABLE_LP4Y_WA 0
+#define ENABLE_DFS_RUNTIME_MRW 0 // for LP4x
+#endif
+#define ENABLE_TIMING_TXSR_DFS_WA REFRESH_OVERHEAD_REDUCTION // Wait overhead refresh enable, @Darren, Entry SREF -> EXIT SREF -> PDE Command violates tXSR time
+#define ENABLE_RANK_NUMBER_AUTO_DETECTION 1
+
+#define DDR_HW_AUTOK_POLLING_CNT 100000
+
+//////////////////////////////////// FIXME end/////////////////////////
+
+#if (fcFOR_CHIP_ID == fcA60868)
+#define WORKAROUND_LP5_HEFF 1 //High efficiency mode
+#undef ENABLE_RUNTIME_MRW_FOR_LP5
+#define ENABLE_RUNTIME_MRW_FOR_LP5 0  // DV fail in 868, use RTSWCMD_MRW
+#endif
+
+#if ENABLE_RODT_TRACKING
+#define GATING_RODT_LATANCY_EN      0
+#else
+#define GATING_RODT_LATANCY_EN		1
+#endif
+
+#define CHECK_GOLDEN_SETTING (FALSE)
+#define APPLY_LOWPOWER_GOLDEN_SETTINGS 1 //0: DCM Off, 1: DCM On
+#define LP5_GOLDEN_SETTING_CHECKER (FALSE) //FALSE: enable LP4 checker
+//#define CMD_PICG_NEW_MODE 1
+//#define ENABLE_RX_DCM_DPHY 1 //Set 0 will lead DCM on/off error (Remove the flag, the setting will be 1)
+//#define CLK_FREE_FUN_FOR_DRAMC_PSEL
+//#define HW_SAVE_FOR_SR
+
+#if APPLY_LOWPOWER_GOLDEN_SETTINGS
+#define TX_PICG_NEW_MODE 1
+#define RX_PICG_NEW_MODE 1
+#else
+#define TX_PICG_NEW_MODE 0
+#define RX_PICG_NEW_MODE 0
+#endif
+
+#define DDR_RESERVE_NEW_MODE 1 //0: old mode 1: new mode
+//=============================================================================
+// for D Sim sumulation used
+//=============================================================================
+#if QT_GUI_Tool || !FOR_DV_SIMULATION_USED
+#define DV_SIMULATION_INIT_C        1
+#define SIMULATION_LP4_ZQ           1
+#define SIMULATION_SW_IMPED         1
+#define SIMULATION_MIOCK_JMETER     0
+#define SIMULATION_8PHASE           0
+#define SIMULATION_RX_INPUT_BUF     0
+#define SIMUILATION_CBT             1
+#define SIMULATION_WRITE_LEVELING   1
+#define SIMULATION_DUTY_CYC_MONITOR 0
+#define SIMULATION_GATING           1
+#define SIMULATION_DATLAT           1
+#define SIMULATION_RX_RDDQC         1
+#define SIMULATION_RX_PERBIT        1
+#define SIMULATION_TX_PERBIT        1  // Please enable with write leveling
+#define SIMULATION_RX_DVS           0
+#define SIMULATION_RUNTIME_CONFIG   0
+#else
+#define DV_SIMULATION_INIT_C        1
+#define SIMULATION_LP4_ZQ           1
+#define SIMULATION_SW_IMPED         1
+#define SIMULATION_MIOCK_JMETER     0
+#define SIMULATION_8PHASE           0
+#define SIMULATION_RX_INPUT_BUF     0
+#define SIMUILATION_CBT             1
+#define SIMULATION_WRITE_LEVELING   1
+#define SIMULATION_DUTY_CYC_MONITOR 0
+#define SIMULATION_GATING           1
+#define SIMULATION_DATLAT           1
+#define SIMULATION_RX_RDDQC         1
+#define SIMULATION_RX_PERBIT        1
+#define SIMULATION_TX_PERBIT        1  // Please enable with write leveling
+#define SIMULATION_RX_DVS           0
+#define SIMULATION_RUNTIME_CONFIG   1 // @Darren for DV sim
+#endif
+//Used to keep original VREF when doing Rx calibration for RX DVS
+#define DVS_CAL_KEEP_VREF 0xf
+
+//#define DDR_INIT_TIME_PROFILING
+#define DDR_INIT_TIME_PROFILING_TEST_CNT 1
+
+#if __FLASH_TOOL_DA__
+#undef PIN_CHECK_TOOL
+#define PIN_CHECK_TOOL 0
+#endif
+//=============================================================================
+// common
+#define DQS_BYTE_NUMBER             2
+#define DQS_BIT_NUMBER              8
+#define DQ_DATA_WIDTH               16   // define max support bus width in the system (to allocate array size)
+#define DQM_BYTE_NUM                2
+#define TIME_OUT_CNT                100  //100us
+#define HW_REG_SHUFFLE_MAX          4
+
+typedef enum
+{
+    BYTE_0 = 0,
+    BYTE_1 = 1,
+    ALL_BYTES
+} BYTES_T;
+
+//Should be removed after A60868
+#define LP5_DDR4266_RDBI_WORKAROUND 0
+#define CBT_O1_PINMUX_WORKAROUND  0
+#define WLEV_O1_PINMUX_WORKAROUND 0
+#define WCK_LEVELING_FM_WORKAROUND  0
+
+//RX input buffer offset calibration
+#define ENABLE_RX_INPUT_BUFF_OFF_K 1
+
+/* Gating window */
+#define DQS_GW_COARSE_STEP      1
+#define DQS_GW_FINE_START       0
+#define DQS_GW_FINE_END         32
+#define DQS_GW_FINE_STEP        4
+
+#define DQS_GW_UI_PER_MCK	16
+#define DQS_GW_PI_PER_UI	32
+
+// DATLAT
+#define DATLAT_TAP_NUMBER 32
+
+// RX DQ/DQS
+#define MAX_RX_DQSDLY_TAPS          511    // 0x018, May set back to 64 if no need.
+#define MAX_RX_DQDLY_TAPS           252
+#define RX_VREF_NOT_SPECIFY         0xff
+#define RX_VREF_DUAL_RANK_K_FREQ    1866    // if freq >=RX_VREF_DUAL_RANK_K_FREQ, Rank1 rx vref K will be enable.
+#define RX_VREF_RANGE_BEGIN         0
+#define RX_VREF_RANGE_BEGIN_ODT_OFF 32
+#define RX_VREF_RANGE_BEGIN_ODT_ON  24
+#define RX_VREF_RANGE_END           128      //field is 6 bit, but can only use 0~63
+#define RX_VREF_RANGE_STEP          1
+#define RX_PASS_WIN_CRITERIA        30
+#define RDDQC_PINMUX_WORKAROUND     1
+
+// TX DQ/DQS
+#if CODE_SIZE_REDUCE
+#define TX_AUTO_K_SUPPORT 0
+#else
+#define TX_AUTO_K_SUPPORT 1
+#endif
+#if TX_AUTO_K_SUPPORT
+#define TX_AUTO_K_DEBUG_ENABLE 0
+#define TX_AUTO_K_WORKAROUND 1
+#define ENABLE_PA_IMPRO_FOR_TX_AUTOK 1
+#endif
+#define MAX_TX_DQDLY_TAPS           31   // max DQ TAP number
+#define MAX_TX_DQSDLY_TAPS          31   // max DQS TAP number
+#define TX_OE_EXTEND 0
+#define TX_DQ_OE_SHIFT_LP5 5
+#if TX_OE_EXTEND
+#define TX_DQ_OE_SHIFT_LP4 4
+#else
+#define TX_DQ_OE_SHIFT_LP4 3
+#endif
+#define TX_DQ_OE_SHIFT_LP3 2
+#define TX_K_DQM_WITH_WDBI  1
+#define TX_OE_CALIBATION (!TX_OE_EXTEND)
+
+#define TX_RETRY_ENABLE 0
+#if TX_RETRY_ENABLE
+#define TX_RETRY_CONTROL_BY_SPM 1
+#define SW_TX_RETRY_ENABLE 0
+#else
+#define TX_RETRY_CONTROL_BY_SPM 0
+#endif
+
+// Sw work around options.
+#define CA_TRAIN_RESULT_DO_NOT_MOVE_CLK                 1 // work around for clock multi phase problem(cannot move clk or the clk will be bad)
+#define DramcHWDQSGatingTracking_JADE_TRACKING_MODE 1
+#define DramcHWDQSGatingTracking_FIFO_MODE          1
+#define DONT_MOVE_CLK_DELAY // don't move clk delay
+/* If defined for gFreqTbl and fastK
+ */
+#define LP4_SHU0_FREQ      (1866)
+#define LP4_SHU8_FREQ      (1600)
+#define LP4_SHU9_FREQ      (1600)
+#define LP4_SHU6_FREQ      (1200)
+#define LP4_SHU5_FREQ      (1200)
+#define LP4_SHU4_FREQ      (800)
+#define LP4_SHU3_FREQ      (800)
+#define LP4_SHU2_FREQ      (600)
+#define LP4_SHU1_FREQ      (600)
+#define LP4_SHU7_FREQ      (400)
+#define LP4_HIGHEST_FREQ LP4_SHU0_FREQ
+
+#define LP4_SHU0_FREQSEL   (LP4_DDR3733)
+#define LP4_SHU8_FREQSEL   (LP4_DDR3200)
+#define LP4_SHU9_FREQSEL   (LP4_DDR3200)
+#define LP4_SHU6_FREQSEL   (LP4_DDR2400)
+#define LP4_SHU5_FREQSEL   (LP4_DDR2400)
+#define LP4_SHU4_FREQSEL   (LP4_DDR1600)
+#define LP4_SHU3_FREQSEL   (LP4_DDR1600)
+#define LP4_SHU2_FREQSEL   (LP4_DDR1200)
+#define LP4_SHU1_FREQSEL   (LP4_DDR1200)
+#define LP4_SHU7_FREQSEL   (LP4_DDR800)
+
+#if FOR_DV_SIMULATION_USED
+#define DEFAULT_TEST2_1_CAL 0x55000000   // pattern0 and base address for test engine when we do calibration
+#define DEFAULT_TEST2_2_CAL 0xaa000020   // pattern1 and offset address for test engine when we do calibraion
+#else
+#define DEFAULT_TEST2_1_CAL 0x55000000   // pattern0 and base address for test engine when we do calibration
+#define DEFAULT_TEST2_2_CAL 0xaa000100   // pattern1 and offset address for test engine when we do calibraion
+#endif
+
+//CBT/CA training
+#if CODE_SIZE_REDUCE
+#define CBT_AUTO_K_SUPPORT 0
+#define CBT_OLDMODE_SUPPORT 0
+#else
+#define CBT_AUTO_K_SUPPORT 1
+#define CBT_OLDMODE_SUPPORT 1
+#endif
+#define CATRAINING_NUM_LP4      6
+#define CATRAINING_NUM_LP5      7
+#define CATRAINING_NUM    CATRAINING_NUM_LP5
+#define LP4_MRFSP_TERM_FREQ 1333
+#define LP5_MRFSP_TERM_FREQ 1866
+
+//Calibration Summary
+#define PRINT_CALIBRATION_SUMMARY (!SW_CHANGE_FOR_SIMULATION)
+#define PRINT_CALIBRATION_SUMMARY_DETAIL 1
+#define PRINT_CALIBRATION_SUMMARY_FASTK_CHECK 0
+
+#if 1 //(FOR_DV_SIMULATION_USED==0)
+#define ETT_PRINT_FORMAT  // Apply for both preloader and ETT
+#endif
+
+#if !CODE_SIZE_REDUCE
+//#define FOR_HQA_TEST_USED
+//#define FOR_HQA_REPORT_USED
+#endif
+//#define DEVIATION  // for special test used
+
+//Run Time Config
+//#define DUMMY_READ_FOR_TRACKING
+#define ZQCS_ENABLE_LP4
+#if ENABLE_LP4Y_DFS // @Darren, RT-mrw to HW-zqcal tMRD Violation Report - SW workaround from Robert
+#undef ZQCS_ENABLE_LP4
+#endif
+#ifndef ZQCS_ENABLE_LP4
+#define ENABLE_SW_RUN_TIME_ZQ_WA
+#endif
+
+//============================ For Future DVT Definition =================================
+
+#define ENABLE_BLOCK_APHY_CLOCK_DFS_OPTION 1
+#define ENABLE_REMOVE_MCK8X_UNCERT_LOWPOWER_OPTION 1
+#define ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION 1
+#define RDSEL_TRACKING_EN 1 // @Darren, for SHU0 only (DDR3733 or DDR4266)
+#define RDSEL_TRACKING_TH 2133
+#define ENABLE_DFS_SSC_WA 0
+#define ENABLE_DDR800_OPEN_LOOP_MODE_OPTION 1
+#define ENABLE_DDR400_OPEN_LOOP_MODE_OPTION 0
+#if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
+    #define OPEN_LOOP_MODE_CLK_TOGGLE_WA 1
+#else
+    #define OPEN_LOOP_MODE_CLK_TOGGLE_WA 0
+#endif
+
+//=============================================================================
+//#define DDR_BASE 0x40000000ULL //for DV sim and ett_test.c
+/***********************************************************************/
+/*              Defines                                                */
+/***********************************************************************/
+#define CBT_LOW_FREQ   0
+#define CBT_HIGH_FREQ   1
+#define CBT_UNKNOWN_FREQ   0xFF
+
+
+#if !__ETT__
+// Preloader: using config CFG_DRAM_CALIB_OPTIMIZATION to identify
+#if (FOR_DV_SIMULATION_USED==0) && !defined(SLT)
+// Preloader: using config CFG_DRAM_CALIB_OPTIMIZATION to identify
+#define SUPPORT_SAVE_TIME_FOR_CALIBRATION		CFG_DRAM_CALIB_OPTIMIZATION
+#else
+// DV simulation, use full calibration flow
+#define SUPPORT_SAVE_TIME_FOR_CALIBRATION		0
+#endif
+#define EMMC_READY CFG_DRAM_CALIB_OPTIMIZATION
+#define BYPASS_VREF_CAL		(SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY)
+#define BYPASS_CBT		(SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY)
+#define BYPASS_DATLAT		(SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY)
+#define BYPASS_WRITELEVELING	(SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY)
+#define BYPASS_RDDQC		(SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY)
+#define BYPASS_RXWINDOW		(SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY)
+#define BYPASS_TXWINDOW		(SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY)
+#define BYPASS_TXOE         (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY)
+#define BYPASS_GatingCal	(SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY)
+#define BYPASS_CA_PER_BIT_DELAY_CELL (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY)
+//#define BYPASS_TX_PER_BIT_DELAY_CELL (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY)
+#else
+// ETT
+#define SUPPORT_SAVE_TIME_FOR_CALIBRATION 0
+#define EMMC_READY 0
+#define BYPASS_VREF_CAL 1
+#define BYPASS_CBT 1
+#define BYPASS_DATLAT 1
+#define BYPASS_WRITELEVELING 1
+#define BYPASS_RDDQC 1
+#define BYPASS_RXWINDOW 1
+#define BYPASS_TXWINDOW 1
+#define BYPASS_TXOE 1
+#define BYPASS_GatingCal 1
+#define BYPASS_CA_PER_BIT_DELAY_CELL CA_PER_BIT_DELAY_CELL
+//#define BYPASS_TX_PER_BIT_DELAY_CELL 0
+#endif
+
+#define ENABLE_PINMUX_FOR_RANK_SWAP    0
+
+//======================== FIRST_BRING_UP Init Definition =====================
+#ifdef FIRST_BRING_UP
+
+//#define USE_CLK26M
+
+#undef DUAL_FREQ_K
+#define DUAL_FREQ_K 0   //0 : only K 1 freq(1600), 1: K multi freq
+
+#undef TDQSCK_PRECALCULATION_FOR_DVFS
+#define TDQSCK_PRECALCULATION_FOR_DVFS  0//DQS pre-calculation
+
+//#undef CHANNEL_NUM
+//#define CHANNEL_NUM 4
+
+#undef REPLACE_DFS_RG_MODE
+#define REPLACE_DFS_RG_MODE 1  //Trial run Remove DFS PHY RG mode
+
+#undef ENABLE_DUTY_SCAN_V2
+#define ENABLE_DUTY_SCAN_V2 0
+
+#undef ENABLE_DRS
+#define ENABLE_DRS 0
+
+#undef ENABLE_CA_TRAINING
+#define ENABLE_CA_TRAINING  1
+#undef ENABLE_WRITE_LEVELING
+#define ENABLE_WRITE_LEVELING 1
+
+//#undef REDUCE_LOG_FOR_PRELOADER
+//#define REDUCE_LOG_FOR_PRELOADER 0
+
+#undef ENABLE_RX_INPUT_BUFF_OFF_K
+#define ENABLE_RX_INPUT_BUFF_OFF_K 0
+
+#undef REDUCE_CALIBRATION_OLYMPUS_ONLY
+#define REDUCE_CALIBRATION_OLYMPUS_ONLY 0
+
+#undef APPLY_LOWPOWER_GOLDEN_SETTINGS
+#define APPLY_LOWPOWER_GOLDEN_SETTINGS 0 //Should open APPLY_LOWPOWER_GOLDEN_SETTINGS before SB + 3
+
+//#undef SPM_CONTROL_AFTERK //Should open SPM_CONTROL_AFTERK before SB + 3
+
+#undef TX_K_DQM_WITH_WDBI
+#define TX_K_DQM_WITH_WDBI 0
+
+#undef ENABLE_EYESCAN_GRAPH
+#define ENABLE_EYESCAN_GRAPH 0
+
+#undef ENABLE_TX_TRACKING
+#undef ENABLE_SW_TX_TRACKING
+#define ENABLE_TX_TRACKING  0
+#define ENABLE_SW_TX_TRACKING 0
+
+#undef ENABLE_RX_TRACKING
+#define ENABLE_RX_TRACKING  0
+
+#undef RDSEL_TRACKING_EN
+#define RDSEL_TRACKING_EN 0
+
+#undef GATING_ADJUST_TXDLY_FOR_TRACKING
+#define GATING_ADJUST_TXDLY_FOR_TRACKING 0
+
+#undef ENABLE_PER_BANK_REFRESH
+#define ENABLE_PER_BANK_REFRESH 1  //align bringup setting, Derping
+
+#undef ENABLE_TPBR2PBR_REFRESH_TIMING
+#define ENABLE_TPBR2PBR_REFRESH_TIMING 1  //align bringup setting, Robert
+
+#undef REFRESH_OVERHEAD_REDUCTION
+#define REFRESH_OVERHEAD_REDUCTION 1  //align bringup setting, Derping
+
+#undef AC_TIMING_DERATE_ENABLE
+#define AC_TIMING_DERATE_ENABLE 1
+
+#undef XRTWTW_NEW_CROSS_RK_MODE
+#define XRTWTW_NEW_CROSS_RK_MODE 1
+#undef XRTRTR_NEW_CROSS_RK_MODE
+#define XRTRTR_NEW_CROSS_RK_MODE 1
+
+#undef ENABLE_DVFS_BYPASS_MR13_FSP
+#define ENABLE_DVFS_BYPASS_MR13_FSP 0
+
+#undef HW_GATING
+#undef DUMMY_READ_FOR_TRACKING
+#undef ZQCS_ENABLE_LP4
+//#define ZQCS_ENABLE_LP4
+
+#undef TEMP_SENSOR_ENABLE
+#define TEMP_SENSOR_ENABLE
+#undef IMPEDANCE_TRACKING_ENABLE
+//#define IMPEDANCE_TRACKING_ENABLE
+#undef IMPEDANCE_HW_CALIBRATION
+#define IMPEDANCE_HW_CALIBRATION 0
+#undef ENABLE_SW_RUN_TIME_ZQ_WA
+
+//#undef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
+
+#undef APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
+#define APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST 0
+
+#undef DFS_NOQUEUE_FLUSH_ENABLE
+#define DFS_NOQUEUE_FLUSH_ENABLE 0
+
+
+#undef TX_PICG_NEW_MODE
+#undef RX_PICG_NEW_MODE
+#if APPLY_LOWPOWER_GOLDEN_SETTINGS
+#define TX_PICG_NEW_MODE 1
+#define RX_PICG_NEW_MODE 1
+#else
+#define TX_PICG_NEW_MODE 0
+#define RX_PICG_NEW_MODE 0
+#endif
+
+
+#if 0
+#undef XRTW2W_PERFORM_ENHANCE_TX
+#undef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
+#ifdef XRTR2W_PERFORM_ENHANCE_RODTEN
+#undef XRTR2W_PERFORM_ENHANCE_RODTEN     //conflict with ENABLE_RODT_TRACKING, LP4 support only
+#endif
+#endif
+#endif //FIRST_BRING_UP
+
+//======================== RSHMOO Definition =====================================
+#define RUNTIME_SHMOO_RELEATED_FUNCTION    CFG_DRAM_SAVE_FOR_RUNTIME_SHMOO
+#define RUNTIME_SHMOO_RG_BACKUP_NUM         (100)
+#define RUNTIME_SHMOO_TX    0    //TX RX can't be opened simultaneously
+#define RUNTIME_SHMOO_RX    0
+
+#if RUNTIME_SHMOO_RELEATED_FUNCTION    //if enable rshmoo, close TX OE calibration
+#undef TX_OE_EXTEND
+#define TX_OE_EXTEND 1
+#undef TX_DQ_OE_SHIFT_LP4
+#define TX_DQ_OE_SHIFT_LP4 4
+#undef TX_OE_CALIBATION
+#define TX_OE_CALIBATION (!TX_OE_EXTEND)
+#undef ENABLE_RX_TRACKING_LP4
+#define ENABLE_RX_TRACKING_LP4 0
+#undef ENABLE_TX_TRACKING
+#undef ENABLE_SW_TX_TRACKING
+#define ENABLE_TX_TRACKING  0
+#define ENABLE_SW_TX_TRACKING 0
+
+
+//#define SUPPORT_CLK_TERM
+
+#define RUNTIME_SHMOO_FAST_K 1
+
+#define RUNTIME_SHMOO_TEST_CHANNEL    0   // 0: CHA, 1: CHB
+#define RUNTIME_SHMOO_TEST_RANK       0   // 0: RK0, 1: RK1
+#define RUNTIME_SHMOO_TEST_BYTE       0   // 0: Byte0, 1: Byte1
+
+#define RUNTIME_SHMOO_TEST_PI_DELAY_START 0   // 0~63
+#define RUNTIME_SHMOO_TEST_PI_DELAY_END   63  // 0~63
+#define RUNTIME_SHMOO_TEST_PI_DELAY_STEP  1
+
+#define RUNTIME_SHMOO_RX_VREF_RANGE_END          127 //La_fite: 63
+#define RUNTIME_SHMOO_RX_TEST_MARGIN        2 //for RX Delay (start:first_pass-margin, end:last_pass +margin)
+
+#define RUNTIME_SHMOO_TEST_VREF_START     0   // 0~81  : 0~50 is range 0, 51~81 is range 1
+#define RUNTIME_SHMOO_TEST_VREF_END       81  // 0~81  : 0~50 is range 0, 51~81 is range 1
+#define RUNTIME_SHMOO_TEST_VREF_STEP      1
+#endif
+//=============================================================================
+
+
+typedef enum
+{
+    CLK_MUX_208M = 0,
+    CLK_MUX_104M,
+    CLK_MUX_52M,
+} CLK_MUX_T;
+
+typedef enum
+{
+    BEF_DFS_MODE = 0,
+    AFT_DFS_MODE,
+    CHG_CLK_MODE,
+} DFS_DBG_T;
+
+typedef enum
+{
+    SHUFFLE_HW_MODE = 0,
+    SPM_DEBUG_MODE,
+    RG_DEBUG_MODE,
+} DFS_IP_CLOCK_T;
+
+typedef enum
+{
+    DutyScan_Calibration_K_CLK= 0,
+    DutyScan_Calibration_K_DQS,
+    DutyScan_Calibration_K_DQ,
+    DutyScan_Calibration_K_DQM,
+    DutyScan_Calibration_K_WCK
+} DUTYSCAN_CALIBRATION_FLOW_K_T;
+
+typedef enum
+{
+    DQS_8PH_DEGREE_0 = 0,
+    DQS_8PH_DEGREE_180,
+    DQS_8PH_DEGREE_45,
+    DQS_8PH_DEGREE_MAX,
+} DQS_8_PHASE_T;
+
+typedef enum
+{
+    CYCLE_05T = 2,
+    CYCLE_1T,
+} DQSIEN_CYCLE_T;
+
+typedef enum
+{
+    DRVP = 0,
+    DRVN,
+    ODTP,
+    ODTN,
+    IMP_DRV_MAX
+} DRAM_IMP_DRV_T;
+
+typedef enum
+{
+    IMP_LOW_FREQ = 0,
+    IMP_HIGH_FREQ,
+    IMP_NT_ODTN, // Samsung support only for LP4X
+    IMP_VREF_MAX
+} DRAMC_IMP_T;
+
+typedef enum
+{
+    GET_MDL_USED = 0,
+    NORMAL_USED,
+    SLT_USED
+} DRAM_INIT_USED_T;
+
+typedef enum
+{
+    PATTERN_RDDQC,
+    PATTERN_TEST_ENGINE,
+} RX_PATTERN_OPTION_T;
+
+typedef enum
+{
+    DRAM_OK = 0, // OK
+    DRAM_FAIL,    // FAIL
+    DRAM_FAST_K,
+    DRAM_NO_K,
+} DRAM_STATUS_T; // DRAM status type
+
+typedef enum
+{
+    VREF_RANGE_0= 0,
+    VREF_RANGE_1,
+    VREF_RANGE_MAX
+}DRAM_VREF_RANGE_T;
+#define VREF_VOLTAGE_TABLE_NUM_LP4 51
+#define VREF_VOLTAGE_TABLE_NUM_LP5 128
+
+typedef enum
+{
+    CKE_FIXOFF = 0,
+    CKE_FIXON,
+    CKE_DYNAMIC //After CKE FIX on/off, CKE should be returned to dynamic (control by HW)
+} CKE_FIX_OPTION;
+
+typedef enum
+{
+    TO_ONE_CHANNEL = 0,
+    TO_ALL_CHANNEL,
+    TO_ALL_RANK
+} CHANNEL_RANK_SEL_T;
+
+typedef enum {
+    CMDOE_DIS_TO_ONE_CHANNEL = 0,
+    CMDOE_DIS_TO_ALL_CHANNEL,
+} CMDOE_DIS_CHANNEL;
+
+typedef enum
+{
+    LP5_DDR6400 = 0,
+    LP5_DDR6000,
+    LP5_DDR5500,
+    LP5_DDR4800,
+    LP5_DDR4266,
+    LP5_DDR3733,
+    LP5_DDR3200,
+    LP5_DDR2400,
+    LP5_DDR1600,
+    LP5_DDR1200,
+    LP5_DDR800,
+
+    LP4_DDR4266,
+    LP4_DDR3733,
+    LP4_DDR3200,
+    LP4_DDR2667,
+    LP4_DDR2400,
+    LP4_DDR2280,
+    LP4_DDR1866,
+    LP4_DDR1600,
+    LP4_DDR1200,
+    LP4_DDR800,
+    LP4_DDR400,
+
+    PLL_FREQ_SEL_MAX
+} DRAM_PLL_FREQ_SEL_T; // DRAM DFS type
+
+typedef enum
+{
+    MCK_TO_4UI_SHIFT = 2,
+    MCK_TO_8UI_SHIFT = 3,
+    MCK_TO_16UI_SHIFT = 4
+} MCK_TO_UI_SHIFT_T;
+
+typedef enum
+{
+    AUTOK_CA,
+    AUTOK_CS,
+    AUTOK_DQS
+} ATUOK_MODE_T;
+
+typedef enum
+{
+    AUTOK_RESPI_1 = 0,
+    AUTOK_RESPI_2 = 1,
+    AUTOK_RESPI_4 = 2,
+    AUTOK_RESPI_8 = 3
+} AUTOK_PI_RESOLUTION;
+
+typedef enum
+{
+    DRAM_DFS_REG_SHU0 = 0,
+    DRAM_DFS_REG_SHU1,
+    DRAM_DFS_REG_MAX
+} DRAM_DFS_REG_SHU_T;
+
+typedef enum
+{
+    SRAM_SHU0 = 0,
+    SRAM_SHU1,
+    SRAM_SHU2,
+    SRAM_SHU3,
+    SRAM_SHU4,
+    SRAM_SHU5,
+    SRAM_SHU6,
+#if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
+    SRAM_SHU7,
+#endif
+    DRAM_DFS_SRAM_MAX
+} DRAM_DFS_SRAM_SHU_T; // DRAM SRAM RG type
+
+typedef enum
+{
+    SHUFFLE_RG = 0,
+    NONSHUFFLE_RG,
+    BOTH_SHU_NONSHU_RG,
+} RG_SHU_TYPE_T; // RG SHUFFLE type
+
+typedef enum
+{
+    DIV16_MODE = 0,
+    DIV8_MODE,
+    DIV4_MODE,
+    UNKNOWN_MODE,
+} DIV_MODE_T;
+
+typedef enum
+{
+    DUTY_DEFAULT = 0,
+    DUTY_NEED_K,
+    DUTY_LAST_K
+} DUTY_CALIBRATION_T;
+
+
+typedef enum
+{
+    VREF_CALI_OFF = 0,
+    VREF_CALI_ON,
+} VREF_CALIBRATION_ENABLE_T;
+
+typedef enum
+{
+    DDR800_CLOSE_LOOP = 0,
+    OPEN_LOOP_MODE,
+    SEMI_OPEN_LOOP_MODE,
+    CLOSE_LOOP_MODE,
+} DDR800_MODE_T;
+
+typedef enum
+{
+    DRAM_CALIBRATION_SW_IMPEDANCE= 0,
+    DRAM_CALIBRATION_DUTY_SCAN,
+    DRAM_CALIBRATION_ZQ,
+    DRAM_CALIBRATION_JITTER_METER,
+    DRAM_CALIBRATION_CA_TRAIN ,
+    DRAM_CALIBRATION_WRITE_LEVEL,
+    DRAM_CALIBRATION_GATING,
+    DRAM_CALIBRATION_RX_INPUT_BUFF_OFFC,
+    DRAM_CALIBRATION_RX_RDDQC,
+    DRAM_CALIBRATION_TX_PERBIT,
+    DRAM_CALIBRATION_DATLAT,
+    DRAM_CALIBRATION_RX_PERBIT,
+    DRAM_CALIBRATION_TX_OE,
+    DRAM_CALIBRATION_MAX
+} DRAM_CALIBRATION_STATUS_T;
+
+typedef struct _DRAM_DFS_FREQUENCY_TABLE_T
+{
+    DRAM_PLL_FREQ_SEL_T freq_sel;
+    DIV_MODE_T divmode;
+    DRAM_DFS_SRAM_SHU_T SRAMIdx;
+    DUTY_CALIBRATION_T duty_calibration_mode;
+    VREF_CALIBRATION_ENABLE_T vref_calibartion_enable; // CBT/RX/TX vref calibration enable or not
+    DDR800_MODE_T ddr_loop_mode;
+} DRAM_DFS_FREQUENCY_TABLE_T;
+
+#if 0 //[FOR_CHROMEOS]define in src\soc\mediatek\mt8195\include\soc\dramc_soc.h
+typedef enum
+{
+    CHANNEL_A = 0,
+    CHANNEL_B,
+#if (CHANNEL_NUM > 2)
+    CHANNEL_C,
+    CHANNEL_D,
+#endif
+    CHANNEL_MAX
+} DRAM_CHANNEL_T;
+
+typedef enum
+{
+    RANK_0 = 0,
+    RANK_1,
+    RANK_MAX
+} DRAM_RANK_T;
+
+/*
+ * Internal CBT mode enum
+ * 1. Calibration flow uses vGet_Dram_CBT_Mode to
+ *    differentiate between mixed vs non-mixed LP4
+ * 2. Declared as dram_cbt_mode[RANK_MAX] internally to
+ *    store each rank's CBT mode type
+ */
+typedef enum
+{
+    CBT_NORMAL_MODE = 0,
+    CBT_BYTE_MODE1
+} DRAM_CBT_MODE_T, dram_cbt_mode;
+
+#endif
+typedef enum
+{
+    CHANNEL_SINGLE = 1,
+    CHANNEL_DUAL,
+#if (CHANNEL_NUM > 2)
+    CHANNEL_THIRD,
+    CHANNEL_FOURTH
+#endif
+} DRAM_CHANNEL_NUMBER_T;
+
+typedef enum
+{
+    RANK_SINGLE = 1,
+    RANK_DUAL
+} DRAM_RANK_NUMBER_T;
+
+
+typedef enum
+{
+    TYPE_DDR1 = 1,
+    TYPE_LPDDR2,
+    TYPE_LPDDR3,
+    TYPE_PCDDR3,
+    TYPE_LPDDR4,
+    TYPE_LPDDR4X,
+    TYPE_LPDDR4P,
+    TYPE_LPDDR5
+} DRAM_DRAM_TYPE_T;
+
+typedef enum
+{
+    PINMUX_EMCP = 0,
+    PINMUX_DSC,
+    PINMUX_MCP,
+    PINMUX_DSC_REV,
+    PINMUX_MAX
+} DRAM_PINMUX;
+
+/* For faster switching between term and un-term operation
+ * FSP_0: For un-terminated freq.
+ * FSP_1: For terminated freq.
+ */
+typedef enum
+{
+    FSP_0 = 0,
+    FSP_1,
+    FSP_2,
+    FSP_MAX
+} DRAM_FAST_SWITH_POINT_T;
+
+
+typedef struct
+{
+    u8 pat_v[8];
+    u8 pat_a[8];
+    u8 pat_dmv;
+    u8 pat_dma;
+    u8 pat_cs0;
+    u8 pat_cs1;
+    u8 ca_golden_sel;
+    u8 invert_num;
+    u8 pat_num;
+    u8 ca_num;
+} new_cbt_pat_cfg_t;
+
+typedef enum
+{
+	TRAINING_MODE1 = 0,
+	TRAINING_MODE2
+} lp5_training_mode_t;
+
+typedef enum
+{
+	CBT_PHASE_RISING = 0,
+	CBT_PHASE_FALLING
+} lp5_cbt_phase_t;
+
+/*
+ * External CBT mode enum
+ * Due to MDL structure compatibility (single field for dram CBT mode),
+ * the below enum is used in preloader to differentiate between dram cbt modes
+ */
+typedef enum
+{
+    CBT_R0_R1_NORMAL = 0,   // Normal mode
+    CBT_R0_R1_BYTE,         // Byte mode
+    CBT_R0_NORMAL_R1_BYTE,  // Mixed mode R0: Normal R1: Byte
+    CBT_R0_BYTE_R1_NORMAL   // Mixed mode R0: Byte R1: Normal
+} DRAM_CBT_MODE_EXTERN_T;
+
+typedef enum
+{
+    EYESCAN_TYPE_CBT = 0,
+    EYESCAN_TYPE_RX,
+    EYESCAN_TYPE_TX
+} DRAM_EYESCAN_TYPE_T;
+
+typedef enum
+{
+    ODT_OFF = 0,
+    ODT_ON
+} DRAM_ODT_MODE_T;
+
+typedef enum
+{
+    DBI_OFF = 0,
+    DBI_ON
+} DRAM_DBI_MODE_T;
+
+typedef enum
+{
+    DATA_WIDTH_16BIT = 16,
+    DATA_WIDTH_32BIT = 32
+} DRAM_DATA_WIDTH_T;
+
+typedef enum
+{
+    TE_OP_WRITE_READ_CHECK = 0,
+    TE_OP_READ_CHECK
+} DRAM_TE_OP_T;
+
+typedef enum
+{
+    TEST_ISI_PATTERN = 0, //don't change
+    TEST_AUDIO_PATTERN = 1, //don't change
+    TEST_XTALK_PATTERN = 2, //don't change
+    TEST_WORST_SI_PATTERN,
+    TEST_TA1_SIMPLE,
+    TEST_TESTPAT4,
+    TEST_TESTPAT4_3,
+    TEST_MIX_PATTERN,
+    TEST_DMA,
+    TEST_SSOXTALK_PATTERN,
+} DRAM_TEST_PATTERN_T;
+
+typedef enum
+{
+    TE_NO_UI_SHIFT = 0,
+    TE_UI_SHIFT
+} DRAM_TE_UI_SHIFT_T;
+
+typedef enum
+{
+    TX_DQ_DQS_MOVE_DQ_ONLY = 0,
+    TX_DQ_DQS_MOVE_DQM_ONLY,
+    TX_DQ_DQS_MOVE_DQ_DQM
+} DRAM_TX_PER_BIT_CALIBRATION_TYTE_T;
+
+typedef enum
+{
+    TX_DQM_WINDOW_SPEC_IN = 0xfe,
+    TX_DQM_WINDOW_SPEC_OUT = 0xff
+} DRAM_TX_PER_BIT_DQM_WINDOW_RESULT_TYPE_T;
+
+// enum for CKE toggle mode (toggle both ranks 1. at the same time (CKE_RANK_DEPENDENT) 2. individually (CKE_RANK_INDEPENDENT))
+typedef enum
+{
+    CKE_RANK_INDEPENDENT = 0,
+    CKE_RANK_DEPENDENT
+} CKE_CTRL_MODE_T;
+
+typedef enum
+{
+    TA2_RKSEL_XRT = 3,
+    TA2_RKSEL_HW = 4,
+} TA2_RKSEL_TYPE_T;
+
+typedef enum
+{
+    TA2_PAT_SWITCH_OFF = 0,
+    TA2_PAT_SWITCH_ON,
+} TA2_PAT_SWITCH_TYPE_T;
+
+typedef enum
+{
+    PHYPLL_MODE = 0,
+    CLRPLL_MODE,
+} PLL_MODE_T;
+
+typedef enum
+{
+    RUNTIME_SWCMD_CAS_FS = 0,
+    RUNTIME_SWCMD_CAS_OFF,
+    RUNTIME_SWCMD_WCK2DQI_START,
+    RUNTIME_SWCMD_WCK2DQO_START,
+    RUNTIME_SWCMD_MRW,
+    RUNTIME_SWCMD_ZQCAL_START,
+    RUNTIME_SWCMD_ZQCAL_LATCH
+} RUNTIME_SWCMD_SEL_T;
+
+typedef enum
+{
+    PI_BASED,
+    DLY_BASED
+} WLEV_DELAY_BASED_T;
+
+enum lpddr5_rpre_mode {
+	LPDDR5_RPRE_4S_0T = 0,
+	LPDDR5_RPRE_2S_2T,
+	LPDDR5_RPRE_0S_4T,
+	LPDDR5_RPRE_XS_4T, /* X = 2~4tWCK */
+};
+
+enum rxdqs_autok_burst_len {
+	RXDQS_BURST_LEN_8 = 0,
+	RXDQS_BURST_LEN_16,
+	RXDQS_BURST_LEN_32,
+};
+
+typedef enum
+{
+    EYESCAN_FLAG_DISABLE= 0,
+    EYESCAN_FLAG_ENABLE,
+    EYESCAN_FLAG_ENABLE_BUT_NORMAL_K,
+} EYESCAN_FLAG_TYPE_T;
+
+#ifdef FOR_HQA_REPORT_USED
+typedef enum
+{
+    HQA_REPORT_FORMAT0 = 0,
+    HQA_REPORT_FORMAT0_1,
+    HQA_REPORT_FORMAT0_2,
+    HQA_REPORT_FORMAT1,
+    HQA_REPORT_FORMAT2,
+    HQA_REPORT_FORMAT2_1,
+    HQA_REPORT_FORMAT3,
+    HQA_REPORT_FORMAT4,
+    HQA_REPORT_FORMAT5,
+    HQA_REPORT_FORMAT6
+} HQA_REPORT_FORMAT_T;
+#endif
+
+#ifdef DEVIATION
+typedef enum
+{
+    Deviation_CA = 0,
+    Deviation_RX,
+    Deviation_TX,
+    Deviation_MAX
+} DRAM_DEVIATION_TYPE_T; // DRAM SHUFFLE RG type
+#endif
+
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+#if RUNTIME_SHMOO_RELEATED_FUNCTION
+typedef struct _RUNTIME_SHMOO_SAVE_PARAMETER_T
+{
+    U8 flag;
+    U16 TX_PI_delay;
+    U16 TX_Original_PI_delay;
+    U16 TX_DQM_PI_delay;
+    U16 TX_Original_DQM_PI_delay;
+    S16 RX_delay[8];
+    S16 RX_Original_delay;
+    U8 TX_Vref_Range;
+    U8 TX_Vref_Value;
+    U8 TX_Channel;
+    U8 TX_Rank;
+    U8 TX_Byte;
+    U8 Scan_Direction;
+} RUNTIME_SHMOO_SAVE_PARAMETER_T;
+#endif
+
+typedef struct _SAVE_TIME_FOR_CALIBRATION_T
+{
+    //U8 femmc_Ready;
+
+    DRAM_RANK_NUMBER_T support_rank_num;
+
+    // Calibration or not
+    //U8 Bypass_TXWINDOW;
+    //U8 Bypass_RXWINDOW;
+    //U8 Bypass_RDDQC;
+
+    // delay cell time
+    U16 u2DelayCellTimex100;
+
+    // CLK & DQS duty
+    S8 s1ClockDuty_clk_delay_cell[CHANNEL_NUM][RANK_MAX];
+    S8 s1DQSDuty_clk_delay_cell[CHANNEL_NUM][DQS_BYTE_NUMBER];
+    S8 s1WCKDuty_clk_delay_cell[CHANNEL_NUM][DQS_BYTE_NUMBER];
+#if APPLY_DQDQM_DUTY_CALIBRATION
+    S8 s1DQDuty_clk_delay_cell[CHANNEL_NUM][DQS_BYTE_NUMBER];
+    S8 s1DQMDuty_clk_delay_cell[CHANNEL_NUM][DQS_BYTE_NUMBER];
+#endif
+    // CBT
+    U8 u1CBTVref_Save[CHANNEL_NUM][RANK_MAX];
+    S8 s1CBTCmdDelay_Save[CHANNEL_NUM][RANK_MAX];
+    U8 u1CBTCsDelay_Save[CHANNEL_NUM][RANK_MAX];
+    #if CA_PER_BIT_DELAY_CELL
+    U8 u1CBTCA_PerBit_DelayLine_Save[CHANNEL_NUM][RANK_MAX][DQS_BIT_NUMBER];
+    #endif
+
+    // Write leveling
+    U8 u1WriteLeveling_bypass_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER];  //for bypass writeleveling
+
+    // Gating
+    U8 u1Gating_MCK_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER];
+    U8 u1Gating_UI_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER];
+    U8 u1Gating_PI_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER];
+    U8 u1Gating_pass_count_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER];
+
+    // TX perbit
+    U8 u1TxWindowPerbitVref_Save[CHANNEL_NUM][RANK_MAX];
+    U16 u1TxCenter_min_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER];
+    U16 u1TxCenter_max_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER];
+    U16 u1Txwin_center_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH];
+    //U16 u1Txfirst_pass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4];
+    //U16 u1Txlast_pass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4];
+    //U8 u1TX_PerBit_DelayLine_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4];
+
+    // Datlat
+    U8 u1RxDatlat_Save[CHANNEL_NUM][RANK_MAX];
+
+    // RX perbit
+    U8 u1RxWinPerbitVref_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER];
+    U16 u1RxWinPerbit_DQS[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER];
+    U16 u1RxWinPerbit_DQM[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER];
+    U16 u1RxWinPerbit_DQ[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH];
+
+    //TX OE
+    U8 u1TX_OE_DQ_MCK[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER];
+    U8 u1TX_OE_DQ_UI[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER];
+
+
+#if RUNTIME_SHMOO_RELEATED_FUNCTION
+    S16 u1RxWinPerbitDQ_firsbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH];  //for bypass rxwindow
+    U8 u1RxWinPerbitDQ_lastbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH];  //for bypass rxwindow
+    U8 u1SwImpedanceResule[2][4];
+    U32 u4RG_Backup[CHANNEL_NUM][RUNTIME_SHMOO_RG_BACKUP_NUM];
+
+    RUNTIME_SHMOO_SAVE_PARAMETER_T Runtime_Shmoo_para;
+#endif
+}SAVE_TIME_FOR_CALIBRATION_T;
+#endif // SUPPORT_SAVE_TIME_FOR_CALIBRATION
+
+#if MRW_CHECK_ONLY
+#define MR_NUM 64
+extern U16 u2MRRecord[CHANNEL_NUM][RANK_MAX][FSP_MAX][MR_NUM];
+#endif
+
+////////////////////////////
+typedef struct _DRAMC_CTX_T
+{
+    DRAM_CHANNEL_NUMBER_T support_channel_num;
+    DRAM_CHANNEL_T channel;
+    DRAM_RANK_NUMBER_T support_rank_num;
+    DRAM_RANK_T rank;
+    DRAM_PLL_FREQ_SEL_T freq_sel;
+    DRAM_DRAM_TYPE_T dram_type;
+    DRAM_FAST_SWITH_POINT_T dram_fsp;  // only for LP4, uesless in LP3
+    DRAM_FAST_SWITH_POINT_T boot_fsp;  // for RTMRW DFS
+    DRAM_ODT_MODE_T odt_onoff;/// only for LP4, uesless in LP3
+    DRAM_CBT_MODE_T dram_cbt_mode[RANK_MAX]; //only for LP4, useless in LP3
+    DRAM_DBI_MODE_T DBI_R_onoff[FSP_MAX];   // only for LP4, uesless in LP3
+    DRAM_DBI_MODE_T DBI_W_onoff[FSP_MAX];   // only for LP4, uesless in LP3
+    DRAM_DATA_WIDTH_T data_width;
+    U32 test2_1;
+    U32 test2_2;
+    DRAM_TEST_PATTERN_T test_pattern;
+    U16 frequency;
+    U16 freqGroup; /* Used to support freq's that are not in ACTimingTable */
+    U16 vendor_id;
+    U16 revision_id;
+    U16 density;
+    U64 ranksize[RANK_MAX];
+    U16 u2DelayCellTimex100;
+    //U8 enable_cbt_scan_vref;
+    //U8 enable_rx_scan_vref;
+    //U8 enable_tx_scan_vref;
+
+    #if PRINT_CALIBRATION_SUMMARY
+    U32 aru4CalResultFlag[CHANNEL_NUM][RANK_MAX];// record the calibration is fail or success,  0:success, 1: fail
+    U32 aru4CalExecuteFlag[CHANNEL_NUM][RANK_MAX]; // record the calibration is execute or not,  0:no operate, 1: done
+    U32 SWImpCalResult;
+    U32 SWImpCalExecute;
+    #if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK
+    U32 FastKResultFlag[2][RANK_MAX];// record the calibration is fail or success,  0:success, 1: fail
+    U32 FastKExecuteFlag[2][RANK_MAX]; // record the calibration is execute or not,  0:no operate, 1: done
+    #endif
+    #endif
+
+    bool isWLevInitShift[CHANNEL_NUM];
+
+    #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+    U8 femmc_Ready;
+    // Calibration or not
+    U8 Bypass_TXWINDOW;
+    U8 Bypass_RXWINDOW;
+    U8 Bypass_RDDQC;
+    SAVE_TIME_FOR_CALIBRATION_T *pSavetimeData;
+    #endif
+    DRAM_DFS_FREQUENCY_TABLE_T *pDFSTable;
+    DRAM_DFS_REG_SHU_T ShuRGAccessIdx;
+    lp5_training_mode_t lp5_training_mode; //only for LP5
+    lp5_cbt_phase_t lp5_cbt_phase; //only for LP5
+    u8 new_cbt_mode;
+    U8 u1PLLMode;
+    DRAM_DBI_MODE_T curDBIState;
+    DRAM_FAST_SWITH_POINT_T support_fsp_num;
+    DRAM_PINMUX DRAMPinmux;
+    U8 u110GBEn[RANK_MAX];
+    bool isMaxFreq4266;
+} DRAMC_CTX_T;
+
+typedef struct _DRAM_DVFS_TABLE_T
+{
+    DRAM_PLL_FREQ_SEL_T freq_sel;
+    DRAM_DFS_SRAM_SHU_T SRAMIdx;
+    U32 u4Vcore;
+} DRAM_DVFS_TABLE_T;
+
+typedef struct _PASS_WIN_DATA_T
+{
+    S16 first_pass;
+    S16 last_pass;
+    S16 win_center;
+    U16 win_size;
+    U16 best_dqdly;
+} PASS_WIN_DATA_T;
+
+typedef struct _FINAL_WIN_DATA_T {
+	unsigned char final_vref;
+	signed int final_ca_clk;
+	unsigned char final_range;
+} FINAL_WIN_DATA_T;
+
+typedef struct _REG_TRANSFER
+{
+    U32 u4Addr;
+    U32 u4Fld;
+} REG_TRANSFER_T;
+
+typedef struct _DRAM_INFO_BY_MRR_T
+{
+    U16 u2MR5VendorID;
+    U16 u2MR6RevisionID;
+    U64 u8MR8Density[RANK_MAX];
+    U32 u4RankNum;
+    U8 u1DieNum[RANK_MAX];
+} DRAM_INFO_BY_MRR_T;
+
+typedef struct _JMETER_DELAYCELL_T
+{
+    U32 Vcore;
+    U16 delay_cell_ps;
+} JMETER_DELAYCELL_T;
+
+#if PIN_CHECK_TOOL
+typedef struct _DEBUG_PIN_INF_FOR_FLASHTOOL_T
+{
+    U16 TOTAL_ERR;//DQ,CA
+    U16 IMP_ERR_FLAG;
+    U8 WL_ERR_FLAG;//DQS
+    U8 CA_ERR_FLAG[CHANNEL_MAX][RANK_MAX];
+    U8 CA_WIN_SIZE[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP4];
+    U8 DRAM_PIN_RX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_BYTE_NUMBER];
+    U8 DRAM_PIN_TX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_BYTE_NUMBER];
+    U8 DQ_RX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_BYTE_NUMBER];
+    U8 DQ_TX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_BYTE_NUMBER];
+    U16 DQ_RX_WIN_SIZE[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH];
+    U8 DQ_TX_WIN_SIZE[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH];
+} DEBUG_PIN_INF_FOR_FLASHTOOL_T;
+#endif
+
+typedef struct _VCORE_DELAYCELL_T
+{
+    U32 u2Vcore;
+    U16 u2DelayCell;
+} VCORE_DELAYCELL_T;
+
+typedef struct _JM_DLY_T
+{
+    U16 u1JmDelay;
+    U8 u1TransLevel;
+} JM_DLY_T;
+
+
+typedef struct _JMETER_T
+{
+    JM_DLY_T JmtrInfo[3];
+    U8 u1TransCnt;
+} JMETER_T;
+
+typedef enum
+{
+    DMA_PREPARE_DATA_ONLY,
+    DMA_CHECK_DATA_ACCESS_ONLY_AND_NO_WAIT,
+    DMA_CHECK_COMAPRE_RESULT_ONLY,
+    DMA_CHECK_DATA_ACCESS_AND_COMPARE,
+} DRAM_DMA_CHECK_RESULT_T;
+
+#if defined(DDR_INIT_TIME_PROFILING) || ENABLE_APB_MASK_WRITE
+typedef struct _PROFILING_TIME_T
+{
+    U32 u4TickHigh;
+    U32 u4TickLow;
+} PROFILING_TIME_T;
+#endif
+
+//For new register access
+#define SHIFT_TO_CHB_ADDR       ((U32)CHANNEL_B << POS_BANK_NUM)
+#if (CHANNEL_NUM > 2)
+#define SHIFT_TO_CHC_ADDR       ((U32)CHANNEL_C << POS_BANK_NUM)
+#define SHIFT_TO_CHD_ADDR       ((U32)CHANNEL_D << POS_BANK_NUM)
+#endif
+#define DRAMC_REG_ADDR(offset)  ((p->channel << POS_BANK_NUM) + (offset))
+#define SYS_REG_ADDR(offset)    (offset)
+
+// Different from Pi_calibration.c due to Base address
+//#define mcSET_DRAMC_REG_ADDR(offset)    (DRAMC_BASE_ADDRESS | (p->channel << POS_BANK_NUM) | (offset))
+#define mcSET_SYS_REG_ADDR(offset)    (DRAMC_BASE_ADDRESS | (offset))
+#define mcSET_DRAMC_NAO_REG_ADDR(offset)   (DRAMC_NAO_BASE_ADDRESS | (offset))
+#define mcSET_DRAMC_AO_REG_ADDR(offset)   (DRAMC_AO_BASE_ADDRESS | (offset))
+//#define mcSET_DRAMC_AO_REG_ADDR_CHC(offset)   ((DRAMC_AO_BASE_ADDRESS + ((U32)CHANNEL_C << POS_BANK_NUM)) | (offset))
+#define mcSET_DDRPHY_REG_ADDR(offset) (DDRPHY_BASE_ADDR | (offset))
+#define mcSET_DDRPHY_REG_ADDR_CHA(offset) ((DDRPHY_BASE_ADDR + ((U32) CHANNEL_A << POS_BANK_NUM)) | (offset))
+#define mcSET_DDRPHY_REG_ADDR_CHB(offset) ((DDRPHY_BASE_ADDR + SHIFT_TO_CHB_ADDR) | (offset))
+//#define mcSET_DDRPHY_REG_ADDR_CHC(offset) ((DDRPHY_BASE_ADDR + ((U32) CHANNEL_C << POS_BANK_NUM)) | (offset))
+//#define mcSET_DDRPHY_REG_ADDR_CHD(offset) ((DDRPHY_BASE_ADDR + ((U32) CHANNEL_D << POS_BANK_NUM)) | (offset))
+
+//--------------------------------------------------------------------------
+//              Dram Mode Registers Operation
+//--------------------------------------------------------------------------
+#define MRWriteFldMulti(p, mr_idx, list, UpdateMode)                        \
+{                                                                           \
+	UINT16 upk = 1; \
+	U8 msk = (U8)(list); \
+	{                                                                       \
+        upk = 0; \
+    	DramcMRWriteFldMsk(p, mr_idx, (U8)(list), msk, UpdateMode); \
+	}                                                                       \
+}
+
+#define JUST_TO_GLOBAL_VALUE (0)
+#define TO_MR     (1)
+
+// LP5 MR30
+#define MR30_DCAU            (Fld(4, 4)) // DCA for upper byte
+#define MR30_DCAL            (Fld(4, 0)) // DCA for lower byte
+
+// LP5 MR26
+#define MR26_DCMU1           (Fld(1, 5))
+#define MR26_DCMU0           (Fld(1, 4))
+#define MR26_DCML1           (Fld(1, 3))
+#define MR26_DCML0           (Fld(1, 2))
+#define MR26_DCM_FLIP        (Fld(1, 1))
+#define MR26_DCM_START_STOP  (Fld(1, 0))
+
+// LP4 MR13
+#define MR13_FSP_OP          (Fld(1, 7))
+#define MR13_FSP_WR          (Fld(1, 6))
+#define MR13_DMD             (Fld(1, 5))
+#define MR13_PRO             (Fld(1, 4))
+#define MR13_VRCG            (Fld(1, 3))
+#define MR13_CBT             (Fld(1, 0))
+
+#define MR16_FSP_WR_SHIFT    (0)
+#define MR16_FSP_OP_SHIFT    (2)
+#define MR16_FSP_CBT         (4)
+#define MR16_VRCG            (6)
+#define MR16_CBT_PHASE       (7)
+
+/***********************************************************************/
+/*              External declarations                                  */
+/***********************************************************************/
+EXTERN DRAMC_CTX_T *psCurrDramCtx;
+#if QT_GUI_Tool
+EXTERN FILE *fp_A60868;
+EXTERN FILE *fp_A60868_RGDump;
+#endif
+/***********************************************************************/
+/*              Public Functions                                       */
+/***********************************************************************/
+// basic function
+EXTERN U8 u1IsLP4Family(DRAM_DRAM_TYPE_T dram_type);
+EXTERN int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_extern, DRAM_INFO_BY_MRR_T *DramInfo, U8 get_mdl_used);
+EXTERN void Dramc_DDR_Reserved_Mode_setting(void);
+EXTERN void Dramc_DDR_Reserved_Mode_AfterSR(void);
+EXTERN void Before_Init_DRAM_While_Reserve_Mode_fail(DRAM_DRAM_TYPE_T dram_type);
+
+void vSetVcoreByFreq(DRAMC_CTX_T *p);
+U32 Get_WL_by_MR_LP4(U8 Version, U8 MR_WL_field_value);
+U8 u1MCK2UI_DivShift(DRAMC_CTX_T *p);
+void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_level);
+void UpdateDFSTbltoDDR3200(DRAMC_CTX_T *p);
+void DFSInitForCalibration(DRAMC_CTX_T *p);
+void mdl_setting(DRAMC_CTX_T *p);
+void MPLLInit(void);
+void DramcCKEDebounce(DRAMC_CTX_T *p);
+void DramcModifiedRefreshMode(DRAMC_CTX_T *p);
+void XRTRTR_SHU_Setting(DRAMC_CTX_T * p);
+void TXPICGSetting(DRAMC_CTX_T * p);
+void XRTWTW_SHU_Setting(DRAMC_CTX_T * p);
+DRAM_STATUS_T DramcDualRankRxdatlatCal(DRAMC_CTX_T *p);
+void vSwitchWriteDBISettings(DRAMC_CTX_T *p, U8 u1OnOff);
+void Get_RX_DelayCell(DRAMC_CTX_T *p);
+void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p);
+void EnableDFSNoQueueFlush(DRAMC_CTX_T *p);
+void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn);
+void Enable_TxWDQS(DRAMC_CTX_T *p);
+void Enable_ClkTxRxLatchEn(DRAMC_CTX_T *p);
+void EnableRxDcmDPhy(DRAMC_CTX_T *p, U16 u2Freq);
+void DramcRxdqsGatingPreProcess(DRAMC_CTX_T *p);
+void LP4_single_end_DRAMC_post_config(DRAMC_CTX_T *p, U8 LP4Y_EN);
+void vResetDelayChainBeforeCalibration(DRAMC_CTX_T *p);
+U32 Get_RL_by_MR_LP4(U8 BYTE_MODE_EN,U8 DBI_EN, U8 MR_RL_field_value);
+U8 LP4_DRAM_INIT_RLWL_MRfield_config(U32 data_rate);
+
+unsigned int dramc_set_vcore_voltage(unsigned int vcore);
+unsigned int dramc_get_vcore_voltage(void);
+unsigned int dramc_set_vdram_voltage(unsigned int ddr_type, unsigned int vdram);
+unsigned int dramc_get_vdram_voltage(unsigned int ddr_type);
+unsigned int dramc_set_vddq_voltage(unsigned int ddr_type, unsigned int vddq);
+unsigned int dramc_get_vddq_voltage(unsigned int ddr_type);
+unsigned int dramc_set_vmddr_voltage(unsigned int vmddr);
+unsigned int dramc_get_vmddr_voltage(void);
+unsigned int dramc_set_vio18_voltage(unsigned int vio18);
+unsigned int dramc_get_vio18_voltage(void);
+
+void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p);
+
+void DramcNewDutyCalibration(DRAMC_CTX_T *p);
+unsigned int mt_get_dram_type_from_hw_trap(void);
+U8 Get_MDL_Used_Flag(void);
+void Set_MDL_Used_Flag(U8 value);
+void SetMr13VrcgToNormalOperation(DRAMC_CTX_T *p);
+U8 u1GetMR4RefreshRate(DRAMC_CTX_T *p, DRAM_CHANNEL_T channel);
+void cbt_dfs_mr13_global(DRAMC_CTX_T *p, U8 freq);
+void TX_Path_Algorithm(DRAMC_CTX_T *p);
+DRAM_PLL_FREQ_SEL_T GetSelByFreq(DRAMC_CTX_T *p, U16 u2freq);
+void DVFS_config(DRAMC_CTX_T *p);
+DRAM_CBT_MODE_T vGet_Dram_CBT_Mode(DRAMC_CTX_T *p);
+int divRoundClosest(const int n, const int d);
+void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_level);
+void DramcDFSDirectJump_SPMMode_forK(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_level);
+void ShuffleDfsToOriginalFSP(DRAMC_CTX_T *p);
+void HwSaveForSR(DRAMC_CTX_T *p);
+void ClkFreeRunForDramcPsel(DRAMC_CTX_T *p);
+void EnableCmdPicgEffImprove(DRAMC_CTX_T *p);
+void TxWinTransferDelayToUIPI(DRAMC_CTX_T *p, U16 uiDelay, U8 u1AdjustPIToCenter, U8* pu1UILarge_DQ, U8* pu1UISmall_DQ, U8* pu1PI, U8* pu1UILarge_DQOE, U8* pu1UISmall_DQOE);
+void CmdOEOnOff(DRAMC_CTX_T *p, U8 u1OnOff, CMDOE_DIS_CHANNEL CmdOeDisChannelNUM);
+DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p);
+void sv_algorithm_assistance_LP4_400(DRAMC_CTX_T *p);
+int doe_get_config(const char* feature);
+void vDramcACTimingOptimize(DRAMC_CTX_T *p);
+
+const char* HQA_LOG_Parsing_Freq(void);
+void HQA_LOG_Print_Freq_String(DRAMC_CTX_T *p);
+void DramcDumpDebugInfo(DRAMC_CTX_T *p);
+void DramcModeReg_Check(DRAMC_CTX_T *p);
+
+
+#endif // _PI_API_H
diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_register.h b/src/vendorcode/mediatek/mt8195/include/dramc_register.h
new file mode 100644
index 000000000000..4cf36f1df322
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/dramc_register.h
@@ -0,0 +1,273 @@
+//
+//  REGISTER.H  Register map include file
+//
+#ifndef _A60868_REGISTER_H_
+#define _A60868_REGISTER_H_
+
+#include "dramc_pi_api.h"
+
+
+#define POS_BANK_NUM 16  // SW Virtual base address position
+
+#if (fcFOR_CHIP_ID == fc8195)
+#include "8195_Register_DDRPHY_MD32.h"
+#include "8195_Register_DDRPHY_NAO.h"
+#include "8195_Register_DDRPHY_AO.h"
+#include "8195_Register_DRAMC_AO.h"
+#include "8195_Register_DRAMC_NAO.h"
+#else
+#include "Register_DDRPHY_MD32.h"
+#include "Register_DDRPHY_NAO.h"
+#include "Register_DDRPHY_AO.h"
+#include "Register_DRAMC_AO.h"
+#include "Register_DRAMC_NAO.h"
+#include "Register_SYSTEM.h"
+#endif
+
+#if FOR_DV_SIMULATION_USED
+#define Channel_A_DRAMC_NAO_BASE_VIRTUAL        0x40000
+#define Channel_B_DRAMC_NAO_BASE_VIRTUAL        0x50000
+#define Channel_A_DRAMC_AO_BASE_VIRTUAL         0x60000
+#define Channel_B_DRAMC_AO_BASE_VIRTUAL         0x70000
+#define Channel_A_DDRPHY_NAO_BASE_VIRTUAL       0x80000
+#define Channel_B_DDRPHY_NAO_BASE_VIRTUAL       0x90000
+#define Channel_A_DDRPHY_AO_BASE_VIRTUAL        0xA0000
+#define Channel_B_DDRPHY_AO_BASE_VIRTUAL        0xB0000
+#define Channel_A_DDRPHY_DPM_BASE_VIRTUAL       0xC0000
+#define MAX_BASE_VIRTUAL                        0xD0000
+#else
+// SW Virtual base address
+#define Channel_A_DRAMC_NAO_BASE_VIRTUAL        0x40000
+#define Channel_B_DRAMC_NAO_BASE_VIRTUAL        0x50000
+#define Channel_C_DRAMC_NAO_BASE_VIRTUAL        0x60000
+#define Channel_D_DRAMC_NAO_BASE_VIRTUAL        0x70000
+#define Channel_A_DRAMC_AO_BASE_VIRTUAL	        0x80000
+#define Channel_B_DRAMC_AO_BASE_VIRTUAL         0x90000
+#define Channel_C_DRAMC_AO_BASE_VIRTUAL         0xA0000
+#define Channel_D_DRAMC_AO_BASE_VIRTUAL         0xB0000
+#define Channel_A_DDRPHY_NAO_BASE_VIRTUAL       0xC0000
+#define Channel_B_DDRPHY_NAO_BASE_VIRTUAL       0xD0000
+#define Channel_C_DDRPHY_NAO_BASE_VIRTUAL       0xE0000
+#define Channel_D_DDRPHY_NAO_BASE_VIRTUAL       0xF0000
+#define Channel_A_DDRPHY_AO_BASE_VIRTUAL        0x100000
+#define Channel_B_DDRPHY_AO_BASE_VIRTUAL        0x110000
+#define Channel_C_DDRPHY_AO_BASE_VIRTUAL        0x120000
+#define Channel_D_DDRPHY_AO_BASE_VIRTUAL        0x130000
+#define Channel_A_DDRPHY_DPM_BASE_VIRTUAL       0x140000
+#define Channel_B_DDRPHY_DPM_BASE_VIRTUAL       0x150000
+#define MAX_BASE_VIRTUAL                        0x160000
+#endif
+
+#define DRAMC_WBR 0x100010B4
+//#if (CHANNEL_NUM==4)
+#define DRAMC_BROADCAST_ON_4CH 0x27f7f  //4CH
+//#else
+#define DRAMC_BROADCAST_ON_2CH 0x7f  //2CH
+//#endif
+#define DRAMC_BROADCAST_ON 0x1
+#define DRAMC_BROADCAST_OFF 0x0
+
+//Definitions indicating DRAMC, DDRPHY register shuffle offset
+#define SHU_GRP_DRAMC_OFFSET      0x700
+#define SHU_GRP_DDRPHY_OFFSET     0x700
+
+#define DRAMC_REG_AO_SHU_OFFSET                 (0x700)
+#define DRAMC_REG_AO_RANK_OFFSET                (0x200)
+#define DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR (DRAMC_REG_RK_TEST2_A1 - DRAMC_AO_BASE_ADDRESS) // 0x0500
+#define DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR  (DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR + DRAMC_REG_AO_RANK_OFFSET)
+#define DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR (DRAMC_REG_SHURK_SELPH_DQ0 - DRAMC_AO_BASE_ADDRESS) // 0x1200
+#define DRAMC_REG_AO_RANK0_W_SHUFFLE0_END_ADDR  (DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR + DRAMC_REG_AO_RANK_OFFSET)
+#define DRAMC_REG_AO_SHUFFLE0_BASE_ADDR         (DRAMC_REG_SHURK_SELPH_DQ0 - DRAMC_AO_BASE_ADDRESS) // 0x1200
+#define DRAMC_REG_AO_SHUFFLE0_END_ADDR          (DRAMC_REG_SHU_ACTIM7 - DRAMC_AO_BASE_ADDRESS) // 0x16E8
+
+#define DDRPHY_AO_B0_B1_OFFSET                  (0x180)
+#define DDRPHY_AO_SHU_OFFSET                    (0x700)
+#define DDRPHY_AO_RANK_OFFSET                   (0x80)
+#define DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR    (DDRPHY_REG_RK_B0_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x0060
+#define DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR     (DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
+#define DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR    (DDRPHY_REG_RK_B1_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x01E0
+#define DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR     (DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
+#define DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR    (DDRPHY_REG_RK_CA_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x0360
+#define DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR     (DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
+#define DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR       (DDRPHY_REG_SHU_R0_B0_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x0760
+#define DDRPHY_AO_RANK0_B0_SHU0_END_ADDR        (DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
+#define DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR       (DDRPHY_REG_SHU_R0_B1_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x08E0
+#define DDRPHY_AO_RANK0_B1_SHU0_END_ADDR        (DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
+#define DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR       (DDRPHY_REG_SHU_R0_CA_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x0A60
+#define DDRPHY_AO_RANK0_CA_SHU0_END_ADDR        (DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
+#define DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR     (DDRPHY_REG_MISC_SHU_RK_DQSCTL - DDRPHY_AO_BASE_ADDRESS) // 0x0BE0
+#define DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR      (DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
+#define DDRPHY_AO_SHUFFLE0_BASE_ADDR            (DDRPHY_REG_SHU_PHYPLL0 - DDRPHY_AO_BASE_ADDRESS) // 0x700
+#define DDRPHY_AO_SHUFFLE0_END_ADDR             (DDRPHY_REG_MISC_SHU_CG_CTRL0 - DDRPHY_AO_BASE_ADDRESS) // 0xDA4
+
+#define DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET        (0x20)
+#define DDRPHY_NAO_GATING_STATUS_RK_OFFSET              (0x10)
+#define DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START   (DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0600
+#define DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END     (DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET)
+#define DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START   (DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0640
+#define DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_END     (DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET)
+#define DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START   (DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0680
+#define DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_END     (DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET)
+#define DDRPHY_NAO_RANK0_GATING_STATUS_START            (DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0420
+#define DDRPHY_NAO_RANK0_GATING_STATUS_END              (DDRPHY_NAO_RANK0_GATING_STATUS_START + DDRPHY_NAO_GATING_STATUS_RK_OFFSET)
+
+#define DRAMC_REG_NAO_RANK_OFFSET                (0x200)
+#define DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR (DRAMC_REG_MR_BACKUP_00_RK0_FSP0 - DRAMC_NAO_BASE_ADDRESS) // 0x0900
+#define DRAMC_REG_NAO_RANK0_ROW_OFFSET_END_ADDR  (DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR + DRAMC_REG_NAO_RANK_OFFSET)
+
+// HW Physical base address
+#if defined(__DPM__)
+/* MD32 address */
+#undef Channel_A_DRAMC_AO_BASE_ADDRESS
+#define Channel_A_DRAMC_AO_BASE_ADDRESS         0x300A2000
+#undef Channel_B_DRAMC_AO_BASE_ADDRESS
+#define Channel_B_DRAMC_AO_BASE_ADDRESS         0x300B2000
+#undef Channel_C_DRAMC_AO_BASE_ADDRESS
+#define Channel_C_DRAMC_AO_BASE_ADDRESS         0x0
+#undef Channel_D_DRAMC_AO_BASE_ADDRESS
+#define Channel_D_DRAMC_AO_BASE_ADDRESS         0x0
+#undef Channel_A_DRAMC_NAO_BASE_ADDRESS
+#define Channel_A_DRAMC_NAO_BASE_ADDRESS        0x300A8000
+#undef Channel_B_DRAMC_NAO_BASE_ADDRESS
+#define Channel_B_DRAMC_NAO_BASE_ADDRESS        0x300B8000
+#undef Channel_C_DRAMC_NAO_BASE_ADDRESS
+#define Channel_C_DRAMC_NAO_BASE_ADDRESS        0x0
+#undef Channel_D_DRAMC_NAO_BASE_ADDRESS
+#define Channel_D_DRAMC_NAO_BASE_ADDRESS        0x0
+#undef Channel_A_DDRPHY_AO_BASE_ADDRESS
+#define Channel_A_DDRPHY_AO_BASE_ADDRESS        0x300A6000
+#undef Channel_B_DDRPHY_AO_BASE_ADDRESS
+#define Channel_B_DDRPHY_AO_BASE_ADDRESS        0x300B6000
+#undef Channel_C_DDRPHY_AO_BASE_ADDRESS
+#define Channel_C_DDRPHY_AO_BASE_ADDRESS        0x0
+#undef Channel_D_DDRPHY_AO_BASE_ADDRESS
+#define Channel_D_DDRPHY_AO_BASE_ADDRESS        0x0
+#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
+#define Channel_A_DDRPHY_NAO_BASE_ADDRESS       0x300AA000
+#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
+#define Channel_B_DDRPHY_NAO_BASE_ADDRESS       0x300BA000
+#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
+#define Channel_C_DDRPHY_NAO_BASE_ADDRESS       0x0
+#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
+#define Channel_D_DDRPHY_NAO_BASE_ADDRESS       0x0
+#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
+#define Channel_A_DDRPHY_DPM_BASE_ADDRESS       0x30040000
+#elif (FOR_DV_SIMULATION_USED)
+#undef Channel_A_DRAMC_AO_BASE_ADDRESS
+#define Channel_A_DRAMC_AO_BASE_ADDRESS         0x10000
+#undef Channel_B_DRAMC_AO_BASE_ADDRESS
+#define Channel_B_DRAMC_AO_BASE_ADDRESS         0x40000
+#undef Channel_C_DRAMC_AO_BASE_ADDRESS
+#define Channel_C_DRAMC_AO_BASE_ADDRESS         0x0
+#undef Channel_D_DRAMC_AO_BASE_ADDRESS
+#define Channel_D_DRAMC_AO_BASE_ADDRESS         0x0
+
+#undef Channel_A_DRAMC_NAO_BASE_ADDRESS
+#define Channel_A_DRAMC_NAO_BASE_ADDRESS        0x20000
+#undef Channel_B_DRAMC_NAO_BASE_ADDRESS
+#define Channel_B_DRAMC_NAO_BASE_ADDRESS        0x50000
+#undef Channel_C_DRAMC_NAO_BASE_ADDRESS
+#define Channel_C_DRAMC_NAO_BASE_ADDRESS         0x0
+#undef Channel_D_DRAMC_NAO_BASE_ADDRESS
+#define Channel_D_DRAMC_NAO_BASE_ADDRESS         0x0
+
+#undef Channel_A_DDRPHY_AO_BASE_ADDRESS
+#define Channel_A_DDRPHY_AO_BASE_ADDRESS        0x30000
+#undef Channel_B_DDRPHY_AO_BASE_ADDRESS
+#define Channel_B_DDRPHY_AO_BASE_ADDRESS        0x60000
+#undef Channel_C_DDRPHY_AO_BASE_ADDRESS
+#define Channel_C_DDRPHY_AO_BASE_ADDRESS        0x0
+#undef Channel_D_DDRPHY_AO_BASE_ADDRESS
+#define Channel_D_DDRPHY_AO_BASE_ADDRESS        0x0
+
+#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
+#define Channel_A_DDRPHY_NAO_BASE_ADDRESS       0x70000
+#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
+#define Channel_B_DDRPHY_NAO_BASE_ADDRESS       0x80000
+#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
+#define Channel_C_DDRPHY_NAO_BASE_ADDRESS        0x0
+#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
+#define Channel_D_DDRPHY_NAO_BASE_ADDRESS        0x0
+
+#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
+#define Channel_A_DDRPHY_DPM_BASE_ADDRESS       0xD0000 //@Darren, 0x90000 + 0x40000 for DV sim
+#elif(HAPS_FPFG_A60868 ==0)
+#undef Channel_A_DRAMC_AO_BASE_ADDRESS
+#define Channel_A_DRAMC_AO_BASE_ADDRESS         0x10230000
+#undef Channel_B_DRAMC_AO_BASE_ADDRESS
+#define Channel_B_DRAMC_AO_BASE_ADDRESS         0x10240000
+#undef Channel_C_DRAMC_AO_BASE_ADDRESS
+#define Channel_C_DRAMC_AO_BASE_ADDRESS         0x10250000
+#undef Channel_D_DRAMC_AO_BASE_ADDRESS
+#define Channel_D_DRAMC_AO_BASE_ADDRESS         0x10260000
+#undef Channel_A_DRAMC_NAO_BASE_ADDRESS
+#define Channel_A_DRAMC_NAO_BASE_ADDRESS        0x10234000
+#undef Channel_B_DRAMC_NAO_BASE_ADDRESS
+#define Channel_B_DRAMC_NAO_BASE_ADDRESS        0x10244000
+#undef Channel_C_DRAMC_NAO_BASE_ADDRESS
+#define Channel_C_DRAMC_NAO_BASE_ADDRESS        0x10254000
+#undef Channel_D_DRAMC_NAO_BASE_ADDRESS
+#define Channel_D_DRAMC_NAO_BASE_ADDRESS        0x10264000
+#undef Channel_A_DDRPHY_AO_BASE_ADDRESS
+#define Channel_A_DDRPHY_AO_BASE_ADDRESS        0x10238000
+#undef Channel_B_DDRPHY_AO_BASE_ADDRESS
+#define Channel_B_DDRPHY_AO_BASE_ADDRESS        0x10248000
+#undef Channel_C_DDRPHY_AO_BASE_ADDRESS
+#define Channel_C_DDRPHY_AO_BASE_ADDRESS        0x10258000
+#undef Channel_D_DDRPHY_AO_BASE_ADDRESS
+#define Channel_D_DDRPHY_AO_BASE_ADDRESS        0x10268000
+#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
+#define Channel_A_DDRPHY_NAO_BASE_ADDRESS       0x10236000
+#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
+#define Channel_B_DDRPHY_NAO_BASE_ADDRESS       0x10246000
+#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
+#define Channel_C_DDRPHY_NAO_BASE_ADDRESS       0x10256000
+#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
+#define Channel_D_DDRPHY_NAO_BASE_ADDRESS       0x10266000
+#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
+#define Channel_A_DDRPHY_DPM_BASE_ADDRESS       0x10940000
+#undef Channel_B_DDRPHY_DPM_BASE_ADDRESS
+#define Channel_B_DDRPHY_DPM_BASE_ADDRESS       0x10A40000
+#else  // A60868 FPGA Base Address
+#undef Channel_A_DRAMC_AO_BASE_ADDRESS
+#define Channel_A_DRAMC_AO_BASE_ADDRESS         0x40000
+#undef Channel_B_DRAMC_AO_BASE_ADDRESS
+#define Channel_B_DRAMC_AO_BASE_ADDRESS         0x0
+#undef Channel_C_DRAMC_AO_BASE_ADDRESS
+#define Channel_C_DRAMC_AO_BASE_ADDRESS         0x0
+#undef Channel_D_DRAMC_AO_BASE_ADDRESS
+#define Channel_D_DRAMC_AO_BASE_ADDRESS         0x0
+#undef Channel_A_DRAMC_NAO_BASE_ADDRESS
+#define Channel_A_DRAMC_NAO_BASE_ADDRESS        0x10000
+#undef Channel_B_DRAMC_NAO_BASE_ADDRESS
+#define Channel_B_DRAMC_NAO_BASE_ADDRESS        0x0
+#undef Channel_C_DRAMC_NAO_BASE_ADDRESS
+#define Channel_C_DRAMC_NAO_BASE_ADDRESS        0x0
+#undef Channel_D_DRAMC_NAO_BASE_ADDRESS
+#define Channel_D_DRAMC_NAO_BASE_ADDRESS        0x0
+#undef Channel_A_DDRPHY_AO_BASE_ADDRESS
+#define Channel_A_DDRPHY_AO_BASE_ADDRESS        0x70000
+#undef Channel_B_DDRPHY_AO_BASE_ADDRESS
+#define Channel_B_DDRPHY_AO_BASE_ADDRESS        0x0
+#undef Channel_C_DDRPHY_AO_BASE_ADDRESS
+#define Channel_C_DDRPHY_AO_BASE_ADDRESS        0x0
+#undef Channel_D_DDRPHY_AO_BASE_ADDRESS
+#define Channel_D_DDRPHY_AO_BASE_ADDRESS        0x0
+#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
+#define Channel_A_DDRPHY_NAO_BASE_ADDRESS       0x80000
+#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
+#define Channel_B_DDRPHY_NAO_BASE_ADDRESS       0x0
+#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
+#define Channel_C_DDRPHY_NAO_BASE_ADDRESS       0x0
+#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
+#define Channel_D_DDRPHY_NAO_BASE_ADDRESS       0x0
+#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
+#define Channel_A_DDRPHY_DPM_BASE_ADDRESS       0x100000
+#undef Channel_B_DDRPHY_DPM_BASE_ADDRESS
+#define Channel_B_DDRPHY_DPM_BASE_ADDRESS       0x0
+#endif
+
+#define CHK_INCLUDE_LOCAL_HEADER "\n ==> Include local header but not one at DV SERVER\n\n"
+
+
+#endif // _A60868_REGISTER_H_
diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_top.h b/src/vendorcode/mediatek/mt8195/include/dramc_top.h
new file mode 100644
index 000000000000..d1b7d4f7edf1
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/dramc_top.h
@@ -0,0 +1,666 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2010. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("Media Tek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __DRAMC_TOP_H__
+#define __DRAMC_TOP_H__
+#ifdef FLASH_TOOL_DA
+  #include "sw_types.h"
+#else
+  #include "dramc_typedefs.h"
+#endif
+#include "dramc_common.h"
+
+
+#if __ETT__
+#if (FOR_DV_SIMULATION_USED==0)
+#define DRAM_ADAPTIVE
+#endif
+#endif
+
+#define DRAM_ADAPTIVE
+
+#define DRAM_BASE 0x40000000ULL
+#define DDR_BASE DRAM_BASE
+
+#if __ETT__
+#define dramc_crit		printf
+#define dramc_debug		printf
+#elif __FLASH_TOOL_DA__
+#define dramc_crit		LOGD
+#define dramc_debug		LOGD
+#else
+#define dramc_crit		print
+#define dramc_debug		printf
+#endif
+
+
+#define DRAMC_MAX_CH	4
+#define DRAMC_MAX_RK	2
+#define DRAMC_MR_CNT	4
+#define DRAMC_FREQ_CNT  7
+
+struct mr_info_t {
+	u16 mr_index;
+	u16 mr_value;
+};
+//[FOR_CHROMEOS]
+extern struct dramc_param *dramc_params;
+
+enum DRAM_TYPE {
+	DTYPE_DDR1 = 1,
+	DTYPE_LPDDR2,
+	DTYPE_LPDDR3,
+	DTYPE_PCDDR3,
+	DTYPE_LPDDR4,
+	DTYPE_LPDDR4X,
+	DTYPE_LPDDR4P
+};
+
+int mt_get_dram_type(void);
+int get_dram_channel_support_nr(void);
+int get_dram_channel_nr(void);
+int get_dram_rank_nr(void);
+int get_dram_mr_cnt(void);
+int get_dram_freq_cnt(void);
+#if !__ETT__
+void get_dram_rank_size(u64 dram_rank_size[]);
+void get_dram_freq_step(u32 dram_freq_step[]);
+void set_dram_mr(unsigned int index, unsigned short value);
+unsigned short get_dram_mr(unsigned int index);
+void get_dram_mr_info(struct mr_info_t mr_info[]);
+void reserve_dramc_dummy_read(void);
+#endif
+typedef struct _AC_TIMING_EXTERNAL_T
+{
+    // U 00
+    U32 AC_TIME_EMI_FREQUENCY      :16;
+    U32 AC_TIME_EMI_TRAS           :8;
+    U32 AC_TIME_EMI_TRP            :8;
+
+    // U 01
+    U32 AC_TIME_EMI_TRPAB          :8;
+    U32 AC_TIME_EMI_TRC            :8;
+    U32 AC_TIME_EMI_TRFC           :8;
+    U32 AC_TIME_EMI_TRFCPB         :8;
+
+    // U 02
+    U32 AC_TIME_EMI_TXP            :8;
+    U32 AC_TIME_EMI_TRTP           :8;
+    U32 AC_TIME_EMI_TRCD           :8;
+    U32 AC_TIME_EMI_TWR            :8;
+
+    // U 03
+    U32 AC_TIME_EMI_TWTR           :8;
+    U32 AC_TIME_EMI_TRRD           :8;
+    U32 AC_TIME_EMI_TFAW           :8;
+    U32 AC_TIME_EMI_TRTW_ODT_OFF   :4;
+    U32 AC_TIME_EMI_TRTW_ODT_ON    :4;
+
+    // U 04
+    U32 AC_TIME_EMI_REFCNT         :8; //(REFFRERUN = 0)
+    U32 AC_TIME_EMI_REFCNT_FR_CLK  :8; //(REFFRERUN = 1)
+    U32 AC_TIME_EMI_TXREFCNT       :8;
+    U32 AC_TIME_EMI_TZQCS          :8;
+
+    // U 05
+    U32 AC_TIME_EMI_TRTPD            :8; // LP4/LP3, // Olymp_us new
+    U32 AC_TIME_EMI_TWTPD            :8; // LP4/LP3, // Olymp_us new
+    U32 AC_TIME_EMI_TMRR2W_ODT_OFF   :8; // LP4      // Olymp_us new
+    U32 AC_TIME_EMI_TMRR2W_ODT_ON    :8; // LP4      // Olymp_us new
+
+    // U 06
+    // Byte0
+    U32 AC_TIME_EMI_TRAS_05T          :2;
+    U32 AC_TIME_EMI_TRP_05T           :2;
+    U32 AC_TIME_EMI_TRPAB_05T         :2;
+    U32 AC_TIME_EMI_TRC_05T           :2;
+    // Byte1
+    U32 AC_TIME_EMI_TRFC_05T          :2;
+    U32 AC_TIME_EMI_TRFCPB_05T        :2;
+    U32 AC_TIME_EMI_TXP_05T           :2;
+    U32 AC_TIME_EMI_TRTP_05T          :2;
+    // Byte2
+    U32 AC_TIME_EMI_TRCD_05T          :2;
+    U32 AC_TIME_EMI_TWR_05T           :2;
+    U32 AC_TIME_EMI_TWTR_05T          :2; // Olymp_us modified
+    U32 AC_TIME_EMI_TRRD_05T          :2;
+    // Byte3
+    U32 AC_TIME_EMI_TFAW_05T          :2;
+    U32 AC_TIME_EMI_TRTW_ODT_OFF_05T  :2;
+    U32 AC_TIME_EMI_TRTW_ODT_ON_05T   :2;
+    U32 AC_TIME_EMI_TRTPD_05T         :2; // LP4/LP3 // Olymp_us new
+
+    // U 07
+    // Byte0
+    U32 AC_TIME_EMI_TWTPD_05T           :2; // LP4/LP3 // Olymp_us new
+    U32 AC_TIME_EMI_TMRR2W_ODT_OFF_05T  :2; // Useless, no 0.5T in Olymp_us and Elbr_us
+    U32 AC_TIME_EMI_TMRR2W_ODT_ON_05T   :2; // Useless, no 0.5T in Olymp_us and Elbr_us
+
+
+}AC_TIMING_EXTERNAL_T;
+
+//[FOR_CHROMEOS] Move EMI_SETTINGS to dramc_custom.h
+typedef struct {
+    unsigned int type; /* 0x0000 : Invalid
+                          0x0001 : Discrete DDR1
+                          0x0002 : Discrete LPDDR2
+                          0x0003 : Discrete LPDDR3
+                          0x0004 : Discrete PCDDR3
+                          0x0005 : Discrete LPDDR4
+                          0x0006 : Discrete LPDR4X
+                          0x0101 : MCP(NAND+DDR1)
+                          0x0102 : MCP(NAND+LPDDR2)
+                          0x0103 : MCP(NAND+LPDDR3)
+                          0x0104 : MCP(NAND+PCDDR3)
+                          0x0201 : MCP(eMMC+DDR1)
+                          0x0202 : MCP(eMMC+LPDDR2)
+                          0x0203 : MCP(eMMC+LPDDR3)
+                          0x0204 : MCP(eMMC+PCDDR3)
+                          0x0205 : MCP(eMMC+LPDDR4)
+                          0x0206 : MCP(eMMC+LPDR4X) */
+    unsigned int EMI_CONA_VAL;
+    unsigned int EMI_CONH_VAL;
+    unsigned int EMI_CONK_VAL;
+    unsigned int EMI_CONF_VAL;
+    unsigned int CHN0_EMI_CONA_VAL;
+    unsigned int CHN1_EMI_CONA_VAL;
+    u64 DRAM_RANK_SIZE[4];
+    unsigned int dram_cbt_mode_extern;
+    unsigned int iLPDDR3_MODE_REG_5;
+    unsigned int highest_freq;
+} EMI_SETTINGS;
+
+typedef struct {
+    unsigned int type;
+    unsigned int id_length; /* storage ID lengty */
+    unsigned char ID[16]; /* storage ID */
+    u64 DRAM_RANK_SIZE[4];
+    unsigned int reserved[6];
+    unsigned int iLPDDR3_MODE_REG_5;
+} QVL_LIST_T;
+
+//typedef  EMI_SETTINGS_v15 EMI_SETTINGS;
+#if (FOR_DV_SIMULATION_USED==0)
+void setup_dramc_voltage_by_pmic(void);
+void switch_dramc_voltage_to_auto_mode(void);
+#if ! __ETT__
+uint32 mt_set_emis(uint8* emi, uint32 len, bool use_default); //array of emi setting.
+#endif
+#endif
+
+extern int num_of_emi_records;
+extern EMI_SETTINGS g_default_emi_setting;
+extern unsigned int channel_num_auxadc;
+#if DRAM_AUXADC_CONFIG
+extern unsigned int dram_type_auxadc;
+#endif
+
+#include "x_hal_io.h"
+
+void init_ta2_single_channel(unsigned int);
+#ifdef LAST_DRAMC
+#define LAST_DRAMC_MAGIC_PATTERN 0x19870611
+static void update_last_dramc_info(void);
+void init_ta2_all_channel(void);
+typedef struct {
+    unsigned long long ta2_result_magic;
+    unsigned long long ta2_result_last;
+    unsigned long long ta2_result_past;
+    unsigned long long ta2_result_checksum;
+    unsigned long long reboot_count;
+    volatile unsigned int last_fatal_err_flag;
+    volatile unsigned int fatal_err_flag;
+    volatile unsigned int storage_api_err_flag;
+    volatile unsigned int last_gating_err[4][2]; // [channel][rank]
+    volatile unsigned int gating_err[4][2]; // [channel][rank]
+    unsigned short mr5;
+    unsigned short mr6;
+    unsigned short mr7;
+    unsigned short mr8;
+} LAST_DRAMC_INFO_T;
+#define DEF_LAST_DRAMC LAST_DRAMC_INFO_T
+
+#define OFFSET_DRAM_FATAL_ERR		(31)
+#define OFFSET_DRAM_TA2_ERR		(23)
+#define OFFSET_DRAM_GATING_ERR		(7)
+#define OFFSET_CPU_RW_ERR		(5)
+#define OFFSET_DDR_RSV_MODE_FLOW	(4)
+#define OFFSET_DDR_RSV_MODE_ERR		(3)
+#define OFFSET_EMI_DCS_ERR		(2)
+#define OFFSET_DVFSRC_ERR		(1)
+#define OFFSET_DRS_ERR			(0)
+
+#define ERR_DRAM_TA2_RK0		(1 << 0)
+#define ERR_DRAM_TA2_RK1		(1 << 1)
+
+#define ERR_DRAM_GATING_RK0_R		(1 << 0)
+#define ERR_DRAM_GATING_RK0_F		(1 << 1)
+#define ERR_DRAM_GATING_RK1_R		(1 << 2)
+#define ERR_DRAM_GATING_RK1_F		(1 << 3)
+
+#define ERR_CPU_RW_RK0			(1 << 0)
+#define ERR_CPU_RW_RK1			(1 << 1)
+
+/* 0x1f -> bit[4:0] is for DDR reserve mode */
+#define DDR_RSV_MODE_ERR_MASK		(0x1f)
+
+unsigned int check_last_dram_fatal_exception(void);
+unsigned int check_dram_fatal_exception(void);
+void set_err_code_for_storage_api(void);
+void dram_fatal_set_ta2_err(unsigned int chn, unsigned int err_code);
+void dram_fatal_set_gating_err(unsigned int chn, unsigned int err_code);
+void dram_fatal_set_cpu_rw_err(unsigned int err_code);
+void dram_fatal_set_stberr(unsigned int chn, unsigned int rk, unsigned int err_code);
+
+void dram_fatal_backup_stberr(void);
+void dram_fatal_init_stberr(void);
+void dram_fatal_set_err(unsigned int err_code, unsigned int mask, unsigned int offset);
+#if 0//DRAM_AUXADC_CONFIG
+unsigned int get_ch_num_by_auxadc(void);
+#endif
+
+#define dram_fatal_set_cpu_rw_err(err_code)\
+	do {\
+		dram_fatal_set_err(err_code, 0x3, OFFSET_CPU_RW_ERR);\
+	} while(0)
+
+#define dram_fatal_set_ddr_rsv_mode_err()\
+	do {\
+		dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_ERR);\
+	} while(0)
+
+#define dram_fatal_set_emi_dcs_err()\
+	do {\
+		dram_fatal_set_err(0x1, 0x1, OFFSET_EMI_DCS_ERR);\
+	} while(0)
+
+#define dram_fatal_set_dvfsrc_err()\
+	do {\
+		dram_fatal_set_err(0x1, 0x1, OFFSET_DVFSRC_ERR);\
+	} while(0)
+
+#define dram_fatal_set_drs_err()\
+	do {\
+		dram_fatal_set_err(0x1, 0x1, OFFSET_DRS_ERR);\
+	} while(0)
+
+#define dram_fatal_set_ddr_rsv_mode_flow()\
+	do {\
+		dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_FLOW);\
+	} while(0)
+
+#endif //LAST_DRAMC
+
+typedef enum {
+        KSHU0 = 0,
+        KSHU1,
+	KSHU2,
+	KSHU3,
+	KSHU4,
+	KSHU5,
+	KSHU6,
+	KSHU7,
+	KSHU8,
+	KSHU9,
+} DRAM_KSHU;
+
+typedef enum {
+	TYPE_VDRAM = 0,
+	TYPE_VDDR1,
+	TYPE_VDDR2,
+	TYPE_VDDQ,
+} TYPE_VOLTAGE;
+
+typedef enum {
+	LEVEL_VB = 0,
+	LEVEL_HV,
+	LEVEL_NV,
+	LEVEL_LV,
+} LEVEL_VOLTAGE;
+
+//================================================
+//=============pmic related api for ETT HQA test ==============
+//================================================
+#if (__ETT__ || CFG_DRAM_LOG_TO_STORAGE)
+#define DRAM_HQA
+#endif
+
+#define MAX_VCORE			1193750
+#define MAX_VDRAM			1300000
+#define MAX_VDDQ			1300000
+#define MAX_VMDDR			2000000
+#define MAX_VIO18			1900000
+
+#define UNIT_VCORE			6250
+#define UNIT_VDRAM			5000
+#define UNIT_VDDQ			10000
+#define UNIT_VMDDR			10000
+#define UNIT_VIO18			10000
+#define UNIT_VIO18_STEP			100000
+
+#define HQA_VIO18_HV			1950000
+#define HQA_VCORE_HV_LP4_KSHU0_PL	787500
+#define HQA_VCORE_HV_LP4_KSHU1_PL	737500
+#define HQA_VCORE_HV_LP4_KSHU2_PL	712500
+#define HQA_VCORE_HV_LP4_KSHU3_PL	712500
+#define HQA_VCORE_HV_LP4_KSHU4_PL	687500
+#define HQA_VCORE_HV_LP4_KSHU5_PL	687500
+#define HQA_VCORE_HV_LP4_KSHU6_PL	687500
+#define HQA_VCORE_HV_LP4_KSHU0_ETT	787500
+#define HQA_VCORE_HV_LP4_KSHU1_ETT	787500
+#define HQA_VCORE_HV_LP4_KSHU2_ETT	787500
+#define HQA_VCORE_HV_LP4_KSHU3_ETT	787500
+#define HQA_VCORE_HV_LP4_KSHU4_ETT	787500
+#define HQA_VCORE_HV_LP4_KSHU5_ETT	787500
+#define HQA_VCORE_HV_LP4_KSHU6_ETT	787500
+#define HQA_VDRAM_HV_LP4		1170000
+#define HQA_VDDQ_HV_LP4			650000
+#define HQA_VMDDR_HV_LP4		790000
+
+#if defined(MTK_AGING_FLAVOR_LOAD)
+#define HQA_VIO18_NV			1730000
+#else
+#define HQA_VIO18_NV			1800000
+#endif
+#define HQA_VCORE_NV_LP4_KSHU0_PL	750000
+#define HQA_VCORE_NV_LP4_KSHU1_PL	700000
+#define HQA_VCORE_NV_LP4_KSHU2_PL	675000
+#define HQA_VCORE_NV_LP4_KSHU3_PL	675000
+#define HQA_VCORE_NV_LP4_KSHU4_PL	650000
+#define HQA_VCORE_NV_LP4_KSHU5_PL	650000
+#define HQA_VCORE_NV_LP4_KSHU6_PL	650000
+#define HQA_VCORE_NV_LP4_KSHU0_ETT	750000
+#define HQA_VCORE_NV_LP4_KSHU1_ETT	700000
+#define HQA_VCORE_NV_LP4_KSHU2_ETT	675000
+#define HQA_VCORE_NV_LP4_KSHU3_ETT	675000
+#define HQA_VCORE_NV_LP4_KSHU4_ETT	650000
+#define HQA_VCORE_NV_LP4_KSHU5_ETT	650000
+#define HQA_VCORE_NV_LP4_KSHU6_ETT	650000
+#if defined(MTK_AGING_FLAVOR_LOAD)
+#define HQA_VDRAM_NV_LP4		1060000
+#define HQA_VDDQ_NV_LP4			570000
+#define HQA_VMDDR_NV_LP4		710000
+#else
+#define HQA_VDRAM_NV_LP4		1125000
+#define HQA_VDDQ_NV_LP4			600000
+#define HQA_VMDDR_NV_LP4		750000
+#endif
+
+#define HQA_VIO18_LV			1730000
+#define HQA_VCORE_LV_LP4_KSHU0_PL	712500
+#define HQA_VCORE_LV_LP4_KSHU1_PL	662500
+#define HQA_VCORE_LV_LP4_KSHU2_PL	637500
+#define HQA_VCORE_LV_LP4_KSHU3_PL	637500
+#define HQA_VCORE_LV_LP4_KSHU4_PL	612500
+#define HQA_VCORE_LV_LP4_KSHU5_PL	612500
+#define HQA_VCORE_LV_LP4_KSHU6_PL	612500
+#define HQA_VCORE_LV_LP4_KSHU0_ETT	712500
+#define HQA_VCORE_LV_LP4_KSHU1_ETT	612500
+#define HQA_VCORE_LV_LP4_KSHU2_ETT	568750
+#define HQA_VCORE_LV_LP4_KSHU3_ETT	568750
+#define HQA_VCORE_LV_LP4_KSHU4_ETT	518750
+#define HQA_VCORE_LV_LP4_KSHU5_ETT	518750
+#define HQA_VCORE_LV_LP4_KSHU6_ETT	518750
+#define HQA_VDRAM_LV_LP4		1060000
+#define HQA_VDDQ_LV_LP4			570000
+#define HQA_VMDDR_LV_LP4		710000
+
+#define  _SEL_PREFIX_SHU_PL(type,vol,dtype,shu)		HQA_##type##_##vol##_##dtype##_##shu##_PL
+#define  _SEL_PREFIX_SHU_ETT(type,vol,dtype,shu)	HQA_##type##_##vol##_##dtype##_##shu##_ETT
+#define  _SEL_PREFIX(type,vol,dtype)			HQA_##type##_##vol##_##dtype
+#define  _SEL_VIO18(vol)				HQA_VIO18_##vol
+
+#define STD_VIO18				_SEL_VIO18(NV)
+#define STD_VCORE(dtype,shu)	_SEL_PREFIX_SHU_PL(VCORE,NV,dtype,shu)
+#define STD_VDRAM(dtype)		_SEL_PREFIX(VDRAM,NV,dtype)
+#define STD_VDDQ				_SEL_PREFIX(VDDQ,NV,LP4)
+#define STD_VMDDR				_SEL_PREFIX(VMDDR,NV,LP4)
+
+#if defined(MTK_AGING_FLAVOR_LOAD)
+#define DRAM_HQA
+#endif
+
+#ifdef DRAM_HQA
+//#define HVCORE_HVDRAM
+#if defined(MTK_AGING_FLAVOR_LOAD)
+#define LVCORE_LVDRAM
+#else
+#define NVCORE_NVDRAM
+//#define LVCORE_LVDRAM
+//#define HVCORE_HVDRAM
+#endif
+
+#if defined(HVCORE_HVDRAM)
+	#define HQA_VCORE(dtype,shu)	_SEL_PREFIX_SHU_PL(VCORE,HV,dtype,shu)
+	#define HQA_VDRAM(dtype)		_SEL_PREFIX(VDRAM,HV,dtype)
+	#define HQA_VDDQ				_SEL_PREFIX(VDDQ,HV,LP4)
+	#define HQA_VMDDR				_SEL_PREFIX(VMDDR,HV,LP4)
+	#define HQA_VIO18				_SEL_VIO18(HV)
+#elif defined(NVCORE_NVDRAM)
+	#define HQA_VCORE(dtype,shu)	_SEL_PREFIX_SHU_PL(VCORE,NV,dtype,shu)
+	#define HQA_VDRAM(dtype)		_SEL_PREFIX(VDRAM,NV,dtype)
+	#define HQA_VDDQ				_SEL_PREFIX(VDDQ,NV,LP4)
+	#define HQA_VMDDR				_SEL_PREFIX(VMDDR,NV,LP4)
+	#define HQA_VIO18				_SEL_VIO18(NV)
+#elif defined(LVCORE_LVDRAM)
+	#define HQA_VCORE(dtype,shu)	_SEL_PREFIX_SHU_PL(VCORE,LV,dtype,shu)
+	#define HQA_VDRAM(dtype)		_SEL_PREFIX(VDRAM,LV,dtype)
+	#define HQA_VDDQ				_SEL_PREFIX(VDDQ,LV,LP4)
+	#define HQA_VMDDR				_SEL_PREFIX(VMDDR,LV,LP4)
+	#define HQA_VIO18				_SEL_VIO18(LV)
+#elif defined(HVCORE_LVDRAM)
+	#define HQA_VCORE(dtype,shu)	_SEL_PREFIX_SHU_PL(VCORE,HV,dtype,shu)
+	#define HQA_VDRAM(dtype)		_SEL_PREFIX(VDRAM,LV,dtype)
+	#define HQA_VDDQ				_SEL_PREFIX(VDDQ,LV,LP4)
+	#define HQA_VMDDR				_SEL_PREFIX(VMDDR,LV,LP4)
+	#define HQA_VIO18				_SEL_VIO18(LV)
+#elif defined(LVCORE_HVDRAM)
+	#define HQA_VCORE(dtype,shu)	_SEL_PREFIX_SHU_PL(VCORE,LV,dtype,shu)
+	#define HQA_VDRAM(dtype)		_SEL_PREFIX(VDRAM,HV,dtype)
+	#define HQA_VDDQ				_SEL_PREFIX(VDDQ,HV,LP4)
+	#define HQA_VMDDR				_SEL_PREFIX(VMDDR,HV,LP4)
+	#define HQA_VIO18				_SEL_VIO18(HV)
+#else
+	#error "Please set HQA voltage type"
+#endif
+
+#define SEL_PREFIX_VCORE(dtype,shu)	HQA_VCORE(dtype,shu)
+#define SEL_PREFIX_VDRAM(dtype)		HQA_VDRAM(dtype)
+#define SEL_PREFIX_VDDQ			HQA_VDDQ
+#define SEL_PREFIX_VMDDR		HQA_VMDDR
+#define SEL_VIO18			HQA_VIO18
+#else
+
+#if defined(MTK_AGING_FLAVOR_LOAD)
+//#define VCORE_BIN
+#endif
+#if !__ETT__
+//#define VCORE_BIN
+#endif
+#define SEL_PREFIX_VCORE(dtype,shu)	STD_VCORE(dtype,shu)
+#define SEL_PREFIX_VDRAM(dtype)		STD_VDRAM(dtype)
+#define SEL_PREFIX_VDDQ			STD_VDDQ
+#define SEL_PREFIX_VMDDR		STD_VMDDR
+#define SEL_VIO18			STD_VIO18
+#endif // #define DRAM_HQA
+
+#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
+
+#define PART_DRAM_DATA_SIZE	0x100000
+
+#define	DRAM_CALIBRATION_DATA_MAGIC	0x9502
+
+typedef struct _DRAM_CALIBRATION_HEADER_T
+{
+	u32	pl_version;
+	u16	magic_number;
+	u32	calib_err_code;
+} DRAM_CALIBRATION_HEADER_T;
+
+typedef struct _DRAM_CALIBRATION_MRR_DATA_T
+{
+	u16	checksum;
+	u16 emi_checksum;
+	DRAM_INFO_BY_MRR_T DramInfo;
+} DRAM_CALIBRATION_MRR_DATA_T;
+
+typedef struct _DRAM_CALIBRATION_SHU_DATA_T
+{
+	u16	checksum;
+	u32	calib_err_code;
+	SAVE_TIME_FOR_CALIBRATION_T	calibration_data;
+} DRAM_CALIBRATION_SHU_DATA_T;
+
+typedef struct _DRAM_CALIBRATION_DATA_T
+{
+	DRAM_CALIBRATION_HEADER_T header;
+	DRAM_CALIBRATION_MRR_DATA_T mrr_info;
+	DRAM_CALIBRATION_SHU_DATA_T	data[DRAM_DFS_SRAM_MAX];
+} DRAM_CALIBRATION_DATA_T;
+
+/*
+ * g_dram_storage_api_err_code:
+ * 	bit[0:3] -> read api
+ * 	bit[4:7] -> write api
+ * 	bit[8:11] -> clean api
+ * 	bit[12:12] -> data formatted due to fatal exception
+ */
+#define ERR_NULL_POINTER	(0x1)
+#define ERR_MAGIC_NUMBER	(0x2)
+#define ERR_CHECKSUM		(0x3)
+#define ERR_PL_UPDATED		(0x4)
+#define ERR_BLKDEV_NOT_FOUND	(0x5)
+#define ERR_BLKDEV_READ_FAIL	(0x6)
+#define ERR_BLKDEV_WRITE_FAIL	(0x7)
+#define ERR_BLKDEV_NO_PART	(0x8)
+
+#define ERR_DATA_FORMATTED_OFFSET	(12)
+
+typedef enum {
+	DRAM_STORAGE_API_READ = 0,
+	DRAM_STORAGE_API_WRITE,
+	DRAM_STORAGE_API_CLEAN,
+} DRAM_STORAGE_API_TPYE;
+
+extern u32 g_dram_storage_api_err_code;
+#define SET_DRAM_STORAGE_API_ERR(err_type, api_type) \
+do {\
+	g_dram_storage_api_err_code |= (err_type << (api_type * 4));\
+} while(0)
+
+#define SET_DATA_FORMATTED_STORAGE_API_ERR() \
+do {\
+	g_dram_storage_api_err_code |= (1 << ERR_DATA_FORMATTED_OFFSET);\
+} while(0)
+
+int read_offline_dram_calibration_data(DRAM_DFS_SRAM_SHU_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData);
+int write_offline_dram_calibration_data(DRAM_DFS_SRAM_SHU_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData);
+int clean_dram_calibration_data(void);
+
+void dram_fatal_exception_detection_start(void);
+void dram_fatal_exception_detection_end(void);
+
+#define CBT_VREF_OFFSET			2
+#define WRITE_LEVELING_OFFSET		5
+#define GATING_START_OFFSET		0
+#define GATING_PASS_WIN_OFFSET		3
+#define RX_WIN_PERBIT_OFFSET		5
+#define RX_WIN_PERBIT_VREF_OFFSET	4
+#define TX_WIN_PERBIT_OFFSET		5
+#define TX_WIN_PERBIT_VREF_OFFSET	4
+#define RX_DATLAT_OFFSET		1
+#define RX_WIN_HIGH_SPEED_TH		10
+#define RX_WIN_LOW_SPEED_TH		100
+#define TX_WIN_TH			12
+
+#endif
+
+#if defined(SLT)
+
+#define SLT_ERR_NO_DATA		(-1)
+#define SLT_ERR_NO_DEV		(-2)
+#define SLT_ERR_NO_ADDR		(-3)
+#define SLT_ERR_WRITE_FAIL	(-4)
+#define SLT_ERR_READ_FAIL	(-5)
+
+typedef struct _DRAM_SLT_HEADER_T
+{
+	u32 pl_version;
+	int stage_status;
+} DRAM_SLT_HEADER_T;
+
+typedef struct _DRAM_SLT_DATA_T
+{
+	DRAM_SLT_HEADER_T header;
+	u32 test_result[10];
+} DRAM_SLT_DATA_T;
+
+int read_slt_data(DRAM_SLT_DATA_T *data);
+int write_slt_data(DRAM_SLT_DATA_T *data);
+int clean_slt_data(void);
+
+#endif
+
+unsigned long long get_dram_size(void);
+
+typedef struct {
+	unsigned long long full_sys_addr;
+	unsigned int addr;
+	unsigned int row;
+	unsigned int col;
+	unsigned char ch;
+	unsigned char rk;
+	unsigned char bk;
+	unsigned char dummy;
+} dram_addr_t;
+
+unsigned int get_dramc_addr(dram_addr_t *dram_addr, unsigned int offset);
+unsigned int get_dummy_read_addr(dram_addr_t *dram_addr);
+unsigned int is_discrete_lpddr4(void);
+unsigned int DRAM_MRR(int MRR_num);
+
+void dram_auto_detection(void);
+
+int mt_get_freq_setting(DRAMC_CTX_T *p);
+unsigned int dramc_get_vmdd_voltage(unsigned int ddr_type);
+unsigned int dramc_get_vmddq_voltage(unsigned int ddr_type);
+unsigned int dramc_set_vmdd_voltage(unsigned int ddr_type, unsigned int vdram);
+unsigned int dramc_set_vmddq_voltage(unsigned int ddr_type, unsigned int vddq);
+
+void release_dram(void);
+
+#endif /* __DRAMC_TOP_H__ */
diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_typedefs.h b/src/vendorcode/mediatek/mt8195/include/dramc_typedefs.h
new file mode 100644
index 000000000000..8c6945e2caf2
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/dramc_typedefs.h
@@ -0,0 +1,114 @@
+#ifndef _DRAMC_TYPEDEFS_H_
+#define _DRAMC_TYPEDEFS_H_
+
+#include <stdint.h>
+
+#define IMPORT  EXTERN
+#ifndef __cplusplus
+  #define EXTERN  extern
+#else
+  #define EXTERN  extern "C"
+#endif
+#define LOCAL     static
+#define GLOBAL
+#define EXPORT    GLOBAL
+
+
+#define EQ        ==
+#define NEQ       !=
+#define AND       &&
+#define OR        ||
+#define XOR(A,B)  ((!(A) AND (B)) OR ((A) AND !(B)))
+
+#ifndef FALSE
+#define FALSE	0
+#endif
+
+#ifndef TRUE
+#define TRUE	1
+#endif
+
+#if 0
+#ifndef NULL
+#define NULL	0
+#endif
+#endif
+
+
+#define ASSERT(expr) \
+    do{ if(!(expr)){while(1);} }while(0)
+#if 0 //[FOR_CHROMEOS]
+#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+#define ARRAY_SIZE(x)       (sizeof(x) / sizeof((x)[0]))
+#endif
+
+#ifndef BOOL
+typedef unsigned char  BOOL;
+#endif
+
+typedef unsigned long ulong;
+typedef unsigned char uchar;
+typedef unsigned int uint;
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+typedef signed int intx;
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long uint32;
+typedef unsigned int uintx;
+
+typedef signed char				S8;
+typedef signed short			S16;
+typedef signed int				S32;
+typedef signed long long		S64;
+
+typedef unsigned char			U8;
+typedef unsigned short			U16;
+typedef unsigned int			U32;
+typedef unsigned long long		U64;
+
+typedef unsigned char			US8;
+typedef unsigned short			US16;
+typedef unsigned int			US32;
+typedef unsigned long long		US64;
+
+typedef unsigned char			u8;
+typedef unsigned short			u16;
+typedef unsigned int			u32;
+typedef unsigned long long		u64;
+
+typedef unsigned char			UINT8;
+typedef unsigned short			UINT16;
+typedef unsigned int			UINT32;
+typedef unsigned short			USHORT;
+typedef signed char				INT8;
+typedef signed short			INT16;
+typedef signed int				INT32;
+
+typedef volatile signed char	*P_S8;
+typedef volatile signed short	*P_S16;
+typedef volatile signed int		*P_S32;
+
+typedef long					LONG;
+typedef unsigned char			UBYTE;
+typedef short					SHORT;
+
+typedef unsigned int			*UINT32P;
+typedef volatile unsigned short	*UINT16P;
+typedef volatile unsigned char	*UINT8P;
+typedef unsigned char			*U8P;
+
+typedef volatile unsigned char	*P_U8;
+typedef volatile unsigned short	*P_U16;
+typedef volatile unsigned int	*P_U32;
+typedef unsigned long long		*P_U64;
+typedef signed long long		*P_S64;
+
+typedef unsigned int			uint;
+
+typedef void					VOID;
+typedef unsigned char			BYTE;
+typedef float					FLOAT;
+
+#endif
diff --git a/src/vendorcode/mediatek/mt8195/include/emi.h b/src/vendorcode/mediatek/mt8195/include/emi.h
new file mode 100644
index 000000000000..e7bd504fba48
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/emi.h
@@ -0,0 +1,113 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2010. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("Media Tek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef __EMI_H__
+#define __EMI_H__
+
+#include <dramc_top.h>
+
+#if __ETT__
+#define emi_log	printf
+#elif __FLASH_TOOL_DA__
+#define emi_log	LOGD
+#else
+#define emi_log	print
+#endif
+
+struct isu_info_t {
+	unsigned int buf_size;
+	unsigned long long buf_addr;
+	unsigned long long ver_addr;
+	unsigned long long con_addr;
+};
+
+#define EMI_ISU_BUF_SIZE	0x800000
+#define LAST_EMI_MAGIC_PATTERN 0x19870611
+typedef struct {
+	unsigned int isu_magic;
+	unsigned int isu_ctrl;
+	unsigned int isu_dram_type;
+	unsigned int isu_diff_us;
+	unsigned int isu_buf_l;
+	unsigned int isu_buf_h;
+	unsigned int isu_version;
+	unsigned int snst_last;
+	unsigned int snst_past;
+	unsigned int os_flag_sspm;
+	unsigned int os_flag_ap;
+} LAST_EMI_INFO_T;
+#define DEF_LAST_EMI LAST_EMI_INFO_T
+
+typedef struct {
+	unsigned int dram_type;
+	unsigned int ch_num;
+	unsigned int rk_num;
+	unsigned int bank_width[DRAMC_MAX_RK];
+	unsigned int row_width[DRAMC_MAX_RK];
+	unsigned int col_width[DRAMC_MAX_RK];
+	U64 rank_size[DRAMC_MAX_RK];
+} EMI_INFO_T;
+
+void emi_init(void);
+void emi_init2(void);
+void clr_emi_mpu_prot(void);
+void dis_emi_apb_prot(void);
+int get_row_width_by_emi(unsigned int rank);
+int get_channel_nr_by_emi(void);
+int get_rank_nr_by_emi(void);
+void get_rank_size_by_emi(unsigned long long dram_rank_size[DRAMC_MAX_RK]);
+void set_cen_emi_cona(unsigned int cona_val);
+void set_cen_emi_conf(unsigned int conf_val);
+void set_cen_emi_conh(unsigned int conh_val);
+void set_chn_emi_cona(unsigned int cona_val);
+void set_chn_emi_conc(unsigned int conc_val);
+unsigned int get_cen_emi_cona(void);
+unsigned int get_chn_emi_cona(void);
+void enable_infra_emi_broadcast(unsigned int enable);
+void phy_addr_to_dram_addr(dram_addr_t *dram_addr, unsigned long long phy_addr);
+unsigned int set_emi_before_rank1_mem_test(void);
+void restore_emi_after_rank1_mem_test(void);
+void get_emi_isu_info(struct isu_info_t *isu_info_ptr);
+void reserve_emi_isu_buf(void);
+void reserve_emi_mbist_buf(void);
+void record_emi_snst(void);
+unsigned long long platform_memory_size(void);
+int update_emi_setting(EMI_SETTINGS *default_emi_setting, EMI_INFO_T *emi_info);
+//int mt_mem_init();
+
+#endif /* __EMI_H__ */
+
diff --git a/src/vendorcode/mediatek/mt8195/include/emi_hw.h b/src/vendorcode/mediatek/mt8195/include/emi_hw.h
new file mode 100644
index 000000000000..e75a8ce49ff4
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/emi_hw.h
@@ -0,0 +1,246 @@
+#ifndef __EMI_HW_H__
+#define __EMI_HW_H__
+
+/* from EMI golden setting */
+//#define EMI_MP_SETTING
+#define REAL_CHIP_EMI_GOLDEN_SETTING
+#define INFRA_DRAMC_REG_CONFIG      (0x100010b4)
+#define INFRACFG_AO_MEM_BASE        (0x10002000)
+#define SUB_INFRACFG_AO_MEM_BASE    (0x1030E000)
+#define MCUSYS_PAR_WRAP_BASE        (0x0C530000)
+
+#define EMI_BASE                    (0x10219000)
+#define SUB_EMI_BASE                (0x1021D000)
+#define EMI_MPU_BASE                (0x10226000)
+#define SUB_EMI_MPU_BASE            (0x10225000)
+#define CHN0_EMI_BASE               (0x10235000)
+#define CHN1_EMI_BASE               (0x10245000)
+
+#define EMI_CONA                    (EMI_BASE+0x000)
+#define EMI_CONB                    (EMI_BASE+0x008)
+#define EMI_CONC                    (EMI_BASE+0x010)
+#define EMI_COND                    (EMI_BASE+0x018)
+#define EMI_CONE                    (EMI_BASE+0x020)
+#define EMI_CONF                    (EMI_BASE+0x028)
+#define EMI_CONG                    (EMI_BASE+0x030)
+#define EMI_CONH                    (EMI_BASE+0x038)
+#define EMI_CONH_2ND                (EMI_BASE+0x03C)
+#define EMI_CONI                    (EMI_BASE+0x040)
+#define EMI_CONJ                    (EMI_BASE+0x048)
+#define EMI_CONK                    (EMI_BASE+0x050)
+#define EMI_CONM                    (EMI_BASE+0x060)
+#define EMI_CONN                    (EMI_BASE+0x068)
+#define EMI_CONO                    (EMI_BASE+0x070)
+#define EMI_MDCT                    (EMI_BASE+0x078)
+#define EMI_MDCT_2ND                (EMI_BASE+0x07C)
+#define EMI_IOCL                    (EMI_BASE+0x0D0)
+#define EMI_IOCL_2ND                (EMI_BASE+0x0D4)
+#define EMI_IOCM                    (EMI_BASE+0x0D8)
+#define EMI_IOCM_2ND                (EMI_BASE+0x0DC)
+#define EMI_TESTB                   (EMI_BASE+0x0E8)
+#define EMI_TESTC                   (EMI_BASE+0x0F0)
+#define EMI_TESTD                   (EMI_BASE+0x0F8)
+#define EMI_ARBA                    (EMI_BASE+0x100)
+#define EMI_ARBB                    (EMI_BASE+0x108)
+#define EMI_ARBC                    (EMI_BASE+0x110)
+#define EMI_ARBD                    (EMI_BASE+0x118)
+#define EMI_ARBE                    (EMI_BASE+0x120)
+#define EMI_ARBF                    (EMI_BASE+0x128)
+#define EMI_ARBG                    (EMI_BASE+0x130)
+#define EMI_ARBH                    (EMI_BASE+0x138)
+#define EMI_ARBI                    (EMI_BASE+0x140)
+#define EMI_ARBI_2ND                (EMI_BASE+0x144)
+#define EMI_ARBJ_2ND                (EMI_BASE+0x14C)
+#define EMI_ARBK                    (EMI_BASE+0x150)
+#define EMI_ARBK_2ND                (EMI_BASE+0x154)
+#define EMI_SLCT                    (EMI_BASE+0x158)
+#define EMI_MPUD0_ST                (EMI_BASE+0x160)
+#define EMI_MPUD1_ST                (EMI_BASE+0x164)
+#define EMI_MPUD2_ST                (EMI_BASE+0x168)
+#define EMI_MPUD3_ST                (EMI_BASE+0x16C)
+#define EMI_MPUD4_ST                (EMI_BASE+0x170)
+#define EMI_MPUD5_ST                (EMI_BASE+0x174)
+#define EMI_MPUD6_ST                (EMI_BASE+0x178)
+#define EMI_MPUD7_ST                (EMI_BASE+0x17C)
+#define EMI_MPUD8_ST                (EMI_BASE+0x180)
+#define EMI_MPUD9_ST                (EMI_BASE+0x184)
+#define EMI_MPUD10_ST               (EMI_BASE+0x188)
+#define EMI_MPUD11_ST               (EMI_BASE+0x18C)
+#define EMI_MPUD12_ST               (EMI_BASE+0x190)
+#define EMI_MPUD13_ST               (EMI_BASE+0x194)
+#define EMI_MPUD14_ST               (EMI_BASE+0x198)
+#define EMI_MPUD15_ST               (EMI_BASE+0x19C)
+#define EMI_MPUD16_ST               (EMI_BASE+0x1A0)
+#define EMI_MPUD17_ST               (EMI_BASE+0x1A4)
+#define EMI_MPUD18_ST               (EMI_BASE+0x1A8)
+#define EMI_MPUD19_ST               (EMI_BASE+0x1AC)
+#define EMI_MPUD20_ST               (EMI_BASE+0x1B0)
+#define EMI_MPUD21_ST               (EMI_BASE+0x1B4)
+#define EMI_MPUD22_ST               (EMI_BASE+0x1B8)
+#define EMI_MPUD23_ST               (EMI_BASE+0x1BC)
+#define EMI_MPUD24_ST               (EMI_BASE+0x1C0)
+#define EMI_MPUD25_ST               (EMI_BASE+0x1C4)
+#define EMI_MPUD26_ST               (EMI_BASE+0x1C8)
+#define EMI_MPUD27_ST               (EMI_BASE+0x1CC)
+#define EMI_MPUD28_ST               (EMI_BASE+0x1D0)
+#define EMI_MPUD29_ST               (EMI_BASE+0x1D4)
+#define EMI_MPUD30_ST               (EMI_BASE+0x1D8)
+#define EMI_MPUD31_ST               (EMI_BASE+0x1DC)
+#define EMI_MPUS                    (EMI_BASE+0x1F0)
+#define EMI_MPUT                    (EMI_BASE+0x1F8)
+#define EMI_MPUT_2ND                (EMI_BASE+0x1FC)
+#define EMI_D0_ST2                  (EMI_BASE+0x200)
+#define EMI_D1_ST2                  (EMI_BASE+0x204)
+#define EMI_D2_ST2                  (EMI_BASE+0x208)
+#define EMI_D3_ST2                  (EMI_BASE+0x20C)
+#define EMI_D4_ST2                  (EMI_BASE+0x210)
+#define EMI_D5_ST2                  (EMI_BASE+0x214)
+#define EMI_D6_ST2                  (EMI_BASE+0x218)
+#define EMI_D7_ST2                  (EMI_BASE+0x21C)
+#define EMI_D8_ST2                  (EMI_BASE+0x220)
+#define EMI_D9_ST2                  (EMI_BASE+0x224)
+#define EMI_D10_ST2                 (EMI_BASE+0x228)
+#define EMI_D11_ST2                 (EMI_BASE+0x22C)
+#define EMI_D12_ST2                 (EMI_BASE+0x230)
+#define EMI_D13_ST2                 (EMI_BASE+0x234)
+#define EMI_D14_ST2                 (EMI_BASE+0x238)
+#define EMI_D15_ST2                 (EMI_BASE+0x23C)
+#define EMI_D16_ST2                 (EMI_BASE+0x240)
+#define EMI_D17_ST2                 (EMI_BASE+0x244)
+#define EMI_D18_ST2                 (EMI_BASE+0x248)
+#define EMI_D19_ST2                 (EMI_BASE+0x24C)
+#define EMI_D20_ST2                 (EMI_BASE+0x250)
+#define EMI_D21_ST2                 (EMI_BASE+0x254)
+#define EMI_D22_ST2                 (EMI_BASE+0x258)
+#define EMI_D23_ST2                 (EMI_BASE+0x25C)
+#define EMI_D24_ST2                 (EMI_BASE+0x260)
+#define EMI_D25_ST2                 (EMI_BASE+0x264)
+#define EMI_D26_ST2                 (EMI_BASE+0x268)
+#define EMI_D27_ST2                 (EMI_BASE+0x26C)
+#define EMI_D28_ST2                 (EMI_BASE+0x270)
+#define EMI_D29_ST2                 (EMI_BASE+0x274)
+#define EMI_D30_ST2                 (EMI_BASE+0x278)
+#define EMI_D31_ST2                 (EMI_BASE+0x27C)
+#define EMI_BMEN                    (EMI_BASE+0x400)
+#define EMI_BSTP                    (EMI_BASE+0x404)
+#define EMI_BCNT                    (EMI_BASE+0x408)
+#define EMI_TACT                    (EMI_BASE+0x410)
+#define EMI_TSCT                    (EMI_BASE+0x418)
+#define EMI_WACT                    (EMI_BASE+0x420)
+#define EMI_WSCT                    (EMI_BASE+0x428)
+#define EMI_BACT                    (EMI_BASE+0x430)
+#define EMI_BSCT                    (EMI_BASE+0x438)
+#define EMI_MSEL                    (EMI_BASE+0x440)
+#define EMI_TSCT2                   (EMI_BASE+0x448)
+#define EMI_TSCT3                   (EMI_BASE+0x450)
+#define EMI_WSCT2                   (EMI_BASE+0x458)
+#define EMI_WSCT3                   (EMI_BASE+0x460)
+#define EMI_WSCT4                   (EMI_BASE+0x464)
+#define EMI_MSEL2                   (EMI_BASE+0x468)
+#define EMI_MSEL3                   (EMI_BASE+0x470)
+#define EMI_MSEL4                   (EMI_BASE+0x478)
+#define EMI_MSEL5                   (EMI_BASE+0x480)
+#define EMI_MSEL6                   (EMI_BASE+0x488)
+#define EMI_MSEL7                   (EMI_BASE+0x490)
+#define EMI_MSEL8                   (EMI_BASE+0x498)
+#define EMI_MSEL9                   (EMI_BASE+0x4A0)
+#define EMI_MSEL10                  (EMI_BASE+0x4A8)
+#define EMI_BMID0                   (EMI_BASE+0x4B0)
+#define EMI_BMID1                   (EMI_BASE+0x4B4)
+#define EMI_BMID2                   (EMI_BASE+0x4B8)
+#define EMI_BMID3                   (EMI_BASE+0x4BC)
+#define EMI_BMID4                   (EMI_BASE+0x4C0)
+#define EMI_BMID5                   (EMI_BASE+0x4C4)
+#define EMI_BMID6                   (EMI_BASE+0x4C8)
+#define EMI_BMID7                   (EMI_BASE+0x4CC)
+#define EMI_BMID8                   (EMI_BASE+0x4D0)
+#define EMI_BMID9                   (EMI_BASE+0x4D4)
+#define EMI_BMID10                  (EMI_BASE+0x4D8)
+#define EMI_BMEN1                   (EMI_BASE+0x4E0)
+#define EMI_BMEN2                   (EMI_BASE+0x4E8)
+#define EMI_BMRW0                   (EMI_BASE+0x4F8)
+#define EMI_BMRW1                   (EMI_BASE+0x4FC)
+#define EMI_TTYPE1                  (EMI_BASE+0x500)
+#define EMI_TTYPE2                  (EMI_BASE+0x508)
+#define EMI_TTYPE3                  (EMI_BASE+0x510)
+#define EMI_TTYPE4                  (EMI_BASE+0x518)
+#define EMI_TTYPE5                  (EMI_BASE+0x520)
+#define EMI_TTYPE6                  (EMI_BASE+0x528)
+#define EMI_TTYPE7                  (EMI_BASE+0x530)
+#define EMI_TTYPE8                  (EMI_BASE+0x538)
+#define EMI_TTYPE9                  (EMI_BASE+0x540)
+#define EMI_TTYPE10                 (EMI_BASE+0x548)
+#define EMI_TTYPE11                 (EMI_BASE+0x550)
+#define EMI_TTYPE12                 (EMI_BASE+0x558)
+#define EMI_TTYPE13                 (EMI_BASE+0x560)
+#define EMI_TTYPE14                 (EMI_BASE+0x568)
+#define EMI_TTYPE15                 (EMI_BASE+0x570)
+#define EMI_TTYPE16                 (EMI_BASE+0x578)
+#define EMI_TTYPE17                 (EMI_BASE+0x580)
+#define EMI_TTYPE18                 (EMI_BASE+0x588)
+#define EMI_TTYPE19                 (EMI_BASE+0x590)
+#define EMI_TTYPE20                 (EMI_BASE+0x598)
+#define EMI_TTYPE21                 (EMI_BASE+0x5A0)
+#define EMI_BWCT0                   (EMI_BASE+0x5B0)
+#define EMI_BWCT1                   (EMI_BASE+0x5B4)
+#define EMI_BWCT2                   (EMI_BASE+0x5B8)
+#define EMI_BWCT3                   (EMI_BASE+0x5BC)
+#define EMI_BWCT4                   (EMI_BASE+0x5C0)
+#define EMI_BWST0                   (EMI_BASE+0x5C4)
+#define EMI_BWST1                   (EMI_BASE+0x5C8)
+#define EMI_EX_CON                  (EMI_BASE+0x5D0)
+#define EMI_EX_ST0                  (EMI_BASE+0x5D4)
+#define EMI_EX_ST1                  (EMI_BASE+0x5D8)
+#define EMI_EX_ST2                  (EMI_BASE+0x5DC)
+#define EMI_WP_ADR                  (EMI_BASE+0x5E0)
+#define EMI_WP_ADR_2ND              (EMI_BASE+0x5E4)
+#define EMI_WP_CTRL                 (EMI_BASE+0x5E8)
+#define EMI_CHKER                   (EMI_BASE+0x5F0)
+#define EMI_CHKER_TYPE              (EMI_BASE+0x5F4)
+#define EMI_CHKER_ADR               (EMI_BASE+0x5F8)
+#define EMI_CHKER_ADR_2ND           (EMI_BASE+0x5FC)
+#define EMI_BWCT0_2ND               (EMI_BASE+0x6A0)
+#define EMI_LTCT0_2ND               (EMI_BASE+0x750)
+#define EMI_LTCT1_2ND               (EMI_BASE+0x754)
+#define EMI_LTCT2_2ND               (EMI_BASE+0x758)
+#define EMI_LTCT3_2ND               (EMI_BASE+0x75C)
+#define EMI_BWCT0_3RD               (EMI_BASE+0x770)
+#define EMI_BWCT0_4TH               (EMI_BASE+0x780)
+#define EMI_BWCT0_5TH               (EMI_BASE+0x7B0)
+#define EMI_BWCT0_6TH               (EMI_BASE+0x7C8)
+#define EMI_SNST                    (EMI_BASE+0x7F8)
+#define EMI_SLVA                    (EMI_BASE+0x800)
+#define EMI_AXI_BIST_ADR0           (EMI_BASE+0x98c)
+#define EMI_AXI_BIST_ADR1           (EMI_BASE+0x990)
+#define EMI_AXI_BIST_ADR2           (EMI_BASE+0x994)
+
+#define EMI_MPU_CTRL                (EMI_MPU_BASE+0x000)
+#define EMI_MPU_DBG                 (EMI_MPU_BASE+0x004)
+#define EMI_MPU_SA0                 (EMI_MPU_BASE+0x100)
+#define EMI_MPU_EA0                 (EMI_MPU_BASE+0x200)
+#define EMI_MPU_SA(region)          (EMI_MPU_SA0 + (region*4))
+#define EMI_MPU_EA(region)          (EMI_MPU_EA0 + (region*4))
+#define EMI_MPU_APC0                (EMI_MPU_BASE+0x300)
+#define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region*4) + ((dgroup)*0x100))
+#define EMI_MPU_CTRL_D0             (EMI_MPU_BASE+0x800)
+#define EMI_MPU_CTRL_D(domain)      (EMI_MPU_CTRL_D0 + (domain*4))
+#define EMI_RG_MASK_D0              (EMI_MPU_BASE+0x900)
+#define EMI_RG_MASK_D(domain)       (EMI_RG_MASK_D0 + (domain*4))
+
+#define SUB_EMI_MPU_CTRL                 (SUB_EMI_MPU_BASE+0x000)
+#define SUB_EMI_MPU_DBG                  (SUB_EMI_MPU_BASE+0x004)
+#define SUB_EMI_MPU_SA0                  (SUB_EMI_MPU_BASE+0x100)
+#define SUB_EMI_MPU_EA0                  (SUB_EMI_MPU_BASE+0x200)
+#define SUB_EMI_MPU_SA(region)           (SUB_EMI_MPU_SA0 + (region*4))
+#define SUB_EMI_MPU_EA(region)           (SUB_EMI_MPU_EA0 + (region*4))
+#define SUB_EMI_MPU_APC0                 (SUB_EMI_MPU_BASE+0x300)
+#define SUB_EMI_MPU_APC(region, dgroup)  (SUB_EMI_MPU_APC0 + (region*4) + ((dgroup)*0x100))
+#define SUB_EMI_MPU_CTRL_D0              (SUB_EMI_MPU_BASE+0x800)
+#define SUB_EMI_MPU_CTRL_D(domain)       (SUB_EMI_MPU_CTRL_D0 + (domain*4))
+#define SUB_EMI_RG_MASK_D0               (SUB_EMI_MPU_BASE+0x900)
+#define SUB_EMI_RG_MASK_D(domain)        (SUB_EMI_RG_MASK_D0 + (domain*4))
+
+#define CHN_EMI_CONA(base)          (base + 0x000)
+#define CHN_EMI_CONC(base)          (base + 0x010)
+
+#endif	// __EMI_HW_H__
diff --git a/src/vendorcode/mediatek/mt8195/include/emi_mpu_mt.h b/src/vendorcode/mediatek/mt8195/include/emi_mpu_mt.h
new file mode 100644
index 000000000000..c0bd8b412203
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/emi_mpu_mt.h
@@ -0,0 +1,13 @@
+#ifndef __EMI_MPU_MT_H__
+#define __EMI_MPU_MT_H__
+
+#define ENABLE_MPU	1
+
+#define EMI_MPU_ALIGN_BITS	16
+#define EMI_MPU_DOMAIN_NUM	16
+#define EMI_MPU_REGION_NUM	32
+#define DRAM_OFFSET		(0x40000000 >> EMI_MPU_ALIGN_BITS)
+
+#define SSPM_MPU_REGION_ID	4
+
+#endif /* __EMI_MPU_MT_H__ */
diff --git a/src/vendorcode/mediatek/mt8195/include/mt8195.h b/src/vendorcode/mediatek/mt8195/include/mt8195.h
new file mode 100644
index 000000000000..a967f8280629
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/mt8195.h
@@ -0,0 +1,234 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein
+ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
+ * Without the prior written permission of MediaTek inc. and/or its licensors,
+ * any reproduction, modification, use or disclosure of MediaTek Software,
+ * and information contained herein, in whole or in part, shall be strictly prohibited.
+ */
+/* MediaTek Inc. (C) 2011. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
+ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
+ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
+ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
+ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ fix* The following software/firmware and/or related documentation ("MediaTek Software")
+ * have been modified by MediaTek Inc. All revisions are subject to any receiver's
+ * applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef MT8195_H
+#define MT8195_H
+
+/*=======================================================================*/
+/* Constant Definitions                                                  */
+/*=======================================================================*/
+
+#define IO_PHYS             (0x10000000)
+#define IO_SIZE             (0x02000000)
+
+#define VER_BASE            (0x08000000)
+
+/*=======================================================================*/
+/* Register Bases                                                        */
+/*=======================================================================*/
+#define MCUCFG_BASE          (0x0C530000)
+#define TOPCKGEN_BASE        (IO_PHYS)
+#define INFRACFG_AO_BASE     (IO_PHYS + 0x00001000)
+#define APMIXED_BASE         (IO_PHYS + 0x0000C000)
+#define INFRA_AO_BCRM_BASE   (IO_PHYS + 0x00022000)
+#define AUDIO_BASE           (IO_PHYS + 0x00890000)
+#define AUDIO_SRC_BASE       (IO_PHYS + 0x008a0000)
+#define CAMSYS_YUVB_BASE     (IO_PHYS + 0x060af000)
+#define CAMSYS_MAIN_BASE     (IO_PHYS + 0x06000000)
+#define CAMSYS_MRAW_BASE     (IO_PHYS + 0x06140000)
+#define CAMSYS_RAWA_BASE     (IO_PHYS + 0x0604f000)
+#define CAMSYS_RAWB_BASE     (IO_PHYS + 0x0608f000)
+#define CAMSYS_YUVA_BASE     (IO_PHYS + 0x0606f000)
+#define CCU_MAIN_BASE        (IO_PHYS + 0x07200000)
+#define IMGSYS1_DIP_NR_BASE  (IO_PHYS + 0x05130000)
+#define IMGSYS1_DIP_TOP_BASE (IO_PHYS + 0x05110000)
+#define IMGSYS1_WPE_BASE     (IO_PHYS + 0x05220000)
+#define IMGSYS_MAIN_BASE     (IO_PHYS + 0x05000000)
+#define IPESYS_BASE          (IO_PHYS + 0x05330000)
+#define MFGCFG_BASE          (IO_PHYS + 0x03fbf000)
+#define PERICFG_AO_BASE      (IO_PHYS + 0x01003000)
+#define SCP_PAR_TOP_BASE     (IO_PHYS + 0x00720000)
+#define IPNNA_BASE           (IO_PHYS + 0x00211000)
+#define VDEC_CORE1_GCON_BASE (IO_PHYS + 0x0803f000)
+#define VDEC_GCON_BASE       (IO_PHYS + 0x0802f000)
+#define VDEC_SOC_GCON_BASE   (IO_PHYS + 0x0800f000)
+#define VDOSYS0_CONFIG_BASE  (IO_PHYS + 0x0c01a000)
+#define VDOSYS1_CONFIG_BASE  (IO_PHYS + 0x0c100000)
+#define VENC_CORE1_GCON_BASE (IO_PHYS + 0x0b000000)
+#define VENC_GCON_BASE       (IO_PHYS + 0x0a000000)
+#define VPP0_REG_BASE        (IO_PHYS + 0x04000000)
+#define VPPSYS1_CONFIG_BASE  (IO_PHYS + 0x04f00000)
+#define WPESYS_TOP_REG_BASE  (IO_PHYS + 0x04e00000)
+#define WPE_VPP0_BASE        (IO_PHYS + 0x04e02000)
+#define WPE_VPP1_BASE        (IO_PHYS + 0x04e03000)
+
+#define IOCFG_BM_BASE 		(0x11D10000)
+#define IOCFG_BL_BASE 		(0x11D30000)
+#define IOCFG_BR_BASE 		(0x11D40000)
+#define IOCFG_LM_BASE 		(0x11E20000)
+#define IOCFG_RB_BASE 		(0x11EB0000)
+#define IOCFG_TL_BASE 		(0x11F40000)
+
+/*should be removed*/
+#define PERICFG_BASE        (IO_PHYS + 0x00003000)
+
+//#define PERI_CON_BASE       (IO_PHYS + 0x00003000)
+
+#define GPIO_BASE           (IO_PHYS + 0x00005000)
+#define SPM_BASE            (IO_PHYS + 0x00006000)
+#define RGU_BASE            (IO_PHYS + 0x00007000)
+#define GPT_BASE            (IO_PHYS + 0x00008000)
+#define SYSTIMER_BASE       (IO_PHYS + 0x00017000)
+#define TIA_BASE            (IO_PHYS + 0x0001C000)
+#define PMIF_SPI_BASE       (IO_PHYS + 0x00024000)
+#define PMICSPI_MST_BASE    (IO_PHYS + 0x00025000)
+#define PMIF_SPMI_BASE      (IO_PHYS + 0x00027000)
+#define SPMI_MST_BASE       (IO_PHYS + 0x00029000)
+#define DDRPHY_BASE         (IO_PHYS + 0x00330000)
+#define KPD_BASE            (IO_PHYS + 0x00010000)
+
+#define DEM_BASE            (0x0D0A0000)
+
+#define MCUSYS_CFGREG_BASE  (0x0C530000)
+//#define CA7MCUCFG_BASE      (IO_PHYS + 0x00200100)
+//#define CA15L_CONFIG_BASE   (IO_PHYS + 0x00200200)
+#define SRAMROM_BASE        (IO_PHYS + 0x00214000)
+#define GICD_BASE           (0x0c000000)
+#define GICR_BASE           (0x0c040000)
+
+#define AUXADC_BASE         (IO_PHYS + 0X01002000)
+#define DEVINFO_BASE        (IO_PHYS + 0x01C10000)
+#define UART0_BASE          (IO_PHYS + 0x01001100)
+#define UART1_BASE          (IO_PHYS + 0x01001200)
+#define UART2_BASE          (IO_PHYS + 0x01001300)
+#define UART3_BASE          (IO_PHYS + 0x01001400)
+#define SPI_BASE            (IO_PHYS + 0x010F0000)
+#define NFI_BASE            (IO_PHYS + 0x0100D000) /* FIXME: not list in memory map */
+#define NFIECC_BASE         (IO_PHYS + 0x0100E000) /* FIXME: not list in memory map */
+#define MSDC0_TOP_BASE      (IO_PHYS + 0x01F50000)
+#define MSDC1_TOP_BASE      (IO_PHYS + 0x01E10000)
+#define MSDC0_BASE          (IO_PHYS + 0x01230000)
+#define MSDC1_BASE          (IO_PHYS + 0x01240000)
+#define MSDC2_BASE          (IO_PHYS + 0x01250000)
+#define MSDC3_BASE          (IO_PHYS + 0x01260000) /* Reserved in Sylvia */
+#define U3D_BASE			(IO_PHYS + 0x01200000) /* MAC: 0x1120_0000 */
+#define USB_SIF_BASE		(IO_PHYS + 0x01E40000) /* PHY: 0x11E4_0000 */
+#define USB1P_SIF_BASE      (IO_PHYS + 0x01C40000)
+#define PCIE_BASE           (IO_PHYS + 0x093F0000)
+#define PCIE_PHY_BASE       (IO_PHYS + 0x01E20000)
+
+#define CPUXGPT_BASE        (IO_PHYS + 0x00200000)
+
+#define SUB_INFRACFG_AO_BASE  (IO_PHYS + 0x0030E000)
+
+/*=======================================================================*/
+/* AP HW code offset                                                     */
+/*=======================================================================*/
+#define APHW_CODE           (VER_BASE)
+#define APHW_SUBCODE        (VER_BASE + 0x04)
+#define APHW_VER            (VER_BASE + 0x08)
+#define APSW_VER            (VER_BASE + 0x0C)
+
+// #define AMCONFG_BASE        (0xFFFFFFFF)
+
+/*=======================================================================*/
+/* USB register offset                                                   */
+/*=======================================================================*/
+#define SSUSB_DEV_BASE                      (U3D_BASE + 0x1000) /* FIXME: not list in memory map */
+#define SSUSB_EPCTL_CSR_BASE                (U3D_BASE + 0x1800) /* FIXME: not list in memory map */
+#define SSUSB_USB3_MAC_CSR_BASE             (U3D_BASE + 0x2400) /* FIXME: not list in memory map */
+#define SSUSB_USB3_SYS_CSR_BASE             (U3D_BASE + 0x2400) /* FIXME: not list in memory map */
+#define SSUSB_USB2_CSR_BASE                 (U3D_BASE + 0x3400) /* FIXME: not list in memory map */
+
+#define SSUSB_SIFSLV_IPPC_BASE              (U3D_BASE + 0x3E00) /* FIXME: not list in memory map */
+
+#define SSUSB_SIFSLV_SPLLC_BASE             (USB_SIF_BASE + 0x700) /* FIXME: not list in memory map */
+#define SSUSB_SIFSLV_U2PHY_COM_BASE         (USB_SIF_BASE + 0x300) /* FIXME: not list in memory map */
+#define SSUSB_SIFSLV_U3PHYD_BASE            (USB_SIF_BASE + 0x900) /* FIXME: not list in memory map */
+#define SSUSB_SIFSLV_U2PHY_COM_SIV_B_BASE   (USB_SIF_BASE + 0x300) /* FIXME: not list in memory map */
+#define SSUSB_USB30_PHYA_SIV_B2_BASE        (USB_SIF_BASE + 0xA00) /* FIXME: not list in memory map */
+#define SSUSB_USB30_PHYA_SIV_B_BASE         (USB_SIF_BASE + 0xB00) /* FIXME: not list in memory map */
+#define SSUSB_SIFSLV_U3PHYA_DA_BASE         (USB_SIF_BASE + 0xC00) /* FIXME: not list in memory map */
+
+
+/*=======================================================================*/
+/* USB download control                                                  */
+/*=======================================================================*/
+#define SECURITY_AO                 (0x1001A000)
+#define BOOT_MISC0                  (SECURITY_AO + 0x0080)
+#define MISC_LOCK_KEY               (SECURITY_AO + 0x0100)
+#define RST_CON                     (SECURITY_AO + 0x0108)
+
+#define MISC_LOCK_KEY_MAGIC    0xAD98
+#define USBDL_FLAG    BOOT_MISC0
+
+
+#define USBDL_BIT_EN        (0x00000001) /* 1: download bit enabled */
+#define USBDL_BROM          (0x00000002) /* 0: usbdl by brom; 1: usbdl by bootloader */
+#define USBDL_TIMEOUT_MASK  (0x0000FFFC) /* 14-bit timeout: 0x0000~0x3FFE: second; 0x3FFFF: no timeout */
+#define USBDL_TIMEOUT_MAX   (USBDL_TIMEOUT_MASK >> 2) /* maximum timeout indicates no timeout */
+#define USBDL_MAGIC         (0x444C0000) /* Brom will check this magic number */
+
+
+#define SRAMROM_USBDL_TO_DIS (SRAMROM_BASE + 0x0054)
+#define USBDL_TO_DIS         (0x00000001)
+
+/*=======================================================================*/
+/* NAND Control                                                          */
+/*=======================================================================*/
+#define NAND_PAGE_SIZE                  (2048)  // (Bytes)
+#define NAND_BLOCK_BLKS                 (64)    // 64 nand pages = 128KB
+#define NAND_PAGE_SHIFT                 (9)
+#define NAND_LARGE_PAGE                 (11)    // large page
+#define NAND_SMALL_PAGE                 (9)     // small page
+#define NAND_BUS_WIDTH_8                (8)
+#define NAND_BUS_WIDTH_16               (16)
+#define NAND_FDM_SIZE                   (8)
+#define NAND_ECC_SW                     (0)
+#define NAND_ECC_HW                     (1)
+
+#define NFI_MAX_FDM_SIZE                (8)
+#define NFI_MAX_FDM_SEC_NUM             (8)
+#define NFI_MAX_LOCK_CHANNEL            (16)
+
+#define ECC_MAX_CORRECTABLE_BITS        (12)
+#define ECC_MAX_PARITY_SIZE             (20)    /* in bytes */
+
+#define ECC_ERR_LOCATION_MASK           (0x1FFF)
+#define ECC_ERR_LOCATION_SHIFT          (16)
+
+#define NAND_FFBUF_SIZE                 (2048 + 64)
+
+/*=======================================================================*/
+/* SW Reset Vector                                                       */
+/*=======================================================================*/
+/* setup the reset vector base address after warm reset to Aarch64 */
+#define RVBADDRESS_CPU0     (MCUSYS_CFGREG_BASE + 0xC900)
+
+/* IRQ */
+#define SYS_TIMER_IRQ       (233 + 32)
+#define GZ_SW_IRQ           (513 + 32)
+
+#endif
diff --git a/src/vendorcode/mediatek/mt8195/include/pll.h b/src/vendorcode/mediatek/mt8195/include/pll.h
new file mode 100644
index 000000000000..7b22fdbaf81f
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/pll.h
@@ -0,0 +1,472 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2010. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+
+#ifndef PLL_H
+#define PLL_H
+
+#include "mt8195.h"
+
+/* for MTCMOS bus protection */
+//TODO
+#define INFRA_TOPAXI_PROTECTEN			(INFRACFG_AO_BASE + 0x0220)
+#define INFRA_TOPAXI_PROTECTEN_SET		(INFRACFG_AO_BASE + 0x02A0)
+#define INFRA_TOPAXI_PROTECTEN_CLR		(INFRACFG_AO_BASE + 0x02A4)
+#define INFRA_TOPAXI_PROTECTEN_STA0		(INFRACFG_AO_BASE + 0x0224)
+#define INFRA_TOPAXI_PROTECTEN_STA1		(INFRACFG_AO_BASE + 0x0228)
+
+#define INFRA_TOPAXI_PROTECTEN_1		(INFRACFG_AO_BASE + 0x0250)
+#define INFRA_TOPAXI_PROTECTEN_1_SET		(INFRACFG_AO_BASE + 0x02A8)
+#define INFRA_TOPAXI_PROTECTEN_1_CLR		(INFRACFG_AO_BASE + 0x02AC)
+#define INFRA_TOPAXI_PROTECTEN_STA0_1		(INFRACFG_AO_BASE + 0x0254)
+#define INFRA_TOPAXI_PROTECTEN_STA1_1		(INFRACFG_AO_BASE + 0x0258)
+
+#define INFRA_TOPAXI_PROTECTEN_MCU		(INFRACFG_AO_BASE + 0x02C0)
+#define INFRA_TOPAXI_PROTECTEN_MCU_STA0		(INFRACFG_AO_BASE + 0x02E0)
+#define INFRA_TOPAXI_PROTECTEN_MCU_STA1		(INFRACFG_AO_BASE + 0x02E4)
+#define INFRA_TOPAXI_PROTECTEN_MCU_SET		(INFRACFG_AO_BASE + 0x02C4)
+#define INFRA_TOPAXI_PROTECTEN_MCU_CLR		(INFRACFG_AO_BASE + 0x02C8)
+
+#define INFRA_TOPAXI_PROTECTEN_MM		(INFRACFG_AO_BASE + 0x02D0)
+#define INFRA_TOPAXI_PROTECTEN_MM_SET		(INFRACFG_AO_BASE + 0x02D4)
+#define INFRA_TOPAXI_PROTECTEN_MM_CLR		(INFRACFG_AO_BASE + 0x02D8)
+#define INFRA_TOPAXI_PROTECTEN_MM_STA0		(INFRACFG_AO_BASE + 0x02E8)
+#define INFRA_TOPAXI_PROTECTEN_MM_STA1		(INFRACFG_AO_BASE + 0x02EC)
+
+#define INFRA_TOPAXI_PROTECTEN_2		(INFRACFG_AO_BASE + 0x0710)
+#define INFRA_TOPAXI_PROTECTEN_2_SET		(INFRACFG_AO_BASE + 0x0714)
+#define INFRA_TOPAXI_PROTECTEN_2_CLR		(INFRACFG_AO_BASE + 0x0718)
+#define INFRA_TOPAXI_PROTECTEN_STA0_2		(INFRACFG_AO_BASE + 0x0720)
+#define INFRA_TOPAXI_PROTECTEN_STA1_2		(INFRACFG_AO_BASE + 0x0724)
+
+#define INFRA_TOPAXI_PROTECTEN_MM_2		(INFRACFG_AO_BASE + 0x0DC8)
+#define INFRA_TOPAXI_PROTECTEN_MM_2_SET		(INFRACFG_AO_BASE + 0x0DCC)
+#define INFRA_TOPAXI_PROTECTEN_MM_2_CLR		(INFRACFG_AO_BASE + 0x0DD0)
+#define INFRA_TOPAXI_PROTECTEN_MM_2_STA0	(INFRACFG_AO_BASE + 0x0DD4)
+#define INFRA_TOPAXI_PROTECTEN_MM_2_STA1	(INFRACFG_AO_BASE + 0x0DD8)
+
+#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR		(INFRACFG_AO_BASE + 0x0B80)
+#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_SET		(INFRACFG_AO_BASE + 0x0B84)
+#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_CLR		(INFRACFG_AO_BASE + 0x0B88)
+#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_STA0		(INFRACFG_AO_BASE + 0x0B8c)
+#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_STA1		(INFRACFG_AO_BASE + 0x0B90)
+
+#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1		(INFRACFG_AO_BASE + 0x0BA0)
+#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_SET		(INFRACFG_AO_BASE + 0x0BA4)
+#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_CLR		(INFRACFG_AO_BASE + 0x0BA8)
+#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_STA0	(INFRACFG_AO_BASE + 0x0BAc)
+#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_STA1	(INFRACFG_AO_BASE + 0x0BB0)
+
+#define INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR		(INFRACFG_AO_BASE + 0x0BB4)
+#define INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_SET	(INFRACFG_AO_BASE + 0x0BB8)
+#define INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_CLR	(INFRACFG_AO_BASE + 0x0BBC)
+#define INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_STA0	(INFRACFG_AO_BASE + 0x0BC0)
+#define INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_STA1	(INFRACFG_AO_BASE + 0x0BC4)
+
+/* MCUCFG Register */
+#define CPU_PLLDIV_CFG0		(MCUCFG_BASE + 0xA2A0)
+#define CPU_PLLDIV_CFG1		(MCUCFG_BASE + 0xA2A4)
+#define BUS_PLLDIV_CFG		(MCUCFG_BASE + 0xA2E0)
+
+/* APMIXEDSYS Register */
+#define AP_PLL_CON0             (APMIXED_BASE + 0x0000)
+
+#define PLLON_CON0		(APMIXED_BASE + 0x0050)
+#define PLLON_CON1		(APMIXED_BASE + 0x0054)
+#define PLLON_CON2		(APMIXED_BASE + 0x0058)
+#define PLLON_CON3		(APMIXED_BASE + 0x005C)
+
+#define ARMPLL_LL_CON0		(APMIXED_BASE + 0x0020)
+#define ARMPLL_LL_CON1          (APMIXED_BASE + 0x0024)
+#define ARMPLL_LL_CON2          (APMIXED_BASE + 0x0028)
+#define ARMPLL_LL_CON3          (APMIXED_BASE + 0x002C)
+#define ARMPLL_LL_CON4          (APMIXED_BASE + 0X0600)
+
+#define ARMPLL_BL_CON0          (APMIXED_BASE + 0X0070)
+#define ARMPLL_BL_CON1          (APMIXED_BASE + 0X0074)
+#define ARMPLL_BL_CON2          (APMIXED_BASE + 0X0078)
+#define ARMPLL_BL_CON3          (APMIXED_BASE + 0X007C)
+#define ARMPLL_BL_CON4          (APMIXED_BASE + 0X0080)
+
+#define CCIPLL_CON0             (APMIXED_BASE + 0X0030)
+#define CCIPLL_CON1             (APMIXED_BASE + 0X0634)
+#define CCIPLL_CON2             (APMIXED_BASE + 0X0638)
+#define CCIPLL_CON3             (APMIXED_BASE + 0X063C)
+#define CCIPLL_CON4             (APMIXED_BASE + 0X0640)
+
+#define NNAPLL_CON0             (APMIXED_BASE + 0X0390)
+#define NNAPLL_CON1             (APMIXED_BASE + 0X0394)
+#define NNAPLL_CON2             (APMIXED_BASE + 0X0398)
+#define NNAPLL_CON3             (APMIXED_BASE + 0X039C)
+#define NNAPLL_CON4             (APMIXED_BASE + 0X03A0)
+
+#define RESPLL_CON0             (APMIXED_BASE + 0X0190)
+#define RESPLL_CON1             (APMIXED_BASE + 0X0194)
+#define RESPLL_CON2             (APMIXED_BASE + 0X0198)
+#define RESPLL_CON3             (APMIXED_BASE + 0X019C)
+#define RESPLL_CON4             (APMIXED_BASE + 0X0320)
+
+#define ETHPLL_CON0             (APMIXED_BASE + 0X0360)
+#define ETHPLL_CON1             (APMIXED_BASE + 0X0364)
+#define ETHPLL_CON2             (APMIXED_BASE + 0X0368)
+#define ETHPLL_CON3             (APMIXED_BASE + 0X036C)
+#define ETHPLL_CON4             (APMIXED_BASE + 0X0370)
+
+#define MSDCPLL_CON0            (APMIXED_BASE + 0X0710)
+#define MSDCPLL_CON1            (APMIXED_BASE + 0X0714)
+#define MSDCPLL_CON2            (APMIXED_BASE + 0X0718)
+#define MSDCPLL_CON3            (APMIXED_BASE + 0X071C)
+#define MSDCPLL_CON4            (APMIXED_BASE + 0X0720)
+
+#define TVDPLL1_CON0            (APMIXED_BASE + 0X00A0)
+#define TVDPLL1_CON1            (APMIXED_BASE + 0X00A4)
+#define TVDPLL1_CON2            (APMIXED_BASE + 0X00A8)
+#define TVDPLL1_CON3            (APMIXED_BASE + 0X00AC)
+#define TVDPLL1_CON4            (APMIXED_BASE + 0X00B0)
+
+#define TVDPLL2_CON0            (APMIXED_BASE + 0X00C0)
+#define TVDPLL2_CON1            (APMIXED_BASE + 0X00C4)
+#define TVDPLL2_CON2            (APMIXED_BASE + 0X00C8)
+#define TVDPLL2_CON3            (APMIXED_BASE + 0X00CC)
+#define TVDPLL2_CON4            (APMIXED_BASE + 0X00D0)
+
+#define MPLL_CON0		(APMIXED_BASE + 0X0800)
+#define MPLL_CON1		(APMIXED_BASE + 0X0804)
+#define MPLL_CON2		(APMIXED_BASE + 0X0808)
+#define MPLL_CON3		(APMIXED_BASE + 0X080C)
+#define MPLL_CON4		(APMIXED_BASE + 0X0810)
+
+#define MMPLL_CON0              (APMIXED_BASE + 0X00E0)
+#define MMPLL_CON1              (APMIXED_BASE + 0X00E4)
+#define MMPLL_CON2              (APMIXED_BASE + 0X00E8)
+#define MMPLL_CON3              (APMIXED_BASE + 0X00EC)
+#define MMPLL_CON4              (APMIXED_BASE + 0X00F0)
+
+#define MAINPLL_CON0            (APMIXED_BASE + 0X01D0)
+#define MAINPLL_CON1            (APMIXED_BASE + 0X01D4)
+#define MAINPLL_CON2            (APMIXED_BASE + 0X01D8)
+#define MAINPLL_CON3            (APMIXED_BASE + 0X01DC)
+#define MAINPLL_CON4            (APMIXED_BASE + 0X01E0)
+
+#define VDECPLL_CON0            (APMIXED_BASE + 0X0890)
+#define VDECPLL_CON1            (APMIXED_BASE + 0X0894)
+#define VDECPLL_CON2            (APMIXED_BASE + 0X0898)
+#define VDECPLL_CON3            (APMIXED_BASE + 0X089C)
+#define VDECPLL_CON4            (APMIXED_BASE + 0X08A0)
+
+#define IMGPLL_CON0             (APMIXED_BASE + 0X0100)
+#define IMGPLL_CON1             (APMIXED_BASE + 0X0104)
+#define IMGPLL_CON2             (APMIXED_BASE + 0X0108)
+#define IMGPLL_CON3             (APMIXED_BASE + 0X010C)
+#define IMGPLL_CON4             (APMIXED_BASE + 0X0110)
+
+#define UNIVPLL_CON0	        (APMIXED_BASE + 0X01F0)
+#define UNIVPLL_CON1            (APMIXED_BASE + 0X01F4)
+#define UNIVPLL_CON2            (APMIXED_BASE + 0X01F8)
+#define UNIVPLL_CON3            (APMIXED_BASE + 0X01FC)
+#define UNIVPLL_CON4            (APMIXED_BASE + 0X0700)
+
+#define HDMIPLL1_CON0           (APMIXED_BASE + 0X08C0)
+#define HDMIPLL1_CON1           (APMIXED_BASE + 0X08C4)
+#define HDMIPLL1_CON2           (APMIXED_BASE + 0X08C8)
+#define HDMIPLL1_CON3           (APMIXED_BASE + 0X08CC)
+#define HDMIPLL1_CON4           (APMIXED_BASE + 0X08D0)
+
+#define HDMIPLL2_CON0           (APMIXED_BASE + 0X0870)
+#define HDMIPLL2_CON1           (APMIXED_BASE + 0X0874)
+#define HDMIPLL2_CON2           (APMIXED_BASE + 0X0878)
+#define HDMIPLL2_CON3           (APMIXED_BASE + 0X087C)
+#define HDMIPLL2_CON4           (APMIXED_BASE + 0X0880)
+
+#define HDMIRX_APLL_CON0        (APMIXED_BASE + 0X08E0)
+#define HDMIRX_APLL_CON1        (APMIXED_BASE + 0X08E4)
+#define HDMIRX_APLL_CON2        (APMIXED_BASE + 0X08E8)
+#define HDMIRX_APLL_CON3        (APMIXED_BASE + 0X08EC)
+#define HDMIRX_APLL_CON4        (APMIXED_BASE + 0X08F0)
+#define HDMIRX_APLL_CON5        (APMIXED_BASE + 0X0DD4)
+
+#define USB1PLL_CON0            (APMIXED_BASE + 0X01A0)
+#define USB1PLL_CON1            (APMIXED_BASE + 0X01A4)
+#define USB1PLL_CON2            (APMIXED_BASE + 0X01A8)
+#define USB1PLL_CON3            (APMIXED_BASE + 0X01AC)
+#define USB1PLL_CON4            (APMIXED_BASE + 0X01B0)
+
+#define ADSPPLL_CON0            (APMIXED_BASE + 0X07E0)
+#define ADSPPLL_CON1            (APMIXED_BASE + 0X07E4)
+#define ADSPPLL_CON2            (APMIXED_BASE + 0X07E8)
+#define ADSPPLL_CON3            (APMIXED_BASE + 0X07EC)
+#define ADSPPLL_CON4            (APMIXED_BASE + 0X07F0)
+
+#define APLL1_CON0              (APMIXED_BASE + 0X07C0)
+#define APLL1_CON1              (APMIXED_BASE + 0X07C4)
+#define APLL1_CON2              (APMIXED_BASE + 0X07C8)
+#define APLL1_CON3              (APMIXED_BASE + 0X07CC)
+#define APLL1_CON4              (APMIXED_BASE + 0X07D0)
+#define APLL1_CON5              (APMIXED_BASE + 0X0DC0)
+
+#define APLL2_CON0              (APMIXED_BASE + 0X0780)
+#define APLL2_CON1              (APMIXED_BASE + 0X0784)
+#define APLL2_CON2              (APMIXED_BASE + 0X0788)
+#define APLL2_CON3              (APMIXED_BASE + 0X078C)
+#define APLL2_CON4              (APMIXED_BASE + 0X0790)
+#define APLL2_CON5              (APMIXED_BASE + 0X0DC4)
+
+#define APLL3_CON0              (APMIXED_BASE + 0X0760)
+#define APLL3_CON1              (APMIXED_BASE + 0X0764)
+#define APLL3_CON2              (APMIXED_BASE + 0X0768)
+#define APLL3_CON3              (APMIXED_BASE + 0X076C)
+#define APLL3_CON4              (APMIXED_BASE + 0X0770)
+#define APLL3_CON5              (APMIXED_BASE + 0X0DC8)
+
+#define APLL4_CON0              (APMIXED_BASE + 0X0740)
+#define APLL4_CON1              (APMIXED_BASE + 0X0744)
+#define APLL4_CON2              (APMIXED_BASE + 0X0748)
+#define APLL4_CON3              (APMIXED_BASE + 0X074C)
+#define APLL4_CON4              (APMIXED_BASE + 0X0750)
+#define APLL4_CON5              (APMIXED_BASE + 0X0DCC)
+
+#define APLL5_CON0              (APMIXED_BASE + 0X07A0)
+#define APLL5_CON1              (APMIXED_BASE + 0X07A4)
+#define APLL5_CON2              (APMIXED_BASE + 0X07A8)
+#define APLL5_CON3              (APMIXED_BASE + 0X07AC)
+#define APLL5_CON4              (APMIXED_BASE + 0X07B0)
+#define APLL5_CON5              (APMIXED_BASE + 0X0DD0)
+
+#define MFGPLL_CON0             (APMIXED_BASE + 0X0340)
+#define MFGPLL_CON1             (APMIXED_BASE + 0X0344)
+#define MFGPLL_CON2             (APMIXED_BASE + 0X0348)
+#define MFGPLL_CON3             (APMIXED_BASE + 0X034C)
+#define MFGPLL_CON4             (APMIXED_BASE + 0X0350)
+
+#define DGIPLL_CON0             (APMIXED_BASE + 0X0150)
+#define DGIPLL_CON1             (APMIXED_BASE + 0X0154)
+#define DGIPLL_CON2             (APMIXED_BASE + 0X0158)
+#define DGIPLL_CON3             (APMIXED_BASE + 0X015C)
+#define DGIPLL_CON4             (APMIXED_BASE + 0X0160)
+
+#define APLL1_TUNER_CON0        (APMIXED_BASE + 0x0470)
+#define APLL2_TUNER_CON0        (APMIXED_BASE + 0x0474)
+#define APLL3_TUNER_CON0        (APMIXED_BASE + 0x0478)
+#define APLL4_TUNER_CON0        (APMIXED_BASE + 0x047C)
+#define APLL5_TUNER_CON0        (APMIXED_BASE + 0x0480)
+
+/* TOPCKGEN Register */
+#define CLK_CFG_UPDATE          (TOPCKGEN_BASE + 0x004)
+#define CLK_CFG_UPDATE1         (TOPCKGEN_BASE + 0x008)
+#define CLK_CFG_UPDATE2         (TOPCKGEN_BASE + 0x00C)
+#define CLK_CFG_UPDATE3		(TOPCKGEN_BASE + 0x010)
+#define CLK_CFG_UPDATE4		(TOPCKGEN_BASE + 0x014)
+
+#define CLK_CFG_0_SET		(TOPCKGEN_BASE + 0x024)
+#define CLK_CFG_0_CLR		(TOPCKGEN_BASE + 0x028)
+#define CLK_CFG_1_SET		(TOPCKGEN_BASE + 0x030)
+#define CLK_CFG_1_CLR		(TOPCKGEN_BASE + 0x034)
+#define CLK_CFG_2_SET		(TOPCKGEN_BASE + 0x03C)
+#define CLK_CFG_2_CLR		(TOPCKGEN_BASE + 0x040)
+#define CLK_CFG_3_SET		(TOPCKGEN_BASE + 0x048)
+#define CLK_CFG_3_CLR		(TOPCKGEN_BASE + 0x04C)
+#define CLK_CFG_4_SET		(TOPCKGEN_BASE + 0x054)
+#define CLK_CFG_4_CLR		(TOPCKGEN_BASE + 0x058)
+#define CLK_CFG_5_SET		(TOPCKGEN_BASE + 0x060)
+#define CLK_CFG_5_CLR		(TOPCKGEN_BASE + 0x064)
+#define CLK_CFG_6_SET		(TOPCKGEN_BASE + 0x06C)
+#define CLK_CFG_6_CLR		(TOPCKGEN_BASE + 0x070)
+#define CLK_CFG_7_SET		(TOPCKGEN_BASE + 0x078)
+#define CLK_CFG_7_CLR		(TOPCKGEN_BASE + 0x07C)
+#define CLK_CFG_8_SET		(TOPCKGEN_BASE + 0x084)
+#define CLK_CFG_8_CLR		(TOPCKGEN_BASE + 0x088)
+#define CLK_CFG_9_SET		(TOPCKGEN_BASE + 0x090)
+#define CLK_CFG_9_CLR		(TOPCKGEN_BASE + 0x094)
+#define CLK_CFG_10_SET		(TOPCKGEN_BASE + 0x09C)
+#define CLK_CFG_10_CLR		(TOPCKGEN_BASE + 0x0A0)
+#define CLK_CFG_11_SET		(TOPCKGEN_BASE + 0x0A8)
+#define CLK_CFG_11_CLR		(TOPCKGEN_BASE + 0x0AC)
+#define CLK_CFG_12_SET		(TOPCKGEN_BASE + 0x0B4)
+#define CLK_CFG_12_CLR		(TOPCKGEN_BASE + 0x0B8)
+#define CLK_CFG_13_SET		(TOPCKGEN_BASE + 0x0C0)
+#define CLK_CFG_13_CLR		(TOPCKGEN_BASE + 0x0C4)
+#define CLK_CFG_14_SET		(TOPCKGEN_BASE + 0x0CC)
+#define CLK_CFG_14_CLR		(TOPCKGEN_BASE + 0x0D0)
+#define CLK_CFG_15_SET		(TOPCKGEN_BASE + 0x0D8)
+#define CLK_CFG_15_CLR		(TOPCKGEN_BASE + 0x0DC)
+#define CLK_CFG_16_SET		(TOPCKGEN_BASE + 0x0E4)
+#define CLK_CFG_16_CLR		(TOPCKGEN_BASE + 0x0E8)
+#define CLK_CFG_17_SET		(TOPCKGEN_BASE + 0x0F0)
+#define CLK_CFG_17_CLR		(TOPCKGEN_BASE + 0x0F4)
+#define CLK_CFG_18_SET		(TOPCKGEN_BASE + 0x0FC)
+#define CLK_CFG_18_CLR		(TOPCKGEN_BASE + 0x0100)
+#define CLK_CFG_19_SET		(TOPCKGEN_BASE + 0x0108)
+#define CLK_CFG_19_CLR		(TOPCKGEN_BASE + 0x010C)
+#define CLK_CFG_20_SET		(TOPCKGEN_BASE + 0x0114)
+#define CLK_CFG_20_CLR		(TOPCKGEN_BASE + 0x0118)
+#define CLK_CFG_21_SET		(TOPCKGEN_BASE + 0x0120)
+#define CLK_CFG_21_CLR		(TOPCKGEN_BASE + 0x0124)
+#define CLK_CFG_22_SET		(TOPCKGEN_BASE + 0x012C)
+#define CLK_CFG_22_CLR		(TOPCKGEN_BASE + 0x0130)
+#define CLK_CFG_23_SET		(TOPCKGEN_BASE + 0x0138)
+#define CLK_CFG_23_CLR		(TOPCKGEN_BASE + 0x013C)
+#define CLK_CFG_24_SET		(TOPCKGEN_BASE + 0x0144)
+#define CLK_CFG_24_CLR		(TOPCKGEN_BASE + 0x0148)
+#define CLK_CFG_25_SET		(TOPCKGEN_BASE + 0x0150)
+#define CLK_CFG_25_CLR		(TOPCKGEN_BASE + 0x0154)
+#define CLK_CFG_26_SET		(TOPCKGEN_BASE + 0x015C)
+#define CLK_CFG_26_CLR		(TOPCKGEN_BASE + 0x0160)
+#define CLK_CFG_27_SET		(TOPCKGEN_BASE + 0x0168)
+#define CLK_CFG_27_CLR		(TOPCKGEN_BASE + 0x016C)
+#define CLK_CFG_28_SET		(TOPCKGEN_BASE + 0x0174)
+#define CLK_CFG_28_CLR		(TOPCKGEN_BASE + 0x0178)
+#define CLK_CFG_29_SET		(TOPCKGEN_BASE + 0x0180)
+#define CLK_CFG_29_CLR		(TOPCKGEN_BASE + 0x0184)
+#define CLK_CFG_30_SET		(TOPCKGEN_BASE + 0x018C)
+#define CLK_CFG_30_CLR		(TOPCKGEN_BASE + 0x0190)
+#define CLK_CFG_31_SET		(TOPCKGEN_BASE + 0x0198)
+#define CLK_CFG_31_CLR		(TOPCKGEN_BASE + 0x019C)
+#define CLK_CFG_32_SET		(TOPCKGEN_BASE + 0x01A4)
+#define CLK_CFG_32_CLR		(TOPCKGEN_BASE + 0x01A8)
+#define CLK_CFG_33_SET		(TOPCKGEN_BASE + 0x01B0)
+#define CLK_CFG_33_CLR		(TOPCKGEN_BASE + 0x01B4)
+#define CLK_CFG_34_SET		(TOPCKGEN_BASE + 0x01BC)
+#define CLK_CFG_34_CLR		(TOPCKGEN_BASE + 0x01C0)
+#define CLK_CFG_35_SET		(TOPCKGEN_BASE + 0x01C8)
+#define CLK_CFG_35_CLR		(TOPCKGEN_BASE + 0x01CC)
+#define CLK_CFG_36_SET		(TOPCKGEN_BASE + 0x01D4)
+#define CLK_CFG_36_CLR		(TOPCKGEN_BASE + 0x01D8)
+#define CLK_CFG_37_SET		(TOPCKGEN_BASE + 0x01E0)
+#define CLK_CFG_37_CLR		(TOPCKGEN_BASE + 0x01E4)
+#define CLK_MISC_CFG_3		(TOPCKGEN_BASE + 0x0250)
+
+#define CLK_DBG_CFG		(TOPCKGEN_BASE + 0x020C)
+#define CLK26CALI_0		(TOPCKGEN_BASE + 0x0218)
+#define CLK26CALI_1		(TOPCKGEN_BASE + 0x021C)
+#define CLK_MISC_CFG_0		(TOPCKGEN_BASE + 0x022C)
+#define CLK_SCP_CFG_0		(TOPCKGEN_BASE + 0x0264)
+
+#define INFRA_BUS_DCM_CTRL		(INFRACFG_AO_BASE + 0x70)
+#define VDNR_DCM_TOP_INFRA_CTRL0	(INFRA_AO_BCRM_BASE + 0x034)
+
+#define TOPCKGEN_CLK_MISC_CFG_1		(TOPCKGEN_BASE + 0x238)
+#define TOPCKGEN_CLK_MISC_CFG_3		(TOPCKGEN_BASE + 0x250)
+#define INFRACFG_AO_MODULE_SW_CG_0_CLR	(INFRACFG_AO_BASE + 0x84)
+#define INFRACFG_AO_MODULE_SW_CG_1_CLR	(INFRACFG_AO_BASE + 0x8c)
+#define INFRACFG_AO_MODULE_SW_CG_2_CLR	(INFRACFG_AO_BASE + 0xa8)
+#define INFRACFG_AO_MODULE_SW_CG_3_CLR	(INFRACFG_AO_BASE + 0xc4)
+#define INFRACFG_AO_MODULE_SW_CG_4_CLR	(INFRACFG_AO_BASE + 0xe4)
+#define APMIXEDSYS_AP_PLL_CON2		(APMIXED_BASE + 0x8)
+#define IPNNA_F26M_CK_CG		(IPNNA_BASE + 0x104)
+#define IPNNA_AXI_CK_CG			(IPNNA_BASE + 0x110)
+#define IPNNA_NNA0_CG_EN		(IPNNA_BASE + 0x90)
+#define IPNNA_NNA1_CG_EN		(IPNNA_BASE + 0x94)
+#define IPNNA_NNA0_EMI_CG_EN		(IPNNA_BASE + 0x98)
+#define IPNNA_NNA1_EMI_CG_EN		(IPNNA_BASE + 0x9c)
+#define IPNNA_NNA0_AXI_CG_EN		(IPNNA_BASE + 0xa0)
+#define IPNNA_NNA1_AXI_CG_EN		(IPNNA_BASE + 0xa4)
+#define SCP_PAR_TOP_AUDIODSP_CK_CG	(SCP_PAR_TOP_BASE + 0x180)
+#define AUDIO_AUDIO_TOP_0		(AUDIO_BASE + 0x0)
+#define AUDIO_AUDIO_TOP_4		(AUDIO_BASE + 0x10)
+#define AUDIO_AUDIO_TOP_5		(AUDIO_BASE + 0x14)
+#define AUDIO_AUDIO_TOP_6		(AUDIO_BASE + 0x18)
+#define AUDIO_AUDIO_TOP_1		(AUDIO_BASE + 0x4)
+#define AUDIO_AUDIO_TOP_3		(AUDIO_BASE + 0xc)
+#define AUDIO_SRC_MEM_ASRC_TOP_1	(AUDIO_SRC_BASE + 0x1004)
+#define PERICFG_AO_PERI_MODULE_SW_CG_0_SET	(PERICFG_AO_BASE + 0x10)
+#define PERICFG_AO_PERI_MODULE_SW_CG_0_CLR	(PERICFG_AO_BASE + 0x14)
+#define MFGCFG_MFG_CG_CLR		(MFGCFG_BASE + 0x8)
+#define VPP0_REG_VPPSYS0_CG0_CLR	(VPP0_REG_BASE + 0x28)
+#define VPP0_REG_VPPSYS0_CG1_CLR	(VPP0_REG_BASE + 0x34)
+#define VPP0_REG_VPPSYS0_CG2_CLR	(VPP0_REG_BASE + 0x40)
+#define WPESYS_TOP_REG_WPESYS_RG_000	(WPESYS_TOP_REG_BASE + 0x0)
+#define WPE_VPP0_CTL_WPE_DCM_DIS	(WPE_VPP0_BASE + 0x58)
+#define WPE_VPP0_CTL_DMA_DCM_DIS	(WPE_VPP0_BASE + 0x5c)
+#define WPE_VPP1_CTL_WPE_DCM_DIS	(WPE_VPP1_BASE + 0x58)
+#define WPE_VPP1_CTL_DMA_DCM_DIS	(WPE_VPP1_BASE + 0x5c)
+#define VPPSYS1_CONFIG_VPPSYS1_CG_0_CLR	(VPPSYS1_CONFIG_BASE + 0x108)
+#define VPPSYS1_CONFIG_VPPSYS1_CG_1_CLR	(VPPSYS1_CONFIG_BASE + 0x118)
+#define IMGSYS_MAIN_IMG_MAIN_CG_CLR	(IMGSYS_MAIN_BASE + 0x8)
+#define IMGSYS1_DIP_TOP_MACRO_CG_CLR	(IMGSYS1_DIP_TOP_BASE + 0x8)
+#define IMGSYS1_DIP_NR_MACRO_CG_CLR	(IMGSYS1_DIP_NR_BASE + 0x8)
+#define IMGSYS1_WPE_MACRO_CG_CLR	(IMGSYS1_WPE_BASE + 0x8)
+#define IPESYS_MACRO_CG			(IPESYS_BASE + 0x0)
+#define CAMSYS_MAIN_CAMSYS_CG_CLR	(CAMSYS_MAIN_BASE + 0x8)
+#define CAMSYS_RAWA_CAMSYS_CG_CLR	(CAMSYS_RAWA_BASE + 0x8)
+#define CAMSYS_YUVA_CAMSYS_CG_CLR	(CAMSYS_YUVA_BASE + 0x8)
+#define CAMSYS_RAWB_CAMSYS_CG_CLR	(CAMSYS_RAWB_BASE + 0x8)
+#define CAMSYS_YUVB_CAMSYS_CG_CLR	(CAMSYS_YUVB_BASE + 0x8)
+#define CAMSYS_MRAW_CAMSYS_CG_CLR	(CAMSYS_MRAW_BASE + 0x8)
+#define CCU_MAIN_CCUSYS_CG_CLR		(CCU_MAIN_BASE + 0x8)
+#define VDEC_SOC_GCON_VDEC_CKEN		(VDEC_SOC_GCON_BASE + 0x0)
+#define VDEC_SOC_GCON_LAT_CKEN		(VDEC_SOC_GCON_BASE + 0x200)
+#define VDEC_SOC_GCON_LARB_CKEN_CON	(VDEC_SOC_GCON_BASE + 0x8)
+#define VDEC_GCON_VDEC_CKEN		(VDEC_GCON_BASE + 0x0)
+#define VDEC_GCON_LAT_CKEN		(VDEC_GCON_BASE + 0x200)
+#define VDEC_GCON_LARB_CKEN_CON		(VDEC_GCON_BASE + 0x8)
+#define VDEC_CORE1_GCON_VDEC_CKEN	(VDEC_CORE1_GCON_BASE + 0x0)
+#define VDEC_CORE1_GCON_LAT_CKEN	(VDEC_CORE1_GCON_BASE + 0x200)
+#define VDEC_CORE1_GCON_LARB_CKEN_CON	(VDEC_CORE1_GCON_BASE + 0x8)
+#define VENC_GCON_VENCSYS_CG_SET	(VENC_GCON_BASE + 0x4)
+#define VENC_CORE1_GCON_VENCSYS_CG_SET	(VENC_CORE1_GCON_BASE + 0x4)
+#define VDOSYS0_CONFIG_GLOBAL0_CG_0_CLR	(VDOSYS0_CONFIG_BASE + 0x108)
+#define VDOSYS0_CONFIG_GLOBAL0_CG_1_CLR	(VDOSYS0_CONFIG_BASE + 0x118)
+#define VDOSYS0_CONFIG_GLOBAL0_CG_2_CLR	(VDOSYS0_CONFIG_BASE + 0x128)
+#define VDOSYS0_CONFIG_GLOBAL1_CG_0_CLR	(VDOSYS0_CONFIG_BASE + 0x308)
+#define VDOSYS0_CONFIG_GLOBAL1_CG_1_CLR	(VDOSYS0_CONFIG_BASE + 0x318)
+#define VDOSYS0_CONFIG_GLOBAL1_CG_2_CLR	(VDOSYS0_CONFIG_BASE + 0x328)
+#define VDOSYS1_CONFIG_VDOSYS1_CG_0_CLR	(VDOSYS1_CONFIG_BASE + 0x108)
+#define VDOSYS1_CONFIG_VDOSYS1_CG_1_CLR	(VDOSYS1_CONFIG_BASE + 0x128)
+#define VDOSYS1_CONFIG_VDOSYS1_CG_2_CLR	(VDOSYS1_CONFIG_BASE + 0x138)
+#define VDOSYS1_CONFIG_VDOSYS1_CG_3_CLR	(VDOSYS1_CONFIG_BASE + 0x148)
+
+#define AP_MDSRC_REQ			(SPM_BASE + 0x43C)
+
+/*  CPU Freq Boost*/
+enum cpu_opp {
+    CPU_OPP0 = 0,
+    CPU_OPP1,
+    CPU_OPP2,
+    CPU_OPP3,
+    CPU_OPP4,
+    CPU_OPP5,
+    CPU_OPP_NUM,
+};
+
+/*
+ * EXTERN FUNCTIONS
+ */
+extern unsigned int mt_get_abist_freq(unsigned int ID);
+extern unsigned int mt_get_cpu_freq(void);
+extern void set_armpll_ll_rate(enum cpu_opp opp);
+extern void mt_set_topck_default(void);
+
+#endif
diff --git a/src/vendorcode/mediatek/mt8195/include/print.h b/src/vendorcode/mediatek/mt8195/include/print.h
new file mode 100644
index 000000000000..78fc840d6fde
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/print.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+#ifndef PRINT_H
+#define PRINT_H
+
+#include <console/console.h>
+
+//int print(const char *fmt, ...);
+#define print(_x_...)	printk(BIOS_INFO, _x_)
+#define printf   print
+
+#endif
diff --git a/src/vendorcode/mediatek/mt8195/include/reg.h b/src/vendorcode/mediatek/mt8195/include/reg.h
new file mode 100644
index 000000000000..9d3216e87590
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/reg.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+#ifndef REG_H
+#define REG_H
+
+#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
+
+#define read32(addr)       (*REG32(addr))
+#define write32(addr, val) (*REG32(addr) = (val))
+
+#endif
diff --git a/src/vendorcode/mediatek/mt8195/include/sv_c_data_traffic.h b/src/vendorcode/mediatek/mt8195/include/sv_c_data_traffic.h
new file mode 100644
index 000000000000..8f2b3e07cc50
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/sv_c_data_traffic.h
@@ -0,0 +1,315 @@
+#ifndef __SV_C_DATA_TRAFFIC_H
+#define __SV_C_DATA_TRAFFIC_H
+
+#if FOR_DV_SIMULATION_USED
+#ifndef STRINGIFY(x)
+#define STRINGIFY(x) #x
+#endif
+#endif
+#define TOSTRING(x) STRINGIFY(x)
+
+#define print_svarg(arg) \
+({ \
+	mcSHOW_DBG_MSG((TOSTRING(arg) "=0x%x\n", psra->arg)); \
+})
+
+/*
+ * channel type from sv's view
+ */
+enum {
+	SV_CHN_A = 0,
+	SV_CHN_B
+};
+
+
+/*
+ * dram type from sv's view
+ */
+enum {
+	SV_LPDDR = 0,
+	SV_LPDDR2,
+	SV_PCDDR3,
+	SV_LPDDR3,
+	SV_LPDDR4,
+	SV_LPDDR5
+};
+
+/*
+ * data rate from sv's view
+ */
+enum {
+	SV_DDR4266 = 0,
+	SV_DDR3200,
+	SV_DDR1600,
+	SV_DDR3733,
+	SV_DDR2400,
+	SV_DDR1866,
+	SV_DDR1200,
+	SV_DDR1333,
+	SV_DDR800,
+	SV_DDR1066,
+	SV_DDR2667,
+	SV_DDR4800,
+	SV_DDR5500,
+	SV_DDR6000,
+	SV_DDR6400,
+	SV_DDR2750,
+	SV_DDR2133
+};
+
+/*
+ * cal_sv_rand_args is data traffic from sv to c.
+ * sv randomizes these arguments for c to control
+ * calibration.
+ */
+typedef struct cal_sv_rand_args {
+
+/* >>>>>>>>>> common part begin>>>>>>>>>> */
+	/*
+	 * 0x4C503435
+	 * "LP45"
+	 */
+	int magic;
+
+	/*
+	 * 0: channel-a
+	 * 1: channel-b
+	 */
+	int calibration_channel;
+
+	/*
+	 * 0: rank0
+	 * 1: rank1
+	 */
+	int calibration_rank;
+
+	/*
+	 * 0: LPDDR
+	 * 1: LPDDR2
+	 * 2: PCDDR3
+	 * 3: LPDDR3
+	 * 4: LPDDR4
+	 * 5: LPDDR5
+	 */
+	int dram_type;
+
+	/*
+	 * 0: DDR4266
+	 * 1: DDR3200
+	 * 2: DDR1600
+	 * 3: DDR3733
+	 * 4: DDR2400
+	 * 5: DDR1866
+	 * 6: DDR1200
+	 * 7: DDR1333
+	 * 8: DDR800
+	 * 9: DDR1066
+	 * 10: DDR2667
+	 * 11: DDR4800
+	 * 12: DDR5500
+	 * 13: DDR6000
+	 * 14: DDR6400
+	 * 15: DDR2750
+	 * 16: DDR2133
+	 */
+	int datarate;
+
+	/*
+	 * Data Mask Disable
+	 * 0: enable
+	 * 1: disable
+	 */
+	int dmd;
+	int mr2_value; /* for lp4-wirteleveling*/
+	int mr3_value;
+	int mr13_value;
+	int mr12_value;
+	int mr16_value;
+	int mr18_value; /* lp5 writeleveling */
+	int mr20_value; /* lp5 rddqc */
+/* ============================= */
+
+
+/* >>>>>>>>>> cbt part begin>>>>>>>>>> */
+	/*
+	 * 0: doesn't run cbt calibration
+	 * 1: run cbt calibration
+	 */
+	int cbt;
+
+	/*
+	 * 0: rising phase
+	 * 1: falling phase
+	 */
+	int cbt_phase;
+
+	/*
+	 * 0: training mode1
+	 * 1: training mode2
+	 */
+	int cbt_training_mode;
+
+	/*
+	 * 0: normal mode
+	 * 1: byte mode
+	 */
+	int rk0_cbt_mode;
+
+	/*
+	 * 0: normal mode
+	 * 1: byte mode
+	 */
+	int rk1_cbt_mode;
+
+	/*
+	 * 0: cbt does NOT use autok
+	 * 1: cbt use autok
+	 */
+	int cbt_autok;
+
+	/*
+	 * autok respi
+	 * 0/1/2/3
+	 */
+	int cbt_atk_respi;
+
+	/*
+	 * 0: cbt does NOT use new cbt mode
+	 * 1: cbt use new cbt mode
+	 */
+	int new_cbt_mode;
+
+	/*
+	 * cbt pat0~7v
+	 */
+	int pat_v[8];
+
+	/*
+	 * cbt pat0~7a
+	 */
+	int pat_a[8];
+
+	/*
+	 * cbt pat_dmv
+	 */
+	int pat_dmv;
+
+	/*
+	 * cbt pat_dma
+	 */
+	int pat_dma;
+
+	/*
+	 * cbt pat_cs
+	 */
+	int pat_cs;
+
+	/*
+	 * new cbt cagolden sel
+	 */
+	int cagolden_sel;
+
+	/*
+	 * new cbt invert num
+	 */
+	int invert_num;
+
+/* ============================= */
+
+/* >>>>>>>>>> wl part begin>>>>>>>>>> */
+	/*
+	 * 0: doesn't run wl calibration
+	 * 1: run wl calibration
+	 */
+	int wl;
+
+	/*
+	 * 0: wl does NOT use autok
+	 * 1: wl use autok
+	 */
+	int wl_autok;
+
+	/*
+	 * autok respi
+	 * 0/1/2/3
+	 */
+	int wl_atk_respi;
+/* ============================= */
+
+/* >>>>>>>>>> Gating part begin >>>>>> */
+	/*
+	 * 0: does not run gating calibration
+	 * 1: run gating calibration
+	 */
+	int gating;
+
+	/*
+	 * 0: SW mode calibration
+	 * 1: HW AUTO calibration
+	 */
+	int gating_autok;
+
+	int dqsien_autok_pi_offset;
+	int dqsien_autok_early_break_en;
+	int dqsien_autok_dbg_mode_en;
+/* ============================= */
+
+/* >>>>>>>>>> RDDQC part begin >>>>>> */
+	/*
+	 * 0: does not run rddq calibration
+	 * 1: run rddq calibration
+	 */
+	int rddqc;
+
+	int low_byte_invert_golden;
+	int upper_byte_invert_golden;
+	int mr_dq_a_golden;
+	int mr_dq_b_golden;
+	int lp5_mr20_6_golden;
+	int lp5_mr20_7_golden;
+/* ============================= */
+
+/* >>>>>>>>>> TX perbit part begin >>>>>> */
+	/*
+	 * 0: does not run txperbit calibration
+	 * 1: run txperbit  calibration
+	 */
+	int tx_perbit;
+
+	/*
+	 * 0: does not run txperbit auto calibration
+	 * 1: run txperbit auto calibration
+	 */
+	int tx_auto_cal;
+
+	int tx_atk_pass_pi_thrd;
+	int tx_atk_early_break;
+/* ============================= */
+
+/* >>>>>>>>>> TX perbit part begin >>>>>> */
+	/*
+	 * 0: does not run rxperbit calibration
+	 * 1: run rxperbit calibration
+	 */
+	int rx_perbit;
+
+	/*
+	 * 0: does not run rxperbit auto calibration
+	 * 1: run rxperbit  auto calibration
+	 */
+	int rx_auto_cal;
+
+	int rx_atk_cal_step;
+	int rx_atk_cal_out_dbg_en;
+	int rx_atk_cal_out_dbg_sel;
+/* ============================= */
+} cal_sv_rand_args_t;
+
+void set_psra(cal_sv_rand_args_t *psra);
+cal_sv_rand_args_t *get_psra(void);
+void print_sv_args(cal_sv_rand_args_t *psra);
+u8 valid_magic(cal_sv_rand_args_t *psra);
+void set_type_freq_by_svargs(DRAMC_CTX_T *p,
+	    cal_sv_rand_args_t *psra);
+
+#endif /* __SV_C_DATA_TRAFFIC_H */
diff --git a/src/vendorcode/mediatek/mt8195/include/x_hal_io.h b/src/vendorcode/mediatek/mt8195/include/x_hal_io.h
new file mode 100644
index 000000000000..e7dd63a8e8ba
--- /dev/null
+++ b/src/vendorcode/mediatek/mt8195/include/x_hal_io.h
@@ -0,0 +1,170 @@
+/*----------------------------------------------------------------------------*
+ * Copyright Statement:                                                       *
+ *                                                                            *
+ *   This software/firmware and related documentation ("MediaTek Software")   *
+ * are protected under international and related jurisdictions'copyright laws *
+ * as unpublished works. The information contained herein is confidential and *
+ * proprietary to MediaTek Inc. Without the prior written permission of       *
+ * MediaTek Inc., any reproduction, modification, use or disclosure of        *
+ * MediaTek Software, and information contained herein, in whole or in part,  *
+ * shall be strictly prohibited.                                              *
+ * MediaTek Inc. Copyright (C) 2010. All rights reserved.                     *
+ *                                                                            *
+ *   BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND     *
+ * AGREES TO THE FOLLOWING:                                                   *
+ *                                                                            *
+ *   1)Any and all intellectual property rights (including without            *
+ * limitation, patent, copyright, and trade secrets) in and to this           *
+ * Software/firmware and related documentation ("MediaTek Software") shall    *
+ * remain the exclusive property of MediaTek Inc. Any and all intellectual    *
+ * property rights (including without limitation, patent, copyright, and      *
+ * trade secrets) in and to any modifications and derivatives to MediaTek     *
+ * Software, whoever made, shall also remain the exclusive property of        *
+ * MediaTek Inc.  Nothing herein shall be construed as any transfer of any    *
+ * title to any intellectual property right in MediaTek Software to Receiver. *
+ *                                                                            *
+ *   2)This MediaTek Software Receiver received from MediaTek Inc. and/or its *
+ * representatives is provided to Receiver on an "AS IS" basis only.          *
+ * MediaTek Inc. expressly disclaims all warranties, expressed or implied,    *
+ * including but not limited to any implied warranties of merchantability,    *
+ * non-infringement and fitness for a particular purpose and any warranties   *
+ * arising out of course of performance, course of dealing or usage of trade. *
+ * MediaTek Inc. does not provide any warranty whatsoever with respect to the *
+ * software of any third party which may be used by, incorporated in, or      *
+ * supplied with the MediaTek Software, and Receiver agrees to look only to   *
+ * such third parties for any warranty claim relating thereto.  Receiver      *
+ * expressly acknowledges that it is Receiver's sole responsibility to obtain *
+ * from any third party all proper licenses contained in or delivered with    *
+ * MediaTek Software.  MediaTek is not responsible for any MediaTek Software  *
+ * releases made to Receiver's specifications or to conform to a particular   *
+ * standard or open forum.                                                    *
+ *                                                                            *
+ *   3)Receiver further acknowledge that Receiver may, either presently       *
+ * and/or in the future, instruct MediaTek Inc. to assist it in the           *
+ * development and the implementation, in accordance with Receiver's designs, *
+ * of certain softwares relating to Receiver's product(s) (the "Services").   *
+ * Except as may be otherwise agreed to in writing, no warranties of any      *
+ * kind, whether express or implied, are given by MediaTek Inc. with respect  *
+ * to the Services provided, and the Services are provided on an "AS IS"      *
+ * basis. Receiver further acknowledges that the Services may contain errors  *
+ * that testing is important and it is solely responsible for fully testing   *
+ * the Services and/or derivatives thereof before they are used, sublicensed  *
+ * or distributed. Should there be any third party action brought against     *
+ * MediaTek Inc. arising out of or relating to the Services, Receiver agree   *
+ * to fully indemnify and hold MediaTek Inc. harmless.  If the parties        *
+ * mutually agree to enter into or continue a business relationship or other  *
+ * arrangement, the terms and conditions set forth herein shall remain        *
+ * effective and, unless explicitly stated otherwise, shall prevail in the    *
+ * event of a conflict in the terms in any agreements entered into between    *
+ * the parties.                                                               *
+ *                                                                            *
+ *   4)Receiver's sole and exclusive remedy and MediaTek Inc.'s entire and    *
+ * cumulative liability with respect to MediaTek Software released hereunder  *
+ * will be, at MediaTek Inc.'s sole discretion, to replace or revise the      *
+ * MediaTek Software at issue.                                                *
+ *                                                                            *
+ *   5)The transaction contemplated hereunder shall be construed in           *
+ * accordance with the laws of Singapore, excluding its conflict of laws      *
+ * principles.  Any disputes, controversies or claims arising thereof and     *
+ * related thereto shall be settled via arbitration in Singapore, under the   *
+ * then current rules of the International Chamber of Commerce (ICC).  The    *
+ * arbitration shall be conducted in English. The awards of the arbitration   *
+ * shall be final and binding upon both parties and shall be entered and      *
+ * enforceable in any court of competent jurisdiction.                        *
+ *---------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------
+ *
+ * Description:
+ *
+ *---------------------------------------------------------------------------*/
+//vIO32WriteFldMulti
+//vIO32WriteFldMulti_All
+#ifndef X_HAL_IO_H
+#define X_HAL_IO_H
+
+#include "dramc_pi_api.h"
+//===========================================================================
+#define REG_ACCESS_NAO_DGB 0
+#define REG_ACCESS_PORTING_DGB 0
+#define REG_SHUFFLE_REG_CHECK 0
+
+// field access macro-----------------------------------------------------------
+
+/* field macros */
+#define Fld(wid, shft)    (((U32)wid << 16) | (shft << 8))
+#define Fld_wid(fld)    ((UINT8)((fld) >> 16))
+#define Fld_shft(fld)   ((UINT8)((fld) >> 8))
+#define Fld_ac(fld)     (UINT8)(fld)
+
+/* access method*/
+#define AC_FULLB0       1
+#define AC_FULLB1       2
+#define AC_FULLB2       3
+#define AC_FULLB3       4
+#define AC_FULLW10      5
+#define AC_FULLW21      6
+#define AC_FULLW32      7
+#define AC_FULLDW       8
+#define AC_MSKB0        11
+#define AC_MSKB1        12
+#define AC_MSKB2        13
+#define AC_MSKB3        14
+#define AC_MSKW10       15
+#define AC_MSKW21       16
+#define AC_MSKW32       17
+#define AC_MSKDW        18
+
+#define Fld2Msk32(fld)  /*lint -save -e504 */ (((U32)0xffffffff>>(32-Fld_wid(fld)))<<Fld_shft(fld)) /*lint -restore */
+#define P_Fld(val, fld) ( upk > 0 ? Fld2Msk32(fld): (((UINT32)(val) & ((1 << Fld_wid(fld)) - 1)) << Fld_shft(fld)))
+
+extern U32 u4Dram_Register_Read(DRAMC_CTX_T *p, U32 u4reg_addr);
+extern void ucDram_Register_Write(DRAMC_CTX_T *p, U32 u4reg_addr, U32 u4reg_value);
+
+extern void vIO32Write4BMsk2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32);
+extern void vIO32Write4BMsk_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32);
+extern void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32);
+
+// =========================
+// public Macro for general use. 
+//==========================
+#define u4IO32Read4B(reg32) u4Dram_Register_Read(p, reg32)
+#define vIO32Write4B(reg32, val32) ucDram_Register_Write(p, reg32, val32)
+#define vIO32Write4B_All(reg32, val32) vIO32Write4B_All2(p, reg32, val32)
+#define vIO32Write4BMsk(reg32, val32, msk32) vIO32Write4BMsk2(p, reg32, val32, msk32)
+#define vIO32Write4BMsk_All(reg32, val32, msk32) vIO32Write4BMsk_All2(p, reg32, val32, msk32)
+
+#define u4IO32ReadFldAlign(reg32, fld) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \
+	((u4IO32Read4B(reg32) & Fld2Msk32(fld)) >> Fld_shft(fld))
+
+#define vIO32WriteFldAlign(reg32, val, fld) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \
+	(vIO32Write4BMsk((reg32), ((U32)(val) << Fld_shft(fld)), Fld2Msk32(fld)))
+
+#define vIO32WriteFldMulti(reg32, list) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \
+{ \
+	UINT16 upk = 1; \
+	INT32 msk = (INT32)(list); \
+	{ upk = 0; \
+    ((U32)msk == 0xffffffff)? (vIO32Write4B(reg32, (list))): (((U32)msk)? vIO32Write4BMsk(reg32, (list), ((U32)msk)):(U32)0); \
+	} \
+}/*lint -restore */
+
+//=========================
+// Public Macro for write all-dramC or all-PHY registers
+//=========================
+#define vIO32WriteFldAlign_All(reg32, val, fld) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \
+	(vIO32Write4BMsk_All((reg32), ((U32)(val) << Fld_shft(fld)), Fld2Msk32(fld)))
+
+#define vIO32WriteFldMulti_All(reg32, list) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \
+{ \
+	UINT16 upk = 1; \
+	INT32 msk = (INT32)(list); \
+	{ upk = 0; \
+    ((U32)msk == 0xffffffff)? (vIO32Write4B_All(reg32, (list))): (((U32)msk)? vIO32Write4BMsk_All(reg32, (list), ((U32)msk)): (void)0); \
+	} \
+}/*lint -restore */
+
+#ifdef __DPM__
+#include "x_hal_io_dpm.h"
+#endif
+
+#endif  // X_HAL_IO_H