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| author | Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> | 2021-11-09 21:45:08 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-11 14:33:12 +0000 |
| commit | b11de6fa0993086557d4c503dcb1af7e0ef98d74 (patch) | |
| tree | 9c0f7adca4f649a582ae0737c48543ee35daea35 /src | |
| parent | fb05b820ebdf06a47cc36e189d86aea02637fe1a (diff) | |
| download | coreboot-b11de6fa0993086557d4c503dcb1af7e0ef98d74.tar.gz coreboot-b11de6fa0993086557d4c503dcb1af7e0ef98d74.tar.bz2 coreboot-b11de6fa0993086557d4c503dcb1af7e0ef98d74.zip | |
mb/google/brya/variants/gimble: Update audio setting for SmartAMP
Divide dsm_param_file_name into dsm_param_R and dsm_param_L
BUG=b:205684021
TEST=build and check SSDT
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie2db709a63152c1ccee2f7d594284e366ada8a01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59046
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/Kconfig.name | 1 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/gimble/overridetree.cb | 4 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index ed9d82c3d07c..8d58fa579980 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -27,6 +27,7 @@ config BOARD_GOOGLE_GIMBLE bool "-> Gimble" select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_DSM_CALIB if CHROMEOS + select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS select DRIVERS_I2C_MAX98390 config BOARD_GOOGLE_REDRIX diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 8448594c1e8a..c015009c0077 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -135,7 +135,7 @@ chip soc/intel/alderlake register "name" = ""MXW0"" register "r0_calib_key" = ""dsm_calib_r0_0"" register "temperature_calib_key" = ""dsm_calib_temp_0"" - register "dsm_param_file_name" = ""dsm_param"" + register "dsm_param_file_name" = ""dsm_param_R"" register "vmon_slot_no" = "0" register "imon_slot_no" = "1" device i2c 0x38 on @@ -147,7 +147,7 @@ chip soc/intel/alderlake register "name" = ""MXW1"" register "r0_calib_key" = ""dsm_calib_r0_1"" register "temperature_calib_key" = ""dsm_calib_temp_1"" - register "dsm_param_file_name" = ""dsm_param"" + register "dsm_param_file_name" = ""dsm_param_L"" register "vmon_slot_no" = "1" register "imon_slot_no" = "0" device i2c 0x3c on |