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| author | Tony Huang <tony-huang@quanta.corp-partner.google.com> | 2020-11-17 19:09:47 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-22 22:30:03 +0000 |
| commit | b37f2e9902ec94a0e9e647ce7774f9db57656121 (patch) | |
| tree | 8afb0e9ae2ea9ea7b3382e153d615715f1089632 /src | |
| parent | 08b862ef47bb5f4401b9d4dea4f77cba14bdbd5e (diff) | |
| download | coreboot-b37f2e9902ec94a0e9e647ce7774f9db57656121.tar.gz coreboot-b37f2e9902ec94a0e9e647ce7774f9db57656121.tar.bz2 coreboot-b37f2e9902ec94a0e9e647ce7774f9db57656121.zip | |
mb/google/puff/var/dooly: update USB2 type-c strength
Based on USB DB report.
BRANCH=puff
BUG=b:163561808
TEST=build and measure by EE team.
Change-Id: I379987b6d6d2a7aef33d4c42e589dc52d40205a3
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/variants/dooly/overridetree.cb | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index 6e2344874750..efa7d719a48e 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -27,7 +27,14 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_11P25MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 0 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 0 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 0 register "usb2_ports[2]" = "{ .enable = 1, .ocpin = OC3, @@ -37,7 +44,14 @@ chip soc/intel/cannonlake .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 1 register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 1 + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 1 register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # USB cam register "usb2_ports[6]" = "USB2_PORT_EMPTY" register "usb2_ports[7]" = "USB2_PORT_EMPTY" |