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| author | Tim Crawford <tcrawford@system76.com> | 2022-07-29 12:07:15 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-02 12:19:17 +0000 |
| commit | b739d80197d7a92ad357d0e45ea0f22b4a06b09f (patch) | |
| tree | 3d94a2418c96190d60660fa758eb7bb6a3d6e4fd /src | |
| parent | 60ac26521ede6fb58765b7b54898e73a08be8025 (diff) | |
| download | coreboot-b739d80197d7a92ad357d0e45ea0f22b4a06b09f.tar.gz coreboot-b739d80197d7a92ad357d0e45ea0f22b4a06b09f.tar.bz2 coreboot-b739d80197d7a92ad357d0e45ea0f22b4a06b09f.zip | |
soc/intel/alderlake: Add IRQ constraints for CPU PCIe ports
Copy the constraint from ADL-S to ADL-P.
Fixes the following warning in Linux on System76 oryp9, which has an
NVIDIA GPU on the bridge.
pcieport 0000:00:01.0: can't derive routing for PCI INT A
This, in turn, resolves an IRQ conflict with the PCH HDA device that
would cause a stack track on every boot.
irq 10: nobody cared (try booting with the "irqpoll" option)
<snip>
[<00000000bf549647>] azx_interrupt [snd_hda_codec]
Disabling IRQ #10
Change-Id: I550c80105ff861d051170ed748149aeb25a545db
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66285
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index ec4281d4b596..592afb8d974b 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -61,6 +61,12 @@ enum fsp_end_of_post { static const struct slot_irq_constraints irq_constraints[] = { { + .slot = SA_DEV_SLOT_CPU_1, + .fns = { + FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE1_0, PCI_INT_A, PIRQ_A), + }, + }, + { .slot = SA_DEV_SLOT_IGD, .fns = { /* INTERRUPT_PIN is RO/0x01 */ |