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| author | hao_chou <hao_chou@pegatron.corp-partner.google.com> | 2021-01-27 18:21:43 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-04 08:47:40 +0000 |
| commit | b967c60dc7085fd6b6c0bcb8badc1dfff9b988ac (patch) | |
| tree | 60bc28c92d0bf592c8fd5ac5765a9a6bd0070027 /src | |
| parent | abefcc2e2c68f94414f85e18d35b624186ddd12f (diff) | |
| download | coreboot-b967c60dc7085fd6b6c0bcb8badc1dfff9b988ac.tar.gz coreboot-b967c60dc7085fd6b6c0bcb8badc1dfff9b988ac.tar.bz2 coreboot-b967c60dc7085fd6b6c0bcb8badc1dfff9b988ac.zip | |
mb/google/volteer/variants/copano: Describe USB ports in devicetree
Modify USB port to match schematics.
And assigned USB2 port to type-c use.
BUG=b:177481079
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot
Change-Id: I25412d16df8ad809c05635022c11bd8882d002c5
Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49980
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/volteer/variants/copano/overridetree.cb | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/src/mainboard/google/volteer/variants/copano/overridetree.cb b/src/mainboard/google/volteer/variants/copano/overridetree.cb index 11921292385f..c331986f1595 100644 --- a/src/mainboard/google/volteer/variants/copano/overridetree.cb +++ b/src/mainboard/google/volteer/variants/copano/overridetree.cb @@ -11,7 +11,6 @@ chip soc/intel/tigerlake register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 # Disable SRCCLKREQ1# register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" @@ -167,14 +166,16 @@ chip soc/intel/tigerlake chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 2)" + register "group" = "ACPI_PLD_GROUP(4, 2)" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 2)" - device ref tcss_usb3_port2 on end + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB4_GEN3 + end end end end @@ -186,24 +187,26 @@ chip soc/intel/tigerlake register "desc" = ""USB2 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(1, 1)" - device ref usb2_port2 on end + device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device ref usb2_port4 on end + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on + probe DB_USB USB4_GEN3 + end end chip drivers/usb/acpi register "desc" = ""USB2 Camera"" register "type" = "UPC_TYPE_INTERNAL" - device ref usb2_port5 on end + device ref usb2_port4 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" - device ref usb2_port9 on end + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port5 on end end chip drivers/usb/acpi register "desc" = ""USB2 Bluetooth"" |