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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-03-07 09:10:31 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-11 16:56:17 +0100 |
| commit | bbfcf625124da70f67675f2f85aec44ecda00b3e (patch) | |
| tree | 9c64fcd19f68f41199168fe773fed6dfaf85b22e /src | |
| parent | 7109304cf241e22923d83344050eb6b30b31484d (diff) | |
| download | coreboot-bbfcf625124da70f67675f2f85aec44ecda00b3e.tar.gz coreboot-bbfcf625124da70f67675f2f85aec44ecda00b3e.tar.bz2 coreboot-bbfcf625124da70f67675f2f85aec44ecda00b3e.zip | |
nb/amd/mct_ddr3: Restore previous DQS delay values on failed loop
Change-Id: Iacfcd7f379d09a633973b4c3ef3cbb97e6d1f09f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13931
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 19a7acb329df..1a3c7c1aa67c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1522,6 +1522,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 143 largest read passing region start ", best_pos, 4); print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 144 largest read passing region center (raw hardware value) ", region_center, 4); } else { + /* Restore current settings of other (previously trained) lanes to the active array */ + memcpy(current_read_dqs_delay, initial_read_dqs_delay, sizeof(current_read_dqs_delay)); + /* Reprogram the Read DQS Timing Control register with the original settings */ write_dqs_read_data_timing_registers(initial_read_dqs_delay, dev, dct, dimm, index_reg); } @@ -1571,6 +1574,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 145 largest write passing region ", best_count, 4); print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 146 largest write passing region start ", best_pos, 4); } else { + /* Restore current settings of other (previously trained) lanes to the active array */ + memcpy(current_write_dqs_delay, initial_write_data_timing, sizeof(current_write_data_delay)); + /* Reprogram the Write DQS Timing Control register with the original settings */ write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, dct, dimm, index_reg); } |