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| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-10-18 19:54:21 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2021-10-20 15:42:51 +0000 |
| commit | bc5f51fa56166e6c2dff273fefba4f3ea7e8bac2 (patch) | |
| tree | 90ad1300c26ebcdee06ba0dbfb4d85b817e7cbe5 /src | |
| parent | e874375394f81eddeb7f9a89e1351cb71c43670c (diff) | |
| download | coreboot-bc5f51fa56166e6c2dff273fefba4f3ea7e8bac2.tar.gz coreboot-bc5f51fa56166e6c2dff273fefba4f3ea7e8bac2.tar.bz2 coreboot-bc5f51fa56166e6c2dff273fefba4f3ea7e8bac2.zip | |
soc/intel/{skl,apl}: don't run or even include SGX code if disabled
Do not run or include any code in case the user did not explicitly
enable SGX through `SOC_INTEL_COMMON_BLOCK_SGX_ENABLE`.
Also move the ifdef inside the ASL file.
Change-Id: Iec4d3d3eb2811ec14d29aff9601ba325724bc28c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/acpi/southbridge.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/acpi/sgx.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/sgx/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/acpi/pch.asl | 2 |
5 files changed, 4 insertions, 6 deletions
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 6e3bde4bb99c..4f5029e5acd6 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -88,7 +88,7 @@ void soc_fill_gnvs(struct global_nvs *gnvs) gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio); } - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) sgx_fill_gnvs(gnvs); /* Fill in Above 4GB MMIO resource */ diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index f4d1497223fc..f857bb97a07c 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -30,6 +30,4 @@ #include <soc/intel/common/acpi/pci_osc.asl> /* SGX */ -#if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) #include <soc/intel/common/acpi/sgx.asl> -#endif diff --git a/src/soc/intel/common/acpi/sgx.asl b/src/soc/intel/common/acpi/sgx.asl index c0b804072931..9aea7a8b09c4 100644 --- a/src/soc/intel/common/acpi/sgx.asl +++ b/src/soc/intel/common/acpi/sgx.asl @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) Scope(\_SB) { // Secure Enclave memory @@ -54,3 +55,4 @@ Scope(\_SB) } // end EPC Device } // End of Scope(\_SB) +#endif diff --git a/src/soc/intel/common/block/sgx/Makefile.inc b/src/soc/intel/common/block/sgx/Makefile.inc index 3fa18d887344..ce3c436141fa 100644 --- a/src/soc/intel/common/block/sgx/Makefile.inc +++ b/src/soc/intel/common/block/sgx/Makefile.inc @@ -1 +1 @@ -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX) += sgx.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) += sgx.c diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index e088ca1782fc..0aa8f9576117 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -62,6 +62,4 @@ Method (_OSC, 4) } /* SGX */ -#if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) #include <soc/intel/common/acpi/sgx.asl> -#endif |