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authorCK Hu <ck.hu@mediatek.com>2020-07-01 15:01:04 +0800
committerHung-Te Lin <hungte@chromium.org>2020-10-28 02:01:10 +0000
commitbd0a222ab44277ab48b8bf95419ae310b8ccf82e (patch)
tree8e3b9404998932635c9f672589232c5f74f1cbb8 /src
parentfc38e8834132f83ed59e6b0f59bd90c940edd991 (diff)
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mb/google/asurada: Pass reset gpio parameter to BL31
To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: I2ae7684a61af76693605cc0bcf8d20c8992c7bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/46388 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/asurada/mainboard.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c
index 7a37df576405..8699ede77259 100644
--- a/src/mainboard/google/asurada/mainboard.c
+++ b/src/mainboard/google/asurada/mainboard.c
@@ -1,16 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <bl31.h>
#include <console/console.h>
#include <device/device.h>
#include <device/mmio.h>
#include <soc/gpio.h>
#include <soc/usb.h>
+#include "gpio.h"
+
+#include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h>
+
#define MSDC0_DRV_MASK 0x3fffffff
#define MSDC1_DRV_MASK 0x3ffff000
#define MSDC0_DRV_VALUE 0x24924924
#define MSDC1_DRV_VALUE 0x24924000
+static void register_reset_to_bl31(void)
+{
+ static struct bl_aux_param_gpio param_reset = {
+ .h = { .type = BL_AUX_PARAM_MTK_RESET_GPIO },
+ .gpio = { .polarity = ARM_TF_GPIO_LEVEL_HIGH },
+ };
+
+ param_reset.gpio.index = GPIO_RESET.id;
+ register_bl31_aux_param(&param_reset.h);
+}
+
static void configure_emmc(void)
{
void *gpio_base = (void *)IOCFG_TL_BASE;
@@ -68,6 +84,8 @@ static void mainboard_init(struct device *dev)
configure_emmc();
configure_sdcard();
setup_usb_host();
+
+ register_reset_to_bl31();
}
static void mainboard_enable(struct device *dev)