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| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2021-04-28 15:02:47 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-02 18:32:20 +0000 |
| commit | be5dc3daa00414ae04b1801f59142245e0e4d17f (patch) | |
| tree | e0e38d50a2923527175edd72177d90ef2aca1968 /src | |
| parent | b85997df25863870405360fdc0c9b1fa6221a9c0 (diff) | |
| download | coreboot-be5dc3daa00414ae04b1801f59142245e0e4d17f.tar.gz coreboot-be5dc3daa00414ae04b1801f59142245e0e4d17f.tar.bz2 coreboot-be5dc3daa00414ae04b1801f59142245e0e4d17f.zip | |
soc/intel/alderlake: Configure DDR5 Physical channel width to 64
A DDR5 DIMM internally has two channels each of width 32 bit.
But the total physical channel width is 64 bit.
BUG=b:180458099
TEST=Boot DDR5 to kernel
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: Ic5e9c58f255bdf86a68ce90a4f853bf4e7c7ccfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52730
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/meminit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index d40ee35e73bf..8b5e0071ef32 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -11,7 +11,7 @@ #define DDR4_PHYSICAL_CH_WIDTH 64 #define DDR4_CHANNELS CHANNEL_COUNT(DDR4_PHYSICAL_CH_WIDTH) -#define DDR5_PHYSICAL_CH_WIDTH 32 +#define DDR5_PHYSICAL_CH_WIDTH 64 /* 32*2 */ #define DDR5_CHANNELS CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH) static void set_rcomp_config(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg) |