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| author | Sean Rhodes <sean@starlabs.systems> | 2022-06-01 11:32:05 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-19 12:19:04 +0000 |
| commit | be8cd6ba61f6c240b543df181a4aa7fe4a4f163b (patch) | |
| tree | 6d556b6dc72750554b6c1c7b06e97f07bdc3a39c /src | |
| parent | 7c5a9c7cb0cf6605435aa4c885c637273f9a0eee (diff) | |
| download | coreboot-be8cd6ba61f6c240b543df181a4aa7fe4a4f163b.tar.gz coreboot-be8cd6ba61f6c240b543df181a4aa7fe4a4f163b.tar.bz2 coreboot-be8cd6ba61f6c240b543df181a4aa7fe4a4f163b.zip | |
soc/intel/apollolake: Call heci_init in romstage
Call heci_init to initialise all Heci devices and bring them to d0.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id2865b649331846fc119da7c4be56cc1fed56b8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index f39a0b0d3639..757bad3e1fba 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -13,6 +13,7 @@ #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> +#include <intelblocks/cse.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/msr.h> #include <intelblocks/pmclib.h> @@ -164,6 +165,9 @@ void mainboard_romstage_entry(void) soc_early_romstage_init(); report_platform_info(); + /* Initialize Heci interfaces */ + heci_init(); + s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); |