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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-06-17 12:42:35 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-06-30 22:19:35 +0000 |
| commit | c0e82e705d9a4747b1ccf7e6863c91c1e01bada7 (patch) | |
| tree | 14e6c4b1b048293baa0e30f0d26b6ccf53b7ad1a /src | |
| parent | 9fdd2b264b1163009b5c3b0fd0a78df88d719192 (diff) | |
| download | coreboot-c0e82e705d9a4747b1ccf7e6863c91c1e01bada7.tar.gz coreboot-c0e82e705d9a4747b1ccf7e6863c91c1e01bada7.tar.bz2 coreboot-c0e82e705d9a4747b1ccf7e6863c91c1e01bada7.zip | |
soc/intel/alderlake: Send End-of-Post message to CSE
This is done to ensure the CSE will not execute any pre-boot commands
after it receives this command. Verified EOP and error recovery sequence
from Intel doc#627331.
TEST=on brya, autotest firmware_CheckEOPState confirms ME is in
post-boot state
Change-Id: Iee8c29f81d5d04852ae3f16dc8a9ff0fa59f056a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 16 |
2 files changed, 16 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b590dfaab788..375fedc434ed 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -75,6 +75,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET + select SOC_INTEL_CSE_SET_EOP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 612bc4ed3195..c814d8c3ee3b 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -32,6 +32,18 @@ #define DEF_DMVAL 15 #define DEF_DITOVAL 625 +/* + * ME End of Post configuration + * 0 - Disable EOP. + * 1 - Send in PEI (Applicable for FSP in API mode) + * 2 - Send in DXE (Not applicable for FSP in API mode) + */ +enum fsp_end_of_post { + EOP_DISABLE = 0, + EOP_PEI = 1, + EOP_DXE = 2, +}; + static const struct slot_irq_constraints irq_constraints[] = { { .slot = SA_DEV_SLOT_IGD, @@ -309,6 +321,9 @@ static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, s_cfg->PchUnlockGpioPads = 0; s_cfg->RtcMemoryLock = 1; } + + /* coreboot will send EOP before loading payload */ + s_cfg->EndOfPostMessage = EOP_DISABLE; } static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg, @@ -569,7 +584,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd; config = config_of_soc(); - arch_silicon_init_params(s_arch_cfg); soc_silicon_init_params(s_cfg, config); mainboard_silicon_init_params(s_cfg); |