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| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-23 22:40:33 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-30 00:47:07 +0000 |
| commit | c3a6d4b2c70472a952db1187e5555ea6a8558ad6 (patch) | |
| tree | 93258f1866baea89303c67f331e87ad1eb7cd9e3 /src | |
| parent | 071754c9dc8b68ef63481688a787be3d8bc17bf2 (diff) | |
| download | coreboot-c3a6d4b2c70472a952db1187e5555ea6a8558ad6.tar.gz coreboot-c3a6d4b2c70472a952db1187e5555ea6a8558ad6.tar.bz2 coreboot-c3a6d4b2c70472a952db1187e5555ea6a8558ad6.zip | |
soc/intel/broadwell: Drop reg-script to finalize PCH
Tested on out-of-tree Acer Aspire E5-573, still boots.
Change-Id: I3b9ae75842e3ec1ecd02323d104a9f1d45564172
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46710
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/broadwell/pch/finalize.c | 32 |
1 files changed, 12 insertions, 20 deletions
diff --git a/src/soc/intel/broadwell/pch/finalize.c b/src/soc/intel/broadwell/pch/finalize.c index 37afded317e8..71f06390e0d3 100644 --- a/src/soc/intel/broadwell/pch/finalize.c +++ b/src/soc/intel/broadwell/pch/finalize.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci_ops.h> -#include <reg_script.h> #include <spi-generic.h> #include <soc/pci_devs.h> #include <soc/lpc.h> @@ -10,38 +9,31 @@ #include <soc/spi.h> #include <southbridge/intel/common/spi.h> -const struct reg_script pch_finalize_script[] = { -#if !CONFIG(EM100PRO_SPI_CONSOLE) +void broadwell_pch_finalize(void) +{ + spi_finalize_ops(); + /* Lock SPIBAR */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS, - SPIBAR_HSFS_FLOCKDN), -#endif + if (!CONFIG(EM100PRO_SPI_CONSOLE)) + RCBA32_OR(SPIBAR_OFFSET + SPIBAR_HSFS, SPIBAR_HSFS_FLOCKDN); /* TC Lockdown */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)), + RCBA32_OR(0x0050, 1 << 31); /* BIOS Interface Lockdown */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)), + RCBA32_OR(GCS, 1 << 0); /* Function Disable SUS Well Lockdown */ - REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)), + RCBA8(FDSW) |= 1 << 7; /* Global SMI Lock */ - REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK), + pci_or_config16(PCH_DEV_LPC, GEN_PMCON_1, SMI_LOCK); /* GEN_PMCON Lock */ - REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK), + pci_or_config8(PCH_DEV_LPC, GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK); /* PMSYNC */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)), - - REG_SCRIPT_END -}; - -void broadwell_pch_finalize(void) -{ - spi_finalize_ops(); - reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script); + RCBA32_OR(PMSYNC_CONFIG, 1 << 31); /* Lock */ RCBA32_OR(0x3a6c, 0x00000001); |