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| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2021-09-30 20:46:15 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-11 15:16:16 +0000 |
| commit | c3a9e5371453c9ce713ce6625105bde66ff28d76 (patch) | |
| tree | 2a2359064778d161cafde20132631701ed80d7d0 /src | |
| parent | 0cd81c325c631108db255546229a95ec2c4fd82b (diff) | |
| download | coreboot-c3a9e5371453c9ce713ce6625105bde66ff28d76.tar.gz coreboot-c3a9e5371453c9ce713ce6625105bde66ff28d76.tar.bz2 coreboot-c3a9e5371453c9ce713ce6625105bde66ff28d76.zip | |
mb/google/guybrush/bootblock: add comment to PM_ACPI_CONF write
Document what setting the PM_ACPI_S5_LPC_PIN_MODE and
PM_ACPI_S5_LPC_PIN_MODE_SEL bits causes. The corresponding code will
eventually be factored out and moved to the Cezanne SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I10e3eee5cfc1c5ba2c88b8b7e83e96e481f787e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/guybrush/bootblock.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 3f7d5a1bf525..9c9fce7e8d9c 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -61,6 +61,7 @@ void bootblock_mainboard_early_init(void) dword |= PM_ESPI_CS_USE_DATA2; pm_write32(PM_SPI_PAD_PU_PD, dword); + /* Switch the pads that can be used as either LPC or secondary eSPI to 1.8V mode */ dword = pm_read32(PM_ACPI_CONF); dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; pm_write32(PM_ACPI_CONF, dword); |