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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-09-26 12:12:20 +0530 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-10-06 18:18:31 +0000 |
| commit | cb4d46463345449f353707f6701626cd57990587 (patch) | |
| tree | fd054d6800f0b7fc3ea9e9307d16486e5b0476d3 /src | |
| parent | a0f3b86e1336be209a43cbd08f9a95e0ebb5e201 (diff) | |
| download | coreboot-cb4d46463345449f353707f6701626cd57990587.tar.gz coreboot-cb4d46463345449f353707f6701626cd57990587.tar.bz2 coreboot-cb4d46463345449f353707f6701626cd57990587.zip | |
soc/intel/meteorlake: Make use of is_devfn_enabled() function
The patch uses is_devfn_enabled() function to enable the TBT PCIe ports
through FSP-M and FSP-S UPDs. Also, removes unused tbt_pcie_port_disable
array member from soc_intel_meteorlake_config struct.
TEST=Build coreboot for Google/Rex
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ie55e196bd8f682864b8f74dbe253f345d7184753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/meteorlake/chip.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/fsp_params.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 10 |
3 files changed, 6 insertions, 12 deletions
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 04b8299b2da1..1d335c574e5f 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -125,7 +125,6 @@ struct soc_intel_meteorlake_config { uint16_t usb3_wake_enable_bitmap; /* Program OC pins for TCSS */ struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS]; - uint8_t tbt_pcie_port_disable[4]; /* Validate TBT firmware authenticated and loaded into IMR */ bool tbt_authentication; diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index e3c85600a1a9..c727fb31aafe 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -337,11 +337,8 @@ static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg, static void fill_fsps_tbt_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_meteorlake_config *config) { - int max_port = get_max_tbt_pcie_port(); - - memset(s_cfg->ITbtPcieRootPortEn, 0, sizeof(s_cfg->ITbtPcieRootPortEn)); - for (int i = 0; i < max_port; i++) - s_cfg->ITbtPcieRootPortEn[i] = !(config->tbt_pcie_port_disable[i]); + for (int i = 0; i < ARRAY_SIZE(s_cfg->ITbtPcieRootPortEn); i++) + s_cfg->ITbtPcieRootPortEn[i] = is_devfn_enabled(PCI_DEVFN_TBT(i)); } static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg, diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 74ea88d6b505..60324e98275d 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -226,12 +226,10 @@ static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_usb4_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_meteorlake_config *config) { - memset(&m_cfg->TcssItbtPcie0En, 0, sizeof(m_cfg->TcssItbtPcie0En)*4); - - m_cfg->TcssItbtPcie0En = !(config->tbt_pcie_port_disable[0]); - m_cfg->TcssItbtPcie1En = !(config->tbt_pcie_port_disable[1]); - m_cfg->TcssItbtPcie2En = !(config->tbt_pcie_port_disable[2]); - m_cfg->TcssItbtPcie3En = !(config->tbt_pcie_port_disable[3]); + m_cfg->TcssItbtPcie0En = is_devfn_enabled(PCI_DEVFN_TBT0); + m_cfg->TcssItbtPcie1En = is_devfn_enabled(PCI_DEVFN_TBT1); + m_cfg->TcssItbtPcie2En = is_devfn_enabled(PCI_DEVFN_TBT2); + m_cfg->TcssItbtPcie3En = is_devfn_enabled(PCI_DEVFN_TBT3); } static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, |