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| author | V Sowmya <v.sowmya@intel.com> | 2020-12-17 08:03:03 +0530 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-21 02:36:40 +0000 |
| commit | ce07b5c0ab304b2f13bbebd731dd1a8fc1077446 (patch) | |
| tree | 0af9131f4a65e8b2a37e46bb9d7b21031f15ce1a /src | |
| parent | 04da829a0f4fa997514dc3131251f6f849158131 (diff) | |
| download | coreboot-ce07b5c0ab304b2f13bbebd731dd1a8fc1077446.tar.gz coreboot-ce07b5c0ab304b2f13bbebd731dd1a8fc1077446.tar.bz2 coreboot-ce07b5c0ab304b2f13bbebd731dd1a8fc1077446.zip | |
mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board
This patch adds initial support for Alderlake Intel Pre-CEP
board called shadowmountain.
BUG=b:175808146
TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max
Change-Id: I9cb650c88986badd6733b001d6f2a0e338421829
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
5 files changed, 52 insertions, 0 deletions
diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig new file mode 100644 index 000000000000..a822bcc350d1 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -0,0 +1,25 @@ +if BOARD_INTEL_SHADOWMOUNTAIN + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_TABLES + select SOC_INTEL_ALDERLAKE + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config MAINBOARD_DIR + string + default "intel/shadowmountain" + +config MAINBOARD_FAMILY + string + default "Intel_shadowmountain" + +config MAINBOARD_PART_NUMBER + string + default "shadowmountain" + +endif # BOARD_INTEL_SHADOWMOUNTAIN diff --git a/src/mainboard/intel/shadowmountain/Kconfig.name b/src/mainboard/intel/shadowmountain/Kconfig.name new file mode 100644 index 000000000000..e48903940058 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_SHADOWMOUNTAIN + bool "shadowmountain" diff --git a/src/mainboard/intel/shadowmountain/board_info.txt b/src/mainboard/intel/shadowmountain/board_info.txt new file mode 100644 index 000000000000..7e0cccf015d5 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Alderlake Pre-CEP +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/shadowmountain/dsdt.asl b/src/mainboard/intel/shadowmountain/dsdt.asl new file mode 100644 index 000000000000..10d08e26e2db --- /dev/null +++ b/src/mainboard/intel/shadowmountain/dsdt.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ +} diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb new file mode 100644 index 000000000000..fbd7d72f9f59 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -0,0 +1,5 @@ +chip soc/intel/alderlake + device cpu_cluster 0 on + device lapic 0 on end + end +end |