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| author | Werner Zeh <werner.zeh@siemens.com> | 2022-12-22 11:09:34 +0100 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-01-10 00:30:59 +0000 |
| commit | ce6cdb360810938ab5800cb2d9f4f3c6e4d9fad8 (patch) | |
| tree | 91afbcb8c131fd374f08935e1da430e285effe1f /src | |
| parent | 921bb34c919a617706f269b89333b5dede59880f (diff) | |
| download | coreboot-ce6cdb360810938ab5800cb2d9f4f3c6e4d9fad8.tar.gz coreboot-ce6cdb360810938ab5800cb2d9f4f3c6e4d9fad8.tar.bz2 coreboot-ce6cdb360810938ab5800cb2d9f4f3c6e4d9fad8.zip | |
mb/siemens/mc_ehl1: Limit SATA speed to Gen 2
Due to mainboard restrictions a SATA link at Gen 3 (6 Gbps) can cause
issues as the margin is not big enough. Limit SATA speed to Gen 2 to
achieve a more robust SATA connection.
Change-Id: Ia79998db5f959528a4e8e29e570a7f55283adee1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71230
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 319a84372247..82070785fcfc 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -82,6 +82,7 @@ chip soc/intel/elkhartlake register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[1]" = "0" + register "SataSpeed" = "SATA_GEN2" register "ScsEmmcHs400Enabled" = "0" register "ScsEmmcDdr50Enabled" = "1" |