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| author | Subrata Banik <subratabanik@google.com> | 2022-01-03 19:19:41 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-21 16:01:54 +0000 |
| commit | cef6770a0bf0cbe06a044ada7a28812cbd22afe8 (patch) | |
| tree | 72dac410d5f59803eaf164190dd5c9c207550eec /src | |
| parent | 0ddb47048d064087bf8c3e206bead1fa55f4e918 (diff) | |
| download | coreboot-cef6770a0bf0cbe06a044ada7a28812cbd22afe8.tar.gz coreboot-cef6770a0bf0cbe06a044ada7a28812cbd22afe8.tar.bz2 coreboot-cef6770a0bf0cbe06a044ada7a28812cbd22afe8.zip | |
soc/intel/icl: Rework on HECI1 disable configs
The only option to make HECI1 function disable on Ice Lake SoC
platform is using SBI under SMM mode. Hence, this patch makes
DISABLE_HECI1_AT_PRE_BOOT=y default and selects
`HECI_DISABLE_USING_SMM` config for Ice Lake.
Also, drop `HeciEnabled` from chip configuration and guard
heci_disable() using DISABLE_HECI1_AT_PRE_BOOT config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If4155e5c7eeb019f7dce59acd5b82720baddcb43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/icelake/Kconfig | 5 | ||||
| -rw-r--r-- | src/soc/intel/icelake/chip.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/icelake/smihandler.c | 6 |
3 files changed, 5 insertions, 10 deletions
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 0a22549e9ea8..cee38c9d748f 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -61,9 +61,12 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO - select HECI_DISABLE_USING_SMM select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI +config DISABLE_HECI1_AT_PRE_BOOT + default y if MAINBOARD_HAS_CHROMEOS + select HECI_DISABLE_USING_SMM + config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 9adc5b056569..05ec99c0b5c0 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -134,10 +134,6 @@ struct soc_intel_icelake_config { uint8_t Device4Enable; - /* HeciEnabled decides the state of Heci1 at end of boot - * Setting to 0 (default) disables Heci1 and hides the device from OS */ - uint8_t HeciEnabled; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 2ca2816a205e..5fb4f43378ca 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -16,11 +16,7 @@ */ void smihandler_soc_at_finalize(void) { - const struct soc_intel_icelake_config *config; - - config = config_of_soc(); - - if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) heci_disable(); } |