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| author | Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> | 2021-01-14 14:23:21 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-22 14:25:58 +0000 |
| commit | d6375cf556fb7a4612a441c4d32f93fa57556f3a (patch) | |
| tree | 666d0b8511c53eea0d4faca0201cdaf9c1146fd3 /src | |
| parent | 37765930ecebb0caf3abc71ffbf192f5e7cdfc8d (diff) | |
| download | coreboot-d6375cf556fb7a4612a441c4d32f93fa57556f3a.tar.gz coreboot-d6375cf556fb7a4612a441c4d32f93fa57556f3a.tar.bz2 coreboot-d6375cf556fb7a4612a441c4d32f93fa57556f3a.zip | |
mb/google/volteer/variants/eldrid: Configure USB2 port for Type-C
1. USB2 ports 3 and 8 assigned to Type-C connector
2. USB2 port 3 keep USB2_PORT_SHORT setting and add .type_c flag
BUG=b:177481076
TEST=tested on eldrid
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I42a39318a151bdf1f5aeb84bb1992be128cb4a4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/volteer/variants/eldrid/overridetree.cb | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 08d013e94115..d7ea9d3d6f38 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -66,7 +66,15 @@ chip soc/intel/tigerlake register "usb2_ports[2]" = "USB2_PORT_EMPTY" #improve the USB2 Port1 eye diagram - register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_39P35MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_39P35MV, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + .type_c = 1, + }" #lower camera driving register "usb2_ports[4]" = "{ @@ -77,6 +85,9 @@ chip soc/intel/tigerlake .pre_emp_bit = 0, }" + #Type-A / Type-C C0 + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" + device domain 0 on device ref dptf on # DPTF Policy for Eldrid board |