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| author | Tobias Diedrich <ranma+openocd@tdiedrich.de> | 2017-02-20 02:46:19 +0100 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-02-22 01:03:23 +0100 |
| commit | d8a2c1fb17b040dc81ca9da873bfcea41c1fe946 (patch) | |
| tree | 2596c91ac33fddaae6392590f4662dd5ec7daaf2 /src | |
| parent | c248044b20d270d14cf460b04972b7ff741685d0 (diff) | |
| download | coreboot-d8a2c1fb17b040dc81ca9da873bfcea41c1fe946.tar.gz coreboot-d8a2c1fb17b040dc81ca9da873bfcea41c1fe946.tar.bz2 coreboot-d8a2c1fb17b040dc81ca9da873bfcea41c1fe946.zip | |
southbridge/amd: Add LPC bridge acpi path for Family14 and SB800
Adds the necessary plumbing for acpi_device_path() to find the LPC
bridge on the AMD Family14 northbridge with an SB800 southbridge.
This is necessary for TPM support since the acpi path to the LPC bridge
(_SB.PCI0.ISAB) doesn't match the built-in default in tpm.c
(_SB.PCI0.LPCB).
Change-Id: I1ba5865d3531d8a4f41399802d58aacdf95fc604
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/18402
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/amd/agesa/family14/northbridge.c | 9 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/late.c | 16 |
2 files changed, 25 insertions, 0 deletions
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 15bb1aa20944..b8d9c6fa6a9d 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -638,6 +638,14 @@ static void domain_enable_resources(device_t dev) printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); } +static const char *domain_acpi_name(struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + return NULL; +} + /* Bus related code */ static void cpu_bus_scan(struct device *dev) @@ -813,6 +821,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, + .acpi_name = domain_acpi_name, }; static struct device_operations cpu_bus_ops = { diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index fa47a96f2ee0..a7076a6b6185 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -34,6 +34,7 @@ #include "sb_cimx.h" /* AMD CIMX wrapper entries */ #include "smbus.h" #include "fan.h" +#include "pci_devs.h" #include <southbridge/amd/common/amd_pci_util.h> /*implement in mainboard.c*/ @@ -150,6 +151,20 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } +static const char *lpc_acpi_name(struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + /* DSDT: acpi/lpc.asl */ + case LPC_DEVFN: + return "LIBR"; + } + + return NULL; +} + static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, @@ -160,6 +175,7 @@ static struct device_operations lpc_ops = { .init = lpc_init, .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, + .acpi_name = lpc_acpi_name, }; static const struct pci_driver lpc_driver __pci_driver = { |