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| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-10-17 09:54:12 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:48:39 +0000 |
| commit | dbd9ea070ede099970e5a9deb50c6fe3aeda0f6a (patch) | |
| tree | 87f0c3748d1fefa83810fb42901c7ba4656e5917 /src | |
| parent | 63405dacb73f9950e082ff88b79f472741c87b75 (diff) | |
| download | coreboot-dbd9ea070ede099970e5a9deb50c6fe3aeda0f6a.tar.gz coreboot-dbd9ea070ede099970e5a9deb50c6fe3aeda0f6a.tar.bz2 coreboot-dbd9ea070ede099970e5a9deb50c6fe3aeda0f6a.zip | |
soc/amd/stoneyridge: Remove DEV_D18F4 definition
The definition DEV_D18F4 is only used once, in file tsc_freq.c, and is
the same as SOC_PM_DEV. Remove the definition, and replace its use in
tsc_freq.c with SOC_PM_DEV.
BUG=b:117754424
TEST=Build and boot grunt.
Change-Id: I9eeeaa084e5b16280713b8b833b4faa78d277586
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/pci_devs.h | 6 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/tsc_freq.c | 2 |
2 files changed, 1 insertions, 7 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 865cf7170a15..5fddc52dc5bc 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -145,12 +145,6 @@ #define PM_DEVID 0x15b4 #define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC) #define SOC_PM_DEV _SOC_DEV(PM_DEV, PM_FUNC) -#if !defined(__SIMPLE_DEVICE__) - #include <device/device.h> - #define DEV_D18F4 dev_find_slot(0, PM_DEVFN) -#else - #define DEV_D18F4 PCI_DEV(0, PM_DEV, PM_FUNC) -#endif /* Northbridge Configuration */ #define NB_DEV 0x18 diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c index 8c1888400173..a8ed7c6a4c76 100644 --- a/src/soc/amd/stoneyridge/tsc_freq.c +++ b/src/soc/amd/stoneyridge/tsc_freq.c @@ -36,7 +36,7 @@ unsigned long tsc_freq_mhz(void) * to the "Software P-state Numbering" section, P0 is the highest * non-boosted state. freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)). */ - boost_states = (pci_read_config32(DEV_D18F4, CORE_PERF_BOOST_CTRL) + boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) >> 2) & 0x7; msr = rdmsr(PSTATE_0_MSR + boost_states); |