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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-15 22:31:33 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-21 11:01:23 +0000 |
| commit | e05f81a3e0e51e7e1d8b907399a6ac887cee37fe (patch) | |
| tree | 7690604ea7dcb0a87e8bc36353b77a3238177df6 /src | |
| parent | 98d580b8fbd2cf9ccafc2dd0ad48ae7d5ba86186 (diff) | |
| download | coreboot-e05f81a3e0e51e7e1d8b907399a6ac887cee37fe.tar.gz coreboot-e05f81a3e0e51e7e1d8b907399a6ac887cee37fe.tar.bz2 coreboot-e05f81a3e0e51e7e1d8b907399a6ac887cee37fe.zip | |
soc/intel/quark: Add pwrs in <soc/nvs.h>
For the time being every soc/intel selects ACPI_SOC_NVS
and pwrs is a required field for the common initialisation
implementation of followup work.
Change-Id: I4a0c7eb35f0646898e49fad15c6448607c398731
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49493
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/quark/include/soc/nvs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/quark/include/soc/nvs.h b/src/soc/intel/quark/include/soc/nvs.h index 904607ff35b7..fee0e42a7dfc 100644 --- a/src/soc/intel/quark/include/soc/nvs.h +++ b/src/soc/intel/quark/include/soc/nvs.h @@ -7,6 +7,7 @@ struct __packed global_nvs { uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */ + uint8_t pwrs; /* 0x4 - Power state (AC = 1) */ }; #endif /* SOC_INTEL_QUARK_NVS_H */ |