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| author | Aaron Durbin <adurbin@chromium.org> | 2016-02-10 10:56:06 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-19 19:50:10 +0100 |
| commit | e0969aec2573872b9f528e33edd2cf3fb84c5948 (patch) | |
| tree | 25c7b837e62b40d6261ac9a58a190dc321e736a4 /src | |
| parent | f6ada1c30755f3de22942996bfcf6490a9b7b6e4 (diff) | |
| download | coreboot-e0969aec2573872b9f528e33edd2cf3fb84c5948.tar.gz coreboot-e0969aec2573872b9f528e33edd2cf3fb84c5948.tar.bz2 coreboot-e0969aec2573872b9f528e33edd2cf3fb84c5948.zip | |
x86: add coreboot table entry for TSC info
The 8254 (Programmable Interrupt Timer) is becoming optional
on x86 platforms -- either from saving power or not including it
at all. To allow a payload to still use a TSC without doing
calibration provide the TSC frequency information in the coreboot
tables. That data is provided by code/logic already employed
by platform. If tsc_freq_mhz() returns 0 or
CONFIG_TSC_CONSTANT_RATE is not selected the coreboot table
record isn't created.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=With all subsequent patches confirmed TSC is picked up in
libpayload.
Change-Id: Iaeadb85c2648587debcf55f4fa5351d0c287e971
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13670
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/x86/cpu.c | 18 | ||||
| -rw-r--r-- | src/commonlib/include/commonlib/coreboot_tables.h | 8 |
2 files changed, 26 insertions, 0 deletions
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 5afae8b486a1..cba105a5db24 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -19,6 +19,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> +#include <cpu/x86/tsc.h> #include <arch/cpu.h> #include <device/path.h> #include <device/device.h> @@ -291,4 +292,21 @@ void cpu_initialize(unsigned int index) void lb_arch_add_records(struct lb_header *header) { + uint32_t freq_khz; + struct lb_tsc_info *tsc_info; + + /* Don't advertise a TSC rate unless it's constant. */ + if (!IS_ENABLED(CONFIG_TSC_CONSTANT_RATE)) + return; + + freq_khz = tsc_freq_mhz() * 1000; + + /* No use exposing a TSC frequency that is zero. */ + if (freq_khz == 0) + return; + + tsc_info = (void *)lb_new_record(header); + tsc_info->tag = LB_TAG_TSC_INFO; + tsc_info->size = sizeof(*tsc_info); + tsc_info->freq_khz = freq_khz; } diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 43adb093755c..5c2879159445 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -335,6 +335,14 @@ struct lb_cbmem_entry { uint32_t id; }; +#define LB_TAG_TSC_INFO 0x0032 +struct lb_tsc_info { + uint32_t tag; + uint32_t size; + + uint32_t freq_khz; +}; + #define LB_TAG_SERIALNO 0x002a #define MAX_SERIALNO_LENGTH 32 |