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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2022-07-14 15:37:07 -0600 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-07-20 14:14:30 +0000 |
| commit | e3eedf7548f282549d272d4e9b352dfb6e3b80da (patch) | |
| tree | d0eb32dd51d04b13b4fd5f3c0c5c7a1e2e8ad33b /src | |
| parent | df74de1cac679549b515ed5f4eb86e7229ab53cc (diff) | |
| download | coreboot-e3eedf7548f282549d272d4e9b352dfb6e3b80da.tar.gz coreboot-e3eedf7548f282549d272d4e9b352dfb6e3b80da.tar.bz2 coreboot-e3eedf7548f282549d272d4e9b352dfb6e3b80da.zip | |
soc/amd/common/psp_verstage: Fix update_boot_region
On SoCs where PSP use A/B recovery layout, PSP expects PSP L2 directory
address relative to the start of the SPI ROM. Unfortunately there is
nothing in the EFS2 header to help identify such SoCs. Hence add a
config item to statically identify such SoCs.
Also when PSP uses A/B recovery layout, BIOS L2 directory is an entry in
the PSP L2 directory. Hence the address of BIOS L2 directory is not part
of EFS2 header. Thankfully PSP is able to identify the BIOS L2 directory
itself and does not expect PSP verstage to pass the address. Modify PSP
verstage to handle these updates.
BUG=b:217414563
TEST=Build Skyrim BIOS image. Ensure that PSP verstage returned the PSP
L2 directory as expected.
Change-Id: I2f856a62055c80b8e2db91c983832611a5f0389c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/common/psp_verstage/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/amd/common/psp_verstage/psp_verstage.c | 16 |
2 files changed, 18 insertions, 6 deletions
diff --git a/src/soc/amd/common/psp_verstage/Kconfig b/src/soc/amd/common/psp_verstage/Kconfig index 45a5d2242305..13dd71659c03 100644 --- a/src/soc/amd/common/psp_verstage/Kconfig +++ b/src/soc/amd/common/psp_verstage/Kconfig @@ -21,3 +21,11 @@ config PSP_INIT_TPM_ON_S0I3_RESUME If the TPM is reset while in S0i3, it must be reinitialized during s0i3 resume. This must be performed in PSP verstage since coreboot is otherwise not involved with s0i3 resume. + +config PSP_SUPPORTS_EFS2_RELATIVE_ADDR + bool + default n + help + On SoCs where PSP uses A/B recovery layout, PSP support relative addressing + from the start of the SPI ROM. Enable this config on SoCs where PSP supports + relative addressing so that PSP verstage can pass the offset. diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 33733848efc0..b928a27e27db 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -104,19 +104,23 @@ static uint32_t update_boot_region(struct vb2_context *ctx) bios_dir_addr = get_bios_dir_addr(ef_table); psp_dir_in_spi = (uint32_t *)((psp_dir_addr & SPI_ADDR_MASK) + (uint32_t)boot_dev_base); - bios_dir_in_spi = (uint32_t *)((bios_dir_addr & SPI_ADDR_MASK) + - (uint32_t)boot_dev_base); if (*psp_dir_in_spi != PSP_COOKIE) { printk(BIOS_ERR, "PSP Directory address is not correct.\n"); return POSTCODE_PSP_COOKIE_MISMATCH_ERROR; } - if (*bios_dir_in_spi != BHD_COOKIE) { - printk(BIOS_ERR, "BIOS Directory address is not correct.\n"); - return POSTCODE_BHD_COOKIE_MISMATCH_ERROR; + + if (bios_dir_addr) { + bios_dir_in_spi = (uint32_t *)((bios_dir_addr & SPI_ADDR_MASK) + + (uint32_t)boot_dev_base); + if (*bios_dir_in_spi != BHD_COOKIE) { + printk(BIOS_ERR, "BIOS Directory address is not correct.\n"); + return POSTCODE_BHD_COOKIE_MISMATCH_ERROR; + } } /* EFS2 uses relative address and PSP isn't happy with that */ - if (ef_table->efs_gen.gen == EFS_SECOND_GEN) { + if (ef_table->efs_gen.gen == EFS_SECOND_GEN && + !CONFIG(PSP_SUPPORTS_EFS2_RELATIVE_ADDR)) { psp_dir_addr = FLASH_BASE_ADDR + (psp_dir_addr & SPI_ADDR_MASK); bios_dir_addr = FLASH_BASE_ADDR + (bios_dir_addr & SPI_ADDR_MASK); } |