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| author | Subrata Banik <subrata.banik@intel.com> | 2021-03-04 16:00:40 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-03-05 08:38:26 +0000 |
| commit | e4606bbff79ef1b0771417a1ee4e3bb0fb1909c2 (patch) | |
| tree | 3e42b89e70824e70ae589b0e51f5ee8cb30f14d5 /src | |
| parent | 99059d170aec06096cb3efe30a84830e5a7f9c22 (diff) | |
| download | coreboot-e4606bbff79ef1b0771417a1ee4e3bb0fb1909c2.tar.gz coreboot-e4606bbff79ef1b0771417a1ee4e3bb0fb1909c2.tar.bz2 coreboot-e4606bbff79ef1b0771417a1ee4e3bb0fb1909c2.zip | |
soc/intel/common/block/cpu: Use tab instead of space
Convert the lines starts with whitespace with tab as applicable.
Change-Id: Ife7b27360661cbfd2c90e2b643ed31225ded228c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51250
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 49b40a8d9aa5..4df7eac31992 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -398,9 +398,9 @@ find_llc_subleaf: * Then we need to allocate just one way for non-eviction * of RW data. */ - movl $0x01, %eax - cmp $CONFIG_DCACHE_RAM_SIZE, %ecx - jnc set_eviction_mask + movl $0x01, %eax + cmp $CONFIG_DCACHE_RAM_SIZE, %ecx + jnc set_eviction_mask /* * RW data size / way size is equal to number of |