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| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2021-08-10 20:28:49 +0530 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-08-13 18:03:15 +0000 |
| commit | eb32a85ade2cd85a9311b7888f0e848c7d8299f6 (patch) | |
| tree | 9cfcba737aed3f25e6603bc760e33c6815f667a7 /src | |
| parent | 5142ab41930d9a7c2463058338081aa02c2dea32 (diff) | |
| download | coreboot-eb32a85ade2cd85a9311b7888f0e848c7d8299f6.tar.gz coreboot-eb32a85ade2cd85a9311b7888f0e848c7d8299f6.tar.bz2 coreboot-eb32a85ade2cd85a9311b7888f0e848c7d8299f6.zip | |
mb/intel/adlrvp: Rename spd_info struct based on memory topology
Naming spd_info struct based on memory topology helps in reuse of
code.
lp4_lp5_spd_info -> memory_down_spd_info
ddr4_ddr5_spd_info -> dimm_module_spd_info
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b7a66b5524d8b80776ab7578ce7b13181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/adlrvp/romstage_fsp_params.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index cccd25859543..5241f960a636 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -30,12 +30,12 @@ void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg) int board_id = get_board_id(); const bool half_populated = false; - const struct mem_spd lp4_lp5_spd_info = { + const struct mem_spd memory_down_spd_info = { .topo = MEM_TOPO_MEMORY_DOWN, .cbfs_index = get_spd_index(), }; - const struct mem_spd ddr4_ddr5_spd_info = { + const struct mem_spd dimm_module_spd_info = { .topo = MEM_TOPO_DIMM_MODULE, .smbus = { [0] = { @@ -54,7 +54,7 @@ void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg) case ADL_P_DDR4_2: case ADL_P_DDR5_1: case ADL_P_DDR5_2: - memcfg_init(m_cfg, mem_config, &ddr4_ddr5_spd_info, half_populated); + memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated); break; case ADL_P_LP4_1: case ADL_P_LP4_2: @@ -62,7 +62,7 @@ void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg) case ADL_P_LP5_2: case ADL_M_LP4: case ADL_M_LP5: - memcfg_init(m_cfg, mem_config, &lp4_lp5_spd_info, half_populated); + memcfg_init(m_cfg, mem_config, &memory_down_spd_info, half_populated); break; default: die("Unknown board id = 0x%x\n", board_id); |