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| author | Angel Pons <th3fanbus@gmail.com> | 2021-09-28 11:33:38 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-29 21:36:19 +0000 |
| commit | ebd43ae8a3002153ca9dacb34215a1aabb60bb26 (patch) | |
| tree | ab461ab8cf0597300d6e593aafbdf6569d22138a /src | |
| parent | 72b8fd5a95513f7da30a6df07812dd00595451b0 (diff) | |
| download | coreboot-ebd43ae8a3002153ca9dacb34215a1aabb60bb26.tar.gz coreboot-ebd43ae8a3002153ca9dacb34215a1aabb60bb26.tar.bz2 coreboot-ebd43ae8a3002153ca9dacb34215a1aabb60bb26.zip | |
soc/intel/common/block/smbus: Drop reg-script usage
Using reg-script just to read-modify-write some registers makes no
sense. Replace reg-script usage with regular register operations.
Change-Id: I87d1278360a231cbe5b5f825ad9a448e59e63ea2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/smbus/smbus_early.c | 25 |
1 files changed, 11 insertions, 14 deletions
diff --git a/src/soc/intel/common/block/smbus/smbus_early.c b/src/soc/intel/common/block/smbus/smbus_early.c index cc59c2884895..a3173f326a54 100644 --- a/src/soc/intel/common/block/smbus/smbus_early.c +++ b/src/soc/intel/common/block/smbus/smbus_early.c @@ -1,30 +1,27 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <device/pci_def.h> +#include <device/pci_ops.h> #include <device/smbus_host.h> #include <intelblocks/smbus.h> -#include <reg_script.h> #include <soc/pci_devs.h> #include "smbuslib.h" -static const struct reg_script smbus_init_script[] = { +void smbus_common_init(void) +{ + const pci_devfn_t dev = PCH_DEV_SMBUS; + /* Set SMBus I/O base address */ - REG_PCI_WRITE32(PCI_BASE_ADDRESS_4, SMBUS_IO_BASE), + pci_write_config32(dev, PCI_BASE_ADDRESS_4, SMBUS_IO_BASE); /* Set SMBus enable */ - REG_PCI_WRITE8(HOSTC, HST_EN), + pci_write_config8(dev, HOSTC, HST_EN); /* Enable I/O access */ - REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); /* Disable interrupts */ - REG_IO_WRITE8(SMBUS_IO_BASE + SMBHSTCTL, 0), + outb(0, SMBUS_IO_BASE + SMBHSTCTL); /* Clear errors */ - REG_IO_WRITE8(SMBUS_IO_BASE + SMBHSTSTAT, 0xff), - /* Indicate the end of this array by REG_SCRIPT_END */ - REG_SCRIPT_END, -}; - -void smbus_common_init(void) -{ - reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); + outb(0xff, SMBUS_IO_BASE + SMBHSTSTAT); } uintptr_t smbus_base(void) |