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| author | Felix Singer <felixsinger@posteo.net> | 2020-11-21 00:16:06 +0000 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-24 22:43:23 +0000 |
| commit | ec8f5c79a5fd16531006dd950dc3fad71c97ca8b (patch) | |
| tree | 1f048743faf5ebe3bed28a21b8cd36991d1a0116 /src | |
| parent | 12e5fda49602812b85f9be76eaecdfe4954544bc (diff) | |
| download | coreboot-ec8f5c79a5fd16531006dd950dc3fad71c97ca8b.tar.gz coreboot-ec8f5c79a5fd16531006dd950dc3fad71c97ca8b.tar.bz2 coreboot-ec8f5c79a5fd16531006dd950dc3fad71c97ca8b.zip | |
mb/clevo/kbl-u: Configure GPIOs using mainboard_ops
Hook up the mainboard_ops driver and configure the GPIOs using .init,
since mainboard_silicon_init_params() is meant for the configuration of
the FSP, not the GPIOs.
Change-Id: I82f1eaf6693d9b117fb211776047058cdc787288
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/clevo/kbl-u/ramstage.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/mainboard/clevo/kbl-u/ramstage.c b/src/mainboard/clevo/kbl-u/ramstage.c index b5d67864a04f..9368021e7f8e 100644 --- a/src/mainboard/clevo/kbl-u/ramstage.c +++ b/src/mainboard/clevo/kbl-u/ramstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <device/device.h> #include <mainboard/gpio.h> -#include <soc/ramstage.h> /* * TODO: @@ -12,7 +12,11 @@ * - Make TBT port configurable (TBT <> DisplayPort) */ -void mainboard_silicon_init_params(FSP_SIL_UPD *params) +static void init_mainboard(void *chip_info) { mainboard_configure_gpios(); } + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; |