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| author | zhixingma <zhixing.ma@intel.com> | 2021-09-21 10:39:52 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-23 16:40:47 +0000 |
| commit | ef8654554f07f4c51130781dee3becbad1d2c618 (patch) | |
| tree | adb0f8152ad706c1ff88643942305e123b96825c /src | |
| parent | 7011fa1135009897a8fee5d96ade0f9fa9c960cc (diff) | |
| download | coreboot-ef8654554f07f4c51130781dee3becbad1d2c618.tar.gz coreboot-ef8654554f07f4c51130781dee3becbad1d2c618.tar.bz2 coreboot-ef8654554f07f4c51130781dee3becbad1d2c618.zip | |
mb/intel/adlrvp_m: Enable HECI1 communication
The patch enables HECI1 interface to allow OS applications to communicate
with CSE.
TEST=Verify PCI device 0:16.0 exposed in the lspci output
Signed-off-by: zhixingma <zhixing.ma@intel.com>
Change-Id: Ifd338345caa183f03097f1003080992da70296ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree_m.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 2c50c289e551..5d24a420c75d 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -27,6 +27,9 @@ chip soc/intel/alderlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" + # Enable HECI1 communication + register "HeciEnabled" = "1" + # FSP configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0 register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1 |