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| author | Angel Pons <th3fanbus@gmail.com> | 2021-09-27 12:02:50 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-09-29 20:40:32 +0000 |
| commit | efe57ebd40475d899e7585c02822cd0baebb8d30 (patch) | |
| tree | bcb05a0a95303f777a5a1f54570f117710eac31a /src | |
| parent | ae364008a7c13b3d4951acbf3554f16c9fb89d1b (diff) | |
| download | coreboot-efe57ebd40475d899e7585c02822cd0baebb8d30.tar.gz coreboot-efe57ebd40475d899e7585c02822cd0baebb8d30.tar.bz2 coreboot-efe57ebd40475d899e7585c02822cd0baebb8d30.zip | |
soc/intel: Rename GNVS struct member to match ASL
Rename the `ecps` GNVS struct member to `epcs` to match the name in ASL.
Change-Id: I1f6b97309eea75e7dbb4e5e664660df05ec0845e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/nvs.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/sgx/sgx.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/nvs.h | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index aa909a80a713..b4717486535f 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -28,7 +28,7 @@ struct __packed global_nvs { uint8_t scdo; /* 0x2A - GPIO pad offset relative to the community */ uint8_t uior; /* 0x2B - UART debug controller init on S3 resume */ - uint8_t ecps; /* 0x2C - SGX Enabled status */ + uint8_t epcs; /* 0x2C - SGX Enabled status */ uint64_t emna; /* 0x2D - 0x34 EPC base address */ uint64_t elng; /* 0x35 - 0x3C EPC Length */ uint64_t a4gb; /* 0x3D - 0x44 Base of above 4GB MMIO Resource */ diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index d6df99b0fa0e..b21e665ac80f 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -254,12 +254,12 @@ void sgx_fill_gnvs(struct global_nvs *gnvs) if (cpuid_regs.eax & SGX_RESOURCE_ENUM_BIT) { /* EPC section enumerated */ - gnvs->ecps = 1; + gnvs->epcs = 1; gnvs->emna = sgx_resource(cpuid_regs.eax, cpuid_regs.ebx); gnvs->elng = sgx_resource(cpuid_regs.ecx, cpuid_regs.edx); } printk(BIOS_DEBUG, "SGX: gnvs ECP status = %d base = 0x%llx len = 0x%llx\n", - gnvs->ecps, gnvs->emna, gnvs->elng); + gnvs->epcs, gnvs->emna, gnvs->elng); } diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index f4868d903ffc..6d5e17256c8e 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -41,7 +41,7 @@ struct __packed global_nvs { u16 u2we; /* 0x3f - USB2 Wake Enable Bitmap */ u8 u3we; /* 0x41 - USB3 Wake Enable Bitmap */ u8 uior; /* 0x42 - UART debug controller init on S3 resume */ - u8 ecps; /* 0x43 - SGX Enabled status */ + u8 epcs; /* 0x43 - SGX Enabled status */ u64 emna; /* 0x44 - 0x4B EPC base address */ u64 elng; /* 0x4C - 0x53 EPC Length */ u64 a4gb; /* 0x54 - 0x5B Base of above 4GB MMIO Resource */ |