diff options
| author | Marc Jones <marcj303@gmail.com> | 2017-10-19 13:43:55 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-20 21:32:23 +0000 |
| commit | f1c8ea35b338981b4cd02c38aed1dfabc3cdf251 (patch) | |
| tree | 28ca7d48d637012d55c847b81d60045047df73e9 /src | |
| parent | 2e8476c35dc5d319af67c16bc24e7b1776f5d63c (diff) | |
| download | coreboot-f1c8ea35b338981b4cd02c38aed1dfabc3cdf251.tar.gz coreboot-f1c8ea35b338981b4cd02c38aed1dfabc3cdf251.tar.bz2 coreboot-f1c8ea35b338981b4cd02c38aed1dfabc3cdf251.zip | |
soc/stoneyridge: Remove _PRW ASL
Remove _PRW GPE settings from GPP and USB ASL. The mainboard sets
the GPEs.
In addition, Stoney Ridge GPPs don't generate a GPE/SCIs.
Change-Id: Ib6a07a997bc3508109a67867014210091efc0c99
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/northbridge.asl | 5 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/usb.asl | 2 |
2 files changed, 0 insertions, 7 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index 9cc8ff0d82f6..4df6567e2cfa 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -49,7 +49,6 @@ Device(AMRT) { /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) - Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { If(PMOD){ Return(APS4) } /* APIC mode */ Return (PS4) /* PIC Mode */ @@ -59,7 +58,6 @@ Device(PBR4) { /* Gpp 1 */ Device(PBR5) { Name(_ADR, 0x00020002) - Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { If(PMOD){ Return(APS5) } /* APIC mode */ Return (PS5) /* PIC Mode */ @@ -69,7 +67,6 @@ Device(PBR5) { /* Gpp 2 */ Device(PBR6) { Name(_ADR, 0x00020003) - Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { If(PMOD){ Return(APS6) } /* APIC mode */ Return (PS6) /* PIC Mode */ @@ -79,7 +76,6 @@ Device(PBR6) { /* Gpp 3 */ Device(PBR7) { Name(_ADR, 0x00020004) - Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { If(PMOD){ Return(APS7) } /* APIC mode */ Return (PS7) /* PIC Mode */ @@ -89,7 +85,6 @@ Device(PBR7) { /* Gpp 4 */ Device(PBR8) { Name(_ADR, 0x00020005) - Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { If(PMOD){ Return(APS8) } /* APIC mode */ Return (PS8) /* PIC Mode */ diff --git a/src/soc/amd/stoneyridge/acpi/usb.asl b/src/soc/amd/stoneyridge/acpi/usb.asl index b93555a2edc9..3fd76b22dd32 100644 --- a/src/soc/amd/stoneyridge/acpi/usb.asl +++ b/src/soc/amd/stoneyridge/acpi/usb.asl @@ -17,12 +17,10 @@ /* 0:12.0 - EHCI */ Device(EHC0) { Name(_ADR, 0x00120000) - Name(_PRW, Package() {0x0b, 3}) } /* end EHC0 */ /* 0:10.0 - XHCI 0*/ Device(XHC0) { Name(_ADR, 0x00100000) - Name(_PRW, Package() {0x0b, 4}) } /* end XHC0 */ |