soc/mediatek/mt8188: Add PMIF and PMIC init support

Add PMIF, SPI, SPMI and PMIC init code.

These PMIC settings are used by MediaTek internally. We can find these
registers in "MT6365_PMIC_Data_Sheet_V1.4.pdf" and
"MT6315 datasheet v1.3.pdf". The setting values are provided by MeidaTek
designers.

TEST=build pass
BUG=b:233720142

Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com>
Change-Id: I05a51894b130a59c28d957b64d6401c8bb9cee91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

9 files changed, 780 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc
index b754c31ecb7a..78d13a5768af 100644
--- a/src/soc/mediatek/mt8188/Makefile.inc
+++ b/src/soc/mediatek/mt8188/Makefile.inc
@@ -15,6 +15,11 @@ bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
 romstage-y += ../common/cbmem.c
 romstage-y += emi.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+romstage-y += ../common/mt6315.c mt6315.c
+romstage-y += ../common/mt6359p.c mt6359p.c
+romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c
+romstage-y += ../common/pmif_spi.c pmif_spi.c
+romstage-y += ../common/pmif_spmi.c pmif_spmi.c
 
 ramstage-y += emi.c
 ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
diff --git a/src/soc/mediatek/mt8188/include/soc/addressmap.h b/src/soc/mediatek/mt8188/include/soc/addressmap.h
index d54a9c690b83..dce2bb5feeb1 100644
--- a/src/soc/mediatek/mt8188/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8188/include/soc/addressmap.h
@@ -74,6 +74,7 @@ enum {
 	MSDC1_TOP_BASE		= IO_PHYS + 0x01EB0000,
 	I2C5_BASE		= IO_PHYS + 0x01EC0000,
 	I2C6_BASE		= IO_PHYS + 0x01EC1000,
+	EFUSE_BASE		= IO_PHYS + 0x01F20000,
 	MSDC0_TOP_BASE		= IO_PHYS + 0x01F50000,
 };
 #endif
diff --git a/src/soc/mediatek/mt8188/include/soc/iocfg.h b/src/soc/mediatek/mt8188/include/soc/iocfg.h
new file mode 100644
index 000000000000..4c37c88921c8
--- /dev/null
+++ b/src/soc/mediatek/mt8188/include/soc/iocfg.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8188 Functional Specification
+ * Chapter number: 5.2
+ */
+
+#ifndef __SOC_MEDIATEK_MT8188_IOCFG_H__
+#define __SOC_MEDIATEK_MT8188_IOCFG_H__
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct mt8188_iocfg_lt_regs {
+	u32 reserved1[4];
+	u32 drv_cfg1;
+	u32 drv_cfg1_set;
+	u32 drv_cfg1_clr;
+	u32 reserved2;
+	u32 drv_cfg2;
+	u32 drv_cfg2_set;
+	u32 drv_cfg2_clr;
+	u32 reserved3;
+	u32 drv_cfg3;
+	u32 drv_cfg3_set;
+	u32 drv_cfg3_clr;
+	u32 reserved4[5];
+	u32 eh_cfg;
+	u32 eh_cfg_set;
+	u32 eh_cfg_clr;
+	u32 reserved5[9];
+	u32 ies_cfg1;
+	u32 ies_cfg1_set;
+	u32 ies_cfg1_clr;
+	u32 reserved6[9];
+	u32 pd_cfg1;
+	u32 pd_cfg1_set;
+	u32 pd_cfg1_clr;
+	u32 reserved7[9];
+	u32 pu_cfg1;
+	u32 pu_cfg1_set;
+	u32 pu_cfg1_clr;
+	u32 reserved8[21];
+	u32 rdsel_cfg3;
+	u32 rdsel_cfg3_set;
+	u32 rdsel_cfg3_clr;
+	u32 reserved9[5];
+	u32 smt_cfg0;
+	u32 smt_cfg0_set;
+	u32 smt_cfg0_clr;
+	u32 reserved10[17];
+	u32 tdsel_cfg3;
+	u32 tdsel_cfg3_set;
+	u32 tdsel_cfg3_clr;
+};
+check_member(mt8188_iocfg_lt_regs, drv_cfg1, 0x10);
+check_member(mt8188_iocfg_lt_regs, drv_cfg2, 0x20);
+check_member(mt8188_iocfg_lt_regs, drv_cfg3, 0x30);
+check_member(mt8188_iocfg_lt_regs, eh_cfg, 0x50);
+check_member(mt8188_iocfg_lt_regs, ies_cfg1, 0x80);
+check_member(mt8188_iocfg_lt_regs, pd_cfg1, 0xB0);
+check_member(mt8188_iocfg_lt_regs, pu_cfg1, 0xE0);
+check_member(mt8188_iocfg_lt_regs, rdsel_cfg3, 0x140);
+check_member(mt8188_iocfg_lt_regs, smt_cfg0, 0x160);
+check_member(mt8188_iocfg_lt_regs, tdsel_cfg3, 0x1B0);
+
+#define mtk_iocfg_lt    ((struct mt8188_iocfg_lt_regs *)IOCFG_LT_BASE)
+
+enum {
+	IO_4_MA = 0x1,
+	IO_6_MA = 0x2,
+};
+
+#endif /* __SOC_MEDIATEK_MT8188_IOCFG_H__ */
diff --git a/src/soc/mediatek/mt8188/include/soc/pmif.h b/src/soc/mediatek/mt8188/include/soc/pmif.h
new file mode 100644
index 000000000000..dd8ada7b33c5
--- /dev/null
+++ b/src/soc/mediatek/mt8188/include/soc/pmif.h
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MT8188_SOC_PMIF_H__
+#define __MT8188_SOC_PMIF_H__
+
+#include <device/mmio.h>
+#include <soc/pmif_common.h>
+#include <types.h>
+
+/* indicate which number SW channel start, by project */
+#define PMIF_SPMI_SW_CHAN	BIT(6)
+#define PMIF_SPMI_INF		0x5E7
+
+struct mtk_pmif_regs {
+	u32 init_done;
+	u32 reserved1[5];
+	u32 inf_busy_sta;
+	u32 other_busy_sta_0;
+	u32 other_busy_sta_1;
+	u32 inf_en;
+	u32 other_inf_en;
+	u32 inf_cmd_per_0;
+	u32 inf_cmd_per_1;
+	u32 inf_cmd_per_2;
+	u32 inf_cmd_per_3;
+	u32 inf_max_bytecnt_per_0;
+	u32 inf_max_bytecnt_per_1;
+	u32 inf_max_bytecnt_per_2;
+	u32 inf_max_bytecnt_per_3;
+	u32 staupd_ctrl;
+	u32 reserved2[48];
+	u32 int_gps_auxadc_cmd_addr;
+	u32 int_gps_auxadc_cmd;
+	u32 int_gps_auxadc_rdata_addr;
+	u32 reserved3[13];
+	u32 arb_en;
+	u32 reserved4[34];
+	u32 lat_cnter_ctrl;
+	u32 lat_cnter_en;
+	u32 lat_limit_loading;
+	u32 lat_limit_0;
+	u32 lat_limit_1;
+	u32 lat_limit_2;
+	u32 lat_limit_3;
+	u32 lat_limit_4;
+	u32 lat_limit_5;
+	u32 lat_limit_6;
+	u32 lat_limit_7;
+	u32 lat_limit_8;
+	u32 lat_limit_9;
+	u32 reserved5[99];
+	u32 crc_ctrl;
+	u32 crc_sta;
+	u32 sig_mode;
+	u32 pmic_sig_addr;
+	u32 pmic_sig_val;
+	u32 reserved6[2];
+	u32 cmdissue_en;
+	u32 reserved7[10];
+	u32 timer_ctrl;
+	u32 timer_sta;
+	u32 sleep_protection_ctrl;
+	u32 reserved8[6];
+	u32 spi_mode_ctrl;
+	u32 reserved9[2];
+	u32 pmic_eint_sta_addr;
+	u32 reserved10[2];
+	u32 irq_event_en_0;
+	u32 irq_flag_raw_0;
+	u32 irq_flag_0;
+	u32 irq_clr_0;
+	u32 reserved11[244];
+	u32 swinf_0_acc;
+	u32 swinf_0_wdata_31_0;
+	u32 swinf_0_wdata_63_32;
+	u32 reserved12[2];
+	u32 swinf_0_rdata_31_0;
+	u32 swinf_0_rdata_63_32;
+	u32 reserved13[2];
+	u32 swinf_0_vld_clr;
+	u32 swinf_0_sta;
+	u32 reserved14[5];
+	u32 swinf_1_acc;
+	u32 swinf_1_wdata_31_0;
+	u32 swinf_1_wdata_63_32;
+	u32 reserved15[2];
+	u32 swinf_1_rdata_31_0;
+	u32 swinf_1_rdata_63_32;
+	u32 reserved16[2];
+	u32 swinf_1_vld_clr;
+	u32 swinf_1_sta;
+	u32 reserved17[5];
+	u32 swinf_2_acc;
+	u32 swinf_2_wdata_31_0;
+	u32 swinf_2_wdata_63_32;
+	u32 reserved18[2];
+	u32 swinf_2_rdata_31_0;
+	u32 swinf_2_rdata_63_32;
+	u32 reserved19[2];
+	u32 swinf_2_vld_clr;
+	u32 swinf_2_sta;
+	u32 reserved20[5];
+	u32 swinf_3_acc;
+	u32 swinf_3_wdata_31_0;
+	u32 swinf_3_wdata_63_32;
+	u32 reserved21[2];
+	u32 swinf_3_rdata_31_0;
+	u32 swinf_3_rdata_63_32;
+	u32 reserved22[2];
+	u32 swinf_3_vld_clr;
+	u32 swinf_3_sta;
+	u32 reserved23[133];
+};
+
+check_member(mtk_pmif_regs, inf_busy_sta, 0x18);
+check_member(mtk_pmif_regs, int_gps_auxadc_cmd_addr, 0x110);
+check_member(mtk_pmif_regs, arb_en, 0x0150);
+check_member(mtk_pmif_regs, lat_cnter_en, 0x1E0);
+check_member(mtk_pmif_regs, crc_ctrl, 0x39C);
+check_member(mtk_pmif_regs, cmdissue_en, 0x3B8);
+check_member(mtk_pmif_regs, timer_ctrl, 0x3E4);
+check_member(mtk_pmif_regs, spi_mode_ctrl, 0x408);
+check_member(mtk_pmif_regs, pmic_eint_sta_addr, 0x414);
+check_member(mtk_pmif_regs, irq_event_en_0, 0x420);
+check_member(mtk_pmif_regs, swinf_0_acc, 0x800);
+
+#define PMIF_SPMI_AP_CHAN	(PMIF_SPMI_BASE + 0x880)
+#define PMIF_SPI_AP_CHAN	(PMIF_SPI_BASE + 0x880)
+
+struct mtk_clk_monitor_regs {
+	u32 clk_monitor_ctrl;
+};
+
+#define mtk_clk_monitor		((struct mtk_clk_monitor_regs *)EFUSE_BASE + 0x45C)
+
+enum {
+	FREQ_260MHZ = 260,
+};
+
+#define FREQ_METER_ABIST_AD_OSC_CK	42
+
+#endif /*__MT8188_SOC_PMIF_H__*/
diff --git a/src/soc/mediatek/mt8188/mt6315.c b/src/soc/mediatek/mt8188/mt6315.c
new file mode 100644
index 000000000000..470d9982053a
--- /dev/null
+++ b/src/soc/mediatek/mt8188/mt6315.c
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/mt6315.h>
+
+/*
+ * These values are used by MediaTek internally.
+ * We can find these registers in "MT6315 datasheet v1.3.pdf".
+ * The setting values are provided by MeidaTek designers.
+ */
+
+static const struct mt6315_setting init_setting_cpu[] = {
+	{0x13, 0x2, 0x2, 0},
+	{0x15, 0x1F, 0x1F, 0},
+	{0x22, 0x12, 0x12, 0},
+	{0x8A, 0x6, 0xF, 0},
+	{0x10B, 0x3, 0x3, 0},
+	{0x38B, 0x4, 0xFF, 0},
+	{0xA07, 0x0, 0x1, 0},
+	{0xA1A, 0x1F, 0x1F, 0},
+	{0x1457, 0x0, 0xFF, 0},
+	{0x997, 0xB, 0x7F, 0},
+	{0x999, 0xF0, 0xF0, 0},
+	{0x9A0, 0x1, 0x1F, 0},
+	{0x9A1, 0x1, 0x1F, 0},
+	{0x9A2, 0x0, 0x1F, 0},
+	{0x9A3, 0x2, 0x1F, 0},
+	{0xA0C, 0x0, 0x78, 0},
+	{0xA11, 0x1, 0x1F, 0},
+	{0xA1A, 0x1F, 0x1F, 0},
+	{0x1440, 0xD, 0xF, 0},
+	{0x1487, 0x58, 0xFF, 0},
+	{0x148B, 0x1, 0x7F, 0},
+	{0x148C, 0x1, 0x7F, 0},
+	{0x1507, 0x58, 0xFF, 0},
+	{0x150B, 0x1, 0x7F, 0},
+	{0x150C, 0x1, 0x7F, 0},
+	{0x1587, 0xB4, 0xFF, 0},
+	{0x158B, 0x1, 0x7F, 0},
+	{0x158C, 0x3, 0x7F, 0},
+	{0x1607, 0x60, 0xFF, 0},
+	{0x160B, 0x1, 0x7F, 0},
+	{0x160C, 0x3, 0x7F, 0},
+	{0x1687, 0x22, 0x76, 0},
+	{0x1688, 0xE, 0x2F, 0},
+	{0x1689, 0xA1, 0xE1, 0},
+	{0x168A, 0x79, 0x7F, 0},
+	{0x168B, 0x12, 0x3F, 0},
+	{0x168E, 0xD7, 0xFF, 0},
+	{0x168F, 0x81, 0xFF, 0},
+	{0x1690, 0x3, 0x3F, 0},
+	{0x1691, 0x22, 0x76, 0},
+	{0x1692, 0xE, 0x2F, 0},
+	{0x1693, 0xA1, 0xE1, 0},
+	{0x1694, 0x79, 0x7F, 0},
+	{0x1695, 0x12, 0x3F, 0},
+	{0x1698, 0xD7, 0xFF, 0},
+	{0x1699, 0x81, 0xFF, 0},
+	{0x169A, 0x3, 0x3F, 0},
+	{0x169B, 0x20, 0x70, 0},
+	{0x169C, 0xE, 0x2F, 0},
+	{0x169D, 0x81, 0xC1, 0},
+	{0x169E, 0xF8, 0xF8, 0},
+	{0x169F, 0x12, 0x3F, 0},
+	{0x16A2, 0xDB, 0xFF, 0},
+	{0x16A3, 0xA1, 0xFF, 0},
+	{0x16A4, 0x3, 0xF, 0},
+	{0x16A5, 0x20, 0x70, 0},
+	{0x16A6, 0xE, 0x2F, 0},
+	{0x16A7, 0x81, 0xC1, 0},
+	{0x16A8, 0xF8, 0xF8, 0},
+	{0x16A9, 0x12, 0x3F, 0},
+	{0x16AC, 0xDB, 0xFF, 0},
+	{0x16AD, 0xA1, 0xFF, 0},
+	{0x16AE, 0x3, 0xF, 0},
+	{0x16B8, 0x20, 0xE0, 0},
+	{0x16B9, 0x0, 0xF0, 0},
+};
+
+void mt6315_init_setting(void)
+{
+	for (int i = 0; i < ARRAY_SIZE(init_setting_cpu); i++)
+		mt6315_write_field(MT6315_CPU,
+			init_setting_cpu[i].addr, init_setting_cpu[i].val,
+			init_setting_cpu[i].mask, init_setting_cpu[i].shift);
+}
diff --git a/src/soc/mediatek/mt8188/mt6359p.c b/src/soc/mediatek/mt8188/mt6359p.c
new file mode 100644
index 000000000000..bdca56061456
--- /dev/null
+++ b/src/soc/mediatek/mt8188/mt6359p.c
@@ -0,0 +1,224 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/mt6359p.h>
+
+/*
+ * These values are used by MediaTek internally.
+ * We can find these registers in "MT6315 datasheet v1.3.pdf".
+ * The setting values are provided by MeidaTek designers.
+ */
+
+static const struct pmic_setting init_setting[] = {
+	{0x20, 0xA, 0xA, 0},
+	{0x24, 0x1F00, 0x1F00, 0},
+	{0x30, 0x1, 0x1, 0},
+	{0x32, 0x1, 0x1, 0},
+	{0x94, 0x0, 0xFFFF, 0},
+	{0x10C, 0x10, 0x10, 0},
+	{0x112, 0x4, 0x4, 0},
+	{0x118, 0x8, 0x8, 0},
+	{0x14A, 0x20, 0x20, 0},
+	{0x198, 0x0, 0x1FF, 0},
+	{0x1B2, 0x3, 0x3, 0},
+	{0x3B0, 0x0, 0x300, 0},
+	{0x790, 0x3, 0x3, 0},
+	{0x796, 0x1750, 0x3FFF, 0},
+	{0x798, 0x1750, 0x3FFF, 0},
+	{0x7A6, 0xF800, 0xFC00, 0},
+	{0x7A8, 0x80, 0x280, 0},
+	{0x98A, 0x80, 0x80, 0},
+	{0x992, 0xF00, 0xF00, 0},
+	{0xA08, 0x1, 0x1, 0},
+	{0xA0C, 0x300, 0x300, 0},
+	{0xA10, 0x0, 0x4000, 0},
+	{0xA12, 0x1E0, 0x1E0, 0},
+	{0xA24, 0xFFFF, 0xFFFF, 0},
+	{0xA26, 0xFFE0, 0xFFE0, 0},
+	{0xA2C, 0xC0DF, 0xC0DF, 0},
+	{0xA2E, 0xEBE0, 0xEBE0, 0},
+	{0xA34, 0x8000, 0x8000, 0},
+	{0xA3C, 0x1600, 0x1F00, 0},
+	{0xA3E, 0x3A61, 0x7FFF, 0},
+	{0xA40, 0x4042, 0x7FFF, 0},
+	{0xA42, 0xED0, 0x7FFF, 0},
+	{0xA44, 0x1CC4, 0x7FFF, 0},
+	{0xA46, 0x21AD, 0x7FFF, 0},
+	{0xA48, 0x4409, 0x7FFF, 0},
+	{0xA4A, 0x46AA, 0x7FFF, 0},
+	{0xA4C, 0x3E8E, 0x7FFF, 0},
+	{0xA4E, 0x5253, 0x7FFF, 0},
+	{0xA50, 0xA0, 0x7FFF, 0},
+	{0xA9C, 0x4000, 0x4000, 0},
+	{0xA9E, 0x2E11, 0xFF11, 0},
+	{0xF8C, 0x115, 0x115, 0},
+	{0x1188, 0x0, 0x8000, 0},
+	{0x1198, 0x13, 0x3FF, 0},
+	{0x119E, 0x6000, 0x7000, 0},
+	{0x11D4, 0x0, 0x2, 0},
+	{0x1212, 0x0, 0x2, 0},
+	{0x1224, 0x0, 0x2, 0},
+	{0x1238, 0x0, 0x2, 0},
+	{0x124A, 0x0, 0x2, 0},
+	{0x125C, 0x0, 0x2, 0},
+	{0x125E, 0x0, 0x8000, 0},
+	{0x1260, 0x1, 0xFFF, 0},
+	{0x1262, 0x4, 0x4, 0},
+	{0x1412, 0x8, 0x8, 0},
+	{0x148E, 0x38, 0x7F, 0},
+	{0x1492, 0xF1F, 0x7F7F, 0},
+	{0x150E, 0x18, 0x7F, 0},
+	{0x1512, 0xC1F, 0x7F7F, 0},
+	{0x158E, 0x18, 0x7F, 0},
+	{0x1592, 0xF00, 0x7F00, 0},
+	{0x160E, 0x18, 0x7F, 0},
+	{0x168E, 0x18, 0x7F, 0},
+	{0x1692, 0xF1F, 0x7F7F, 0},
+	{0x170E, 0x18, 0x7F, 0},
+	{0x1712, 0xF1F, 0x7F7F, 0},
+	{0x178E, 0x18, 0x7F, 0},
+	{0x1792, 0xF0F, 0x7F7F, 0},
+	{0x1918, 0x0, 0x3F3F, 0},
+	{0x191A, 0x0, 0x3F00, 0},
+	{0x198A, 0x5004, 0x502C, 0},
+	{0x198C, 0x3E, 0x3F, 0},
+	{0x198E, 0x1E0, 0x1E0, 0},
+	{0x1990, 0xFD, 0xFF, 0},
+	{0x1994, 0x10, 0x38, 0},
+	{0x1996, 0x2004, 0xA02C, 0},
+	{0x1998, 0x3E, 0x3F, 0},
+	{0x199A, 0xFB78, 0xFF78, 0},
+	{0x199E, 0x2, 0x7, 0},
+	{0x19A0, 0x1050, 0x10F1, 0},
+	{0x19A2, 0x3E, 0x3F, 0},
+	{0x19A4, 0xFD0F, 0xFF0F, 0},
+	{0x19A6, 0x20, 0xFF, 0},
+	{0x19AC, 0x4208, 0x4698, 0},
+	{0x19AE, 0x6E, 0x7E, 0},
+	{0x19B0, 0x3C00, 0x3C00, 0},
+	{0x19B4, 0x20FD, 0xFFFF, 0},
+	{0x1A08, 0x4208, 0x4698, 0},
+	{0x1A0A, 0x6E, 0x7E, 0},
+	{0x1A0C, 0x3C00, 0x3C00, 0},
+	{0x1A10, 0x20FD, 0xFFFF, 0},
+	{0x1A14, 0x4208, 0x4698, 0},
+	{0x1A16, 0x6E, 0x7E, 0},
+	{0x1A18, 0x3C00, 0x3C00, 0},
+	{0x1A1C, 0x20FD, 0xFFFF, 0},
+	{0x1A1E, 0x0, 0x200, 0},
+	{0x1A20, 0x4208, 0x4698, 0},
+	{0x1A22, 0x4A, 0x7E, 0},
+	{0x1A24, 0x3C00, 0x3C00, 0},
+	{0x1A28, 0x20FD, 0xFF00, 0},
+	{0x1A2C, 0x20, 0x74, 0},
+	{0x1A2E, 0x1E, 0x1E, 0},
+	{0x1A30, 0x42, 0xFF, 0},
+	{0x1A32, 0x480, 0x7E0, 0},
+	{0x1A34, 0x20, 0x74, 0},
+	{0x1A36, 0x1E, 0x1E, 0},
+	{0x1A38, 0x42, 0xFF, 0},
+	{0x1A3A, 0x480, 0x7E0, 0},
+	{0x1A3C, 0x14C, 0x3CC, 0},
+	{0x1A3E, 0x23C, 0x3FC, 0},
+	{0x1A40, 0xC400, 0xFF00, 0},
+	{0x1A42, 0x80, 0xFF, 0},
+	{0x1A44, 0x702C, 0xFF2C, 0},
+	{0x1B0E, 0xF, 0xF, 0},
+	{0x1B10, 0x1, 0x1, 0},
+	{0x1B14, 0xFFFF, 0xFFFF, 0},
+	{0x1B1A, 0x3FFF, 0x3FFF, 0},
+	{0x1B32, 0x8, 0x8, 0},
+	{0x1B8A, 0x30, 0x8030, 0},
+	{0x1B9C, 0x10, 0x8010, 0},
+	{0x1BA0, 0x4000, 0x4000, 0},
+	{0x1BAE, 0x1410, 0x9C10, 0},
+	{0x1BB2, 0x2, 0x2, 0},
+	{0x1BC0, 0x10, 0x8010, 0},
+	{0x1BD2, 0x13, 0x8013, 0},
+	{0x1BE4, 0x10, 0x8010, 0},
+	{0x1C0A, 0x10, 0x8010, 0},
+	{0x1C1E, 0x10, 0x8010, 0},
+	{0x1C30, 0x10, 0x8010, 0},
+	{0x1C42, 0x10, 0x8010, 0},
+	{0x1C54, 0x32, 0x8033, 0},
+	{0x1C66, 0x10, 0x8010, 0},
+	{0x1C8A, 0x10, 0x8010, 0},
+	{0x1C8E, 0x4000, 0x4000, 0},
+	{0x1C9C, 0x10, 0x8010, 0},
+	{0x1CAE, 0x10, 0x8010, 0},
+	{0x1CC0, 0x10, 0x8010, 0},
+	{0x1CD2, 0x33, 0x8033, 0},
+	{0x1CE4, 0x33, 0x8033, 0},
+	{0x1D0A, 0x10, 0x8010, 0},
+	{0x1D1E, 0x10, 0x8010, 0},
+	{0x1D22, 0x4000, 0x4000, 0},
+	{0x1D30, 0x10, 0x8010, 0},
+	{0x1D34, 0x4000, 0x4000, 0},
+	{0x1D42, 0x30, 0x8030, 0},
+	{0x1D46, 0x4000, 0x4000, 0},
+	{0x1D54, 0x30, 0x8030, 0},
+	{0x1D66, 0x32, 0x8033, 0},
+	{0x1D8A, 0x10, 0x8010, 0},
+	{0x1D9C, 0x10, 0x8010, 0},
+	{0x1E8A, 0x10, 0x8010, 0},
+	{0x1E8E, 0x10, 0x7F, 0},
+	{0x1E92, 0xF1F, 0x7F7F, 0},
+	{0x1EAA, 0x10, 0x8010, 0},
+	{0x1EAE, 0x10, 0x7F, 0},
+	{0x1EB2, 0xF1F, 0x7F7F, 0},
+	{0x1F0A, 0x10, 0x8010, 0},
+	{0x1F0E, 0x8, 0x7F, 0},
+	{0x1F12, 0xF1F, 0x7F7F, 0},
+	{0x1F30, 0x10, 0x8010, 0},
+	{0x1F34, 0x8, 0x7F, 0},
+	{0x1F38, 0xF1F, 0x7F7F, 0},
+	{0x200A, 0x8, 0xC, 0},
+	{0x202C, 0x8, 0xC, 0},
+	{0x208C, 0x100, 0xF00, 0},
+	{0x209C, 0x80, 0x1E0, 0},
+};
+
+static const struct pmic_setting lp_setting[] = {
+	/* Suspend */
+	{0x1594, 0x1, 0x1, 0x0},
+	{0x159a, 0x1, 0x1, 0x0},
+	{0x1d22, 0x1, 0x1, 0xe},
+	{0x1d28, 0x0, 0x1, 0xe},
+	{0x1c6a, 0x1, 0x1, 0x0},
+	{0x1c70, 0x1, 0x1, 0x0},
+	{0x1d34, 0x1, 0x1, 0xe},
+	{0x1d3a, 0x0, 0x1, 0xe},
+	{0x1d46, 0x1, 0x1, 0xe},
+	{0x1d4c, 0x0, 0x1, 0xe},
+	{0x1c8e, 0x1, 0x1, 0x0},
+	{0x1c94, 0x1, 0x1, 0x0},
+	{0x1ba0, 0x1, 0x1, 0x0},
+	{0x1ba6, 0x1, 0x1, 0x0},
+	{0x1d0e, 0x1, 0x1, 0x0},
+	{0x1d14, 0x1, 0x1, 0x0},
+
+	/* Deep idle */
+	{0x1594, 0x1, 0x1, 0x2},
+	{0x159a, 0x1, 0x1, 0x2},
+	{0x1c6a, 0x1, 0x1, 0x2},
+	{0x1c70, 0x1, 0x1, 0x2},
+	{0x1c8e, 0x1, 0x1, 0x2},
+	{0x1c94, 0x1, 0x1, 0x2},
+	{0x1ba0, 0x1, 0x1, 0x2},
+	{0x1ba6, 0x1, 0x1, 0x2},
+	{0x1d0e, 0x1, 0x1, 0x2},
+	{0x1d14, 0x1, 0x1, 0x2},
+};
+
+void pmic_init_setting(void)
+{
+	for (int i = 0; i < ARRAY_SIZE(init_setting); i++)
+		mt6359p_write_field(init_setting[i].addr, init_setting[i].val,
+			init_setting[i].mask, init_setting[i].shift);
+}
+
+void pmic_lp_setting(void)
+{
+	for (int i = 0; i < ARRAY_SIZE(lp_setting); i++)
+		mt6359p_write_field(lp_setting[i].addr, lp_setting[i].val,
+			lp_setting[i].mask, lp_setting[i].shift);
+}
diff --git a/src/soc/mediatek/mt8188/pmif_clk.c b/src/soc/mediatek/mt8188/pmif_clk.c
new file mode 100644
index 000000000000..4856852c29a2
--- /dev/null
+++ b/src/soc/mediatek/mt8188/pmif_clk.c
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <commonlib/helpers.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <soc/infracfg.h>
+#include <soc/pll.h>
+#include <soc/pll_common.h>
+#include <soc/pmif.h>
+#include <soc/pmif_clk_common.h>
+#include <soc/pmif_sw.h>
+#include <soc/pmif_spmi.h>
+#include <soc/spm.h>
+
+/* APMIXED, ULPOSC_CTRL_SEL */
+DEFINE_BITFIELD(OSC1_SEL, 3, 0)
+
+/* APMIXED, ULPOSC1_CON0 */
+DEFINE_BITFIELD(OSC1_CALI, 6, 0)
+DEFINE_BITFIELD(OSC1_IBAND, 13, 7)
+DEFINE_BITFIELD(OSC1_FBAND, 17, 14)
+DEFINE_BITFIELD(OSC1_DIV, 23, 18)
+DEFINE_BIT(OSC1_CP_EN, 24)
+
+/* APMIXED, ULPOSC1_CON1 */
+DEFINE_BITFIELD(OSC1_32KCALI, 7, 0)
+DEFINE_BITFIELD(OSC1_RSV1, 15, 8)
+DEFINE_BITFIELD(OSC1_RSV2, 23, 16)
+DEFINE_BITFIELD(OSC1_MOD, 25, 24)
+DEFINE_BIT(OSC1_DIV2_EN, 26)
+
+/* APMIXED, ULPOSC1_CON2 */
+DEFINE_BITFIELD(OSC1_BIAS, 7, 0)
+
+/* SPM, POWERON_CONFIG_EN */
+DEFINE_BIT(BCLK_CG_EN, 0)
+DEFINE_BITFIELD(PROJECT_CODE, 31, 16)
+
+/* SPM, ULPOSC_CON */
+DEFINE_BIT(ULPOSC_EN, 0)
+DEFINE_BIT(ULPOSC_CG_EN, 2)
+
+/* INFRA, MODULE_SW_CG */
+DEFINE_BIT(PMIC_CG_TMR, 0)
+DEFINE_BIT(PMIC_CG_AP, 1)
+DEFINE_BIT(PMIC_CG_MD, 2)
+DEFINE_BIT(PMIC_CG_CONN, 3)
+
+/* INFRA, INFRA_GLOBALCON_RST2 */
+DEFINE_BIT(PMIC_WRAP_SWRST, 0)
+DEFINE_BIT(PMICSPMI_SWRST, 14)
+
+/* INFRA, PMICW_CLOCK_CTRL */
+DEFINE_BITFIELD(PMIC_SYSCK_26M_SEL, 3, 0)
+
+/* TOPCKGEN, CLK_CFG_9 */
+DEFINE_BITFIELD(CLK_PWRAP_ULPOSC_SET, 2, 0)
+DEFINE_BIT(PDN_PWRAP_ULPOSC, 0)
+
+/* TOPCKGEN, CLK_CFG_UPDATE1 */
+DEFINE_BIT(CLK_CFG_UPDATE1, 4)
+
+/* EFUSE, CLK_MONITOR_CTRL */
+DEFINE_BIT(CLK_MONITOR_CTRL, 0)
+
+static void pmif_ulposc_config(void)
+{
+	/* ULPOSC_CTRL_SEL */
+	SET32_BITFIELDS(&mtk_apmixed->ulposc_ctrl_sel, OSC1_SEL, 0x0F);
+
+	/* ULPOSC1_CON0 */
+	SET32_BITFIELDS(&mtk_apmixed->ulposc1_con0, OSC1_CP_EN, 0, OSC1_DIV, 0x0F,
+			OSC1_FBAND, 0x2, OSC1_IBAND, 0x4A, OSC1_CALI, 0x7D);
+
+	/* ULPOSC1_CON1 */
+	SET32_BITFIELDS(&mtk_apmixed->ulposc1_con1, OSC1_DIV2_EN, 0, OSC1_MOD, 0,
+			OSC1_RSV2, 0, OSC1_RSV1, 0x29, OSC1_32KCALI, 0);
+
+	/* ULPOSC1_CON2 */
+	SET32_BITFIELDS(&mtk_apmixed->ulposc1_con2, OSC1_BIAS, 0x41);
+
+	udelay(15);
+}
+
+u32 pmif_get_ulposc_freq_mhz(u32 cali_val)
+{
+	u32 result = 0;
+
+	/* set calibration value */
+	SET32_BITFIELDS(&mtk_apmixed->ulposc1_con0, OSC1_CALI, cali_val);
+	udelay(50);
+	result = mt_fmeter_get_freq_khz(FMETER_ABIST, FREQ_METER_ABIST_AD_OSC_CK);
+
+	return result / 1000;
+}
+
+static void pmif_clockmonitor_config(bool enable)
+{
+	SET32_BITFIELDS(&mtk_clk_monitor->clk_monitor_ctrl,
+			CLK_MONITOR_CTRL, !enable);
+}
+
+static int pmif_init_ulposc(void)
+{
+	/* calibrate ULPOSC1 */
+	pmif_ulposc_config();
+
+	/* enable APB clock swinf */
+	if (!READ32_BITFIELD(&mtk_spm->poweron_config_en, BCLK_CG_EN))
+		SET32_BITFIELDS(&mtk_spm->poweron_config_en, BCLK_CG_EN, 1,
+				PROJECT_CODE, 0xb16);
+
+	/* turn on ulposc */
+	SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_EN, 1);
+	udelay(50);
+	SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_CG_EN, 1);
+	udelay(50);
+
+	return pmif_ulposc_cali(FREQ_260MHZ);
+}
+
+int pmif_clk_init(void)
+{
+	u32 ulposc1;
+
+	ulposc1 = mt_fmeter_get_freq_khz(FMETER_ABIST, FREQ_METER_ABIST_AD_OSC_CK);
+	if (pmif_ulposc_check(ulposc1, FREQ_260MHZ)) {
+		pmif_clockmonitor_config(false);
+		if (pmif_init_ulposc())
+			return E_NODEV;
+		pmif_clockmonitor_config(true);
+	}
+
+	/* turn off pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */
+	SET32_BITFIELDS(&mt8188_infracfg_ao->module_sw_cg_0_set, PMIC_CG_TMR, 1, PMIC_CG_AP, 1,
+			PMIC_CG_MD, 1, PMIC_CG_CONN, 1);
+
+	SET32_BITFIELDS(&mtk_topckgen->clk_cfg_9, PDN_PWRAP_ULPOSC, 0,
+			CLK_PWRAP_ULPOSC_SET, 0);
+	SET32_BITFIELDS(&mtk_topckgen->clk_cfg_update1, CLK_CFG_UPDATE1, 1);
+
+	/* use ULPOSC1 clock */
+	SET32_BITFIELDS(&mt8188_infracfg_ao->pmicw_clock_ctrl_clr, PMIC_SYSCK_26M_SEL, 0xf);
+
+	/* toggle SPI/SPMI sw reset */
+	SET32_BITFIELDS(&mt8188_infracfg_ao->infra_globalcon_rst2_set, PMICSPMI_SWRST, 1,
+			PMIC_WRAP_SWRST, 1);
+	SET32_BITFIELDS(&mt8188_infracfg_ao->infra_globalcon_rst2_clr, PMICSPMI_SWRST, 1,
+			PMIC_WRAP_SWRST, 1);
+
+	/* turn on pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */
+	SET32_BITFIELDS(&mt8188_infracfg_ao->module_sw_cg_0_clr, PMIC_CG_TMR, 1, PMIC_CG_AP, 1,
+			PMIC_CG_MD, 1, PMIC_CG_CONN, 1);
+
+	return 0;
+}
diff --git a/src/soc/mediatek/mt8188/pmif_spi.c b/src/soc/mediatek/mt8188/pmif_spi.c
new file mode 100644
index 000000000000..df86ccda393f
--- /dev/null
+++ b/src/soc/mediatek/mt8188/pmif_spi.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/iocfg.h>
+#include <soc/pmif_spi.h>
+
+/* IOCFG_BM, PWRAP_SPI_DRIVING */
+DEFINE_BITFIELD(PWRAP_SPI_DRIVING, 11, 9)
+
+void pmif_spi_iocfg(void)
+{
+	/* Set SoC SPI IO driving strength to 6 mA */
+	SET32_BITFIELDS(&mtk_iocfg_lt->drv_cfg2, PWRAP_SPI_DRIVING, IO_6_MA);
+}
diff --git a/src/soc/mediatek/mt8188/pmif_spmi.c b/src/soc/mediatek/mt8188/pmif_spmi.c
new file mode 100644
index 000000000000..e0a3030b5041
--- /dev/null
+++ b/src/soc/mediatek/mt8188/pmif_spmi.c
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/iocfg.h>
+#include <soc/pll.h>
+#include <soc/pmif_spmi.h>
+
+/* IOCFG_LT, DRV_CFG2 */
+DEFINE_BITFIELD(SPMI_SCL, 14, 12)
+DEFINE_BITFIELD(SPMI_SDA, 17, 15)
+DEFINE_BIT(SPMI_SCL_IN, 27)
+DEFINE_BIT(SPMI_SDA_IN, 28)
+DEFINE_BIT(SPMI_SCL_PU, 11)
+DEFINE_BIT(SPMI_SDA_PD, 12)
+DEFINE_BIT(SPMI_SCL_SMT, 28)
+DEFINE_BIT(SPMI_SDA_SMT, 28)
+DEFINE_BITFIELD(SPMI_TD, 19, 16)
+DEFINE_BITFIELD(SPMI_RD, 15, 14)
+DEFINE_BITFIELD(SPMI_DRI, 5, 3)
+
+/* TOPRGU, WDT_SWSYSRST2 */
+DEFINE_BIT(SPMI_MST_RST, 23)
+DEFINE_BITFIELD(UNLOCK_KEY, 31, 24)
+
+/* TOPCKGEN, CLK_CFG_17 */
+DEFINE_BITFIELD(CLK_SPMI_MST_SEL, 10, 8)
+DEFINE_BIT(CLK_SPMI_MST_INT, 12)
+DEFINE_BIT(PDN_SPMI_MST, 15)
+
+/* TOPCKGEN, CLK_CFG_UPDATE2 */
+DEFINE_BIT(SPMI_MST_CK_UPDATE, 5)
+
+const struct spmi_device spmi_dev[] = {
+	{
+		.slvid = SPMI_SLAVE_6,
+		.type = BUCK_CPU,
+		.type_id = BUCK_CPU_ID,
+	},
+};
+
+const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev);
+
+int spmi_config_master(void)
+{
+	/* Software reset */
+	SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 1, UNLOCK_KEY, 0x88);
+
+	SET32_BITFIELDS(&mtk_topckgen->clk_cfg_17,
+			CLK_SPMI_MST_SEL, 0x3,
+			CLK_SPMI_MST_INT, 0,
+			PDN_SPMI_MST, 0);
+	SET32_BITFIELDS(&mtk_topckgen->clk_cfg_update2, SPMI_MST_CK_UPDATE, 1);
+
+	/* Software reset */
+	SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 0, UNLOCK_KEY, 0x88);
+
+	/* Enable SPMI */
+	write32(&mtk_spmi_mst->mst_req_en, 1);
+	write32(&mtk_spmi_mst->rcs_ctrl, 0x15);
+
+	return 0;
+}
+
+void pmif_spmi_iocfg(void)
+{
+	SET32_BITFIELDS(&mtk_iocfg_lt->eh_cfg_clr, SPMI_SCL, 0x7, SPMI_SDA, 0x7);
+	SET32_BITFIELDS(&mtk_iocfg_lt->ies_cfg1_clr, SPMI_SCL_IN, 0x1);
+	SET32_BITFIELDS(&mtk_iocfg_lt->ies_cfg1_set, SPMI_SDA_IN, 0x1);
+	SET32_BITFIELDS(&mtk_iocfg_lt->pu_cfg1_clr, SPMI_SCL_PU, 0x1,
+			SPMI_SDA_PD, 0x1);
+	SET32_BITFIELDS(&mtk_iocfg_lt->pd_cfg1_clr, SPMI_SCL_PU, 0x1,
+			SPMI_SDA_PD, 0x1);
+	SET32_BITFIELDS(&mtk_iocfg_lt->smt_cfg0_set, SPMI_SCL_SMT, 0x1,
+			SPMI_SDA_SMT, 0x1);
+	SET32_BITFIELDS(&mtk_iocfg_lt->tdsel_cfg3_clr, SPMI_TD, 0xF);
+	SET32_BITFIELDS(&mtk_iocfg_lt->rdsel_cfg3_clr, SPMI_RD, 0x3);
+	SET32_BITFIELDS(&mtk_iocfg_lt->drv_cfg3_clr, SPMI_DRI, 0x07);
+	SET32_BITFIELDS(&mtk_iocfg_lt->drv_cfg3_set, SPMI_DRI, 0x02);
+}