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| author | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-10-08 15:23:59 -0600 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-10-10 21:50:20 +0000 |
| commit | f225d761ba1ae6dea878c33668b590fe94293fe5 (patch) | |
| tree | 8df060964af2c145c00d86eb5ff88b70591e7932 /src | |
| parent | 1a3de8e5bcc5c83934fa2a690e125b843e8b01ab (diff) | |
| download | coreboot-f225d761ba1ae6dea878c33668b590fe94293fe5.tar.gz coreboot-f225d761ba1ae6dea878c33668b590fe94293fe5.tar.bz2 coreboot-f225d761ba1ae6dea878c33668b590fe94293fe5.zip | |
soc/amd/common: Remove buildtime error for unknown cpu
This is not critical functionality and doesn't need a build-time error.
Having it as a build time error causes a chicken & egg issue where
the chipset needs to be added before it can be added to this file, but
the header file fails the build because the chipset is unknown.
It's not practical to exclude these files from the new platform builds
because the PSP functionality is thoroughly embedded into the coreboot
structure.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ib02bbe1f9ffb343e1ff7c2bfdc45e7edffe7aaed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/psp_efs.h | 3 | ||||
| -rw-r--r-- | src/soc/amd/common/block/psp/psp_efs.c | 7 |
2 files changed, 7 insertions, 3 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h index 1f93807538ae..51b06a68100b 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -19,11 +19,8 @@ #elif CONFIG(SOC_AMD_CEZANNE) | CONFIG(SOC_AMD_MENDOCINO) #define SPI_MODE_FIELD spi_readmode_f17_mod_30_3f #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_30_3f -#else - #error <Error: Unknown Processor> #endif - struct second_gen_efs { /* todo: expand for Server products */ uint32_t gen:1; /* Client products only use bit 0 */ uint32_t reserved:31; diff --git a/src/soc/amd/common/block/psp/psp_efs.c b/src/soc/amd/common/block/psp/psp_efs.c index feb0276463b6..eacd5f637c6a 100644 --- a/src/soc/amd/common/block/psp/psp_efs.c +++ b/src/soc/amd/common/block/psp/psp_efs.c @@ -2,6 +2,7 @@ #include <amdblocks/psp_efs.h> #include <arch/mmio.h> +#include <assert.h> #include <boot_device.h> #include <commonlib/region.h> #include <types.h> @@ -24,7 +25,13 @@ bool read_efs_spi_settings(uint8_t *mode, uint8_t *speed) if (!efs_is_valid()) return false; +#ifndef SPI_MODE_FIELD + printk(BIOS_ERR, "Unknown cpu in psp_efs.h\n"); + printk(BIOS_ERR, "SPI speed/mode not set.\n"); + return false; +#else *mode = efs->SPI_MODE_FIELD; *speed = efs->SPI_SPEED_FIELD; return true; +#endif } |