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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-25 06:22:10 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-27 20:42:30 +0000 |
| commit | f38f30a3de453c877eb593280419da612b220d17 (patch) | |
| tree | 71a630e0833bab5f7a3fe4930710677f27eeab7d /src | |
| parent | 5b92aa9c64c74194d1e405e0c8ec9f827f7c4fc6 (diff) | |
| download | coreboot-f38f30a3de453c877eb593280419da612b220d17.tar.gz coreboot-f38f30a3de453c877eb593280419da612b220d17.tar.bz2 coreboot-f38f30a3de453c877eb593280419da612b220d17.zip | |
Revert "sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros"
This reverts commit 9f0e21a4dae864809e9651403ab5bad48e784bee.
It should be allowed for i82801gx/early_init.c to have
#include <southbridge/intel/common/pmutil.h>
But there is a conflict:
src/southbridge/intel/common/pmutil.h:
#define TCO1_CNT 0x68
src/southbridge/intel/common/tco.h:
#define TCO1_CNT 0x08
Followup works resolve the difficulties around the offset
0x60 used for TCO register bank, tree-wide.
Change-Id: I827558a0e0ef1c4d1f866756df51cd1b2abfc7a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/i82801gx/early_init.c | 9 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/lpc.c | 5 |
3 files changed, 8 insertions, 7 deletions
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index dda5c00566a2..deb3debb81e7 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -6,7 +6,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/rcba.h> -#include <southbridge/intel/common/tco.h> #include "chip.h" #include "i82801gx.h" @@ -58,6 +57,8 @@ void i82801gx_setup_bars(void) pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN); } +#define TCO_BASE 0x60 + #if ENV_RAMINIT void i82801gx_early_init(void) { @@ -71,9 +72,9 @@ void i82801gx_early_init(void) printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, TCO_TMR_HLT); - write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); - write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS); + write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */ + write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */ + write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */ printk(BIOS_DEBUG, " done.\n"); /* program secondary mlt XXX byte? */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 0625db08d47b..ee34f742676e 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -323,6 +323,7 @@ void ich7_setup_cir(void); #define DEVACT_STS 0x44 #define SS_CNT 0x50 #define C3_RES 0x54 +#define TCO1_CNT 0x68 #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index f8a2dac89d9a..fd0a203efa06 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -20,7 +20,6 @@ #include <southbridge/intel/common/hpet.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/spi.h> -#include <southbridge/intel/common/tco.h> #include "chip.h" #include "i82801gx.h" @@ -428,9 +427,9 @@ static void lpc_final(struct device *dev) pci_or_config16(dev, GEN_PMCON_1, 1 << 4); /* TCO_Lock */ - tco1_cnt = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT); + tco1_cnt = inw(DEFAULT_PMBASE + 0x60 + TCO1_CNT); tco1_cnt |= (1 << 12); /* TCO lock */ - write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, tco1_cnt); + outw(tco1_cnt, DEFAULT_PMBASE + 0x60 + TCO1_CNT); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); |