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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-08-03 03:05:39 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-09 17:49:48 +0000 |
| commit | f4e64669244054a079d1d5e647ddc86ef4f08d71 (patch) | |
| tree | 8991191f4a17bf083bddde52cb81a75f8e80fd12 /src | |
| parent | 711023590278eb1cfdb050b5e68d14827c63527a (diff) | |
| download | coreboot-f4e64669244054a079d1d5e647ddc86ef4f08d71.tar.gz coreboot-f4e64669244054a079d1d5e647ddc86ef4f08d71.tar.bz2 coreboot-f4e64669244054a079d1d5e647ddc86ef4f08d71.zip | |
soc/amd/cezanne/include/gpio: add remote GPIO pin mux definitions
Add the pin definitions for the remote GPIOs and the GPIO pin mux values
for the GPIO mode of those pins. For now, accessing the remote GPIOs is
only supported from the native coreboot code running on the x86 cores
and not from verstage on PSP or ACPI.
BUG=b:194524995
TEST=On Majolica with a Cezanne APU configuring GPIO 262 as output and
then toggling that GPIO in an infinite loop in the mainboard's bootblock
code results in GPIO 262 toggling as expected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0e57042e74da88503b36d6065e9500876287f8bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/gpio.h | 38 |
1 files changed, 37 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/include/soc/gpio.h b/src/soc/amd/cezanne/include/soc/gpio.h index b2e9817bb8b6..d12d7b5a8750 100644 --- a/src/soc/amd/cezanne/include/soc/gpio.h +++ b/src/soc/amd/cezanne/include/soc/gpio.h @@ -15,7 +15,7 @@ /* The following sections describe only the GPIOs defined for this SOC */ -#define SOC_GPIO_TOTAL_PINS 149 +#define SOC_GPIO_TOTAL_PINS 272 /* Bank 0: GPIO_0 - GPIO_63 */ #define GPIO_0 0 @@ -94,6 +94,24 @@ #define GPIO_147 147 #define GPIO_148 148 +/* remote GPIO bank: GPIO_256 - GPIO_271 */ +#define GPIO_256 256 +#define GPIO_257 257 +#define GPIO_258 258 +#define GPIO_259 259 +#define GPIO_260 260 +#define GPIO_261 261 +#define GPIO_262 262 +#define GPIO_263 263 +#define GPIO_264 264 +#define GPIO_265 265 +#define GPIO_266 266 +#define GPIO_267 267 +#define GPIO_268 268 +#define GPIO_269 269 +#define GPIO_270 270 +#define GPIO_271 271 + /* IOMUX function names and values */ #define GPIO_0_IOMUX_PWR_BTN_L 0 #define GPIO_0_IOMUX_GPIOxx 1 @@ -282,4 +300,22 @@ #define GPIO_148_IOMUX_I2C1_SDA 0 #define GPIO_148_IOMUX_GPIOxx 1 +/* Remote GPIOs */ +#define GPIO_256_IOMUX_GPIOxx 1 +#define GPIO_257_IOMUX_GPIOxx 1 +#define GPIO_258_IOMUX_GPIOxx 1 +#define GPIO_259_IOMUX_GPIOxx 1 +#define GPIO_260_IOMUX_GPIOxx 1 +#define GPIO_261_IOMUX_GPIOxx 1 +#define GPIO_262_IOMUX_GPIOxx 1 +#define GPIO_263_IOMUX_GPIOxx 1 +#define GPIO_264_IOMUX_GPIOxx 1 +#define GPIO_265_IOMUX_GPIOxx 1 +#define GPIO_266_IOMUX_GPIOxx 1 +#define GPIO_267_IOMUX_GPIOxx 1 +#define GPIO_268_IOMUX_GPIOxx 1 +#define GPIO_269_IOMUX_GPIOxx 1 +#define GPIO_270_IOMUX_GPIOxx 1 +#define GPIO_271_IOMUX_GPIOxx 1 + #endif /* AMD_CEZANNE_GPIO_H */ |