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| author | Werner Zeh <werner.zeh@siemens.com> | 2022-10-21 11:53:19 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-25 15:05:35 +0000 |
| commit | f61070e87c80e75793f755a544f6f2f5465a9cc8 (patch) | |
| tree | a9c99c9e227eca75f03c3343e5059f0da7484858 /src | |
| parent | d03e896b57ea1ae2fea640937df2d57b684ce629 (diff) | |
| download | coreboot-f61070e87c80e75793f755a544f6f2f5465a9cc8.tar.gz coreboot-f61070e87c80e75793f755a544f6f2f5465a9cc8.tar.bz2 coreboot-f61070e87c80e75793f755a544f6f2f5465a9cc8.zip | |
mb/siemens/mc_ehl1: Disable L1 prefetcher
The highly real time driven application executed on mc_ehl1 has shown
that the L1 prefetcher on Elkhart Lake is too aggressive which in the
end leads to an increased number of cache misses. Disabling the L1
prefetcher boosts up the performance (in some cases by more than 10 %)
in this specific use case.
Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68668
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index bc3c4a0e0693..319a84372247 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -132,6 +132,9 @@ chip soc/intel/elkhartlake .vcc_low_high_us = 50, }" + # Disable L1 prefetcher + register "L1_prefetcher_disable" = "true" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device |