amdblocks/acpimmio: Unify BIOSRAM usage

All AMD CPU families supported in coreboot have BIOSRAM space. Looking at
the source code, every family could have the same API to save and restore
cbmem top or UMA base and size.

Unify BIOSRAM layout and add implementation for cbmem top and UMA storing.
Also replace the existing implementation of cbmem top and UMA with the
BIOSRAM access.

TEST=boot PC Engines apu1 and apu2

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37402
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

15 files changed, 72 insertions, 198 deletions

diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc
index ffafc6038f69..61917c9d48a4 100644
--- a/src/northbridge/amd/pi/Makefile.inc
+++ b/src/northbridge/amd/pi/Makefile.inc
@@ -19,7 +19,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01
 
-romstage-y += ramtop.c
-postcar-y += ramtop.c
-ramstage-y += ramtop.c
 endif
diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc
index 9517b10b8a5d..69253b92032a 100644
--- a/src/soc/amd/common/block/acpimmio/Makefile.inc
+++ b/src/soc/amd/common/block/acpimmio/Makefile.inc
@@ -4,3 +4,10 @@ romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c
 postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c
 ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c
 smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c
+
+bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c
+verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c
+romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c
+postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c
+ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c
+smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c
diff --git a/src/northbridge/amd/pi/ramtop.c b/src/soc/amd/common/block/acpimmio/biosram.c
index 823a15c0798b..f0a1257fb941 100644
--- a/src/northbridge/amd/pi/ramtop.c
+++ b/src/soc/amd/common/block/acpimmio/biosram.c
@@ -11,23 +11,40 @@
  * GNU General Public License for more details.
  */
 
-#define __SIMPLE_DEVICE__
-
-#include <stdint.h>
-#include <device/pci_ops.h>
 #include <cbmem.h>
-
-#define CBMEM_TOP_SCRATCHPAD 0x78
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/biosram.h>
 
 void backup_top_of_low_cacheable(uintptr_t ramtop)
 {
-	uint16_t top_cache = ramtop >> 16;
-	pci_write_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD, top_cache);
+	biosram_write32(BIOSRAM_CBMEM_TOP, ramtop);
 }
 
 uintptr_t restore_top_of_low_cacheable(void)
 {
-	uint16_t top_cache;
-	top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD);
-	return (top_cache << 16);
+	return biosram_read32(BIOSRAM_CBMEM_TOP);
+}
+
+void save_uma_size(uint32_t size)
+{
+	biosram_write32(BIOSRAM_UMA_SIZE, size);
+}
+
+void save_uma_base(uint64_t base)
+{
+	biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base);
+	biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32));
+}
+
+uint32_t get_uma_size(void)
+{
+	return biosram_read32(BIOSRAM_UMA_SIZE);
+}
+
+uint64_t get_uma_base(void)
+{
+	uint64_t base;
+	base = biosram_read32(BIOSRAM_UMA_BASE);
+	base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32);
+	return base;
 }
diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h
new file mode 100644
index 000000000000..e2c1eb33f7e2
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/biosram.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AMDBLOCKS_BIOSRAM_H__
+#define __AMDBLOCKS_BIOSRAM_H__
+
+#include <stdint.h>
+
+/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */
+#define BIOSRAM_CBMEM_TOP		0xf0 /* 4 bytes */
+#define BIOSRAM_UMA_SIZE		0xf4 /* 4 bytes */
+#define BIOSRAM_UMA_BASE		0xf8 /* 8 bytes */
+
+/* Saves the UMA size returned by AGESA */
+void save_uma_size(uint32_t size);
+/* Saves the UMA base address returned by AGESA */
+void save_uma_base(uint64_t base);
+/* Returns the saved UMA size */
+uint32_t get_uma_size(void);
+/* Returns the saved UMA base */
+uint64_t get_uma_base(void);
+
+#endif
diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c
index c5464df83487..45842168de6d 100644
--- a/src/soc/amd/common/block/pi/agesawrapper.c
+++ b/src/soc/amd/common/block/pi/agesawrapper.c
@@ -18,11 +18,11 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <timestamp.h>
+#include <amdblocks/biosram.h>
 #include <amdblocks/s3_resume.h>
 #include <amdblocks/agesawrapper.h>
 #include <amdblocks/BiosCallOuts.h>
 #include <soc/pci_devs.h>
-#include <soc/southbridge.h>
 #include <soc/northbridge.h>
 #include <soc/cpu.h>
 
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 0fb187dc523b..cbf95b9b1695 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -335,38 +335,6 @@ void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
 void fch_pre_init(void);
 void fch_early_init(void);
 void set_uart_config(int idx);
-/**
- * @brief Save the UMA bize
- *
- * @param size = in bytes
- *
- * @return none
- */
-void save_uma_size(uint32_t size);
-/**
- * @brief Save the UMA base address
- *
- * @param base = 64bit base address
- *
- * @return none
- */
-void save_uma_base(uint64_t base);
-/**
- * @brief Get the saved UMA size
- *
- * @param none
- *
- * @return size in bytes
- */
-uint32_t get_uma_size(void);
-/**
- * @brief Get the saved UMA base
- *
- * @param none
- *
- * @return 64bit base address
- */
-uint64_t get_uma_base(void);
 
 /* Initialize all the i2c buses that are marked with early init. */
 void i2c_soc_early_init(void);
diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c
index 82d6fb6e8e94..ae5a331259b8 100644
--- a/src/soc/amd/picasso/memmap.c
+++ b/src/soc/amd/picasso/memmap.c
@@ -28,16 +28,6 @@
 #include <soc/iomap.h>
 #include <amdblocks/acpimmio.h>
 
-void backup_top_of_low_cacheable(uintptr_t ramtop)
-{
-	biosram_write32(BIOSRAM_CBMEM_TOP, ramtop);
-}
-
-uintptr_t restore_top_of_low_cacheable(void)
-{
-	return biosram_read32(BIOSRAM_CBMEM_TOP);
-}
-
 #if CONFIG(ACPI_BERT)
  #if CONFIG_SMM_TSEG_SIZE == 0x0
   #define BERT_REGION_MAX_SIZE 0x100000
diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c
index 08807f332151..4a1493cba3f2 100644
--- a/src/soc/amd/picasso/northbridge.c
+++ b/src/soc/amd/picasso/northbridge.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <amdblocks/biosram.h>
 #include <device/pci_ops.h>
 #include <arch/ioapic.h>
 #include <arch/acpi.h>
@@ -29,7 +30,6 @@
 #include <romstage_handoff.h>
 #include <soc/cpu.h>
 #include <soc/northbridge.h>
-#include <soc/southbridge.h>
 #include <soc/pci_devs.h>
 #include <soc/iomap.h>
 #include <stdint.h>
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 041d262af73e..0dff4bcae327 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -501,27 +501,3 @@ static void set_pci_irqs(void *unused)
  * on entry into BS_DEV_ENABLE.
  */
 BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);
-
-void save_uma_size(uint32_t size)
-{
-	biosram_write32(BIOSRAM_UMA_SIZE, size);
-}
-
-void save_uma_base(uint64_t base)
-{
-	biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base);
-	biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32));
-}
-
-uint32_t get_uma_size(void)
-{
-	return biosram_read32(BIOSRAM_UMA_SIZE);
-}
-
-uint64_t get_uma_base(void)
-{
-	uint64_t base;
-	base = biosram_read32(BIOSRAM_UMA_BASE);
-	base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32);
-	return base;
-}
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index dd514ab88f28..0555afbba8dc 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -350,38 +350,7 @@ void sb_read_mode(u32 mode);
 void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
 void bootblock_fch_early_init(void);
 void bootblock_fch_init(void);
-/**
- * @brief Save the UMA bize returned by AGESA
- *
- * @param size = in bytes
- *
- * @return none
- */
-void save_uma_size(uint32_t size);
-/**
- * @brief Save the UMA base address returned by AGESA
- *
- * @param base = 64bit base address
- *
- * @return none
- */
-void save_uma_base(uint64_t base);
-/**
- * @brief Get the saved UMA size
- *
- * @param none
- *
- * @return size in bytes
- */
-uint32_t get_uma_size(void);
-/**
- * @brief Get the saved UMA base
- *
- * @param none
- *
- * @return 64bit base address
- */
-uint64_t get_uma_base(void);
+
 /*
  * Call the mainboard to get the USB Over Current Map. The mainboard
  * returns the map and 0 on Success or -1 on error or no map. There is
diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c
index 82d6fb6e8e94..ae5a331259b8 100644
--- a/src/soc/amd/stoneyridge/memmap.c
+++ b/src/soc/amd/stoneyridge/memmap.c
@@ -28,16 +28,6 @@
 #include <soc/iomap.h>
 #include <amdblocks/acpimmio.h>
 
-void backup_top_of_low_cacheable(uintptr_t ramtop)
-{
-	biosram_write32(BIOSRAM_CBMEM_TOP, ramtop);
-}
-
-uintptr_t restore_top_of_low_cacheable(void)
-{
-	return biosram_read32(BIOSRAM_CBMEM_TOP);
-}
-
 #if CONFIG(ACPI_BERT)
  #if CONFIG_SMM_TSEG_SIZE == 0x0
   #define BERT_REGION_MAX_SIZE 0x100000
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 044a1b05ca7f..c98d0a9517c9 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <amdblocks/biosram.h>
 #include <device/pci_ops.h>
 #include <arch/ioapic.h>
 #include <arch/acpi.h>
@@ -32,7 +33,6 @@
 #include <agesa_headers.h>
 #include <soc/cpu.h>
 #include <soc/northbridge.h>
-#include <soc/southbridge.h>
 #include <soc/pci_devs.h>
 #include <soc/iomap.h>
 #include <stdint.h>
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 85c7eafcf177..1b2afec3f1e1 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -648,27 +648,3 @@ static void set_pci_irqs(void *unused)
  * on entry into BS_DEV_ENABLE.
  */
 BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);
-
-void save_uma_size(uint32_t size)
-{
-	biosram_write32(BIOSRAM_UMA_SIZE, size);
-}
-
-void save_uma_base(uint64_t base)
-{
-	biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base);
-	biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32));
-}
-
-uint32_t get_uma_size(void)
-{
-	return biosram_read32(BIOSRAM_UMA_SIZE);
-}
-
-uint64_t get_uma_base(void)
-{
-	uint64_t base;
-	base = biosram_read32(BIOSRAM_UMA_BASE);
-	base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32);
-	return base;
-}
diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c
index 22b291d1bbad..2af95df03471 100644
--- a/src/southbridge/amd/agesa/hudson/ramtop.c
+++ b/src/southbridge/amd/agesa/hudson/ramtop.c
@@ -16,7 +16,6 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <arch/acpi.h>
-#include <cbmem.h>
 #include "hudson.h"
 
 int acpi_get_sleep_type(void)
@@ -25,27 +24,3 @@ int acpi_get_sleep_type(void)
 	tmp = ((tmp & (7 << 10)) >> 10);
 	return (int)tmp;
 }
-
-void backup_top_of_low_cacheable(uintptr_t ramtop)
-{
-	u32 dword = ramtop;
-	int nvram_pos = 0xf8, i; /* temp */
-	for (i = 0; i < 4; i++) {
-		outb(nvram_pos, BIOSRAM_INDEX);
-		outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
-		nvram_pos++;
-	}
-}
-
-uintptr_t restore_top_of_low_cacheable(void)
-{
-	uint32_t xdata = 0;
-	int xnvram_pos = 0xf8, xi;
-	for (xi = 0; xi < 4; xi++) {
-		outb(xnvram_pos, BIOSRAM_INDEX);
-		xdata &= ~(0xff << (xi * 8));
-		xdata |= inb(BIOSRAM_DATA) << (xi *8);
-		xnvram_pos++;
-	}
-	return xdata;
-}
diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c
index b9fc00df064f..98d12c71014d 100644
--- a/src/southbridge/amd/cimx/sb800/ramtop.c
+++ b/src/southbridge/amd/cimx/sb800/ramtop.c
@@ -25,27 +25,3 @@ int acpi_get_sleep_type(void)
 	tmp = ((tmp & (7 << 10)) >> 10);
 	return (int)tmp;
 }
-
-void backup_top_of_low_cacheable(uintptr_t ramtop)
-{
-	u32 dword = ramtop;
-	int nvram_pos = 0xf8, i;	/* temp */
-	for (i = 0; i < 4; i++) {
-		outb(nvram_pos, BIOSRAM_INDEX);
-		outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
-		nvram_pos++;
-	}
-}
-
-uintptr_t restore_top_of_low_cacheable(void)
-{
-	u32 xdata = 0;
-	int xnvram_pos = 0xf8, xi;
-	for (xi = 0; xi < 4; xi++) {
-		outb(xnvram_pos, BIOSRAM_INDEX);
-		xdata &= ~(0xff << (xi * 8));
-		xdata |= inb(BIOSRAM_DATA) << (xi * 8);
-		xnvram_pos++;
-	}
-	return xdata;
-}