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| author | Nico Huber <nico.huber@secunet.com> | 2021-09-07 16:03:44 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-08 18:49:50 +0000 |
| commit | fc726b9ea0d935103dce6d33c855994035c6d645 (patch) | |
| tree | eddf530f272259b284271da407445bc24c5fc15e /src | |
| parent | da3ef13d27809bc004e01a21c9d8bbc7445ba499 (diff) | |
| download | coreboot-fc726b9ea0d935103dce6d33c855994035c6d645.tar.gz coreboot-fc726b9ea0d935103dce6d33c855994035c6d645.tar.bz2 coreboot-fc726b9ea0d935103dce6d33c855994035c6d645.zip | |
mb/google/slippy: Fix overridden southbridge settings
To take any effect, a `chip` entry in a devicetree or overridetree
always needs a `device` node.
Change-Id: I158459e28dc8c63df4f1d58b30017868a57e5602
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57466
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
3 files changed, 23 insertions, 13 deletions
diff --git a/src/mainboard/google/slippy/variants/falco/overridetree.cb b/src/mainboard/google/slippy/variants/falco/overridetree.cb index fc77345dab44..b9f99a3a4d1c 100644 --- a/src/mainboard/google/slippy/variants/falco/overridetree.cb +++ b/src/mainboard/google/slippy/variants/falco/overridetree.cb @@ -13,8 +13,10 @@ chip northbridge/intel/haswell chip southbridge/intel/lynxpoint - # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013e0000" + device pci 16.0 on # Management Engine Interface 1 + # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013e0000" + end end end end diff --git a/src/mainboard/google/slippy/variants/peppy/overridetree.cb b/src/mainboard/google/slippy/variants/peppy/overridetree.cb index e732a9270cf5..bb30f763f3a5 100644 --- a/src/mainboard/google/slippy/variants/peppy/overridetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/overridetree.cb @@ -13,12 +13,16 @@ chip northbridge/intel/haswell chip southbridge/intel/lynxpoint - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" + device pci 1f.2 on # SATA Controller + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + end - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" + device pci 16.0 on # Management Engine Interface 1 + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + end end end end diff --git a/src/mainboard/google/slippy/variants/wolf/overridetree.cb b/src/mainboard/google/slippy/variants/wolf/overridetree.cb index 824694720dd5..b2a766684ea4 100644 --- a/src/mainboard/google/slippy/variants/wolf/overridetree.cb +++ b/src/mainboard/google/slippy/variants/wolf/overridetree.cb @@ -13,14 +13,18 @@ chip northbridge/intel/haswell chip southbridge/intel/lynxpoint - register "sata_devslp_disable" = "0x1" + device pci 1f.2 on # SATA Controller + register "sata_devslp_disable" = "0x1" - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + end - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" + device pci 16.0 on # Management Engine Interface 1 + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + end end end end |