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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2025-04-03 08:36:54 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2025-04-14 09:30:54 +0000 |
| commit | fdb0701336e35f45c00beef43df5d41777231f3a (patch) | |
| tree | e6780d81f117badc73ab034a5bde030bd79fe9cc /src | |
| parent | e6358d98c4691bd967d268033918c6d212b17994 (diff) | |
| download | coreboot-fdb0701336e35f45c00beef43df5d41777231f3a.tar.gz coreboot-fdb0701336e35f45c00beef43df5d41777231f3a.tar.bz2 coreboot-fdb0701336e35f45c00beef43df5d41777231f3a.zip | |
soc/amd/common/block/spi: Enforce default ROM mapping
Make sure that the ROM2 MMIO area starts at flash address 0.
Document 56780
Change-Id: I1fc06517ea496441147375579800f7349e39facc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/common/block/spi/mmap_boot.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/spi/mmap_boot.c b/src/soc/amd/common/block/spi/mmap_boot.c index d29af41636be..6a917195ce72 100644 --- a/src/soc/amd/common/block/spi/mmap_boot.c +++ b/src/soc/amd/common/block/spi/mmap_boot.c @@ -3,6 +3,7 @@ #include <boot_device.h> #include <endian.h> #include <spi_flash.h> +#include <amdblocks/spi.h> #if CONFIG_ROM_SIZE >= (16 * MiB) #define ROM_SIZE (16 * MiB) @@ -18,6 +19,13 @@ static const struct mem_region_device boot_dev = const struct region_device *boot_device_ro(void) { + /* + * The following code assumes that ROM2 is mapped at flash offset 0. This is the default + * configuration currently enforced by soft-straps. + */ + if (fch_spi_rom_remapping() != 0) + die("Non default SPI ROM remapping is not supported!"); + return &boot_dev.rdev; } |