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author | Zheng Bao <fishbaozi@gmail.com> | 2021-09-17 13:24:54 +0800 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-21 23:47:20 +0000 |
commit | 990d154898f97318ec812bed1e0fc1b9e84666f5 (patch) | |
tree | 10ee741178dd0e9c1dc50a20db9e8f6771024cf7 /util/amdfwtool/amdfwtool.h | |
parent | 1a9e54302b421b6d838be48a921529b45bc89413 (diff) | |
download | coreboot-990d154898f97318ec812bed1e0fc1b9e84666f5.tar.gz coreboot-990d154898f97318ec812bed1e0fc1b9e84666f5.tar.bz2 coreboot-990d154898f97318ec812bed1e0fc1b9e84666f5.zip |
amdfwtool: Add support for AMD's BIOS A/B recovery feature
The rom layout for A/B recovery:
EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A
0x4A -> PSP L2 B -> BIOS L2 B
The coreboot doesn't implement the AMD's A/B recovery. This is only
for the ROM layout. To save some flash space, the entire B section can
be eliminated.
To enable A/B recovery in PSP layout, add "--recovery-ab" to
amdfwtool.
TEST=Majolica(Cezanne)
Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'util/amdfwtool/amdfwtool.h')
-rw-r--r-- | util/amdfwtool/amdfwtool.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index 79e52fc93263..70afe3c6df68 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -43,6 +43,9 @@ typedef enum _amd_fw_type { AMD_FW_USB_PHY = 0x44, AMD_FW_TOS_SEC_POLICY = 0x45, AMD_FW_DRTM_TA = 0x47, + AMD_FW_RECOVERYAB_A = 0x48, + AMD_FW_RECOVERYAB_B = 0x4A, + AMD_FW_BIOS_TABLE = 0x49, AMD_FW_KEYDB_BL = 0x50, AMD_FW_KEYDB_TOS = 0x51, AMD_FW_PSP_VERSTAGE = 0x52, @@ -209,7 +212,10 @@ typedef struct _bios_directory_table { #define BDT_LVL1 (1 << 0) #define BDT_LVL2 (1 << 1) +#define BDT_LVL1_AB (1 << 2) +#define BDT_LVL2_AB (1 << 3) #define BDT_BOTH (BDT_LVL1 | BDT_LVL2) +#define BDT_BOTH_AB (BDT_LVL1_AB | BDT_LVL2_AB) typedef struct _amd_bios_entry { amd_bios_type type; char *filename; @@ -235,7 +241,10 @@ typedef struct _amd_bios_entry { #define PSP_LVL1 (1 << 0) #define PSP_LVL2 (1 << 1) +#define PSP_LVL1_AB (1 << 2) +#define PSP_LVL2_AB (1 << 3) #define PSP_BOTH (PSP_LVL1 | PSP_LVL2) +#define PSP_BOTH_AB (PSP_LVL1_AB | PSP_LVL2_AB) typedef struct _amd_fw_entry { amd_fw_type type; char *filename; @@ -252,6 +261,7 @@ typedef struct _amd_cb_config { bool multi_level; bool s0i3; bool have_mb_spl; + bool recovery_ab; } amd_cb_config; void register_fw_fuse(char *str); |