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authorVladimir Serbinenko <phcoder@gmail.com>2016-02-10 02:36:04 +0100
committerMartin Roth <martinroth@google.com>2016-02-12 17:09:05 +0100
commit144eea069726903d157f67a2f886dff4575d9b19 (patch)
tree995376822269c860e71fbae390a970fab3d587a7 /util/autoport/sandybridge.go
parentc37c7c8b1f3977e362e05945a48ddecf803e20a7 (diff)
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Make MRC vs native a config rather than making a separate chipset for it.
Tested by making lenovo x230 configurable despite pretty MRC bugs. Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13658 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'util/autoport/sandybridge.go')
-rw-r--r--util/autoport/sandybridge.go1
1 files changed, 1 insertions, 0 deletions
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go
index 66d44d942663..4ef6609b4580 100644
--- a/util/autoport/sandybridge.go
+++ b/util/autoport/sandybridge.go
@@ -114,6 +114,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true
KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE"] = true
+ KconfigBool["USE_NATIVE_RAMINIT"] = true
KconfigBool["INTEL_INT15"] = true
KconfigBool["HAVE_ACPI_TABLES"] = true
KconfigBool["HAVE_ACPI_RESUME"] = true