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| author | Angel Pons <th3fanbus@gmail.com> | 2020-01-08 15:05:56 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-01-08 14:25:23 +0000 |
| commit | 6779d2352cd33f98ad03e800c0de472fd3d3dfcc (patch) | |
| tree | 7e790f02058cb158af44be8827b8b63470f2010d /util/autoport/sandybridge.go | |
| parent | 38a4f2a9740c0a61b1c89525950bc8bd4febb22c (diff) | |
| download | coreboot-6779d2352cd33f98ad03e800c0de472fd3d3dfcc.tar.gz coreboot-6779d2352cd33f98ad03e800c0de472fd3d3dfcc.tar.bz2 coreboot-6779d2352cd33f98ad03e800c0de472fd3d3dfcc.zip | |
util/autoport: correct build errors of produced files
Change-Id: I8d1a6af6f1d70268f17692bee130c08502082c97
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'util/autoport/sandybridge.go')
| -rw-r--r-- | util/autoport/sandybridge.go | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 170d197af4d4..718fbe8f37ab 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -8,7 +8,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { /* FIXME:XX Move this somewhere else. */ MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h") - MainboardEnable += (` /* FIXME: fix those values*/ + MainboardEnable += (` /* FIXME: fix these values. */ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); @@ -37,7 +37,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { DevTree = DevTreeNode{ Chip: "northbridge/intel/sandybridge", MissingParent: "northbridge", - Comment: "FIXME: check gfx.ndid and gfx.did", + Comment: "FIXME: GPU registers may not always apply.", Registers: map[string]string{ "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7), "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7), @@ -52,9 +52,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001), "gfx.use_spread_spectrum_clock": FormatBool((inteltool.IGD[0xc6200]>>12)&1 != 0), "gfx.link_frequency_270_mhz": FormatBool(link_frequency > 200000), - /* FIXME:XX hardcoded. */ - "gfx.ndid": "3", - "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410 }", }, Children: []DevTreeNode{ { @@ -95,8 +92,8 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { ChildPCIBus: 0, PCISlots: []PCISlot{ PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PEG"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "iGPU"}, }, }, }, @@ -134,7 +131,7 @@ func init() { 0x0112, 0x0116, 0x0122, 0x0126, 0x0152, 0x0156, 0x0162, 0x0166, } { - RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}}) + RegisterPCI(0x8086, id, GenericVGA{GenericPCI{}}) } /* PCIe bridge */ |