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authorArthur Heymans <arthur@aheymans.xyz>2018-01-18 23:40:04 +0100
committerArthur Heymans <arthur@aheymans.xyz>2018-01-20 14:35:31 +0000
commit1e931f3e47a24855bd18146ccbaed31273510d6a (patch)
tree2262c2c17259f921aa4dca7bd2fc904f140097bd /util/autoport
parentc8c3aca81846210c101ce326d0bb3c6417da5ef9 (diff)
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autoport: Don't include default_irq_route.asl
This file is no longer there since ACPI pirq routing is now done in an automated fashion in SSDT. Change-Id: I8bafafbf670fe0fc2f20b46b5d8abee722931c6d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christoph Pomaska <cp_public@posteo.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'util/autoport')
-rw-r--r--util/autoport/bd82x6x.go2
1 files changed, 0 insertions, 2 deletions
diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go
index dc5d6897f462..d342a79d853e 100644
--- a/util/autoport/bd82x6x.go
+++ b/util/autoport/bd82x6x.go
@@ -297,8 +297,6 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
})
DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
File: "southbridge/intel/bd82x6x/acpi/pch.asl",
- }, DSDTInclude{
- File: "southbridge/intel/bd82x6x/acpi/default_irq_route.asl",
})
sb := Create(ctx, "early_southbridge.c")